From 32624bc6ee9c23bf1f6f0995fafc02fc2fa078c1 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Thu, 5 Sep 2024 12:50:09 -0700
Subject: [PATCH] Relocated a logic in a file to avoid a future merge conflict.

---
 src/uncore/spi_apb.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/uncore/spi_apb.sv b/src/uncore/spi_apb.sv
index a40079357..91021e2b6 100644
--- a/src/uncore/spi_apb.sv
+++ b/src/uncore/spi_apb.sv
@@ -99,6 +99,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
     /* verilator lint_off UNDRIVEN */
     logic [7:0] ReceiveShiftRegEndian;              // Reverses ReceiveShiftReg if Format[2] set (little endian transmission)
     rsrstatetype ReceiveState;
+    logic	  ReceiveFiFoTakingData;
 
     // Transmission signals
     logic ZeroDiv;                                  // High when SckDiv is 0
@@ -152,7 +153,6 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
     logic SCLKenableEarly;                          // SCLKenable 1 PCLK cycle early, needed for on time register changes when ChipSelectMode is hold and Delay1[15:8] (InterXFR delay) is 0
 
 
-    logic	  ReceiveFiFoTakingData;
 
     // APB access
     assign Entry = {PADDR[7:2],2'b00};  //  32-bit word-aligned accesses