diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test
index eeffdf802..3baa17a88 160000
--- a/addins/riscv-arch-test
+++ b/addins/riscv-arch-test
@@ -1 +1 @@
-Subproject commit eeffdf802c117f592b30e380b59caf48da384e76
+Subproject commit 3baa17a888cd6b5a8ca78ada757783ae0c061b3a
diff --git a/testbench/tests.vh b/testbench/tests.vh
index 83a7f6828..dc30acbe1 100644
--- a/testbench/tests.vh
+++ b/testbench/tests.vh
@@ -250,6 +250,9 @@ string arch32vm_sv32[] = '{
   "rv32i_m/vm_sv32/src/satp_access_tests.S",
   "rv32i_m/vm_sv32/src/vm_A_and_D_S_mode.S",
   "rv32i_m/vm_sv32/src/vm_A_and_D_U_mode.S",
+  "rv32i_m/vm_sv32/src/vm_U_Bit_set_U_mode.S",
+  "rv32i_m/vm_sv32/src/vm_U_Bit_unset_S_mode.S",
+  "rv32i_m/vm_sv32/src/vm_U_Bit_unset_U_mode.S",
   "rv32i_m/vm_sv32/src/vm_invalid_pte_S_mode.S",
   "rv32i_m/vm_sv32/src/vm_invalid_pte_U_mode.S",
   "rv32i_m/vm_sv32/src/vm_misaligned_S_mode.S",
@@ -267,10 +270,7 @@ string arch32vm_sv32[] = '{
   "rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_S_mode.S",
   "rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_U_mode.S",
   "rv32i_m/vm_sv32/src/vm_sum_set_S_mode.S",
-  "rv32i_m/vm_sv32/src/vm_sum_unset_S_mode.S",
-  "rv32i_m/vm_sv32/src/vm_U_Bit_set_U_mode.S",
-  "rv32i_m/vm_sv32/src/vm_U_Bit_unset_S_mode.S",
-  "rv32i_m/vm_sv32/src/vm_U_Bit_unset_U_mode.S"
+  "rv32i_m/vm_sv32/src/vm_sum_unset_S_mode.S"
 };
 
 string arch64priv[] = '{