diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index ddbf7372b..4b7c47d36 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -319,9 +319,6 @@ cd "$RISCV" if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2"; then cd "$RISCV"/riscv-gnu-toolchain git reset --hard && git clean -f && git checkout master && git pull && git submodule update - # sed commands needed to fix broken shallow cloning of submodules - sed -i '/shallow = true/d' .gitmodules - sed -i 's/--depth 1//g' Makefile.in ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" make -j "${NUM_THREADS}" 2>&1 | logger; [ "${PIPESTATUS[0]}" == 0 ] if [ "$clean" ]; then @@ -412,11 +409,17 @@ fi # Verilator needs to be built from source to get the latest version (Wally needs 5.021 or later). section_header "Installing/Updating Verilator" STATUS="verilator" +if [ "$UBUNTU_VERSION" == 20 ] || [ "$DEBIAN_VERSION" == 11 ]; then + # On Ubuntu 20 and Debian 11, the last version of Verilator that build successfully is 5.036. + export VERILATOR_VERSION="5.036" +else + export VERILATOR_VERSION="master" +fi cd "$RISCV" if git_check "verilator" "https://github.com/verilator/verilator" "$RISCV/share/pkgconfig/verilator.pc"; then unset VERILATOR_ROOT cd "$RISCV"/verilator - git reset --hard && git clean -f && git checkout master && git pull + git reset --hard && git clean -f && git checkout "$VERILATOR_VERSION" && (git pull || true) autoconf ./configure --prefix="$RISCV" make -j "${NUM_THREADS}" 2>&1 | logger; [ "${PIPESTATUS[0]}" == 0 ] diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index 1b73b1087..506cf3ab0 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -17,6 +17,10 @@ `define M_COVERAGE `define F_COVERAGE `define D_COVERAGE +`define VX8_COVERAGE +`define VX16_COVERAGE +`define VX32_COVERAGE +`define VX64_COVERAGE `define ZBA_COVERAGE `define ZBB_COVERAGE `define ZBC_COVERAGE @@ -58,6 +62,7 @@ `define EXCEPTIONSM_COVERAGE `define EXCEPTIONSS_COVERAGE `define EXCEPTIONSU_COVERAGE +`define EXCEPTIONSV_COVERAGE `define EXCEPTIONSF_COVERAGE `define EXCEPTIONSZC_COVERAGE `define EXCEPTIONSZAAMO_COVERAGE diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index 2ddf210c0..d9898d62a 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -17,6 +17,10 @@ `define M_COVERAGE `define F_COVERAGE `define D_COVERAGE +`define VX8_COVERAGE +`define VX16_COVERAGE +`define VX32_COVERAGE +`define VX64_COVERAGE `define ZBA_COVERAGE `define ZBB_COVERAGE `define ZBC_COVERAGE @@ -55,6 +59,7 @@ `define EXCEPTIONSM_COVERAGE `define EXCEPTIONSS_COVERAGE `define EXCEPTIONSU_COVERAGE +`define EXCEPTIONSV_COVERAGE `define EXCEPTIONSF_COVERAGE `define EXCEPTIONSZC_COVERAGE `define EXCEPTIONSVM_COVERAGE diff --git a/setup.sh b/setup.sh index d14f11b08..754c1dc4e 100644 --- a/setup.sh +++ b/setup.sh @@ -54,7 +54,7 @@ ulimit -c 300000 if [ -e "${RISCV}"/site-setup.sh ]; then source "${RISCV}"/site-setup.sh else - echo -e "${ERROR_COLOR}site-setup.sh not found in \$RISCV directory. Rerun wally-toolchain-install.sh to automatically download it.${ENDC}" + echo -e "${FAIL_COLOR}site-setup.sh not found in \$RISCV directory. Rerun wally-toolchain-install.sh to automatically download it.${ENDC}" return 1 fi diff --git a/tests/coverage/tlbmisc.S b/tests/coverage/tlbmisc.S index a15b1141b..f8f3944b3 100644 --- a/tests/coverage/tlbmisc.S +++ b/tests/coverage/tlbmisc.S @@ -64,10 +64,10 @@ main: li t0, 0x80200000 jalr ra, t0 # jump to misaligned megapage li t0, 0x7FFFFFFF80000000 - - jalr ra, t0 # jump to page with UpperBitsUnequal - li t0, 0x0000000080C00000 + li t0, 0x8000000080C00000 + jalr ra, t0 + li t0, 0x000000080C00000 jalr ra, t0 # jump to page with bad reserved bits 60:54 in PTE # test with ENVCFG_ADUE = 1: switch to machine mode, set ADUE, access page with A=0, clear ADUE, diff --git a/tests/riscof/Makefile b/tests/riscof/Makefile index f6c3023d2..9030c9c6a 100644 --- a/tests/riscof/Makefile +++ b/tests/riscof/Makefile @@ -18,7 +18,13 @@ current_dir := $(shell pwd) .PHONY: all riscv-arch-test wally-riscv-arch-test clean all: riscv-arch-test wally-riscv-arch-test riscv-arch-test: arch32e arch32 arch64 -cvw-riscv-arch-test: cvw-arch32 cvw-arch64 # cvw-arch32e + +cvw-riscv-arch-test: # cvw-arch32e + rm -rf $(cvw_arch_workdir) + rm -rf $(WALLY)/addins/cvw-arch-verif/work/* + $(MAKE) cvw-arch32 + $(MAKE) cvw-arch64 + wally-riscv-arch-test: wally32 wally64 # Generate config.ini files @@ -51,6 +57,7 @@ clean: rm -rf $(wally_workdir) rm -rf $(arch_workdir) rm -rf $(cvw_arch_workdir) + rm -rf $(WALLY)/addins/cvw-arch-verif/work/* $(work_dir) $(arch_workdir) $(wally_workdir) $(cvw_arch_workdir): mkdir -p $@ diff --git a/tests/riscof/sail_cSim/riscof_sail_cSim.py b/tests/riscof/sail_cSim/riscof_sail_cSim.py index 3b21fd04b..a9e4fcc64 100644 --- a/tests/riscof/sail_cSim/riscof_sail_cSim.py +++ b/tests/riscof/sail_cSim/riscof_sail_cSim.py @@ -63,6 +63,8 @@ class sail_cSim(pluginTemplate): self.isa += 'd' if "Q" in ispec["ISA"]: self.isa += 'q' + if "V" in ispec["ISA"]: + self.isa += 'v' objdump = "riscv64-unknown-elf-objdump" if shutil.which(objdump) is None: logger.error(objdump+": executable not found. Please check environment setup.") diff --git a/tests/riscof/sail_cSim/rv32gc.json b/tests/riscof/sail_cSim/rv32gc.json index f7782d0ef..668e4c915 100644 --- a/tests/riscof/sail_cSim/rv32gc.json +++ b/tests/riscof/sail_cSim/rv32gc.json @@ -56,7 +56,7 @@ "supported": true }, "V": { - "supported": false, + "supported": true, "vlen_exp": 9, "elen_exp": 6, "vl_use_ceil": false @@ -82,6 +82,9 @@ "Zicntr": { "supported": true }, + "Zicsr": { + "supported": true + }, "Zifencei": { "supported": true }, @@ -103,6 +106,15 @@ "Zalrsc": { "supported": false }, + "Zawrs": { + "supported": false, + "nto": { + "is_nop": false + }, + "sto": { + "is_nop": false + } + }, "Zfa": { "supported": true }, @@ -181,6 +193,9 @@ "Zvbc": { "supported": false }, + "Zvkned": { + "supported": false + }, "Zvknha": { "supported": false }, @@ -203,7 +218,8 @@ "supported": true }, "Svbare": { - "supported": true + "supported": true, + "sfence_vma_illegal_if_svbare_only": true }, "Sv32": { "supported": true diff --git a/tests/riscof/sail_cSim/rv64gc.json b/tests/riscof/sail_cSim/rv64gc.json index 4247ceeb8..7e70e1461 100644 --- a/tests/riscof/sail_cSim/rv64gc.json +++ b/tests/riscof/sail_cSim/rv64gc.json @@ -56,7 +56,7 @@ "supported": true }, "V": { - "supported": false, + "supported": true, "vlen_exp": 9, "elen_exp": 6, "vl_use_ceil": false @@ -82,6 +82,9 @@ "Zicntr": { "supported": true }, + "Zicsr": { + "supported": true + }, "Zifencei": { "supported": true }, @@ -103,6 +106,15 @@ "Zalrsc": { "supported": false }, + "Zawrs": { + "supported": false, + "nto": { + "is_nop": false + }, + "sto": { + "is_nop": false + } + }, "Zfa": { "supported": true }, @@ -181,6 +193,9 @@ "Zvbc": { "supported": false }, + "Zvkned": { + "supported": false + }, "Zvknha": { "supported": false }, @@ -203,7 +218,8 @@ "supported": true }, "Svbare": { - "supported": true + "supported": true, + "sfence_vma_illegal_if_svbare_only": true }, "Sv32": { "supported": false diff --git a/tests/riscof/spike/riscof_spike.py b/tests/riscof/spike/riscof_spike.py index fcb07f900..474ac63ff 100644 --- a/tests/riscof/spike/riscof_spike.py +++ b/tests/riscof/spike/riscof_spike.py @@ -103,6 +103,8 @@ class spike(pluginTemplate): self.isa += 'q' if "C" in ispec["ISA"]: self.isa += 'c' + if "V" in ispec["ISA"]: + self.isa += 'v' if "Zicsr" in ispec["ISA"]: self.isa += '_Zicsr' if "Zicond" in ispec["ISA"]: diff --git a/tests/riscof/spike/spike_rv32gc_isa.yaml b/tests/riscof/spike/spike_rv32gc_isa.yaml index f2d01c438..24db88078 100644 --- a/tests/riscof/spike/spike_rv32gc_isa.yaml +++ b/tests/riscof/spike/spike_rv32gc_isa.yaml @@ -1,11 +1,11 @@ hart_ids: [0] hart0: - ISA: RV32IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zcd_Zcf_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh + ISA: RV32IMAFDCVSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zcd_Zcf_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh physical_addr_sz: 32 User_Spec_Version: '2.3' supported_xlen: [32] misa: - reset-val: 0x4014112D + reset-val: 0x4034112D rv32: accessible: true mxl: @@ -23,7 +23,7 @@ hart0: warl: dependency_fields: [] legal: - - extensions[25:0] bitmask [0x014112D, 0x0000000] + - extensions[25:0] bitmask [0x034112D, 0x0000000] wr_illegal: - Unchanged PMP: @@ -31,3 +31,4 @@ hart0: pmp-grain: 4 pmp-count: 16 pmp-writable: 12 + diff --git a/tests/riscof/spike/spike_rv64gc_isa.yaml b/tests/riscof/spike/spike_rv64gc_isa.yaml index 7ac691876..78b7f4413 100644 --- a/tests/riscof/spike/spike_rv64gc_isa.yaml +++ b/tests/riscof/spike/spike_rv64gc_isa.yaml @@ -1,11 +1,11 @@ hart_ids: [0] hart0: - ISA: RV64IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zcd_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh + ISA: RV64IMAFDCVSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zcd_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh physical_addr_sz: 56 User_Spec_Version: '2.3' supported_xlen: [64] misa: - reset-val: 0x800000000014112D + reset-val: 0x800000000034112D rv32: accessible: false rv64: @@ -25,7 +25,7 @@ hart0: warl: dependency_fields: [] legal: - - extensions[25:0] bitmask [0x015112D, 0x0000000] + - extensions[25:0] bitmask [0x035112D, 0x0000000] wr_illegal: - Unchanged PMP: