diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile
index d397c5edb..c65e522f2 100644
--- a/fpga/generator/Makefile
+++ b/fpga/generator/Makefile
@@ -1,7 +1,11 @@
 dst := IP
 
+all: FPGA
 
-all: $(dst)/xlnx_proc_sys_reset.log \
+FPGA: IP
+	vivado -mode batch -source wally.tcl | tee wally.log
+
+IP: $(dst)/xlnx_proc_sys_reset.log \
 	$(dst)/xlnx_ddr4.log \
 	$(dst)/xlnx_axi_clock_converter.log \
 	 $(dst)/xlnx_ahblite_axi_bridge.log
@@ -11,5 +15,13 @@ $(dst)/%.log: %.tcl
 	cd IP;\
 	vivado -mode batch -source ../$*.tcl | tee $*.log
 
-clean:
-	rm -rf IP vivado.jou vivado.log
+cleanIP:
+	rm -rf IP
+
+cleanLogs:
+	rm -rf  *.jou *.log
+
+cleanFPGA:
+	rm -rf WallyFPGA.* reports sim .Xil
+
+cleanAll: cleanIP cleanLogs cleanFPGA
diff --git a/fpga/generator/xlnx_axi_clock_converter.tcl b/fpga/generator/xlnx_axi_clock_converter.tcl
index c63d8761f..9e581c29d 100644
--- a/fpga/generator/xlnx_axi_clock_converter.tcl
+++ b/fpga/generator/xlnx_axi_clock_converter.tcl
@@ -11,7 +11,13 @@ set_property board_part $boardName [current_project]
 
 create_ip -name axi_clock_converter -vendor xilinx.com -library ip -module_name $ipName
 
-set_property -dict [list CONFIG.ACLK_ASYNC {1} CONFIG.PROTOCOL {AXI4} CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {64} CONFIG.ID_WIDTH {4}] [get_ips $ipName]
+set_property -dict [list CONFIG.ACLK_ASYNC {1} \
+			CONFIG.PROTOCOL {AXI4} \
+			CONFIG.ADDR_WIDTH {32} \
+			CONFIG.DATA_WIDTH {64} \
+			CONFIG.ID_WIDTH {4} \
+		        CONFIG.MI_CLK.FREQ_HZ {208333333} \
+			CONFIG.SI_CLK.FREQ_HZ {10000000}] [get_ips $ipName]
 
 generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
 generate_target all [get_files  ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]