diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-MIE-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-MIE-01.S index 265169429..88555e3de 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-MIE-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-MIE-01.S @@ -33,10 +33,19 @@ li x28, 0x8 csrs mstatus, x28 // set mstatus.MIE bit to 1. WRITE_READ_CSR mie, 0x0 // force zeroing out mie CSR. -// test 5.3.1.6 Interrupt enabling and priority tests +// test 5.3.1.6 Interrupt enabling and priority tests +// testing with MIE bits set already tested in WALLY-trap // note that none of these interrupts should be caught or handled. +jal cause_s_soft_interrupt jal cause_m_soft_interrupt +jal cause_s_time_interrupt +jal cause_m_time_interrupt +li a3, 0x40 // these interrupts involve a time loop waiting for the interrupt to go off. +// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3 +jal cause_s_ext_interrupt_GPIO +li a3, 0x40 +jal cause_m_ext_interrupt END_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MIE-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MIE-01.S index bc6915070..ce265a35c 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MIE-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MIE-01.S @@ -34,9 +34,18 @@ csrs mstatus, x28 // set mstatus.MIE bit to 1. WRITE_READ_CSR mie, 0x0 // force zeroing out mie CSR. // test 5.3.1.6 Interrupt enabling and priority tests +// testing with MIE bits set already tested in WALLY-trap // note that none of these interrupts should be caught or handled. +jal cause_s_soft_interrupt jal cause_m_soft_interrupt +jal cause_s_time_interrupt +jal cause_m_time_interrupt +li a3, 0x40 // these interrupts involve a time loop waiting for the interrupt to go off. +// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3 +jal cause_s_ext_interrupt_GPIO +li a3, 0x40 +jal cause_m_ext_interrupt END_TESTS