From 784a6795cf29379228743f9bdfdfec7cc1aaa98f Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 25 Jan 2025 16:16:37 -0800 Subject: [PATCH 1/3] Remove empty checksignature.sv file --- testbench/common/checksignature.sv | 26 -------------------------- 1 file changed, 26 deletions(-) delete mode 100644 testbench/common/checksignature.sv diff --git a/testbench/common/checksignature.sv b/testbench/common/checksignature.sv deleted file mode 100644 index 7fb589bb6..000000000 --- a/testbench/common/checksignature.sv +++ /dev/null @@ -1,26 +0,0 @@ -/////////////////////////////////////////// -// checksignature.sv -// -// Written: David Harris David_Harris@hmc.edu -// Modified: 14 June 2023 -// -// Purpose: Verifies the memory signature. -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - From a338089b6f89298413590eac9e93746e8c90bfd5 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 25 Jan 2025 16:22:27 -0800 Subject: [PATCH 2/3] Fix FunctionName module naming --- sim/questa/fpga-wave.do | 2 +- testbench/common/functionName.sv | 2 +- testbench/common/loggers.sv | 16 ++++++++-------- testbench/testbench.sv | 12 ++++++------ 4 files changed, 16 insertions(+), 16 deletions(-) diff --git a/sim/questa/fpga-wave.do b/sim/questa/fpga-wave.do index e95443fbe..ebff54cd3 100644 --- a/sim/questa/fpga-wave.do +++ b/sim/questa/fpga-wave.do @@ -53,7 +53,7 @@ add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE add wave -noupdate -group {Execution Stage} /testbench/InstrEName add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE -add wave -noupdate -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName +add wave -noupdate -group {Execution Stage} /testbench/functionName/functionName/FunctionName add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName diff --git a/testbench/common/functionName.sv b/testbench/common/functionName.sv index 2d257ce32..141dcd88f 100644 --- a/testbench/common/functionName.sv +++ b/testbench/common/functionName.sv @@ -23,7 +23,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module FunctionName import cvw::*; #(parameter cvw_t P) ( +module functionName import cvw::*; #(parameter cvw_t P) ( input logic reset, input logic clk, input string ProgramAddrMapFile, diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv index 1a88bc052..5ed07b6d6 100644 --- a/testbench/common/loggers.sv +++ b/testbench/common/loggers.sv @@ -84,11 +84,11 @@ module loggers import cvw::*; #(parameter cvw_t P, always_comb if (TEST == "embench") begin - StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger"; - EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_trigger"; + StartSampleFirst = functionName.functionName.FunctionName == "start_trigger"; + EndSampleFirst = functionName.functionName.FunctionName == "stop_trigger"; end else if (TEST == "coremark") begin - StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_time"; - EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time"; + StartSampleFirst = functionName.functionName.FunctionName == "start_time"; + EndSampleFirst = functionName.functionName.FunctionName == "stop_time"; end else begin StartSampleFirst = reset; EndSampleFirst = '0; @@ -106,22 +106,22 @@ module loggers import cvw::*; #(parameter cvw_t P, if(TEST == "embench") begin // embench runs warmup then runs start_trigger // embench end with stop_trigger. - //assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger"; + //assign StartSampleFirst = functionName.functionName.FunctionName == "start_trigger"; //flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed); //assign StartSample = StartSampleFirst & ~ StartSampleDelayed; - //assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_trigger"; + //assign EndSampleFirst = functionName.functionName.FunctionName == "stop_trigger"; flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed); assign EndSample = EndSampleFirst & ~ EndSampleDelayed; end else if(TEST == "coremark") begin // embench runs warmup then runs start_trigger // embench end with stop_trigger. - //assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_time"; + //assign StartSampleFirst = functionName.functionName.FunctionName == "start_time"; //flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed); //assign StartSample = StartSampleFirst & ~ StartSampleDelayed; - //assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time"; + //assign EndSampleFirst = functionName.functionName.FunctionName == "stop_time"; flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed); assign EndSample = EndSampleFirst & ~ EndSampleDelayed; diff --git a/testbench/testbench.sv b/testbench/testbench.sv index eb1c88955..194e70d6c 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -38,7 +38,7 @@ import cvw::*; module testbench; /* verilator lint_off WIDTHTRUNC */ /* verilator lint_off WIDTHEXPAND */ - parameter DEBUG=0; + parameter DEBUG=1; parameter PrintHPMCounters=0; parameter BPRED_LOGGER=0; parameter I_CACHE_ADDR_LOGGER=0; @@ -684,8 +684,8 @@ module testbench; loggers (clk, reset, DCacheFlushStart, DCacheFlushDone, memfilename, TEST); // track the current function or global label - if (DEBUG > 0 | ((PrintHPMCounters | BPRED_LOGGER) & P.ZICNTR_SUPPORTED)) begin : FunctionName - FunctionName #(P) FunctionName(.reset(reset_ext | TestBenchReset), + if (DEBUG > 0 | ((PrintHPMCounters | BPRED_LOGGER) & P.ZICNTR_SUPPORTED)) begin : functionName + functionName #(P) functionName(.reset(reset_ext | TestBenchReset), .clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile)); end @@ -710,11 +710,11 @@ module testbench; always @(posedge clk) begin // if (reset) PrevPCZero <= 0; - // else if (dut.core.InstrValidM) PrevPCZero <= (FunctionName.PCM == 0 & dut.core.ifu.InstrM == 0); + // else if (dut.core.InstrValidM) PrevPCZero <= (functionName.PCM == 0 & dut.core.ifu.InstrM == 0); TestComplete <= ((InstrM == 32'h6f) & dut.core.InstrValidM ) | ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"] & dut.core.lsu.IEUAdrM != 0) & InstrMName == "SW"); // | - // (FunctionName.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero)); - // if (FunctionName.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero) + // (functionName.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero)); + // if (functionName.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero) // $error("Program fetched illegal instruction 0x00000000 from address 0x00000000 twice in a row. Usually due to fault with no fault handler."); end From 9fc2e23eee54a09eae78711fef85139b4b428815 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 25 Jan 2025 17:35:37 -0800 Subject: [PATCH 3/3] Turn off debug mode --- testbench/testbench.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 194e70d6c..696a288f1 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -38,7 +38,7 @@ import cvw::*; module testbench; /* verilator lint_off WIDTHTRUNC */ /* verilator lint_off WIDTHEXPAND */ - parameter DEBUG=1; + parameter DEBUG=0; parameter PrintHPMCounters=0; parameter BPRED_LOGGER=0; parameter I_CACHE_ADDR_LOGGER=0;