From 301377262e4e628d1b42e15261b30d3562a978fc Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 20 Jun 2024 20:47:18 -0700 Subject: [PATCH 001/219] initial version of red hat install toolchain --- bin/wally-tool-chain-install-redhat.sh | 257 +++++++++++++++++++++++++ 1 file changed, 257 insertions(+) create mode 100644 bin/wally-tool-chain-install-redhat.sh diff --git a/bin/wally-tool-chain-install-redhat.sh b/bin/wally-tool-chain-install-redhat.sh new file mode 100644 index 000000000..72cf6c5b8 --- /dev/null +++ b/bin/wally-tool-chain-install-redhat.sh @@ -0,0 +1,257 @@ +#!/bin/bash +########################################### +## Tool chain install script. +## +## Written: Ross Thompson ross1728@gmail.com +## Created: 18 January 2023 +## Modified: 22 January 2023 +## Modified: 23 March 2023 +## Adapted for Red Hat: June 19 2024, Jordan Carlin jcarlin@hmc.edu +## +## Purpose: Open source tool chain installation script +## +## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https:##solderpad.org/licenses/SHL-2.1/ +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ + +# All tools will be installed under the $RISCV directory. Depending on the location selected, +# the script may need to be run as root +export RISCV=/opt/riscv +export PATH=$PATH:$RISCV/bin:/usr/bin +export PKG_CONFIG_PATH=$RISCV/lib64/pkgconfig:$RISCV/lib/pkgconfig:$PKG_CONFIG_PATH + +set -e # break on error + +# Modify accordingly for your machine +# Increasing NUM_THREADS will speed up parallel compilation of the tools +#NUM_THREADS=2 # for low memory machines > 16GiB +NUM_THREADS=8 # for >= 32GiB +#NUM_THREADS=16 # for >= 64GiB + +mkdir -p $RISCV + +# Dependencies in package manager +echo -e "\n************************************************************" +echo -e "Installing Dependencies from Package Manager" +echo -e "************************************************************\n" +sudo yum install -y dnf-plugins-core +sudo yum config-manager --set-enabled powertools # FOR ROCKY +# sudo subscription-manager repos --enable codeready-builder-for-rhel-8-x86_64-rpms # FOR RHEL +sudo yum update -y +sudo yum group install -y "Development Tools" +sudo yum install -y git gawk make texinfo bison flex python3.12 expat-devel autoconf dtc ninja-build pixman-devel ncurses-base ncurses ncurses-libs ncurses-devel dialog curl wget ftp gmp-devel glib2-devel python3-pip pkgconfig zlib-devel automake libmpc-devel mpfr-devel gperf libtool patchutils bc mutt cmake perl gcc-c++ clang help2man numactl ocaml +sudo yum install -y gcc-toolset-13* + +# activate gcc13 +source /opt/rh/gcc-toolset-13/enable + +# Python virtual environment and package installation +echo -e "\n************************************************************" +echo -e "Setting up Python Environment" +echo -e "************************************************************\n" +cd $RISCV +python3.12 -m venv --system-site-packages riscv-python +source $RISCV/riscv-python/bin/activate +pip install --upgrade pip +pip install sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown pyyaml meson z3-solver testresources riscv_config +pip install riscv_isac # to generate new tests, such as quads with fp_dataset.py +source $RISCV/riscv-python/bin/activate + +# Other dependencies +# newer versin of glib required for Qemu +# anything newer than this won't build on red hat 8 +echo -e "\n************************************************************" +echo -e "Installing glib" +echo -e "************************************************************\n" +cd $RISCV +wget https://download.gnome.org/sources/glib/2.70/glib-2.70.5.tar.xz +tar -xJf glib-2.70.5.tar.xz +rm glib-2.70.5.tar.xz +cd glib-2.70.5 +meson setup _build --prefix=$RISCV +meson compile -C _build +meson install -C _build +cd $RISCV +rm -rf glib-2.70.5 +# gperftools - not available in yum, needed for Verilator +echo -e "\n************************************************************" +echo -e "Installing gperftools" +echo -e "************************************************************\n" +cd $RISCV +wget https://github.com/gperftools/gperftools/releases/download/gperftools-2.15/gperftools-2.15.tar.gz +tar -xzf gperftools-2.15.tar.gz +rm gperftools-2.15.tar.gz +cd gperftools-2.15 +./configure --prefix=$RISCV +make -j ${NUM_THREADS} +make install +cd $RISCV +rm -rf gperftools-2.15 +# ccache - not available in yum, needed for Verilator +echo -e "\n************************************************************" +echo -e "Installing ccache" +echo -e "************************************************************\n" +cd $RISCV +wget https://github.com/ccache/ccache/releases/download/v4.10/ccache-4.10-linux-x86_64.tar.xz +tar -xJf ccache-4.10-linux-x86_64.tar.xz +rm ccache-4.10-linux-x86_64.tar.xz +cd ccache-4.10-linux-x86_64 +cp ccache $RISCV/bin/ccache +cd $RISCV +rm -rf ccache-4.10-linux-x86_64 +# newer version of gmp needed for sail-riscv model +echo -e "\n************************************************************" +echo -e "Installing gmp" +echo -e "************************************************************\n" +cd $RISCV +wget https://ftp.gnu.org/gnu/gmp/gmp-6.3.0.tar.xz +tar -xJf gmp-6.3.0.tar.xz +rm gmp-6.3.0.tar.xz +cd gmp-6.3.0 +./configure --prefix=$RISCV +make -j ${NUM_THREADS} +make install +cd $RISCV +rm -rf gmp-6.3.0 + +# gcc cross-compiler (https://github.com/riscv-collab/riscv-gnu-toolchain) +# To install GCC from source can take hours to compile. +# This configuration enables multilib to target many flavors of RISC-V. +# This book is tested with GCC 13.2.0 +echo -e "\n************************************************************" +echo -e "Installing RISC-V GNU Toolchain" +echo -e "************************************************************\n" +cd $RISCV +git clone https://github.com/riscv/riscv-gnu-toolchain +cd riscv-gnu-toolchain +./configure --prefix=${RISCV} --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" +make -j ${NUM_THREADS} + +# elf2hex (https://github.com/sifive/elf2hex) +#The elf2hex utility to converts executable files into hexadecimal files for Verilog simulation. +# Note: The exe2hex utility that comes with Spike doesn’t work for our purposes because it doesn’t +# handle programs that start at 0x80000000. The SiFive version above is touchy to install. +# For example, if Python version 2.x is in your path, it won’t install correctly. +# Also, be sure riscv64-unknown-elf-objcopy shows up in your path in $RISCV/riscv-gnu-toolchain/bin +# at the time of compilation, or elf2hex won’t work properly. +echo -e "\n************************************************************" +echo -e "Installing elf2hex" +echo -e "************************************************************\n" +cd $RISCV +export PATH=$RISCV/bin:$PATH +git clone https://github.com/sifive/elf2hex.git +cd elf2hex +autoreconf -i +./configure --target=riscv64-unknown-elf --prefix=$RISCV +make +make install + + +# QEMU (https://www.qemu.org/docs/master/system/target-riscv.html) +echo -e "\n************************************************************" +echo -e "Installing QEMU" +echo -e "************************************************************\n" +cd $RISCV +git clone --recurse-submodules https://github.com/qemu/qemu +cd qemu +./configure --target-list=riscv64-softmmu --prefix=$RISCV +make -j ${NUM_THREADS} +make install + +# Spike (https://github.com/riscv-software-src/riscv-isa-sim) +# Spike also takes a while to install and compile, but this can be done concurrently +# with the GCC installation. +echo -e "\n************************************************************" +echo -e "Installing SPIKE" +echo -e "************************************************************\n" +cd $RISCV +git clone https://github.com/riscv-software-src/riscv-isa-sim +mkdir -p riscv-isa-sim/build +cd riscv-isa-sim/build +../configure --prefix=$RISCV +make -j ${NUM_THREADS} +make install + + +# Wally needs Verilator 5.021 or later. +# Verilator needs to be built from source to get the latest version +echo -e "\n************************************************************" +echo -e "Installing Verilator" +echo -e "************************************************************\n" +cd $RISCV +git clone https://github.com/verilator/verilator # Only first time +# unsetenv VERILATOR_ROOT # For csh; ignore error if on bash +unset VERILATOR_ROOT # For bash +cd verilator +git pull # Make sure git repository is up-to-date +git checkout master +autoconf # Create ./configure script +./configure --prefix=$RISCV # Configure and create Makefile +make -j ${NUM_THREADS} # Build Verilator itself (if error, try just 'make') +make install + +# Sail (https://github.com/riscv/sail-riscv) +# Sail is the golden reference model for RISC-V. Sail is written in OCaml, which +# is an object-oriented extension of ML, which in turn is a functional programming +# language suited to formal verification. OCaml is installed with the opam OCcaml +# package manager. Sail has so many dependencies that it can be difficult to install. +echo -e "\n************************************************************" +echo -e "Installing Opam" +echo -e "************************************************************\n" +cd $RISCV +mkdir -p opam +cd opam +wget https://raw.githubusercontent.com/ocaml/opam/master/shell/install.sh +printf '%s\n' $RISCV/bin Y | sh install.sh # the print command provides $RISCV/bin as the installation path when prompted +cd $RISCV +rm -rf opam +echo -e "\n************************************************************" +echo -e "Installing Sail Compiler" +echo -e "************************************************************\n" +opam init -y --disable-sandboxing +opam update +opam upgrade +opam switch create 5.1.0 +opam install sail -y + +echo -e "\n************************************************************" +echo -e "Installing riscv-sail Model" +echo -e "************************************************************\n" +eval $(opam config env) +git clone https://github.com/riscv/sail-riscv.git +cd sail-riscv +export OPAMCLI=2.0 # Sail is not compatible with opam 2.1 as of 4/16/24 +ARCH=RV64 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV64 +ARCH=RV32 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV32 +cd $RISCV +ln -sf sail-riscv/c_emulator/riscv_sim_RV64 bin/riscv_sim_RV64 +ln -sf sail-riscv/c_emulator/riscv_sim_RV32 bin/riscv_sim_RV32 + +# riscof +echo -e "\n************************************************************" +echo -e "Installing riscof" +echo -e "************************************************************\n" +pip3 install git+https://github.com/riscv/riscof.git + +# Download OSU Skywater 130 cell library +echo -e "\n************************************************************" +echo -e "Installing OSU Skywater 130 cell library" +echo -e "************************************************************\n" +mkdir -p $RISCV/cad/lib +cd $RISCV/cad/lib +git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12 From 5966df60a9fc7fd2279a0d4bffd4de2ce34b6ac1 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 20 Jun 2024 21:22:16 -0700 Subject: [PATCH 002/219] Update red hat install script to only install each tool if it is the first time or if there are updates --- bin/wally-tool-chain-install-redhat.sh | 228 ++++++++++++++----------- 1 file changed, 131 insertions(+), 97 deletions(-) diff --git a/bin/wally-tool-chain-install-redhat.sh b/bin/wally-tool-chain-install-redhat.sh index 72cf6c5b8..250807834 100644 --- a/bin/wally-tool-chain-install-redhat.sh +++ b/bin/wally-tool-chain-install-redhat.sh @@ -65,82 +65,94 @@ echo -e "\n************************************************************" echo -e "Setting up Python Environment" echo -e "************************************************************\n" cd $RISCV -python3.12 -m venv --system-site-packages riscv-python +if [ ! -e $RISCV/riscv-python/bin/activate ]; then + python3.12 -m venv riscv-python +fi source $RISCV/riscv-python/bin/activate -pip install --upgrade pip -pip install sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown pyyaml meson z3-solver testresources riscv_config -pip install riscv_isac # to generate new tests, such as quads with fp_dataset.py +pip install -U pip +pip install -U sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown pyyaml meson z3-solver testresources riscv_config +pip install -U riscv_isac # to generate new tests, such as quads with fp_dataset.py source $RISCV/riscv-python/bin/activate # Other dependencies # newer versin of glib required for Qemu # anything newer than this won't build on red hat 8 -echo -e "\n************************************************************" -echo -e "Installing glib" -echo -e "************************************************************\n" -cd $RISCV -wget https://download.gnome.org/sources/glib/2.70/glib-2.70.5.tar.xz -tar -xJf glib-2.70.5.tar.xz -rm glib-2.70.5.tar.xz -cd glib-2.70.5 -meson setup _build --prefix=$RISCV -meson compile -C _build -meson install -C _build -cd $RISCV -rm -rf glib-2.70.5 +if [ ! -e $RISCV/include/glib-2.0 ]; then + echo -e "\n************************************************************" + echo -e "Installing glib" + echo -e "************************************************************\n" + cd $RISCV + wget https://download.gnome.org/sources/glib/2.70/glib-2.70.5.tar.xz + tar -xJf glib-2.70.5.tar.xz + rm glib-2.70.5.tar.xz + cd glib-2.70.5 + meson setup _build --prefix=$RISCV + meson compile -C _build + meson install -C _build + cd $RISCV + rm -rf glib-2.70.5 +fi # gperftools - not available in yum, needed for Verilator -echo -e "\n************************************************************" -echo -e "Installing gperftools" -echo -e "************************************************************\n" -cd $RISCV -wget https://github.com/gperftools/gperftools/releases/download/gperftools-2.15/gperftools-2.15.tar.gz -tar -xzf gperftools-2.15.tar.gz -rm gperftools-2.15.tar.gz -cd gperftools-2.15 -./configure --prefix=$RISCV -make -j ${NUM_THREADS} -make install -cd $RISCV -rm -rf gperftools-2.15 +if [ ! -e $RISCV/include/gperftools ]; then + echo -e "\n************************************************************" + echo -e "Installing gperftools" + echo -e "************************************************************\n" + cd $RISCV + wget https://github.com/gperftools/gperftools/releases/download/gperftools-2.15/gperftools-2.15.tar.gz + tar -xzf gperftools-2.15.tar.gz + rm gperftools-2.15.tar.gz + cd gperftools-2.15 + ./configure --prefix=$RISCV + make -j ${NUM_THREADS} + make install + cd $RISCV + rm -rf gperftools-2.15 +fi # ccache - not available in yum, needed for Verilator -echo -e "\n************************************************************" -echo -e "Installing ccache" -echo -e "************************************************************\n" -cd $RISCV -wget https://github.com/ccache/ccache/releases/download/v4.10/ccache-4.10-linux-x86_64.tar.xz -tar -xJf ccache-4.10-linux-x86_64.tar.xz -rm ccache-4.10-linux-x86_64.tar.xz -cd ccache-4.10-linux-x86_64 -cp ccache $RISCV/bin/ccache -cd $RISCV -rm -rf ccache-4.10-linux-x86_64 +if [ ! -e $RISCV/bin/ccache ]; then + echo -e "\n************************************************************" + echo -e "Installing ccache" + echo -e "************************************************************\n" + cd $RISCV + wget https://github.com/ccache/ccache/releases/download/v4.10/ccache-4.10-linux-x86_64.tar.xz + tar -xJf ccache-4.10-linux-x86_64.tar.xz + rm ccache-4.10-linux-x86_64.tar.xz + cd ccache-4.10-linux-x86_64 + cp ccache $RISCV/bin/ccache + cd $RISCV + rm -rf ccache-4.10-linux-x86_64 +fi # newer version of gmp needed for sail-riscv model -echo -e "\n************************************************************" -echo -e "Installing gmp" -echo -e "************************************************************\n" -cd $RISCV -wget https://ftp.gnu.org/gnu/gmp/gmp-6.3.0.tar.xz -tar -xJf gmp-6.3.0.tar.xz -rm gmp-6.3.0.tar.xz -cd gmp-6.3.0 -./configure --prefix=$RISCV -make -j ${NUM_THREADS} -make install -cd $RISCV -rm -rf gmp-6.3.0 +if [ ! -e $RISCV/include/gmp.h ]; then + echo -e "\n************************************************************" + echo -e "Installing gmp" + echo -e "************************************************************\n" + cd $RISCV + wget https://ftp.gnu.org/gnu/gmp/gmp-6.3.0.tar.xz + tar -xJf gmp-6.3.0.tar.xz + rm gmp-6.3.0.tar.xz + cd gmp-6.3.0 + ./configure --prefix=$RISCV + make -j ${NUM_THREADS} + make install + cd $RISCV + rm -rf gmp-6.3.0 +fi # gcc cross-compiler (https://github.com/riscv-collab/riscv-gnu-toolchain) # To install GCC from source can take hours to compile. -# This configuration enables multilib to target many flavors of RISC-V. +# This configuration enables multilib to target many flavors of RISC-V. # This book is tested with GCC 13.2.0 -echo -e "\n************************************************************" echo -e "Installing RISC-V GNU Toolchain" echo -e "************************************************************\n" cd $RISCV -git clone https://github.com/riscv/riscv-gnu-toolchain -cd riscv-gnu-toolchain -./configure --prefix=${RISCV} --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" -make -j ${NUM_THREADS} +if [[ ((! -e riscv-gnu-toolchain) && ($(git clone https://github.com/riscv/riscv-gnu-toolchain) || 1)) || ($(cd riscv-gnu-toolchain; git fetch; git rev-parse HEAD) != $(cd riscv-gnu-toolchain; git rev-parse master)) ]]; then + cd riscv-gnu-toolchain + git checkout master + git pull + ./configure --prefix=${RISCV} --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" + make -j ${NUM_THREADS} +fi # elf2hex (https://github.com/sifive/elf2hex) #The elf2hex utility to converts executable files into hexadecimal files for Verilog simulation. @@ -154,12 +166,15 @@ echo -e "Installing elf2hex" echo -e "************************************************************\n" cd $RISCV export PATH=$RISCV/bin:$PATH -git clone https://github.com/sifive/elf2hex.git -cd elf2hex -autoreconf -i -./configure --target=riscv64-unknown-elf --prefix=$RISCV -make -make install +if [[ ((! -e elf2hex) && ($(git clone https://github.com/sifive/elf2hex.git) || 1)) || ($(cd elf2hex; git fetch; git rev-parse HEAD) != $(cd elf2hex; git rev-parse master)) ]]; then + cd elf2hex + git checkout master + git pull + autoreconf -i + ./configure --target=riscv64-unknown-elf --prefix=$RISCV + make + make install +fi # QEMU (https://www.qemu.org/docs/master/system/target-riscv.html) @@ -167,11 +182,14 @@ echo -e "\n************************************************************" echo -e "Installing QEMU" echo -e "************************************************************\n" cd $RISCV -git clone --recurse-submodules https://github.com/qemu/qemu -cd qemu -./configure --target-list=riscv64-softmmu --prefix=$RISCV -make -j ${NUM_THREADS} -make install +if [[ ((! -e qemu) && ($(git clone --recurse-submodules https://github.com/qemu/qemu) || 1)) || ($(cd qemu; git fetch --recurse-submodules=yes; git rev-parse HEAD) != $(cd qemu; git rev-parse master)) ]]; then + cd qemu + git checkout master + git pull --recurse-submodules + ./configure --target-list=riscv64-softmmu --prefix=$RISCV + make -j ${NUM_THREADS} + make install +fi # Spike (https://github.com/riscv-software-src/riscv-isa-sim) # Spike also takes a while to install and compile, but this can be done concurrently @@ -180,12 +198,16 @@ echo -e "\n************************************************************" echo -e "Installing SPIKE" echo -e "************************************************************\n" cd $RISCV -git clone https://github.com/riscv-software-src/riscv-isa-sim -mkdir -p riscv-isa-sim/build -cd riscv-isa-sim/build -../configure --prefix=$RISCV -make -j ${NUM_THREADS} -make install +if [[ ((! -e riscv-isa-sim) && ($(git clone https://github.com/riscv-software-src/riscv-isa-sim) || 1)) || ($(cd riscv-isa-sim; git fetch; git rev-parse HEAD) != $(cd riscv-isa-sim; git rev-parse master)) ]]; then + cd riscv-isa-sim + git checkout master + git pull + mkdir -p riscv-isa-sim/build + cd riscv-isa-sim/build + ../configure --prefix=$RISCV + make -j ${NUM_THREADS} + make install +fi # Wally needs Verilator 5.021 or later. @@ -194,16 +216,21 @@ echo -e "\n************************************************************" echo -e "Installing Verilator" echo -e "************************************************************\n" cd $RISCV -git clone https://github.com/verilator/verilator # Only first time -# unsetenv VERILATOR_ROOT # For csh; ignore error if on bash -unset VERILATOR_ROOT # For bash -cd verilator +if [[ ((! -e verilator) && ($(git clone https://github.com/verilator/verilator) || 1)) || ($(cd verilator; git fetch; git rev-parse HEAD) != $(cd verilator; git rev-parse master)) ]]; then + # unsetenv VERILATOR_ROOT # For csh; ignore error if on bash + unset VERILATOR_ROOT # For bash + cd verilator + git checkout master +git pull # Make sure git repository is up-to-date git pull # Make sure git repository is up-to-date git checkout master -autoconf # Create ./configure script -./configure --prefix=$RISCV # Configure and create Makefile -make -j ${NUM_THREADS} # Build Verilator itself (if error, try just 'make') -make install + git pull # Make sure git repository is up-to-date +git checkout master + autoconf # Create ./configure script + ./configure --prefix=$RISCV # Configure and create Makefile + make -j ${NUM_THREADS} # Build Verilator itself (if error, try just 'make') + make install +fi # Sail (https://github.com/riscv/sail-riscv) # Sail is the golden reference model for RISC-V. Sail is written in OCaml, which @@ -224,23 +251,26 @@ echo -e "\n************************************************************" echo -e "Installing Sail Compiler" echo -e "************************************************************\n" opam init -y --disable-sandboxing -opam update -opam upgrade -opam switch create 5.1.0 +opam update -y +opam upgrade -y +opam switch create 5.1.0 || opam switch set 5.1.0 opam install sail -y echo -e "\n************************************************************" echo -e "Installing riscv-sail Model" echo -e "************************************************************\n" eval $(opam config env) -git clone https://github.com/riscv/sail-riscv.git -cd sail-riscv -export OPAMCLI=2.0 # Sail is not compatible with opam 2.1 as of 4/16/24 -ARCH=RV64 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV64 -ARCH=RV32 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV32 -cd $RISCV -ln -sf sail-riscv/c_emulator/riscv_sim_RV64 bin/riscv_sim_RV64 -ln -sf sail-riscv/c_emulator/riscv_sim_RV32 bin/riscv_sim_RV32 +if [[ ((! -e sail-riscv) && ($(git clone https://github.com/riscv/sail-riscv.git) || 1)) || ($(cd sail-riscv; git fetch; git rev-parse HEAD) != $(cd sail-riscv; git rev-parse master)) ]]; then + cd sail-riscv + git checkout master + git pull + export OPAMCLI=2.0 # Sail is not compatible with opam 2.1 as of 4/16/24 + ARCH=RV64 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV64 + ARCH=RV32 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV32 + cd $RISCV + ln -sf ../sail-riscv/c_emulator/riscv_sim_RV64 bin/riscv_sim_RV64 + ln -sf ../sail-riscv/c_emulator/riscv_sim_RV32 bin/riscv_sim_RV32 +fi # riscof echo -e "\n************************************************************" @@ -254,4 +284,8 @@ echo -e "Installing OSU Skywater 130 cell library" echo -e "************************************************************\n" mkdir -p $RISCV/cad/lib cd $RISCV/cad/lib -git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12 +if [[ ((! -e sky130_osu_sc_t12) && ($(git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12) || 1)) || ($(cd sky130_osu_sc_t12; git fetch; git rev-parse HEAD) != $(cd sky130_osu_sc_t12; git rev-parse master)) ]]; then + cd sky130_osu_sc_t12 + git checkout main + git pull +fi \ No newline at end of file From cb6a9787dcd4081a502f2bbfdd22fc331a6e057d Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 20 Jun 2024 23:40:54 -0700 Subject: [PATCH 003/219] Update to use EPEL package repo for ccache and gperftools --- bin/wally-tool-chain-install-redhat.sh | 35 +++----------------------- 1 file changed, 3 insertions(+), 32 deletions(-) diff --git a/bin/wally-tool-chain-install-redhat.sh b/bin/wally-tool-chain-install-redhat.sh index 250807834..d73488945 100644 --- a/bin/wally-tool-chain-install-redhat.sh +++ b/bin/wally-tool-chain-install-redhat.sh @@ -50,11 +50,12 @@ echo -e "\n************************************************************" echo -e "Installing Dependencies from Package Manager" echo -e "************************************************************\n" sudo yum install -y dnf-plugins-core -sudo yum config-manager --set-enabled powertools # FOR ROCKY +sudo yum config-manager --set-enabled powertools # FOR ROCKY 8 +sudo yum install -y epel-release # sudo subscription-manager repos --enable codeready-builder-for-rhel-8-x86_64-rpms # FOR RHEL sudo yum update -y sudo yum group install -y "Development Tools" -sudo yum install -y git gawk make texinfo bison flex python3.12 expat-devel autoconf dtc ninja-build pixman-devel ncurses-base ncurses ncurses-libs ncurses-devel dialog curl wget ftp gmp-devel glib2-devel python3-pip pkgconfig zlib-devel automake libmpc-devel mpfr-devel gperf libtool patchutils bc mutt cmake perl gcc-c++ clang help2man numactl ocaml +sudo yum install -y git gawk make texinfo bison flex python3.12 expat-devel autoconf dtc ninja-build pixman-devel ncurses-base ncurses ncurses-libs ncurses-devel dialog curl wget ftp gmp-devel glib2-devel python3-pip pkgconfig zlib-devel automake libmpc-devel mpfr-devel gperf libtool patchutils bc mutt cmake perl gcc-c++ clang help2man numactl ocaml mold gperftools ccache sudo yum install -y gcc-toolset-13* # activate gcc13 @@ -92,36 +93,6 @@ if [ ! -e $RISCV/include/glib-2.0 ]; then cd $RISCV rm -rf glib-2.70.5 fi -# gperftools - not available in yum, needed for Verilator -if [ ! -e $RISCV/include/gperftools ]; then - echo -e "\n************************************************************" - echo -e "Installing gperftools" - echo -e "************************************************************\n" - cd $RISCV - wget https://github.com/gperftools/gperftools/releases/download/gperftools-2.15/gperftools-2.15.tar.gz - tar -xzf gperftools-2.15.tar.gz - rm gperftools-2.15.tar.gz - cd gperftools-2.15 - ./configure --prefix=$RISCV - make -j ${NUM_THREADS} - make install - cd $RISCV - rm -rf gperftools-2.15 -fi -# ccache - not available in yum, needed for Verilator -if [ ! -e $RISCV/bin/ccache ]; then - echo -e "\n************************************************************" - echo -e "Installing ccache" - echo -e "************************************************************\n" - cd $RISCV - wget https://github.com/ccache/ccache/releases/download/v4.10/ccache-4.10-linux-x86_64.tar.xz - tar -xJf ccache-4.10-linux-x86_64.tar.xz - rm ccache-4.10-linux-x86_64.tar.xz - cd ccache-4.10-linux-x86_64 - cp ccache $RISCV/bin/ccache - cd $RISCV - rm -rf ccache-4.10-linux-x86_64 -fi # newer version of gmp needed for sail-riscv model if [ ! -e $RISCV/include/gmp.h ]; then echo -e "\n************************************************************" From bfc5440b085fab143fa626bbb690f156aa0407fe Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 21 Jun 2024 01:02:24 -0700 Subject: [PATCH 004/219] red hat install script checks distro & version to determine what to install. Groundwork laid for ubuntu in same file. --- bin/wally-tool-chain-install-redhat.sh | 254 +++++++++++++++++-------- 1 file changed, 174 insertions(+), 80 deletions(-) diff --git a/bin/wally-tool-chain-install-redhat.sh b/bin/wally-tool-chain-install-redhat.sh index d73488945..8ebfa2ec2 100644 --- a/bin/wally-tool-chain-install-redhat.sh +++ b/bin/wally-tool-chain-install-redhat.sh @@ -29,93 +29,169 @@ ## and limitations under the License. ################################################################################################ -# All tools will be installed under the $RISCV directory. Depending on the location selected, -# the script may need to be run as root -export RISCV=/opt/riscv -export PATH=$PATH:$RISCV/bin:/usr/bin -export PKG_CONFIG_PATH=$RISCV/lib64/pkgconfig:$RISCV/lib/pkgconfig:$PKG_CONFIG_PATH - -set -e # break on error - -# Modify accordingly for your machine +# MODIFY FOR YOUR MACHINE # Increasing NUM_THREADS will speed up parallel compilation of the tools #NUM_THREADS=2 # for low memory machines > 16GiB NUM_THREADS=8 # for >= 32GiB #NUM_THREADS=16 # for >= 64GiB +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" +echo -e "Checking Distro and Permissions and Setting Installation Directory" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" + +set -e # break on error + +# Get distribution information +test -e /etc/os-release && os_release="/etc/os-release" || os_release="/usr/lib/os-release" +source $os_release + +# Check for compatible distro +if [[ $ID = rhel || $ID = rocky ]]; then + FAMILY=rhel + if [ "${VERSION_ID:0:1}" = 8 ]; then + RHEL_VERSION=8 + elif [ "${VERSION_ID:0:1}" = 9 ]; then + RHEL_VERSION=9 + else + echo "The Wally install script is only compatible with versions 8 and 9 of RHEL and Rocky Linux. You have version $VERSION." + exit 1 + fi +elif [[ $ID = ubuntu || $ID_LIKE = *ubuntu* ]]; then + FAMILY=ubuntu +else + echo "The Wally install script is currently only compatible with Ubuntu and Red Hat family \ +(RHEL or Rocky Linux) distros. Your detected distro is $ID. You may try manually running the \ +commands in this script, but it is likely that some will need to be altered." + exit 1 +fi + +# Check if root +ROOT=$( [ "${EUID:=$(id -u)}" = 0 ] && echo 1 || echo 0); + +# All tools will be installed under the $RISCV directory. By default, if run as root (with sudo) +# this is set to /opt/riscv. Otherwise, it is set to ~/riscv. This value can be changed if needed. +if [ $ROOT = 1 ]; then + export RISCV=/opt/riscv +else + export RISCV=~/riscv +fi + +export PATH=$PATH:$RISCV/bin:/usr/bin +export PKG_CONFIG_PATH=$RISCV/lib64/pkgconfig:$RISCV/lib/pkgconfig:$PKG_CONFIG_PATH mkdir -p $RISCV -# Dependencies in package manager -echo -e "\n************************************************************" +echo "Detected information:" +echo "Distribution: $NAME" +echo "Version: $VERSION" +echo "Running as root: $ROOT" +echo "Installation path: $RISCV" + +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" echo -e "Installing Dependencies from Package Manager" -echo -e "************************************************************\n" -sudo yum install -y dnf-plugins-core -sudo yum config-manager --set-enabled powertools # FOR ROCKY 8 -sudo yum install -y epel-release -# sudo subscription-manager repos --enable codeready-builder-for-rhel-8-x86_64-rpms # FOR RHEL -sudo yum update -y -sudo yum group install -y "Development Tools" -sudo yum install -y git gawk make texinfo bison flex python3.12 expat-devel autoconf dtc ninja-build pixman-devel ncurses-base ncurses ncurses-libs ncurses-devel dialog curl wget ftp gmp-devel glib2-devel python3-pip pkgconfig zlib-devel automake libmpc-devel mpfr-devel gperf libtool patchutils bc mutt cmake perl gcc-c++ clang help2man numactl ocaml mold gperftools ccache -sudo yum install -y gcc-toolset-13* +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" +if [ $FAMILY = rhel ]; then + sudo dnf install -y dnf-plugins-core + if [ $ID = rocky ]; then + if [ $RHEL_VERSION = 8 ]; then + sudo dnf config-manager -y --set-enabled powertools + else # Version 9 + sudo dnf config-manager -y --set-enabled crb + fi + sudo dnf install -y epel-release + else # RHEL + if [ $RHEL_VERSION = 8 ]; then + sudo subscription-manager repos --enable codeready-builder-for-rhel-8-x86_64-rpms + sudo dnf install -y https://dl.fedoraproject.org/pub/epel/epel-release-latest-8.noarch.rpm + else # Version 9 + sudo subscription-manager repos --enable codeready-builder-for-rhel-9-x86_64-rpms + sudo dnf install -y https://dl.fedoraproject.org/pub/epel/epel-release-latest-9.noarch.rpm + fi + fi + sudo dnf update -y + sudo dnf group install -y "Development Tools" + sudo dnf install -y git gawk make texinfo bison flex python3.12 expat-devel autoconf dtc ninja-build pixman-devel ncurses-base ncurses ncurses-libs ncurses-devel dialog curl wget ftp gmp-devel glib2-devel python3-pip pkgconfig zlib-devel automake libmpc-devel mpfr-devel gperf libtool patchutils bc mutt cmake perl gcc-c++ clang help2man numactl ocaml mold gperftools ccache + if [ $RHEL_VERSION = 9 ]; then + sudo dnf install -y z3 + fi + sudo dnf install -y gcc-toolset-13* -# activate gcc13 -source /opt/rh/gcc-toolset-13/enable + # activate gcc13 + source /opt/rh/gcc-toolset-13/enable +fi -# Python virtual environment and package installation -echo -e "\n************************************************************" +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" echo -e "Setting up Python Environment" -echo -e "************************************************************\n" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" cd $RISCV if [ ! -e $RISCV/riscv-python/bin/activate ]; then python3.12 -m venv riscv-python fi source $RISCV/riscv-python/bin/activate pip install -U pip -pip install -U sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown pyyaml meson z3-solver testresources riscv_config +pip install -U sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown pyyaml meson testresources riscv_config pip install -U riscv_isac # to generate new tests, such as quads with fp_dataset.py +if [ $RHEL_VERSION = 8 ]; then + pip install -U z3-solver +fi + source $RISCV/riscv-python/bin/activate -# Other dependencies -# newer versin of glib required for Qemu -# anything newer than this won't build on red hat 8 -if [ ! -e $RISCV/include/glib-2.0 ]; then - echo -e "\n************************************************************" - echo -e "Installing glib" - echo -e "************************************************************\n" - cd $RISCV - wget https://download.gnome.org/sources/glib/2.70/glib-2.70.5.tar.xz - tar -xJf glib-2.70.5.tar.xz - rm glib-2.70.5.tar.xz - cd glib-2.70.5 - meson setup _build --prefix=$RISCV - meson compile -C _build - meson install -C _build - cd $RISCV - rm -rf glib-2.70.5 -fi -# newer version of gmp needed for sail-riscv model -if [ ! -e $RISCV/include/gmp.h ]; then - echo -e "\n************************************************************" - echo -e "Installing gmp" - echo -e "************************************************************\n" - cd $RISCV - wget https://ftp.gnu.org/gnu/gmp/gmp-6.3.0.tar.xz - tar -xJf gmp-6.3.0.tar.xz - rm gmp-6.3.0.tar.xz - cd gmp-6.3.0 - ./configure --prefix=$RISCV - make -j ${NUM_THREADS} - make install - cd $RISCV - rm -rf gmp-6.3.0 +if [ $RHEL_VERSION = 8 ]; then + # Other dependencies + # newer versin of glib required for Qemu + # anything newer than this won't build on red hat 8 + if [ ! -e $RISCV/include/glib-2.0 ]; then + echo -e "\n*************************************************************************" + echo -e "*************************************************************************" + echo -e "Installing glib" + echo -e "*************************************************************************" + echo -e "*************************************************************************\n" + cd $RISCV + wget https://download.gnome.org/sources/glib/2.70/glib-2.70.5.tar.xz + tar -xJf glib-2.70.5.tar.xz + rm glib-2.70.5.tar.xz + cd glib-2.70.5 + meson setup _build --prefix=$RISCV + meson compile -C _build + meson install -C _build + cd $RISCV + rm -rf glib-2.70.5 + fi + # newer version of gmp needed for sail-riscv model + if [ ! -e $RISCV/include/gmp.h ]; then + echo -e "\n*************************************************************************" + echo -e "*************************************************************************" + echo -e "Installing gmp" + echo -e "*************************************************************************" + echo -e "*************************************************************************\n" + cd $RISCV + wget https://ftp.gnu.org/gnu/gmp/gmp-6.3.0.tar.xz + tar -xJf gmp-6.3.0.tar.xz + rm gmp-6.3.0.tar.xz + cd gmp-6.3.0 + ./configure --prefix=$RISCV + make -j ${NUM_THREADS} + make install + cd $RISCV + rm -rf gmp-6.3.0 + fi fi # gcc cross-compiler (https://github.com/riscv-collab/riscv-gnu-toolchain) # To install GCC from source can take hours to compile. # This configuration enables multilib to target many flavors of RISC-V. # This book is tested with GCC 13.2.0 +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" echo -e "Installing RISC-V GNU Toolchain" -echo -e "************************************************************\n" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" cd $RISCV if [[ ((! -e riscv-gnu-toolchain) && ($(git clone https://github.com/riscv/riscv-gnu-toolchain) || 1)) || ($(cd riscv-gnu-toolchain; git fetch; git rev-parse HEAD) != $(cd riscv-gnu-toolchain; git rev-parse master)) ]]; then cd riscv-gnu-toolchain @@ -132,9 +208,11 @@ fi # For example, if Python version 2.x is in your path, it won’t install correctly. # Also, be sure riscv64-unknown-elf-objcopy shows up in your path in $RISCV/riscv-gnu-toolchain/bin # at the time of compilation, or elf2hex won’t work properly. -echo -e "\n************************************************************" +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" echo -e "Installing elf2hex" -echo -e "************************************************************\n" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" cd $RISCV export PATH=$RISCV/bin:$PATH if [[ ((! -e elf2hex) && ($(git clone https://github.com/sifive/elf2hex.git) || 1)) || ($(cd elf2hex; git fetch; git rev-parse HEAD) != $(cd elf2hex; git rev-parse master)) ]]; then @@ -149,9 +227,11 @@ fi # QEMU (https://www.qemu.org/docs/master/system/target-riscv.html) -echo -e "\n************************************************************" +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" echo -e "Installing QEMU" -echo -e "************************************************************\n" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" cd $RISCV if [[ ((! -e qemu) && ($(git clone --recurse-submodules https://github.com/qemu/qemu) || 1)) || ($(cd qemu; git fetch --recurse-submodules=yes; git rev-parse HEAD) != $(cd qemu; git rev-parse master)) ]]; then cd qemu @@ -165,16 +245,18 @@ fi # Spike (https://github.com/riscv-software-src/riscv-isa-sim) # Spike also takes a while to install and compile, but this can be done concurrently # with the GCC installation. -echo -e "\n************************************************************" +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" echo -e "Installing SPIKE" -echo -e "************************************************************\n" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" cd $RISCV if [[ ((! -e riscv-isa-sim) && ($(git clone https://github.com/riscv-software-src/riscv-isa-sim) || 1)) || ($(cd riscv-isa-sim; git fetch; git rev-parse HEAD) != $(cd riscv-isa-sim; git rev-parse master)) ]]; then cd riscv-isa-sim git checkout master git pull - mkdir -p riscv-isa-sim/build - cd riscv-isa-sim/build + mkdir -p build + cd build ../configure --prefix=$RISCV make -j ${NUM_THREADS} make install @@ -183,9 +265,11 @@ fi # Wally needs Verilator 5.021 or later. # Verilator needs to be built from source to get the latest version -echo -e "\n************************************************************" +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" echo -e "Installing Verilator" -echo -e "************************************************************\n" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" cd $RISCV if [[ ((! -e verilator) && ($(git clone https://github.com/verilator/verilator) || 1)) || ($(cd verilator; git fetch; git rev-parse HEAD) != $(cd verilator; git rev-parse master)) ]]; then # unsetenv VERILATOR_ROOT # For csh; ignore error if on bash @@ -208,9 +292,11 @@ fi # is an object-oriented extension of ML, which in turn is a functional programming # language suited to formal verification. OCaml is installed with the opam OCcaml # package manager. Sail has so many dependencies that it can be difficult to install. -echo -e "\n************************************************************" +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" echo -e "Installing Opam" -echo -e "************************************************************\n" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" cd $RISCV mkdir -p opam cd opam @@ -218,18 +304,22 @@ wget https://raw.githubusercontent.com/ocaml/opam/master/shell/install.sh printf '%s\n' $RISCV/bin Y | sh install.sh # the print command provides $RISCV/bin as the installation path when prompted cd $RISCV rm -rf opam -echo -e "\n************************************************************" +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" echo -e "Installing Sail Compiler" -echo -e "************************************************************\n" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" opam init -y --disable-sandboxing opam update -y opam upgrade -y opam switch create 5.1.0 || opam switch set 5.1.0 opam install sail -y -echo -e "\n************************************************************" +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" echo -e "Installing riscv-sail Model" -echo -e "************************************************************\n" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" eval $(opam config env) if [[ ((! -e sail-riscv) && ($(git clone https://github.com/riscv/sail-riscv.git) || 1)) || ($(cd sail-riscv; git fetch; git rev-parse HEAD) != $(cd sail-riscv; git rev-parse master)) ]]; then cd sail-riscv @@ -244,15 +334,19 @@ if [[ ((! -e sail-riscv) && ($(git clone https://github.com/riscv/sail-riscv.git fi # riscof -echo -e "\n************************************************************" +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" echo -e "Installing riscof" -echo -e "************************************************************\n" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" pip3 install git+https://github.com/riscv/riscof.git # Download OSU Skywater 130 cell library -echo -e "\n************************************************************" +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" echo -e "Installing OSU Skywater 130 cell library" -echo -e "************************************************************\n" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" mkdir -p $RISCV/cad/lib cd $RISCV/cad/lib if [[ ((! -e sky130_osu_sc_t12) && ($(git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12) || 1)) || ($(cd sky130_osu_sc_t12; git fetch; git rev-parse HEAD) != $(cd sky130_osu_sc_t12; git rev-parse master)) ]]; then From ca48447ff15454c2f836ca2e26a3ba0e5eec37db Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 21 Jun 2024 15:45:51 -0700 Subject: [PATCH 005/219] Check if repo cloned but tool not installed (if there was an error and the script is being rerun), and install if so --- bin/wally-tool-chain-install-redhat.sh | 39 +++++++++----------------- 1 file changed, 14 insertions(+), 25 deletions(-) diff --git a/bin/wally-tool-chain-install-redhat.sh b/bin/wally-tool-chain-install-redhat.sh index 8ebfa2ec2..1ed5bb8cd 100644 --- a/bin/wally-tool-chain-install-redhat.sh +++ b/bin/wally-tool-chain-install-redhat.sh @@ -79,7 +79,7 @@ else fi export PATH=$PATH:$RISCV/bin:/usr/bin -export PKG_CONFIG_PATH=$RISCV/lib64/pkgconfig:$RISCV/lib/pkgconfig:$PKG_CONFIG_PATH +export PKG_CONFIG_PATH=$RISCV/lib64/pkgconfig:$RISCV/lib/pkgconfig:$RISCV/share/pkgconfig:$PKG_CONFIG_PATH mkdir -p $RISCV echo "Detected information:" @@ -193,7 +193,7 @@ echo -e "Installing RISC-V GNU Toolchain" echo -e "*************************************************************************" echo -e "*************************************************************************\n" cd $RISCV -if [[ ((! -e riscv-gnu-toolchain) && ($(git clone https://github.com/riscv/riscv-gnu-toolchain) || 1)) || ($(cd riscv-gnu-toolchain; git fetch; git rev-parse HEAD) != $(cd riscv-gnu-toolchain; git rev-parse master)) ]]; then +if [[ ((! -e riscv-gnu-toolchain) && ($(git clone https://github.com/riscv/riscv-gnu-toolchain) || 1)) || ($(cd riscv-gnu-toolchain; git fetch; git rev-parse HEAD) != $(cd riscv-gnu-toolchain; git rev-parse master)) || (! -e $RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2) ]]; then cd riscv-gnu-toolchain git checkout master git pull @@ -215,10 +215,9 @@ echo -e "*********************************************************************** echo -e "*************************************************************************\n" cd $RISCV export PATH=$RISCV/bin:$PATH -if [[ ((! -e elf2hex) && ($(git clone https://github.com/sifive/elf2hex.git) || 1)) || ($(cd elf2hex; git fetch; git rev-parse HEAD) != $(cd elf2hex; git rev-parse master)) ]]; then +if [[ ((! -e elf2hex) && ($(git clone https://github.com/sifive/elf2hex.git) || 1)) || ($(cd elf2hex; git fetch; git rev-parse HEAD) != $(cd elf2hex; git rev-parse master)) || (! -e $RISCV/bin/riscv64-unknown-elf-elf2bin) ]]; then cd elf2hex - git checkout master - git pull + git reset --hard && git clean -f && git checkout master && git pull autoreconf -i ./configure --target=riscv64-unknown-elf --prefix=$RISCV make @@ -233,10 +232,9 @@ echo -e "Installing QEMU" echo -e "*************************************************************************" echo -e "*************************************************************************\n" cd $RISCV -if [[ ((! -e qemu) && ($(git clone --recurse-submodules https://github.com/qemu/qemu) || 1)) || ($(cd qemu; git fetch --recurse-submodules=yes; git rev-parse HEAD) != $(cd qemu; git rev-parse master)) ]]; then +if [[ ((! -e qemu) && ($(git clone --recurse-submodules https://github.com/qemu/qemu) || 1)) || ($(cd qemu; git fetch --recurse-submodules=yes; git rev-parse HEAD) != $(cd qemu; git rev-parse master)) || (! -e $RISCV/include/qemu-plugin.h) ]]; then cd qemu - git checkout master - git pull --recurse-submodules + git reset --hard && git clean -f && git checkout master && git pull --recurse-submodules ./configure --target-list=riscv64-softmmu --prefix=$RISCV make -j ${NUM_THREADS} make install @@ -251,10 +249,9 @@ echo -e "Installing SPIKE" echo -e "*************************************************************************" echo -e "*************************************************************************\n" cd $RISCV -if [[ ((! -e riscv-isa-sim) && ($(git clone https://github.com/riscv-software-src/riscv-isa-sim) || 1)) || ($(cd riscv-isa-sim; git fetch; git rev-parse HEAD) != $(cd riscv-isa-sim; git rev-parse master)) ]]; then +if [[ ((! -e riscv-isa-sim) && ($(git clone https://github.com/riscv-software-src/riscv-isa-sim) || 1)) || ($(cd riscv-isa-sim; git fetch; git rev-parse HEAD) != $(cd riscv-isa-sim; git rev-parse master)) || (! -e $RISCV/lib/pkgconfig/riscv-riscv.pc) ]]; then cd riscv-isa-sim - git checkout master - git pull + git reset --hard && git clean -f && git checkout master && git pull mkdir -p build cd build ../configure --prefix=$RISCV @@ -262,7 +259,6 @@ if [[ ((! -e riscv-isa-sim) && ($(git clone https://github.com/riscv-software-sr make install fi - # Wally needs Verilator 5.021 or later. # Verilator needs to be built from source to get the latest version echo -e "\n*************************************************************************" @@ -271,16 +267,11 @@ echo -e "Installing Verilator" echo -e "*************************************************************************" echo -e "*************************************************************************\n" cd $RISCV -if [[ ((! -e verilator) && ($(git clone https://github.com/verilator/verilator) || 1)) || ($(cd verilator; git fetch; git rev-parse HEAD) != $(cd verilator; git rev-parse master)) ]]; then +if [[ ((! -e verilator) && ($(git clone https://github.com/verilator/verilator) || 1)) || ($(cd verilator; git fetch; git rev-parse HEAD) != $(cd verilator; git rev-parse master)) || (! -e $RISCV/share/pkgconfig/verilator.pc) ]]; then # unsetenv VERILATOR_ROOT # For csh; ignore error if on bash unset VERILATOR_ROOT # For bash cd verilator - git checkout master -git pull # Make sure git repository is up-to-date -git pull # Make sure git repository is up-to-date -git checkout master - git pull # Make sure git repository is up-to-date -git checkout master + git reset --hard && git clean -f && git checkout master && git pull autoconf # Create ./configure script ./configure --prefix=$RISCV # Configure and create Makefile make -j ${NUM_THREADS} # Build Verilator itself (if error, try just 'make') @@ -321,10 +312,9 @@ echo -e "Installing riscv-sail Model" echo -e "*************************************************************************" echo -e "*************************************************************************\n" eval $(opam config env) -if [[ ((! -e sail-riscv) && ($(git clone https://github.com/riscv/sail-riscv.git) || 1)) || ($(cd sail-riscv; git fetch; git rev-parse HEAD) != $(cd sail-riscv; git rev-parse master)) ]]; then +if [[ ((! -e sail-riscv) && ($(git clone https://github.com/riscv/sail-riscv.git) || 1)) || ($(cd sail-riscv; git fetch; git rev-parse HEAD) != $(cd sail-riscv; git rev-parse master)) || (! -e $RISCV/bin/riscv_sim_RV32) ]]; then cd sail-riscv - git checkout master - git pull + git reset --hard && git clean -f && git checkout master && git pull export OPAMCLI=2.0 # Sail is not compatible with opam 2.1 as of 4/16/24 ARCH=RV64 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV64 ARCH=RV32 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV32 @@ -351,6 +341,5 @@ mkdir -p $RISCV/cad/lib cd $RISCV/cad/lib if [[ ((! -e sky130_osu_sc_t12) && ($(git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12) || 1)) || ($(cd sky130_osu_sc_t12; git fetch; git rev-parse HEAD) != $(cd sky130_osu_sc_t12; git rev-parse master)) ]]; then cd sky130_osu_sc_t12 - git checkout main - git pull -fi \ No newline at end of file + git reset --hard && git clean -f && git checkout main && git pull +fi From 57f042c6b6fe3b2dbe23c2c9dc34dc776a1c0281 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 21 Jun 2024 16:58:45 -0700 Subject: [PATCH 006/219] code style fixes --- bin/wally-tool-chain-install-redhat.sh | 39 +++++++++++++------------- 1 file changed, 19 insertions(+), 20 deletions(-) diff --git a/bin/wally-tool-chain-install-redhat.sh b/bin/wally-tool-chain-install-redhat.sh index 1ed5bb8cd..c34b87c2a 100644 --- a/bin/wally-tool-chain-install-redhat.sh +++ b/bin/wally-tool-chain-install-redhat.sh @@ -45,10 +45,10 @@ set -e # break on error # Get distribution information test -e /etc/os-release && os_release="/etc/os-release" || os_release="/usr/lib/os-release" -source $os_release +source "$os_release" # Check for compatible distro -if [[ $ID = rhel || $ID = rocky ]]; then +if [[ "$ID" = rhel || "$ID" = rocky ]]; then FAMILY=rhel if [ "${VERSION_ID:0:1}" = 8 ]; then RHEL_VERSION=8 @@ -58,7 +58,7 @@ if [[ $ID = rhel || $ID = rocky ]]; then echo "The Wally install script is only compatible with versions 8 and 9 of RHEL and Rocky Linux. You have version $VERSION." exit 1 fi -elif [[ $ID = ubuntu || $ID_LIKE = *ubuntu* ]]; then +elif [[ "$ID" = ubuntu || "$ID_LIKE" = *ubuntu* ]]; then FAMILY=ubuntu else echo "The Wally install script is currently only compatible with Ubuntu and Red Hat family \ @@ -68,11 +68,11 @@ commands in this script, but it is likely that some will need to be altered." fi # Check if root -ROOT=$( [ "${EUID:=$(id -u)}" = 0 ] && echo 1 || echo 0); +ROOT=$( [ "${EUID:=$(id -u)}" = 0 ] && echo true || echo false); # All tools will be installed under the $RISCV directory. By default, if run as root (with sudo) # this is set to /opt/riscv. Otherwise, it is set to ~/riscv. This value can be changed if needed. -if [ $ROOT = 1 ]; then +if [ "$ROOT" = true ]; then export RISCV=/opt/riscv else export RISCV=~/riscv @@ -93,17 +93,17 @@ echo -e "*********************************************************************** echo -e "Installing Dependencies from Package Manager" echo -e "*************************************************************************" echo -e "*************************************************************************\n" -if [ $FAMILY = rhel ]; then +if [ "$FAMILY" = rhel ]; then sudo dnf install -y dnf-plugins-core - if [ $ID = rocky ]; then - if [ $RHEL_VERSION = 8 ]; then + if [ "$ID" = rocky ]; then + if [ "$RHEL_VERSION" = 8 ]; then sudo dnf config-manager -y --set-enabled powertools else # Version 9 sudo dnf config-manager -y --set-enabled crb fi sudo dnf install -y epel-release else # RHEL - if [ $RHEL_VERSION = 8 ]; then + if [ "$RHEL_VERSION" = 8 ]; then sudo subscription-manager repos --enable codeready-builder-for-rhel-8-x86_64-rpms sudo dnf install -y https://dl.fedoraproject.org/pub/epel/epel-release-latest-8.noarch.rpm else # Version 9 @@ -114,7 +114,7 @@ if [ $FAMILY = rhel ]; then sudo dnf update -y sudo dnf group install -y "Development Tools" sudo dnf install -y git gawk make texinfo bison flex python3.12 expat-devel autoconf dtc ninja-build pixman-devel ncurses-base ncurses ncurses-libs ncurses-devel dialog curl wget ftp gmp-devel glib2-devel python3-pip pkgconfig zlib-devel automake libmpc-devel mpfr-devel gperf libtool patchutils bc mutt cmake perl gcc-c++ clang help2man numactl ocaml mold gperftools ccache - if [ $RHEL_VERSION = 9 ]; then + if [ "$RHEL_VERSION" = 9 ]; then sudo dnf install -y z3 fi sudo dnf install -y gcc-toolset-13* @@ -136,13 +136,12 @@ source $RISCV/riscv-python/bin/activate pip install -U pip pip install -U sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown pyyaml meson testresources riscv_config pip install -U riscv_isac # to generate new tests, such as quads with fp_dataset.py -if [ $RHEL_VERSION = 8 ]; then +if [ "$RHEL_VERSION" = 8 ]; then pip install -U z3-solver fi - source $RISCV/riscv-python/bin/activate -if [ $RHEL_VERSION = 8 ]; then +if [ "$RHEL_VERSION" = 8 ]; then # Other dependencies # newer versin of glib required for Qemu # anything newer than this won't build on red hat 8 @@ -193,7 +192,7 @@ echo -e "Installing RISC-V GNU Toolchain" echo -e "*************************************************************************" echo -e "*************************************************************************\n" cd $RISCV -if [[ ((! -e riscv-gnu-toolchain) && ($(git clone https://github.com/riscv/riscv-gnu-toolchain) || 1)) || ($(cd riscv-gnu-toolchain; git fetch; git rev-parse HEAD) != $(cd riscv-gnu-toolchain; git rev-parse master)) || (! -e $RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2) ]]; then +if [[ ((! -e riscv-gnu-toolchain) && ($(git clone https://github.com/riscv/riscv-gnu-toolchain) || true)) || ($(cd riscv-gnu-toolchain; git fetch; git rev-parse HEAD) != $(cd riscv-gnu-toolchain; git rev-parse master)) || (! -e $RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2) ]]; then cd riscv-gnu-toolchain git checkout master git pull @@ -215,7 +214,7 @@ echo -e "*********************************************************************** echo -e "*************************************************************************\n" cd $RISCV export PATH=$RISCV/bin:$PATH -if [[ ((! -e elf2hex) && ($(git clone https://github.com/sifive/elf2hex.git) || 1)) || ($(cd elf2hex; git fetch; git rev-parse HEAD) != $(cd elf2hex; git rev-parse master)) || (! -e $RISCV/bin/riscv64-unknown-elf-elf2bin) ]]; then +if [[ ((! -e elf2hex) && ($(git clone https://github.com/sifive/elf2hex.git) || true)) || ($(cd elf2hex; git fetch; git rev-parse HEAD) != $(cd elf2hex; git rev-parse master)) || (! -e $RISCV/bin/riscv64-unknown-elf-elf2bin) ]]; then cd elf2hex git reset --hard && git clean -f && git checkout master && git pull autoreconf -i @@ -232,7 +231,7 @@ echo -e "Installing QEMU" echo -e "*************************************************************************" echo -e "*************************************************************************\n" cd $RISCV -if [[ ((! -e qemu) && ($(git clone --recurse-submodules https://github.com/qemu/qemu) || 1)) || ($(cd qemu; git fetch --recurse-submodules=yes; git rev-parse HEAD) != $(cd qemu; git rev-parse master)) || (! -e $RISCV/include/qemu-plugin.h) ]]; then +if [[ ((! -e qemu) && ($(git clone --recurse-submodules https://github.com/qemu/qemu) || true)) || ($(cd qemu; git fetch --recurse-submodules=yes; git rev-parse HEAD) != $(cd qemu; git rev-parse master)) || (! -e $RISCV/include/qemu-plugin.h) ]]; then cd qemu git reset --hard && git clean -f && git checkout master && git pull --recurse-submodules ./configure --target-list=riscv64-softmmu --prefix=$RISCV @@ -249,7 +248,7 @@ echo -e "Installing SPIKE" echo -e "*************************************************************************" echo -e "*************************************************************************\n" cd $RISCV -if [[ ((! -e riscv-isa-sim) && ($(git clone https://github.com/riscv-software-src/riscv-isa-sim) || 1)) || ($(cd riscv-isa-sim; git fetch; git rev-parse HEAD) != $(cd riscv-isa-sim; git rev-parse master)) || (! -e $RISCV/lib/pkgconfig/riscv-riscv.pc) ]]; then +if [[ ((! -e riscv-isa-sim) && ($(git clone https://github.com/riscv-software-src/riscv-isa-sim) || true)) || ($(cd riscv-isa-sim; git fetch; git rev-parse HEAD) != $(cd riscv-isa-sim; git rev-parse master)) || (! -e $RISCV/lib/pkgconfig/riscv-riscv.pc) ]]; then cd riscv-isa-sim git reset --hard && git clean -f && git checkout master && git pull mkdir -p build @@ -267,7 +266,7 @@ echo -e "Installing Verilator" echo -e "*************************************************************************" echo -e "*************************************************************************\n" cd $RISCV -if [[ ((! -e verilator) && ($(git clone https://github.com/verilator/verilator) || 1)) || ($(cd verilator; git fetch; git rev-parse HEAD) != $(cd verilator; git rev-parse master)) || (! -e $RISCV/share/pkgconfig/verilator.pc) ]]; then +if [[ ((! -e verilator) && ($(git clone https://github.com/verilator/verilator) || true)) || ($(cd verilator; git fetch; git rev-parse HEAD) != $(cd verilator; git rev-parse master)) || (! -e $RISCV/share/pkgconfig/verilator.pc) ]]; then # unsetenv VERILATOR_ROOT # For csh; ignore error if on bash unset VERILATOR_ROOT # For bash cd verilator @@ -312,7 +311,7 @@ echo -e "Installing riscv-sail Model" echo -e "*************************************************************************" echo -e "*************************************************************************\n" eval $(opam config env) -if [[ ((! -e sail-riscv) && ($(git clone https://github.com/riscv/sail-riscv.git) || 1)) || ($(cd sail-riscv; git fetch; git rev-parse HEAD) != $(cd sail-riscv; git rev-parse master)) || (! -e $RISCV/bin/riscv_sim_RV32) ]]; then +if [[ ((! -e sail-riscv) && ($(git clone https://github.com/riscv/sail-riscv.git) || true)) || ($(cd sail-riscv; git fetch; git rev-parse HEAD) != $(cd sail-riscv; git rev-parse master)) || (! -e $RISCV/bin/riscv_sim_RV32) ]]; then cd sail-riscv git reset --hard && git clean -f && git checkout master && git pull export OPAMCLI=2.0 # Sail is not compatible with opam 2.1 as of 4/16/24 @@ -339,7 +338,7 @@ echo -e "*********************************************************************** echo -e "*************************************************************************\n" mkdir -p $RISCV/cad/lib cd $RISCV/cad/lib -if [[ ((! -e sky130_osu_sc_t12) && ($(git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12) || 1)) || ($(cd sky130_osu_sc_t12; git fetch; git rev-parse HEAD) != $(cd sky130_osu_sc_t12; git rev-parse master)) ]]; then +if [[ ((! -e sky130_osu_sc_t12) && ($(git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12) || true)) || ($(cd sky130_osu_sc_t12; git fetch; git rev-parse HEAD) != $(cd sky130_osu_sc_t12; git rev-parse master)) ]]; then cd sky130_osu_sc_t12 git reset --hard && git clean -f && git checkout main && git pull fi From 009672092a8bffeb668a16311c6ba83be9845df7 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 21 Jun 2024 18:28:36 -0700 Subject: [PATCH 007/219] Red Hat family distro detection improvements --- bin/wally-tool-chain-install-redhat.sh | 29 ++++++++++++++------------ 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/bin/wally-tool-chain-install-redhat.sh b/bin/wally-tool-chain-install-redhat.sh index c34b87c2a..16f7836ff 100644 --- a/bin/wally-tool-chain-install-redhat.sh +++ b/bin/wally-tool-chain-install-redhat.sh @@ -48,8 +48,12 @@ test -e /etc/os-release && os_release="/etc/os-release" || os_release="/usr/lib/ source "$os_release" # Check for compatible distro -if [[ "$ID" = rhel || "$ID" = rocky ]]; then +if [[ "$ID" = rhel || "$ID_LIKE" = *rhel* ]]; then FAMILY=rhel + if [ "$ID" != rhel ] && [ "$ID" != rocky ]; then + echo "For Red Hat family distros, the Wally install script has only been tested on RHEL and Rocky Linux. Your distro \ +is $PRETTY_NAME. The regular Red Hat install will be attempted, but there will likely be issues." + fi if [ "${VERSION_ID:0:1}" = 8 ]; then RHEL_VERSION=8 elif [ "${VERSION_ID:0:1}" = 9 ]; then @@ -60,6 +64,10 @@ if [[ "$ID" = rhel || "$ID" = rocky ]]; then fi elif [[ "$ID" = ubuntu || "$ID_LIKE" = *ubuntu* ]]; then FAMILY=ubuntu + if [ "$ID" != ubuntu ]; then + echo "For Ubuntu family distros, the Wally install script has only been tested on standard Ubuntu. Your distro \ +is $PRETTY_NAME. The regular Ubuntu install will be attempted, but there may be issues." + fi else echo "The Wally install script is currently only compatible with Ubuntu and Red Hat family \ (RHEL or Rocky Linux) distros. Your detected distro is $ID. You may try manually running the \ @@ -82,9 +90,9 @@ export PATH=$PATH:$RISCV/bin:/usr/bin export PKG_CONFIG_PATH=$RISCV/lib64/pkgconfig:$RISCV/lib/pkgconfig:$RISCV/share/pkgconfig:$PKG_CONFIG_PATH mkdir -p $RISCV -echo "Detected information:" -echo "Distribution: $NAME" -echo "Version: $VERSION" +echo -e "\nDetected information:" +echo "Distribution: $NAME_PRETTY" +echo "Version: $VERSION_PRETTY" echo "Running as root: $ROOT" echo "Installation path: $RISCV" @@ -95,21 +103,16 @@ echo -e "*********************************************************************** echo -e "*************************************************************************\n" if [ "$FAMILY" = rhel ]; then sudo dnf install -y dnf-plugins-core - if [ "$ID" = rocky ]; then + if [ "$ID" = rhel ]; then + sudo subscription-manager repos --enable "codeready-builder-for-rhel-$RHEL_VERSION-x86_64-rpms" + sudo dnf install -y "https://dl.fedoraproject.org/pub/epel/epel-release-latest-$RHEL_VERSION.noarch.rpm" + else if [ "$RHEL_VERSION" = 8 ]; then sudo dnf config-manager -y --set-enabled powertools else # Version 9 sudo dnf config-manager -y --set-enabled crb fi sudo dnf install -y epel-release - else # RHEL - if [ "$RHEL_VERSION" = 8 ]; then - sudo subscription-manager repos --enable codeready-builder-for-rhel-8-x86_64-rpms - sudo dnf install -y https://dl.fedoraproject.org/pub/epel/epel-release-latest-8.noarch.rpm - else # Version 9 - sudo subscription-manager repos --enable codeready-builder-for-rhel-9-x86_64-rpms - sudo dnf install -y https://dl.fedoraproject.org/pub/epel/epel-release-latest-9.noarch.rpm - fi fi sudo dnf update -y sudo dnf group install -y "Development Tools" From 206f52a3718b390ebdaf2b23170cbccb220f1075 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 21 Jun 2024 21:15:02 -0700 Subject: [PATCH 008/219] red hat install script syntax updates and allow for overriding of $RISCV directory --- bin/wally-tool-chain-install-redhat.sh | 62 +++++++++++++------------- 1 file changed, 31 insertions(+), 31 deletions(-) mode change 100644 => 100755 bin/wally-tool-chain-install-redhat.sh diff --git a/bin/wally-tool-chain-install-redhat.sh b/bin/wally-tool-chain-install-redhat.sh old mode 100644 new mode 100755 index 16f7836ff..d0994965f --- a/bin/wally-tool-chain-install-redhat.sh +++ b/bin/wally-tool-chain-install-redhat.sh @@ -81,14 +81,14 @@ ROOT=$( [ "${EUID:=$(id -u)}" = 0 ] && echo true || echo false); # All tools will be installed under the $RISCV directory. By default, if run as root (with sudo) # this is set to /opt/riscv. Otherwise, it is set to ~/riscv. This value can be changed if needed. if [ "$ROOT" = true ]; then - export RISCV=/opt/riscv + export RISCV="${1:-/opt/riscv}" else - export RISCV=~/riscv + export RISCV="${1:-$HOME/riscv}" fi export PATH=$PATH:$RISCV/bin:/usr/bin export PKG_CONFIG_PATH=$RISCV/lib64/pkgconfig:$RISCV/lib/pkgconfig:$RISCV/share/pkgconfig:$PKG_CONFIG_PATH -mkdir -p $RISCV +mkdir -p "$RISCV" echo -e "\nDetected information:" echo "Distribution: $NAME_PRETTY" @@ -131,56 +131,56 @@ echo -e "*********************************************************************** echo -e "Setting up Python Environment" echo -e "*************************************************************************" echo -e "*************************************************************************\n" -cd $RISCV -if [ ! -e $RISCV/riscv-python/bin/activate ]; then +cd "$RISCV" +if [ ! -e "$RISCV"/riscv-python/bin/activate ]; then python3.12 -m venv riscv-python fi -source $RISCV/riscv-python/bin/activate +source "$RISCV"/riscv-python/bin/activate pip install -U pip pip install -U sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown pyyaml meson testresources riscv_config pip install -U riscv_isac # to generate new tests, such as quads with fp_dataset.py if [ "$RHEL_VERSION" = 8 ]; then pip install -U z3-solver fi -source $RISCV/riscv-python/bin/activate +source "$RISCV"/riscv-python/bin/activate if [ "$RHEL_VERSION" = 8 ]; then # Other dependencies # newer versin of glib required for Qemu # anything newer than this won't build on red hat 8 - if [ ! -e $RISCV/include/glib-2.0 ]; then + if [ ! -e "$RISCV"/include/glib-2.0 ]; then echo -e "\n*************************************************************************" echo -e "*************************************************************************" echo -e "Installing glib" echo -e "*************************************************************************" echo -e "*************************************************************************\n" - cd $RISCV + cd "$RISCV" wget https://download.gnome.org/sources/glib/2.70/glib-2.70.5.tar.xz tar -xJf glib-2.70.5.tar.xz rm glib-2.70.5.tar.xz cd glib-2.70.5 - meson setup _build --prefix=$RISCV + meson setup _build --prefix="$RISCV" meson compile -C _build meson install -C _build - cd $RISCV + cd "$RISCV" rm -rf glib-2.70.5 fi # newer version of gmp needed for sail-riscv model - if [ ! -e $RISCV/include/gmp.h ]; then + if [ ! -e "$RISCV"/include/gmp.h ]; then echo -e "\n*************************************************************************" echo -e "*************************************************************************" echo -e "Installing gmp" echo -e "*************************************************************************" echo -e "*************************************************************************\n" - cd $RISCV + cd "$RISCV" wget https://ftp.gnu.org/gnu/gmp/gmp-6.3.0.tar.xz tar -xJf gmp-6.3.0.tar.xz rm gmp-6.3.0.tar.xz cd gmp-6.3.0 - ./configure --prefix=$RISCV + ./configure --prefix="$RISCV" make -j ${NUM_THREADS} make install - cd $RISCV + cd "$RISCV" rm -rf gmp-6.3.0 fi fi @@ -194,12 +194,12 @@ echo -e "*********************************************************************** echo -e "Installing RISC-V GNU Toolchain" echo -e "*************************************************************************" echo -e "*************************************************************************\n" -cd $RISCV +cd "$RISCV" if [[ ((! -e riscv-gnu-toolchain) && ($(git clone https://github.com/riscv/riscv-gnu-toolchain) || true)) || ($(cd riscv-gnu-toolchain; git fetch; git rev-parse HEAD) != $(cd riscv-gnu-toolchain; git rev-parse master)) || (! -e $RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2) ]]; then cd riscv-gnu-toolchain git checkout master git pull - ./configure --prefix=${RISCV} --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" + ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" make -j ${NUM_THREADS} fi @@ -215,13 +215,13 @@ echo -e "*********************************************************************** echo -e "Installing elf2hex" echo -e "*************************************************************************" echo -e "*************************************************************************\n" -cd $RISCV +cd "$RISCV" export PATH=$RISCV/bin:$PATH if [[ ((! -e elf2hex) && ($(git clone https://github.com/sifive/elf2hex.git) || true)) || ($(cd elf2hex; git fetch; git rev-parse HEAD) != $(cd elf2hex; git rev-parse master)) || (! -e $RISCV/bin/riscv64-unknown-elf-elf2bin) ]]; then cd elf2hex git reset --hard && git clean -f && git checkout master && git pull autoreconf -i - ./configure --target=riscv64-unknown-elf --prefix=$RISCV + ./configure --target=riscv64-unknown-elf --prefix="$RISCV" make make install fi @@ -233,11 +233,11 @@ echo -e "*********************************************************************** echo -e "Installing QEMU" echo -e "*************************************************************************" echo -e "*************************************************************************\n" -cd $RISCV +cd "$RISCV" if [[ ((! -e qemu) && ($(git clone --recurse-submodules https://github.com/qemu/qemu) || true)) || ($(cd qemu; git fetch --recurse-submodules=yes; git rev-parse HEAD) != $(cd qemu; git rev-parse master)) || (! -e $RISCV/include/qemu-plugin.h) ]]; then cd qemu git reset --hard && git clean -f && git checkout master && git pull --recurse-submodules - ./configure --target-list=riscv64-softmmu --prefix=$RISCV + ./configure --target-list=riscv64-softmmu --prefix="$RISCV" make -j ${NUM_THREADS} make install fi @@ -250,13 +250,13 @@ echo -e "*********************************************************************** echo -e "Installing SPIKE" echo -e "*************************************************************************" echo -e "*************************************************************************\n" -cd $RISCV +cd "$RISCV" if [[ ((! -e riscv-isa-sim) && ($(git clone https://github.com/riscv-software-src/riscv-isa-sim) || true)) || ($(cd riscv-isa-sim; git fetch; git rev-parse HEAD) != $(cd riscv-isa-sim; git rev-parse master)) || (! -e $RISCV/lib/pkgconfig/riscv-riscv.pc) ]]; then cd riscv-isa-sim git reset --hard && git clean -f && git checkout master && git pull mkdir -p build cd build - ../configure --prefix=$RISCV + ../configure --prefix="$RISCV" make -j ${NUM_THREADS} make install fi @@ -268,14 +268,14 @@ echo -e "*********************************************************************** echo -e "Installing Verilator" echo -e "*************************************************************************" echo -e "*************************************************************************\n" -cd $RISCV +cd "$RISCV" if [[ ((! -e verilator) && ($(git clone https://github.com/verilator/verilator) || true)) || ($(cd verilator; git fetch; git rev-parse HEAD) != $(cd verilator; git rev-parse master)) || (! -e $RISCV/share/pkgconfig/verilator.pc) ]]; then # unsetenv VERILATOR_ROOT # For csh; ignore error if on bash unset VERILATOR_ROOT # For bash cd verilator git reset --hard && git clean -f && git checkout master && git pull autoconf # Create ./configure script - ./configure --prefix=$RISCV # Configure and create Makefile + ./configure --prefix="$RISCV" # Configure and create Makefile make -j ${NUM_THREADS} # Build Verilator itself (if error, try just 'make') make install fi @@ -290,12 +290,12 @@ echo -e "*********************************************************************** echo -e "Installing Opam" echo -e "*************************************************************************" echo -e "*************************************************************************\n" -cd $RISCV +cd "$RISCV" mkdir -p opam cd opam wget https://raw.githubusercontent.com/ocaml/opam/master/shell/install.sh -printf '%s\n' $RISCV/bin Y | sh install.sh # the print command provides $RISCV/bin as the installation path when prompted -cd $RISCV +printf '%s\n' "$RISCV"/bin Y | sh install.sh # the print command provides $RISCV/bin as the installation path when prompted +cd "$RISCV" rm -rf opam echo -e "\n*************************************************************************" echo -e "*************************************************************************" @@ -320,7 +320,7 @@ if [[ ((! -e sail-riscv) && ($(git clone https://github.com/riscv/sail-riscv.git export OPAMCLI=2.0 # Sail is not compatible with opam 2.1 as of 4/16/24 ARCH=RV64 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV64 ARCH=RV32 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV32 - cd $RISCV + cd "$RISCV" ln -sf ../sail-riscv/c_emulator/riscv_sim_RV64 bin/riscv_sim_RV64 ln -sf ../sail-riscv/c_emulator/riscv_sim_RV32 bin/riscv_sim_RV32 fi @@ -339,8 +339,8 @@ echo -e "*********************************************************************** echo -e "Installing OSU Skywater 130 cell library" echo -e "*************************************************************************" echo -e "*************************************************************************\n" -mkdir -p $RISCV/cad/lib -cd $RISCV/cad/lib +mkdir -p "$RISCV"/cad/lib +cd "$RISCV"/cad/lib if [[ ((! -e sky130_osu_sc_t12) && ($(git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12) || true)) || ($(cd sky130_osu_sc_t12; git fetch; git rev-parse HEAD) != $(cd sky130_osu_sc_t12; git rev-parse master)) ]]; then cd sky130_osu_sc_t12 git reset --hard && git clean -f && git checkout main && git pull From 2862b897140b273dc0fd4dca66dada3381478a41 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 21 Jun 2024 21:18:09 -0700 Subject: [PATCH 009/219] Update ubuntu toolchain install to match new red hat form in preparation for merging of scripts. --- bin/wally-tool-chain-install.sh | 254 +++++++++++++++++++------------- 1 file changed, 149 insertions(+), 105 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index cf2ff9cce..247318fca 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -6,6 +6,7 @@ ## Created: 18 January 2023 ## Modified: 22 January 2023 ## Modified: 23 March 2023 +## Modified: 21 June 2024, Jordan Carlin jcarlin@hmc.edu ## ## Purpose: Open source tool chain installation script ## @@ -28,8 +29,17 @@ ## and limitations under the License. ################################################################################################ -# Use /opt/riscv for installation - may require running script with sudo -export RISCV="${1:-/opt/riscv}" +# Check if root +ROOT=$( [ "${EUID:=$(id -u)}" = 0 ] && echo true || echo false); + +# All tools will be installed under the $RISCV directory. By default, if run as root (with sudo) +# this is set to /opt/riscv. Otherwise, it is set to ~/riscv. This value can be changed if needed. +if [ "$ROOT" = true ]; then + export RISCV="${1:-/opt/riscv}" +else + export RISCV="${1:-$HOME/riscv}" +fi + export PATH=$PATH:$RISCV/bin:/usr/bin set -e # break on error @@ -40,23 +50,39 @@ set -e # break on error NUM_THREADS=8 # for >= 32GiB #NUM_THREADS=16 # for >= 64GiB -sudo mkdir -p $RISCV -# *** need to update permissions to local user +mkdir -p "$RISCV" +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" +echo -e "Installing Dependencies from Package Manager" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" # Update and Upgrade tools (see https://itsfoss.com/apt-update-vs-upgrade/) sudo apt update -y sudo apt upgrade -y -sudo apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev automake autotools-dev libmpc-dev libmpfr-dev gperf libtool patchutils bc mutt ssmtp -# Other python libraries used through the book. -sudo -H pip3 install sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown pyyaml -sudo -H pip3 install riscv_isac # to generate new tests, such as quads with fp_dataset.py +sudo apt install -y git gawk make texinfo bison flex build-essential python3 python3-venv libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev automake autotools-dev libmpc-dev libmpfr-dev gperf libtool patchutils bc mutt ssmtp perl g++ ccache help2man libgoogle-perftools-dev numactl perl-doc -# needed for Ubuntu 22.04, gcc cross compiler expects python not python2 or python3. -if ! command -v python &> /dev/null -then - echo "WARNING: python3 was installed as python3 rather than python. Creating symlink." - sudo ln -sf /usr/bin/python3 /usr/bin/python +# 24 +# Note, selecting 'zlib1g-dev' instead of 'libz-dev' +# Note, selecting 'libexpat1-dev' instead of 'libexpat-dev' +# Note, selecting 'libncurses-dev' instead of 'libncurses5-dev' + + +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" +echo -e "Setting up Python Environment" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" +# Other python libraries used through the book. +cd "$RISCV" +if [ ! -e "$RISCV"/riscv-python/bin/activate ]; then + python3 -m venv riscv-python fi +source "$RISCV"/riscv-python/bin/activate +pip install -U pip +pip install -U sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown pyyaml meson testresources riscv_config +pip install -U riscv_isac # to generate new tests, such as quads with fp_dataset.py +source "$RISCV"/riscv-python/bin/activate # gcc cross-compiler (https://github.com/riscv-collab/riscv-gnu-toolchain) # To install GCC from source can take hours to compile. @@ -65,11 +91,19 @@ fi # Versions newer than 2023-12-20 fail to compile the RISC-V arch test with an error: # cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/jalr-01.S:72: Error: illegal operands `la x0,5b' # PR *** submitted to fix riscv-arch-test to be compatible with latest GCC by modifying test_macros.h for TEST_JALR_OP -cd $RISCV -git clone https://github.com/riscv/riscv-gnu-toolchain -cd riscv-gnu-toolchain -./configure --prefix=${RISCV} --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" -make -j 8 +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" +echo -e "Installing RISC-V GNU Toolchain" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" +cd "$RISCV" +if [[ ((! -e riscv-gnu-toolchain) && ($(git clone https://github.com/riscv/riscv-gnu-toolchain) || true)) || ($(cd riscv-gnu-toolchain; git fetch; git rev-parse HEAD) != $(cd riscv-gnu-toolchain; git rev-parse master)) || (! -e $RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2) ]]; then + cd riscv-gnu-toolchain + git checkout master + git pull + ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" + make -j ${NUM_THREADS} +fi # elf2hex (https://github.com/sifive/elf2hex) #The elf2hex utility to converts executable files into hexadecimal files for Verilog simulation. @@ -78,51 +112,77 @@ make -j 8 # For example, if Python version 2.x is in your path, it won’t install correctly. # Also, be sure riscv64-unknown-elf-objcopy shows up in your path in $RISCV/riscv-gnu-toolchain/bin # at the time of compilation, or elf2hex won’t work properly. -cd $RISCV +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" +echo -e "Installing elf2hex" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" +cd "$RISCV" export PATH=$RISCV/bin:$PATH -git clone https://github.com/sifive/elf2hex.git -cd elf2hex -autoreconf -i -./configure --target=riscv64-unknown-elf --prefix=$RISCV -make -make install +if [[ ((! -e elf2hex) && ($(git clone https://github.com/sifive/elf2hex.git) || true)) || ($(cd elf2hex; git fetch; git rev-parse HEAD) != $(cd elf2hex; git rev-parse master)) || (! -e $RISCV/bin/riscv64-unknown-elf-elf2bin) ]]; then + cd elf2hex + git reset --hard && git clean -f && git checkout master && git pull + autoreconf -i + ./configure --target=riscv64-unknown-elf --prefix="$RISCV" + make + make install +fi # QEMU (https://www.qemu.org/docs/master/system/target-riscv.html) -cd $RISCV -git clone --recurse-submodules https://github.com/qemu/qemu -cd qemu -./configure --target-list=riscv64-softmmu --prefix=$RISCV -make -j 8 -make install +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" +echo -e "Installing QEMU" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" +cd "$RISCV" +if [[ ((! -e qemu) && ($(git clone --recurse-submodules https://github.com/qemu/qemu) || true)) || ($(cd qemu; git fetch --recurse-submodules=yes; git rev-parse HEAD) != $(cd qemu; git rev-parse master)) || (! -e $RISCV/include/qemu-plugin.h) ]]; then + cd qemu + git reset --hard && git clean -f && git checkout master && git pull --recurse-submodules + ./configure --target-list=riscv64-softmmu --prefix="$RISCV" + make -j ${NUM_THREADS} + make install +fi # Spike (https://github.com/riscv-software-src/riscv-isa-sim) -# Spike also takes a while to install and compile, but this can be done concurrently -# with the GCC installation. -cd $RISCV -git clone https://github.com/riscv-software-src/riscv-isa-sim -mkdir -p riscv-isa-sim/build -cd riscv-isa-sim/build -../configure --prefix=$RISCV -make -j 8 -make install +# Spike also takes a while to install and compile, but this can be done concurrently +# with the GCC installation. +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" +echo -e "Installing SPIKE" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" +cd "$RISCV" +if [[ ((! -e riscv-isa-sim) && ($(git clone https://github.com/riscv-software-src/riscv-isa-sim) || true)) || ($(cd riscv-isa-sim; git fetch; git rev-parse HEAD) != $(cd riscv-isa-sim; git rev-parse master)) || (! -e $RISCV/lib/pkgconfig/riscv-riscv.pc) ]]; then + cd riscv-isa-sim + git reset --hard && git clean -f && git checkout master && git pull + mkdir -p build + cd build + ../configure --prefix="$RISCV" + make -j ${NUM_THREADS} + make install +fi # Wally needs Verilator 5.021 or later. # Verilator needs to be built from scratch to get the latest version # apt-get install verilator installs version 4.028 as of 6/8/23 -sudo apt-get install -y perl g++ ccache help2man libgoogle-perftools-dev numactl perl-doc zlib1g -cd $RISCV -git clone https://github.com/verilator/verilator # Only first time -# unsetenv VERILATOR_ROOT # For csh; ignore error if on bash -unset VERILATOR_ROOT # For bash -cd verilator -git pull # Make sure git repository is up-to-date -git checkout master -autoconf # Create ./configure script -./configure # Configure and create Makefile -make -j 8 # Build Verilator itself (if error, try just 'make') -sudo make install +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" +echo -e "Installing Verilator" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" +cd "$RISCV" +if [[ ((! -e verilator) && ($(git clone https://github.com/verilator/verilator) || true)) || ($(cd verilator; git fetch; git rev-parse HEAD) != $(cd verilator; git rev-parse master)) || (! -e $RISCV/share/pkgconfig/verilator.pc) ]]; then + # unsetenv VERILATOR_ROOT # For csh; ignore error if on bash + unset VERILATOR_ROOT # For bash + cd verilator + git reset --hard && git clean -f && git checkout master && git pull + autoconf # Create ./configure script + ./configure --prefix="$RISCV" # Configure and create Makefile + make -j ${NUM_THREADS} # Build Verilator itself (if error, try just 'make') + make install +fi # Sail (https://github.com/riscv/sail-riscv) # Sail is the new golden reference model for RISC-V. Sail is written in OCaml, which @@ -130,63 +190,47 @@ sudo make install # language suited to formal verification. OCaml is installed with the opam OCcaml # package manager. Sail has so many dependencies that it can be difficult to install. # This script works for Ubuntu. - -# Alex Solomatnikov found these commands worked to build Sail for Centos 8 on 1/12/24 -#sudo su - -#dnf install ocaml.x86_64 -#pip3 install z3-solver -#wget https://raw.githubusercontent.com/ocaml/opam/master/shell/install.sh -#sh install.sh -#opam init -#exit -#ocaml -version -#opam switch create 5.1.0 -#eval $(opam config env) -#git clone --recurse-submodules git@github.com:riscv/sail-riscv.git -#cd sail-riscv -#make -#ARCH=RV32 make -#ARCH=RV64 make -#git log -1 -#cp -p c_emulator/riscv_sim_RV* /tools/sail-riscv/d7a3d8012fd579f40e53a29569141d72dd5e0c32/bin/. - - -# This was an earlier attemp to prepare to install Sail on RedHat 8 -# Do these commands only for RedHat / Rocky 8 to build from source. -#cd $RISCV -#git clone https://github.com/Z3Prover/z3.git -#cd z3 -#python scripts/mk_make.py -#cd build -#make -j 8 -#make install -#cd ../.. -#pip3 install chardet==3.0.4 -#pip3 install urllib3==1.22 - -cd $RISCV +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" +echo -e "Installing Sail Compiler" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" +cd "$RISCV" opam init -y --disable-sandboxing -opam update -opam upgrade -opam switch create 5.1.0 -opam install sail -y +opam update -y +opam upgrade -y +opam switch create 5.1.0 || opam switch set 5.1.0 +opam install sail -y eval $(opam config env) -git clone https://github.com/riscv/sail-riscv.git -cd sail-riscv -# For now, use checkout that is stable for Wally -#git checkout 72b2516d10d472ac77482fd959a9401ce3487f60 # not new enough for Zicboz? -export OPAMCLI=2.0 # Sail is not compatible with opam 2.1 as of 4/16/24 -ARCH=RV64 make -j 8 c_emulator/riscv_sim_RV64 -ARCH=RV32 make -j 8 c_emulator/riscv_sim_RV32 -sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64 -sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32 +if [[ ((! -e sail-riscv) && ($(git clone https://github.com/riscv/sail-riscv.git) || true)) || ($(cd sail-riscv; git fetch; git rev-parse HEAD) != $(cd sail-riscv; git rev-parse master)) || (! -e $RISCV/bin/riscv_sim_RV32) ]]; then + cd sail-riscv + git reset --hard && git clean -f && git checkout master && git pull + export OPAMCLI=2.0 # Sail is not compatible with opam 2.1 as of 4/16/24 + ARCH=RV64 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV64 + ARCH=RV32 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV32 + cd "$RISCV" + ln -sf ../sail-riscv/c_emulator/riscv_sim_RV64 bin/riscv_sim_RV64 + ln -sf ../sail-riscv/c_emulator/riscv_sim_RV32 bin/riscv_sim_RV32 +fi # riscof -sudo -H pip3 install -U testresources riscv_config -sudo -H pip3 install git+https://github.com/riscv/riscof.git +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" +echo -e "Installing riscof" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" +pip3 install git+https://github.com/riscv/riscof.git # Download OSU Skywater 130 cell library -sudo mkdir -p $RISCV/cad/lib -cd $RISCV/cad/lib -sudo git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12 +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" +echo -e "Installing OSU Skywater 130 cell library" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" +mkdir -p "$RISCV"/cad/lib +cd "$RISCV"/cad/lib +if [[ ((! -e sky130_osu_sc_t12) && ($(git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12) || true)) || ($(cd sky130_osu_sc_t12; git fetch; git rev-parse HEAD) != $(cd sky130_osu_sc_t12; git rev-parse master)) ]]; then + cd sky130_osu_sc_t12 + git reset --hard && git clean -f && git checkout master && git pull +fi From d785189942cb7b5e3cb2e98baa8df9ef794962fb Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 22 Jun 2024 12:18:38 -0700 Subject: [PATCH 010/219] Update install script comments and clean up packages. --- bin/wally-tool-chain-install-redhat.sh | 67 +++++++++++++++++--------- bin/wally-tool-chain-install.sh | 42 +++++++++------- 2 files changed, 68 insertions(+), 41 deletions(-) diff --git a/bin/wally-tool-chain-install-redhat.sh b/bin/wally-tool-chain-install-redhat.sh index d0994965f..01da3b1ca 100755 --- a/bin/wally-tool-chain-install-redhat.sh +++ b/bin/wally-tool-chain-install-redhat.sh @@ -78,8 +78,8 @@ fi # Check if root ROOT=$( [ "${EUID:=$(id -u)}" = 0 ] && echo true || echo false); -# All tools will be installed under the $RISCV directory. By default, if run as root (with sudo) -# this is set to /opt/riscv. Otherwise, it is set to ~/riscv. This value can be changed if needed. +# All tools will be installed under the $RISCV directory. By default, if run as root (with sudo) this is set to +# /opt/riscv. Otherwise, it is set to ~/riscv. This value can be overridden with an argument passed to the script. if [ "$ROOT" = true ]; then export RISCV="${1:-/opt/riscv}" else @@ -102,9 +102,10 @@ echo -e "Installing Dependencies from Package Manager" echo -e "*************************************************************************" echo -e "*************************************************************************\n" if [ "$FAMILY" = rhel ]; then + # Enable extra package repos sudo dnf install -y dnf-plugins-core if [ "$ID" = rhel ]; then - sudo subscription-manager repos --enable "codeready-builder-for-rhel-$RHEL_VERSION-x86_64-rpms" + sudo subscription-manager repos --enable "codeready-builder-for-rhel-$RHEL_VERSION-$(arch)-rpms" sudo dnf install -y "https://dl.fedoraproject.org/pub/epel/epel-release-latest-$RHEL_VERSION.noarch.rpm" else if [ "$RHEL_VERSION" = 8 ]; then @@ -114,16 +115,27 @@ if [ "$FAMILY" = rhel ]; then fi sudo dnf install -y epel-release fi + + # Update packages and install additional core tools sudo dnf update -y sudo dnf group install -y "Development Tools" - sudo dnf install -y git gawk make texinfo bison flex python3.12 expat-devel autoconf dtc ninja-build pixman-devel ncurses-base ncurses ncurses-libs ncurses-devel dialog curl wget ftp gmp-devel glib2-devel python3-pip pkgconfig zlib-devel automake libmpc-devel mpfr-devel gperf libtool patchutils bc mutt cmake perl gcc-c++ clang help2man numactl ocaml mold gperftools ccache - if [ "$RHEL_VERSION" = 9 ]; then - sudo dnf install -y z3 - fi - sudo dnf install -y gcc-toolset-13* - # activate gcc13 - source /opt/rh/gcc-toolset-13/enable + # Packages are grouped by which tool requires them, split by line. + # If mutltipole tools need a package, it is included in the first tool only + # General/Wally specific, riscv-gnu-toolchain, qemu, spike, verilator + sudo dnf install -y git make cmake python3.12 python3-pip curl wget ftp tar pkgconfig dialog mutt ssmtp \ + autoconf automake libmpc-devel mpfr-devel gmp-devel gawk bison flex texinfo gperf libtool patchutils bc gcc gcc-c++ zlib-devel expat-devel libslirp-devel \ + glib2-devel libfdt-devel pixman-devel bzip2 ninja-build \ + dtc boost-devel \ + help2man perl clang ccache gperftools numactl mold + # Extra packages not availale in rhel8, nice for verialtor and needed for sail respectively + if [ "$RHEL_VERSION" = 9 ]; then + sudo dnf install -y perl-doc z3 + fi + + # A newer version of gcc is required for qemu + sudo dnf install -y gcc-toolset-13* + source /opt/rh/gcc-toolset-13/enable # activate gcc13 fi echo -e "\n*************************************************************************" @@ -131,23 +143,29 @@ echo -e "*********************************************************************** echo -e "Setting up Python Environment" echo -e "*************************************************************************" echo -e "*************************************************************************\n" +# Create python virtual environment so the python command targets our desired version of python +# and installed packages are isolated from the rest of the system. cd "$RISCV" if [ ! -e "$RISCV"/riscv-python/bin/activate ]; then python3.12 -m venv riscv-python fi -source "$RISCV"/riscv-python/bin/activate +source "$RISCV"/riscv-python/bin/activate # activate python virtual environment + +# Install python packages pip install -U pip pip install -U sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown pyyaml meson testresources riscv_config pip install -U riscv_isac # to generate new tests, such as quads with fp_dataset.py + +# Needed for sail and not availabe from dnf for rhel 8 if [ "$RHEL_VERSION" = 8 ]; then pip install -U z3-solver fi -source "$RISCV"/riscv-python/bin/activate +source "$RISCV"/riscv-python/bin/activate # reload python virtual environment +# Extra dependecies needed for rhel 8 that don't have new enough versions available from dnf if [ "$RHEL_VERSION" = 8 ]; then - # Other dependencies - # newer versin of glib required for Qemu - # anything newer than this won't build on red hat 8 + # Newer versin of glib required for Qemu. + # Anything newer than this won't build on red hat 8 if [ ! -e "$RISCV"/include/glib-2.0 ]; then echo -e "\n*************************************************************************" echo -e "*************************************************************************" @@ -165,7 +183,7 @@ if [ "$RHEL_VERSION" = 8 ]; then cd "$RISCV" rm -rf glib-2.70.5 fi - # newer version of gmp needed for sail-riscv model + # Newer version of gmp needed for sail-riscv model if [ ! -e "$RISCV"/include/gmp.h ]; then echo -e "\n*************************************************************************" echo -e "*************************************************************************" @@ -280,11 +298,13 @@ if [[ ((! -e verilator) && ($(git clone https://github.com/verilator/verilator) make install fi -# Sail (https://github.com/riscv/sail-riscv) -# Sail is the golden reference model for RISC-V. Sail is written in OCaml, which -# is an object-oriented extension of ML, which in turn is a functional programming -# language suited to formal verification. OCaml is installed with the opam OCcaml -# package manager. Sail has so many dependencies that it can be difficult to install. +# RISC-V Sail Model (https://github.com/riscv/sail-riscv) +# The RISC-V Sail Model is the golden reference model for RISC-V. It is written in Sail, +# a language designed for expressing the semantics of an ISA. Sail itself is written in +# OCaml, which is an object-oriented extension of ML, which in turn is a functional programming +# language suited to formal verification. The Sail compiler is installed with the opam OCcaml +# package manager. The Sail compiler has so many dependencies that it can be difficult to install, +# but a binary release of it should be available soon, removing the need to use opam. echo -e "\n*************************************************************************" echo -e "*************************************************************************" echo -e "Installing Opam" @@ -297,6 +317,7 @@ wget https://raw.githubusercontent.com/ocaml/opam/master/shell/install.sh printf '%s\n' "$RISCV"/bin Y | sh install.sh # the print command provides $RISCV/bin as the installation path when prompted cd "$RISCV" rm -rf opam + echo -e "\n*************************************************************************" echo -e "*************************************************************************" echo -e "Installing Sail Compiler" @@ -310,11 +331,11 @@ opam install sail -y echo -e "\n*************************************************************************" echo -e "*************************************************************************" -echo -e "Installing riscv-sail Model" +echo -e "Installing RISC-V Sail Model" echo -e "*************************************************************************" echo -e "*************************************************************************\n" -eval $(opam config env) if [[ ((! -e sail-riscv) && ($(git clone https://github.com/riscv/sail-riscv.git) || true)) || ($(cd sail-riscv; git fetch; git rev-parse HEAD) != $(cd sail-riscv; git rev-parse master)) || (! -e $RISCV/bin/riscv_sim_RV32) ]]; then + eval $(opam config env) cd sail-riscv git reset --hard && git clean -f && git checkout master && git pull export OPAMCLI=2.0 # Sail is not compatible with opam 2.1 as of 4/16/24 diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 247318fca..8c5e0e4a3 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -60,13 +60,16 @@ echo -e "*********************************************************************** # Update and Upgrade tools (see https://itsfoss.com/apt-update-vs-upgrade/) sudo apt update -y sudo apt upgrade -y -sudo apt install -y git gawk make texinfo bison flex build-essential python3 python3-venv libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev automake autotools-dev libmpc-dev libmpfr-dev gperf libtool patchutils bc mutt ssmtp perl g++ ccache help2man libgoogle-perftools-dev numactl perl-doc - -# 24 -# Note, selecting 'zlib1g-dev' instead of 'libz-dev' -# Note, selecting 'libexpat1-dev' instead of 'libexpat-dev' -# Note, selecting 'libncurses-dev' instead of 'libncurses5-dev' +# Packages are grouped by which tool requires them, split by line. +# If mutltipole tools need a package, it is included in the first tool only +# General/Wally specific, riscv-gnu-toolchain, qemu, spike, verilator, sail +sudo apt install -y git make cmake python3 python3-pip python3-venv curl wget ftp tar pkg-config dialog mutt ssmtp \ + autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat1-dev ninja-build libglib2.0-dev libslirp-dev \ + libfdt-dev libpixman-1-dev \ + device-tree-compiler libboost-regex-dev libboost-system-dev \ + help2man perl g++ clang ccache libgoogle-perftools-dev numactl mold perl-doc libfl2 libfl-dev zlib1g \ + opam z3 echo -e "\n*************************************************************************" echo -e "*************************************************************************" @@ -80,7 +83,7 @@ if [ ! -e "$RISCV"/riscv-python/bin/activate ]; then fi source "$RISCV"/riscv-python/bin/activate pip install -U pip -pip install -U sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown pyyaml meson testresources riscv_config +pip install -U sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown pyyaml testresources riscv_config pip install -U riscv_isac # to generate new tests, such as quads with fp_dataset.py source "$RISCV"/riscv-python/bin/activate @@ -88,9 +91,6 @@ source "$RISCV"/riscv-python/bin/activate # To install GCC from source can take hours to compile. # This configuration enables multilib to target many flavors of RISC-V. # This book is tested with GCC 13.2.0 -# Versions newer than 2023-12-20 fail to compile the RISC-V arch test with an error: -# cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/jalr-01.S:72: Error: illegal operands `la x0,5b' -# PR *** submitted to fix riscv-arch-test to be compatible with latest GCC by modifying test_macros.h for TEST_JALR_OP echo -e "\n*************************************************************************" echo -e "*************************************************************************" echo -e "Installing RISC-V GNU Toolchain" @@ -184,12 +184,13 @@ if [[ ((! -e verilator) && ($(git clone https://github.com/verilator/verilator) make install fi -# Sail (https://github.com/riscv/sail-riscv) -# Sail is the new golden reference model for RISC-V. Sail is written in OCaml, which -# is an object-oriented extension of ML, which in turn is a functional programming -# language suited to formal verification. OCaml is installed with the opam OCcaml -# package manager. Sail has so many dependencies that it can be difficult to install. -# This script works for Ubuntu. +# RISC-V Sail Model (https://github.com/riscv/sail-riscv) +# The RISC-V Sail Model is the golden reference model for RISC-V. It is written in Sail, +# a language designed for expressing the semantics of an ISA. Sail itself is written in +# OCaml, which is an object-oriented extension of ML, which in turn is a functional programming +# language suited to formal verification. The Sail compiler is installed with the opam OCcaml +# package manager. The Sail compiler has so many dependencies that it can be difficult to install, +# but a binary release of it should be available soon, removing the need to use opam. echo -e "\n*************************************************************************" echo -e "*************************************************************************" echo -e "Installing Sail Compiler" @@ -202,8 +203,13 @@ opam upgrade -y opam switch create 5.1.0 || opam switch set 5.1.0 opam install sail -y -eval $(opam config env) +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" +echo -e "Installing RISC-V Sail Model" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" if [[ ((! -e sail-riscv) && ($(git clone https://github.com/riscv/sail-riscv.git) || true)) || ($(cd sail-riscv; git fetch; git rev-parse HEAD) != $(cd sail-riscv; git rev-parse master)) || (! -e $RISCV/bin/riscv_sim_RV32) ]]; then + eval $(opam config env) cd sail-riscv git reset --hard && git clean -f && git checkout master && git pull export OPAMCLI=2.0 # Sail is not compatible with opam 2.1 as of 4/16/24 @@ -232,5 +238,5 @@ mkdir -p "$RISCV"/cad/lib cd "$RISCV"/cad/lib if [[ ((! -e sky130_osu_sc_t12) && ($(git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12) || true)) || ($(cd sky130_osu_sc_t12; git fetch; git rev-parse HEAD) != $(cd sky130_osu_sc_t12; git rev-parse master)) ]]; then cd sky130_osu_sc_t12 - git reset --hard && git clean -f && git checkout master && git pull + git reset --hard && git clean -f && git checkout main && git pull fi From f1b2e6a8dea0aa52adfb2771c4b54e3a65ec9727 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 22 Jun 2024 13:05:29 -0700 Subject: [PATCH 011/219] Initial attempt at unified script --- bin/wally-tool-chain-install-unified.sh | 390 ++++++++++++++++++++++++ 1 file changed, 390 insertions(+) create mode 100755 bin/wally-tool-chain-install-unified.sh diff --git a/bin/wally-tool-chain-install-unified.sh b/bin/wally-tool-chain-install-unified.sh new file mode 100755 index 000000000..d231c28d3 --- /dev/null +++ b/bin/wally-tool-chain-install-unified.sh @@ -0,0 +1,390 @@ +#!/bin/bash +########################################### +## Tool chain install script. +## +## Written: Ross Thompson ross1728@gmail.com +## Created: 18 January 2023 +## Modified: 22 January 2023 +## Modified: 23 March 2023 +## Modified for Red Hat: June 20 2024, Jordan Carlin jcarlin@hmc.edu +## +## Purpose: Open source tool chain installation script +## +## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https:##solderpad.org/licenses/SHL-2.1/ +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ + +# MODIFY FOR YOUR MACHINE +# Increasing NUM_THREADS will speed up parallel compilation of the tools +#NUM_THREADS=2 # for low memory machines > 16GiB +NUM_THREADS=8 # for >= 32GiB +#NUM_THREADS=16 # for >= 64GiB + +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" +echo -e "Checking Distro and Permissions and Setting Installation Directory" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" + +set -e # break on error + +# Get distribution information +test -e /etc/os-release && os_release="/etc/os-release" || os_release="/usr/lib/os-release" +source "$os_release" + +# Check for compatible distro +if [[ "$ID" = rhel || "$ID_LIKE" = *rhel* ]]; then + FAMILY=rhel + if [ "$ID" != rhel ] && [ "$ID" != rocky ]; then + echo "For Red Hat family distros, the Wally install script has only been tested on RHEL and Rocky Linux. Your distro \ +is $PRETTY_NAME. The regular Red Hat install will be attempted, but there will likely be issues." + fi + if [ "${VERSION_ID:0:1}" = 8 ]; then + RHEL_VERSION=8 + elif [ "${VERSION_ID:0:1}" = 9 ]; then + RHEL_VERSION=9 + else + echo "The Wally install script is only compatible with versions 8 and 9 of RHEL and Rocky Linux. You have version $VERSION." + exit 1 + fi +elif [[ "$ID" = ubuntu || "$ID_LIKE" = *ubuntu* ]]; then + FAMILY=ubuntu + if [ "$ID" != ubuntu ]; then + echo "For Ubuntu family distros, the Wally install script has only been tested on standard Ubuntu. Your distro \ +is $PRETTY_NAME. The regular Ubuntu install will be attempted, but there may be issues." + fi +else + echo "The Wally install script is currently only compatible with Ubuntu and Red Hat family \ +(RHEL or Rocky Linux) distros. Your detected distro is $ID. You may try manually running the \ +commands in this script, but it is likely that some will need to be altered." + exit 1 +fi + +# Check if root +ROOT=$( [ "${EUID:=$(id -u)}" = 0 ] && echo true || echo false); + +# All tools will be installed under the $RISCV directory. By default, if run as root (with sudo) this is set to +# /opt/riscv. Otherwise, it is set to ~/riscv. This value can be overridden with an argument passed to the script. +if [ "$ROOT" = true ]; then + export RISCV="${1:-/opt/riscv}" +else + export RISCV="${1:-$HOME/riscv}" +fi + +export PATH=$PATH:$RISCV/bin:/usr/bin +export PKG_CONFIG_PATH=$RISCV/lib64/pkgconfig:$RISCV/lib/pkgconfig:$RISCV/share/pkgconfig:$PKG_CONFIG_PATH +mkdir -p "$RISCV" + +echo -e "\nDetected information:" +echo "Distribution: $NAME_PRETTY" +echo "Version: $VERSION_PRETTY" +echo "Running as root: $ROOT" +echo "Installation path: $RISCV" + +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" +echo -e "Installing Dependencies from Package Manager" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" +# Installs appropriate packages for rhel or ubuntu distros, picking apt or dnf appropriately +if [ "$FAMILY" = rhel ]; then + # Enable extra package repos + sudo dnf install -y dnf-plugins-core + if [ "$ID" = rhel ]; then + sudo subscription-manager repos --enable "codeready-builder-for-rhel-$RHEL_VERSION-$(arch)-rpms" + sudo dnf install -y "https://dl.fedoraproject.org/pub/epel/epel-release-latest-$RHEL_VERSION.noarch.rpm" + else + if [ "$RHEL_VERSION" = 8 ]; then + sudo dnf config-manager -y --set-enabled powertools + else # Version 9 + sudo dnf config-manager -y --set-enabled crb + fi + sudo dnf install -y epel-release + fi + + # Update packages and install additional core tools + sudo dnf update -y + sudo dnf group install -y "Development Tools" + + # Packages are grouped by which tool requires them, split by line. + # If mutltipole tools need a package, it is included in the first tool only + # General/Wally specific, riscv-gnu-toolchain, qemu, spike, verilator + sudo dnf install -y git make cmake python3.12 python3-pip curl wget ftp tar pkgconfig dialog mutt ssmtp \ + autoconf automake libmpc-devel mpfr-devel gmp-devel gawk bison flex texinfo gperf libtool patchutils bc gcc gcc-c++ zlib-devel expat-devel libslirp-devel \ + glib2-devel libfdt-devel pixman-devel bzip2 ninja-build \ + dtc boost-devel \ + help2man perl clang ccache gperftools numactl mold + # Extra packages not availale in rhel8, nice for verialtor and needed for sail respectively + if [ "$RHEL_VERSION" = 9 ]; then + sudo dnf install -y perl-doc z3 + fi + + # A newer version of gcc is required for qemu + sudo dnf install -y gcc-toolset-13* + source /opt/rh/gcc-toolset-13/enable # activate gcc13 +elif [ "$FAMILY" = ubuntu ]; then + # Update and Upgrade tools (see https://itsfoss.com/apt-update-vs-upgrade/) + sudo apt update -y + sudo apt upgrade -y + + # Packages are grouped by which tool requires them, split by line. + # If mutltipole tools need a package, it is included in the first tool only + # General/Wally specific, riscv-gnu-toolchain, qemu, spike, verilator, sail + sudo apt install -y git make cmake python3 python3-pip python3-venv curl wget ftp tar pkg-config dialog mutt ssmtp \ + autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat1-dev ninja-build libglib2.0-dev libslirp-dev \ + libfdt-dev libpixman-1-dev \ + device-tree-compiler libboost-regex-dev libboost-system-dev \ + help2man perl g++ clang ccache libgoogle-perftools-dev numactl mold perl-doc libfl2 libfl-dev zlib1g \ + opam z3 +fi + +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" +echo -e "Setting up Python Environment" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" +# Create python virtual environment so the python command targets our desired version of python +# and installed packages are isolated from the rest of the system. +cd "$RISCV" +if [ ! -e "$RISCV"/riscv-python/bin/activate ]; then + # If python3.12 is avaiable, use it. Otherise, use whatever version of python3 is installed. + if [ "$(which python3.12)" ]; then + python3.12 -m venv riscv-python + else + python3 -m venv riscv-python + fi +fi +source "$RISCV"/riscv-python/bin/activate # activate python virtual environment + +# Install python packages +pip install -U pip +pip install -U sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown pyyaml testresources riscv_config +pip install -U riscv_isac # to generate new tests, such as quads with fp_dataset.py + +# z3 is eeded for sail and not availabe from dnf for rhel 8. Meson is needed to build extra dependencies +if [ "$RHEL_VERSION" = 8 ]; then + pip install -U z3-solver meson +fi +source "$RISCV"/riscv-python/bin/activate # reload python virtual environment + +# Extra dependecies needed for rhel 8 that don't have new enough versions available from dnf +if [ "$RHEL_VERSION" = 8 ]; then + # Newer versin of glib required for Qemu. + # Anything newer than this won't build on red hat 8 + if [ ! -e "$RISCV"/include/glib-2.0 ]; then + echo -e "\n*************************************************************************" + echo -e "*************************************************************************" + echo -e "Installing glib" + echo -e "*************************************************************************" + echo -e "*************************************************************************\n" + cd "$RISCV" + wget https://download.gnome.org/sources/glib/2.70/glib-2.70.5.tar.xz + tar -xJf glib-2.70.5.tar.xz + rm glib-2.70.5.tar.xz + cd glib-2.70.5 + meson setup _build --prefix="$RISCV" + meson compile -C _build + meson install -C _build + cd "$RISCV" + rm -rf glib-2.70.5 + fi + # Newer version of gmp needed for sail-riscv model + if [ ! -e "$RISCV"/include/gmp.h ]; then + echo -e "\n*************************************************************************" + echo -e "*************************************************************************" + echo -e "Installing gmp" + echo -e "*************************************************************************" + echo -e "*************************************************************************\n" + cd "$RISCV" + wget https://ftp.gnu.org/gnu/gmp/gmp-6.3.0.tar.xz + tar -xJf gmp-6.3.0.tar.xz + rm gmp-6.3.0.tar.xz + cd gmp-6.3.0 + ./configure --prefix="$RISCV" + make -j ${NUM_THREADS} + make install + cd "$RISCV" + rm -rf gmp-6.3.0 + fi +fi + +# gcc cross-compiler (https://github.com/riscv-collab/riscv-gnu-toolchain) +# To install GCC from source can take hours to compile. +# This configuration enables multilib to target many flavors of RISC-V. +# This book is tested with GCC 13.2.0 +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" +echo -e "Installing RISC-V GNU Toolchain" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" +cd "$RISCV" +if [[ ((! -e riscv-gnu-toolchain) && ($(git clone https://github.com/riscv/riscv-gnu-toolchain) || true)) || ($(cd riscv-gnu-toolchain; git fetch; git rev-parse HEAD) != $(cd riscv-gnu-toolchain; git rev-parse master)) || (! -e $RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2) ]]; then + cd riscv-gnu-toolchain + git checkout master + git pull + ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" + make -j ${NUM_THREADS} +fi + +# elf2hex (https://github.com/sifive/elf2hex) +#The elf2hex utility to converts executable files into hexadecimal files for Verilog simulation. +# Note: The exe2hex utility that comes with Spike doesn’t work for our purposes because it doesn’t +# handle programs that start at 0x80000000. The SiFive version above is touchy to install. +# For example, if Python version 2.x is in your path, it won’t install correctly. +# Also, be sure riscv64-unknown-elf-objcopy shows up in your path in $RISCV/riscv-gnu-toolchain/bin +# at the time of compilation, or elf2hex won’t work properly. +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" +echo -e "Installing elf2hex" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" +cd "$RISCV" +export PATH=$RISCV/bin:$PATH +if [[ ((! -e elf2hex) && ($(git clone https://github.com/sifive/elf2hex.git) || true)) || ($(cd elf2hex; git fetch; git rev-parse HEAD) != $(cd elf2hex; git rev-parse master)) || (! -e $RISCV/bin/riscv64-unknown-elf-elf2bin) ]]; then + cd elf2hex + git reset --hard && git clean -f && git checkout master && git pull + autoreconf -i + ./configure --target=riscv64-unknown-elf --prefix="$RISCV" + make + make install +fi + +# QEMU (https://www.qemu.org/docs/master/system/target-riscv.html) +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" +echo -e "Installing QEMU" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" +cd "$RISCV" +if [[ ((! -e qemu) && ($(git clone --recurse-submodules https://github.com/qemu/qemu) || true)) || ($(cd qemu; git fetch --recurse-submodules=yes; git rev-parse HEAD) != $(cd qemu; git rev-parse master)) || (! -e $RISCV/include/qemu-plugin.h) ]]; then + cd qemu + git reset --hard && git clean -f && git checkout master && git pull --recurse-submodules + ./configure --target-list=riscv64-softmmu --prefix="$RISCV" + make -j ${NUM_THREADS} + make install +fi + +# Spike (https://github.com/riscv-software-src/riscv-isa-sim) +# Spike also takes a while to install and compile, but this can be done concurrently +# with the GCC installation. +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" +echo -e "Installing SPIKE" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" +cd "$RISCV" +if [[ ((! -e riscv-isa-sim) && ($(git clone https://github.com/riscv-software-src/riscv-isa-sim) || true)) || ($(cd riscv-isa-sim; git fetch; git rev-parse HEAD) != $(cd riscv-isa-sim; git rev-parse master)) || (! -e $RISCV/lib/pkgconfig/riscv-riscv.pc) ]]; then + cd riscv-isa-sim + git reset --hard && git clean -f && git checkout master && git pull + mkdir -p build + cd build + ../configure --prefix="$RISCV" + make -j ${NUM_THREADS} + make install +fi + +# Wally needs Verilator 5.021 or later. +# Verilator needs to be built from source to get the latest version +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" +echo -e "Installing Verilator" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" +cd "$RISCV" +if [[ ((! -e verilator) && ($(git clone https://github.com/verilator/verilator) || true)) || ($(cd verilator; git fetch; git rev-parse HEAD) != $(cd verilator; git rev-parse master)) || (! -e $RISCV/share/pkgconfig/verilator.pc) ]]; then + # unsetenv VERILATOR_ROOT # For csh; ignore error if on bash + unset VERILATOR_ROOT # For bash + cd verilator + git reset --hard && git clean -f && git checkout master && git pull + autoconf # Create ./configure script + ./configure --prefix="$RISCV" # Configure and create Makefile + make -j ${NUM_THREADS} # Build Verilator itself (if error, try just 'make') + make install +fi + +# RISC-V Sail Model (https://github.com/riscv/sail-riscv) +# The RISC-V Sail Model is the golden reference model for RISC-V. It is written in Sail, +# a language designed for expressing the semantics of an ISA. Sail itself is written in +# OCaml, which is an object-oriented extension of ML, which in turn is a functional programming +# language suited to formal verification. The Sail compiler is installed with the opam OCcaml +# package manager. The Sail compiler has so many dependencies that it can be difficult to install, +# but a binary release of it should be available soon, removing the need to use opam. +cd "$RISCV" +if [ "$FAMILY" = rhel ]; then + echo -e "\n*************************************************************************" + echo -e "*************************************************************************" + echo -e "Installing Opam" + echo -e "*************************************************************************" + echo -e "*************************************************************************\n" + mkdir -p opam + cd opam + wget https://raw.githubusercontent.com/ocaml/opam/master/shell/install.sh + printf '%s\n' "$RISCV"/bin Y | sh install.sh # the print command provides $RISCV/bin as the installation path when prompted + cd "$RISCV" + rm -rf opam +fi + +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" +echo -e "Installing Sail Compiler" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" +cd "$RISCV" +opam init -y --disable-sandboxing +opam update -y +opam upgrade -y +opam switch create 5.1.0 || opam switch set 5.1.0 +opam install sail -y + +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" +echo -e "Installing RISC-V Sail Model" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" +if [[ ((! -e sail-riscv) && ($(git clone https://github.com/riscv/sail-riscv.git) || true)) || ($(cd sail-riscv; git fetch; git rev-parse HEAD) != $(cd sail-riscv; git rev-parse master)) || (! -e $RISCV/bin/riscv_sim_RV32) ]]; then + eval $(opam config env) + cd sail-riscv + git reset --hard && git clean -f && git checkout master && git pull + export OPAMCLI=2.0 # Sail is not compatible with opam 2.1 as of 4/16/24 + ARCH=RV64 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV64 + ARCH=RV32 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV32 + cd "$RISCV" + ln -sf ../sail-riscv/c_emulator/riscv_sim_RV64 bin/riscv_sim_RV64 + ln -sf ../sail-riscv/c_emulator/riscv_sim_RV32 bin/riscv_sim_RV32 +fi + +# riscof +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" +echo -e "Installing riscof" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" +pip3 install git+https://github.com/riscv/riscof.git + +# Download OSU Skywater 130 cell library +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" +echo -e "Installing OSU Skywater 130 cell library" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" +mkdir -p "$RISCV"/cad/lib +cd "$RISCV"/cad/lib +if [[ ((! -e sky130_osu_sc_t12) && ($(git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12) || true)) || ($(cd sky130_osu_sc_t12; git fetch; git rev-parse HEAD) != $(cd sky130_osu_sc_t12; git rev-parse master)) ]]; then + cd sky130_osu_sc_t12 + git reset --hard && git clean -f && git checkout main && git pull +fi From ba25bf8c16b4f191a1b9b3d803311b46da0458c7 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 22 Jun 2024 16:05:20 -0700 Subject: [PATCH 012/219] Fix environment variables --- bin/wally-tool-chain-install-redhat.sh | 4 ++-- bin/wally-tool-chain-install-unified.sh | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/bin/wally-tool-chain-install-redhat.sh b/bin/wally-tool-chain-install-redhat.sh index 01da3b1ca..1a5b53579 100755 --- a/bin/wally-tool-chain-install-redhat.sh +++ b/bin/wally-tool-chain-install-redhat.sh @@ -91,8 +91,8 @@ export PKG_CONFIG_PATH=$RISCV/lib64/pkgconfig:$RISCV/lib/pkgconfig:$RISCV/share/ mkdir -p "$RISCV" echo -e "\nDetected information:" -echo "Distribution: $NAME_PRETTY" -echo "Version: $VERSION_PRETTY" +echo "Distribution: $PRETTY_NAME" +echo "Version: $VERSION" echo "Running as root: $ROOT" echo "Installation path: $RISCV" diff --git a/bin/wally-tool-chain-install-unified.sh b/bin/wally-tool-chain-install-unified.sh index d231c28d3..916077532 100755 --- a/bin/wally-tool-chain-install-unified.sh +++ b/bin/wally-tool-chain-install-unified.sh @@ -90,9 +90,9 @@ export PATH=$PATH:$RISCV/bin:/usr/bin export PKG_CONFIG_PATH=$RISCV/lib64/pkgconfig:$RISCV/lib/pkgconfig:$RISCV/share/pkgconfig:$PKG_CONFIG_PATH mkdir -p "$RISCV" -echo -e "\nDetected information:" -echo "Distribution: $NAME_PRETTY" -echo "Version: $VERSION_PRETTY" +echo -e "\nDetected information" +echo "Distribution: $PRETTY_NAME" +echo "Version: $VERSION" echo "Running as root: $ROOT" echo "Installation path: $RISCV" From 2134a3cafb609c8548d1a177f188fc32105dc823 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 22 Jun 2024 17:46:29 -0700 Subject: [PATCH 013/219] Update red hat packages --- bin/wally-tool-chain-install-redhat.sh | 2 +- bin/wally-tool-chain-install-unified.sh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/bin/wally-tool-chain-install-redhat.sh b/bin/wally-tool-chain-install-redhat.sh index 1a5b53579..547182f64 100755 --- a/bin/wally-tool-chain-install-redhat.sh +++ b/bin/wally-tool-chain-install-redhat.sh @@ -126,7 +126,7 @@ if [ "$FAMILY" = rhel ]; then sudo dnf install -y git make cmake python3.12 python3-pip curl wget ftp tar pkgconfig dialog mutt ssmtp \ autoconf automake libmpc-devel mpfr-devel gmp-devel gawk bison flex texinfo gperf libtool patchutils bc gcc gcc-c++ zlib-devel expat-devel libslirp-devel \ glib2-devel libfdt-devel pixman-devel bzip2 ninja-build \ - dtc boost-devel \ + dtc boost-regex boost-system \ help2man perl clang ccache gperftools numactl mold # Extra packages not availale in rhel8, nice for verialtor and needed for sail respectively if [ "$RHEL_VERSION" = 9 ]; then diff --git a/bin/wally-tool-chain-install-unified.sh b/bin/wally-tool-chain-install-unified.sh index 916077532..002e2e662 100755 --- a/bin/wally-tool-chain-install-unified.sh +++ b/bin/wally-tool-chain-install-unified.sh @@ -127,7 +127,7 @@ if [ "$FAMILY" = rhel ]; then sudo dnf install -y git make cmake python3.12 python3-pip curl wget ftp tar pkgconfig dialog mutt ssmtp \ autoconf automake libmpc-devel mpfr-devel gmp-devel gawk bison flex texinfo gperf libtool patchutils bc gcc gcc-c++ zlib-devel expat-devel libslirp-devel \ glib2-devel libfdt-devel pixman-devel bzip2 ninja-build \ - dtc boost-devel \ + dtc boost-regex boost-system \ help2man perl clang ccache gperftools numactl mold # Extra packages not availale in rhel8, nice for verialtor and needed for sail respectively if [ "$RHEL_VERSION" = 9 ]; then From 0c93e17fc2180e20caade25986fba021c6d19ab4 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 28 Jun 2024 13:24:19 -0700 Subject: [PATCH 014/219] Correct detection of remote changes --- bin/wally-tool-chain-install-unified.sh | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/bin/wally-tool-chain-install-unified.sh b/bin/wally-tool-chain-install-unified.sh index 002e2e662..5815fea25 100755 --- a/bin/wally-tool-chain-install-unified.sh +++ b/bin/wally-tool-chain-install-unified.sh @@ -233,7 +233,7 @@ echo -e "Installing RISC-V GNU Toolchain" echo -e "*************************************************************************" echo -e "*************************************************************************\n" cd "$RISCV" -if [[ ((! -e riscv-gnu-toolchain) && ($(git clone https://github.com/riscv/riscv-gnu-toolchain) || true)) || ($(cd riscv-gnu-toolchain; git fetch; git rev-parse HEAD) != $(cd riscv-gnu-toolchain; git rev-parse master)) || (! -e $RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2) ]]; then +if [[ ((! -e riscv-gnu-toolchain) && ($(git clone https://github.com/riscv/riscv-gnu-toolchain) || true)) || ($(cd riscv-gnu-toolchain; git fetch; git rev-parse HEAD) != $(cd riscv-gnu-toolchain; git rev-parse origin/master)) || (! -e $RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2) ]]; then cd riscv-gnu-toolchain git checkout master git pull @@ -255,7 +255,7 @@ echo -e "*********************************************************************** echo -e "*************************************************************************\n" cd "$RISCV" export PATH=$RISCV/bin:$PATH -if [[ ((! -e elf2hex) && ($(git clone https://github.com/sifive/elf2hex.git) || true)) || ($(cd elf2hex; git fetch; git rev-parse HEAD) != $(cd elf2hex; git rev-parse master)) || (! -e $RISCV/bin/riscv64-unknown-elf-elf2bin) ]]; then +if [[ ((! -e elf2hex) && ($(git clone https://github.com/sifive/elf2hex.git) || true)) || ($(cd elf2hex; git fetch; git rev-parse HEAD) != $(cd elf2hex; git rev-parse origin/master)) || (! -e $RISCV/bin/riscv64-unknown-elf-elf2bin) ]]; then cd elf2hex git reset --hard && git clean -f && git checkout master && git pull autoreconf -i @@ -271,7 +271,7 @@ echo -e "Installing QEMU" echo -e "*************************************************************************" echo -e "*************************************************************************\n" cd "$RISCV" -if [[ ((! -e qemu) && ($(git clone --recurse-submodules https://github.com/qemu/qemu) || true)) || ($(cd qemu; git fetch --recurse-submodules=yes; git rev-parse HEAD) != $(cd qemu; git rev-parse master)) || (! -e $RISCV/include/qemu-plugin.h) ]]; then +if [[ ((! -e qemu) && ($(git clone --recurse-submodules https://github.com/qemu/qemu) || true)) || ($(cd qemu; git fetch --recurse-submodules=yes; git rev-parse HEAD) != $(cd qemu; git rev-parse origin/master)) || (! -e $RISCV/include/qemu-plugin.h) ]]; then cd qemu git reset --hard && git clean -f && git checkout master && git pull --recurse-submodules ./configure --target-list=riscv64-softmmu --prefix="$RISCV" @@ -288,7 +288,7 @@ echo -e "Installing SPIKE" echo -e "*************************************************************************" echo -e "*************************************************************************\n" cd "$RISCV" -if [[ ((! -e riscv-isa-sim) && ($(git clone https://github.com/riscv-software-src/riscv-isa-sim) || true)) || ($(cd riscv-isa-sim; git fetch; git rev-parse HEAD) != $(cd riscv-isa-sim; git rev-parse master)) || (! -e $RISCV/lib/pkgconfig/riscv-riscv.pc) ]]; then +if [[ ((! -e riscv-isa-sim) && ($(git clone https://github.com/riscv-software-src/riscv-isa-sim) || true)) || ($(cd riscv-isa-sim; git fetch; git rev-parse HEAD) != $(cd riscv-isa-sim; git rev-parse origin/master)) || (! -e $RISCV/lib/pkgconfig/riscv-riscv.pc) ]]; then cd riscv-isa-sim git reset --hard && git clean -f && git checkout master && git pull mkdir -p build @@ -306,7 +306,7 @@ echo -e "Installing Verilator" echo -e "*************************************************************************" echo -e "*************************************************************************\n" cd "$RISCV" -if [[ ((! -e verilator) && ($(git clone https://github.com/verilator/verilator) || true)) || ($(cd verilator; git fetch; git rev-parse HEAD) != $(cd verilator; git rev-parse master)) || (! -e $RISCV/share/pkgconfig/verilator.pc) ]]; then +if [[ ((! -e verilator) && ($(git clone https://github.com/verilator/verilator) || true)) || ($(cd verilator; git fetch; git rev-parse HEAD) != $(cd verilator; git rev-parse origin/master)) || (! -e $RISCV/share/pkgconfig/verilator.pc) ]]; then # unsetenv VERILATOR_ROOT # For csh; ignore error if on bash unset VERILATOR_ROOT # For bash cd verilator @@ -356,7 +356,7 @@ echo -e "*********************************************************************** echo -e "Installing RISC-V Sail Model" echo -e "*************************************************************************" echo -e "*************************************************************************\n" -if [[ ((! -e sail-riscv) && ($(git clone https://github.com/riscv/sail-riscv.git) || true)) || ($(cd sail-riscv; git fetch; git rev-parse HEAD) != $(cd sail-riscv; git rev-parse master)) || (! -e $RISCV/bin/riscv_sim_RV32) ]]; then +if [[ ((! -e sail-riscv) && ($(git clone https://github.com/riscv/sail-riscv.git) || true)) || ($(cd sail-riscv; git fetch; git rev-parse HEAD) != $(cd sail-riscv; git rev-parse origin/master)) || (! -e $RISCV/bin/riscv_sim_RV32) ]]; then eval $(opam config env) cd sail-riscv git reset --hard && git clean -f && git checkout master && git pull @@ -384,7 +384,7 @@ echo -e "*********************************************************************** echo -e "*************************************************************************\n" mkdir -p "$RISCV"/cad/lib cd "$RISCV"/cad/lib -if [[ ((! -e sky130_osu_sc_t12) && ($(git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12) || true)) || ($(cd sky130_osu_sc_t12; git fetch; git rev-parse HEAD) != $(cd sky130_osu_sc_t12; git rev-parse master)) ]]; then +if [[ ((! -e sky130_osu_sc_t12) && ($(git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12) || true)) || ($(cd sky130_osu_sc_t12; git fetch; git rev-parse HEAD) != $(cd sky130_osu_sc_t12; git rev-parse origin/main)) ]]; then cd sky130_osu_sc_t12 git reset --hard && git clean -f && git checkout main && git pull fi From d6644a743c8d522fd0437231ea20707badf9ce15 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 28 Jun 2024 15:02:16 -0700 Subject: [PATCH 015/219] Update setup scripts and automatically copy site-setup to $RISCV --- bin/wally-tool-chain-install-unified.sh | 19 +++++++++++++++++-- setup.sh | 25 ++++++++++++++----------- site-setup.sh | 21 +++++++++++---------- 3 files changed, 42 insertions(+), 23 deletions(-) diff --git a/bin/wally-tool-chain-install-unified.sh b/bin/wally-tool-chain-install-unified.sh index bbaa39a73..9a41af59a 100755 --- a/bin/wally-tool-chain-install-unified.sh +++ b/bin/wally-tool-chain-install-unified.sh @@ -70,7 +70,7 @@ is $PRETTY_NAME. The regular Ubuntu install will be attempted, but there may be fi else echo "The Wally install script is currently only compatible with Ubuntu and Red Hat family \ -(RHEL or Rocky Linux) distros. Your detected distro is $ID. You may try manually running the \ +(RHEL or Rocky Linux) distros. Your detected distro is $PRETTY_NAME. You may try manually running the \ commands in this script, but it is likely that some will need to be altered." exit 1 fi @@ -371,7 +371,7 @@ fi # riscof echo -e "\n*************************************************************************" echo -e "*************************************************************************" -echo -e "Installing riscof" +echo -e "Installing Riscof" echo -e "*************************************************************************" echo -e "*************************************************************************\n" pip3 install git+https://github.com/riscv/riscof.git @@ -388,3 +388,18 @@ if [[ ((! -e sky130_osu_sc_t12) && ($(git clone https://foss-eda-tools.googlesou cd sky130_osu_sc_t12 git reset --hard && git clean -f && git checkout main && git pull fi + +# site-setup script +echo -e "\n*************************************************************************" +echo -e "*************************************************************************" +echo -e "Downloading Site Setup Script" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n" +cd "$RISCV" +if [ ! -e "${RISCV}"/site-setup.sh ]; then + wget https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.sh + wget https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.csh + if [ "$FAMILY" = rhel ]; then + echo "source /opt/rh/gcc-toolset-13/enable" >> site-setup.sh + fi +fi \ No newline at end of file diff --git a/setup.sh b/setup.sh index 656fed5a6..3531b2bce 100644 --- a/setup.sh +++ b/setup.sh @@ -14,23 +14,26 @@ echo "Executing Wally setup.sh" # Path to RISC-V Tools -export RISCV=/opt/riscv # change this if you installed the tools in a different location +if [ -e /opt/riscv ]; then + export RISCV=/opt/riscv +elif [ -e ~/riscv ]; then + export RISCV=~/riscv +else + # set the $RISCV directory here and remove the subsequent two lines + # export RISCV= + echo "\$RISCV directory not found. Checked /opt/riscv and ~/riscv. Edit setup.sh to point to your custom \$RISCV directory." + exit 1; +fi +echo \$RISCV set to "${RISCV}" # Path to Wally repository -WALLY=$(dirname ${BASH_SOURCE[0]:-$0}) +WALLY=$(dirname "${BASH_SOURCE[0]:-$0}") export WALLY=$(cd "$WALLY" && pwd) -echo \$WALLY set to ${WALLY} +echo \$WALLY set to "${WALLY}" # utility functions in Wally repository export PATH=$WALLY/bin:$PATH -# Verilator needs a larger stack to simulate CORE-V Wally -ulimit -c 234613 - # load site licenses and tool locations -if [ -f ${RISCV}/site-setup.sh ]; then - source ${RISCV}/site-setup.sh -else - source ${WALLY}/site-setup.sh -fi +source "${RISCV}"/site-setup.sh echo "setup done" diff --git a/site-setup.sh b/site-setup.sh index acda541aa..dbbd2775c 100755 --- a/site-setup.sh +++ b/site-setup.sh @@ -20,19 +20,22 @@ export VCS_HOME=/cad/synopsys/vcs/U-2023.03-SP2-4 # Change thi export PATH=$QUESTA_HOME/bin:$DC_HOME/bin:$VCS_HOME/bin:$PATH # GCC -export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib +export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RISCV/riscv64-unknown-elf/lib -# Spike -export LD_LIBRARY_PATH=$RISCV/lib:$LD_LIBRARY_PATH +# RISC-V Tools +export LD_LIBRARY_PATH=$RISCV/lib:$RISCV/lib64:$LD_LIBRARY_PATH export PATH=$PATH:$RISCV/bin -# Verilator -export PATH=/usr/local/bin/verilator:$PATH # Change this for your path to Verilator +# Activate riscv-python Virtual Environment +source "$RISCV"/riscv-python/bin/activate # environment variables needed for RISCV-DV -export RISCV_GCC=`which riscv64-unknown-elf-gcc` # Copy this as it is -export RISCV_OBJCOPY=`which riscv64-unknown-elf-objcopy` # Copy this as it is -export SPIKE_PATH=/usr/bin # Change this for your path to riscv-isa-sim (spike) +export RISCV_GCC=$(which riscv64-unknown-elf-gcc) # Copy this as it is +export RISCV_OBJCOPY=$(which riscv64-unknown-elf-objcopy) # Copy this as it is +export SPIKE_PATH=$RISCV/bin # Change this for your path to riscv-isa-sim (spike) + +# Verilator needs a larger stack to simulate CORE-V Wally +ulimit -c 234613 # Imperas OVPsim; put this in if you are using it #export PATH=$RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:$PATH @@ -48,5 +51,3 @@ if [ -e "$IDV" ]; then setupImperas ${IMPERAS_HOME} export PATH=$IDV/scripts/cvw:$PATH fi - - From beae45034791bb83fa20789606adafe199aed871 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 28 Jun 2024 15:21:30 -0700 Subject: [PATCH 016/219] Update cshell setup scripts --- bin/wally-tool-chain-install-unified.sh | 1 + setup.csh | 15 +++++++++++++-- site-setup.csh | 20 +++++++++++++------- 3 files changed, 27 insertions(+), 9 deletions(-) diff --git a/bin/wally-tool-chain-install-unified.sh b/bin/wally-tool-chain-install-unified.sh index 9a41af59a..4ff99d0d5 100755 --- a/bin/wally-tool-chain-install-unified.sh +++ b/bin/wally-tool-chain-install-unified.sh @@ -401,5 +401,6 @@ if [ ! -e "${RISCV}"/site-setup.sh ]; then wget https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.csh if [ "$FAMILY" = rhel ]; then echo "source /opt/rh/gcc-toolset-13/enable" >> site-setup.sh + echo "source /opt/rh/gcc-toolset-13/enable" >> site-setup.csh fi fi \ No newline at end of file diff --git a/setup.csh b/setup.csh index 62a99f376..ae86d4737 100755 --- a/setup.csh +++ b/setup.csh @@ -1,4 +1,4 @@ -#!/bin/sh +#!/bin/csh # setup.csh # james.stine@okstate.edu 18 February 2023 @@ -11,7 +11,17 @@ alias extend 'if (-d \!:2) if ("$\!:1" \!~ *"\!:2"*) setenv \!:1 ${\!:1}:\!:2;ec alias prepend 'if (-d \!:2) if ("$\!:1" \!~ *"\!:2"*) setenv \!:1 "\!:2":${\!:1};echo Added \!:2 to \!:1' # Path to RISC-V Tools -setenv RISCV /opt/riscv # change this if you installed the tools in a different location +if ( -e /opt/riscv ) then + setenv RISCV /opt/riscv +else if ( -e ~/riscv ) then + setenv RISCV ~/riscv +else + # set the $RISCV directory here and remove the subsequent two lines + # setenv RISCV + echo "\$RISCV directory not found. Checked /opt/riscv and ~/riscv. Edit setup.sh to point to your custom \$RISCV directory." + exit 1; +endif +echo \$RISCV set to "${RISCV}" # Path to Wally repository setenv WALLY $PWD @@ -19,6 +29,7 @@ echo '$WALLY set to ' ${WALLY} # utility functions in Wally repository extend PATH $WALLY/bin +# load site licenses and tool locations source $RISCV/site-setup.csh echo "setup done" diff --git a/site-setup.csh b/site-setup.csh index d2a52e720..4f8411a02 100644 --- a/site-setup.csh +++ b/site-setup.csh @@ -8,24 +8,30 @@ setenv MGLS_LICENSE_FILE 27002@zircon.eng.hmc.edu # Change this setenv SNPSLMD_LICENSE_FILE 27020@zircon.eng.hmc.edu # Change this to your Synopsys license server setenv QUESTAPATH /cad/mentor/questa_sim-2022.4_2/questasim/bin # Change this for your path to Questa setenv SNPSPATH /cad/synopsys/SYN/bin # Change this for your path to Design Compiler +setenv VCSPATH /cad/synopsys/vcs/U-2023.03-SP2-4/bin # Change this for your path to Synopsys VCS # Tools # Questa and Synopsys extend PATH $QUESTAPATH extend PATH $SNPSPATH +extend PATH $VCSPATH # GCC -prepend LD_LIBRARY_PATH $RISCV/riscv-gnu-toolchain/lib -prepend LD_LIBRARY_PATH $RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib -extend PATH $RISCV/riscv-gnu-toolchain/bin # GCC tools -extend PATH $RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/bin # GCC tools +extend LD_LIBRARY_PATH $RISCV/riscv64-unknown-elf/lib -# Spike +# RISC-V Tools extend LD_LIBRARY_PATH $RISCV/lib +extend LD_LIBRARY_PATH $RISCV/lib64 extend PATH $RISCV/bin -# Verilator -extend PATH /usr/local/bin/verilator # Change this for your path to Verilator +# Activate riscv-python Virtual Environment +source "$RISCV"/riscv-python/bin/activate + +# environment variables needed for RISCV-DV +setenv RISCV_GCC $(which riscv64-unknown-elf-gcc) # Copy this as it is +setenv RISCV_OBJCOPY $(which riscv64-unknown-elf-objcopy) # Copy this as it is +setenv SPIKE_PATH $RISCV/bin # Change this for your path to riscv-isa-sim (spike) + # Verilator needs a larger stack to simulate CORE-V Wally limit stacksize unlimited From 419917517fe3d8294e885cc08de5d1c1584fc7c4 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 28 Jun 2024 15:50:05 -0700 Subject: [PATCH 017/219] Add ncurses back for buildroot --- bin/wally-tool-chain-install-unified.sh | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/bin/wally-tool-chain-install-unified.sh b/bin/wally-tool-chain-install-unified.sh index 4ff99d0d5..2cdb10cd2 100755 --- a/bin/wally-tool-chain-install-unified.sh +++ b/bin/wally-tool-chain-install-unified.sh @@ -123,12 +123,13 @@ if [ "$FAMILY" = rhel ]; then # Packages are grouped by which tool requires them, split by line. # If mutltipole tools need a package, it is included in the first tool only - # General/Wally specific, riscv-gnu-toolchain, qemu, spike, verilator + # General/Wally specific, riscv-gnu-toolchain, qemu, spike, verilator, buildroot sudo dnf install -y git make cmake python3.12 python3-pip curl wget ftp tar pkgconfig dialog mutt ssmtp gcc-gfortran \ autoconf automake libmpc-devel mpfr-devel gmp-devel gawk bison flex texinfo gperf libtool patchutils bc gcc gcc-c++ zlib-devel expat-devel libslirp-devel \ glib2-devel libfdt-devel pixman-devel bzip2 ninja-build \ dtc boost-regex boost-system \ - help2man perl clang ccache gperftools numactl mold + help2man perl clang ccache gperftools numactl mold \ + ncurses-base ncurses ncurses-libs ncurses-devel # Extra packages not availale in rhel8, nice for verialtor and needed for sail respectively if [ "$RHEL_VERSION" = 9 ]; then sudo dnf install -y perl-doc z3 @@ -144,13 +145,14 @@ elif [ "$FAMILY" = ubuntu ]; then # Packages are grouped by which tool requires them, split by line. # If mutltipole tools need a package, it is included in the first tool only - # General/Wally specific, riscv-gnu-toolchain, qemu, spike, verilator, sail + # General/Wally specific, riscv-gnu-toolchain, qemu, spike, verilator, sail, buildroot sudo apt install -y git make cmake python3 python3-pip python3-venv curl wget ftp tar pkg-config dialog mutt ssmtp gfortran libboost-all-dev \ autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat1-dev ninja-build libglib2.0-dev libslirp-dev \ libfdt-dev libpixman-1-dev \ device-tree-compiler libboost-regex-dev libboost-system-dev \ help2man perl g++ clang ccache libgoogle-perftools-dev numactl mold perl-doc libfl2 libfl-dev zlib1g \ - opam z3 + opam z3 \ + ncurses-base ncurses-bin libncurses5-dev fi echo -e "\n*************************************************************************" From 7a13c584074ca8e9f614fbf2a8054e871d89c66c Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 28 Jun 2024 15:51:10 -0700 Subject: [PATCH 018/219] Remove individual install scripts --- bin/wally-tool-chain-install-redhat.sh | 368 ------------------------- bin/wally-tool-chain-install.sh | 242 ---------------- 2 files changed, 610 deletions(-) delete mode 100755 bin/wally-tool-chain-install-redhat.sh delete mode 100755 bin/wally-tool-chain-install.sh diff --git a/bin/wally-tool-chain-install-redhat.sh b/bin/wally-tool-chain-install-redhat.sh deleted file mode 100755 index 8ad49a57f..000000000 --- a/bin/wally-tool-chain-install-redhat.sh +++ /dev/null @@ -1,368 +0,0 @@ -#!/bin/bash -########################################### -## Tool chain install script. -## -## Written: Ross Thompson ross1728@gmail.com -## Created: 18 January 2023 -## Modified: 22 January 2023 -## Modified: 23 March 2023 -## Adapted for Red Hat: June 19 2024, Jordan Carlin jcarlin@hmc.edu -## -## Purpose: Open source tool chain installation script -## -## A component of the CORE-V-WALLY configurable RISC-V project. -## https://github.com/openhwgroup/cvw -## -## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -## -## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -## -## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -## except in compliance with the License, or, at your option, the Apache License version 2.0. You -## may obtain a copy of the License at -## -## https:##solderpad.org/licenses/SHL-2.1/ -## -## Unless required by applicable law or agreed to in writing, any work distributed under the -## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -## either express or implied. See the License for the specific language governing permissions -## and limitations under the License. -################################################################################################ - -# MODIFY FOR YOUR MACHINE -# Increasing NUM_THREADS will speed up parallel compilation of the tools -#NUM_THREADS=2 # for low memory machines > 16GiB -NUM_THREADS=8 # for >= 32GiB -#NUM_THREADS=16 # for >= 64GiB - -echo -e "\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Checking Distro and Permissions and Setting Installation Directory" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n" - -set -e # break on error - -# Get distribution information -test -e /etc/os-release && os_release="/etc/os-release" || os_release="/usr/lib/os-release" -source "$os_release" - -# Check for compatible distro -if [[ "$ID" = rhel || "$ID_LIKE" = *rhel* ]]; then - FAMILY=rhel - if [ "$ID" != rhel ] && [ "$ID" != rocky ]; then - echo "For Red Hat family distros, the Wally install script has only been tested on RHEL and Rocky Linux. Your distro \ -is $PRETTY_NAME. The regular Red Hat install will be attempted, but there will likely be issues." - fi - if [ "${VERSION_ID:0:1}" = 8 ]; then - RHEL_VERSION=8 - elif [ "${VERSION_ID:0:1}" = 9 ]; then - RHEL_VERSION=9 - else - echo "The Wally install script is only compatible with versions 8 and 9 of RHEL and Rocky Linux. You have version $VERSION." - exit 1 - fi -elif [[ "$ID" = ubuntu || "$ID_LIKE" = *ubuntu* ]]; then - FAMILY=ubuntu - if [ "$ID" != ubuntu ]; then - echo "For Ubuntu family distros, the Wally install script has only been tested on standard Ubuntu. Your distro \ -is $PRETTY_NAME. The regular Ubuntu install will be attempted, but there may be issues." - fi -else - echo "The Wally install script is currently only compatible with Ubuntu and Red Hat family \ -(RHEL or Rocky Linux) distros. Your detected distro is $ID. You may try manually running the \ -commands in this script, but it is likely that some will need to be altered." - exit 1 -fi - -# Check if root -ROOT=$( [ "${EUID:=$(id -u)}" = 0 ] && echo true || echo false); - -# All tools will be installed under the $RISCV directory. By default, if run as root (with sudo) this is set to -# /opt/riscv. Otherwise, it is set to ~/riscv. This value can be overridden with an argument passed to the script. -if [ "$ROOT" = true ]; then - export RISCV="${1:-/opt/riscv}" -else - export RISCV="${1:-$HOME/riscv}" -fi - -export PATH=$PATH:$RISCV/bin:/usr/bin -export PKG_CONFIG_PATH=$RISCV/lib64/pkgconfig:$RISCV/lib/pkgconfig:$RISCV/share/pkgconfig:$PKG_CONFIG_PATH -mkdir -p "$RISCV" - -echo -e "\nDetected information:" -echo "Distribution: $PRETTY_NAME" -echo "Version: $VERSION" -echo "Running as root: $ROOT" -echo "Installation path: $RISCV" - -echo -e "\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Installing Dependencies from Package Manager" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n" -if [ "$FAMILY" = rhel ]; then - # Enable extra package repos - sudo dnf install -y dnf-plugins-core - if [ "$ID" = rhel ]; then - sudo subscription-manager repos --enable "codeready-builder-for-rhel-$RHEL_VERSION-$(arch)-rpms" - sudo dnf install -y "https://dl.fedoraproject.org/pub/epel/epel-release-latest-$RHEL_VERSION.noarch.rpm" - else - if [ "$RHEL_VERSION" = 8 ]; then - sudo dnf config-manager -y --set-enabled powertools - else # Version 9 - sudo dnf config-manager -y --set-enabled crb - fi - sudo dnf install -y epel-release - fi - - # Update packages and install additional core tools - sudo dnf update -y - sudo dnf group install -y "Development Tools" - - # Packages are grouped by which tool requires them, split by line. - # If mutltipole tools need a package, it is included in the first tool only - # General/Wally specific, riscv-gnu-toolchain, qemu, spike, verilator - sudo dnf install -y git make cmake python3.12 python3-pip curl wget ftp tar pkgconfig dialog mutt ssmtp gcc-gfortran boost-devel\ - autoconf automake libmpc-devel mpfr-devel gmp-devel gawk bison flex texinfo gperf libtool patchutils bc gcc gcc-c++ zlib-devel expat-devel libslirp-devel \ - glib2-devel libfdt-devel pixman-devel bzip2 ninja-build \ - dtc boost-regex boost-system \ - help2man perl clang ccache gperftools numactl mold - # Extra packages not availale in rhel8, nice for verialtor and needed for sail respectively - if [ "$RHEL_VERSION" = 9 ]; then - sudo dnf install -y perl-doc z3 - fi - - # A newer version of gcc is required for qemu - sudo dnf install -y gcc-toolset-13* - source /opt/rh/gcc-toolset-13/enable # activate gcc13 -fi - -echo -e "\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Setting up Python Environment" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n" -# Create python virtual environment so the python command targets our desired version of python -# and installed packages are isolated from the rest of the system. -cd "$RISCV" -if [ ! -e "$RISCV"/riscv-python/bin/activate ]; then - python3.12 -m venv riscv-python -fi -source "$RISCV"/riscv-python/bin/activate # activate python virtual environment - -# Install python packages -pip install -U pip -pip install -U sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown pyyaml meson testresources riscv_config -pip install -U riscv_isac # to generate new tests, such as quads with fp_dataset.py - -# Needed for sail and not availabe from dnf for rhel 8 -if [ "$RHEL_VERSION" = 8 ]; then - pip install -U z3-solver -fi -source "$RISCV"/riscv-python/bin/activate # reload python virtual environment - -# Extra dependecies needed for rhel 8 that don't have new enough versions available from dnf -if [ "$RHEL_VERSION" = 8 ]; then - # Newer versin of glib required for Qemu. - # Anything newer than this won't build on red hat 8 - if [ ! -e "$RISCV"/include/glib-2.0 ]; then - echo -e "\n*************************************************************************" - echo -e "*************************************************************************" - echo -e "Installing glib" - echo -e "*************************************************************************" - echo -e "*************************************************************************\n" - cd "$RISCV" - wget https://download.gnome.org/sources/glib/2.70/glib-2.70.5.tar.xz - tar -xJf glib-2.70.5.tar.xz - rm glib-2.70.5.tar.xz - cd glib-2.70.5 - meson setup _build --prefix="$RISCV" - meson compile -C _build - meson install -C _build - cd "$RISCV" - rm -rf glib-2.70.5 - fi - # Newer version of gmp needed for sail-riscv model - if [ ! -e "$RISCV"/include/gmp.h ]; then - echo -e "\n*************************************************************************" - echo -e "*************************************************************************" - echo -e "Installing gmp" - echo -e "*************************************************************************" - echo -e "*************************************************************************\n" - cd "$RISCV" - wget https://ftp.gnu.org/gnu/gmp/gmp-6.3.0.tar.xz - tar -xJf gmp-6.3.0.tar.xz - rm gmp-6.3.0.tar.xz - cd gmp-6.3.0 - ./configure --prefix="$RISCV" - make -j ${NUM_THREADS} - make install - cd "$RISCV" - rm -rf gmp-6.3.0 - fi -fi - -# gcc cross-compiler (https://github.com/riscv-collab/riscv-gnu-toolchain) -# To install GCC from source can take hours to compile. -# This configuration enables multilib to target many flavors of RISC-V. -# This book is tested with GCC 13.2.0 -echo -e "\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Installing RISC-V GNU Toolchain" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n" -cd "$RISCV" -if [[ ((! -e riscv-gnu-toolchain) && ($(git clone https://github.com/riscv/riscv-gnu-toolchain) || true)) || ($(cd riscv-gnu-toolchain; git fetch; git rev-parse HEAD) != $(cd riscv-gnu-toolchain; git rev-parse master)) || (! -e $RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2) ]]; then - cd riscv-gnu-toolchain - git checkout master - git pull - ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" - make -j ${NUM_THREADS} -fi - -# elf2hex (https://github.com/sifive/elf2hex) -#The elf2hex utility to converts executable files into hexadecimal files for Verilog simulation. -# Note: The exe2hex utility that comes with Spike doesn’t work for our purposes because it doesn’t -# handle programs that start at 0x80000000. The SiFive version above is touchy to install. -# For example, if Python version 2.x is in your path, it won’t install correctly. -# Also, be sure riscv64-unknown-elf-objcopy shows up in your path in $RISCV/riscv-gnu-toolchain/bin -# at the time of compilation, or elf2hex won’t work properly. -echo -e "\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Installing elf2hex" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n" -cd "$RISCV" -export PATH=$RISCV/bin:$PATH -if [[ ((! -e elf2hex) && ($(git clone https://github.com/sifive/elf2hex.git) || true)) || ($(cd elf2hex; git fetch; git rev-parse HEAD) != $(cd elf2hex; git rev-parse master)) || (! -e $RISCV/bin/riscv64-unknown-elf-elf2bin) ]]; then - cd elf2hex - git reset --hard && git clean -f && git checkout master && git pull - autoreconf -i - ./configure --target=riscv64-unknown-elf --prefix="$RISCV" - make - make install -fi - - -# QEMU (https://www.qemu.org/docs/master/system/target-riscv.html) -echo -e "\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Installing QEMU" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n" -cd "$RISCV" -if [[ ((! -e qemu) && ($(git clone --recurse-submodules https://github.com/qemu/qemu) || true)) || ($(cd qemu; git fetch --recurse-submodules=yes; git rev-parse HEAD) != $(cd qemu; git rev-parse master)) || (! -e $RISCV/include/qemu-plugin.h) ]]; then - cd qemu - git reset --hard && git clean -f && git checkout master && git pull --recurse-submodules - ./configure --target-list=riscv64-softmmu --prefix="$RISCV" - make -j ${NUM_THREADS} - make install -fi - -# Spike (https://github.com/riscv-software-src/riscv-isa-sim) -# Spike also takes a while to install and compile, but this can be done concurrently -# with the GCC installation. -echo -e "\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Installing SPIKE" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n" -cd "$RISCV" -if [[ ((! -e riscv-isa-sim) && ($(git clone https://github.com/riscv-software-src/riscv-isa-sim) || true)) || ($(cd riscv-isa-sim; git fetch; git rev-parse HEAD) != $(cd riscv-isa-sim; git rev-parse master)) || (! -e $RISCV/lib/pkgconfig/riscv-riscv.pc) ]]; then - cd riscv-isa-sim - git reset --hard && git clean -f && git checkout master && git pull - mkdir -p build - cd build - ../configure --prefix="$RISCV" - make -j ${NUM_THREADS} - make install -fi - -# Wally needs Verilator 5.021 or later. -# Verilator needs to be built from source to get the latest version -echo -e "\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Installing Verilator" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n" -cd "$RISCV" -if [[ ((! -e verilator) && ($(git clone https://github.com/verilator/verilator) || true)) || ($(cd verilator; git fetch; git rev-parse HEAD) != $(cd verilator; git rev-parse master)) || (! -e $RISCV/share/pkgconfig/verilator.pc) ]]; then - # unsetenv VERILATOR_ROOT # For csh; ignore error if on bash - unset VERILATOR_ROOT # For bash - cd verilator - git reset --hard && git clean -f && git checkout master && git pull - autoconf # Create ./configure script - ./configure --prefix="$RISCV" # Configure and create Makefile - make -j ${NUM_THREADS} # Build Verilator itself (if error, try just 'make') - make install -fi - -# RISC-V Sail Model (https://github.com/riscv/sail-riscv) -# The RISC-V Sail Model is the golden reference model for RISC-V. It is written in Sail, -# a language designed for expressing the semantics of an ISA. Sail itself is written in -# OCaml, which is an object-oriented extension of ML, which in turn is a functional programming -# language suited to formal verification. The Sail compiler is installed with the opam OCcaml -# package manager. The Sail compiler has so many dependencies that it can be difficult to install, -# but a binary release of it should be available soon, removing the need to use opam. -echo -e "\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Installing Opam" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n" -cd "$RISCV" -mkdir -p opam -cd opam -wget https://raw.githubusercontent.com/ocaml/opam/master/shell/install.sh -printf '%s\n' "$RISCV"/bin Y | sh install.sh # the print command provides $RISCV/bin as the installation path when prompted -cd "$RISCV" -rm -rf opam - -echo -e "\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Installing Sail Compiler" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n" -opam init -y --disable-sandboxing -opam update -y -opam upgrade -y -opam switch create 5.1.0 || opam switch set 5.1.0 -opam install sail -y - -echo -e "\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Installing RISC-V Sail Model" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n" -if [[ ((! -e sail-riscv) && ($(git clone https://github.com/riscv/sail-riscv.git) || true)) || ($(cd sail-riscv; git fetch; git rev-parse HEAD) != $(cd sail-riscv; git rev-parse master)) || (! -e $RISCV/bin/riscv_sim_RV32) ]]; then - eval $(opam config env) - cd sail-riscv - git reset --hard && git clean -f && git checkout master && git pull - export OPAMCLI=2.0 # Sail is not compatible with opam 2.1 as of 4/16/24 - ARCH=RV64 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV64 - ARCH=RV32 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV32 - cd "$RISCV" - ln -sf ../sail-riscv/c_emulator/riscv_sim_RV64 bin/riscv_sim_RV64 - ln -sf ../sail-riscv/c_emulator/riscv_sim_RV32 bin/riscv_sim_RV32 -fi - -# riscof -echo -e "\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Installing riscof" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n" -pip3 install git+https://github.com/riscv/riscof.git - -# Download OSU Skywater 130 cell library -echo -e "\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Installing OSU Skywater 130 cell library" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n" -mkdir -p "$RISCV"/cad/lib -cd "$RISCV"/cad/lib -if [[ ((! -e sky130_osu_sc_t12) && ($(git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12) || true)) || ($(cd sky130_osu_sc_t12; git fetch; git rev-parse HEAD) != $(cd sky130_osu_sc_t12; git rev-parse master)) ]]; then - cd sky130_osu_sc_t12 - git reset --hard && git clean -f && git checkout main && git pull -fi diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh deleted file mode 100755 index 3a81e3f06..000000000 --- a/bin/wally-tool-chain-install.sh +++ /dev/null @@ -1,242 +0,0 @@ -#!/bin/bash -########################################### -## Tool chain install script. -## -## Written: Ross Thompson ross1728@gmail.com -## Created: 18 January 2023 -## Modified: 22 January 2023 -## Modified: 23 March 2023 -## Modified: 21 June 2024, Jordan Carlin jcarlin@hmc.edu -## -## Purpose: Open source tool chain installation script -## -## A component of the CORE-V-WALLY configurable RISC-V project. -## https://github.com/openhwgroup/cvw -## -## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -## -## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -## -## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -## except in compliance with the License, or, at your option, the Apache License version 2.0. You -## may obtain a copy of the License at -## -## https:##solderpad.org/licenses/SHL-2.1/ -## -## Unless required by applicable law or agreed to in writing, any work distributed under the -## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -## either express or implied. See the License for the specific language governing permissions -## and limitations under the License. -################################################################################################ - -# Check if root -ROOT=$( [ "${EUID:=$(id -u)}" = 0 ] && echo true || echo false); - -# All tools will be installed under the $RISCV directory. By default, if run as root (with sudo) -# this is set to /opt/riscv. Otherwise, it is set to ~/riscv. This value can be changed if needed. -if [ "$ROOT" = true ]; then - export RISCV="${1:-/opt/riscv}" -else - export RISCV="${1:-$HOME/riscv}" -fi - -export PATH=$PATH:$RISCV/bin:/usr/bin - -set -e # break on error - -# Modify accordingly for your machine -# Increasing NUM_THREADS will speed up parallel compilation of the tools -#NUM_THREADS=2 # for low memory machines > 16GiB -NUM_THREADS=8 # for >= 32GiB -#NUM_THREADS=16 # for >= 64GiB - -mkdir -p "$RISCV" - -echo -e "\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Installing Dependencies from Package Manager" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n" -# Update and Upgrade tools (see https://itsfoss.com/apt-update-vs-upgrade/) -sudo apt update -y -sudo apt upgrade -y - -# Packages are grouped by which tool requires them, split by line. -# If mutltipole tools need a package, it is included in the first tool only -# General/Wally specific, riscv-gnu-toolchain, qemu, spike, verilator, sail -sudo apt install -y git make cmake python3 python3-pip python3-venv curl wget ftp tar pkg-config dialog mutt ssmtp gfortran libboost-all-dev \ - autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat1-dev ninja-build libglib2.0-dev libslirp-dev \ - libfdt-dev libpixman-1-dev \ - device-tree-compiler libboost-regex-dev libboost-system-dev \ - help2man perl g++ clang ccache libgoogle-perftools-dev numactl mold perl-doc libfl2 libfl-dev zlib1g \ - opam z3 - -echo -e "\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Setting up Python Environment" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n" -# Other python libraries used through the book. -cd "$RISCV" -if [ ! -e "$RISCV"/riscv-python/bin/activate ]; then - python3 -m venv riscv-python -fi -source "$RISCV"/riscv-python/bin/activate -pip install -U pip -pip install -U sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown pyyaml testresources riscv_config -pip install -U riscv_isac # to generate new tests, such as quads with fp_dataset.py -source "$RISCV"/riscv-python/bin/activate - -# gcc cross-compiler (https://github.com/riscv-collab/riscv-gnu-toolchain) -# To install GCC from source can take hours to compile. -# This configuration enables multilib to target many flavors of RISC-V. -# This book is tested with GCC 13.2.0 -echo -e "\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Installing RISC-V GNU Toolchain" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n" -cd "$RISCV" -if [[ ((! -e riscv-gnu-toolchain) && ($(git clone https://github.com/riscv/riscv-gnu-toolchain) || true)) || ($(cd riscv-gnu-toolchain; git fetch; git rev-parse HEAD) != $(cd riscv-gnu-toolchain; git rev-parse master)) || (! -e $RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2) ]]; then - cd riscv-gnu-toolchain - git checkout master - git pull - ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" - make -j ${NUM_THREADS} -fi - -# elf2hex (https://github.com/sifive/elf2hex) -#The elf2hex utility to converts executable files into hexadecimal files for Verilog simulation. -# Note: The exe2hex utility that comes with Spike doesn’t work for our purposes because it doesn’t -# handle programs that start at 0x80000000. The SiFive version above is touchy to install. -# For example, if Python version 2.x is in your path, it won’t install correctly. -# Also, be sure riscv64-unknown-elf-objcopy shows up in your path in $RISCV/riscv-gnu-toolchain/bin -# at the time of compilation, or elf2hex won’t work properly. -echo -e "\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Installing elf2hex" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n" -cd "$RISCV" -export PATH=$RISCV/bin:$PATH -if [[ ((! -e elf2hex) && ($(git clone https://github.com/sifive/elf2hex.git) || true)) || ($(cd elf2hex; git fetch; git rev-parse HEAD) != $(cd elf2hex; git rev-parse master)) || (! -e $RISCV/bin/riscv64-unknown-elf-elf2bin) ]]; then - cd elf2hex - git reset --hard && git clean -f && git checkout master && git pull - autoreconf -i - ./configure --target=riscv64-unknown-elf --prefix="$RISCV" - make - make install -fi - - -# QEMU (https://www.qemu.org/docs/master/system/target-riscv.html) -echo -e "\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Installing QEMU" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n" -cd "$RISCV" -if [[ ((! -e qemu) && ($(git clone --recurse-submodules https://github.com/qemu/qemu) || true)) || ($(cd qemu; git fetch --recurse-submodules=yes; git rev-parse HEAD) != $(cd qemu; git rev-parse master)) || (! -e $RISCV/include/qemu-plugin.h) ]]; then - cd qemu - git reset --hard && git clean -f && git checkout master && git pull --recurse-submodules - ./configure --target-list=riscv64-softmmu --prefix="$RISCV" - make -j ${NUM_THREADS} - make install -fi - -# Spike (https://github.com/riscv-software-src/riscv-isa-sim) -# Spike also takes a while to install and compile, but this can be done concurrently -# with the GCC installation. -echo -e "\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Installing SPIKE" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n" -cd "$RISCV" -if [[ ((! -e riscv-isa-sim) && ($(git clone https://github.com/riscv-software-src/riscv-isa-sim) || true)) || ($(cd riscv-isa-sim; git fetch; git rev-parse HEAD) != $(cd riscv-isa-sim; git rev-parse master)) || (! -e $RISCV/lib/pkgconfig/riscv-riscv.pc) ]]; then - cd riscv-isa-sim - git reset --hard && git clean -f && git checkout master && git pull - mkdir -p build - cd build - ../configure --prefix="$RISCV" - make -j ${NUM_THREADS} - make install -fi - - -# Wally needs Verilator 5.021 or later. -# Verilator needs to be built from scratch to get the latest version -# apt-get install verilator installs version 4.028 as of 6/8/23 -echo -e "\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Installing Verilator" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n" -cd "$RISCV" -if [[ ((! -e verilator) && ($(git clone https://github.com/verilator/verilator) || true)) || ($(cd verilator; git fetch; git rev-parse HEAD) != $(cd verilator; git rev-parse master)) || (! -e $RISCV/share/pkgconfig/verilator.pc) ]]; then - # unsetenv VERILATOR_ROOT # For csh; ignore error if on bash - unset VERILATOR_ROOT # For bash - cd verilator - git reset --hard && git clean -f && git checkout master && git pull - autoconf # Create ./configure script - ./configure --prefix="$RISCV" # Configure and create Makefile - make -j ${NUM_THREADS} # Build Verilator itself (if error, try just 'make') - make install -fi - -# RISC-V Sail Model (https://github.com/riscv/sail-riscv) -# The RISC-V Sail Model is the golden reference model for RISC-V. It is written in Sail, -# a language designed for expressing the semantics of an ISA. Sail itself is written in -# OCaml, which is an object-oriented extension of ML, which in turn is a functional programming -# language suited to formal verification. The Sail compiler is installed with the opam OCcaml -# package manager. The Sail compiler has so many dependencies that it can be difficult to install, -# but a binary release of it should be available soon, removing the need to use opam. -echo -e "\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Installing Sail Compiler" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n" -cd "$RISCV" -opam init -y --disable-sandboxing -opam update -y -opam upgrade -y -opam switch create 5.1.0 || opam switch set 5.1.0 -opam install sail -y - -echo -e "\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Installing RISC-V Sail Model" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n" -if [[ ((! -e sail-riscv) && ($(git clone https://github.com/riscv/sail-riscv.git) || true)) || ($(cd sail-riscv; git fetch; git rev-parse HEAD) != $(cd sail-riscv; git rev-parse master)) || (! -e $RISCV/bin/riscv_sim_RV32) ]]; then - eval $(opam config env) - cd sail-riscv - git reset --hard && git clean -f && git checkout master && git pull - export OPAMCLI=2.0 # Sail is not compatible with opam 2.1 as of 4/16/24 - ARCH=RV64 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV64 - ARCH=RV32 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV32 - cd "$RISCV" - ln -sf ../sail-riscv/c_emulator/riscv_sim_RV64 bin/riscv_sim_RV64 - ln -sf ../sail-riscv/c_emulator/riscv_sim_RV32 bin/riscv_sim_RV32 -fi - -# riscof -echo -e "\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Installing riscof" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n" -pip3 install git+https://github.com/riscv/riscof.git - -# Download OSU Skywater 130 cell library -echo -e "\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Installing OSU Skywater 130 cell library" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n" -mkdir -p "$RISCV"/cad/lib -cd "$RISCV"/cad/lib -if [[ ((! -e sky130_osu_sc_t12) && ($(git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12) || true)) || ($(cd sky130_osu_sc_t12; git fetch; git rev-parse HEAD) != $(cd sky130_osu_sc_t12; git rev-parse master)) ]]; then - cd sky130_osu_sc_t12 - git reset --hard && git clean -f && git checkout main && git pull -fi From d876b769111829abdb6858691999c5bcd3baa338 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 28 Jun 2024 15:58:09 -0700 Subject: [PATCH 019/219] Rename unified install script --- ...-tool-chain-install-unified.sh => wally-tool-chain-install.sh} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename bin/{wally-tool-chain-install-unified.sh => wally-tool-chain-install.sh} (100%) diff --git a/bin/wally-tool-chain-install-unified.sh b/bin/wally-tool-chain-install.sh similarity index 100% rename from bin/wally-tool-chain-install-unified.sh rename to bin/wally-tool-chain-install.sh From 79870cc910300e2457528f8e02061d58d0f19a62 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 28 Jun 2024 16:13:08 -0700 Subject: [PATCH 020/219] csh script corrections --- site-setup.csh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/site-setup.csh b/site-setup.csh index 4f8411a02..cd70da08c 100644 --- a/site-setup.csh +++ b/site-setup.csh @@ -25,11 +25,11 @@ extend LD_LIBRARY_PATH $RISCV/lib64 extend PATH $RISCV/bin # Activate riscv-python Virtual Environment -source "$RISCV"/riscv-python/bin/activate +source "$RISCV"/riscv-python/bin/activate.csh # environment variables needed for RISCV-DV -setenv RISCV_GCC $(which riscv64-unknown-elf-gcc) # Copy this as it is -setenv RISCV_OBJCOPY $(which riscv64-unknown-elf-objcopy) # Copy this as it is +setenv RISCV_GCC `which riscv64-unknown-elf-gcc` # Copy this as it is +setenv RISCV_OBJCOPY `which riscv64-unknown-elf-objcopy` # Copy this as it is setenv SPIKE_PATH $RISCV/bin # Change this for your path to riscv-isa-sim (spike) # Verilator needs a larger stack to simulate CORE-V Wally From 5634577a24f29af72c4db7510cb8bda1b94df030 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 26 Jun 2024 22:39:43 -0700 Subject: [PATCH 021/219] Remove verilator hack --- testbench/testbench.sv | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index be0422550..3661c6a98 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -385,14 +385,6 @@ module testbench; // and initialize them to zero (also initilaize them to zero at the start of the next test) updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray); end -`ifdef VERILATOR // this macro is defined when verilator is used - // Simulator Verilator has an issue that the validate logic below slows runtime 110x if it is - // in the posedge clk block rather than a separate posedge Validate block. - // Until it is fixed, provide a silly posedge Validate block to keep Verilator happy. - // https://github.com/verilator/verilator/issues/4967 - end // restored - always @(posedge Validate) // added -`endif if(Validate) begin if (PrevPCZero) totalerrors = totalerrors + 1; // error if PC is stuck at zero if (TEST == "buildroot") @@ -445,10 +437,7 @@ module testbench; `endif end end -`ifndef VERILATOR - // Remove this when issue 4967 is resolved and the posedge Validate logic above is removed - end -`endif + end //////////////////////////////////////////////////////////////////////////////// From fbb39efc4d8cacae2fa35e5da5d54b20092a0d54 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 28 Jun 2024 20:25:11 -0700 Subject: [PATCH 022/219] red hat gcc-toolset-13 not compatible with csh --- bin/wally-tool-chain-install.sh | 3 +-- site-setup.csh | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 2cdb10cd2..be3530cbe 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -90,7 +90,7 @@ export PATH=$PATH:$RISCV/bin:/usr/bin export PKG_CONFIG_PATH=$RISCV/lib64/pkgconfig:$RISCV/lib/pkgconfig:$RISCV/share/pkgconfig:$PKG_CONFIG_PATH mkdir -p "$RISCV" -echo -e "\nDetected information" +echo -e "Detected information" echo "Distribution: $PRETTY_NAME" echo "Version: $VERSION" echo "Running as root: $ROOT" @@ -403,6 +403,5 @@ if [ ! -e "${RISCV}"/site-setup.sh ]; then wget https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.csh if [ "$FAMILY" = rhel ]; then echo "source /opt/rh/gcc-toolset-13/enable" >> site-setup.sh - echo "source /opt/rh/gcc-toolset-13/enable" >> site-setup.csh fi fi \ No newline at end of file diff --git a/site-setup.csh b/site-setup.csh index cd70da08c..2c18b6943 100644 --- a/site-setup.csh +++ b/site-setup.csh @@ -48,5 +48,5 @@ if ($?IDV) then source ${IMPERAS_HOME}/bin/setup.sh setupImperas ${IMPERAS_HOME} extend PATH $IDV/scripts/cvw -endfi +endif From 48e2293fa939e616c569dfa7bc7c3c402d3c9adb Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 28 Jun 2024 21:53:55 -0700 Subject: [PATCH 023/219] Fix libboost --- bin/wally-tool-chain-install.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index be3530cbe..a5f163ed6 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -146,7 +146,7 @@ elif [ "$FAMILY" = ubuntu ]; then # Packages are grouped by which tool requires them, split by line. # If mutltipole tools need a package, it is included in the first tool only # General/Wally specific, riscv-gnu-toolchain, qemu, spike, verilator, sail, buildroot - sudo apt install -y git make cmake python3 python3-pip python3-venv curl wget ftp tar pkg-config dialog mutt ssmtp gfortran libboost-all-dev \ + sudo apt install -y git make cmake python3 python3-pip python3-venv curl wget ftp tar pkg-config dialog mutt ssmtp gfortran \ autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat1-dev ninja-build libglib2.0-dev libslirp-dev \ libfdt-dev libpixman-1-dev \ device-tree-compiler libboost-regex-dev libboost-system-dev \ From 0298ee479efbe7823fe477ccd041699f2045280f Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 28 Jun 2024 23:25:44 -0700 Subject: [PATCH 024/219] Install working on Rocky 8 + 9 and Ubuntu 22 + 24 --- bin/wally-tool-chain-install.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index a5f163ed6..5cef88b29 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -404,4 +404,4 @@ if [ ! -e "${RISCV}"/site-setup.sh ]; then if [ "$FAMILY" = rhel ]; then echo "source /opt/rh/gcc-toolset-13/enable" >> site-setup.sh fi -fi \ No newline at end of file +fi From 3d8e8505053204026496d3d0e6d605ec7f19fc00 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 28 Jun 2024 23:36:47 -0700 Subject: [PATCH 025/219] Fix ubuntu libncurses to avoid redirect on Ubuntu 24 --- bin/wally-tool-chain-install.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 5cef88b29..4680ff9df 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -152,7 +152,7 @@ elif [ "$FAMILY" = ubuntu ]; then device-tree-compiler libboost-regex-dev libboost-system-dev \ help2man perl g++ clang ccache libgoogle-perftools-dev numactl mold perl-doc libfl2 libfl-dev zlib1g \ opam z3 \ - ncurses-base ncurses-bin libncurses5-dev + ncurses-base ncurses-bin libncurses-dev fi echo -e "\n*************************************************************************" From 6c81fd7759caf7c67618f6c20cb38fd6ddf3e2af Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 29 Jun 2024 00:29:01 -0700 Subject: [PATCH 026/219] whitespace cleanup --- bin/wally-tool-chain-install.sh | 336 ++++++++++++++++---------------- setup.sh | 2 +- site-setup.csh | 2 +- site-setup.sh | 4 +- 4 files changed, 172 insertions(+), 172 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 4680ff9df..7620900c6 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -49,30 +49,30 @@ source "$os_release" # Check for compatible distro if [[ "$ID" = rhel || "$ID_LIKE" = *rhel* ]]; then - FAMILY=rhel - if [ "$ID" != rhel ] && [ "$ID" != rocky ]; then - echo "For Red Hat family distros, the Wally install script has only been tested on RHEL and Rocky Linux. Your distro \ -is $PRETTY_NAME. The regular Red Hat install will be attempted, but there will likely be issues." - fi - if [ "${VERSION_ID:0:1}" = 8 ]; then - RHEL_VERSION=8 - elif [ "${VERSION_ID:0:1}" = 9 ]; then - RHEL_VERSION=9 - else - echo "The Wally install script is only compatible with versions 8 and 9 of RHEL and Rocky Linux. You have version $VERSION." - exit 1 - fi + FAMILY=rhel + if [ "$ID" != rhel ] && [ "$ID" != rocky ]; then + printf "%s\n" "For Red Hat family distros, the Wally install script has only been tested on RHEL and Rocky Linux. Your distro " \ + "is $PRETTY_NAME. The regular Red Hat install will be attempted, but there will likely be issues." + fi + if [ "${VERSION_ID:0:1}" = 8 ]; then + RHEL_VERSION=8 + elif [ "${VERSION_ID:0:1}" = 9 ]; then + RHEL_VERSION=9 + else + echo "The Wally install script is only compatible with versions 8 and 9 of RHEL and Rocky Linux. You have version $VERSION." + exit 1 + fi elif [[ "$ID" = ubuntu || "$ID_LIKE" = *ubuntu* ]]; then - FAMILY=ubuntu + FAMILY=ubuntu if [ "$ID" != ubuntu ]; then - echo "For Ubuntu family distros, the Wally install script has only been tested on standard Ubuntu. Your distro \ -is $PRETTY_NAME. The regular Ubuntu install will be attempted, but there may be issues." - fi + printf "%s\n" "For Ubuntu family distros, the Wally install script has only been tested on standard Ubuntu. Your distro " \ + "is $PRETTY_NAME. The regular Ubuntu install will be attempted, but there may be issues." + fi else - echo "The Wally install script is currently only compatible with Ubuntu and Red Hat family \ -(RHEL or Rocky Linux) distros. Your detected distro is $PRETTY_NAME. You may try manually running the \ -commands in this script, but it is likely that some will need to be altered." - exit 1 + printf "%s\n" "The Wally install script is currently only compatible with Ubuntu and Red Hat family " \ + "(RHEL or Rocky Linux) distros. Your detected distro is $PRETTY_NAME. You may try manually running the " \ + "commands in this script, but it is likely that some will need to be altered." + exit 1 fi # Check if root @@ -81,16 +81,16 @@ ROOT=$( [ "${EUID:=$(id -u)}" = 0 ] && echo true || echo false); # All tools will be installed under the $RISCV directory. By default, if run as root (with sudo) this is set to # /opt/riscv. Otherwise, it is set to ~/riscv. This value can be overridden with an argument passed to the script. if [ "$ROOT" = true ]; then - export RISCV="${1:-/opt/riscv}" + export RISCV="${1:-/opt/riscv}" else - export RISCV="${1:-$HOME/riscv}" + export RISCV="${1:-$HOME/riscv}" fi export PATH=$PATH:$RISCV/bin:/usr/bin export PKG_CONFIG_PATH=$RISCV/lib64/pkgconfig:$RISCV/lib/pkgconfig:$RISCV/share/pkgconfig:$PKG_CONFIG_PATH mkdir -p "$RISCV" -echo -e "Detected information" +echo "Detected information" echo "Distribution: $PRETTY_NAME" echo "Version: $VERSION" echo "Running as root: $ROOT" @@ -103,56 +103,56 @@ echo -e "*********************************************************************** echo -e "*************************************************************************\n" # Installs appropriate packages for rhel or ubuntu distros, picking apt or dnf appropriately if [ "$FAMILY" = rhel ]; then - # Enable extra package repos - sudo dnf install -y dnf-plugins-core - if [ "$ID" = rhel ]; then - sudo subscription-manager repos --enable "codeready-builder-for-rhel-$RHEL_VERSION-$(arch)-rpms" - sudo dnf install -y "https://dl.fedoraproject.org/pub/epel/epel-release-latest-$RHEL_VERSION.noarch.rpm" - else - if [ "$RHEL_VERSION" = 8 ]; then - sudo dnf config-manager -y --set-enabled powertools - else # Version 9 - sudo dnf config-manager -y --set-enabled crb + # Enable extra package repos + sudo dnf install -y dnf-plugins-core + if [ "$ID" = rhel ]; then + sudo subscription-manager repos --enable "codeready-builder-for-rhel-$RHEL_VERSION-$(arch)-rpms" + sudo dnf install -y "https://dl.fedoraproject.org/pub/epel/epel-release-latest-$RHEL_VERSION.noarch.rpm" + else + if [ "$RHEL_VERSION" = 8 ]; then + sudo dnf config-manager -y --set-enabled powertools + else # Version 9 + sudo dnf config-manager -y --set-enabled crb + fi + sudo dnf install -y epel-release fi - sudo dnf install -y epel-release - fi - # Update packages and install additional core tools - sudo dnf update -y - sudo dnf group install -y "Development Tools" + # Update packages and install additional core tools + sudo dnf update -y + sudo dnf group install -y "Development Tools" # Packages are grouped by which tool requires them, split by line. # If mutltipole tools need a package, it is included in the first tool only # General/Wally specific, riscv-gnu-toolchain, qemu, spike, verilator, buildroot - sudo dnf install -y git make cmake python3.12 python3-pip curl wget ftp tar pkgconfig dialog mutt ssmtp gcc-gfortran \ - autoconf automake libmpc-devel mpfr-devel gmp-devel gawk bison flex texinfo gperf libtool patchutils bc gcc gcc-c++ zlib-devel expat-devel libslirp-devel \ - glib2-devel libfdt-devel pixman-devel bzip2 ninja-build \ - dtc boost-regex boost-system \ - help2man perl clang ccache gperftools numactl mold \ - ncurses-base ncurses ncurses-libs ncurses-devel - # Extra packages not availale in rhel8, nice for verialtor and needed for sail respectively - if [ "$RHEL_VERSION" = 9 ]; then - sudo dnf install -y perl-doc z3 - fi + sudo dnf install -y git make cmake python3.12 python3-pip curl wget ftp tar pkgconfig dialog mutt ssmtp gcc-gfortran \ + autoconf automake libmpc-devel mpfr-devel gmp-devel gawk bison flex texinfo gperf libtool patchutils bc gcc gcc-c++ zlib-devel expat-devel libslirp-devel \ + glib2-devel libfdt-devel pixman-devel bzip2 ninja-build \ + dtc boost-regex boost-system \ + help2man perl clang ccache gperftools numactl mold \ + ncurses-base ncurses ncurses-libs ncurses-devel + # Extra packages not availale in rhel8, nice for verialtor and needed for sail respectively + if [ "$RHEL_VERSION" = 9 ]; then + sudo dnf install -y perl-doc z3 + fi - # A newer version of gcc is required for qemu - sudo dnf install -y gcc-toolset-13* - source /opt/rh/gcc-toolset-13/enable # activate gcc13 + # A newer version of gcc is required for qemu + sudo dnf install -y gcc-toolset-13* + source /opt/rh/gcc-toolset-13/enable # activate gcc13 elif [ "$FAMILY" = ubuntu ]; then - # Update and Upgrade tools (see https://itsfoss.com/apt-update-vs-upgrade/) - sudo apt update -y - sudo apt upgrade -y + # Update and Upgrade tools (see https://itsfoss.com/apt-update-vs-upgrade/) + sudo apt update -y + sudo apt upgrade -y - # Packages are grouped by which tool requires them, split by line. - # If mutltipole tools need a package, it is included in the first tool only - # General/Wally specific, riscv-gnu-toolchain, qemu, spike, verilator, sail, buildroot - sudo apt install -y git make cmake python3 python3-pip python3-venv curl wget ftp tar pkg-config dialog mutt ssmtp gfortran \ - autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat1-dev ninja-build libglib2.0-dev libslirp-dev \ - libfdt-dev libpixman-1-dev \ - device-tree-compiler libboost-regex-dev libboost-system-dev \ - help2man perl g++ clang ccache libgoogle-perftools-dev numactl mold perl-doc libfl2 libfl-dev zlib1g \ - opam z3 \ - ncurses-base ncurses-bin libncurses-dev + # Packages are grouped by which tool requires them, split by line. + # If mutltipole tools need a package, it is included in the first tool only + # General/Wally specific, riscv-gnu-toolchain, qemu, spike, verilator, sail, buildroot + sudo apt install -y git make cmake python3 python3-pip python3-venv curl wget ftp tar pkg-config dialog mutt ssmtp gfortran \ + autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat1-dev ninja-build libglib2.0-dev libslirp-dev \ + libfdt-dev libpixman-1-dev \ + device-tree-compiler libboost-regex-dev libboost-system-dev \ + help2man perl g++ clang ccache libgoogle-perftools-dev numactl mold perl-doc libfl2 libfl-dev zlib1g \ + opam z3 \ + ncurses-base ncurses-bin libncurses-dev fi echo -e "\n*************************************************************************" @@ -164,12 +164,12 @@ echo -e "*********************************************************************** # and installed packages are isolated from the rest of the system. cd "$RISCV" if [ ! -e "$RISCV"/riscv-python/bin/activate ]; then - # If python3.12 is avaiable, use it. Otherise, use whatever version of python3 is installed. - if [ "$(which python3.12)" ]; then - python3.12 -m venv riscv-python - else - python3 -m venv riscv-python - fi + # If python3.12 is avaiable, use it. Otherise, use whatever version of python3 is installed. + if [ "$(which python3.12)" ]; then + python3.12 -m venv riscv-python + else + python3 -m venv riscv-python + fi fi source "$RISCV"/riscv-python/bin/activate # activate python virtual environment @@ -180,54 +180,54 @@ pip install -U riscv_isac # to generate new tests, such as quads with fp_dataset # z3 is eeded for sail and not availabe from dnf for rhel 8. Meson is needed to build extra dependencies if [ "$RHEL_VERSION" = 8 ]; then - pip install -U z3-solver meson + pip install -U z3-solver meson fi source "$RISCV"/riscv-python/bin/activate # reload python virtual environment # Extra dependecies needed for rhel 8 that don't have new enough versions available from dnf if [ "$RHEL_VERSION" = 8 ]; then - # Newer versin of glib required for Qemu. - # Anything newer than this won't build on red hat 8 - if [ ! -e "$RISCV"/include/glib-2.0 ]; then - echo -e "\n*************************************************************************" - echo -e "*************************************************************************" - echo -e "Installing glib" - echo -e "*************************************************************************" - echo -e "*************************************************************************\n" - cd "$RISCV" - wget https://download.gnome.org/sources/glib/2.70/glib-2.70.5.tar.xz - tar -xJf glib-2.70.5.tar.xz - rm glib-2.70.5.tar.xz - cd glib-2.70.5 - meson setup _build --prefix="$RISCV" - meson compile -C _build - meson install -C _build - cd "$RISCV" - rm -rf glib-2.70.5 - fi - # Newer version of gmp needed for sail-riscv model - if [ ! -e "$RISCV"/include/gmp.h ]; then - echo -e "\n*************************************************************************" - echo -e "*************************************************************************" - echo -e "Installing gmp" - echo -e "*************************************************************************" - echo -e "*************************************************************************\n" - cd "$RISCV" - wget https://ftp.gnu.org/gnu/gmp/gmp-6.3.0.tar.xz - tar -xJf gmp-6.3.0.tar.xz - rm gmp-6.3.0.tar.xz - cd gmp-6.3.0 - ./configure --prefix="$RISCV" - make -j ${NUM_THREADS} - make install - cd "$RISCV" - rm -rf gmp-6.3.0 - fi + # Newer versin of glib required for Qemu. + # Anything newer than this won't build on red hat 8 + if [ ! -e "$RISCV"/include/glib-2.0 ]; then + echo -e "\n*************************************************************************" + echo -e "*************************************************************************" + echo -e "Installing glib" + echo -e "*************************************************************************" + echo -e "*************************************************************************\n" + cd "$RISCV" + wget https://download.gnome.org/sources/glib/2.70/glib-2.70.5.tar.xz + tar -xJf glib-2.70.5.tar.xz + rm glib-2.70.5.tar.xz + cd glib-2.70.5 + meson setup _build --prefix="$RISCV" + meson compile -C _build + meson install -C _build + cd "$RISCV" + rm -rf glib-2.70.5 + fi + # Newer version of gmp needed for sail-riscv model + if [ ! -e "$RISCV"/include/gmp.h ]; then + echo -e "\n*************************************************************************" + echo -e "*************************************************************************" + echo -e "Installing gmp" + echo -e "*************************************************************************" + echo -e "*************************************************************************\n" + cd "$RISCV" + wget https://ftp.gnu.org/gnu/gmp/gmp-6.3.0.tar.xz + tar -xJf gmp-6.3.0.tar.xz + rm gmp-6.3.0.tar.xz + cd gmp-6.3.0 + ./configure --prefix="$RISCV" + make -j ${NUM_THREADS} + make install + cd "$RISCV" + rm -rf gmp-6.3.0 + fi fi # gcc cross-compiler (https://github.com/riscv-collab/riscv-gnu-toolchain) # To install GCC from source can take hours to compile. -# This configuration enables multilib to target many flavors of RISC-V. +# This configuration enables multilib to target many flavors of RISC-V. # This book is tested with GCC 13.2.0 echo -e "\n*************************************************************************" echo -e "*************************************************************************" @@ -236,11 +236,11 @@ echo -e "*********************************************************************** echo -e "*************************************************************************\n" cd "$RISCV" if [[ ((! -e riscv-gnu-toolchain) && ($(git clone https://github.com/riscv/riscv-gnu-toolchain) || true)) || ($(cd riscv-gnu-toolchain; git fetch; git rev-parse HEAD) != $(cd riscv-gnu-toolchain; git rev-parse origin/master)) || (! -e $RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2) ]]; then - cd riscv-gnu-toolchain - git checkout master - git pull - ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" - make -j ${NUM_THREADS} + cd riscv-gnu-toolchain + git checkout master + git pull + ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" + make -j ${NUM_THREADS} fi # elf2hex (https://github.com/sifive/elf2hex) @@ -258,12 +258,12 @@ echo -e "*********************************************************************** cd "$RISCV" export PATH=$RISCV/bin:$PATH if [[ ((! -e elf2hex) && ($(git clone https://github.com/sifive/elf2hex.git) || true)) || ($(cd elf2hex; git fetch; git rev-parse HEAD) != $(cd elf2hex; git rev-parse origin/master)) || (! -e $RISCV/bin/riscv64-unknown-elf-elf2bin) ]]; then - cd elf2hex - git reset --hard && git clean -f && git checkout master && git pull - autoreconf -i - ./configure --target=riscv64-unknown-elf --prefix="$RISCV" - make - make install + cd elf2hex + git reset --hard && git clean -f && git checkout master && git pull + autoreconf -i + ./configure --target=riscv64-unknown-elf --prefix="$RISCV" + make + make install fi # QEMU (https://www.qemu.org/docs/master/system/target-riscv.html) @@ -274,11 +274,11 @@ echo -e "*********************************************************************** echo -e "*************************************************************************\n" cd "$RISCV" if [[ ((! -e qemu) && ($(git clone --recurse-submodules https://github.com/qemu/qemu) || true)) || ($(cd qemu; git fetch --recurse-submodules=yes; git rev-parse HEAD) != $(cd qemu; git rev-parse origin/master)) || (! -e $RISCV/include/qemu-plugin.h) ]]; then - cd qemu - git reset --hard && git clean -f && git checkout master && git pull --recurse-submodules - ./configure --target-list=riscv64-softmmu --prefix="$RISCV" - make -j ${NUM_THREADS} - make install + cd qemu + git reset --hard && git clean -f && git checkout master && git pull --recurse-submodules + ./configure --target-list=riscv64-softmmu --prefix="$RISCV" + make -j ${NUM_THREADS} + make install fi # Spike (https://github.com/riscv-software-src/riscv-isa-sim) @@ -291,13 +291,13 @@ echo -e "*********************************************************************** echo -e "*************************************************************************\n" cd "$RISCV" if [[ ((! -e riscv-isa-sim) && ($(git clone https://github.com/riscv-software-src/riscv-isa-sim) || true)) || ($(cd riscv-isa-sim; git fetch; git rev-parse HEAD) != $(cd riscv-isa-sim; git rev-parse origin/master)) || (! -e $RISCV/lib/pkgconfig/riscv-riscv.pc) ]]; then - cd riscv-isa-sim - git reset --hard && git clean -f && git checkout master && git pull - mkdir -p build - cd build - ../configure --prefix="$RISCV" - make -j ${NUM_THREADS} - make install + cd riscv-isa-sim + git reset --hard && git clean -f && git checkout master && git pull + mkdir -p build + cd build + ../configure --prefix="$RISCV" + make -j ${NUM_THREADS} + make install fi # Wally needs Verilator 5.021 or later. @@ -309,14 +309,14 @@ echo -e "*********************************************************************** echo -e "*************************************************************************\n" cd "$RISCV" if [[ ((! -e verilator) && ($(git clone https://github.com/verilator/verilator) || true)) || ($(cd verilator; git fetch; git rev-parse HEAD) != $(cd verilator; git rev-parse origin/master)) || (! -e $RISCV/share/pkgconfig/verilator.pc) ]]; then - # unsetenv VERILATOR_ROOT # For csh; ignore error if on bash - unset VERILATOR_ROOT # For bash - cd verilator - git reset --hard && git clean -f && git checkout master && git pull - autoconf # Create ./configure script - ./configure --prefix="$RISCV" # Configure and create Makefile - make -j ${NUM_THREADS} # Build Verilator itself (if error, try just 'make') - make install + # unsetenv VERILATOR_ROOT # For csh; ignore error if on bash + unset VERILATOR_ROOT # For bash + cd verilator + git reset --hard && git clean -f && git checkout master && git pull + autoconf # Create ./configure script + ./configure --prefix="$RISCV" # Configure and create Makefile + make -j ${NUM_THREADS} # Build Verilator itself (if error, try just 'make') + make install fi # RISC-V Sail Model (https://github.com/riscv/sail-riscv) @@ -328,17 +328,17 @@ fi # but a binary release of it should be available soon, removing the need to use opam. cd "$RISCV" if [ "$FAMILY" = rhel ]; then - echo -e "\n*************************************************************************" - echo -e "*************************************************************************" - echo -e "Installing Opam" - echo -e "*************************************************************************" - echo -e "*************************************************************************\n" - mkdir -p opam - cd opam - wget https://raw.githubusercontent.com/ocaml/opam/master/shell/install.sh - printf '%s\n' "$RISCV"/bin Y | sh install.sh # the print command provides $RISCV/bin as the installation path when prompted - cd "$RISCV" - rm -rf opam + echo -e "\n*************************************************************************" + echo -e "*************************************************************************" + echo -e "Installing Opam" + echo -e "*************************************************************************" + echo -e "*************************************************************************\n" + mkdir -p opam + cd opam + wget https://raw.githubusercontent.com/ocaml/opam/master/shell/install.sh + printf '%s\n' "$RISCV"/bin Y | sh install.sh # the print command provides $RISCV/bin as the installation path when prompted + cd "$RISCV" + rm -rf opam fi echo -e "\n*************************************************************************" @@ -359,15 +359,15 @@ echo -e "Installing RISC-V Sail Model" echo -e "*************************************************************************" echo -e "*************************************************************************\n" if [[ ((! -e sail-riscv) && ($(git clone https://github.com/riscv/sail-riscv.git) || true)) || ($(cd sail-riscv; git fetch; git rev-parse HEAD) != $(cd sail-riscv; git rev-parse origin/master)) || (! -e $RISCV/bin/riscv_sim_RV32) ]]; then - eval $(opam config env) - cd sail-riscv - git reset --hard && git clean -f && git checkout master && git pull - export OPAMCLI=2.0 # Sail is not compatible with opam 2.1 as of 4/16/24 - ARCH=RV64 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV64 - ARCH=RV32 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV32 - cd "$RISCV" - ln -sf ../sail-riscv/c_emulator/riscv_sim_RV64 bin/riscv_sim_RV64 - ln -sf ../sail-riscv/c_emulator/riscv_sim_RV32 bin/riscv_sim_RV32 + eval $(opam config env) + cd sail-riscv + git reset --hard && git clean -f && git checkout master && git pull + export OPAMCLI=2.0 # Sail is not compatible with opam 2.1 as of 4/16/24 + ARCH=RV64 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV64 + ARCH=RV32 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV32 + cd "$RISCV" + ln -sf ../sail-riscv/c_emulator/riscv_sim_RV64 bin/riscv_sim_RV64 + ln -sf ../sail-riscv/c_emulator/riscv_sim_RV32 bin/riscv_sim_RV32 fi # riscof @@ -387,8 +387,8 @@ echo -e "*********************************************************************** mkdir -p "$RISCV"/cad/lib cd "$RISCV"/cad/lib if [[ ((! -e sky130_osu_sc_t12) && ($(git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12) || true)) || ($(cd sky130_osu_sc_t12; git fetch; git rev-parse HEAD) != $(cd sky130_osu_sc_t12; git rev-parse origin/main)) ]]; then - cd sky130_osu_sc_t12 - git reset --hard && git clean -f && git checkout main && git pull + cd sky130_osu_sc_t12 + git reset --hard && git clean -f && git checkout main && git pull fi # site-setup script @@ -399,9 +399,9 @@ echo -e "*********************************************************************** echo -e "*************************************************************************\n" cd "$RISCV" if [ ! -e "${RISCV}"/site-setup.sh ]; then - wget https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.sh - wget https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.csh - if [ "$FAMILY" = rhel ]; then - echo "source /opt/rh/gcc-toolset-13/enable" >> site-setup.sh - fi + wget https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.sh + wget https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.csh + if [ "$FAMILY" = rhel ]; then + echo "source /opt/rh/gcc-toolset-13/enable" >> site-setup.sh + fi fi diff --git a/setup.sh b/setup.sh index 3531b2bce..d8b511c6f 100644 --- a/setup.sh +++ b/setup.sh @@ -31,7 +31,7 @@ WALLY=$(dirname "${BASH_SOURCE[0]:-$0}") export WALLY=$(cd "$WALLY" && pwd) echo \$WALLY set to "${WALLY}" # utility functions in Wally repository -export PATH=$WALLY/bin:$PATH +export PATH=$WALLY/bin:$PATH # load site licenses and tool locations source "${RISCV}"/site-setup.sh diff --git a/site-setup.csh b/site-setup.csh index 2c18b6943..428ebb30e 100644 --- a/site-setup.csh +++ b/site-setup.csh @@ -41,7 +41,7 @@ limit stacksize unlimited setenv IDV $RISCV/ImperasDV-OpenHW if ($?IDV) then -# echo "Imperas exists" + # echo "Imperas exists" setenv IMPERAS_HOME $IDV/Imperas setenv IMPERAS_PERSONALITY CPUMAN_DV_ASYNC setenv ROOTDIR ~/ diff --git a/site-setup.sh b/site-setup.sh index dbbd2775c..53490e57a 100755 --- a/site-setup.sh +++ b/site-setup.sh @@ -38,12 +38,12 @@ export SPIKE_PATH=$RISCV/bin # Change this for your path to riscv-isa-s ulimit -c 234613 # Imperas OVPsim; put this in if you are using it -#export PATH=$RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:$PATH +#export PATH=$RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:$PATH #export LD_LIBRARY_PATH=$RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH export IDV=$RISCV/ImperasDV-OpenHW if [ -e "$IDV" ]; then -# echo "Imperas exists" + # echo "Imperas exists" export IMPERAS_HOME=$IDV/Imperas export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC export ROOTDIR=~/ From b3f04857d48415461d3a5e0df69772275310991f Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 29 Jun 2024 01:23:38 -0700 Subject: [PATCH 027/219] Initial Ubuntu 20.04 support --- bin/wally-tool-chain-install.sh | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 7620900c6..381de053e 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -67,6 +67,12 @@ elif [[ "$ID" = ubuntu || "$ID_LIKE" = *ubuntu* ]]; then if [ "$ID" != ubuntu ]; then printf "%s\n" "For Ubuntu family distros, the Wally install script has only been tested on standard Ubuntu. Your distro " \ "is $PRETTY_NAME. The regular Ubuntu install will be attempted, but there may be issues." + else + UBUNTU_VERSION="${VERSION_ID:0:2}" + if (( UBUNTU_VERSION < 20 )); then + echo "The Wally install script is only compatible with versions 20.04, 22.04, and 24.04 of Ubuntu. You have version $VERSION." + exit 1 + fi fi else printf "%s\n" "The Wally install script is currently only compatible with Ubuntu and Red Hat family " \ @@ -150,9 +156,13 @@ elif [ "$FAMILY" = ubuntu ]; then autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat1-dev ninja-build libglib2.0-dev libslirp-dev \ libfdt-dev libpixman-1-dev \ device-tree-compiler libboost-regex-dev libboost-system-dev \ - help2man perl g++ clang ccache libgoogle-perftools-dev numactl mold perl-doc libfl2 libfl-dev zlib1g \ + help2man perl g++ clang ccache libgoogle-perftools-dev numactl perl-doc libfl2 libfl-dev zlib1g \ opam z3 \ ncurses-base ncurses-bin libncurses-dev + # Extra packages not availale in Ubuntu 20.04, nice for verialtor + if (( UBUNTU_VERSION >= 22 )); then + sudo apt install -y mold + fi fi echo -e "\n*************************************************************************" @@ -184,8 +194,8 @@ if [ "$RHEL_VERSION" = 8 ]; then fi source "$RISCV"/riscv-python/bin/activate # reload python virtual environment -# Extra dependecies needed for rhel 8 that don't have new enough versions available from dnf -if [ "$RHEL_VERSION" = 8 ]; then +# Extra dependecies needed for older distros that don't have new enough versions available from package manager +if [ "$RHEL_VERSION" = 8 ] || (( UBUNTU_VERSION < 22 )); then # Newer versin of glib required for Qemu. # Anything newer than this won't build on red hat 8 if [ ! -e "$RISCV"/include/glib-2.0 ]; then @@ -205,7 +215,10 @@ if [ "$RHEL_VERSION" = 8 ]; then cd "$RISCV" rm -rf glib-2.70.5 fi - # Newer version of gmp needed for sail-riscv model +fi + +# Newer version of gmp needed for sail-riscv model +if [ "$RHEL_VERSION" = 8 ]; then if [ ! -e "$RISCV"/include/gmp.h ]; then echo -e "\n*************************************************************************" echo -e "*************************************************************************" From c503260b2f1ee53ab6175b9156418e3d76cadf64 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 29 Jun 2024 01:26:48 -0700 Subject: [PATCH 028/219] Additional Ubuntu 20.04 updates --- bin/wally-tool-chain-install.sh | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 381de053e..d952b1d7b 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -93,7 +93,7 @@ else fi export PATH=$PATH:$RISCV/bin:/usr/bin -export PKG_CONFIG_PATH=$RISCV/lib64/pkgconfig:$RISCV/lib/pkgconfig:$RISCV/share/pkgconfig:$PKG_CONFIG_PATH +export PKG_CONFIG_PATH=$RISCV/lib64/pkgconfig:$RISCV/lib/pkgconfig:$RISCV/share/pkgconfig:$RISCV/lib/x86_64-linux-gnu/pkgconfig:$PKG_CONFIG_PATH mkdir -p "$RISCV" echo "Detected information" @@ -188,9 +188,9 @@ pip install -U pip pip install -U sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown pyyaml testresources riscv_config pip install -U riscv_isac # to generate new tests, such as quads with fp_dataset.py -# z3 is eeded for sail and not availabe from dnf for rhel 8. Meson is needed to build extra dependencies +# z3 is eeded for sail and not availabe from dnf for rhel 8 if [ "$RHEL_VERSION" = 8 ]; then - pip install -U z3-solver meson + pip install -U z3-solver fi source "$RISCV"/riscv-python/bin/activate # reload python virtual environment @@ -204,6 +204,8 @@ if [ "$RHEL_VERSION" = 8 ] || (( UBUNTU_VERSION < 22 )); then echo -e "Installing glib" echo -e "*************************************************************************" echo -e "*************************************************************************\n" + # Meson is needed to build glib + pip install -U meson cd "$RISCV" wget https://download.gnome.org/sources/glib/2.70/glib-2.70.5.tar.xz tar -xJf glib-2.70.5.tar.xz From b8adac9beb28f038fb79ffb8dd41c470d2a2f10d Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 29 Jun 2024 10:45:42 -0700 Subject: [PATCH 029/219] Use gcc 10 for Ubuntu 20.04 for Verilator --- bin/wally-tool-chain-install.sh | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index d952b1d7b..4d67d887d 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -163,6 +163,15 @@ elif [ "$FAMILY" = ubuntu ]; then if (( UBUNTU_VERSION >= 22 )); then sudo apt install -y mold fi + # Newer version of gcc needed for Ubuntu 20.04 for Verilator + if (( UBUNTU_VERSION < 22 )); then + sudo apt install -y gcc-10 g++-10 cpp-10 + mkdir -p "$RISCV"/gcc-10/bin + for f in gcc cpp g++ gcc-ar gcc-nm gcc-ranlib gcov gcov-dump gcov-tool lto-dump; do + ln -vsf /usr/bin/$f-10 "$RISCV"/gcc-10/bin/$f + done + export PATH="$RISCV"/gcc-10/bin:$PATH + fi fi echo -e "\n*************************************************************************" @@ -418,5 +427,8 @@ if [ ! -e "${RISCV}"/site-setup.sh ]; then wget https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.csh if [ "$FAMILY" = rhel ]; then echo "source /opt/rh/gcc-toolset-13/enable" >> site-setup.sh + elif (( UBUNTU_VERSION < 22 )); then + echo "export PATH=\$RISCV/gcc-10/bin:\$PATH" >> site-setup.sh + echo "prepend PATH \$RISCV/gcc-10/bin" >> site-setup.csh fi fi From c47411b4e382a53efff75cad88831df8b16f731f Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 29 Jun 2024 12:37:58 -0700 Subject: [PATCH 030/219] Add support for AlmaLinux 8 and 9 (testing) --- bin/wally-tool-chain-install.sh | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 4d67d887d..cd6ed1638 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -50,8 +50,8 @@ source "$os_release" # Check for compatible distro if [[ "$ID" = rhel || "$ID_LIKE" = *rhel* ]]; then FAMILY=rhel - if [ "$ID" != rhel ] && [ "$ID" != rocky ]; then - printf "%s\n" "For Red Hat family distros, the Wally install script has only been tested on RHEL and Rocky Linux. Your distro " \ + if [ "$ID" != rhel ] && [ "$ID" != rocky ] && [ "$ID" != almalinux ]; then + printf "%s\n" "For Red Hat family distros, the Wally install script has only been tested on RHEL, Rocky Linux, and AlmaLinux. Your distro " \ "is $PRETTY_NAME. The regular Red Hat install will be attempted, but there will likely be issues." fi if [ "${VERSION_ID:0:1}" = 8 ]; then @@ -59,7 +59,7 @@ if [[ "$ID" = rhel || "$ID_LIKE" = *rhel* ]]; then elif [ "${VERSION_ID:0:1}" = 9 ]; then RHEL_VERSION=9 else - echo "The Wally install script is only compatible with versions 8 and 9 of RHEL and Rocky Linux. You have version $VERSION." + echo "The Wally install script is only compatible with versions 8 and 9 of RHEL, Rocky Linux, and AlmaLinux. You have version $VERSION." exit 1 fi elif [[ "$ID" = ubuntu || "$ID_LIKE" = *ubuntu* ]]; then @@ -76,7 +76,7 @@ elif [[ "$ID" = ubuntu || "$ID_LIKE" = *ubuntu* ]]; then fi else printf "%s\n" "The Wally install script is currently only compatible with Ubuntu and Red Hat family " \ - "(RHEL or Rocky Linux) distros. Your detected distro is $PRETTY_NAME. You may try manually running the " \ + "(RHEL, Rocky Linux, or AlmaLinux) distros. Your detected distro is $PRETTY_NAME. You may try manually running the " \ "commands in this script, but it is likely that some will need to be altered." exit 1 fi @@ -107,14 +107,14 @@ echo -e "*********************************************************************** echo -e "Installing Dependencies from Package Manager" echo -e "*************************************************************************" echo -e "*************************************************************************\n" -# Installs appropriate packages for rhel or ubuntu distros, picking apt or dnf appropriately +# Installs appropriate packages for red hat or ubuntu distros, picking apt or dnf appropriately if [ "$FAMILY" = rhel ]; then # Enable extra package repos sudo dnf install -y dnf-plugins-core if [ "$ID" = rhel ]; then sudo subscription-manager repos --enable "codeready-builder-for-rhel-$RHEL_VERSION-$(arch)-rpms" sudo dnf install -y "https://dl.fedoraproject.org/pub/epel/epel-release-latest-$RHEL_VERSION.noarch.rpm" - else + else # RHEL clone if [ "$RHEL_VERSION" = 8 ]; then sudo dnf config-manager -y --set-enabled powertools else # Version 9 From 4144f3f3c27fa85f62e98382f90aca9fe2bf2a40 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 29 Jun 2024 13:38:34 -0700 Subject: [PATCH 031/219] Fix regression from Ubuntu 20.04 support --- bin/wally-tool-chain-install.sh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index cd6ed1638..ce7ef2e10 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -164,7 +164,7 @@ elif [ "$FAMILY" = ubuntu ]; then sudo apt install -y mold fi # Newer version of gcc needed for Ubuntu 20.04 for Verilator - if (( UBUNTU_VERSION < 22 )); then + if [ "$UBUNTU_VERSION" = 20 ]; then sudo apt install -y gcc-10 g++-10 cpp-10 mkdir -p "$RISCV"/gcc-10/bin for f in gcc cpp g++ gcc-ar gcc-nm gcc-ranlib gcov gcov-dump gcov-tool lto-dump; do @@ -204,7 +204,7 @@ fi source "$RISCV"/riscv-python/bin/activate # reload python virtual environment # Extra dependecies needed for older distros that don't have new enough versions available from package manager -if [ "$RHEL_VERSION" = 8 ] || (( UBUNTU_VERSION < 22 )); then +if [ "$RHEL_VERSION" = 8 ] || [ "$UBUNTU_VERSION" = 20 ]; then # Newer versin of glib required for Qemu. # Anything newer than this won't build on red hat 8 if [ ! -e "$RISCV"/include/glib-2.0 ]; then @@ -427,7 +427,7 @@ if [ ! -e "${RISCV}"/site-setup.sh ]; then wget https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.csh if [ "$FAMILY" = rhel ]; then echo "source /opt/rh/gcc-toolset-13/enable" >> site-setup.sh - elif (( UBUNTU_VERSION < 22 )); then + elif [ "$UBUNTU_VERSION" = 20 ]; then echo "export PATH=\$RISCV/gcc-10/bin:\$PATH" >> site-setup.sh echo "prepend PATH \$RISCV/gcc-10/bin" >> site-setup.csh fi From 24de9e3cabb2b86fc93aba8f6e03f2c3328e005f Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 29 Jun 2024 13:49:05 -0700 Subject: [PATCH 032/219] Cleanup --- bin/wally-tool-chain-install.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index ce7ef2e10..3e20a05fe 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -261,7 +261,7 @@ echo -e "*********************************************************************** cd "$RISCV" if [[ ((! -e riscv-gnu-toolchain) && ($(git clone https://github.com/riscv/riscv-gnu-toolchain) || true)) || ($(cd riscv-gnu-toolchain; git fetch; git rev-parse HEAD) != $(cd riscv-gnu-toolchain; git rev-parse origin/master)) || (! -e $RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2) ]]; then cd riscv-gnu-toolchain - git checkout master + git reset --hard && git clean -f && git checkout master && git pull git pull ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" make -j ${NUM_THREADS} @@ -297,7 +297,7 @@ echo -e "Installing QEMU" echo -e "*************************************************************************" echo -e "*************************************************************************\n" cd "$RISCV" -if [[ ((! -e qemu) && ($(git clone --recurse-submodules https://github.com/qemu/qemu) || true)) || ($(cd qemu; git fetch --recurse-submodules=yes; git rev-parse HEAD) != $(cd qemu; git rev-parse origin/master)) || (! -e $RISCV/include/qemu-plugin.h) ]]; then +if [[ ((! -e qemu) && ($(git clone --recurse-submodules https://github.com/qemu/qemu) || true)) || ($(cd qemu; git fetch; git rev-parse HEAD) != $(cd qemu; git rev-parse origin/master)) || (! -e $RISCV/include/qemu-plugin.h) ]]; then cd qemu git reset --hard && git clean -f && git checkout master && git pull --recurse-submodules ./configure --target-list=riscv64-softmmu --prefix="$RISCV" From 355cbdd99c63f22992039b49a4ef5453498be9fc Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 29 Jun 2024 22:55:16 -0700 Subject: [PATCH 033/219] Increase ulimit for verilator --- site-setup.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/site-setup.sh b/site-setup.sh index 53490e57a..4750e039d 100755 --- a/site-setup.sh +++ b/site-setup.sh @@ -35,7 +35,7 @@ export RISCV_OBJCOPY=$(which riscv64-unknown-elf-objcopy) # Copy this as export SPIKE_PATH=$RISCV/bin # Change this for your path to riscv-isa-sim (spike) # Verilator needs a larger stack to simulate CORE-V Wally -ulimit -c 234613 +ulimit -c 300000 # Imperas OVPsim; put this in if you are using it #export PATH=$RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:$PATH From 547a859ed83c2677243eb69798435f44fcdafc83 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 30 Jun 2024 11:34:57 -0700 Subject: [PATCH 034/219] Clean up .gitmodules file to eliminate warnings when cloning --- .gitmodules | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/.gitmodules b/.gitmodules index ca097a125..b5ae648b7 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,9 +1,3 @@ -[submodule "sky130/sky130_osu_sc_t12"] - path = sky130/sky130_osu_sc_t12 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12/ -[submodule "addins/imperas-riscv-tests"] - path = addins/imperas-riscv-tests - url = https://github.com/riscv-ovpsim/imperas-riscv-tests [submodule "addins/riscv-dv"] path = addins/riscv-dv url = https://github.com/google/riscv-dv @@ -29,4 +23,4 @@ url = https://github.com/ross144/branch-predictor-simulator [submodule "addins/ahbsdc"] path = addins/ahbsdc - url = http://github.com/JacobPease/ahbsdc.git + url = https://github.com/JacobPease/ahbsdc.git From 53bda7fe406fbe244bd7dc1d253021ea9bf8d7d5 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 30 Jun 2024 15:48:28 -0700 Subject: [PATCH 035/219] Improve print messages --- bin/wally-tool-chain-install.sh | 158 +++++++++++++++++++++----------- 1 file changed, 102 insertions(+), 56 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 3e20a05fe..3ba192249 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -6,7 +6,7 @@ ## Created: 18 January 2023 ## Modified: 22 January 2023 ## Modified: 23 March 2023 -## Modified for Red Hat: June 20 2024, Jordan Carlin jcarlin@hmc.edu +## Modified: 30 June 2024, Jordan Carlin jcarlin@hmc.edu ## ## Purpose: Open source tool chain installation script ## @@ -35,11 +35,21 @@ NUM_THREADS=8 # for >= 32GiB #NUM_THREADS=16 # for >= 64GiB -echo -e "\n*************************************************************************" +# Colors +BOLD='\033[1m' +UNDERLINE='\033[4m' +SECTION_COLOR='\033[95m'$BOLD +OK_COLOR='\033[94m' +SUCCESS_COLOR='\033[92m' +WARNING_COLOR='\033[93m' +FAIL_COLOR='\033[91m' +ENDC='\033[0m' + +echo -e "${SECTION_COLOR}\n*************************************************************************" echo -e "*************************************************************************" -echo -e "Checking Distro and Permissions and Setting Installation Directory" +echo -e "Checking System Requirements and Configuring Installation" echo -e "*************************************************************************" -echo -e "*************************************************************************\n" +echo -e "*************************************************************************\n${ENDC}" set -e # break on error @@ -51,31 +61,31 @@ source "$os_release" if [[ "$ID" = rhel || "$ID_LIKE" = *rhel* ]]; then FAMILY=rhel if [ "$ID" != rhel ] && [ "$ID" != rocky ] && [ "$ID" != almalinux ]; then - printf "%s\n" "For Red Hat family distros, the Wally install script has only been tested on RHEL, Rocky Linux, and AlmaLinux. Your distro " \ - "is $PRETTY_NAME. The regular Red Hat install will be attempted, but there will likely be issues." + printf "${WARNING_COLOR}%s\n${ENDC}" "For Red Hat family distros, the Wally install script has only been tested on RHEL, Rocky Linux," \ + " and AlmaLinux. Your distro is $PRETTY_NAME. The regular Red Hat install will be attempted, but there will likely be issues." fi if [ "${VERSION_ID:0:1}" = 8 ]; then RHEL_VERSION=8 elif [ "${VERSION_ID:0:1}" = 9 ]; then RHEL_VERSION=9 else - echo "The Wally install script is only compatible with versions 8 and 9 of RHEL, Rocky Linux, and AlmaLinux. You have version $VERSION." + echo "${FAIL_COLOR}The Wally install script is only compatible with versions 8 and 9 of RHEL, Rocky Linux, and AlmaLinux. You have version $VERSION.${ENDC}" exit 1 fi elif [[ "$ID" = ubuntu || "$ID_LIKE" = *ubuntu* ]]; then FAMILY=ubuntu if [ "$ID" != ubuntu ]; then - printf "%s\n" "For Ubuntu family distros, the Wally install script has only been tested on standard Ubuntu. Your distro " \ + printf "${WARNING_COLOR}%s\n${ENDC}" "For Ubuntu family distros, the Wally install script has only been tested on standard Ubuntu. Your distro " \ "is $PRETTY_NAME. The regular Ubuntu install will be attempted, but there may be issues." else UBUNTU_VERSION="${VERSION_ID:0:2}" if (( UBUNTU_VERSION < 20 )); then - echo "The Wally install script is only compatible with versions 20.04, 22.04, and 24.04 of Ubuntu. You have version $VERSION." + echo "${FAIL_COLOR}The Wally install script is only compatible with versions 20.04, 22.04, and 24.04 of Ubuntu. You have version $VERSION.${ENDC}" exit 1 fi fi else - printf "%s\n" "The Wally install script is currently only compatible with Ubuntu and Red Hat family " \ + printf "${FAIL_COLOR}%s\n${ENDC}" "The Wally install script is currently only compatible with Ubuntu and Red Hat family " \ "(RHEL, Rocky Linux, or AlmaLinux) distros. Your detected distro is $PRETTY_NAME. You may try manually running the " \ "commands in this script, but it is likely that some will need to be altered." exit 1 @@ -96,17 +106,17 @@ export PATH=$PATH:$RISCV/bin:/usr/bin export PKG_CONFIG_PATH=$RISCV/lib64/pkgconfig:$RISCV/lib/pkgconfig:$RISCV/share/pkgconfig:$RISCV/lib/x86_64-linux-gnu/pkgconfig:$PKG_CONFIG_PATH mkdir -p "$RISCV" -echo "Detected information" +echo "${OK_COLOR}${UNDERLINE}Detected information${ENDC}" echo "Distribution: $PRETTY_NAME" echo "Version: $VERSION" echo "Running as root: $ROOT" echo "Installation path: $RISCV" -echo -e "\n*************************************************************************" +echo -e "${SECTION_COLOR}\n*************************************************************************" echo -e "*************************************************************************" -echo -e "Installing Dependencies from Package Manager" +echo -e "Installing/Updating Dependencies from Package Manager" echo -e "*************************************************************************" -echo -e "*************************************************************************\n" +echo -e "*************************************************************************\n${ENDC}" # Installs appropriate packages for red hat or ubuntu distros, picking apt or dnf appropriately if [ "$FAMILY" = rhel ]; then # Enable extra package repos @@ -130,12 +140,12 @@ if [ "$FAMILY" = rhel ]; then # Packages are grouped by which tool requires them, split by line. # If mutltipole tools need a package, it is included in the first tool only # General/Wally specific, riscv-gnu-toolchain, qemu, spike, verilator, buildroot - sudo dnf install -y git make cmake python3.12 python3-pip curl wget ftp tar pkgconfig dialog mutt ssmtp gcc-gfortran \ + sudo dnf install -y git make cmake python3.12 python3-pip curl wget ftp tar pkgconfig dialog mutt ssmtp \ autoconf automake libmpc-devel mpfr-devel gmp-devel gawk bison flex texinfo gperf libtool patchutils bc gcc gcc-c++ zlib-devel expat-devel libslirp-devel \ glib2-devel libfdt-devel pixman-devel bzip2 ninja-build \ dtc boost-regex boost-system \ help2man perl clang ccache gperftools numactl mold \ - ncurses-base ncurses ncurses-libs ncurses-devel + ncurses-base ncurses ncurses-libs ncurses-devel gcc-gfortran # Extra packages not availale in rhel8, nice for verialtor and needed for sail respectively if [ "$RHEL_VERSION" = 9 ]; then sudo dnf install -y perl-doc z3 @@ -152,13 +162,13 @@ elif [ "$FAMILY" = ubuntu ]; then # Packages are grouped by which tool requires them, split by line. # If mutltipole tools need a package, it is included in the first tool only # General/Wally specific, riscv-gnu-toolchain, qemu, spike, verilator, sail, buildroot - sudo apt install -y git make cmake python3 python3-pip python3-venv curl wget ftp tar pkg-config dialog mutt ssmtp gfortran \ + sudo apt install -y git make cmake python3 python3-pip python3-venv curl wget ftp tar pkg-config dialog mutt ssmtp \ autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat1-dev ninja-build libglib2.0-dev libslirp-dev \ libfdt-dev libpixman-1-dev \ device-tree-compiler libboost-regex-dev libboost-system-dev \ help2man perl g++ clang ccache libgoogle-perftools-dev numactl perl-doc libfl2 libfl-dev zlib1g \ opam z3 \ - ncurses-base ncurses-bin libncurses-dev + ncurses-base ncurses-bin libncurses-dev gfortran # Extra packages not availale in Ubuntu 20.04, nice for verialtor if (( UBUNTU_VERSION >= 22 )); then sudo apt install -y mold @@ -174,11 +184,13 @@ elif [ "$FAMILY" = ubuntu ]; then fi fi -echo -e "\n*************************************************************************" +echo -e "${SUCCESS_COLOR}Packages successfully installed.${ENDC}" + +echo -e "${SECTION_COLOR}\n*************************************************************************" echo -e "*************************************************************************" echo -e "Setting up Python Environment" echo -e "*************************************************************************" -echo -e "*************************************************************************\n" +echo -e "*************************************************************************\n${ENDC}" # Create python virtual environment so the python command targets our desired version of python # and installed packages are isolated from the rest of the system. cd "$RISCV" @@ -189,6 +201,9 @@ if [ ! -e "$RISCV"/riscv-python/bin/activate ]; then else python3 -m venv riscv-python fi + echo -e "${OK_COLOR}Python virtual environment created.\nInstalling pip packages.${ENDC}" +else + echo -e "${OK_COLOR}Python virtual environment already exists.\Updating pip packages.${ENDC}" fi source "$RISCV"/riscv-python/bin/activate # activate python virtual environment @@ -202,17 +217,18 @@ if [ "$RHEL_VERSION" = 8 ]; then pip install -U z3-solver fi source "$RISCV"/riscv-python/bin/activate # reload python virtual environment +echo -e "${SUCCESS_COLOR}Python environment successfully configured.${ENDC}" # Extra dependecies needed for older distros that don't have new enough versions available from package manager if [ "$RHEL_VERSION" = 8 ] || [ "$UBUNTU_VERSION" = 20 ]; then # Newer versin of glib required for Qemu. # Anything newer than this won't build on red hat 8 if [ ! -e "$RISCV"/include/glib-2.0 ]; then - echo -e "\n*************************************************************************" + echo -e "${SECTION_COLOR}\n*************************************************************************" echo -e "*************************************************************************" echo -e "Installing glib" echo -e "*************************************************************************" - echo -e "*************************************************************************\n" + echo -e "*************************************************************************\n${ENDC}" # Meson is needed to build glib pip install -U meson cd "$RISCV" @@ -225,17 +241,18 @@ if [ "$RHEL_VERSION" = 8 ] || [ "$UBUNTU_VERSION" = 20 ]; then meson install -C _build cd "$RISCV" rm -rf glib-2.70.5 + echo -e "${SUCCESS_COLOR}glib successfully installed${ENDC}" fi fi # Newer version of gmp needed for sail-riscv model if [ "$RHEL_VERSION" = 8 ]; then if [ ! -e "$RISCV"/include/gmp.h ]; then - echo -e "\n*************************************************************************" + echo -e "${SECTION_COLOR}\n*************************************************************************" echo -e "*************************************************************************" echo -e "Installing gmp" echo -e "*************************************************************************" - echo -e "*************************************************************************\n" + echo -e "*************************************************************************\n${ENDC}" cd "$RISCV" wget https://ftp.gnu.org/gnu/gmp/gmp-6.3.0.tar.xz tar -xJf gmp-6.3.0.tar.xz @@ -246,6 +263,7 @@ if [ "$RHEL_VERSION" = 8 ]; then make install cd "$RISCV" rm -rf gmp-6.3.0 + echo -e "${SUCCESS_COLOR}gmp successfully installed${ENDC}" fi fi @@ -253,11 +271,11 @@ fi # To install GCC from source can take hours to compile. # This configuration enables multilib to target many flavors of RISC-V. # This book is tested with GCC 13.2.0 -echo -e "\n*************************************************************************" +echo -e "${SECTION_COLOR}\n*************************************************************************" echo -e "*************************************************************************" -echo -e "Installing RISC-V GNU Toolchain" +echo -e "Installing/Updating RISC-V GNU Toolchain" echo -e "*************************************************************************" -echo -e "*************************************************************************\n" +echo -e "*************************************************************************\n${ENDC}" cd "$RISCV" if [[ ((! -e riscv-gnu-toolchain) && ($(git clone https://github.com/riscv/riscv-gnu-toolchain) || true)) || ($(cd riscv-gnu-toolchain; git fetch; git rev-parse HEAD) != $(cd riscv-gnu-toolchain; git rev-parse origin/master)) || (! -e $RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2) ]]; then cd riscv-gnu-toolchain @@ -265,6 +283,9 @@ if [[ ((! -e riscv-gnu-toolchain) && ($(git clone https://github.com/riscv/riscv git pull ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" make -j ${NUM_THREADS} + echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain successfully installed${ENDC}" +else + echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain already up to date${ENDC}" fi # elf2hex (https://github.com/sifive/elf2hex) @@ -274,11 +295,11 @@ fi # For example, if Python version 2.x is in your path, it won’t install correctly. # Also, be sure riscv64-unknown-elf-objcopy shows up in your path in $RISCV/riscv-gnu-toolchain/bin # at the time of compilation, or elf2hex won’t work properly. -echo -e "\n*************************************************************************" +echo -e "${SECTION_COLOR}\n*************************************************************************" echo -e "*************************************************************************" -echo -e "Installing elf2hex" +echo -e "Installing/Updating elf2hex" echo -e "*************************************************************************" -echo -e "*************************************************************************\n" +echo -e "*************************************************************************\n${ENDC}" cd "$RISCV" export PATH=$RISCV/bin:$PATH if [[ ((! -e elf2hex) && ($(git clone https://github.com/sifive/elf2hex.git) || true)) || ($(cd elf2hex; git fetch; git rev-parse HEAD) != $(cd elf2hex; git rev-parse origin/master)) || (! -e $RISCV/bin/riscv64-unknown-elf-elf2bin) ]]; then @@ -288,14 +309,17 @@ if [[ ((! -e elf2hex) && ($(git clone https://github.com/sifive/elf2hex.git) || ./configure --target=riscv64-unknown-elf --prefix="$RISCV" make make install + echo -e "${SUCCESS_COLOR}elf2hex successfully installed${ENDC}" +else + echo -e "${SUCCESS_COLOR}elf2hex already up to date${ENDC}" fi # QEMU (https://www.qemu.org/docs/master/system/target-riscv.html) -echo -e "\n*************************************************************************" +echo -e "${SECTION_COLOR}\n*************************************************************************" echo -e "*************************************************************************" -echo -e "Installing QEMU" +echo -e "Installing/Updating QEMU" echo -e "*************************************************************************" -echo -e "*************************************************************************\n" +echo -e "*************************************************************************\n${ENDC}" cd "$RISCV" if [[ ((! -e qemu) && ($(git clone --recurse-submodules https://github.com/qemu/qemu) || true)) || ($(cd qemu; git fetch; git rev-parse HEAD) != $(cd qemu; git rev-parse origin/master)) || (! -e $RISCV/include/qemu-plugin.h) ]]; then cd qemu @@ -303,16 +327,19 @@ if [[ ((! -e qemu) && ($(git clone --recurse-submodules https://github.com/qemu/ ./configure --target-list=riscv64-softmmu --prefix="$RISCV" make -j ${NUM_THREADS} make install + echo -e "${SUCCESS_COLOR}QEMU successfully installed${ENDC}" +else + echo -e "${SUCCESS_COLOR}QEMU already up to date${ENDC}" fi # Spike (https://github.com/riscv-software-src/riscv-isa-sim) # Spike also takes a while to install and compile, but this can be done concurrently # with the GCC installation. -echo -e "\n*************************************************************************" +echo -e "${SECTION_COLOR}\n*************************************************************************" echo -e "*************************************************************************" -echo -e "Installing SPIKE" +echo -e "Installing/Updating SPIKE" echo -e "*************************************************************************" -echo -e "*************************************************************************\n" +echo -e "*************************************************************************\n${ENDC}" cd "$RISCV" if [[ ((! -e riscv-isa-sim) && ($(git clone https://github.com/riscv-software-src/riscv-isa-sim) || true)) || ($(cd riscv-isa-sim; git fetch; git rev-parse HEAD) != $(cd riscv-isa-sim; git rev-parse origin/master)) || (! -e $RISCV/lib/pkgconfig/riscv-riscv.pc) ]]; then cd riscv-isa-sim @@ -322,15 +349,18 @@ if [[ ((! -e riscv-isa-sim) && ($(git clone https://github.com/riscv-software-sr ../configure --prefix="$RISCV" make -j ${NUM_THREADS} make install + echo -e "${SUCCESS_COLOR}Spike successfully installed${ENDC}" +else + echo -e "${SUCCESS_COLOR}Spike already up to date${ENDC}" fi # Wally needs Verilator 5.021 or later. # Verilator needs to be built from source to get the latest version -echo -e "\n*************************************************************************" +echo -e "\n${SECTION_COLOR}*************************************************************************" echo -e "*************************************************************************" -echo -e "Installing Verilator" +echo -e "Installing/Updating Verilator" echo -e "*************************************************************************" -echo -e "*************************************************************************\n" +echo -e "*************************************************************************\n${ENDC}" cd "$RISCV" if [[ ((! -e verilator) && ($(git clone https://github.com/verilator/verilator) || true)) || ($(cd verilator; git fetch; git rev-parse HEAD) != $(cd verilator; git rev-parse origin/master)) || (! -e $RISCV/share/pkgconfig/verilator.pc) ]]; then # unsetenv VERILATOR_ROOT # For csh; ignore error if on bash @@ -341,6 +371,9 @@ if [[ ((! -e verilator) && ($(git clone https://github.com/verilator/verilator) ./configure --prefix="$RISCV" # Configure and create Makefile make -j ${NUM_THREADS} # Build Verilator itself (if error, try just 'make') make install + echo -e "${SUCCESS_COLOR}Verilator successfully installed${ENDC}" +else + echo -e "${SUCCESS_COLOR}Verilator already up to date${ENDC}" fi # RISC-V Sail Model (https://github.com/riscv/sail-riscv) @@ -352,36 +385,38 @@ fi # but a binary release of it should be available soon, removing the need to use opam. cd "$RISCV" if [ "$FAMILY" = rhel ]; then - echo -e "\n*************************************************************************" + echo -e "${SECTION_COLOR}\n*************************************************************************" echo -e "*************************************************************************" - echo -e "Installing Opam" + echo -e "Installing/Updating Opam" echo -e "*************************************************************************" - echo -e "*************************************************************************\n" + echo -e "*************************************************************************\n${ENDC}" mkdir -p opam cd opam wget https://raw.githubusercontent.com/ocaml/opam/master/shell/install.sh printf '%s\n' "$RISCV"/bin Y | sh install.sh # the print command provides $RISCV/bin as the installation path when prompted cd "$RISCV" rm -rf opam + echo -e "${SUCCESS_COLOR}Opam successfully installed/updated${ENDC}" fi -echo -e "\n*************************************************************************" +echo -e "${SECTION_COLOR}\n*************************************************************************" echo -e "*************************************************************************" -echo -e "Installing Sail Compiler" +echo -e "Installing/Updating Sail Compiler" echo -e "*************************************************************************" -echo -e "*************************************************************************\n" +echo -e "*************************************************************************\n${ENDC}" cd "$RISCV" opam init -y --disable-sandboxing opam update -y opam upgrade -y opam switch create 5.1.0 || opam switch set 5.1.0 opam install sail -y +echo -e "${SUCCESS_COLOR}Sail Compiler successfully installed/updated${ENDC}" -echo -e "\n*************************************************************************" +echo -e "${SECTION_COLOR}\n*************************************************************************" echo -e "*************************************************************************" -echo -e "Installing RISC-V Sail Model" +echo -e "Installing/Updating RISC-V Sail Model" echo -e "*************************************************************************" -echo -e "*************************************************************************\n" +echo -e "*************************************************************************\n${ENDC}" if [[ ((! -e sail-riscv) && ($(git clone https://github.com/riscv/sail-riscv.git) || true)) || ($(cd sail-riscv; git fetch; git rev-parse HEAD) != $(cd sail-riscv; git rev-parse origin/master)) || (! -e $RISCV/bin/riscv_sim_RV32) ]]; then eval $(opam config env) cd sail-riscv @@ -392,35 +427,41 @@ if [[ ((! -e sail-riscv) && ($(git clone https://github.com/riscv/sail-riscv.git cd "$RISCV" ln -sf ../sail-riscv/c_emulator/riscv_sim_RV64 bin/riscv_sim_RV64 ln -sf ../sail-riscv/c_emulator/riscv_sim_RV32 bin/riscv_sim_RV32 + echo -e "${SUCCESS_COLOR}RISC-V Sail Model successfully installed${ENDC}" +else + echo -e "${SUCCESS_COLOR}RISC-V Sail Model already up to date${ENDC}" fi # riscof -echo -e "\n*************************************************************************" +echo -e "${SECTION_COLOR}\n*************************************************************************" echo -e "*************************************************************************" -echo -e "Installing Riscof" +echo -e "Installing/Updating RISCOF" echo -e "*************************************************************************" -echo -e "*************************************************************************\n" +echo -e "*************************************************************************\n${ENDC}" pip3 install git+https://github.com/riscv/riscof.git # Download OSU Skywater 130 cell library -echo -e "\n*************************************************************************" +echo -e "${SECTION_COLOR}\n*************************************************************************" echo -e "*************************************************************************" -echo -e "Installing OSU Skywater 130 cell library" +echo -e "Installing/Updating OSU Skywater 130 cell library" echo -e "*************************************************************************" -echo -e "*************************************************************************\n" +echo -e "*************************************************************************\n${ENDC}" mkdir -p "$RISCV"/cad/lib cd "$RISCV"/cad/lib if [[ ((! -e sky130_osu_sc_t12) && ($(git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12) || true)) || ($(cd sky130_osu_sc_t12; git fetch; git rev-parse HEAD) != $(cd sky130_osu_sc_t12; git rev-parse origin/main)) ]]; then cd sky130_osu_sc_t12 git reset --hard && git clean -f && git checkout main && git pull + echo -e "${SUCCESS_COLOR}OSU Skywater library successfully installed${ENDC}" +else + echo -e "${SUCCESS_COLOR}OSU Skywater library already up to date${ENDC}" fi # site-setup script -echo -e "\n*************************************************************************" +echo -e "${SECTION_COLOR}\n*************************************************************************" echo -e "*************************************************************************" echo -e "Downloading Site Setup Script" echo -e "*************************************************************************" -echo -e "*************************************************************************\n" +echo -e "*************************************************************************\n${ENDC}" cd "$RISCV" if [ ! -e "${RISCV}"/site-setup.sh ]; then wget https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.sh @@ -431,4 +472,9 @@ if [ ! -e "${RISCV}"/site-setup.sh ]; then echo "export PATH=\$RISCV/gcc-10/bin:\$PATH" >> site-setup.sh echo "prepend PATH \$RISCV/gcc-10/bin" >> site-setup.csh fi + echo -e "${SUCCESS_COLOR}Site setup script successfully downloaded${ENDC}" +else + echo -e "${OK_COLOR}Site setup script already exists. Not checking for updates to avoid overwritng modifications${ENDC}" fi + +echo -e "${SUCCESS_COLOR}${BOLD}\n\nINSTALLATION SUCCESSFUL\n\n${ENDC}" From bd6fa79a18fd3fec80f7e92d6356886bbefbabdc Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 30 Jun 2024 16:31:40 -0700 Subject: [PATCH 036/219] Cleanup root detection logic --- bin/wally-tool-chain-install.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 3ba192249..f41b896d1 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -92,11 +92,11 @@ else fi # Check if root -ROOT=$( [ "${EUID:=$(id -u)}" = 0 ] && echo true || echo false); +ROOT=$( [ "${EUID:=$(id -u)}" = 0 ] && echo true) # All tools will be installed under the $RISCV directory. By default, if run as root (with sudo) this is set to # /opt/riscv. Otherwise, it is set to ~/riscv. This value can be overridden with an argument passed to the script. -if [ "$ROOT" = true ]; then +if [ "$ROOT" ]; then export RISCV="${1:-/opt/riscv}" else export RISCV="${1:-$HOME/riscv}" From 459b659c50fa2a8a73bf01a17892f0ee69f41719 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 2 Jul 2024 21:25:52 -0700 Subject: [PATCH 037/219] Move package installation and distro check to separate files --- bin/wally-distro-check.sh | 87 +++++++++++++++++++ bin/wally-package-install.sh | 131 +++++++++++++++++++++++++++++ bin/wally-tool-chain-install.sh | 143 +++++--------------------------- 3 files changed, 240 insertions(+), 121 deletions(-) create mode 100755 bin/wally-distro-check.sh create mode 100755 bin/wally-package-install.sh diff --git a/bin/wally-distro-check.sh b/bin/wally-distro-check.sh new file mode 100755 index 000000000..79a62dfd0 --- /dev/null +++ b/bin/wally-distro-check.sh @@ -0,0 +1,87 @@ +#!/bin/bash +########################################### +## Get Linux distro information +## +## Written: Jordan Carlin, jcarlin@hmc.edu +## Created: 30 June 2024 +## Modified: +## +## Purpose: Check for compatible Linux distibution and set variables accordingly +## +## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https:##solderpad.org/licenses/SHL-2.1/ +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ + +set -e # break on error + +# Colors +BOLD='\033[1m' +UNDERLINE='\033[4m' +SECTION_COLOR='\033[95m'$BOLD +OK_COLOR='\033[94m' +WARNING_COLOR='\033[93m' +FAIL_COLOR='\033[91m' +ENDC='\033[0m' + +echo -e "${SECTION_COLOR}\n*************************************************************************" +echo -e "*************************************************************************" +echo -e "Checking System Requirements and Configuring Installation" +echo -e "*************************************************************************" +echo -e "*************************************************************************\n${ENDC}" + +# Get distribution information +test -e /etc/os-release && os_release="/etc/os-release" || os_release="/usr/lib/os-release" +source "$os_release" + +# Check for compatible distro +if [[ "$ID" = rhel || "$ID_LIKE" = *rhel* ]]; then + FAMILY=rhel + if [ "$ID" != rhel ] && [ "$ID" != rocky ] && [ "$ID" != almalinux ]; then + printf "${WARNING_COLOR}%s\n${ENDC}" "For Red Hat family distros, the Wally install script has only been tested on RHEL, Rocky Linux," \ + " and AlmaLinux. Your distro is $PRETTY_NAME. The regular Red Hat install will be attempted, but there will likely be issues." + fi + if [ "${VERSION_ID:0:1}" = 8 ]; then + RHEL_VERSION=8 + elif [ "${VERSION_ID:0:1}" = 9 ]; then + RHEL_VERSION=9 + else + echo "${FAIL_COLOR}The Wally install script is only compatible with versions 8 and 9 of RHEL, Rocky Linux, and AlmaLinux. You have version $VERSION.${ENDC}" + exit 1 + fi +elif [[ "$ID" = ubuntu || "$ID_LIKE" = *ubuntu* ]]; then + FAMILY=ubuntu + if [ "$ID" != ubuntu ]; then + printf "${WARNING_COLOR}%s\n${ENDC}" "For Ubuntu family distros, the Wally install script has only been tested on standard Ubuntu. Your distro " \ + "is $PRETTY_NAME. The regular Ubuntu install will be attempted, but there may be issues." + else + UBUNTU_VERSION="${VERSION_ID:0:2}" + if (( UBUNTU_VERSION < 20 )); then + echo "${FAIL_COLOR}The Wally install script is only compatible with versions 20.04, 22.04, and 24.04 of Ubuntu. You have version $VERSION.${ENDC}" + exit 1 + fi + fi +else + printf "${FAIL_COLOR}%s\n${ENDC}" "The Wally install script is currently only compatible with Ubuntu and Red Hat family " \ + "(RHEL, Rocky Linux, or AlmaLinux) distros. Your detected distro is $PRETTY_NAME. You may try manually running the " \ + "commands in this script, but it is likely that some will need to be altered." + exit 1 +fi + +echo -e "${OK_COLOR}${UNDERLINE}Detected information${ENDC}" +echo "Distribution: $PRETTY_NAME" +echo "Version: $VERSION" diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh new file mode 100755 index 000000000..f012fe259 --- /dev/null +++ b/bin/wally-package-install.sh @@ -0,0 +1,131 @@ +#!/bin/bash +########################################### +## Package installation +## +## Written: Jordan Carlin, jcarlin@hmc.edu +## Created: 30 June 2024 +## Modified: +## +## Purpose: Package manager installation for open source tool chain installation script +## +## A component of the CORE-V-WALLY configurable RISC-V project. +## https://github.com/openhwgroup/cvw +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https:##solderpad.org/licenses/SHL-2.1/ +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ + +set -e # break on error + +# Colors +BOLD='\033[1m' +SECTION_COLOR='\033[95m'$BOLD +SUCCESS_COLOR='\033[92m' +FAIL_COLOR='\033[91m' +ENDC='\033[0m' + +# If run standalone, determine distro information. Otherwise, use info from main install script +if [ -z "$FAMILY" ]; then + source wally-distro-check.sh +fi + +# Generate list of packages to install, determined based on distro +if [ "$FAMILY" = rhel ]; then + PACKAGE_MANAGER="dnf" + UPDATE_COMMAND="sudo dnf update -y" + # Packages are grouped by which tool requires them. If multiple tools need a package, it is included in the first tool only + GENERAL_PACKAGES="git make cmake python3.12 python3-pip curl wget ftp tar pkgconf-pkg-config dialog mutt ssmtp" + GNU_PACKAGES="autoconf automake libmpc-devel mpfr-devel gmp-devel gawk bison flex texinfo gperf libtool patchutils bc gcc gcc-c++ zlib-devel expat-devel libslirp-devel" + QEMU_PACKAGES="glib2-devel libfdt-devel pixman-devel bzip2 ninja-build" + SPIKE_PACKAGES="dtc boost-regex boost-system" + VERILATOR_PACKAGES="help2man perl clang ccache gperftools numactl mold" + BUILDROOT_PACKAGES="ncurses-base ncurses ncurses-libs ncurses-devel gcc-gfortran" + # Extra packages not availale in rhel8, nice for Verilator and needed for sail respectively + if [ "$RHEL_VERSION" = 9 ]; then + VERILATOR_PACKAGES="$VERILATOR_PACKAGES perl-doc" + SAIL_PACKAGES="z3" + fi + # A newer version of gcc is required for qemu + OTHER_PACKAGES="gcc-toolset-13" +elif [ "$FAMILY" = ubuntu ]; then + PACKAGE_MANAGER=apt + UPDATE_COMMAND="sudo apt update -y && sudo apt upgrade -y" + # Packages are grouped by which tool requires them. If multiple tools need a package, it is included in the first tool only + GENERAL_PACKAGES="git make cmake python3 python3-pip python3-venv curl wget ftp tar pkg-config dialog mutt ssmtp" + GNU_PACKAGES="autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat1-dev ninja-build libglib2.0-dev libslirp-dev" + QEMU_PACKAGES="libfdt-dev libpixman-1-dev" + SPIKE_PACKAGES="device-tree-compiler libboost-regex-dev libboost-system-dev" + VERILATOR_PACKAGES="help2man perl g++ clang ccache libgoogle-perftools-dev numactl perl-doc libfl2 libfl-dev zlib1g" + SAIL_PACKAGES="opam z3" + BUILDROOT_PACKAGES="ncurses-base ncurses-bin libncurses-dev gfortran" + # Extra packages not availale in Ubuntu 20.04, nice for Verilator + if (( UBUNTU_VERSION >= 22 )); then + VERILATOR_PACKAGES="$VERILATOR_PACKAGES mold" + fi + # Newer version of gcc needed for Ubuntu 20.04 for Verilator + if [ "$UBUNTU_VERSION" = 20 ]; then + OTHER_PACKAGES="gcc-10 g++-10 cpp-10" + fi +fi + +# Check packages are installed or install/update them depending on passed flag. +if [ "${1}" = "--check" ]; then + echo -e "${SECTION_COLOR}\n*************************************************************************" + echo -e "*************************************************************************" + echo -e "Checking Dependencies from Package Manager" + echo -e "*************************************************************************" + echo -e "*************************************************************************\n${ENDC}" + if [ "$FAMILY" = rhel ]; then + for pack in $GENERAL_PACKAGES $GNU_PACKAGES $QEMU_PACKAGES $SPIKE_PACKAGES $VERILATOR_PACKAGES $SAIL_PACKAGES $BUILDROOT_PACKAGES $OTHER_PACKAGES; do + rpm -q "$pack" > /dev/null || (echo -e "${FAIL_COLOR}Missing packages detected (${WARNING_COLOR}$pack${FAIL_COLOR}). Run as root to auto-install or run wally-package-install.sh first.${ENDC}" && exit 1) + done + elif [ "$FAMILY" = ubuntu ]; then + for pack in $GENERAL_PACKAGES $GNU_PACKAGES $QEMU_PACKAGES $SPIKE_PACKAGES $VERILATOR_PACKAGES $SAIL_PACKAGES $BUILDROOT_PACKAGES $OTHER_PACKAGES; do + dpkg -l "$pack" | grep "ii" > /dev/null || (echo -e "${FAIL_COLOR}Missing packages detected (${WARNING_COLOR}$pack${FAIL_COLOR}). Run as root to auto-install or run wally-package-install.sh first." && exit 1) + done + fi + echo -e "${OK_COLOR}All required packages detected.${ENDC}" +else + # Check if root, otherwise exit with error message + [ "${EUID:=$(id -u)}" -ne 0 ] && echo -e "\n${FAIL_COLOR}Must be run as root${ENDC}" && exit 1 + + echo -e "${SECTION_COLOR}\n*************************************************************************" + echo -e "*************************************************************************" + echo -e "Installing/Updating Dependencies from Package Manager" + echo -e "*************************************************************************" + echo -e "*************************************************************************\n${ENDC}" + # Extra red hat commands to set up package manager with extra repos + if [ "$FAMILY" = rhel ]; then + sudo dnf install -y dnf-plugins-core + sudo dnf group install -y "Development Tools" + if [ "$ID" = rhel ]; then + sudo subscription-manager repos --enable "codeready-builder-for-rhel-$RHEL_VERSION-$(arch)-rpms" + sudo dnf install -y "https://dl.fedoraproject.org/pub/epel/epel-release-latest-$RHEL_VERSION.noarch.rpm" + else # RHEL clone + if [ "$RHEL_VERSION" = 8 ]; then + sudo dnf config-manager -y --set-enabled powertools + else # Version 9 + sudo dnf config-manager -y --set-enabled crb + fi + sudo dnf install -y epel-release + fi + fi + + # Update and Upgrade tools + eval "$UPDATE_COMMAND" + # Install packages listed above + sudo "$PACKAGE_MANAGER" install -y $GENERAL_PACKAGES $GNU_PACKAGES $QEMU_PACKAGES $SPIKE_PACKAGES $VERILATOR_PACKAGES $SAIL_PACKAGES $BUILDROOT_PACKAGES $OTHER_PACKAGES + echo -e "${SUCCESS_COLOR}Packages successfully installed.${ENDC}" +fi diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index f41b896d1..3db0bb40f 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -35,6 +35,8 @@ NUM_THREADS=8 # for >= 32GiB #NUM_THREADS=16 # for >= 64GiB +set -e # break on error + # Colors BOLD='\033[1m' UNDERLINE='\033[4m' @@ -45,58 +47,15 @@ WARNING_COLOR='\033[93m' FAIL_COLOR='\033[91m' ENDC='\033[0m' -echo -e "${SECTION_COLOR}\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Checking System Requirements and Configuring Installation" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n${ENDC}" - -set -e # break on error - -# Get distribution information -test -e /etc/os-release && os_release="/etc/os-release" || os_release="/usr/lib/os-release" -source "$os_release" - -# Check for compatible distro -if [[ "$ID" = rhel || "$ID_LIKE" = *rhel* ]]; then - FAMILY=rhel - if [ "$ID" != rhel ] && [ "$ID" != rocky ] && [ "$ID" != almalinux ]; then - printf "${WARNING_COLOR}%s\n${ENDC}" "For Red Hat family distros, the Wally install script has only been tested on RHEL, Rocky Linux," \ - " and AlmaLinux. Your distro is $PRETTY_NAME. The regular Red Hat install will be attempted, but there will likely be issues." - fi - if [ "${VERSION_ID:0:1}" = 8 ]; then - RHEL_VERSION=8 - elif [ "${VERSION_ID:0:1}" = 9 ]; then - RHEL_VERSION=9 - else - echo "${FAIL_COLOR}The Wally install script is only compatible with versions 8 and 9 of RHEL, Rocky Linux, and AlmaLinux. You have version $VERSION.${ENDC}" - exit 1 - fi -elif [[ "$ID" = ubuntu || "$ID_LIKE" = *ubuntu* ]]; then - FAMILY=ubuntu - if [ "$ID" != ubuntu ]; then - printf "${WARNING_COLOR}%s\n${ENDC}" "For Ubuntu family distros, the Wally install script has only been tested on standard Ubuntu. Your distro " \ - "is $PRETTY_NAME. The regular Ubuntu install will be attempted, but there may be issues." - else - UBUNTU_VERSION="${VERSION_ID:0:2}" - if (( UBUNTU_VERSION < 20 )); then - echo "${FAIL_COLOR}The Wally install script is only compatible with versions 20.04, 22.04, and 24.04 of Ubuntu. You have version $VERSION.${ENDC}" - exit 1 - fi - fi -else - printf "${FAIL_COLOR}%s\n${ENDC}" "The Wally install script is currently only compatible with Ubuntu and Red Hat family " \ - "(RHEL, Rocky Linux, or AlmaLinux) distros. Your detected distro is $PRETTY_NAME. You may try manually running the " \ - "commands in this script, but it is likely that some will need to be altered." - exit 1 -fi +# Get Linux distro and version +source wally-distro-check.sh # Check if root -ROOT=$( [ "${EUID:=$(id -u)}" = 0 ] && echo true) +ROOT=$( [ "${EUID:=$(id -u)}" = 0 ] && echo true || echo false); # All tools will be installed under the $RISCV directory. By default, if run as root (with sudo) this is set to # /opt/riscv. Otherwise, it is set to ~/riscv. This value can be overridden with an argument passed to the script. -if [ "$ROOT" ]; then +if [ "$ROOT" = true ]; then export RISCV="${1:-/opt/riscv}" else export RISCV="${1:-$HOME/riscv}" @@ -106,85 +65,27 @@ export PATH=$PATH:$RISCV/bin:/usr/bin export PKG_CONFIG_PATH=$RISCV/lib64/pkgconfig:$RISCV/lib/pkgconfig:$RISCV/share/pkgconfig:$RISCV/lib/x86_64-linux-gnu/pkgconfig:$PKG_CONFIG_PATH mkdir -p "$RISCV" -echo "${OK_COLOR}${UNDERLINE}Detected information${ENDC}" -echo "Distribution: $PRETTY_NAME" -echo "Version: $VERSION" echo "Running as root: $ROOT" echo "Installation path: $RISCV" -echo -e "${SECTION_COLOR}\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Installing/Updating Dependencies from Package Manager" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n${ENDC}" -# Installs appropriate packages for red hat or ubuntu distros, picking apt or dnf appropriately -if [ "$FAMILY" = rhel ]; then - # Enable extra package repos - sudo dnf install -y dnf-plugins-core - if [ "$ID" = rhel ]; then - sudo subscription-manager repos --enable "codeready-builder-for-rhel-$RHEL_VERSION-$(arch)-rpms" - sudo dnf install -y "https://dl.fedoraproject.org/pub/epel/epel-release-latest-$RHEL_VERSION.noarch.rpm" - else # RHEL clone - if [ "$RHEL_VERSION" = 8 ]; then - sudo dnf config-manager -y --set-enabled powertools - else # Version 9 - sudo dnf config-manager -y --set-enabled crb - fi - sudo dnf install -y epel-release - fi - - # Update packages and install additional core tools - sudo dnf update -y - sudo dnf group install -y "Development Tools" - - # Packages are grouped by which tool requires them, split by line. - # If mutltipole tools need a package, it is included in the first tool only - # General/Wally specific, riscv-gnu-toolchain, qemu, spike, verilator, buildroot - sudo dnf install -y git make cmake python3.12 python3-pip curl wget ftp tar pkgconfig dialog mutt ssmtp \ - autoconf automake libmpc-devel mpfr-devel gmp-devel gawk bison flex texinfo gperf libtool patchutils bc gcc gcc-c++ zlib-devel expat-devel libslirp-devel \ - glib2-devel libfdt-devel pixman-devel bzip2 ninja-build \ - dtc boost-regex boost-system \ - help2man perl clang ccache gperftools numactl mold \ - ncurses-base ncurses ncurses-libs ncurses-devel gcc-gfortran - # Extra packages not availale in rhel8, nice for verialtor and needed for sail respectively - if [ "$RHEL_VERSION" = 9 ]; then - sudo dnf install -y perl-doc z3 - fi - - # A newer version of gcc is required for qemu - sudo dnf install -y gcc-toolset-13* - source /opt/rh/gcc-toolset-13/enable # activate gcc13 -elif [ "$FAMILY" = ubuntu ]; then - # Update and Upgrade tools (see https://itsfoss.com/apt-update-vs-upgrade/) - sudo apt update -y - sudo apt upgrade -y - - # Packages are grouped by which tool requires them, split by line. - # If mutltipole tools need a package, it is included in the first tool only - # General/Wally specific, riscv-gnu-toolchain, qemu, spike, verilator, sail, buildroot - sudo apt install -y git make cmake python3 python3-pip python3-venv curl wget ftp tar pkg-config dialog mutt ssmtp \ - autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat1-dev ninja-build libglib2.0-dev libslirp-dev \ - libfdt-dev libpixman-1-dev \ - device-tree-compiler libboost-regex-dev libboost-system-dev \ - help2man perl g++ clang ccache libgoogle-perftools-dev numactl perl-doc libfl2 libfl-dev zlib1g \ - opam z3 \ - ncurses-base ncurses-bin libncurses-dev gfortran - # Extra packages not availale in Ubuntu 20.04, nice for verialtor - if (( UBUNTU_VERSION >= 22 )); then - sudo apt install -y mold - fi - # Newer version of gcc needed for Ubuntu 20.04 for Verilator - if [ "$UBUNTU_VERSION" = 20 ]; then - sudo apt install -y gcc-10 g++-10 cpp-10 - mkdir -p "$RISCV"/gcc-10/bin - for f in gcc cpp g++ gcc-ar gcc-nm gcc-ranlib gcov gcov-dump gcov-tool lto-dump; do - ln -vsf /usr/bin/$f-10 "$RISCV"/gcc-10/bin/$f - done - export PATH="$RISCV"/gcc-10/bin:$PATH - fi +# Install/update packages if root. Otherwise, check that packages are already installed. +if [ "$ROOT" = true ]; then + ./wally-package-install.sh +else + ./wally-package-install.sh --check fi -echo -e "${SUCCESS_COLOR}Packages successfully installed.${ENDC}" +if [ "$FAMILY" = rhel ]; then + # A newer version of gcc is required for qemu + source /opt/rh/gcc-toolset-13/enable # activate gcc13 + # Newer version of gcc needed for Ubuntu 20.04 for Verilator +elif [ "$UBUNTU_VERSION" = 20 ]; then + mkdir -p "$RISCV"/gcc-10/bin + for f in gcc cpp g++ gcc-ar gcc-nm gcc-ranlib gcov gcov-dump gcov-tool lto-dump; do + ln -vsf /usr/bin/$f-10 "$RISCV"/gcc-10/bin/$f + done + export PATH="$RISCV"/gcc-10/bin:$PATH +fi echo -e "${SECTION_COLOR}\n*************************************************************************" echo -e "*************************************************************************" From bd4f3e89fab9df3e12fef825856c6252cdcf5ed2 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 2 Jul 2024 21:41:37 -0700 Subject: [PATCH 038/219] Source package install script so variables are shared --- bin/wally-tool-chain-install.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 3db0bb40f..55dcba9a3 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -70,9 +70,9 @@ echo "Installation path: $RISCV" # Install/update packages if root. Otherwise, check that packages are already installed. if [ "$ROOT" = true ]; then - ./wally-package-install.sh + source wally-package-install.sh else - ./wally-package-install.sh --check + source wally-package-install.sh --check fi if [ "$FAMILY" = rhel ]; then From b6ad0571ac585b85dc6d336602986b5d6bb0a18e Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 2 Jul 2024 22:17:43 -0700 Subject: [PATCH 039/219] Update sourcing of secondary scripts to work when called from any directory --- bin/wally-package-install.sh | 3 ++- bin/wally-tool-chain-install.sh | 7 ++++--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index f012fe259..fd9031ccc 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -38,7 +38,8 @@ ENDC='\033[0m' # If run standalone, determine distro information. Otherwise, use info from main install script if [ -z "$FAMILY" ]; then - source wally-distro-check.sh + dir="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" + source "${dir}"/wally-distro-check.sh fi # Generate list of packages to install, determined based on distro diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 55dcba9a3..61686a22e 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -36,6 +36,7 @@ NUM_THREADS=8 # for >= 32GiB #NUM_THREADS=16 # for >= 64GiB set -e # break on error +dir="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" # Colors BOLD='\033[1m' @@ -48,7 +49,7 @@ FAIL_COLOR='\033[91m' ENDC='\033[0m' # Get Linux distro and version -source wally-distro-check.sh +source "${dir}"/wally-distro-check.sh # Check if root ROOT=$( [ "${EUID:=$(id -u)}" = 0 ] && echo true || echo false); @@ -70,9 +71,9 @@ echo "Installation path: $RISCV" # Install/update packages if root. Otherwise, check that packages are already installed. if [ "$ROOT" = true ]; then - source wally-package-install.sh + source "${dir}"/wally-package-install.sh else - source wally-package-install.sh --check + source "${dir}"/wally-package-install.sh --check fi if [ "$FAMILY" = rhel ]; then From f9e865e5373d9db1ccb3f0f74dd5b68cc53d79e5 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 3 Jul 2024 19:51:52 -0700 Subject: [PATCH 040/219] Update README with new installation flow and other general cleanup --- README.md | 84 +++++++++++++++++++++++++++++++------------------------ 1 file changed, 48 insertions(+), 36 deletions(-) diff --git a/README.md b/README.md index 084741107..032304c25 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,6 @@ # core-v-wally -Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, Q, M, and Zb* extensions, virtual memory, PMP, and the various privileged modes and CSRs. It provides optional caches, branch prediction, and standard RISC-V peripherals (CLINT, PLIC, UART, GPIO). Wally is written in SystemVerilog. It passes the RISC-V Arch Tests and boots Linux on an FPGA. Configurations range from a minimal RV32E core to a fully featured RV64GC application processor. +Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, including RV32/64, A, B, C, D, F, M, Q, and Zk* extensions, virtual memory, PMP, and the various privileged modes and CSRs. It provides optional caches, branch prediction, and standard RISC-V peripherals (CLINT, PLIC, UART, GPIO). Wally is written in SystemVerilog. It passes the [RISC-V Arch Tests](https://github.com/riscv-non-isa/riscv-arch-test) and boots Linux on an FPGA. Configurations range from a minimal RV32E core to a fully featured RV64GC application processor. ![Wally block diagram](wallyriscvTopAll.png) @@ -29,49 +29,63 @@ Then fork and clone the repo, source setup, make the tests and run regression If you don't already have a Github account, create one In a web browser, visit https://github.com/openhwgroup/cvw In the upper right part of the screen, click on Fork - Create a fork, choosing the owner as your github account + Create a fork, choosing the owner as your github account and the repository as cvw. - + On the Linux computer where you will be working, log in -Clone your fork of the repo and run the setup script. Change to your github id. +Clone your fork of the repo. Change `` to your github id. $ git clone --recurse-submodules https://github.com//cvw $ cd cvw $ git remote add upstream https://github.com/openhwgroup/cvw + +If you are installing on a new system without any tools installed, please jump to the next section, Toolchain Installation then come back here. + +Run the setup script to update your `PATH` and activate the python virtual environment. + $ source ./setup.sh -If you are installing on a new system without any tools installed please jump to the next section, Toolchain Installation then come back here. - -Add the following lines to your .bashrc or .bash_profile to run the setup script each time you log in. +Add the following lines to your `.bashrc` or `.bash_profile` to run the setup script each time you log in. if [ -f ~/cvw/setup.sh ]; then source ~/cvw/setup.sh fi -If the tools are not yet installed on your server, follow the Toolchain Installation instructions in the section below. -Build the tests and run a regression simulation with Questa to prove everything is installed. Building tests will take a while. +Build the tests and run a regression simulation to prove everything is installed. Building tests will take a while. $ make - $ regression-wally (depends on having Questa installed) + $ regression-wally -# Toolchain Installation (Sys Admin) +# Toolchain Installation and Configuration (Sys Admin) -This section describes the open source toolchain installation. The -current version of the toolchain has been tested on Ubuntu and partly on Red -Hat/Rocky 8 Linux. Ubuntu works more smoothly and is recommended -unless you have a compelling need for RedHat. However, Ubuntu 22.04LTS -is incompatible with Synopsys Design Compiler. +This section describes the open source toolchain installation. The current version of the toolchain has been tested on Ubuntu (versions 20.04, 22.04, and 24.04) and on Red Hat/Rocky/AlmaLinux (versions 8 and 9). +NOTE: Ubuntu 22.04LTS is incompatible with Synopsys Design Compiler. -Ubuntu users can install the tools by running +### Installation - $ sudo $WALLY/bin/wally-tool-chain-install.sh +The tools can be installed by running -The default installation directory is /opt/riscv defined by the environment variable RISCV. You must copy and edit ~/cvw/site-setup.sh to $RISCV/site-setup.sh. + $ $WALLY/bin/wally-tool-chain-install.sh -~/cvw/setup.sh sources $RISCV/site-setup.sh. -This allows for customization of the site specific information such as commerical licenses and PATH variables. +If this script is run as root or using `sudo`, it will also install all of the prerequisite packages using the system package manager. The default installation directory when run in this manner is `/opt/riscv`. + +If a user-level installation is desired, the script can instead be run by any user without `sudo` and the installation directory will be `~/riscv`. In this case, the prerequisite packages must first be installed by running + + $ sudo $WALLY/bin/wally-package-install.sh + +In either case, the installation directory can be overridden by passing the desired directory as an argument to the installation script. For example, + + $ sudo $WALLY/bin/wally-tool-chain-install.sh /home/riscv + +See wally-tool-chain-install.sh for a detailed description of each component, +or to issue the commands one at a time to install on the command line. + +### Configuration +`$WALLY/setup.sh` sources `$RISCV/site-setup.sh`. If the toolchain was installed in either of the default locations (`/opt/riscv` or `~/riscv`), `$RISCV` will automatically be set to the correct path when `setup.sh` is run. If a custom installation directory was used, then `$WALLY/setup.sh` must be modified to set the correct path. + +`$RISCV/site-setup.sh` allows for customization of the site specific information such as commercial licenses and PATH variables. It is automatically copied into your `$RISCV` folder when the installation script is run. Change the following lines to point to the path and license server for your Siemens Questa and Synopsys Design Compiler installation and license server. If you only have Questa, you can still simulate but cannot run logic synthesis. If Questa or Design Compiler are already setup on this system then don't set these variables. @@ -81,24 +95,22 @@ Change the following lines to point to the path and license server for your Siem export SNPSPATH=.. # Change this for your path to Design Compiler -See wally-tool-chain-install.sh for a detailed description of each component, -or to issue the commands one at a time to install on the command line. ## Installing EDA Tools Electronic Design Automation (EDA) tools are vital to implementations of System on Chip architectures as well as validating different designs. Open-source and commercial tools exist for multiple strategies and although the one can spend a lifetime using combinations of different tools, only a small subset of tools is utilized for this text. The tools are chosen because of their ease in access as well as their repeatability for accomplishing many of the tasks utilized to design Wally. It is anticipated that additional tools may be documented later after this is text is published to improve use and access. -Siemens Quest is the primary tool utilized for simulating and validating Wally. For logic synthesis, you will need Synopsys Design Compiler. Questa and Design Compiler are commercial tools that require an educational or commercial license. +Siemens Questa is the primary tool utilized for simulating and validating Wally. For logic synthesis, you will need Synopsys Design Compiler. Questa and Design Compiler are commercial tools that require an educational or commercial license. -Note: Some EDA tools utilize LM_LICENSE_FILE for their environmental variable to point to their license server. Some operating systems may also utilize MGLS_LICENSE_FILE instead, therefore, it is important to read the user manual on the preferred environmental variable required to point to a user’s license file. Although there are different mechanisms to allow licenses to work, many companies commonly utilize the FlexLM (i.e., Flex-enabled) license server manager that runs off a node locked license. +Note: Some EDA tools utilize `LM_LICENSE_FILE` for their environmental variable to point to their license server. Some operating systems may also utilize `MGLS_LICENSE_FILE` instead, therefore, it is important to read the user manual on the preferred environmental variable required to point to a user’s license file. Although there are different mechanisms to allow licenses to work, many companies commonly utilize the FlexLM (i.e., Flex-enabled) license server manager that runs off a node locked license. -Although most EDA tools are Linux-friendly, they tend to have issues when not installed on recommended OS flavors. Both Red Hat Enterprise Linux and SUSE Linux products typically tend to be recommended for installing commercial-based EDA tools and are recommended for utilizing complex simulation and architecture exploration. Questa can also be installed on Microsoft Windows as well as Mac OS with a Virtual Machine such as Parallels. +Although most EDA tools are Linux-friendly, they tend to have issues when not installed on recommended OS flavors. Both Red Hat Enterprise Linux and SUSE Linux products typically tend to be recommended for installing commercial-based EDA tools and are recommended for utilizing complex simulation and architecture exploration. Questa can also be installed on Microsoft Windows as well as Mac OS with a Virtual Machine such as Parallels. -Siemens Questa +#### Siemens Questa -Siemens Questa simulates behavioral, RTL and gate-level HDL. To install Siemens Questa first go to a web browser and navigate to -https://eda.sw.siemens.com/en-US/ic/questa/simulation/advanced-simulator/. Click Sign In and log in with your credentials and the product can easily be downloaded and installed. Some Windows-based installations also require gcc libraries that are typically provided as a compressed zip download through Siemens. +Siemens Questa simulates behavioral, RTL and gate-level HDL. To install Siemens Questa first go to a web browser and navigate to +https://eda.sw.siemens.com/en-US/ic/questa/simulation/advanced-simulator/. Click Sign In and log in with your credentials and the product can easily be downloaded and installed. Some Windows-based installations also require gcc libraries that are typically provided as a compressed zip download through Siemens. -Synopsys Design Compiler (DC) +#### Synopsys Design Compiler (DC) Many commercial synthesis and place and route tools require a common installer. These installers are provided by the EDA vendor and Synopsys has one called Synopsys Installer. To use Synopsys Installer, you will need to acquire a license through Synopsys that is typically Called Synopsys Common Licensing (SCL). Both the Synopsys Installer, license key file, and Design Compiler can all be downloaded through Synopsys Solvnet. First open a web browser, log into Synsopsy Solvnet, and download the installer and Design Compiler installation files. Then, install the Installer @@ -110,7 +122,7 @@ Select the latest version (currently 5.4). Click Download Here, agree, Click on SynopsysInstaller_v5.4.run Return to downloads and also get Design Compiler (synthesis) latest version, and any others you want. Click on all parts and the .spf file, then click Download Files near the top -move the SynopsysIntaller into /cad/synopsys/Installer_5.4 with 755 permission for cad, +move the SynopsysInstaller into /cad/synopsys/Installer_5.4 with 755 permission for cad, move other files into /cad/synopsys/downloads and work as user cad from here on $ cd /cad/synopsys/installer_5.4 @@ -121,17 +133,17 @@ move other files into /cad/synopsys/downloads and work as user cad from here on When prompted, enter your site ID Follow prompts -Installer can be utilized in graphical or text-based modes. It is far easier to use the text-based installation tool. To install DC, navigate to the location where your downloaded DC files are and type installer. You should be prompted with questions related to where you wish to have your files installed. +Installer can be utilized in graphical or text-based modes. It is far easier to use the text-based installation tool. To install DC, navigate to the location where your downloaded DC files are and type installer. You should be prompted with questions related to where you wish to have your files installed. The Synopsys Installer automatically installs all downloaded product files into a single top-level target directory. You do not need to specify the installation directory for each product. For example, if you specify /import/programs/synopsys as the target directory, your installation directory structure might look like this after installation: /import/programs/synopsys/syn/S-2021.06-SP1 -Note: Although most parts of Wally, including the software used in this chapter and Questa simulation, will work on most modern Linux platforms, as of 2022, the Synopsys CAD tools for SoC design are only supported on RedHat Enterprise Linux 7.4 or 8 or SUSE Linux Enterprise Server (SLES) 12 or 15. Moreover, the RISC-V formal specification (sail-riscv) does not build gracefully on RHEL7. +Note: Although most parts of Wally, including the Questa simulator, will work on most modern Linux platforms, as of 2022, the Synopsys CAD tools for SoC design are only supported on RedHat Enterprise Linux 7.4 or 8 or SUSE Linux Enterprise Server (SLES) 12 or 15. Moreover, the RISC-V formal specification (sail-riscv) does not build gracefully on RHEL7. -The Verilog simulation has been tested with Siemens Questa/ModelSim. This package is available to universities worldwide as part of the Design Verification Bundle through the Siemens Academic Partner Program members for $990/year. +The Verilog simulation has been tested with Siemens Questa/ModelSim. This package is available to universities worldwide as part of the Design Verification Bundle through the Siemens Academic Partner Program members for $990/year. -If you want to implement your own version of the chip, your tool and license complexity rises significantly. Logic synthesis uses Synopsys Design Compiler. Placement and routing uses Cadence Innovus. Both Synopsys and Cadence offer their tools at a steep discount to their university program members, but the cost is still several thousand dollars per year. Most research universities with integrated circuit design programs have Siemens, Synopsys, and Cadence licenses. You also need a process design kit (PDK) for a specific integrated circuit technology and its libraries. The open-source Google Skywater 130 nm PDK is sufficient to synthesize the core but lacks memories. Google presently funds some fabrication runs for universities. IMEC and Muse Semiconductor offers full access to multiproject wafer fabrication on the TSMC 28 nm process including logic, I/O, and memory libraries; this involves three non-disclosure agreements. Fabrication costs on the order of $10,000 for a batch of 1 mm2 chips. +If you want to implement your own version of the chip, your tool and license complexity rises significantly. Logic synthesis uses Synopsys Design Compiler. Placement and routing uses Cadence Innovus. Both Synopsys and Cadence offer their tools at a steep discount to their university program members, but the cost is still several thousand dollars per year. Most research universities with integrated circuit design programs have Siemens, Synopsys, and Cadence licenses. You also need a process design kit (PDK) for a specific integrated circuit technology and its libraries. The open-source Google Skywater 130 nm PDK is sufficient to synthesize the core but lacks memories. Google presently funds some fabrication runs for universities. IMEC and Muse Semiconductor offers full access to multiproject wafer fabrication on the TSMC 28 nm process including logic, I/O, and memory libraries; this involves three non-disclosure agreements. Fabrication costs on the order of $10,000 for a batch of 1 mm2 chips. Startups can expect to spend more than $1 million on CAD tools to get a chip to market. Commercial CAD tools are not realistically available to individuals without a university or company connection. @@ -183,7 +195,7 @@ Run lockstep against ImperasDV with a single elf file. Compute coverage. wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/ref/ref.elf --lockstep --coverage -Run lockstep against ImperasDV with directory file. +Run lockstep against ImperasDV with directory file. wsim rv64gc ../../tests/riscof/work/riscv-arch-test/rv64i_m/I/src/ --lockstep From 74196893590a3321f923dd4ea7f401eee8e54a61 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 3 Jul 2024 20:42:55 -0700 Subject: [PATCH 041/219] Update python shebangs to use /usr/bin/env python3 so virtual environment can be used (also aids in general portability) --- Makefile | 6 +++--- benchmarks/coremark/coremark_sweep.py | 2 +- benchmarks/embench/embench_arch_sweep.py | 2 +- benchmarks/graphGen.py | 2 +- bin/nightly_build.py | 2 +- bin/parseHPMC.py | 2 +- bin/regression-wally | 2 +- bin/wrapper_nightly_runs.sh | 2 +- bin/wsim | 2 +- fpga/generator/probe | 2 +- fpga/probe | 2 +- fpga/proberange | 14 +++++++------- fpga/probes | 2 +- fpga/renumber.py | 2 +- .../testvector-generation/disassembleBootTrace.py | 2 +- .../filterTrapsToInterrupts.py | 2 +- linux/testvector-generation/parseGDBtoTrace.py | 2 +- linux/testvector-generation/parsePlicState.py | 2 +- linux/testvector-generation/parseQEMUtoGDB.py | 2 +- linux/testvector-generation/parseState.py | 2 +- linux/testvector-generation/parseUartState.py | 2 +- sim/bpred-sim.py | 2 +- sim/buildrootBugFinder.py | 2 +- sim/slack-notifier/slack-notifier.py | 2 +- .../testgen/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py | 2 +- studies/testgen/testgen-ADDI-XORI-ORI-ANDI-SLTI.py | 2 +- studies/testgen/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py | 2 +- .../testgen/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py | 2 +- studies/testgen/testgen-BRANCH.py | 2 +- studies/testgen/testgen-CSR.py | 2 +- studies/testgen/testgen-JAL-JALR.py | 2 +- studies/testgen/testgen-LOAD.py | 2 +- studies/testgen/testgen-PIPELINE.py | 2 +- studies/testgen/testgen-SLL-SRL-SRA.py | 2 +- studies/testgen/testgen-SLLI-SRLI-SRAI.py | 2 +- studies/testgen/testgen-SLTIU.py | 2 +- studies/testgen/testgen-STORE.py | 2 +- studies/testgen/testgen-VIRTUALMEMORY.py | 2 +- synthDC/extractSummary.py | 2 +- synthDC/ppa/ppaAnalyze.py | 2 +- synthDC/ppa/ppaSynth.py | 2 +- synthDC/scripts/wrapperGen.py | 2 +- synthDC/wallySynth.py | 2 +- testbench/sdc/ram2sdLoad.py | 2 +- .../fp/combined_IF_vectors/extract_arch_vectors.py | 2 +- .../extract_testfloat_vectors.py | 2 +- tests/fp/quad/fpdatasetgen.py | 2 +- tests/testgen/PIPELINE.py | 2 +- tests/testgen/covergen.py | 2 +- tests/testgen/privileged/run.sh | 2 +- tests/testgen/privileged/testgen-CAUSE.py | 2 +- .../testgen/privileged/testgen-CSR-PERMISSIONS.py | 2 +- tests/testgen/privileged/testgen-DELEG.py | 2 +- tests/testgen/privileged/testgen-EPC.py | 2 +- tests/testgen/privileged/testgen-IE.py | 2 +- tests/testgen/privileged/testgen-IP.py | 2 +- tests/testgen/privileged/testgen-READONLY.py | 2 +- tests/testgen/privileged/testgen-RET.py | 2 +- tests/testgen/privileged/testgen-TVAL.py | 2 +- tests/testgen/privileged/testgen-TVEC.py | 2 +- tests/testgen/testgen.py | 2 +- 61 files changed, 69 insertions(+), 69 deletions(-) diff --git a/Makefile b/Makefile index 740287dcc..be870b028 100644 --- a/Makefile +++ b/Makefile @@ -51,9 +51,9 @@ funcovreg: # test_name=riscv_arithmetic_basic_test riscvdv: - python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gen,gcc_compile >> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1 -# python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gcc_compile >> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1 -# python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps iss_sim >> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1 + ${RISCV}/riscv-python/bin/python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gen,gcc_compile >> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1 +# ${RISCV}/riscv-python/bin/python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gcc_compile >> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1 +# ${RISCV}/riscv-python/bin/python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps iss_sim >> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1 # run-elf.bash --seed ${SIM}/questa/seed0.txt --verbose --elf ${WALLY}/tests/riscvdv/asm_test/${test_name}_0.o >> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1 #run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/riscv.ucdb --elf ${WALLY}/tests/riscvdv/asm_test/${test_name}_0.o >> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1 #cp ${SIM}/questa/riscv.ucdb ${SIM}/questa/functcov_ucdbs/${test_name}.ucdb diff --git a/benchmarks/coremark/coremark_sweep.py b/benchmarks/coremark/coremark_sweep.py index d912349dc..8cfce025d 100755 --- a/benchmarks/coremark/coremark_sweep.py +++ b/benchmarks/coremark/coremark_sweep.py @@ -1,4 +1,4 @@ -#!/usr/bin/python +#!/usr/bin/env python3 ################################################## ## coremark_sweep.py diff --git a/benchmarks/embench/embench_arch_sweep.py b/benchmarks/embench/embench_arch_sweep.py index 14b1f1b0c..99d49e7be 100755 --- a/benchmarks/embench/embench_arch_sweep.py +++ b/benchmarks/embench/embench_arch_sweep.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 # embench_arch_sweep.py # David_Harris@hmc.edu 16 November 2023 # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 diff --git a/benchmarks/graphGen.py b/benchmarks/graphGen.py index dd7b3a204..95e48db6e 100755 --- a/benchmarks/graphGen.py +++ b/benchmarks/graphGen.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 # Daniel Torres 2022 # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 diff --git a/bin/nightly_build.py b/bin/nightly_build.py index d82877a7a..5a062266b 100755 --- a/bin/nightly_build.py +++ b/bin/nightly_build.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 """ Python Regression Build Automation Script diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py index fd4efe20e..4408f2211 100755 --- a/bin/parseHPMC.py +++ b/bin/parseHPMC.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ########################################### ## Written: Rose Thompson ross1728@gmail.com diff --git a/bin/regression-wally b/bin/regression-wally index ed725b51a..24f287ca0 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ################################## # # regression-wally diff --git a/bin/wrapper_nightly_runs.sh b/bin/wrapper_nightly_runs.sh index 982132792..88a1e094a 100755 --- a/bin/wrapper_nightly_runs.sh +++ b/bin/wrapper_nightly_runs.sh @@ -17,5 +17,5 @@ source ./setup.sh cd $PYTHON_SCRIPT pwd echo "Running python file" -python nightly_build.py +$RISCV/riscv-python/bin/python nightly_build.py echo "Finished" diff --git a/bin/wsim b/bin/wsim index 35b48dbb1..8500892fc 100755 --- a/bin/wsim +++ b/bin/wsim @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 # # wsim # David_Harris@hmc.edu 5 April 2024 diff --git a/fpga/generator/probe b/fpga/generator/probe index d3142e0f2..cb2b95b23 100755 --- a/fpga/generator/probe +++ b/fpga/generator/probe @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ########################################### ## fpgaTop.sv ## diff --git a/fpga/probe b/fpga/probe index 1cf1104c1..fa60dc658 100755 --- a/fpga/probe +++ b/fpga/probe @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ########################################### ## probe.sh ## diff --git a/fpga/proberange b/fpga/proberange index 73bfc3383..44885a0eb 100755 --- a/fpga/proberange +++ b/fpga/proberange @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ########################################### ## proberange.sh ## @@ -13,15 +13,15 @@ ## ## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 ## -## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You ## may obtain a copy of the License at ## ## https:##solderpad.org#licenses#SHL-2.1# ## -## Unless required by applicable law or agreed to in writing, any work distributed under the -## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -## either express or implied. See the License for the specific language governing permissions +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions ## and limitations under the License. ################################################################################################ @@ -41,7 +41,7 @@ set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] -startgroup +startgroup set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ] set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ] set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ] diff --git a/fpga/probes b/fpga/probes index 1ea571057..8d220c62f 100755 --- a/fpga/probes +++ b/fpga/probes @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ########################################### ## probe.sh ## diff --git a/fpga/renumber.py b/fpga/renumber.py index adf625920..84a2543d7 100755 --- a/fpga/renumber.py +++ b/fpga/renumber.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 import sys import re diff --git a/linux/testvector-generation/disassembleBootTrace.py b/linux/testvector-generation/disassembleBootTrace.py index 12e2202cb..ac36fd36e 100755 --- a/linux/testvector-generation/disassembleBootTrace.py +++ b/linux/testvector-generation/disassembleBootTrace.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 # # disassembleBootTrace.py # David_Harris@hmc.edu 22 November 2023 diff --git a/linux/testvector-generation/filterTrapsToInterrupts.py b/linux/testvector-generation/filterTrapsToInterrupts.py index de0553098..7476e110f 100755 --- a/linux/testvector-generation/filterTrapsToInterrupts.py +++ b/linux/testvector-generation/filterTrapsToInterrupts.py @@ -1,4 +1,4 @@ -#! /usr/bin/python3 +#!/usr/bin/env python3 import sys, os from functools import reduce diff --git a/linux/testvector-generation/parseGDBtoTrace.py b/linux/testvector-generation/parseGDBtoTrace.py index 9a467e3e2..a5ace11b0 100755 --- a/linux/testvector-generation/parseGDBtoTrace.py +++ b/linux/testvector-generation/parseGDBtoTrace.py @@ -1,4 +1,4 @@ -#! /usr/bin/python3 +#!/usr/bin/env python3 import sys, fileinput, re # Ross Thompson diff --git a/linux/testvector-generation/parsePlicState.py b/linux/testvector-generation/parsePlicState.py index 49f2a558e..5fb2b4eac 100755 --- a/linux/testvector-generation/parsePlicState.py +++ b/linux/testvector-generation/parsePlicState.py @@ -1,4 +1,4 @@ -#! /usr/bin/python3 +#!/usr/bin/env python3 import sys, os from functools import reduce diff --git a/linux/testvector-generation/parseQEMUtoGDB.py b/linux/testvector-generation/parseQEMUtoGDB.py index aea5e057e..457085a1b 100755 --- a/linux/testvector-generation/parseQEMUtoGDB.py +++ b/linux/testvector-generation/parseQEMUtoGDB.py @@ -1,4 +1,4 @@ -#! /usr/bin/python3 +#!/usr/bin/env python3 import fileinput, sys parseState = "idle" diff --git a/linux/testvector-generation/parseState.py b/linux/testvector-generation/parseState.py index 1f7e93c09..f54ba0f78 100755 --- a/linux/testvector-generation/parseState.py +++ b/linux/testvector-generation/parseState.py @@ -1,4 +1,4 @@ -#! /usr/bin/python3 +#!/usr/bin/env python3 import sys, os ################ diff --git a/linux/testvector-generation/parseUartState.py b/linux/testvector-generation/parseUartState.py index 611937054..82028d528 100755 --- a/linux/testvector-generation/parseUartState.py +++ b/linux/testvector-generation/parseUartState.py @@ -1,4 +1,4 @@ -#! /usr/bin/python3 +#!/usr/bin/env python3 import sys, os ################ diff --git a/sim/bpred-sim.py b/sim/bpred-sim.py index c04b9bd51..45c0965a1 100755 --- a/sim/bpred-sim.py +++ b/sim/bpred-sim.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ################################## # # regression-wally diff --git a/sim/buildrootBugFinder.py b/sim/buildrootBugFinder.py index af6324596..55613e64b 100755 --- a/sim/buildrootBugFinder.py +++ b/sim/buildrootBugFinder.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 import sys, os, subprocess def main(): diff --git a/sim/slack-notifier/slack-notifier.py b/sim/slack-notifier/slack-notifier.py index 273299d23..ac824feec 100755 --- a/sim/slack-notifier/slack-notifier.py +++ b/sim/slack-notifier/slack-notifier.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 import os,sys,subprocess from datetime import datetime, timezone, timedelta diff --git a/studies/testgen/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py b/studies/testgen/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py index 9f795036b..7a5b824b5 100755 --- a/studies/testgen/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py +++ b/studies/testgen/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ################################## # testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py # diff --git a/studies/testgen/testgen-ADDI-XORI-ORI-ANDI-SLTI.py b/studies/testgen/testgen-ADDI-XORI-ORI-ANDI-SLTI.py index b755519f6..a25958552 100644 --- a/studies/testgen/testgen-ADDI-XORI-ORI-ANDI-SLTI.py +++ b/studies/testgen/testgen-ADDI-XORI-ORI-ANDI-SLTI.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ################################## # testgen-ADD-SUB.py # diff --git a/studies/testgen/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py b/studies/testgen/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py index 57a2bad77..55cffb3db 100755 --- a/studies/testgen/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py +++ b/studies/testgen/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ################################## # testgen-ADDIW-SLLIW-SRLIW-SRAIW.py # diff --git a/studies/testgen/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py b/studies/testgen/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py index d95bc3fc4..f57b95315 100755 --- a/studies/testgen/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py +++ b/studies/testgen/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ################################## # testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py # diff --git a/studies/testgen/testgen-BRANCH.py b/studies/testgen/testgen-BRANCH.py index 04a9caa80..cf5236ad9 100755 --- a/studies/testgen/testgen-BRANCH.py +++ b/studies/testgen/testgen-BRANCH.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ################################## # testgen-branch.py # diff --git a/studies/testgen/testgen-CSR.py b/studies/testgen/testgen-CSR.py index f28f9925d..7f74b1658 100644 --- a/studies/testgen/testgen-CSR.py +++ b/studies/testgen/testgen-CSR.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ################################## # testgen-ADD-SUB.py # diff --git a/studies/testgen/testgen-JAL-JALR.py b/studies/testgen/testgen-JAL-JALR.py index 87c0c423d..7ce482bd5 100755 --- a/studies/testgen/testgen-JAL-JALR.py +++ b/studies/testgen/testgen-JAL-JALR.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ################################## # testgen-JAL.py # diff --git a/studies/testgen/testgen-LOAD.py b/studies/testgen/testgen-LOAD.py index 4a80fbfc7..736b8e05b 100755 --- a/studies/testgen/testgen-LOAD.py +++ b/studies/testgen/testgen-LOAD.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ################################## # testgen-LOAD.py # diff --git a/studies/testgen/testgen-PIPELINE.py b/studies/testgen/testgen-PIPELINE.py index 3a425da98..0a2a66491 100755 --- a/studies/testgen/testgen-PIPELINE.py +++ b/studies/testgen/testgen-PIPELINE.py @@ -1,4 +1,4 @@ -#!/usr/bin/python +#!/usr/bin/env python3 ################################################################################################### # testgen-PIPELINE.py # diff --git a/studies/testgen/testgen-SLL-SRL-SRA.py b/studies/testgen/testgen-SLL-SRL-SRA.py index 6b4996d90..ede82af48 100755 --- a/studies/testgen/testgen-SLL-SRL-SRA.py +++ b/studies/testgen/testgen-SLL-SRL-SRA.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ################################## # testgen-SLL-SRL-SRA.py # diff --git a/studies/testgen/testgen-SLLI-SRLI-SRAI.py b/studies/testgen/testgen-SLLI-SRLI-SRAI.py index 201763890..cc01f1eb8 100644 --- a/studies/testgen/testgen-SLLI-SRLI-SRAI.py +++ b/studies/testgen/testgen-SLLI-SRLI-SRAI.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ################################## # testgen-ADD-SUB.py # diff --git a/studies/testgen/testgen-SLTIU.py b/studies/testgen/testgen-SLTIU.py index 25eb5ddfb..8642a7aec 100644 --- a/studies/testgen/testgen-SLTIU.py +++ b/studies/testgen/testgen-SLTIU.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ################################## # testgen-ADD-SUB.py # diff --git a/studies/testgen/testgen-STORE.py b/studies/testgen/testgen-STORE.py index d4a995d48..4f3944c70 100755 --- a/studies/testgen/testgen-STORE.py +++ b/studies/testgen/testgen-STORE.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ################################## # testgen-STORE.py # diff --git a/studies/testgen/testgen-VIRTUALMEMORY.py b/studies/testgen/testgen-VIRTUALMEMORY.py index 07bb6e374..310e96b3c 100644 --- a/studies/testgen/testgen-VIRTUALMEMORY.py +++ b/studies/testgen/testgen-VIRTUALMEMORY.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ################################## # testgen-VIRTUALMEMORY.py # diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py index 354c6f70f..826be54d8 100755 --- a/synthDC/extractSummary.py +++ b/synthDC/extractSummary.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 # Madeleine Masser-Frye (mmmasserfrye@hmc.edu) 06/2022 from collections import namedtuple import re diff --git a/synthDC/ppa/ppaAnalyze.py b/synthDC/ppa/ppaAnalyze.py index 56248ed9e..a43de80bb 100755 --- a/synthDC/ppa/ppaAnalyze.py +++ b/synthDC/ppa/ppaAnalyze.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 # # Python regression test for DC # Madeleine Masser-Frye mmasserfrye@hmc.edu 5/22 diff --git a/synthDC/ppa/ppaSynth.py b/synthDC/ppa/ppaSynth.py index 315fa554a..1947a5809 100755 --- a/synthDC/ppa/ppaSynth.py +++ b/synthDC/ppa/ppaSynth.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 # # Python regression test for DC # Madeleine Masser-Frye mmasserfrye@hmc.edu 5/22 diff --git a/synthDC/scripts/wrapperGen.py b/synthDC/scripts/wrapperGen.py index b570ad0c0..f91052638 100755 --- a/synthDC/scripts/wrapperGen.py +++ b/synthDC/scripts/wrapperGen.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 """ wrapperGen.py diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py index a5e8b5d6b..caf7e1697 100755 --- a/synthDC/wallySynth.py +++ b/synthDC/wallySynth.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 # Madeleine Masser-Frye mmasserfrye@hmc.edu 1/2023 import subprocess diff --git a/testbench/sdc/ram2sdLoad.py b/testbench/sdc/ram2sdLoad.py index d283ad3ac..ebfa37939 100755 --- a/testbench/sdc/ram2sdLoad.py +++ b/testbench/sdc/ram2sdLoad.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 import sys, fileinput diff --git a/tests/fp/combined_IF_vectors/extract_arch_vectors.py b/tests/fp/combined_IF_vectors/extract_arch_vectors.py index d0fd3ab9c..ddb3e0c35 100755 --- a/tests/fp/combined_IF_vectors/extract_arch_vectors.py +++ b/tests/fp/combined_IF_vectors/extract_arch_vectors.py @@ -1,4 +1,4 @@ -#! /usr/bin/python3 +#!/usr/bin/env python3 # author: Alessandro Maiuolo, Kevin Kim # contact: amaiuolo@g.hmc.edu, kekim@hmc.edu diff --git a/tests/fp/combined_IF_vectors/extract_testfloat_vectors.py b/tests/fp/combined_IF_vectors/extract_testfloat_vectors.py index 07047be25..dce1fc2aa 100755 --- a/tests/fp/combined_IF_vectors/extract_testfloat_vectors.py +++ b/tests/fp/combined_IF_vectors/extract_testfloat_vectors.py @@ -1,4 +1,4 @@ -#! /usr/bin/python3 +#!/usr/bin/env python3 # extract sqrt and float div testfloat vectors # author: Alessandro Maiuolo diff --git a/tests/fp/quad/fpdatasetgen.py b/tests/fp/quad/fpdatasetgen.py index 6208b1ba3..01cfd7777 100755 --- a/tests/fp/quad/fpdatasetgen.py +++ b/tests/fp/quad/fpdatasetgen.py @@ -1,4 +1,4 @@ -#!/usr/bin/python +#!/usr/bin/env python3 from fp_dataset import * #coverpoints=ibm_b1(128, 128, 'fadd.q', 2) #ibm_b1(flen, iflen, opcode, ops) diff --git a/tests/testgen/PIPELINE.py b/tests/testgen/PIPELINE.py index 6432bb023..35d040763 100755 --- a/tests/testgen/PIPELINE.py +++ b/tests/testgen/PIPELINE.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ################################## # PIPELINE.py # diff --git a/tests/testgen/covergen.py b/tests/testgen/covergen.py index 1e06e7b9c..135125f82 100755 --- a/tests/testgen/covergen.py +++ b/tests/testgen/covergen.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ################################## # covergen.py # diff --git a/tests/testgen/privileged/run.sh b/tests/testgen/privileged/run.sh index d1afb4e89..8509e77e6 100755 --- a/tests/testgen/privileged/run.sh +++ b/tests/testgen/privileged/run.sh @@ -12,7 +12,7 @@ printf "\n\n#####\nStarting tests for $1\n#####\n\n" if [[ "$2" != "-simonly" ]] then cd $WALLY/testgen/privileged - python3 "testgen-$1.py" + $RISCV/riscv-python/bin/python3 "testgen-$1.py" printf "\n\n#####\nRan testgen-$1.py Making...\n#####\n\n\n" if [[ "$2" == "-c" ]] diff --git a/tests/testgen/privileged/testgen-CAUSE.py b/tests/testgen/privileged/testgen-CAUSE.py index 0ab0128b4..12e4ef886 100755 --- a/tests/testgen/privileged/testgen-CAUSE.py +++ b/tests/testgen/privileged/testgen-CAUSE.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ################################## # testgen-CAUSE.py (new) # diff --git a/tests/testgen/privileged/testgen-CSR-PERMISSIONS.py b/tests/testgen/privileged/testgen-CSR-PERMISSIONS.py index 1cd262458..fadff0a36 100755 --- a/tests/testgen/privileged/testgen-CSR-PERMISSIONS.py +++ b/tests/testgen/privileged/testgen-CSR-PERMISSIONS.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ################################## # testgen-CSR-PERMISSIONS.py # diff --git a/tests/testgen/privileged/testgen-DELEG.py b/tests/testgen/privileged/testgen-DELEG.py index ab08d09d5..4d7a99716 100755 --- a/tests/testgen/privileged/testgen-DELEG.py +++ b/tests/testgen/privileged/testgen-DELEG.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ################################## # testgen-CAUSE.py # diff --git a/tests/testgen/privileged/testgen-EPC.py b/tests/testgen/privileged/testgen-EPC.py index 8093ef403..c9b5ad0e0 100755 --- a/tests/testgen/privileged/testgen-EPC.py +++ b/tests/testgen/privileged/testgen-EPC.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ################################## # testgen-CAUSE.py # diff --git a/tests/testgen/privileged/testgen-IE.py b/tests/testgen/privileged/testgen-IE.py index 5a82d019f..032d719d2 100755 --- a/tests/testgen/privileged/testgen-IE.py +++ b/tests/testgen/privileged/testgen-IE.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ################################## # testgen-IE.py # diff --git a/tests/testgen/privileged/testgen-IP.py b/tests/testgen/privileged/testgen-IP.py index a4910977d..2741362ed 100755 --- a/tests/testgen/privileged/testgen-IP.py +++ b/tests/testgen/privileged/testgen-IP.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ################################## # testgen-IE.py # diff --git a/tests/testgen/privileged/testgen-READONLY.py b/tests/testgen/privileged/testgen-READONLY.py index ad94b60cd..71eedbde5 100755 --- a/tests/testgen/privileged/testgen-READONLY.py +++ b/tests/testgen/privileged/testgen-READONLY.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ################################## # testgen-CAUSE.py # diff --git a/tests/testgen/privileged/testgen-RET.py b/tests/testgen/privileged/testgen-RET.py index 8921cfb8e..94d5f7262 100755 --- a/tests/testgen/privileged/testgen-RET.py +++ b/tests/testgen/privileged/testgen-RET.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ################################## # testgen-CAUSE.py # diff --git a/tests/testgen/privileged/testgen-TVAL.py b/tests/testgen/privileged/testgen-TVAL.py index 572d930c9..b5402d0e7 100755 --- a/tests/testgen/privileged/testgen-TVAL.py +++ b/tests/testgen/privileged/testgen-TVAL.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ################################## # testgen-TVAL.py # diff --git a/tests/testgen/privileged/testgen-TVEC.py b/tests/testgen/privileged/testgen-TVEC.py index fcdc80d7f..ce484c8b4 100755 --- a/tests/testgen/privileged/testgen-TVEC.py +++ b/tests/testgen/privileged/testgen-TVEC.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ################################## # testgen-TVEC.py (new) # diff --git a/tests/testgen/testgen.py b/tests/testgen/testgen.py index 02d16a319..46bd2cb75 100755 --- a/tests/testgen/testgen.py +++ b/tests/testgen/testgen.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 ################################## # testgen.py # From a30d4b29df6a99b08d9aee2b1562cab878ca329d Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 3 Jul 2024 21:34:48 -0700 Subject: [PATCH 042/219] Additional shebang updates --- bin/derivgen.pl | 2 +- bin/exe2memfile.pl | 2 +- bin/fparchtest.sh | 2 +- bin/libppa.pl | 2 +- bin/testlist.pl | 2 +- bin/vclean.pl | 2 +- sim/questa/sim-testfloat-verilator | 2 +- synthDC/extractArea.pl | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/bin/derivgen.pl b/bin/derivgen.pl index dbb856781..656612956 100755 --- a/bin/derivgen.pl +++ b/bin/derivgen.pl @@ -1,4 +1,4 @@ -#!/bin/perl -W +#!/usr/bin/env perl -w ########################################### ## derivgen.pl diff --git a/bin/exe2memfile.pl b/bin/exe2memfile.pl index 4f04ff512..314d3b989 100755 --- a/bin/exe2memfile.pl +++ b/bin/exe2memfile.pl @@ -1,4 +1,4 @@ -#!/usr/bin/perl -w +#!/usr/bin/env perl -w ########################################### ## exe2memfile.pl diff --git a/bin/fparchtest.sh b/bin/fparchtest.sh index 7ea690e96..7c5b0d28f 100755 --- a/bin/fparchtest.sh +++ b/bin/fparchtest.sh @@ -1,4 +1,4 @@ -#!/usr/bin/bash +#!/bin/bash # # fparchtest.sh # David_Harris@hmc.edu 26 December 2023 diff --git a/bin/libppa.pl b/bin/libppa.pl index 9f1e8515d..58f2a8bbf 100755 --- a/bin/libppa.pl +++ b/bin/libppa.pl @@ -1,4 +1,4 @@ -#!/bin/perl -W +#!/usr/bin/env perl -w ########################################### ## libppa.pl diff --git a/bin/testlist.pl b/bin/testlist.pl index c72b96961..861a4bc91 100755 --- a/bin/testlist.pl +++ b/bin/testlist.pl @@ -1,4 +1,4 @@ -#!/bin/perl -W +#!/usr/bin/env perl -w ########################################### ## testlist.pl diff --git a/bin/vclean.pl b/bin/vclean.pl index 294d1d435..e1c499b1c 100755 --- a/bin/vclean.pl +++ b/bin/vclean.pl @@ -1,4 +1,4 @@ -#!/usr/bin/perl -w +#!/usr/bin/env perl -w ########################################### ## vclean.pl diff --git a/sim/questa/sim-testfloat-verilator b/sim/questa/sim-testfloat-verilator index 6470837f9..1bd0386b9 100755 --- a/sim/questa/sim-testfloat-verilator +++ b/sim/questa/sim-testfloat-verilator @@ -1,4 +1,4 @@ -#!/usr/bin/bash +#!/bin/bash # sim-testfloat-verilator # David_Harris@hmc.edu 3 April 2024 diff --git a/synthDC/extractArea.pl b/synthDC/extractArea.pl index fa630a3e7..e13daa4aa 100755 --- a/synthDC/extractArea.pl +++ b/synthDC/extractArea.pl @@ -1,4 +1,4 @@ -#!/bin/perl -W +#!/usr/bin/env perl -w ########################################### ## extractArea.pl From eaac8e9b6a07d344e658cecdbd1a14a3ae65c254 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 3 Jul 2024 22:14:17 -0700 Subject: [PATCH 043/219] Speed up qemu clone with multiple submodules in parallel --- bin/wally-tool-chain-install.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 61686a22e..959ade85c 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -223,9 +223,9 @@ echo -e "Installing/Updating QEMU" echo -e "*************************************************************************" echo -e "*************************************************************************\n${ENDC}" cd "$RISCV" -if [[ ((! -e qemu) && ($(git clone --recurse-submodules https://github.com/qemu/qemu) || true)) || ($(cd qemu; git fetch; git rev-parse HEAD) != $(cd qemu; git rev-parse origin/master)) || (! -e $RISCV/include/qemu-plugin.h) ]]; then +if [[ ((! -e qemu) && ($(git clone --recurse-submodules -j ${NUM_THREADS} https://github.com/qemu/qemu) || true)) || ($(cd qemu; git fetch; git rev-parse HEAD) != $(cd qemu; git rev-parse origin/master)) || (! -e $RISCV/include/qemu-plugin.h) ]]; then cd qemu - git reset --hard && git clean -f && git checkout master && git pull --recurse-submodules + git reset --hard && git clean -f && git checkout master && git pull --recurse-submodules -j ${NUM_THREADS} ./configure --target-list=riscv64-softmmu --prefix="$RISCV" make -j ${NUM_THREADS} make install From 090a4f9544ca17a25397dcd834905aa151a22e34 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 3 Jul 2024 22:26:10 -0700 Subject: [PATCH 044/219] Add error messages --- bin/wally-tool-chain-install.sh | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 959ade85c..09efdc163 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -36,6 +36,18 @@ NUM_THREADS=8 # for >= 32GiB #NUM_THREADS=16 # for >= 64GiB set -e # break on error +STATUS="setup" # keep track of what part of the installation is running for error messages + +# Error handler +error() { + echo -e "${FAIL_COLOR}Error: $STATUS installation failed$" + echo -e "Error on line ${BASH_LINENO[0]} with command $BASH_COMMAND${ENDC}" + exit 1 +} + +trap error ERR # run error function on error + +# Get the directory of the script to find other scripts dir="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" # Colors @@ -70,6 +82,7 @@ echo "Running as root: $ROOT" echo "Installation path: $RISCV" # Install/update packages if root. Otherwise, check that packages are already installed. +STATUS="system packages" if [ "$ROOT" = true ]; then source "${dir}"/wally-package-install.sh else @@ -95,6 +108,7 @@ echo -e "*********************************************************************** echo -e "*************************************************************************\n${ENDC}" # Create python virtual environment so the python command targets our desired version of python # and installed packages are isolated from the rest of the system. +STATUS="python virtual environment" cd "$RISCV" if [ ! -e "$RISCV"/riscv-python/bin/activate ]; then # If python3.12 is avaiable, use it. Otherise, use whatever version of python3 is installed. @@ -110,6 +124,7 @@ fi source "$RISCV"/riscv-python/bin/activate # activate python virtual environment # Install python packages +STATUS="python packages" pip install -U pip pip install -U sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown pyyaml testresources riscv_config pip install -U riscv_isac # to generate new tests, such as quads with fp_dataset.py @@ -125,6 +140,7 @@ echo -e "${SUCCESS_COLOR}Python environment successfully configured.${ENDC}" if [ "$RHEL_VERSION" = 8 ] || [ "$UBUNTU_VERSION" = 20 ]; then # Newer versin of glib required for Qemu. # Anything newer than this won't build on red hat 8 + STATUS="glib" if [ ! -e "$RISCV"/include/glib-2.0 ]; then echo -e "${SECTION_COLOR}\n*************************************************************************" echo -e "*************************************************************************" @@ -149,6 +165,7 @@ fi # Newer version of gmp needed for sail-riscv model if [ "$RHEL_VERSION" = 8 ]; then + STATUS="gmp" if [ ! -e "$RISCV"/include/gmp.h ]; then echo -e "${SECTION_COLOR}\n*************************************************************************" echo -e "*************************************************************************" @@ -178,6 +195,7 @@ echo -e "*********************************************************************** echo -e "Installing/Updating RISC-V GNU Toolchain" echo -e "*************************************************************************" echo -e "*************************************************************************\n${ENDC}" +STATUS="RISC-V GNU Toolchain" cd "$RISCV" if [[ ((! -e riscv-gnu-toolchain) && ($(git clone https://github.com/riscv/riscv-gnu-toolchain) || true)) || ($(cd riscv-gnu-toolchain; git fetch; git rev-parse HEAD) != $(cd riscv-gnu-toolchain; git rev-parse origin/master)) || (! -e $RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2) ]]; then cd riscv-gnu-toolchain @@ -202,6 +220,7 @@ echo -e "*********************************************************************** echo -e "Installing/Updating elf2hex" echo -e "*************************************************************************" echo -e "*************************************************************************\n${ENDC}" +STATUS="elf2hex" cd "$RISCV" export PATH=$RISCV/bin:$PATH if [[ ((! -e elf2hex) && ($(git clone https://github.com/sifive/elf2hex.git) || true)) || ($(cd elf2hex; git fetch; git rev-parse HEAD) != $(cd elf2hex; git rev-parse origin/master)) || (! -e $RISCV/bin/riscv64-unknown-elf-elf2bin) ]]; then @@ -222,6 +241,7 @@ echo -e "*********************************************************************** echo -e "Installing/Updating QEMU" echo -e "*************************************************************************" echo -e "*************************************************************************\n${ENDC}" +STATUS="QEMU" cd "$RISCV" if [[ ((! -e qemu) && ($(git clone --recurse-submodules -j ${NUM_THREADS} https://github.com/qemu/qemu) || true)) || ($(cd qemu; git fetch; git rev-parse HEAD) != $(cd qemu; git rev-parse origin/master)) || (! -e $RISCV/include/qemu-plugin.h) ]]; then cd qemu @@ -242,6 +262,7 @@ echo -e "*********************************************************************** echo -e "Installing/Updating SPIKE" echo -e "*************************************************************************" echo -e "*************************************************************************\n${ENDC}" +STATUS="SPIKE" cd "$RISCV" if [[ ((! -e riscv-isa-sim) && ($(git clone https://github.com/riscv-software-src/riscv-isa-sim) || true)) || ($(cd riscv-isa-sim; git fetch; git rev-parse HEAD) != $(cd riscv-isa-sim; git rev-parse origin/master)) || (! -e $RISCV/lib/pkgconfig/riscv-riscv.pc) ]]; then cd riscv-isa-sim @@ -263,6 +284,7 @@ echo -e "*********************************************************************** echo -e "Installing/Updating Verilator" echo -e "*************************************************************************" echo -e "*************************************************************************\n${ENDC}" +STATUS="Verilator" cd "$RISCV" if [[ ((! -e verilator) && ($(git clone https://github.com/verilator/verilator) || true)) || ($(cd verilator; git fetch; git rev-parse HEAD) != $(cd verilator; git rev-parse origin/master)) || (! -e $RISCV/share/pkgconfig/verilator.pc) ]]; then # unsetenv VERILATOR_ROOT # For csh; ignore error if on bash @@ -292,6 +314,7 @@ if [ "$FAMILY" = rhel ]; then echo -e "Installing/Updating Opam" echo -e "*************************************************************************" echo -e "*************************************************************************\n${ENDC}" + STATUS="Opam" mkdir -p opam cd opam wget https://raw.githubusercontent.com/ocaml/opam/master/shell/install.sh @@ -306,6 +329,7 @@ echo -e "*********************************************************************** echo -e "Installing/Updating Sail Compiler" echo -e "*************************************************************************" echo -e "*************************************************************************\n${ENDC}" +STATUS="Sail Compiler" cd "$RISCV" opam init -y --disable-sandboxing opam update -y @@ -319,6 +343,7 @@ echo -e "*********************************************************************** echo -e "Installing/Updating RISC-V Sail Model" echo -e "*************************************************************************" echo -e "*************************************************************************\n${ENDC}" +STATUS="RISC-V Sail Model" if [[ ((! -e sail-riscv) && ($(git clone https://github.com/riscv/sail-riscv.git) || true)) || ($(cd sail-riscv; git fetch; git rev-parse HEAD) != $(cd sail-riscv; git rev-parse origin/master)) || (! -e $RISCV/bin/riscv_sim_RV32) ]]; then eval $(opam config env) cd sail-riscv @@ -340,6 +365,7 @@ echo -e "*********************************************************************** echo -e "Installing/Updating RISCOF" echo -e "*************************************************************************" echo -e "*************************************************************************\n${ENDC}" +STATUS="RISCOF" pip3 install git+https://github.com/riscv/riscof.git # Download OSU Skywater 130 cell library @@ -348,6 +374,7 @@ echo -e "*********************************************************************** echo -e "Installing/Updating OSU Skywater 130 cell library" echo -e "*************************************************************************" echo -e "*************************************************************************\n${ENDC}" +STATUS="OSU Skywater 130 cell library" mkdir -p "$RISCV"/cad/lib cd "$RISCV"/cad/lib if [[ ((! -e sky130_osu_sc_t12) && ($(git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12) || true)) || ($(cd sky130_osu_sc_t12; git fetch; git rev-parse HEAD) != $(cd sky130_osu_sc_t12; git rev-parse origin/main)) ]]; then @@ -364,6 +391,7 @@ echo -e "*********************************************************************** echo -e "Downloading Site Setup Script" echo -e "*************************************************************************" echo -e "*************************************************************************\n${ENDC}" +STATUS="site-setup scripts" cd "$RISCV" if [ ! -e "${RISCV}"/site-setup.sh ]; then wget https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.sh From c7d556a7ed4f60a0a27f80f656bf2b0cf2aa16fa Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 3 Jul 2024 23:42:31 -0700 Subject: [PATCH 045/219] Update installation script comments --- bin/wally-distro-check.sh | 3 +- bin/wally-package-install.sh | 15 ++--- bin/wally-tool-chain-install.sh | 99 +++++++++++++++++++++------------ 3 files changed, 73 insertions(+), 44 deletions(-) diff --git a/bin/wally-distro-check.sh b/bin/wally-distro-check.sh index 79a62dfd0..d8c87f2c4 100755 --- a/bin/wally-distro-check.sh +++ b/bin/wally-distro-check.sh @@ -36,7 +36,8 @@ SECTION_COLOR='\033[95m'$BOLD OK_COLOR='\033[94m' WARNING_COLOR='\033[93m' FAIL_COLOR='\033[91m' -ENDC='\033[0m' +ENDC='\033[0m' # Reset to default color + echo -e "${SECTION_COLOR}\n*************************************************************************" echo -e "*************************************************************************" diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index fd9031ccc..d9f668c51 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -34,7 +34,7 @@ BOLD='\033[1m' SECTION_COLOR='\033[95m'$BOLD SUCCESS_COLOR='\033[92m' FAIL_COLOR='\033[91m' -ENDC='\033[0m' +ENDC='\033[0m' # Reset to default color # If run standalone, determine distro information. Otherwise, use info from main install script if [ -z "$FAMILY" ]; then @@ -42,11 +42,12 @@ if [ -z "$FAMILY" ]; then source "${dir}"/wally-distro-check.sh fi -# Generate list of packages to install, determined based on distro + +# Generate list of packages to install and package manager commands based on distro +# Packages are grouped by which tool requires them. If multiple tools need a package, it is included in the first tool only if [ "$FAMILY" = rhel ]; then PACKAGE_MANAGER="dnf" UPDATE_COMMAND="sudo dnf update -y" - # Packages are grouped by which tool requires them. If multiple tools need a package, it is included in the first tool only GENERAL_PACKAGES="git make cmake python3.12 python3-pip curl wget ftp tar pkgconf-pkg-config dialog mutt ssmtp" GNU_PACKAGES="autoconf automake libmpc-devel mpfr-devel gmp-devel gawk bison flex texinfo gperf libtool patchutils bc gcc gcc-c++ zlib-devel expat-devel libslirp-devel" QEMU_PACKAGES="glib2-devel libfdt-devel pixman-devel bzip2 ninja-build" @@ -63,7 +64,6 @@ if [ "$FAMILY" = rhel ]; then elif [ "$FAMILY" = ubuntu ]; then PACKAGE_MANAGER=apt UPDATE_COMMAND="sudo apt update -y && sudo apt upgrade -y" - # Packages are grouped by which tool requires them. If multiple tools need a package, it is included in the first tool only GENERAL_PACKAGES="git make cmake python3 python3-pip python3-venv curl wget ftp tar pkg-config dialog mutt ssmtp" GNU_PACKAGES="autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat1-dev ninja-build libglib2.0-dev libslirp-dev" QEMU_PACKAGES="libfdt-dev libpixman-1-dev" @@ -81,7 +81,8 @@ elif [ "$FAMILY" = ubuntu ]; then fi fi -# Check packages are installed or install/update them depending on passed flag. + +# Check if required packages are installed or install/update them depending on passed flag. if [ "${1}" = "--check" ]; then echo -e "${SECTION_COLOR}\n*************************************************************************" echo -e "*************************************************************************" @@ -107,7 +108,7 @@ else echo -e "Installing/Updating Dependencies from Package Manager" echo -e "*************************************************************************" echo -e "*************************************************************************\n${ENDC}" - # Extra red hat commands to set up package manager with extra repos + # Enable extra repos necessary for rhel if [ "$FAMILY" = rhel ]; then sudo dnf install -y dnf-plugins-core sudo dnf group install -y "Development Tools" @@ -126,7 +127,7 @@ else # Update and Upgrade tools eval "$UPDATE_COMMAND" - # Install packages listed above + # Install packages listed above using appropriate package manager sudo "$PACKAGE_MANAGER" install -y $GENERAL_PACKAGES $GNU_PACKAGES $QEMU_PACKAGES $SPIKE_PACKAGES $VERILATOR_PACKAGES $SAIL_PACKAGES $BUILDROOT_PACKAGES $OTHER_PACKAGES echo -e "${SUCCESS_COLOR}Packages successfully installed.${ENDC}" fi diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 09efdc163..bb243ce7a 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -13,7 +13,7 @@ ## A component of the CORE-V-WALLY configurable RISC-V project. ## https://github.com/openhwgroup/cvw ## -## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University ## ## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 ## @@ -35,9 +35,6 @@ NUM_THREADS=8 # for >= 32GiB #NUM_THREADS=16 # for >= 64GiB -set -e # break on error -STATUS="setup" # keep track of what part of the installation is running for error messages - # Error handler error() { echo -e "${FAIL_COLOR}Error: $STATUS installation failed$" @@ -45,9 +42,11 @@ error() { exit 1 } -trap error ERR # run error function on error +set -e # break on error +trap error ERR # run error handler on error +STATUS="setup" # keep track of what part of the installation is running for error messages -# Get the directory of the script to find other scripts +# Determine script directory to locate related scripts dir="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" # Colors @@ -58,7 +57,7 @@ OK_COLOR='\033[94m' SUCCESS_COLOR='\033[92m' WARNING_COLOR='\033[93m' FAIL_COLOR='\033[91m' -ENDC='\033[0m' +ENDC='\033[0m' # Reset to default color # Get Linux distro and version source "${dir}"/wally-distro-check.sh @@ -66,22 +65,27 @@ source "${dir}"/wally-distro-check.sh # Check if root ROOT=$( [ "${EUID:=$(id -u)}" = 0 ] && echo true || echo false); -# All tools will be installed under the $RISCV directory. By default, if run as root (with sudo) this is set to -# /opt/riscv. Otherwise, it is set to ~/riscv. This value can be overridden with an argument passed to the script. +# Set installation directory based on execution privileges +# If the script is run as root, the default installation path is /opt/riscv +# If the script is run as a user, the default installation path is ~/riscv +# The installation path can be overridden with an argument passed to the script. if [ "$ROOT" = true ]; then export RISCV="${1:-/opt/riscv}" else export RISCV="${1:-$HOME/riscv}" fi +# Set environment variables export PATH=$PATH:$RISCV/bin:/usr/bin export PKG_CONFIG_PATH=$RISCV/lib64/pkgconfig:$RISCV/lib/pkgconfig:$RISCV/share/pkgconfig:$RISCV/lib/x86_64-linux-gnu/pkgconfig:$PKG_CONFIG_PATH -mkdir -p "$RISCV" +# Create installation directory +mkdir -p "$RISCV" echo "Running as root: $ROOT" echo "Installation path: $RISCV" -# Install/update packages if root. Otherwise, check that packages are already installed. + +# Install/update system packages if root. Otherwise, check that packages are already installed. STATUS="system packages" if [ "$ROOT" = true ]; then source "${dir}"/wally-package-install.sh @@ -89,10 +93,9 @@ else source "${dir}"/wally-package-install.sh --check fi +# Enable newer version of gcc for older distros (required for QEMU/Verilator) if [ "$FAMILY" = rhel ]; then - # A newer version of gcc is required for qemu - source /opt/rh/gcc-toolset-13/enable # activate gcc13 - # Newer version of gcc needed for Ubuntu 20.04 for Verilator + source /opt/rh/gcc-toolset-13/enable elif [ "$UBUNTU_VERSION" = 20 ]; then mkdir -p "$RISCV"/gcc-10/bin for f in gcc cpp g++ gcc-ar gcc-nm gcc-ranlib gcov gcov-dump gcov-tool lto-dump; do @@ -101,12 +104,13 @@ elif [ "$UBUNTU_VERSION" = 20 ]; then export PATH="$RISCV"/gcc-10/bin:$PATH fi + echo -e "${SECTION_COLOR}\n*************************************************************************" echo -e "*************************************************************************" echo -e "Setting up Python Environment" echo -e "*************************************************************************" echo -e "*************************************************************************\n${ENDC}" -# Create python virtual environment so the python command targets our desired version of python +# Create python virtual environment so the python command targets desired version of python # and installed packages are isolated from the rest of the system. STATUS="python virtual environment" cd "$RISCV" @@ -119,8 +123,9 @@ if [ ! -e "$RISCV"/riscv-python/bin/activate ]; then fi echo -e "${OK_COLOR}Python virtual environment created.\nInstalling pip packages.${ENDC}" else - echo -e "${OK_COLOR}Python virtual environment already exists.\Updating pip packages.${ENDC}" + echo -e "${OK_COLOR}Python virtual environment already exists.\nUpdating pip packages.${ENDC}" fi + source "$RISCV"/riscv-python/bin/activate # activate python virtual environment # Install python packages @@ -129,13 +134,15 @@ pip install -U pip pip install -U sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown pyyaml testresources riscv_config pip install -U riscv_isac # to generate new tests, such as quads with fp_dataset.py -# z3 is eeded for sail and not availabe from dnf for rhel 8 +# z3 is needed for sail and not availabe from dnf for rhel 8 if [ "$RHEL_VERSION" = 8 ]; then pip install -U z3-solver fi + source "$RISCV"/riscv-python/bin/activate # reload python virtual environment echo -e "${SUCCESS_COLOR}Python environment successfully configured.${ENDC}" + # Extra dependecies needed for older distros that don't have new enough versions available from package manager if [ "$RHEL_VERSION" = 8 ] || [ "$UBUNTU_VERSION" = 20 ]; then # Newer versin of glib required for Qemu. @@ -147,8 +154,7 @@ if [ "$RHEL_VERSION" = 8 ] || [ "$UBUNTU_VERSION" = 20 ]; then echo -e "Installing glib" echo -e "*************************************************************************" echo -e "*************************************************************************\n${ENDC}" - # Meson is needed to build glib - pip install -U meson + pip install -U meson # Meson is needed to build glib cd "$RISCV" wget https://download.gnome.org/sources/glib/2.70/glib-2.70.5.tar.xz tar -xJf glib-2.70.5.tar.xz @@ -186,7 +192,10 @@ if [ "$RHEL_VERSION" = 8 ]; then fi fi -# gcc cross-compiler (https://github.com/riscv-collab/riscv-gnu-toolchain) + +# RISC-V GNU Toolchain (https://github.com/riscv-collab/riscv-gnu-toolchain) +# The RISC-V GNU Toolchain includes the GNU Compiler Collection (gcc), GNU Binutils, Newlib, +# and the GNU Debugger Project (gdb). It is a collection of tools used to compile RISC-V programs. # To install GCC from source can take hours to compile. # This configuration enables multilib to target many flavors of RISC-V. # This book is tested with GCC 13.2.0 @@ -208,8 +217,9 @@ else echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain already up to date${ENDC}" fi + # elf2hex (https://github.com/sifive/elf2hex) -#The elf2hex utility to converts executable files into hexadecimal files for Verilog simulation. +# The elf2hex utility to converts executable files into hexadecimal files for Verilog simulation. # Note: The exe2hex utility that comes with Spike doesn’t work for our purposes because it doesn’t # handle programs that start at 0x80000000. The SiFive version above is touchy to install. # For example, if Python version 2.x is in your path, it won’t install correctly. @@ -235,7 +245,9 @@ else echo -e "${SUCCESS_COLOR}elf2hex already up to date${ENDC}" fi + # QEMU (https://www.qemu.org/docs/master/system/target-riscv.html) +# QEMU is an open source machine emulator and virtualizer capable of emulating RISC-V echo -e "${SECTION_COLOR}\n*************************************************************************" echo -e "*************************************************************************" echo -e "Installing/Updating QEMU" @@ -254,9 +266,9 @@ else echo -e "${SUCCESS_COLOR}QEMU already up to date${ENDC}" fi + # Spike (https://github.com/riscv-software-src/riscv-isa-sim) -# Spike also takes a while to install and compile, but this can be done concurrently -# with the GCC installation. +# Spike is a reference model for RISC-V. It is a functional simulator that can be used to run RISC-V programs. echo -e "${SECTION_COLOR}\n*************************************************************************" echo -e "*************************************************************************" echo -e "Installing/Updating SPIKE" @@ -277,8 +289,11 @@ else echo -e "${SUCCESS_COLOR}Spike already up to date${ENDC}" fi -# Wally needs Verilator 5.021 or later. -# Verilator needs to be built from source to get the latest version + +# Verilator (https://github.com/verilator/verilator) +# Verilator is a fast open-source Verilog simulator that compiles synthesizable Verilog code into C++ code. +# It is used for linting and simulation of Wally. +# Verilator needs to be built from source to get the latest version (Wally needs 5.021 or later). echo -e "\n${SECTION_COLOR}*************************************************************************" echo -e "*************************************************************************" echo -e "Installing/Updating Verilator" @@ -287,7 +302,6 @@ echo -e "*********************************************************************** STATUS="Verilator" cd "$RISCV" if [[ ((! -e verilator) && ($(git clone https://github.com/verilator/verilator) || true)) || ($(cd verilator; git fetch; git rev-parse HEAD) != $(cd verilator; git rev-parse origin/master)) || (! -e $RISCV/share/pkgconfig/verilator.pc) ]]; then - # unsetenv VERILATOR_ROOT # For csh; ignore error if on bash unset VERILATOR_ROOT # For bash cd verilator git reset --hard && git clean -f && git checkout master && git pull @@ -300,15 +314,11 @@ else echo -e "${SUCCESS_COLOR}Verilator already up to date${ENDC}" fi -# RISC-V Sail Model (https://github.com/riscv/sail-riscv) -# The RISC-V Sail Model is the golden reference model for RISC-V. It is written in Sail, -# a language designed for expressing the semantics of an ISA. Sail itself is written in -# OCaml, which is an object-oriented extension of ML, which in turn is a functional programming -# language suited to formal verification. The Sail compiler is installed with the opam OCcaml -# package manager. The Sail compiler has so many dependencies that it can be difficult to install, -# but a binary release of it should be available soon, removing the need to use opam. + cd "$RISCV" if [ "$FAMILY" = rhel ]; then + # Install opam from binary disribution on rhel as it is not available from dnf + # Opam is needed to install the sail compiler echo -e "${SECTION_COLOR}\n*************************************************************************" echo -e "*************************************************************************" echo -e "Installing/Updating Opam" @@ -324,6 +334,13 @@ if [ "$FAMILY" = rhel ]; then echo -e "${SUCCESS_COLOR}Opam successfully installed/updated${ENDC}" fi +# Sail Compiler (https://github.com/rems-project/sail) +# Sail is a formal specification language designed for describing the semantics of an ISA. +# It is used to generate the RISC-V Sail Model, which is the golden reference model for RISC-V. +# The Sail Compiler is written in OCaml, which is an object-oriented extension of ML, which in turn +# is a functional programming language suited to formal verification. The Sail compiler is installed +# with the opam OCaml package manager. It has so many dependencies that it can be difficult to install, +# but a binary release of it should be available soon, removing the need to use opam. echo -e "${SECTION_COLOR}\n*************************************************************************" echo -e "*************************************************************************" echo -e "Installing/Updating Sail Compiler" @@ -338,6 +355,8 @@ opam switch create 5.1.0 || opam switch set 5.1.0 opam install sail -y echo -e "${SUCCESS_COLOR}Sail Compiler successfully installed/updated${ENDC}" +# RISC-V Sail Model (https://github.com/riscv/sail-riscv) +# The RISC-V Sail Model is the golden reference model for RISC-V. It is written in Sail (described above) echo -e "${SECTION_COLOR}\n*************************************************************************" echo -e "*************************************************************************" echo -e "Installing/Updating RISC-V Sail Model" @@ -359,7 +378,9 @@ else echo -e "${SUCCESS_COLOR}RISC-V Sail Model already up to date${ENDC}" fi -# riscof + +# RISCOF (https://github.com/riscv/riscof.git) +# RISCOF is a RISC-V compliance test framework that is used to run the RISC-V Arch Tests. echo -e "${SECTION_COLOR}\n*************************************************************************" echo -e "*************************************************************************" echo -e "Installing/Updating RISCOF" @@ -368,7 +389,9 @@ echo -e "*********************************************************************** STATUS="RISCOF" pip3 install git+https://github.com/riscv/riscof.git -# Download OSU Skywater 130 cell library + +# OSU Skywater 130 cell library (https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12) +# The OSU Skywater 130 cell library is a standard cell library that is used to synthesize Wally. echo -e "${SECTION_COLOR}\n*************************************************************************" echo -e "*************************************************************************" echo -e "Installing/Updating OSU Skywater 130 cell library" @@ -385,7 +408,10 @@ else echo -e "${SUCCESS_COLOR}OSU Skywater library already up to date${ENDC}" fi -# site-setup script + +# Download site-setup scripts +# The site-setup script is used to set up the environment for the RISC-V tools and EDA tools by setting +# the PATH and other environment variables. It also sources the Python virtual environment. echo -e "${SECTION_COLOR}\n*************************************************************************" echo -e "*************************************************************************" echo -e "Downloading Site Setup Script" @@ -396,6 +422,7 @@ cd "$RISCV" if [ ! -e "${RISCV}"/site-setup.sh ]; then wget https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.sh wget https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.csh + # Add necessary lines to site-setup script to activate newer version of gcc for older distros if [ "$FAMILY" = rhel ]; then echo "source /opt/rh/gcc-toolset-13/enable" >> site-setup.sh elif [ "$UBUNTU_VERSION" = 20 ]; then From 985d9b4edc16bf639b969a8c743ce209ff62dbd9 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 3 Jul 2024 23:47:26 -0700 Subject: [PATCH 046/219] Update run_vcs shebang after merge --- sim/vcs/run_vcs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/vcs/run_vcs b/sim/vcs/run_vcs index a9e9c2fca..00bfea9c7 100755 --- a/sim/vcs/run_vcs +++ b/sim/vcs/run_vcs @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 # run_vcs # David_Harris@hmc.edu 2 July 2024 From a7b78e6773861b5b1c5c7f8e26d58296ed2388da Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 4 Jul 2024 01:48:20 -0700 Subject: [PATCH 047/219] Fix perl shebang lines --- bin/exe2memfile.pl | 2 +- bin/libppa.pl | 2 +- bin/testlist.pl | 2 +- bin/vclean.pl | 2 +- synthDC/extractArea.pl | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/bin/exe2memfile.pl b/bin/exe2memfile.pl index 314d3b989..2d09c1fdb 100755 --- a/bin/exe2memfile.pl +++ b/bin/exe2memfile.pl @@ -1,4 +1,4 @@ -#!/usr/bin/env perl -w +#!/usr/bin/env -S perl -w ########################################### ## exe2memfile.pl diff --git a/bin/libppa.pl b/bin/libppa.pl index 58f2a8bbf..bb3d4b729 100755 --- a/bin/libppa.pl +++ b/bin/libppa.pl @@ -1,4 +1,4 @@ -#!/usr/bin/env perl -w +#!/usr/bin/env -S perl -w ########################################### ## libppa.pl diff --git a/bin/testlist.pl b/bin/testlist.pl index 861a4bc91..50b77eb78 100755 --- a/bin/testlist.pl +++ b/bin/testlist.pl @@ -1,4 +1,4 @@ -#!/usr/bin/env perl -w +#!/usr/bin/env -S perl -w ########################################### ## testlist.pl diff --git a/bin/vclean.pl b/bin/vclean.pl index e1c499b1c..94a14c54c 100755 --- a/bin/vclean.pl +++ b/bin/vclean.pl @@ -1,4 +1,4 @@ -#!/usr/bin/env perl -w +#!/usr/bin/env -S perl -w ########################################### ## vclean.pl diff --git a/synthDC/extractArea.pl b/synthDC/extractArea.pl index e13daa4aa..cd795d3ff 100755 --- a/synthDC/extractArea.pl +++ b/synthDC/extractArea.pl @@ -1,4 +1,4 @@ -#!/usr/bin/env perl -w +#!/usr/bin/env -S perl -w ########################################### ## extractArea.pl From 47501b9ef4a2942cfdd06401b7dde97125459fdd Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 4 Jul 2024 13:44:50 -0700 Subject: [PATCH 048/219] Add comments to site-setup for new gcc --- bin/wally-tool-chain-install.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index bb243ce7a..2a34ae937 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -424,9 +424,12 @@ if [ ! -e "${RISCV}"/site-setup.sh ]; then wget https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.csh # Add necessary lines to site-setup script to activate newer version of gcc for older distros if [ "$FAMILY" = rhel ]; then + echo "# Activate newer gcc version" >> site-setup.sh echo "source /opt/rh/gcc-toolset-13/enable" >> site-setup.sh elif [ "$UBUNTU_VERSION" = 20 ]; then + echo "# Activate newer gcc version" >> site-setup.sh echo "export PATH=\$RISCV/gcc-10/bin:\$PATH" >> site-setup.sh + echo "# Activate newer gcc version" >> site-setup.csh echo "prepend PATH \$RISCV/gcc-10/bin" >> site-setup.csh fi echo -e "${SUCCESS_COLOR}Site setup script successfully downloaded${ENDC}" From 6d46549ee378d537c0dfc6767f2c04ec883adeb6 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 4 Jul 2024 13:45:24 -0700 Subject: [PATCH 049/219] Fix setup.csh typo --- setup.csh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/setup.csh b/setup.csh index ae86d4737..da617202c 100755 --- a/setup.csh +++ b/setup.csh @@ -18,7 +18,7 @@ else if ( -e ~/riscv ) then else # set the $RISCV directory here and remove the subsequent two lines # setenv RISCV - echo "\$RISCV directory not found. Checked /opt/riscv and ~/riscv. Edit setup.sh to point to your custom \$RISCV directory." + echo "\$RISCV directory not found. Checked /opt/riscv and ~/riscv. Edit setup.csh to point to your custom \$RISCV directory." exit 1; endif echo \$RISCV set to "${RISCV}" From 70a65e2d6bdbf32fa2f81b91c3775f9a4678f2d5 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 8 Jul 2024 06:50:29 -0700 Subject: [PATCH 050/219] Cleanup --- bin/wally-tool-chain-install.sh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 2a34ae937..91ceea495 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -37,7 +37,7 @@ NUM_THREADS=8 # for >= 32GiB # Error handler error() { - echo -e "${FAIL_COLOR}Error: $STATUS installation failed$" + echo -e "${FAIL_COLOR}Error: $STATUS installation failed" echo -e "Error on line ${BASH_LINENO[0]} with command $BASH_COMMAND${ENDC}" exit 1 } @@ -347,6 +347,7 @@ echo -e "Installing/Updating Sail Compiler" echo -e "*************************************************************************" echo -e "*************************************************************************\n${ENDC}" STATUS="Sail Compiler" +OPAMROOTISOK=1 # Silence warnings about running opam as root cd "$RISCV" opam init -y --disable-sandboxing opam update -y From bea95c7d5433c16e03c2bbb1992b81685e4fb0a4 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 8 Jul 2024 07:21:08 -0700 Subject: [PATCH 051/219] Refactor section headers --- bin/wally-distro-check.sh | 9 ++- bin/wally-package-install.sh | 20 +++--- bin/wally-tool-chain-install.sh | 121 ++++++++++---------------------- 3 files changed, 52 insertions(+), 98 deletions(-) diff --git a/bin/wally-distro-check.sh b/bin/wally-distro-check.sh index d8c87f2c4..1bf8d666b 100755 --- a/bin/wally-distro-check.sh +++ b/bin/wally-distro-check.sh @@ -38,12 +38,11 @@ WARNING_COLOR='\033[93m' FAIL_COLOR='\033[91m' ENDC='\033[0m' # Reset to default color - -echo -e "${SECTION_COLOR}\n*************************************************************************" -echo -e "*************************************************************************" +printf "${SECTION_COLOR}%$(tput cols)s" | tr ' ' '#' +printf "%$(tput cols)s" | tr ' ' '#' echo -e "Checking System Requirements and Configuring Installation" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n${ENDC}" +printf "%$(tput cols)s" | tr ' ' '#' +printf "%$(tput cols)s${ENDC}" | tr ' ' '#' # Get distribution information test -e /etc/os-release && os_release="/etc/os-release" || os_release="/usr/lib/os-release" diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index d9f668c51..39cdd76c1 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -84,11 +84,12 @@ fi # Check if required packages are installed or install/update them depending on passed flag. if [ "${1}" = "--check" ]; then - echo -e "${SECTION_COLOR}\n*************************************************************************" - echo -e "*************************************************************************" + printf "${SECTION_COLOR}%$(tput cols)s" | tr ' ' '#' + printf "%$(tput cols)s" | tr ' ' '#' echo -e "Checking Dependencies from Package Manager" - echo -e "*************************************************************************" - echo -e "*************************************************************************\n${ENDC}" + printf "%$(tput cols)s" | tr ' ' '#' + printf "%$(tput cols)s${ENDC}" | tr ' ' '#' + if [ "$FAMILY" = rhel ]; then for pack in $GENERAL_PACKAGES $GNU_PACKAGES $QEMU_PACKAGES $SPIKE_PACKAGES $VERILATOR_PACKAGES $SAIL_PACKAGES $BUILDROOT_PACKAGES $OTHER_PACKAGES; do rpm -q "$pack" > /dev/null || (echo -e "${FAIL_COLOR}Missing packages detected (${WARNING_COLOR}$pack${FAIL_COLOR}). Run as root to auto-install or run wally-package-install.sh first.${ENDC}" && exit 1) @@ -103,11 +104,12 @@ else # Check if root, otherwise exit with error message [ "${EUID:=$(id -u)}" -ne 0 ] && echo -e "\n${FAIL_COLOR}Must be run as root${ENDC}" && exit 1 - echo -e "${SECTION_COLOR}\n*************************************************************************" - echo -e "*************************************************************************" - echo -e "Installing/Updating Dependencies from Package Manager" - echo -e "*************************************************************************" - echo -e "*************************************************************************\n${ENDC}" + printf "${SECTION_COLOR}%$(tput cols)s" | tr ' ' '#' + printf "%$(tput cols)s" | tr ' ' '#' + echo -e ""Installing/Updating Dependencies from Package Manager"" + printf "%$(tput cols)s" | tr ' ' '#' + printf "%$(tput cols)s${ENDC}" | tr ' ' '#' + # Enable extra repos necessary for rhel if [ "$FAMILY" = rhel ]; then sudo dnf install -y dnf-plugins-core diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 91ceea495..8648a59b3 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -35,20 +35,6 @@ NUM_THREADS=8 # for >= 32GiB #NUM_THREADS=16 # for >= 64GiB -# Error handler -error() { - echo -e "${FAIL_COLOR}Error: $STATUS installation failed" - echo -e "Error on line ${BASH_LINENO[0]} with command $BASH_COMMAND${ENDC}" - exit 1 -} - -set -e # break on error -trap error ERR # run error handler on error -STATUS="setup" # keep track of what part of the installation is running for error messages - -# Determine script directory to locate related scripts -dir="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" - # Colors BOLD='\033[1m' UNDERLINE='\033[4m' @@ -59,6 +45,29 @@ WARNING_COLOR='\033[93m' FAIL_COLOR='\033[91m' ENDC='\033[0m' # Reset to default color +# Error handler +error() { + echo -e "${FAIL_COLOR}Error: $STATUS installation failed" + echo -e "Error on line ${BASH_LINENO[0]} with command $BASH_COMMAND${ENDC}" + exit 1 +} + +# Print section header +section_header() { + printf "${SECTION_COLOR}%$(tput cols)s" | tr ' ' '#' + printf "%$(tput cols)s" | tr ' ' '#' + echo -e "$1" + printf "%$(tput cols)s" | tr ' ' '#' + printf "%$(tput cols)s${ENDC}" | tr ' ' '#' +} + +set -e # break on error +trap error ERR # run error handler on error +STATUS="setup" # keep track of what part of the installation is running for error messages + +# Determine script directory to locate related scripts +dir="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" + # Get Linux distro and version source "${dir}"/wally-distro-check.sh @@ -105,13 +114,9 @@ elif [ "$UBUNTU_VERSION" = 20 ]; then fi -echo -e "${SECTION_COLOR}\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Setting up Python Environment" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n${ENDC}" # Create python virtual environment so the python command targets desired version of python # and installed packages are isolated from the rest of the system. +section_header "Setting up Python Environment" STATUS="python virtual environment" cd "$RISCV" if [ ! -e "$RISCV"/riscv-python/bin/activate ]; then @@ -149,11 +154,7 @@ if [ "$RHEL_VERSION" = 8 ] || [ "$UBUNTU_VERSION" = 20 ]; then # Anything newer than this won't build on red hat 8 STATUS="glib" if [ ! -e "$RISCV"/include/glib-2.0 ]; then - echo -e "${SECTION_COLOR}\n*************************************************************************" - echo -e "*************************************************************************" - echo -e "Installing glib" - echo -e "*************************************************************************" - echo -e "*************************************************************************\n${ENDC}" + section_header "Installing glib" pip install -U meson # Meson is needed to build glib cd "$RISCV" wget https://download.gnome.org/sources/glib/2.70/glib-2.70.5.tar.xz @@ -173,11 +174,7 @@ fi if [ "$RHEL_VERSION" = 8 ]; then STATUS="gmp" if [ ! -e "$RISCV"/include/gmp.h ]; then - echo -e "${SECTION_COLOR}\n*************************************************************************" - echo -e "*************************************************************************" - echo -e "Installing gmp" - echo -e "*************************************************************************" - echo -e "*************************************************************************\n${ENDC}" + section_header "Installing gmp" cd "$RISCV" wget https://ftp.gnu.org/gnu/gmp/gmp-6.3.0.tar.xz tar -xJf gmp-6.3.0.tar.xz @@ -199,11 +196,7 @@ fi # To install GCC from source can take hours to compile. # This configuration enables multilib to target many flavors of RISC-V. # This book is tested with GCC 13.2.0 -echo -e "${SECTION_COLOR}\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Installing/Updating RISC-V GNU Toolchain" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n${ENDC}" +section_header "Installing/Updating RISC-V GNU Toolchain" STATUS="RISC-V GNU Toolchain" cd "$RISCV" if [[ ((! -e riscv-gnu-toolchain) && ($(git clone https://github.com/riscv/riscv-gnu-toolchain) || true)) || ($(cd riscv-gnu-toolchain; git fetch; git rev-parse HEAD) != $(cd riscv-gnu-toolchain; git rev-parse origin/master)) || (! -e $RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2) ]]; then @@ -225,11 +218,7 @@ fi # For example, if Python version 2.x is in your path, it won’t install correctly. # Also, be sure riscv64-unknown-elf-objcopy shows up in your path in $RISCV/riscv-gnu-toolchain/bin # at the time of compilation, or elf2hex won’t work properly. -echo -e "${SECTION_COLOR}\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Installing/Updating elf2hex" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n${ENDC}" +section_header "Installing/Updating elf2hex" STATUS="elf2hex" cd "$RISCV" export PATH=$RISCV/bin:$PATH @@ -248,11 +237,7 @@ fi # QEMU (https://www.qemu.org/docs/master/system/target-riscv.html) # QEMU is an open source machine emulator and virtualizer capable of emulating RISC-V -echo -e "${SECTION_COLOR}\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Installing/Updating QEMU" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n${ENDC}" +section_header "Installing/Updating QEMU" STATUS="QEMU" cd "$RISCV" if [[ ((! -e qemu) && ($(git clone --recurse-submodules -j ${NUM_THREADS} https://github.com/qemu/qemu) || true)) || ($(cd qemu; git fetch; git rev-parse HEAD) != $(cd qemu; git rev-parse origin/master)) || (! -e $RISCV/include/qemu-plugin.h) ]]; then @@ -269,11 +254,7 @@ fi # Spike (https://github.com/riscv-software-src/riscv-isa-sim) # Spike is a reference model for RISC-V. It is a functional simulator that can be used to run RISC-V programs. -echo -e "${SECTION_COLOR}\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Installing/Updating SPIKE" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n${ENDC}" +section_header "Installing/Updating SPIKE" STATUS="SPIKE" cd "$RISCV" if [[ ((! -e riscv-isa-sim) && ($(git clone https://github.com/riscv-software-src/riscv-isa-sim) || true)) || ($(cd riscv-isa-sim; git fetch; git rev-parse HEAD) != $(cd riscv-isa-sim; git rev-parse origin/master)) || (! -e $RISCV/lib/pkgconfig/riscv-riscv.pc) ]]; then @@ -294,11 +275,7 @@ fi # Verilator is a fast open-source Verilog simulator that compiles synthesizable Verilog code into C++ code. # It is used for linting and simulation of Wally. # Verilator needs to be built from source to get the latest version (Wally needs 5.021 or later). -echo -e "\n${SECTION_COLOR}*************************************************************************" -echo -e "*************************************************************************" -echo -e "Installing/Updating Verilator" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n${ENDC}" +section_header "Installing/Updating Verilator" STATUS="Verilator" cd "$RISCV" if [[ ((! -e verilator) && ($(git clone https://github.com/verilator/verilator) || true)) || ($(cd verilator; git fetch; git rev-parse HEAD) != $(cd verilator; git rev-parse origin/master)) || (! -e $RISCV/share/pkgconfig/verilator.pc) ]]; then @@ -319,11 +296,7 @@ cd "$RISCV" if [ "$FAMILY" = rhel ]; then # Install opam from binary disribution on rhel as it is not available from dnf # Opam is needed to install the sail compiler - echo -e "${SECTION_COLOR}\n*************************************************************************" - echo -e "*************************************************************************" - echo -e "Installing/Updating Opam" - echo -e "*************************************************************************" - echo -e "*************************************************************************\n${ENDC}" + section_header "Installing/Updating Opam" STATUS="Opam" mkdir -p opam cd opam @@ -341,11 +314,7 @@ fi # is a functional programming language suited to formal verification. The Sail compiler is installed # with the opam OCaml package manager. It has so many dependencies that it can be difficult to install, # but a binary release of it should be available soon, removing the need to use opam. -echo -e "${SECTION_COLOR}\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Installing/Updating Sail Compiler" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n${ENDC}" +section_header "Installing/Updating Sail Compiler" STATUS="Sail Compiler" OPAMROOTISOK=1 # Silence warnings about running opam as root cd "$RISCV" @@ -358,11 +327,7 @@ echo -e "${SUCCESS_COLOR}Sail Compiler successfully installed/updated${ENDC}" # RISC-V Sail Model (https://github.com/riscv/sail-riscv) # The RISC-V Sail Model is the golden reference model for RISC-V. It is written in Sail (described above) -echo -e "${SECTION_COLOR}\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Installing/Updating RISC-V Sail Model" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n${ENDC}" +section_header "Installing/Updating RISC-V Sail Model" STATUS="RISC-V Sail Model" if [[ ((! -e sail-riscv) && ($(git clone https://github.com/riscv/sail-riscv.git) || true)) || ($(cd sail-riscv; git fetch; git rev-parse HEAD) != $(cd sail-riscv; git rev-parse origin/master)) || (! -e $RISCV/bin/riscv_sim_RV32) ]]; then eval $(opam config env) @@ -382,22 +347,14 @@ fi # RISCOF (https://github.com/riscv/riscof.git) # RISCOF is a RISC-V compliance test framework that is used to run the RISC-V Arch Tests. -echo -e "${SECTION_COLOR}\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Installing/Updating RISCOF" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n${ENDC}" +section_header "Installing/Updating RISCOF" STATUS="RISCOF" pip3 install git+https://github.com/riscv/riscof.git # OSU Skywater 130 cell library (https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12) # The OSU Skywater 130 cell library is a standard cell library that is used to synthesize Wally. -echo -e "${SECTION_COLOR}\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Installing/Updating OSU Skywater 130 cell library" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n${ENDC}" +section_header "Installing/Updating OSU Skywater 130 cell library" STATUS="OSU Skywater 130 cell library" mkdir -p "$RISCV"/cad/lib cd "$RISCV"/cad/lib @@ -413,11 +370,7 @@ fi # Download site-setup scripts # The site-setup script is used to set up the environment for the RISC-V tools and EDA tools by setting # the PATH and other environment variables. It also sources the Python virtual environment. -echo -e "${SECTION_COLOR}\n*************************************************************************" -echo -e "*************************************************************************" -echo -e "Downloading Site Setup Script" -echo -e "*************************************************************************" -echo -e "*************************************************************************\n${ENDC}" +section_header "Downloading Site Setup Script" STATUS="site-setup scripts" cd "$RISCV" if [ ! -e "${RISCV}"/site-setup.sh ]; then From 467436e30cca33ca044919d70faac3078f10bc6a Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 15 Jul 2024 05:32:16 -0700 Subject: [PATCH 052/219] Renamed --coverage to --ccov and moved UCDB files to questa/ucdb --- Makefile | 8 +++++--- bin/regression-wally | 20 ++++++++++---------- bin/wsim | 12 ++++++------ sim/Makefile | 43 +++++++++++++++++++++---------------------- sim/questa/wally.do | 22 +++++++++++++--------- 5 files changed, 55 insertions(+), 50 deletions(-) diff --git a/Makefile b/Makefile index 740287dcc..050f066fa 100644 --- a/Makefile +++ b/Makefile @@ -91,9 +91,11 @@ combine_functcov: mkdir -p ${SIM}/questa/functcov mkdir -p ${SIM}/questa/functcov_logs cd ${SIM}/questa/functcov && rm -rf * - run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/functcov/add.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-add.elf >> ${SIM}/questa/functcov_logs/add.log 2>&1 - run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/functcov/and.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-and.elf >> ${SIM}/questa/functcov_logs/add.log 2>&1 - run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/functcov/ori.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-ori.elf >> ${SIM}/questa/functcov_logs/add.log 2>&1 + wsim rv64gc ${WALLY}/tests/functcov/rv64/I/WALLY-COV-add.elf > ${SIM}/questa/functcov_logs/add.log 2>&1 + + #run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/functcov/add.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-add.elf >> ${SIM}/questa/functcov_logs/add.log 2>&1 + #run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/functcov/and.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-and.elf >> ${SIM}/questa/functcov_logs/add.log 2>&1 + #run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/functcov/ori.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-ori.elf >> ${SIM}/questa/functcov_logs/add.log 2>&1 vcover merge ${SIM}/questa/functcov/functcov.ucdb ${SIM}/questa/functcov/*.ucdb ${SIM}/questa/functcov_ucdbs/* -suppress 6854 -64 # vcover merge ${SIM}/questa/functcov/functcov.ucdb ${SIM}/questa/functcov_ucdbs/* -suppress 6854 -64 diff --git a/bin/regression-wally b/bin/regression-wally index 8225968aa..a059bf648 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -320,7 +320,7 @@ coveragesim = "questa" # Questa is required for code/functional coverage #defaultsim = "questa" # Default simulator for all other tests; change to Verilator when flow is ready defaultsim = "verilator" # Default simulator for all other tests -coverage = '--coverage' in sys.argv +ccov = '--ccov' in sys.argv fp = '--fp' in sys.argv nightly = '--nightly' in sys.argv testfloat = '--testfloat' in sys.argv @@ -334,8 +334,8 @@ else: nightMode = "" sims = [defaultsim] -if (coverage): # only run RV64GC tests in coverage mode - coverStr = '--coverage' +if (ccov): # only run RV64GC tests in coverage mode + coverStr = '--ccov' else: coverStr = '' @@ -357,7 +357,7 @@ if (buildroot): # addTests(tests_buildrootboot, defaultsim) # non-lockstep with Verilator runs in about 2 hours addTests(tests_buildrootbootlockstep, "questa") # lockstep with Questa and ImperasDV runs overnight -if (coverage): # only run RV64GC tests on Questa in coverage mode +if (ccov): # only run RV64GC tests on Questa in code coverage mode addTests(tests64gc_nofp, "questa") if (fp): addTests(tests64gc_fp, "questa") @@ -385,7 +385,7 @@ if (nightly): tc = TestCase( name="lockstep_wally-riscv-arch-test", variant="rv64gc", - cmd="iterelf " + WALLY + "/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege > " + sim_log, + cmd="iterelf " + WALLY + "/tests/riscof/work/wally-riscv-arch-test/rv64i_m > " + sim_log, grepstr="SUCCESS! All tests ran without failures", grepfile = sim_log) configs.append(tc) @@ -393,7 +393,7 @@ if (nightly): # testfloat tests if (testfloat): # for testfloat alone, just run testfloat tests configs = [] -if (testfloat or nightly): # for nightly, run testfloat along with othres +if (testfloat or nightly): # for nightly, run testfloat along with others testfloatsim = "questa" # change to Verilator when Issue #707 about testfloat not running Verilator is resolved testfloatconfigs = ["fdqh_ieee_rv64gc", "fdq_ieee_rv64gc", "fdh_ieee_rv64gc", "fd_ieee_rv64gc", "fh_ieee_rv64gc", "f_ieee_rv64gc", "fdqh_ieee_rv32gc", "f_ieee_rv32gc"] for config in testfloatconfigs: @@ -458,7 +458,7 @@ if (testfloat or nightly): # for nightly, run testfloat along with othres def main(): """Run the tests and count the failures""" - global configs, coverage + global configs, ccov os.chdir(regressionDir) dirs = ["questa/logs", "questa/wkdir", "verilator/logs", "verilator/wkdir", "vcs/logs", "vcs/wkdir"] for d in dirs: @@ -472,7 +472,7 @@ def main(): os.chdir(regressionDir) os.system('./make-tests.sh | tee ./logs/make-tests.log') - elif '--coverage' in sys.argv: + elif '--ccov' in sys.argv: TIMEOUT_DUR = 20*60 # seconds os.system('rm -f questa/cov/*.ucdb') elif '--nightly' in sys.argv: @@ -497,8 +497,8 @@ def main(): print(f"{bcolors.FAIL}%s_%s: Timeout - runtime exceeded %d seconds{bcolors.ENDC}" % (config.variant, config.name, TIMEOUT_DUR)) # Coverage report - if coverage: - os.system('make QuestaCoverage') + if ccov: + os.system('make QuestaCodeCoverage') # Count the number of failures if num_fail: print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail) diff --git a/bin/wsim b/bin/wsim index 68c6ce019..f5c297067 100755 --- a/bin/wsim +++ b/bin/wsim @@ -26,8 +26,8 @@ parser.add_argument("--elf", "-e", help="ELF File name; use if name does not end parser.add_argument("--sim", "-s", help="Simulator", choices=["questa", "verilator", "vcs"], default="questa") parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench") parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true") -parser.add_argument("--coverage", "-c", help="Code & Functional Coverage", action="store_true") -parser.add_argument("--fcov", "-f", help="Code & Functional Coverage", action="store_true") +parser.add_argument("--ccov", "-c", help="Code Coverage", action="store_true") +parser.add_argument("--fcov", "-f", help="Functional Coverage", action="store_true") parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="") parser.add_argument("--vcd", "-v", help="Generate testbench.vcd", action="store_true") parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true") @@ -55,7 +55,7 @@ if(args.testsuite.endswith('.elf') and args.elf == ""): # No --elf argument; che # Validate arguments -if (args.gui or args.coverage or args.fcov or args.lockstep): +if (args.gui or args.ccov or args.fcov or args.lockstep): if args.sim not in ["questa", "vcs"]: print("Option only supported for Questa and VCS") exit(1) @@ -86,14 +86,14 @@ else: flags = suffix + " " + ImperasPlusArgs # other flags -if (args.coverage): - flags += " --coverage" +if (args.ccov): + flags += " --ccov" if (args.fcov): flags += " --fcov" # create the output sub-directories. regressionDir = WALLY + '/sim/' -for d in ["logs", "wkdir", "cov"]: +for d in ["logs", "wkdir", "cov", "ucdb"]: try: os.mkdir(regressionDir+args.sim+"/"+d) except: diff --git a/sim/Makefile b/sim/Makefile index 09d417124..e8fe3c860 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -17,28 +17,27 @@ all: riscoftests memfiles coveragetests deriv wally-riscv-arch-test: wallyriscoftests memfiles -QuestaCoverage: questa/cov/rv64gc_arch64i.ucdb - #iter-elf.bash --cover --search ../tests/coverage - vcover merge -out questa/cov/cov.ucdb questa/cov/rv64gc_arch64i.ucdb questa/cov/rv64gc*.ucdb -logfile questa/cov/log -# vcover merge -out questa/cov/cov.ucdb questa/cov/rv64gc_arch64i.ucdb questa/cov/rv64gc*.ucdb questa/cov/buildroot_buildroot.ucdb riscv.ucdb -logfile questa/cov/log - vcover report -details questa/cov/cov.ucdb > questa/cov/rv64gc_coverage_details.rpt - vcover report questa/cov/cov.ucdb -details -instance=/core/ebu. > questa/cov/rv64gc_coverage_ebu.rpt - vcover report questa/cov/cov.ucdb -details -instance=/core/priv. > questa/cov/rv64gc_coverage_priv.rpt - vcover report questa/cov/cov.ucdb -details -instance=/core/ifu. > questa/cov/rv64gc_coverage_ifu.rpt - vcover report questa/cov/cov.ucdb -details -instance=/core/lsu. > questa/cov/rv64gc_coverage_lsu.rpt - vcover report questa/cov/cov.ucdb -details -instance=/core/fpu. > questa/cov/rv64gc_coverage_fpu.rpt - vcover report questa/cov/cov.ucdb -details -instance=/core/ieu. > questa/cov/rv64gc_coverage_ieu.rpt - vcover report questa/cov/cov.ucdb -below 100 -details -instance=/core/ebu. > questa/cov/rv64gc_uncovered_ebu.rpt - vcover report questa/cov/cov.ucdb -below 100 -details -instance=/core/priv. > questa/cov/rv64gc_uncovered_priv.rpt - vcover report questa/cov/cov.ucdb -below 100 -details -instance=/core/ifu. > questa/cov/rv64gc_uncovered_ifu.rpt - vcover report questa/cov/cov.ucdb -below 100 -details -instance=/core/lsu. > questa/cov/rv64gc_uncovered_lsu.rpt - vcover report questa/cov/cov.ucdb -below 100 -details -instance=/core/fpu. > questa/cov/rv64gc_uncovered_fpu.rpt - vcover report questa/cov/cov.ucdb -below 100 -details -instance=/core/ieu. > questa/cov/rv64gc_uncovered_ieu.rpt - vcover report -hierarchical questa/cov/cov.ucdb > questa/cov/rv64gc_coverage_hierarchical.rpt - vcover report -below 100 -hierarchical questa/cov/cov.ucdb > questa/cov/rv64gc_uncovered_hierarchical.rpt -# vcover report -below 100 questa/cov/cov.ucdb > questa/cov/rv64gc_coverage.rpt -# vcover report -recursive questa/cov/cov.ucdb > questa/cov/rv64gc_recursive.rpt - vcover report -details -threshH 100 -html questa/cov/cov.ucdb +QuestaCodeCoverage: questa/ucdb/rv64gc_arch64i.ucdb + vcover merge -out questa/ucdb/cov.ucdb questa/ucdb/rv64gc_arch64i.ucdb questa/ucdb/rv64gc*.ucdb -logfile questa/cov/log +# vcover merge -out questa/ucdb/cov.ucdb questa/ucdb/rv64gc_arch64i.ucdb questa/ucdb/rv64gc*.ucdb questa/ucdb/buildroot_buildroot.ucdb riscv.ucdb -logfile questa/cov/log + vcover report -details questa/ucdb/cov.ucdb > questa/cov/rv64gc_coverage_details.rpt + vcover report questa/ucdb/cov.ucdb -details -instance=/core/ebu. > questa/cov/rv64gc_coverage_ebu.rpt + vcover report questa/ucdb/cov.ucdb -details -instance=/core/priv. > questa/cov/rv64gc_coverage_priv.rpt + vcover report questa/ucdb/cov.ucdb -details -instance=/core/ifu. > questa/cov/rv64gc_coverage_ifu.rpt + vcover report questa/ucdb/cov.ucdb -details -instance=/core/lsu. > questa/cov/rv64gc_coverage_lsu.rpt + vcover report questa/ucdb/cov.ucdb -details -instance=/core/fpu. > questa/cov/rv64gc_coverage_fpu.rpt + vcover report questa/ucdb/cov.ucdb -details -instance=/core/ieu. > questa/cov/rv64gc_coverage_ieu.rpt + vcover report questa/ucdb/cov.ucdb -below 100 -details -instance=/core/ebu. > questa/cov/rv64gc_uncovered_ebu.rpt + vcover report questa/ucdb/cov.ucdb -below 100 -details -instance=/core/priv. > questa/cov/rv64gc_uncovered_priv.rpt + vcover report questa/ucdb/cov.ucdb -below 100 -details -instance=/core/ifu. > questa/cov/rv64gc_uncovered_ifu.rpt + vcover report questa/ucdb/cov.ucdb -below 100 -details -instance=/core/lsu. > questa/cov/rv64gc_uncovered_lsu.rpt + vcover report questa/ucdb/cov.ucdb -below 100 -details -instance=/core/fpu. > questa/cov/rv64gc_uncovered_fpu.rpt + vcover report questa/ucdb/cov.ucdb -below 100 -details -instance=/core/ieu. > questa/cov/rv64gc_uncovered_ieu.rpt + vcover report -hierarchical questa/ucdb/cov.ucdb > questa/cov/rv64gc_coverage_hierarchical.rpt + vcover report -below 100 -hierarchical questa/ucdb/cov.ucdb > questa/cov/rv64gc_uncovered_hierarchical.rpt +# vcover report -below 100 questa/ucdb/cov.ucdb > questa/cov/rv64gc_coverage.rpt +# vcover report -recursive questa/ucdb/cov.ucdb > questa/cov/rv64gc_recursive.rpt + vcover report -details -threshH 100 -html questa/ucdb/cov.ucdb allclean: clean all diff --git a/sim/questa/wally.do b/sim/questa/wally.do index a0e6fdbb6..c3dbc3b0f 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -8,7 +8,7 @@ # # Takes 1:10 to run RV64IC tests using gui -# Usage: do wally-batch.do [-coverage] [+acc] [any number of +value] [any number of -G VAR=VAL] +# Usage: do wally-batch.do [--ccov] [--fcov] [+acc] [any number of +value] [any number of -G VAR=VAL] # Example: do wally-batch.do rv64gc arch64i testbench # Use this wally-batch.do file to run this example. @@ -40,7 +40,7 @@ vlib ${WKDIR} # Create directory for coverage data mkdir -p cov -set coverage 0 +set ccov 0 set CoverageVoptArg "" set CoverageVsimArg "" @@ -104,9 +104,9 @@ if {$AccIndex >= 0} { } # if +coverage found set flag and remove from list -set CoverageIndex [lsearch -exact $lst "--coverage"] +set CoverageIndex [lsearch -exact $lst "--ccov"] if {$CoverageIndex >= 0} { - set coverage 1 + set ccov 1 set CoverageVoptArg "+cover=sbecf" set CoverageVsimArg "-coverage" set lst [lreplace $lst $CoverageIndex $CoverageIndex] @@ -166,7 +166,7 @@ foreach otherArg $lst { if {$DEBUG > 0} { echo "GUI = $GUI" - echo "coverage = $coverage" + echo "ccov = $ccov" echo "lockstep = $lockstep" echo "FunctCoverage = $FunctCoverage" echo "remaining list = $lst" @@ -215,14 +215,18 @@ if { ${GUI} } { } } +if {$ccov || $FunctCoverage} { + set UCDB ${WALLY}/sim/questa/ucdb/${CFG}_${TESTSUITE}.ucdb + echo "Saving coverage to ${UCDB}" + coverage save -instance /testbench/dut/core ${UCDB} +} + run -all # power off -r /dut/core/* -if {$coverage || $FunctCoverage} { - set UCDB ${WALLY}/sim/questa/cov/${CFG}_${TESTSUITE}.ucdb - echo "Saving coverage to ${UCDB}" +# Code coverage exclusions +if {$ccov} { do coverage-exclusions-rv64gc.do # beware: this assumes testing the rv64gc configuration - coverage save -instance /testbench/dut/core ${UCDB} } # These aren't doing anything helpful From 3ce92ab0a59210092109d4fed1c024ccaabb0069 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 15 Jul 2024 05:34:50 -0700 Subject: [PATCH 053/219] Ignoring more sim files --- .gitignore | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.gitignore b/.gitignore index 3eba7966b..74bfca985 100644 --- a/.gitignore +++ b/.gitignore @@ -196,10 +196,12 @@ sim/questa/cov sim/questa/covhtmlreport/ sim/questa/logs sim/questa/wkdir +sim/questa/ucdb sim/verilator/logs sim/verilator/wkdir sim/vcs/logs sim/vcs/wkdir +sim/vcs/ucdb benchmarks/coremark/coremark_results.csv fpga/zsbl/OBJ/* fpga/zsbl/bin/* From c3267e8fa4f9eea9677022c453b34cef811e3123 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 15 Jul 2024 05:46:35 -0700 Subject: [PATCH 054/219] Fixed .gitignore --- .gitignore | 2 +- Makefile | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitignore b/.gitignore index 74bfca985..90864dc0f 100644 --- a/.gitignore +++ b/.gitignore @@ -193,7 +193,7 @@ config/deriv docs/docker/buildroot-config-src docs/docker/testvector-generation sim/questa/cov -sim/questa/covhtmlreport/ +sim/covhtmlreport/ sim/questa/logs sim/questa/wkdir sim/questa/ucdb diff --git a/Makefile b/Makefile index 050f066fa..2431614d1 100644 --- a/Makefile +++ b/Makefile @@ -107,7 +107,7 @@ combine_functcov: grep "Total Coverage By Instance" ${SIM}/questa/functcov/functcov.ucdb.log remove_functcov_artifacts: - rm ${SIM}/questa/riscv.ucdb ${SIM}/questa/functcov.log covhtmlreport/ ${SIM}/questa/functcov_logs/ ${SIM}/questa/functcov_ucdbs/ ${SIM}/questa/functcov/ -rf + rm ${SIM}/questa/riscv.ucdb ${SIM}/questa/functcov.log ${SIM}/questa/covhtmlreport/ ${SIM}/questa/functcov_logs/ ${SIM}/questa/functcov_ucdbs/ ${SIM}/questa/functcov/ -rf collect_functcov: remove_functcov_artifacts riscvdv_functcov combine_functcov From ff15671878735ca32333da3023d7650e48e3ddfe Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 15 Jul 2024 14:19:37 -0700 Subject: [PATCH 055/219] Ignore functional coverage outputs --- .gitignore | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.gitignore b/.gitignore index 90864dc0f..0d8423d82 100644 --- a/.gitignore +++ b/.gitignore @@ -197,6 +197,9 @@ sim/covhtmlreport/ sim/questa/logs sim/questa/wkdir sim/questa/ucdb +sim/questa/fcov +sim/questa/fcov_logs +sim/questa/fcov_ucdb sim/verilator/logs sim/verilator/wkdir sim/vcs/logs From ac05fa55537232d509cdc07f49f7e0c35b56d217 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 15 Jul 2024 14:20:48 -0700 Subject: [PATCH 056/219] Attempt at functional coverage; breaks code and functional coverage --- Makefile | 86 --------------------------------------- bin/wsim | 2 +- sim/Makefile | 98 ++++++++++++++++++++++++++++++++++++++------- sim/questa/wally.do | 20 ++++++--- 4 files changed, 99 insertions(+), 107 deletions(-) diff --git a/Makefile b/Makefile index 2431614d1..b0f01c49c 100644 --- a/Makefile +++ b/Makefile @@ -25,92 +25,6 @@ verify: cd ${SIM}/sim; ./sim-testfloat-batch all make imperasdv -imperasdv: - iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m - iter-elf.bash --search ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m - -imperasdv_cov: - touch ${SIM}/seed0.txt - echo "0" > ${SIM}/seed0.txt -# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --verbose --seed 0 --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m -# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${SIM}/seed0.txt --coverdb ${SIM}/cov/rv64gc_arch64i.ucdb --verbose -# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${SIM}/seed0.txt --coverdb ${SIM}/questa/riscv.ucdb --verbose - run-elf-cov.bash --elf ${WALLY}/tests/riscvdv/asm_test/riscv_arithmetic_basic_test_0.elf --seed ${SIM}/questa/seed0.txt --coverdb ${SIM}/questa/riscv.ucdb --verbose - vcover report -details -html ${SIM}/questa/riscv.ucdb - -funcovreg: - #iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m --cover - #iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/I --cover - #iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege --cover - #iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/Q --cover - rm -f ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/*/src/*/dut/my.elf - iter-elf.bash --search ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I --cover - vcover report -details -html ${SIM}/questa/riscv.ucdb - - - -# test_name=riscv_arithmetic_basic_test -riscvdv: - python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gen,gcc_compile >> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1 -# python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gcc_compile >> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1 -# python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps iss_sim >> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1 -# run-elf.bash --seed ${SIM}/questa/seed0.txt --verbose --elf ${WALLY}/tests/riscvdv/asm_test/${test_name}_0.o >> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1 - #run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/riscv.ucdb --elf ${WALLY}/tests/riscvdv/asm_test/${test_name}_0.o >> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1 - #cp ${SIM}/questa/riscv.ucdb ${SIM}/questa/functcov_ucdbs/${test_name}.ucdb - -riscvdv_functcov: - mkdir -p ${SIM}/questa/functcov_logs - mkdir -p ${SIM}/questa/functcov_ucdbs - cd ${SIM}/questa/functcov_logs && rm -rf * - cd ${SIM}/questa/functcov_ucdbs && rm -rf * - make riscvdv test_name=riscv_arithmetic_basic_test >> ${SIM}/questa/functcov.log 2>&1 - make riscvdv test_name=riscv_amo_test >> ${SIM}/questa/functcov.log 2>&1 - make riscvdv test_name=riscv_ebreak_debug_mode_test >> ${SIM}/questa/functcov.log 2>&1 - make riscvdv test_name=riscv_ebreak_test >> ${SIM}/questa/functcov.log 2>&1 - make riscvdv test_name=riscv_floating_point_arithmetic_test >> ${SIM}/questa/functcov.log 2>&1 - make riscvdv test_name=riscv_floating_point_mmu_stress_test >> ${SIM}/questa/functcov.log 2>&1 - make riscvdv test_name=riscv_floating_point_rand_test >> ${SIM}/questa/functcov.log 2>&1 - make riscvdv test_name=riscv_full_interrupt_test >> ${SIM}/questa/functcov.log 2>&1 - make riscvdv test_name=riscv_hint_instr_test >> ${SIM}/questa/functcov.log 2>&1 - make riscvdv test_name=riscv_illegal_instr_test >> ${SIM}/questa/functcov.log 2>&1 - make riscvdv test_name=riscv_invalid_csr_test >> ${SIM}/questa/functcov.log 2>&1 - make riscvdv test_name=riscv_jump_stress_test >> ${SIM}/questa/functcov.log 2>&1 - make riscvdv test_name=riscv_loop_test >> ${SIM}/questa/functcov.log 2>&1 - make riscvdv test_name=riscv_machine_mode_rand_test >> ${SIM}/questa/functcov.log 2>&1 - make riscvdv test_name=riscv_mmu_stress_test >> ${SIM}/questa/functcov.log 2>&1 - make riscvdv test_name=riscv_no_fence_test >> ${SIM}/questa/functcov.log 2>&1 - make riscvdv test_name=riscv_non_compressed_instr_test >> ${SIM}/questa/functcov.log 2>&1 - make riscvdv test_name=riscv_pmp_test >> ${SIM}/questa/functcov.log 2>&1 - make riscvdv test_name=riscv_privileged_mode_rand_test >> ${SIM}/questa/functcov.log 2>&1 - make riscvdv test_name=riscv_rand_instr_test >> ${SIM}/questa/functcov.log 2>&1 - make riscvdv test_name=riscv_rand_jump_test >> ${SIM}/questa/functcov.log 2>&1 - make riscvdv test_name=riscv_sfence_exception_test >> ${SIM}/questa/functcov.log 2>&1 - make riscvdv test_name=riscv_unaligned_load_store_test >> ${SIM}/questa/functcov.log 2>&1 - -combine_functcov: - mkdir -p ${SIM}/questa/functcov - mkdir -p ${SIM}/questa/functcov_logs - cd ${SIM}/questa/functcov && rm -rf * - wsim rv64gc ${WALLY}/tests/functcov/rv64/I/WALLY-COV-add.elf > ${SIM}/questa/functcov_logs/add.log 2>&1 - - #run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/functcov/add.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-add.elf >> ${SIM}/questa/functcov_logs/add.log 2>&1 - #run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/functcov/and.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-and.elf >> ${SIM}/questa/functcov_logs/add.log 2>&1 - #run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/functcov/ori.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-ori.elf >> ${SIM}/questa/functcov_logs/add.log 2>&1 - - vcover merge ${SIM}/questa/functcov/functcov.ucdb ${SIM}/questa/functcov/*.ucdb ${SIM}/questa/functcov_ucdbs/* -suppress 6854 -64 - # vcover merge ${SIM}/questa/functcov/functcov.ucdb ${SIM}/questa/functcov_ucdbs/* -suppress 6854 -64 - vcover report -details -html ${SIM}/questa/functcov/functcov.ucdb - vcover report ${SIM}/questa/functcov/functcov.ucdb -details -cvg > ${SIM}/questa/functcov/functcov.log - vcover report ${SIM}/questa/functcov/functcov.ucdb -testdetails -cvg > ${SIM}/questa/functcov/functcov.testdetails.log -# vcover report ${SIM}/questa/functcov/functcov.ucdb -details -cvg -below 100 | egrep "Coverpoint|Covergroup|Cross" | grep -v Metric > ${SIM}/questa/functcov/functcov.ucdb.summary.log - vcover report ${SIM}/questa/functcov/functcov.ucdb -details -cvg | egrep "Coverpoint|Covergroup|Cross|TYPE" > ${SIM}/questa/functcov/functcov.summary.log - grep "Total Coverage By Instance" ${SIM}/questa/functcov/functcov.ucdb.log - -remove_functcov_artifacts: - rm ${SIM}/questa/riscv.ucdb ${SIM}/questa/functcov.log ${SIM}/questa/covhtmlreport/ ${SIM}/questa/functcov_logs/ ${SIM}/questa/functcov_ucdbs/ ${SIM}/questa/functcov/ -rf - -collect_functcov: remove_functcov_artifacts riscvdv_functcov combine_functcov - benchmarks: make coremark make embench diff --git a/bin/wsim b/bin/wsim index f5c297067..8d9ba3167 100755 --- a/bin/wsim +++ b/bin/wsim @@ -93,7 +93,7 @@ if (args.fcov): # create the output sub-directories. regressionDir = WALLY + '/sim/' -for d in ["logs", "wkdir", "cov", "ucdb"]: +for d in ["logs", "wkdir", "cov", "ucdb", "fcov", "fcov_ucdb"]: try: os.mkdir(regressionDir+args.sim+"/"+d) except: diff --git a/sim/Makefile b/sim/Makefile index e8fe3c860..9ce1b5c49 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -1,19 +1,10 @@ +# David_Harris@hmc.edu 15 July 2024 +# Simulation Makefile for CORE-V-Wally +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +SIM = ${WALLY}/sim all: riscoftests memfiles coveragetests deriv - # *** Build old tests/imperas-riscv-tests for now; - # Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test - # DH: 2/27/22 temporarily commented out imperas-riscv-tests because license expired - #make -C ../tests/imperas-riscv-tests --jobs - #make -C ../tests/imperas-riscv-tests XLEN=64 --jobs - # Only compile Imperas tests if they are installed locally. - # They are usually a symlink to $RISCV/imperas-riscv-tests and only - # get compiled there manually during installation - #make -C ../addins/imperas-riscv-tests - #make -C ../addins/imperas-riscv-tests XLEN=64 - #cd ../addins/imperas-riscv-tests; elf2hex.sh - #cd ../addins/imperas-riscv-tests; extractFunctionRadix.sh work/*/*/*.elf.objdump - # Link Linux test vectors - #cd ../tests/linux-testgen/linux-testvectors/;./tvLinker.sh wally-riscv-arch-test: wallyriscoftests memfiles @@ -39,6 +30,85 @@ QuestaCodeCoverage: questa/ucdb/rv64gc_arch64i.ucdb # vcover report -recursive questa/ucdb/cov.ucdb > questa/cov/rv64gc_recursive.rpt vcover report -details -threshH 100 -html questa/ucdb/cov.ucdb + +imperasdv_cov: + touch ${SIM}/seed0.txt + echo "0" > ${SIM}/seed0.txt +# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --verbose --seed 0 --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m +# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${SIM}/seed0.txt --coverdb ${SIM}/cov/rv64gc_arch64i.ucdb --verbose +# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${SIM}/seed0.txt --coverdb ${SIM}/questa/riscv.ucdb --verbose + run-elf-cov.bash --elf ${WALLY}/tests/riscvdv/asm_test/riscv_arithmetic_basic_test_0.elf --seed ${SIM}/questa/seed0.txt --coverdb ${SIM}/questa/riscv.ucdb --verbose + vcover report -details -html ${SIM}/questa/riscv.ucdb + +funcovreg: + #iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m --cover + #iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/I --cover + #iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege --cover + #iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/Q --cover + rm -f ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/*/src/*/dut/my.elf + iter-elf.bash --search ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I --cover + vcover report -details -html ${SIM}/questa/riscv.ucdb + + +riscvdv: + python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gen,gcc_compile >> ${SIM}/questa/fcov_logs/${test_name}.log 2>&1 +# python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gcc_compile >> ${SIM}/questa/fcov_logs/${test_name}.log 2>&1 +# python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps iss_sim >> ${SIM}/questa/fcov_logs/${test_name}.log 2>&1 +# run-elf.bash --seed ${SIM}/questa/seed0.txt --verbose --elf ${WALLY}/tests/riscvdv/asm_test/${test_name}_0.o >> ${SIM}/questa/fcov_logs/${test_name}.log 2>&1 + +riscvdv_functcov: + mkdir -p ${SIM}/questa/fcov_logs + mkdir -p ${SIM}/questa/fcov_ucdbs + cd ${SIM}/questa/fcov_logs && rm -rf * + cd ${SIM}/questa/fcov_ucdbs && rm -rf * + make riscvdv test_name=riscv_arithmetic_basic_test >> ${SIM}/questa/fcov.log 2>&1 + make riscvdv test_name=riscv_amo_test >> ${SIM}/questa/fcov.log 2>&1 + make riscvdv test_name=riscv_ebreak_debug_mode_test >> ${SIM}/questa/fcov.log 2>&1 + make riscvdv test_name=riscv_ebreak_test >> ${SIM}/questa/fcov.log 2>&1 + make riscvdv test_name=riscv_floating_point_arithmetic_test >> ${SIM}/questa/fcov.log 2>&1 + make riscvdv test_name=riscv_floating_point_mmu_stress_test >> ${SIM}/questa/fcov.log 2>&1 + make riscvdv test_name=riscv_floating_point_rand_test >> ${SIM}/questa/fcov.log 2>&1 + make riscvdv test_name=riscv_full_interrupt_test >> ${SIM}/questa/fcov.log 2>&1 + make riscvdv test_name=riscv_hint_instr_test >> ${SIM}/questa/fcov.log 2>&1 + make riscvdv test_name=riscv_illegal_instr_test >> ${SIM}/questa/fcov.log 2>&1 + make riscvdv test_name=riscv_invalid_csr_test >> ${SIM}/questa/fcov.log 2>&1 + make riscvdv test_name=riscv_jump_stress_test >> ${SIM}/questa/fcov.log 2>&1 + make riscvdv test_name=riscv_loop_test >> ${SIM}/questa/fcov.log 2>&1 + make riscvdv test_name=riscv_machine_mode_rand_test >> ${SIM}/questa/fcov.log 2>&1 + make riscvdv test_name=riscv_mmu_stress_test >> ${SIM}/questa/fcov.log 2>&1 + make riscvdv test_name=riscv_no_fence_test >> ${SIM}/questa/fcov.log 2>&1 + make riscvdv test_name=riscv_non_compressed_instr_test >> ${SIM}/questa/fcov.log 2>&1 + make riscvdv test_name=riscv_pmp_test >> ${SIM}/questa/fcov.log 2>&1 + make riscvdv test_name=riscv_privileged_mode_rand_test >> ${SIM}/questa/fcov.log 2>&1 + make riscvdv test_name=riscv_rand_instr_test >> ${SIM}/questa/fcov.log 2>&1 + make riscvdv test_name=riscv_rand_jump_test >> ${SIM}/questa/fcov.log 2>&1 + make riscvdv test_name=riscv_sfence_exception_test >> ${SIM}/questa/fcov.log 2>&1 + make riscvdv test_name=riscv_unaligned_load_store_test >> ${SIM}/questa/fcov.log 2>&1 + +combine_functcov: + mkdir -p ${SIM}/questa/fcov + mkdir -p ${SIM}/questa/fcov_logs + cd ${SIM}/questa/fcov && rm -rf * + wsim rv64gc ${WALLY}/tests/functcov/rv64/I/WALLY-COV-add.elf --fcov > ${SIM}/questa/fcov_logs/add.log 2>&1 + + #run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/fcov/add.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-add.elf >> ${SIM}/questa/fcov_logs/add.log 2>&1 + #run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/fcov/and.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-and.elf >> ${SIM}/questa/fcov_logs/add.log 2>&1 + #run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/fcov/ori.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-ori.elf >> ${SIM}/questa/fcov_logs/add.log 2>&1 + + vcover merge ${SIM}/questa/fcov_ucdb/fcov.ucdb ${SIM}/questa/fcov_ucdb/*.ucdb ${SIM}/questa/fcov_ucdb/* -suppress 6854 -64 + # vcover merge ${SIM}/questa/fcov/fcov.ucdb ${SIM}/questa/fcov_ucdbs/* -suppress 6854 -64 + vcover report -details -html ${SIM}/questa/fcov_ucdb/fcov.ucdb + vcover report ${SIM}/questa/fcov_ucdb/fcov.ucdb -details -cvg > ${SIM}/questa/fcov/fcov.log + vcover report ${SIM}/questa/fcov_ucdb/fcov.ucdb -testdetails -cvg > ${SIM}/questa/fcov/fcov.testdetails.log +# vcover report ${SIM}/questa/fcov/fcov.ucdb -details -cvg -below 100 | egrep "Coverpoint|Covergroup|Cross" | grep -v Metric > ${SIM}/questa/fcov/fcov.ucdb.summary.log + vcover report ${SIM}/questa/fcov_ucdb/fcov.ucdb -details -cvg | egrep "Coverpoint|Covergroup|Cross|TYPE" > ${SIM}/questa/fcov/fcov.summary.log + grep "Total Coverage By Instance" ${SIM}/questa/fcov/fcov.log + +remove_functcov_artifacts: + rm ${SIM}/questa/riscv.ucdb ${SIM}/questa/fcov.log ${SIM}/questa/covhtmlreport/ ${SIM}/questa/fcov_logs/ ${SIM}/questa/fcov_ucdbs/ ${SIM}/questa/fcov/ -rf + +collect_functcov: remove_functcov_artifacts riscvdv_functcov combine_functcov + allclean: clean all clean: diff --git a/sim/questa/wally.do b/sim/questa/wally.do index c3dbc3b0f..54d6a1124 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -57,6 +57,7 @@ set FCdefineCOVER_RV64D "" set FCdefineCOVER_RV64ZICSR "" set FCdefineCOVER_RV64C "" set FCdefineIDV_INCLUDE_TRACE2COV "" +set FCTRACE2COV "" set lockstep 0 # ok this is annoying. vlog, vopt, and vsim are very picky about how arguments are passed. @@ -65,7 +66,7 @@ set lockstep 0 set lockstepvoptstring "" set SVLib "" set SVLibPath "" -#set OtherFlags "" +set OtherFlags "" set ImperasPubInc "" set ImperasPrivInc "" set rvviFiles "" @@ -129,10 +130,11 @@ if {$FunctCoverageIndex >= 0} { set FCdefineCOVER_RV64ZICSR "+define+COVER_RV64ZICSR" set FCdefineCOVER_RV64C "+define+COVER_RV64C" set FCdefineIDV_INCLUDE_TRACE2COV "+define+IDV_INCLUDE_TRACE2COV" + set FCTRACE2COV "+TRACE2COV_ENABLE=1 +VERBOSE=1" set lst [lreplace $lst $FunctCoverageIndex $FunctCoverageIndex] -} - +}\ + set LockStepIndex [lsearch -exact $lst "--lockstep"] # ugh. can't have more than 9 arguments passed to vsim. why? I'll have to remove --lockstep when running # functional coverage and imply it. @@ -148,13 +150,14 @@ if {$LockStepIndex >= 0 || $FunctCoverageIndex >= 0} { set idvFiles $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/*.sv set SVLib "-sv_lib" set SVLibPath $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model - #set OtherFlags $env(OTHERFLAGS) + #set OtherFlags $::env(OTHERFLAGS) # not working 7/15/24 dh; this should be the way to pass things like --verbose (Issue 871) if {$LockStepIndex >= 0} { set lst [lreplace $lst $LockStepIndex $LockStepIndex] } } + # separate the +args from the -G parameters foreach otherArg $lst { if {[string index $otherArg 0] eq "+"} { @@ -201,7 +204,7 @@ vopt $accFlag wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} ${ParamArgs} #vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} ${PlusArgs} -fatal 7 ${SVLib} ${SVLibPath} ${OtherFlags} +TRACE2COV_ENABLE=1 -suppress 3829 ${CoverageVsimArg} #vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} ${PlusArgs} -fatal 7 ${SVLib} ${SVLibPath} +IDV_TRACE2COV=1 +TRACE2COV_ENABLE=1 -suppress 3829 ${CoverageVsimArg} -vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} $temp0 $temp1 $temp2 $temp3 -fatal 7 ${SVLib} ${SVLibPath} -suppress 3829 ${CoverageVsimArg} +vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} $temp0 $temp1 $temp2 $temp3 -fatal 7 ${SVLib} ${SVLibPath} ${OtherFlags} ${FCTRACE2COV} -suppress 3829 ${CoverageVsimArg} # vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829 # power add generates the logging necessary for said generation. @@ -215,12 +218,17 @@ if { ${GUI} } { } } -if {$ccov || $FunctCoverage} { +if {$ccov} { set UCDB ${WALLY}/sim/questa/ucdb/${CFG}_${TESTSUITE}.ucdb echo "Saving coverage to ${UCDB}" coverage save -instance /testbench/dut/core ${UCDB} } +if {$FunctCoverage} { + set UCDB ${WALLY}/sim/questa/fcov_ucdb/${CFG}_${TESTSUITE}.ucdb + coverage save -onexit ${UCDB} +} + run -all # power off -r /dut/core/* From d86ef9673d8e2aae9f41f469e6a1773e47df74e9 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 15 Jul 2024 15:34:44 -0700 Subject: [PATCH 057/219] More attempts at functional coverage --- sim/Makefile | 4 ++-- sim/questa/wally.do | 22 +++++++++++----------- 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/sim/Makefile b/sim/Makefile index 9ce1b5c49..5635431ff 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -89,14 +89,14 @@ combine_functcov: mkdir -p ${SIM}/questa/fcov mkdir -p ${SIM}/questa/fcov_logs cd ${SIM}/questa/fcov && rm -rf * + cd ${SIM}/questa/fcov_ucdb && rm -rf * wsim rv64gc ${WALLY}/tests/functcov/rv64/I/WALLY-COV-add.elf --fcov > ${SIM}/questa/fcov_logs/add.log 2>&1 #run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/fcov/add.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-add.elf >> ${SIM}/questa/fcov_logs/add.log 2>&1 #run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/fcov/and.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-and.elf >> ${SIM}/questa/fcov_logs/add.log 2>&1 #run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/fcov/ori.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-ori.elf >> ${SIM}/questa/fcov_logs/add.log 2>&1 - vcover merge ${SIM}/questa/fcov_ucdb/fcov.ucdb ${SIM}/questa/fcov_ucdb/*.ucdb ${SIM}/questa/fcov_ucdb/* -suppress 6854 -64 - # vcover merge ${SIM}/questa/fcov/fcov.ucdb ${SIM}/questa/fcov_ucdbs/* -suppress 6854 -64 + vcover merge ${SIM}/questa/fcov_ucdb/fcov.ucdb ${SIM}/questa/fcov_ucdb/*.ucdb -suppress 6854 -64 vcover report -details -html ${SIM}/questa/fcov_ucdb/fcov.ucdb vcover report ${SIM}/questa/fcov_ucdb/fcov.ucdb -details -cvg > ${SIM}/questa/fcov/fcov.log vcover report ${SIM}/questa/fcov_ucdb/fcov.ucdb -testdetails -cvg > ${SIM}/questa/fcov/fcov.testdetails.log diff --git a/sim/questa/wally.do b/sim/questa/wally.do index 54d6a1124..156431bef 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -130,7 +130,7 @@ if {$FunctCoverageIndex >= 0} { set FCdefineCOVER_RV64ZICSR "+define+COVER_RV64ZICSR" set FCdefineCOVER_RV64C "+define+COVER_RV64C" set FCdefineIDV_INCLUDE_TRACE2COV "+define+IDV_INCLUDE_TRACE2COV" - set FCTRACE2COV "+TRACE2COV_ENABLE=1 +VERBOSE=1" + set FCTRACE2COV "+TRACE2COV_ENABLE=1" set lst [lreplace $lst $FunctCoverageIndex $FunctCoverageIndex] }\ @@ -218,24 +218,24 @@ if { ${GUI} } { } } -if {$ccov} { - set UCDB ${WALLY}/sim/questa/ucdb/${CFG}_${TESTSUITE}.ucdb - echo "Saving coverage to ${UCDB}" - coverage save -instance /testbench/dut/core ${UCDB} -} - if {$FunctCoverage} { set UCDB ${WALLY}/sim/questa/fcov_ucdb/${CFG}_${TESTSUITE}.ucdb coverage save -onexit ${UCDB} } run -all + +if {$ccov} { + set UCDB ${WALLY}/sim/questa/ucdb/${CFG}_${TESTSUITE}.ucdb + echo "Saving coverage to ${UCDB}" + do coverage-exclusions-rv64gc.do # beware: this assumes testing the rv64gc configuration + coverage save -instance /testbench/dut/core ${UCDB} +} + + # power off -r /dut/core/* -# Code coverage exclusions -if {$ccov} { - do coverage-exclusions-rv64gc.do # beware: this assumes testing the rv64gc configuration -} + # These aren't doing anything helpful #profile report -calltree -file wally-calltree.rpt -cutoff 2 From 25f271064f97ec84a171f3d55beec83cc251422b Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 16 Jul 2024 09:28:05 -0700 Subject: [PATCH 058/219] Fixed slli.uw bug reported by Lee Moore 16 July 2024 --- bin/wsim | 3 +- src/ieu/alu.sv | 6 +- src/ieu/bmu/bitmanipalu.sv | 10 +-- src/ieu/bmu/bmuctrl.sv | 173 +++++++++++++++++++------------------ src/ieu/controller.sv | 12 +-- src/ieu/datapath.sv | 4 +- src/ieu/ieu.sv | 5 +- 7 files changed, 109 insertions(+), 104 deletions(-) diff --git a/bin/wsim b/bin/wsim index 8d9ba3167..34e725707 100755 --- a/bin/wsim +++ b/bin/wsim @@ -47,7 +47,8 @@ elif (args.elf != ""): if(args.testsuite.endswith('.elf') and args.elf == ""): # No --elf argument; check if testsuite has a .elf extension and use that instead if (os.path.isfile(args.testsuite)): ElfFile = "+ElfFile=" + os.path.abspath(args.testsuite) - args.testsuite=args.testsuite.rsplit('/', 1)[1] + if ('/' in args.testsuite): + args.testsuite=args.testsuite.rsplit('/', 1)[1] # strip off path if present else: print("ELF file not found: " + args.testsuite) exit(1) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index e142de1e7..acd5b025d 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -30,7 +30,7 @@ module alu import cvw::*; #(parameter cvw_t P) ( input logic [P.XLEN-1:0] A, B, // Operands - input logic W64, // W64-type instruction + input logic W64, UW64, // W64/.uw-type instruction input logic SubArith, // Subtraction or arithmetic shift input logic [2:0] ALUSelect, // ALU mux select signal input logic [3:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction @@ -77,7 +77,7 @@ module alu import cvw::*; #(parameter cvw_t P) ( end else assign ZeroCondMaskInvB = CondMaskInvB; // no masking if Zicond is not supported // Shifts (configurable for rotation) - shifter #(P) sh(.A, .Amt(B[P.LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .SubArith, .Y(Shift), .Rotate(BALUControl[2])); + shifter #(P) sh(.A(CondShiftA), .Amt(B[P.LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .SubArith, .Y(Shift), .Rotate(BALUControl[2])); // Condition code flags are based on subtraction output Sum = A-B. // Overflow occurs when the numbers being subtracted have the opposite sign @@ -113,7 +113,7 @@ module alu import cvw::*; #(parameter cvw_t P) ( P.ZBKB_SUPPORTED | P.ZBKC_SUPPORTED | P.ZBKX_SUPPORTED | P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED | P.ZKNH_SUPPORTED) begin : bitmanipalu bitmanipalu #(P) balu( - .A, .B, .W64, .BSelect, .ZBBSelect, .BMUActive, + .A, .B, .W64, .UW64, .BSelect, .ZBBSelect, .BMUActive, .Funct3, .Funct7, .Rs2E, .LT,.LTU, .BALUControl, .PreALUResult, .FullResult, .CondMaskB, .CondShiftA, .ALUResult); end else begin diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index 4caee782a..9bb0905ad 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -30,16 +30,16 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) ( input logic [P.XLEN-1:0] A, B, // Operands - input logic W64, // W64-type instruction + input logic W64, UW64, // W64/.uw-type instruction input logic [3:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction input logic [3:0] ZBBSelect, // ZBB mux select signal input logic [2:0] Funct3, // Funct3 field of opcode indicates operation to perform input logic [6:0] Funct7, // Funct7 field for ZKND and ZKNE operations input logic [4:0] Rs2E, // Register source2 for RNUM of ZKNE/ZKND - input logic LT, // less than flag - input logic LTU, // less than unsigned flag + input logic LT, // less than flag + input logic LTU, // less than unsigned flag input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage - input logic BMUActive, // Bit manipulation instruction being executed + input logic BMUActive, // Bit manipulation instruction being executed input logic [P.XLEN-1:0] PreALUResult, // PreALUResult signals input logic [P.XLEN-1:0] FullResult, // FullResult signals output logic [P.XLEN-1:0] CondMaskB, // B is conditionally masked for ZBS instructions @@ -76,7 +76,7 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) ( // 0-3 bit Pre-Shift Mux if (P.ZBA_SUPPORTED) begin: zbapreshift if (P.XLEN == 64) begin - mux2 #(64) zextmux(A, {{32{1'b0}}, A[31:0]}, W64, CondZextA); + mux2 #(64) zextmux(A, {{32{1'b0}}, A[31:0]}, UW64, CondZextA); end else assign CondZextA = A; assign PreShiftAmt = Funct3[2:1] & {2{PreShift}}; assign CondShiftA = CondZextA << (PreShiftAmt); diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index fb4e603c0..d482616ef 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -36,6 +36,7 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( output logic BRegWriteD, // Indicates if it is a R type B instruction in Decode Stage output logic BALUSrcBD, // Indicates if it is an I/IW (non auipc) type B instruction in Decode Stage output logic BW64D, // Indiciates if it is a W type B instruction in Decode Stage + output logic BUW64D, // Indiciates if it is a .uw type B instruction in Decode Stage output logic BSubArithD, // TRUE if ext, clr, andn, orn, xnor instruction in Decode Stage output logic IllegalBitmanipInstrD, // Indicates if it is unrecognized B instruction in Decode Stage // Execute stage control signals @@ -60,7 +61,7 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( logic [3:0] BSelectD; // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage logic [3:0] ZBBSelectD; // ZBB mux select signal in Decode stage - `define BMUCTRLW 20 + `define BMUCTRLW 21 logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals @@ -72,209 +73,209 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( // Main Instruction Decoder always_comb begin - // BALUSelect_BSelect_ZBBSelect_BRegWrite_BALUSrcB_BW64_BALUOp_BSubArithD_RotateD_MaskD_PreShiftD_IllegalBitmanipInstrD + // BALUSelect_BSelect_ZBBSelect_BRegWrite_BALUSrcB_BW64_BUW64_BALUOp_BSubArithD_RotateD_MaskD_PreShiftD_IllegalBitmanipInstrD BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // default: Illegal bmu instruction; if (P.ZBA_SUPPORTED) begin casez({OpD, Funct7D, Funct3D}) - 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_0_1_0_0_0_1_0; // sh1add - 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_0_1_0_0_0_1_0; // sh2add - 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_0_1_0_0_0_1_0; // sh3add + 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_0_0_1_0_0_0_1_0; // sh1add + 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_0_0_1_0_0_0_1_0; // sh2add + 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_0_0_1_0_0_0_1_0; // sh3add endcase if (P.XLEN==64) casez({OpD, Funct7D, Funct3D}) - 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_1_1_0_0_0_1_0; // sh1add.uw - 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_1_1_0_0_0_1_0; // sh2add.uw - 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_1_1_0_0_0_1_0; // sh3add.uw - 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_1_1_0_0_0_0_0; // add.uw - 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_0001_0000_1_1_1_1_0_0_0_0_0; // slli.uw + 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_0_1_1_0_0_0_1_0; // sh1add.uw + 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_0_1_1_0_0_0_1_0; // sh2add.uw + 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_0_1_1_0_0_0_1_0; // sh3add.uw + 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_0_1_1_0_0_0_0_0; // add.uw + 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_0001_0000_1_1_0_1_1_0_0_0_0_0; // slli.uw endcase end if (P.ZBB_SUPPORTED) begin casez({OpD, Funct7D, Funct3D}) 17'b0010011_0110000_001: if ((Rs2D[4:1] == 4'b0010)) - BMUControlsD = `BMUCTRLW'b000_0010_0001_1_1_0_1_0_0_0_0_0; // sign extend instruction + BMUControlsD = `BMUCTRLW'b000_0010_0001_1_1_0_0_1_0_0_0_0_0; // sign extend instruction else if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0])) - BMUControlsD = `BMUCTRLW'b000_0010_0000_1_1_0_1_0_0_0_0_0; // count instruction + BMUControlsD = `BMUCTRLW'b000_0010_0000_1_1_0_0_1_0_0_0_0_0; // count instruction 17'b0010011_0010100_101: if (Rs2D[4:0] == 5'b00111) - BMUControlsD = `BMUCTRLW'b000_0010_0010_1_1_0_1_0_0_0_0_0; // orc.b - 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0010_0111_1_0_0_1_1_0_0_0_0; // max - 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0010_0111_1_0_0_1_1_0_0_0_0; // maxu - 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0010_0011_1_0_0_1_1_0_0_0_0; // min - 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0010_0011_1_0_0_1_1_0_0_0_0; // minu + BMUControlsD = `BMUCTRLW'b000_0010_0010_1_1_0_0_1_0_0_0_0_0; // orc.b + 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0010_0111_1_0_0_0_1_1_0_0_0_0; // max + 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0010_0111_1_0_0_0_1_1_0_0_0_0; // maxu + 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0010_0011_1_0_0_0_1_1_0_0_0_0; // min + 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0010_0011_1_0_0_0_1_1_0_0_0_0; // minu endcase if (P.XLEN==32) casez({OpD, Funct7D, Funct3D}) - 17'b0110011_0000100_100: BMUControlsD = `BMUCTRLW'b000_0010_0001_1_1_0_1_0_0_0_0_0; // zexth (rv32) + 17'b0110011_0000100_100: BMUControlsD = `BMUCTRLW'b000_0010_0001_1_1_0_0_1_0_0_0_0_0; // zexth (rv32) endcase else if (P.XLEN==64) casez({OpD, Funct7D, Funct3D}) - 17'b0111011_0000100_100: BMUControlsD = `BMUCTRLW'b000_0010_0001_1_0_0_1_0_0_0_0_0; // zexth (rv64) + 17'b0111011_0000100_100: BMUControlsD = `BMUCTRLW'b000_0010_0001_1_0_0_0_1_0_0_0_0_0; // zexth (rv64) 17'b0011011_0110000_001: if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0])) - BMUControlsD = `BMUCTRLW'b000_0010_0000_1_1_1_1_0_0_0_0_0; // count word instruction + BMUControlsD = `BMUCTRLW'b000_0010_0000_1_1_1_1_0_0_0_0_0_0; // count word instruction (clzw/ctzw/cpopw) endcase end if (P.ZBC_SUPPORTED) casez({OpD, Funct7D, Funct3D}) - 17'b0110011_0000101_010: BMUControlsD = `BMUCTRLW'b000_0011_0001_1_0_0_1_0_0_0_0_0; // clmulr - 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_1_0_0_0_0_0; // clmul/clmulh + 17'b0110011_0000101_010: BMUControlsD = `BMUCTRLW'b000_0011_0001_1_0_0_0_1_0_0_0_0_0; // clmulr + 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_0_1_0_0_0_0_0; // clmul/clmulh endcase if (P.ZBKC_SUPPORTED) begin casez({OpD, Funct7D, Funct3D}) - 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_1_0_0_0_0_0; // clmul/clmulh - // 17'b0110011_0000101_001: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_1_0_0_0_0_0; // clmul - // 17'b0110011_0000101_011: BMUControlsD = `BMUCTRLW'b000_0011_0001_1_0_0_1_0_0_0_0_0; // clmulh + 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_0_1_0_0_0_0_0; // clmul/clmulh + // 17'b0110011_0000101_001: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_0_1_0_0_0_0_0; // clmul + // 17'b0110011_0000101_011: BMUControlsD = `BMUCTRLW'b000_0011_0001_1_0_0_0_1_0_0_0_0_0; // clmulh endcase end if (P.ZBS_SUPPORTED) begin // ZBS casez({OpD, Funct7D, Funct3D}) - 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_0000_1_0_0_1_1_0_1_0_0; // bclr - 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_0000_1_0_0_1_0_0_1_0_0; // bext - 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_0000_1_0_0_1_0_0_1_0_0; // binv - 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_0000_1_0_0_1_0_0_1_0_0; // bset + 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_0000_1_0_0_0_1_1_0_1_0_0; // bclr + 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_0000_1_0_0_0_1_0_0_1_0_0; // bext + 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_0000_1_0_0_0_1_0_0_1_0_0; // binv + 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_0000_1_0_0_0_1_0_0_1_0_0; // bset endcase if (P.XLEN==32) // ZBS 64-bit casez({OpD, Funct7D, Funct3D}) - 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_0000_1_1_0_1_1_0_1_0_0; // bclri - 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_0000_1_1_0_1_0_0_1_0_0; // bexti - 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_0000_1_1_0_1_0_0_1_0_0; // binvi - 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_0000_1_1_0_1_0_0_1_0_0; // bseti + 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_0000_1_1_0_0_1_1_0_1_0_0; // bclri + 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_0000_1_1_0_0_1_0_0_1_0_0; // bexti + 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_0000_1_1_0_0_1_0_0_1_0_0; // binvi + 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_0000_1_1_0_0_1_0_0_1_0_0; // bseti endcase else if (P.XLEN==64) // ZBS 64-bit casez({OpD, Funct7D, Funct3D}) - 17'b0010011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0001_0000_1_1_0_1_1_0_1_0_0; // bclri (rv64) - 17'b0010011_010010?_101: BMUControlsD = `BMUCTRLW'b101_0001_0000_1_1_0_1_0_0_1_0_0; // bexti (rv64) - 17'b0010011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0001_0000_1_1_0_1_0_0_1_0_0; // binvi (rv64) - 17'b0010011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0001_0000_1_1_0_1_0_0_1_0_0; // bseti (rv64) + 17'b0010011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0001_0000_1_1_0_0_1_1_0_1_0_0; // bclri (rv64) + 17'b0010011_010010?_101: BMUControlsD = `BMUCTRLW'b101_0001_0000_1_1_0_0_1_0_0_1_0_0; // bexti (rv64) + 17'b0010011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0001_0000_1_1_0_0_1_0_0_1_0_0; // binvi (rv64) + 17'b0010011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0001_0000_1_1_0_0_1_0_0_1_0_0; // bseti (rv64) endcase end if (P.ZBB_SUPPORTED | P.ZBS_SUPPORTED) // rv32i/64i shift instructions need BMU ALUSelect when BMU shifter is used casez({OpD, Funct7D, Funct3D}) - 17'b0110011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_0_1_0_0_0_0_0; // sra, srl, sll - 17'b0010011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_0_1_0_0_0_0_0; // srai, srli, slli - 17'b0111011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_1_1_0_0_0_0_0; // sraw, srlw, sllw - 17'b0011011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_1_1_0_0_0_0_0; // sraiw, srliw, slliw + 17'b0110011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_0_0_1_0_0_0_0_0; // sra, srl, sll + 17'b0010011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_0_0_1_0_0_0_0_0; // srai, srli, slli + 17'b0111011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_1_0_1_0_0_0_0_0; // sraw, srlw, sllw + 17'b0011011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_1_0_1_0_0_0_0_0; // sraiw, srliw, slliw endcase if (P.ZBKB_SUPPORTED) begin // ZBKB Bitmanip casez({OpD,Funct7D, Funct3D}) - 17'b0110011_0000100_100: BMUControlsD = `BMUCTRLW'b000_0100_0001_1_0_0_1_0_0_0_0_0; // pack - 17'b0110011_0000100_111: BMUControlsD = `BMUCTRLW'b000_0100_0001_1_0_0_1_0_0_0_0_0; // packh + 17'b0110011_0000100_100: BMUControlsD = `BMUCTRLW'b000_0100_0001_1_0_0_0_1_0_0_0_0_0; // pack + 17'b0110011_0000100_111: BMUControlsD = `BMUCTRLW'b000_0100_0001_1_0_0_0_1_0_0_0_0_0; // packh 17'b0010011_0110100_101: if (Rs2D == 5'b00111) - BMUControlsD = `BMUCTRLW'b000_0100_0000_1_1_0_1_0_0_0_0_0; // brev8 + BMUControlsD = `BMUCTRLW'b000_0100_0000_1_1_0_0_1_0_0_0_0_0; // brev8 endcase if (P.XLEN==32) casez({OpD, Funct7D, Funct3D}) 17'b0010011_0000100_001: if (Rs2D == 5'b01111) - BMUControlsD = `BMUCTRLW'b000_0100_0011_1_1_0_1_0_0_0_0_0; //zip + BMUControlsD = `BMUCTRLW'b000_0100_0011_1_1_0_0_1_0_0_0_0_0; //zip 17'b0010011_0000100_101: if (Rs2D == 5'b01111) - BMUControlsD = `BMUCTRLW'b000_0100_0011_1_1_0_1_0_0_0_0_0; //unzip + BMUControlsD = `BMUCTRLW'b000_0100_0011_1_1_0_0_1_0_0_0_0_0; //unzip endcase else if (P.XLEN==64) casez({OpD,Funct7D, Funct3D}) - 17'b0111011_0000100_100: BMUControlsD = `BMUCTRLW'b000_0100_0101_1_0_1_1_0_0_0_0_0; //packw + 17'b0111011_0000100_100: BMUControlsD = `BMUCTRLW'b000_0100_0101_1_0_1_0_1_0_0_0_0_0; //packw endcase end if (P.ZBB_SUPPORTED | P.ZBKB_SUPPORTED) begin // ZBB and ZBKB shared instructions casez({OpD, Funct7D, Funct3D}) - 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0001_0111_1_0_0_1_0_1_0_0_0; // rol - 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0001_0111_1_0_0_1_0_1_0_0_0; // ror - 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0001_0111_1_0_0_1_1_0_0_0_0; // andn - 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0001_0111_1_0_0_1_1_0_0_0_0; // orn - 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0001_0111_1_0_0_1_1_0_0_0_0; // xnor + 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0001_0111_1_0_0_0_1_0_1_0_0_0; // rol + 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0001_0111_1_0_0_0_1_0_1_0_0_0; // ror + 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0001_0111_1_0_0_0_1_1_0_0_0_0; // andn + 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0001_0111_1_0_0_0_1_1_0_0_0_0; // orn + 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0001_0111_1_0_0_0_1_1_0_0_0_0; // xnor 17'b0010011_011010?_101: if ((P.XLEN == 32 ^ Funct7D[0]) & (Rs2D == 5'b11000)) - BMUControlsD = `BMUCTRLW'b000_0010_0010_1_1_0_1_0_0_0_0_0; // rev8 + BMUControlsD = `BMUCTRLW'b000_0010_0010_1_1_0_0_1_0_0_0_0_0; // rev8 endcase if (P.XLEN==32) casez({OpD, Funct7D, Funct3D}) - 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0000_0111_1_1_0_1_0_1_0_0_0; // rori (rv32) + 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0000_0111_1_1_0_0_1_0_1_0_0_0; // rori (rv32) endcase else if (P.XLEN==64) casez({OpD, Funct7D, Funct3D}) - 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0000_0111_1_0_1_1_0_1_0_0_0; // rolw - 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0000_0111_1_0_1_1_0_1_0_0_0; // rorw - 17'b0010011_011000?_101: BMUControlsD = `BMUCTRLW'b001_0000_0111_1_1_0_1_0_1_0_0_0; // rori (rv64) - 17'b0011011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0000_0111_1_1_1_1_0_1_0_0_0; // roriw + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0000_0111_1_0_1_0_1_0_1_0_0_0; // rolw + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0000_0111_1_0_1_0_1_0_1_0_0_0; // rorw + 17'b0010011_011000?_101: BMUControlsD = `BMUCTRLW'b001_0000_0111_1_1_0_0_1_0_1_0_0_0; // rori (rv64) + 17'b0011011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0000_0111_1_1_1_0_1_0_1_0_0_0; // roriw endcase end if (P.ZBKX_SUPPORTED) begin //ZBKX casez({OpD, Funct7D, Funct3D}) - 17'b0110011_0010100_100: BMUControlsD = `BMUCTRLW'b000_0110_0000_1_0_0_1_0_0_0_0_0; // xperm8 - 17'b0110011_0010100_010: BMUControlsD = `BMUCTRLW'b000_0110_0001_1_0_0_1_0_0_0_0_0; // xperm4 + 17'b0110011_0010100_100: BMUControlsD = `BMUCTRLW'b000_0110_0000_1_0_0_0_1_0_0_0_0_0; // xperm8 + 17'b0110011_0010100_010: BMUControlsD = `BMUCTRLW'b000_0110_0001_1_0_0_0_1_0_0_0_0_0; // xperm4 endcase end if (P.ZKND_SUPPORTED) begin //ZKND if (P.XLEN==32) casez({OpD, Funct7D, Funct3D}) - 17'b0110011_??10101_000: BMUControlsD = `BMUCTRLW'b000_0111_0100_1_0_0_1_0_0_0_0_0; // aes32dsi - final round decrypt - 17'b0110011_??10111_000: BMUControlsD = `BMUCTRLW'b000_0111_0000_1_0_0_1_0_0_0_0_0; // aes32dsmi - mid round decrypt + 17'b0110011_??10101_000: BMUControlsD = `BMUCTRLW'b000_0111_0100_1_0_0_0_1_0_0_0_0_0; // aes32dsi - final round decrypt + 17'b0110011_??10111_000: BMUControlsD = `BMUCTRLW'b000_0111_0000_1_0_0_0_1_0_0_0_0_0; // aes32dsmi - mid round decrypt endcase else if (P.XLEN==64) casez({OpD, Funct7D, Funct3D}) - 17'b0110011_0011101_000: BMUControlsD = `BMUCTRLW'b000_0111_0100_1_0_0_1_0_0_0_0_0; // aes64ds - decrypt final round - 17'b0110011_0011111_000: BMUControlsD = `BMUCTRLW'b000_0111_0000_1_0_0_1_0_0_0_0_0; // aes64dsm - decrypt mid round + 17'b0110011_0011101_000: BMUControlsD = `BMUCTRLW'b000_0111_0100_1_0_0_0_1_0_0_0_0_0; // aes64ds - decrypt final round + 17'b0110011_0011111_000: BMUControlsD = `BMUCTRLW'b000_0111_0000_1_0_0_0_1_0_0_0_0_0; // aes64dsm - decrypt mid round 17'b0010011_0011000_001: if (Rs2D == 5'b00000) - BMUControlsD = `BMUCTRLW'b000_0111_1000_1_1_0_1_0_0_0_0_0; // aes64im - decrypt keyschdule mixcolumns + BMUControlsD = `BMUCTRLW'b000_0111_1000_1_1_0_0_1_0_0_0_0_0; // aes64im - decrypt keyschdule mixcolumns endcase end if (P.ZKNE_SUPPORTED) begin //ZKNE if (P.XLEN==32) casez({OpD, Funct7D, Funct3D}) - 17'b0110011_??10001_000: BMUControlsD = `BMUCTRLW'b000_0111_0101_1_0_0_1_0_0_0_0_0; // aes32esi - final round encrypt - 17'b0110011_??10011_000: BMUControlsD = `BMUCTRLW'b000_0111_0001_1_0_0_1_0_0_0_0_0; // aes32esmi - mid round encrypt + 17'b0110011_??10001_000: BMUControlsD = `BMUCTRLW'b000_0111_0101_1_0_0_0_1_0_0_0_0_0; // aes32esi - final round encrypt + 17'b0110011_??10011_000: BMUControlsD = `BMUCTRLW'b000_0111_0001_1_0_0_0_1_0_0_0_0_0; // aes32esmi - mid round encrypt endcase else if (P.XLEN==64) casez({OpD, Funct7D, Funct3D}) - 17'b0110011_0011001_000: BMUControlsD = `BMUCTRLW'b000_0111_0101_1_0_0_1_0_0_0_0_0; // aes64es - encrypt final round - 17'b0110011_0011011_000: BMUControlsD = `BMUCTRLW'b000_0111_0001_1_0_0_1_0_0_0_0_0; // aes64esm - encrypt mid round + 17'b0110011_0011001_000: BMUControlsD = `BMUCTRLW'b000_0111_0101_1_0_0_0_1_0_0_0_0_0; // aes64es - encrypt final round + 17'b0110011_0011011_000: BMUControlsD = `BMUCTRLW'b000_0111_0001_1_0_0_0_1_0_0_0_0_0; // aes64esm - encrypt mid round endcase end if ((P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED) & P.XLEN == 64) begin // ZKND and ZKNE shared instructions casez({OpD, Funct7D, Funct3D}) 17'b0010011_0011000_001: if (Rs2D[4] == 1'b1) - BMUControlsD = `BMUCTRLW'b000_0111_0010_1_0_0_1_0_0_0_0_0; // aes64ks1i - key schedule istr1 - 17'b0110011_0111111_000: BMUControlsD = `BMUCTRLW'b000_0111_0011_1_0_0_1_0_0_0_0_0; // aes64ks2 - key schedule istr2 + BMUControlsD = `BMUCTRLW'b000_0111_0010_1_0_0_0_1_0_0_0_0_0; // aes64ks1i - key schedule istr1 + 17'b0110011_0111111_000: BMUControlsD = `BMUCTRLW'b000_0111_0011_1_0_0_0_1_0_0_0_0_0; // aes64ks2 - key schedule istr2 endcase end if (P.ZKNH_SUPPORTED) begin // ZKNH casez({OpD, Funct7D, Funct3D}) 17'b0010011_0001000_001: - if (Rs2D == 5'b00010) BMUControlsD = `BMUCTRLW'b000_1000_0000_1_0_0_1_0_0_0_0_0; // sha256sig0 - else if (Rs2D == 5'b00011) BMUControlsD = `BMUCTRLW'b000_1000_0001_1_0_0_1_0_0_0_0_0; // sha256sig1 - else if (Rs2D == 5'b00000) BMUControlsD = `BMUCTRLW'b000_1000_0010_1_0_0_1_0_0_0_0_0; // sha256sum0 - else if (Rs2D == 5'b00001) BMUControlsD = `BMUCTRLW'b000_1000_0011_1_0_0_1_0_0_0_0_0; // sha256sum1 + if (Rs2D == 5'b00010) BMUControlsD = `BMUCTRLW'b000_1000_0000_1_0_0_0_1_0_0_0_0_0; // sha256sig0 + else if (Rs2D == 5'b00011) BMUControlsD = `BMUCTRLW'b000_1000_0001_1_0_0_0_1_0_0_0_0_0; // sha256sig1 + else if (Rs2D == 5'b00000) BMUControlsD = `BMUCTRLW'b000_1000_0010_1_0_0_0_1_0_0_0_0_0; // sha256sum0 + else if (Rs2D == 5'b00001) BMUControlsD = `BMUCTRLW'b000_1000_0011_1_0_0_0_1_0_0_0_0_0; // sha256sum1 endcase if (P.XLEN==32) casez({OpD, Funct7D, Funct3D}) - 17'b0110011_0101110_000: BMUControlsD = `BMUCTRLW'b000_1000_1000_1_0_0_1_0_0_0_0_0; // sha512sig0h - 17'b0110011_0101010_000: BMUControlsD = `BMUCTRLW'b000_1000_1001_1_0_0_1_0_0_0_0_0; // sha512sig0l - 17'b0110011_0101111_000: BMUControlsD = `BMUCTRLW'b000_1000_1010_1_0_0_1_0_0_0_0_0; // sha512sig1h - 17'b0110011_0101011_000: BMUControlsD = `BMUCTRLW'b000_1000_1011_1_0_0_1_0_0_0_0_0; // sha512sig1l - 17'b0110011_0101000_000: BMUControlsD = `BMUCTRLW'b000_1000_1100_1_0_0_1_0_0_0_0_0; // sha512sum0r - 17'b0110011_0101001_000: BMUControlsD = `BMUCTRLW'b000_1000_1110_1_0_0_1_0_0_0_0_0; // sha512sum1r + 17'b0110011_0101110_000: BMUControlsD = `BMUCTRLW'b000_1000_1000_1_0_0_0_1_0_0_0_0_0; // sha512sig0h + 17'b0110011_0101010_000: BMUControlsD = `BMUCTRLW'b000_1000_1001_1_0_0_0_1_0_0_0_0_0; // sha512sig0l + 17'b0110011_0101111_000: BMUControlsD = `BMUCTRLW'b000_1000_1010_1_0_0_0_1_0_0_0_0_0; // sha512sig1h + 17'b0110011_0101011_000: BMUControlsD = `BMUCTRLW'b000_1000_1011_1_0_0_0_1_0_0_0_0_0; // sha512sig1l + 17'b0110011_0101000_000: BMUControlsD = `BMUCTRLW'b000_1000_1100_1_0_0_0_1_0_0_0_0_0; // sha512sum0r + 17'b0110011_0101001_000: BMUControlsD = `BMUCTRLW'b000_1000_1110_1_0_0_0_1_0_0_0_0_0; // sha512sum1r endcase else if (P.XLEN==64) casez({OpD, Funct7D, Funct3D}) 17'b0010011_0001000_001: - if (Rs2D == 5'b00110) BMUControlsD = `BMUCTRLW'b000_1000_1000_1_0_0_1_0_0_0_0_0; // sha512sig0 - else if (Rs2D == 5'b00111) BMUControlsD = `BMUCTRLW'b000_1000_1001_1_0_0_1_0_0_0_0_0; // sha512sig1 - else if (Rs2D == 5'b00100) BMUControlsD = `BMUCTRLW'b000_1000_1010_1_0_0_1_0_0_0_0_0; // sha512sum0 - else if (Rs2D == 5'b00101) BMUControlsD = `BMUCTRLW'b000_1000_1011_1_0_0_1_0_0_0_0_0; // sha512sum1 + if (Rs2D == 5'b00110) BMUControlsD = `BMUCTRLW'b000_1000_1000_1_0_0_0_1_0_0_0_0_0; // sha512sig0 + else if (Rs2D == 5'b00111) BMUControlsD = `BMUCTRLW'b000_1000_1001_1_0_0_0_1_0_0_0_0_0; // sha512sig1 + else if (Rs2D == 5'b00100) BMUControlsD = `BMUCTRLW'b000_1000_1010_1_0_0_0_1_0_0_0_0_0; // sha512sum0 + else if (Rs2D == 5'b00101) BMUControlsD = `BMUCTRLW'b000_1000_1011_1_0_0_0_1_0_0_0_0_0; // sha512sum1 endcase end end // Unpack Control Signals - assign {BALUSelectD, BSelectD, ZBBSelectD, BRegWriteD,BALUSrcBD, BW64D, BALUOpD, BSubArithD, RotateD, MaskD, PreShiftD, IllegalBitmanipInstrD} = BMUControlsD; + assign {BALUSelectD, BSelectD, ZBBSelectD, BRegWriteD,BALUSrcBD, BW64D, BUW64D, BALUOpD, BSubArithD, RotateD, MaskD, PreShiftD, IllegalBitmanipInstrD} = BMUControlsD; // Pack BALUControl Signals assign BALUControlD = {RotateD, MaskD, PreShiftD}; diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 4dbb8ff82..74f5162ba 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -56,7 +56,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( output logic [2:0] Funct3E, // Instruction's funct3 field output logic [6:0] Funct7E, // Instruction's funct7 field output logic IntDivE, // Integer divide - output logic W64E, // RV64 W-type operation + output logic W64E, UW64E, // RV64 W/.uw-type operation output logic SubArithE, // Subtraction or arithmetic shift output logic JumpE, // jump instruction output logic BranchE, // Branch instruction @@ -158,6 +158,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( logic MatchDE; // Match between a source register in Decode stage and destination register in Execute stage logic FCvtIntStallD, MDUStallD, CSRRdStallD; // Stall due to conversion, load, multiply/divide, CSR read logic FunctCZeroD; // Funct7 and Funct3 indicate czero.* (not including Op check) + logic BUW64D; // Indiciates if it is a .uw type B instruction in Decode Stage // Extract fields assign OpD = InstrD[6:0]; @@ -326,7 +327,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( logic BALUSrcBD; // BMU alu src select signal bmuctrl #(P) bmuctrl(.clk, .reset, .InstrD, .ALUOpD, - .BRegWriteD, .BALUSrcBD, .BW64D, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, + .BRegWriteD, .BALUSrcBD, .BW64D, .BUW64D, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectD(PreALUSelectD), .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE); if (P.ZBA_SUPPORTED) begin // ALU Decoding is more comprehensive when ZBA is supported. slt and slti conflicts with sh1add, sh1add.uw @@ -350,6 +351,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( assign W64D = BaseW64D; assign ALUSrcBD = BaseALUSrcBD; assign SubArithD = BaseSubArithD; // TRUE If B-type or R-type instruction involves inverted operand + assign BUW64D = 1'b0; // no .uw instructions // tie off unused bit manipulation signals assign BSelectE = 4'b0000; @@ -417,9 +419,9 @@ module controller import cvw::*; #(parameter cvw_t P) ( flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD); // Execute stage pipeline control register and logic - flopenrc #(44) controlregE(clk, reset, FlushE, ~StallE, - {ALUSelectD, RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, Funct7D, W64D, SubArithD, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, CMOpD, IFUPrefetchD, LSUPrefetchD, CZeroD, InstrValidD}, - {ALUSelectE, IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, Funct7E, W64E, SubArithE, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, CMOpE, IFUPrefetchE, LSUPrefetchE, CZeroE, InstrValidE}); + flopenrc #(45) controlregE(clk, reset, FlushE, ~StallE, + {ALUSelectD, RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, Funct7D, W64D, BUW64D, SubArithD, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, CMOpD, IFUPrefetchD, LSUPrefetchD, CZeroD, InstrValidD}, + {ALUSelectE, IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, Funct7E, W64E, UW64E, SubArithE, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, CMOpE, IFUPrefetchE, LSUPrefetchE, CZeroE, InstrValidE}); flopenrc #(5) Rs1EReg(clk, reset, FlushE, ~StallE, Rs1D, Rs1E); flopenrc #(5) Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E); flopenrc #(5) RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE); diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index 12f4204e7..c04d0a4a6 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -41,7 +41,7 @@ module datapath import cvw::*; #(parameter cvw_t P) ( input logic [6:0] Funct7E, // Funct7 field of instruction in Execute stage input logic StallE, FlushE, // Stall, flush Execute stage input logic [1:0] ForwardAE, ForwardBE, // Forward ALU operands from later stages - input logic W64E, // W64-type instruction + input logic W64E,UW64E, // W64/.uw-type instruction input logic SubArithE, // Subtraction or arithmetic shift input logic ALUSrcAE, ALUSrcBE, // ALU operands input logic ALUResultSrcE, // Selects result to pass on to Memory stage @@ -109,7 +109,7 @@ module datapath import cvw::*; #(parameter cvw_t P) ( comparator #(P.XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE); mux2 #(P.XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(P.XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE); - alu #(P) alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, Funct7E, Rs2E, BALUControlE, BMUActiveE, CZeroE, ALUResultE, IEUAdrE); + alu #(P) alu(SrcAE, SrcBE, W64E, UW64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, Funct7E, Rs2E, BALUControlE, BMUActiveE, CZeroE, ALUResultE, IEUAdrE); mux2 #(P.XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE); mux2 #(P.XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index 4f9c62cb3..e820a3e41 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -93,6 +93,7 @@ module ieu import cvw::*; #(parameter cvw_t P) ( logic [3:0] ZBBSelectE; // ZBB Result Select Signal in Execute Stage logic [2:0] BALUControlE; // ALU Control signals for B instructions in Execute Stage logic SubArithE; // Subtraction or arithmetic shift + logic UW64E; // .uw-type instruction logic [6:0] Funct7E; @@ -111,7 +112,7 @@ module ieu import cvw::*; #(parameter cvw_t P) ( .StructuralStallD, .LoadStallD, .StoreStallD, .Rs1D, .Rs2D, .Rs2E, .StallE, .FlushE, .FlagsE, .FWriteIntE, .PCSrcE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, - .Funct3E, .Funct7E, .IntDivE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE, + .Funct3E, .Funct7E, .IntDivE, .W64E, .UW64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE, .BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .CZeroE, .MDUActiveE, .FCvtIntE, .ForwardAE, .ForwardBE, .CMOpM, .IFUPrefetchE, .LSUPrefetchM, .StallM, .FlushM, .MemRWE, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, @@ -120,7 +121,7 @@ module ieu import cvw::*; #(parameter cvw_t P) ( .RdW, .RdE, .RdM); datapath #(P) dp( - .clk, .reset, .ImmSrcD, .InstrD, .Rs1D, .Rs2D, .Rs2E, .StallE, .FlushE, .ForwardAE, .ForwardBE, .W64E, .SubArithE, + .clk, .reset, .ImmSrcD, .InstrD, .Rs1D, .Rs2D, .Rs2E, .StallE, .FlushE, .ForwardAE, .ForwardBE, .W64E, .UW64E, .SubArithE, .Funct3E, .Funct7E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE, .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .CZeroE, .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW, From 19e9dc5ce0d54f9a07c3345e04419c1aaa439b18 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 16 Jul 2024 15:52:52 -0500 Subject: [PATCH 059/219] Fixed wally.do to correctly log functional coverage. --- sim/questa/wally.do | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/sim/questa/wally.do b/sim/questa/wally.do index 156431bef..e5c85b92e 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -58,7 +58,7 @@ set FCdefineCOVER_RV64ZICSR "" set FCdefineCOVER_RV64C "" set FCdefineIDV_INCLUDE_TRACE2COV "" set FCTRACE2COV "" - +set FCdefineIDV_TRACE2COV "" set lockstep 0 # ok this is annoying. vlog, vopt, and vsim are very picky about how arguments are passed. # unforunately it won't allow these to be grouped as one argument per command so they are broken @@ -131,7 +131,7 @@ if {$FunctCoverageIndex >= 0} { set FCdefineCOVER_RV64C "+define+COVER_RV64C" set FCdefineIDV_INCLUDE_TRACE2COV "+define+IDV_INCLUDE_TRACE2COV" set FCTRACE2COV "+TRACE2COV_ENABLE=1" - + set FCdefineIDV_TRACE2COV "+IDV_TRACE2COV=1" set lst [lreplace $lst $FunctCoverageIndex $FunctCoverageIndex] }\ @@ -196,7 +196,7 @@ set temp3 [lindex $PlusArgs 3] # "Extra checking for conflicts with always_comb done at vopt time" # because vsim will run vopt -vlog -lint -work ${WKDIR} +incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared ${lockstepvoptstring} ${FCdefineIDV_INCLUDE_TRACE2COV} ${FCdefineINCLUDE_TRACE2COV} ${ImperasPubInc} ${ImperasPrivInc} ${rvviFiles} ${idvFiles} ${FCdefineCOVER_BASE_RV64I} ${FCdefineCOVER_LEVEL_DV_PR_EXT} ${FCdefineCOVER_RV64I} ${FCdefineCOVER_RV64M} ${FCdefineCOVER_RV64A} ${FCdefineCOVER_RV64F} ${FCdefineCOVER_RV64D} ${FCdefineCOVER_RV64ZICSR} ${FCdefineCOVER_RV64C} ${riscvISACOVsrc} ${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 +vlog -lint -work ${WKDIR} +incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared ${lockstepvoptstring} ${FCdefineIDV_INCLUDE_TRACE2COV} ${FCdefineINCLUDE_TRACE2COV} ${ImperasPubInc} ${ImperasPrivInc} ${rvviFiles} ${FCdefineCOVER_BASE_RV64I} ${FCdefineCOVER_LEVEL_DV_PR_EXT} ${FCdefineCOVER_RV64I} ${FCdefineCOVER_RV64M} ${FCdefineCOVER_RV64A} ${FCdefineCOVER_RV64F} ${FCdefineCOVER_RV64D} ${FCdefineCOVER_RV64ZICSR} ${FCdefineCOVER_RV64C} ${idvFiles} ${riscvISACOVsrc} ${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals @@ -204,7 +204,7 @@ vopt $accFlag wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} ${ParamArgs} #vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} ${PlusArgs} -fatal 7 ${SVLib} ${SVLibPath} ${OtherFlags} +TRACE2COV_ENABLE=1 -suppress 3829 ${CoverageVsimArg} #vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} ${PlusArgs} -fatal 7 ${SVLib} ${SVLibPath} +IDV_TRACE2COV=1 +TRACE2COV_ENABLE=1 -suppress 3829 ${CoverageVsimArg} -vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} $temp0 $temp1 $temp2 $temp3 -fatal 7 ${SVLib} ${SVLibPath} ${OtherFlags} ${FCTRACE2COV} -suppress 3829 ${CoverageVsimArg} +vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} $temp0 $temp1 $temp2 $temp3 -fatal 7 ${SVLib} ${SVLibPath} ${OtherFlags} ${FCTRACE2COV} ${FCdefineIDV_TRACE2COV} -suppress 3829 ${CoverageVsimArg} # vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829 # power add generates the logging necessary for said generation. From 4d36072f094a2839b8d605a56eeb4db0cb03c5f1 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 17 Jul 2024 06:04:21 -0700 Subject: [PATCH 060/219] Converted regression-wally to use argparse --- bin/regression-wally | 47 ++++++++++++++++++++++---------------------- bin/wsim | 2 +- 2 files changed, 24 insertions(+), 25 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index a059bf648..8d67e387b 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -11,6 +11,7 @@ # ################################## import sys,os,shutil +import argparse import multiprocessing from collections import namedtuple from multiprocessing import Pool, TimeoutError @@ -320,13 +321,16 @@ coveragesim = "questa" # Questa is required for code/functional coverage #defaultsim = "questa" # Default simulator for all other tests; change to Verilator when flow is ready defaultsim = "verilator" # Default simulator for all other tests -ccov = '--ccov' in sys.argv -fp = '--fp' in sys.argv -nightly = '--nightly' in sys.argv -testfloat = '--testfloat' in sys.argv -buildroot = '--buildroot' in sys.argv +parser = argparse.ArgumentParser() +parser.add_argument("--ccov", help="Code Coverage", action="store_true") +parser.add_argument("--fcov", help="Functional Coverage", action="store_true") +parser.add_argument("--nightly", help="Run large nightly regression", action="store_true") +parser.add_argument("--buildroot", help="Include Buildroot Linux boot test (takes many hours, done along with --nightly)", action="store_true") +parser.add_argument("--testfloat", help="Include Testfloat floating-point unit tests", action="store_true") +parser.add_argument("--fp", help="Include floating-point tests in coverage (slower runtime)", action="store_true") +args = parser.parse_args() -if (nightly): +if (args.nightly): nightMode = "--nightly"; # sims = [defaultsim] # uncomment to use only the default simulator sims = ["questa", "verilator", "vcs"] # uncomment to exercise all simulators @@ -334,7 +338,7 @@ else: nightMode = "" sims = [defaultsim] -if (ccov): # only run RV64GC tests in coverage mode +if (args.ccov): # only run RV64GC tests in coverage mode coverStr = '--ccov' else: coverStr = '' @@ -353,24 +357,24 @@ configs = [ # run full buildroot boot simulation (slow) if buildroot flag is set. Start it early to overlap with other tests -if (buildroot): +if (args.buildroot): # addTests(tests_buildrootboot, defaultsim) # non-lockstep with Verilator runs in about 2 hours addTests(tests_buildrootbootlockstep, "questa") # lockstep with Questa and ImperasDV runs overnight -if (ccov): # only run RV64GC tests on Questa in code coverage mode +if (args.ccov): # only run RV64GC tests on Questa in code coverage mode addTests(tests64gc_nofp, "questa") - if (fp): + if (args.fp): addTests(tests64gc_fp, "questa") else: for sim in sims: - if (not (buildroot and sim == defaultsim)): # skip shot buildroot sim if running long one + if (not (args.buildroot and sim == defaultsim)): # skip short buildroot sim if running long one addTests(tests_buildrootshort, sim) addTests(tests, sim) addTests(tests64gc_nofp, sim) addTests(tests64gc_fp, sim) # run derivative configurations and lockstep tests in nightly regression -if (nightly): +if (args.nightly): addTests(derivconfigtests, defaultsim) sim_log = WALLY + "/sim/questa/logs/lockstep_coverage.log" tc = TestCase( @@ -391,9 +395,9 @@ if (nightly): configs.append(tc) # testfloat tests -if (testfloat): # for testfloat alone, just run testfloat tests +if (args.testfloat): # for testfloat alone, just run testfloat tests configs = [] -if (testfloat or nightly): # for nightly, run testfloat along with others +if (args.testfloat or args.nightly): # for nightly, run testfloat along with others testfloatsim = "questa" # change to Verilator when Issue #707 about testfloat not running Verilator is resolved testfloatconfigs = ["fdqh_ieee_rv64gc", "fdq_ieee_rv64gc", "fdh_ieee_rv64gc", "fd_ieee_rv64gc", "fh_ieee_rv64gc", "f_ieee_rv64gc", "fdqh_ieee_rv32gc", "f_ieee_rv32gc"] for config in testfloatconfigs: @@ -458,7 +462,7 @@ if (testfloat or nightly): # for nightly, run testfloat along with others def main(): """Run the tests and count the failures""" - global configs, ccov + global configs, args os.chdir(regressionDir) dirs = ["questa/logs", "questa/wkdir", "verilator/logs", "verilator/wkdir", "vcs/logs", "vcs/wkdir"] for d in dirs: @@ -467,17 +471,12 @@ def main(): os.mkdir(d) except: pass - - if '--makeTests' in sys.argv: - os.chdir(regressionDir) - os.system('./make-tests.sh | tee ./logs/make-tests.log') - - elif '--ccov' in sys.argv: + if args.ccov: TIMEOUT_DUR = 20*60 # seconds os.system('rm -f questa/cov/*.ucdb') - elif '--nightly' in sys.argv: + elif args.nightly in sys.argv: TIMEOUT_DUR = 60*1440 # 1 day - elif '--testfloat' in sys.argv: + elif args.testfloat in sys.argv: TIMEOUT_DUR = 30*60 # seconds else: TIMEOUT_DUR = 10*60 # seconds @@ -497,7 +496,7 @@ def main(): print(f"{bcolors.FAIL}%s_%s: Timeout - runtime exceeded %d seconds{bcolors.ENDC}" % (config.variant, config.name, TIMEOUT_DUR)) # Coverage report - if ccov: + if args.ccov: os.system('make QuestaCodeCoverage') # Count the number of failures if num_fail: diff --git a/bin/wsim b/bin/wsim index 34e725707..b70d0e26f 100755 --- a/bin/wsim +++ b/bin/wsim @@ -27,7 +27,7 @@ parser.add_argument("--sim", "-s", help="Simulator", choices=["questa", "verilat parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench") parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true") parser.add_argument("--ccov", "-c", help="Code Coverage", action="store_true") -parser.add_argument("--fcov", "-f", help="Functional Coverage", action="store_true") +parser.add_argument("--fcov", "-f", help="Functional Coverage, implies lockstep", action="store_true") parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="") parser.add_argument("--vcd", "-v", help="Generate testbench.vcd", action="store_true") parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true") From df063acf611f0bb2a335fe93ce39a331bab55dee Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 18 Jul 2024 08:26:58 -0700 Subject: [PATCH 061/219] Refactored decompression to use simpler default illegal instruction --- src/ifu/decompress.sv | 190 ++++++++++++++++-------------------------- 1 file changed, 70 insertions(+), 120 deletions(-) diff --git a/src/ifu/decompress.sv b/src/ifu/decompress.sv index 512dacfd5..d8a1afb8b 100644 --- a/src/ifu/decompress.sv +++ b/src/ifu/decompress.sv @@ -32,7 +32,8 @@ module decompress import cvw::*; #(parameter cvw_t P) ( output logic [31:0] InstrD, // Decompressed instruction output logic IllegalCompInstrD // Invalid decompressed instruction ); - + + logic [32:0] LInstrD; // decompressed instruction with illegal flag in [32] logic [15:0] instr16; logic [4:0] rds1, rs2, rs1p, rs2p, rds1p, rdp; logic [11:0] immCILSP, immCILSPD, immCSS, immCSSD, immCL, immCLD, immCI, immCS, immCSD, immCB, immCIASP, immCIW; @@ -75,173 +76,122 @@ module decompress import cvw::*; #(parameter cvw_t P) ( always_comb if (op == 2'b11) begin // noncompressed instruction - InstrD = InstrRawD; - IllegalCompInstrD = '0; + LInstrD = {1'b0, InstrRawD}; end else begin // convert compressed instruction into uncompressed - IllegalCompInstrD = '0; + LInstrD = {1'b1, 16'b0, instr16}; // if a legal instruction is not decoded, default to illegal and preserve 16-bit value for mtval case ({op, instr16[15:13]}) - 5'b00000: if (immCIW != 0) InstrD = {immCIW, 5'b00010, 3'b000, rdp, 7'b0010011}; // c.addi4spn - else begin // illegal instruction - IllegalCompInstrD = 1'b1; - InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap - end + 5'b00000: if (immCIW != 0) LInstrD = {1'b0, immCIW, 5'b00010, 3'b000, rdp, 7'b0010011}; // c.addi4spn 5'b00001: if (P.ZCD_SUPPORTED) - InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000111}; // c.fld - else begin // unsupported instruction - IllegalCompInstrD = 1'b1; - InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap - end - 5'b00010: InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000011}; // c.lw - 5'b00011: if (P.XLEN==32) + LInstrD = {1'b0, immCLD, rs1p, 3'b011, rdp, 7'b0000111}; // c.fld + 5'b00010: LInstrD = {1'b0, immCL, rs1p, 3'b010, rdp, 7'b0000011}; // c.lw + 5'b00011: if (P.XLEN==32) begin if (P.ZCF_SUPPORTED) - InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000111}; // c.flw - else begin - IllegalCompInstrD = 1'b1; - InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap - end - else - InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000011}; // c.ld; + LInstrD = {1'b0, immCL, rs1p, 3'b010, rdp, 7'b0000111}; // c.flw + end else + LInstrD = {1'b0, immCLD, rs1p, 3'b011, rdp, 7'b0000011}; // c.ld 5'b00100: if (P.ZCB_SUPPORTED) if (instr16[12:10] == 3'b000) - InstrD = {10'b0, instr16[5], instr16[6], rs1p, 3'b100, rdp, 7'b0000011}; // c.lbu + LInstrD = {1'b0, 10'b0, instr16[5], instr16[6], rs1p, 3'b100, rdp, 7'b0000011}; // c.lbu else if (instr16[12:10] == 3'b001) begin if (instr16[6]) - InstrD = {10'b0, instr16[5], 1'b0, rs1p, 3'b001, rdp, 7'b0000011}; // c.lh + LInstrD = {1'b0, 10'b0, instr16[5], 1'b0, rs1p, 3'b001, rdp, 7'b0000011}; // c.lh else - InstrD = {10'b0, instr16[5], 1'b0, rs1p, 3'b101, rdp, 7'b0000011}; // c.lhu + LInstrD = {1'b0, 10'b0, instr16[5], 1'b0, rs1p, 3'b101, rdp, 7'b0000011}; // c.lhu end else if (instr16[12:10] == 3'b010) - InstrD = {7'b0, rs2p, rs1p, 3'b000, 3'b000, instr16[5], instr16[6], 7'b0100011}; // c.sb + LInstrD = {1'b0, 7'b0, rs2p, rs1p, 3'b000, 3'b000, instr16[5], instr16[6], 7'b0100011}; // c.sb else if (instr16[12:10] == 3'b011 & instr16[6] == 1'b0) - InstrD = {7'b0, rs2p, rs1p, 3'b001, 3'b000, instr16[5], 1'b0, 7'b0100011}; // c.sh - else begin - IllegalCompInstrD = 1'b1; - InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap - end - else begin - IllegalCompInstrD = 1'b1; - InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap - end + LInstrD = {1'b0, 7'b0, rs2p, rs1p, 3'b001, 3'b000, instr16[5], 1'b0, 7'b0100011}; // c.sh 5'b00101: if (P.ZCD_SUPPORTED) - InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100111}; // c.fsd - else begin // unsupported instruction - IllegalCompInstrD = 1'b1; - InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap - end - 5'b00110: InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100011}; // c.sw - 5'b00111: if (P.XLEN==32) + LInstrD = {1'b0, immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100111}; // c.fsd + 5'b00110: LInstrD = {1'b0, immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100011}; // c.sw + 5'b00111: if (P.XLEN==32) begin if (P.ZCF_SUPPORTED) - InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw - else begin - IllegalCompInstrD = 1'b1; - InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap - end - else - InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100011}; //c.sd - 5'b01000: InstrD = {immCI, rds1, 3'b000, rds1, 7'b0010011}; // c.addi + LInstrD = {1'b0, immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw + end else + LInstrD = {1'b0, immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100011}; //c.sd + 5'b01000: LInstrD = {1'b0, immCI, rds1, 3'b000, rds1, 7'b0010011}; // c.addi 5'b01001: if (P.XLEN==32) - InstrD = {immCJ, 5'b00001, 7'b1101111}; // c.jal + LInstrD = {1'b0, immCJ, 5'b00001, 7'b1101111}; // c.jal else - InstrD = {immCI, rds1, 3'b000, rds1, 7'b0011011}; // c.addiw - 5'b01010: InstrD = {immCI, 5'b00000, 3'b000, rds1, 7'b0010011}; // c.li + LInstrD = {1'b0, immCI, rds1, 3'b000, rds1, 7'b0011011}; // c.addiw + 5'b01010: LInstrD = {1'b0, immCI, 5'b00000, 3'b000, rds1, 7'b0010011}; // c.li 5'b01011: if (rds1 != 5'b00010) - InstrD = {immCILUI, rds1, 7'b0110111}; // c.lui + LInstrD = {1'b0, immCILUI, rds1, 7'b0110111}; // c.lui else - InstrD = {immCIASP, rds1, 3'b000, rds1, 7'b0010011}; // c.addi16sp + LInstrD = {1'b0, immCIASP, rds1, 3'b000, rds1, 7'b0010011}; // c.addi16sp 5'b01100: if (instr16[11:10] == 2'b00) - InstrD = {6'b000000, immSH, rds1p, 3'b101, rds1p, 7'b0010011}; // c.srli + LInstrD = {1'b0, 6'b000000, immSH, rds1p, 3'b101, rds1p, 7'b0010011}; // c.srli else if (instr16[11:10] == 2'b01) - InstrD = {6'b010000, immSH, rds1p, 3'b101, rds1p, 7'b0010011}; // c.srai + LInstrD = {1'b0, 6'b010000, immSH, rds1p, 3'b101, rds1p, 7'b0010011}; // c.srai else if (instr16[11:10] == 2'b10) - InstrD = {immCI, rds1p, 3'b111, rds1p, 7'b0010011}; // c.andi + LInstrD = {1'b0, immCI, rds1p, 3'b111, rds1p, 7'b0010011}; // c.andi else if (instr16[12:10] == 3'b011) if (instr16[6:5] == 2'b00) - InstrD = {7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0110011}; // c.sub + LInstrD = {1'b0, 7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0110011}; // c.sub else if (instr16[6:5] == 2'b01) - InstrD = {7'b0000000, rs2p, rds1p, 3'b100, rds1p, 7'b0110011}; // c.xor + LInstrD = {1'b0, 7'b0000000, rs2p, rds1p, 3'b100, rds1p, 7'b0110011}; // c.xor else if (instr16[6:5] == 2'b10) - InstrD = {7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011}; // c.or + LInstrD = {1'b0, 7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011}; // c.or else // if (instr16[6:5] == 2'b11) - InstrD = {7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011}; // c.and + LInstrD = {1'b0, 7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011}; // c.and else begin // (instr16[12:10] == 3'b111) if (instr16[6:5] == 2'b00 & P.XLEN > 32) - InstrD = {7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.subw + LInstrD = {1'b0, 7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.subw else if (instr16[6:5] == 2'b01 & P.XLEN > 32) - InstrD = {7'b0000000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.addw + LInstrD = {1'b0, 7'b0000000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.addw else if (instr16[6:2] == 5'b11000 & P.ZCB_SUPPORTED) - InstrD = {12'b000011111111, rds1p, 3'b111, rds1p, 7'b0010011}; // c.zext.b = andi rd, rs1, 255 + LInstrD = {1'b0, 12'b000011111111, rds1p, 3'b111, rds1p, 7'b0010011}; // c.zext.b = andi rd, rs1, 255 else if (instr16[6:2] == 5'b11001 & P.ZCB_SUPPORTED & P.ZBB_SUPPORTED) - InstrD = {12'b011000000100, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.b + LInstrD = {1'b0, 12'b011000000100, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.b else if (instr16[6:2] == 5'b11010 & P.ZCB_SUPPORTED & P.ZBB_SUPPORTED) - InstrD = {7'b0000100, 5'b00000, rds1p, 3'b100, rds1p, 3'b011, P.XLEN > 32, 3'b011}; // c.zext.h + LInstrD = {1'b0, 7'b0000100, 5'b00000, rds1p, 3'b100, rds1p, 3'b011, P.XLEN > 32, 3'b011}; // c.zext.h else if (instr16[6:2] == 5'b11011 & P.ZCB_SUPPORTED & P.ZBB_SUPPORTED) - InstrD = {12'b011000000101, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.h + LInstrD = {1'b0, 12'b011000000101, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.h else if (instr16[6:2] == 5'b11101 & P.ZCB_SUPPORTED) - InstrD = {12'b111111111111, rds1p, 3'b100, rds1p, 7'b0010011}; // c.not = xori + LInstrD = {1'b0, 12'b111111111111, rds1p, 3'b100, rds1p, 7'b0010011}; // c.not = xori else if (instr16[6:2] == 5'b11100 & P.ZCB_SUPPORTED & P.ZBA_SUPPORTED & P.XLEN > 32) - InstrD = {7'b0000100, 5'b00000, rds1p, 3'b000, rds1p, 7'b0111011}; // c.zext.w = add.uw rd, rs1, 0 + LInstrD = {1'b0, 7'b0000100, 5'b00000, rds1p, 3'b000, rds1p, 7'b0111011}; // c.zext.w = add.uw rd, rs1, 0 else if (instr16[6:5] == 2'b10 & P.ZCB_SUPPORTED & P.ZMMUL_SUPPORTED) - InstrD = {7'b0000001, rs2p, rds1p, 3'b000, rds1p, 7'b0110011}; // c.mul - else begin // reserved - IllegalCompInstrD = 1'b1; - InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap - end - /** end else begin // illegal instruction - IllegalCompInstrD = 1'b1; - InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap **/ + LInstrD = {1'b0, 7'b0000001, rs2p, rds1p, 3'b000, rds1p, 7'b0110011}; // c.mul end - 5'b01101: InstrD = {immCJ, 5'b00000, 7'b1101111}; // c.j - 5'b01110: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011}; // c.beqz - 5'b01111: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b001, immCB[4:0], 7'b1100011}; // c.bnez - 5'b10000: InstrD = {6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli + 5'b01101: LInstrD = {1'b0, immCJ, 5'b00000, 7'b1101111}; // c.j + 5'b01110: LInstrD = {1'b0, immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011}; // c.beqz + 5'b01111: LInstrD = {1'b0, immCB[11:5], 5'b00000, rs1p, 3'b001, immCB[4:0], 7'b1100011}; // c.bnez + 5'b10000: LInstrD = {1'b0, 6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli 5'b10001: if (P.ZCD_SUPPORTED) - InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp - else begin // unsupported instruction - IllegalCompInstrD = 1'b1; - InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap - end - 5'b10010: InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp - 5'b10011: if (P.XLEN == 32) + LInstrD = {1'b0, immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp + 5'b10010: LInstrD = {1'b0, immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp + 5'b10011: if (P.XLEN == 32) begin if (P.ZCF_SUPPORTED) - InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp - else begin - IllegalCompInstrD = 1'b1; - InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap - end - else - InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000011}; // c.ldsp + LInstrD = {1'b0, immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp + end else + LInstrD = {1'b0, immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000011}; // c.ldsp 5'b10100: if (instr16[12] == 0) if (instr16[6:2] == 5'b00000) - InstrD = {7'b0000000, 5'b00000, rds1, 3'b000, 5'b00000, 7'b1100111}; // c.jr + LInstrD = {1'b0, 7'b0000000, 5'b00000, rds1, 3'b000, 5'b00000, 7'b1100111}; // c.jr else - InstrD = {7'b0000000, rs2, 5'b00000, 3'b000, rds1, 7'b0110011}; // c.mv + LInstrD = {1'b0, 7'b0000000, rs2, 5'b00000, 3'b000, rds1, 7'b0110011}; // c.mv else if (rs2 == 5'b00000) if (rds1 == 5'b00000) - InstrD = {12'b1, 5'b00000, 3'b000, 5'b00000, 7'b1110011}; // c.ebreak + LInstrD = {1'b0, 12'b1, 5'b00000, 3'b000, 5'b00000, 7'b1110011}; // c.ebreak else - InstrD = {12'b0, rds1, 3'b000, 5'b00001, 7'b1100111}; // c.jalr + LInstrD = {1'b0, 12'b0, rds1, 3'b000, 5'b00001, 7'b1100111}; // c.jalr else - InstrD = {7'b0000000, rs2, rds1, 3'b000, rds1, 7'b0110011}; // c.add + LInstrD = {1'b0, 7'b0000000, rs2, rds1, 3'b000, rds1, 7'b0110011}; // c.add 5'b10101: if (P.ZCD_SUPPORTED) - InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp - else begin // unsupported instruction - IllegalCompInstrD = 1'b1; - InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap - end - 5'b10110: InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100011}; // c.swsp - 5'b10111: if (P.XLEN==32) + LInstrD = {1'b0, immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp + 5'b10110: LInstrD = {1'b0, immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100011}; // c.swsp + 5'b10111: if (P.XLEN==32) begin if (P.ZCF_SUPPORTED) - InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100111}; // c.fswsp - else begin - IllegalCompInstrD = 1'b1; - InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap - end - else - InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100011}; // c.sdsp - default: begin // illegal instruction - IllegalCompInstrD = 1'b1; - InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap - end + LInstrD = {1'b0, immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100111}; // c.fswsp + end else + LInstrD = {1'b0, immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100011}; // c.sdsp + default: ; // illegal instruction endcase end + + // extract instruction and illegal from LInstrD + assign {IllegalCompInstrD, InstrD} = LInstrD; + endmodule From 3b4726ea9906cbc943d32b83be98bf0729966f84 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 18 Jul 2024 09:30:16 -0700 Subject: [PATCH 062/219] Check legal compressed nonzero destination registers, add c.nop decoding --- src/ifu/decompress.sv | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/src/ifu/decompress.sv b/src/ifu/decompress.sv index d8a1afb8b..340c5055a 100644 --- a/src/ifu/decompress.sv +++ b/src/ifu/decompress.sv @@ -109,16 +109,17 @@ module decompress import cvw::*; #(parameter cvw_t P) ( LInstrD = {1'b0, immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw end else LInstrD = {1'b0, immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100011}; //c.sd - 5'b01000: LInstrD = {1'b0, immCI, rds1, 3'b000, rds1, 7'b0010011}; // c.addi + 5'b01000: if (rds1 != 5'b0) LInstrD = {1'b0, immCI, rds1, 3'b000, rds1, 7'b0010011}; // c.addi + else if (immCI[5:0] == 6'b0) LInstrD = {1'b0, 25'b0, 7'b0010011}; // c.nop 5'b01001: if (P.XLEN==32) LInstrD = {1'b0, immCJ, 5'b00001, 7'b1101111}; // c.jal else LInstrD = {1'b0, immCI, rds1, 3'b000, rds1, 7'b0011011}; // c.addiw - 5'b01010: LInstrD = {1'b0, immCI, 5'b00000, 3'b000, rds1, 7'b0010011}; // c.li - 5'b01011: if (rds1 != 5'b00010) - LInstrD = {1'b0, immCILUI, rds1, 7'b0110111}; // c.lui - else + 5'b01010: if (rds1 != 5'b0) LInstrD = {1'b0, immCI, 5'b00000, 3'b000, rds1, 7'b0010011}; // c.li + 5'b01011: if (rds1 == 5'b00010) LInstrD = {1'b0, immCIASP, rds1, 3'b000, rds1, 7'b0010011}; // c.addi16sp + else if (rds1 != 5'b0) + LInstrD = {1'b0, immCILUI, rds1, 7'b0110111}; // c.lui 5'b01100: if (instr16[11:10] == 2'b00) LInstrD = {1'b0, 6'b000000, immSH, rds1p, 3'b101, rds1p, 7'b0010011}; // c.srli else if (instr16[11:10] == 2'b01) @@ -159,25 +160,25 @@ module decompress import cvw::*; #(parameter cvw_t P) ( 5'b01111: LInstrD = {1'b0, immCB[11:5], 5'b00000, rs1p, 3'b001, immCB[4:0], 7'b1100011}; // c.bnez 5'b10000: LInstrD = {1'b0, 6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli 5'b10001: if (P.ZCD_SUPPORTED) - LInstrD = {1'b0, immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp - 5'b10010: LInstrD = {1'b0, immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp + if (rds1 != 5'b0) LInstrD = {1'b0, immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp + 5'b10010: if (rds1 != 5'b0) LInstrD = {1'b0, immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp 5'b10011: if (P.XLEN == 32) begin if (P.ZCF_SUPPORTED) LInstrD = {1'b0, immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp end else LInstrD = {1'b0, immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000011}; // c.ldsp 5'b10100: if (instr16[12] == 0) - if (instr16[6:2] == 5'b00000) - LInstrD = {1'b0, 7'b0000000, 5'b00000, rds1, 3'b000, 5'b00000, 7'b1100111}; // c.jr - else + if (instr16[6:2] == 5'b00000) begin + if (rds1 != 5'b0) LInstrD = {1'b0, 7'b0000000, 5'b00000, rds1, 3'b000, 5'b00000, 7'b1100111}; // c.jr + end else LInstrD = {1'b0, 7'b0000000, rs2, 5'b00000, 3'b000, rds1, 7'b0110011}; // c.mv else - if (rs2 == 5'b00000) + if (rs2 == 5'b00000) begin if (rds1 == 5'b00000) LInstrD = {1'b0, 12'b1, 5'b00000, 3'b000, 5'b00000, 7'b1110011}; // c.ebreak else - LInstrD = {1'b0, 12'b0, rds1, 3'b000, 5'b00001, 7'b1100111}; // c.jalr - else + if (rds1 != 5'b0) LInstrD = {1'b0, 12'b0, rds1, 3'b000, 5'b00001, 7'b1100111}; // c.jalr + end else LInstrD = {1'b0, 7'b0000000, rs2, rds1, 3'b000, rds1, 7'b0110011}; // c.add 5'b10101: if (P.ZCD_SUPPORTED) LInstrD = {1'b0, immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp From ebea314a6edd238cfff2563f647eeafbd57383e7 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 18 Jul 2024 21:38:17 -0700 Subject: [PATCH 063/219] Modified decompressor to look for illegal x0 values and hints --- src/ifu/decompress.sv | 33 +++++++++++++++++++++------------ 1 file changed, 21 insertions(+), 12 deletions(-) diff --git a/src/ifu/decompress.sv b/src/ifu/decompress.sv index 340c5055a..10d59f7f2 100644 --- a/src/ifu/decompress.sv +++ b/src/ifu/decompress.sv @@ -109,22 +109,27 @@ module decompress import cvw::*; #(parameter cvw_t P) ( LInstrD = {1'b0, immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw end else LInstrD = {1'b0, immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100011}; //c.sd - 5'b01000: if (rds1 != 5'b0) LInstrD = {1'b0, immCI, rds1, 3'b000, rds1, 7'b0010011}; // c.addi + 5'b01000: if (rds1 != 5'b0) + if (immCI[5:0] != 0) LInstrD = {1'b0, immCI, rds1, 3'b000, rds1, 7'b0010011}; // c.addi + else LInstrD = {1'b0, 25'b0, 7'b0010011}; // c.addi with imm = 0 is a HINT, treated as nop else if (immCI[5:0] == 6'b0) LInstrD = {1'b0, 25'b0, 7'b0010011}; // c.nop + else LInstrD = {1'b0, 25'b0, 7'b0010011}; // c.nop with imm != 0 is a HINT, treated as nop 5'b01001: if (P.XLEN==32) LInstrD = {1'b0, immCJ, 5'b00001, 7'b1101111}; // c.jal - else + else if (rds1 != 5'b0) LInstrD = {1'b0, immCI, rds1, 3'b000, rds1, 7'b0011011}; // c.addiw 5'b01010: if (rds1 != 5'b0) LInstrD = {1'b0, immCI, 5'b00000, 3'b000, rds1, 7'b0010011}; // c.li + else LInstrD = {1'b0, 25'b0, 7'b0010011}; // c.li with rd = 0 is a HINT, treated as nop 5'b01011: if (rds1 == 5'b00010) LInstrD = {1'b0, immCIASP, rds1, 3'b000, rds1, 7'b0010011}; // c.addi16sp else if (rds1 != 5'b0) LInstrD = {1'b0, immCILUI, rds1, 7'b0110111}; // c.lui - 5'b01100: if (instr16[11:10] == 2'b00) - LInstrD = {1'b0, 6'b000000, immSH, rds1p, 3'b101, rds1p, 7'b0010011}; // c.srli - else if (instr16[11:10] == 2'b01) - LInstrD = {1'b0, 6'b010000, immSH, rds1p, 3'b101, rds1p, 7'b0010011}; // c.srai - else if (instr16[11:10] == 2'b10) + else if (immCILUI[5:0] != 0) LInstrD = {1'b0, 25'b0, 7'b0010011}; // c.lui with rd = 0, imm!=0 is a HINT, treated as nop + 5'b01100: if (instr16[11:10] == 2'b00) begin + if (P.XLEN == 64 | ~immSH[5]) LInstrD = {1'b0, 6'b000000, immSH, rds1p, 3'b101, rds1p, 7'b0010011}; // c.srli; shamt[5] must be 0 in RV32C + end else if (instr16[11:10] == 2'b01) begin + if (P.XLEN == 64 | ~immSH[5]) LInstrD = {1'b0, 6'b010000, immSH, rds1p, 3'b101, rds1p, 7'b0010011}; // c.srai; shamt[5] must be 0 in RV32C + end else if (instr16[11:10] == 2'b10) LInstrD = {1'b0, immCI, rds1p, 3'b111, rds1p, 7'b0010011}; // c.andi else if (instr16[12:10] == 3'b011) if (instr16[6:5] == 2'b00) @@ -158,20 +163,23 @@ module decompress import cvw::*; #(parameter cvw_t P) ( 5'b01101: LInstrD = {1'b0, immCJ, 5'b00000, 7'b1101111}; // c.j 5'b01110: LInstrD = {1'b0, immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011}; // c.beqz 5'b01111: LInstrD = {1'b0, immCB[11:5], 5'b00000, rs1p, 3'b001, immCB[4:0], 7'b1100011}; // c.bnez - 5'b10000: LInstrD = {1'b0, 6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli + 5'b10000: if (rds1 != 5'b0) begin + if (P.XLEN == 64 | ~immSH[5]) LInstrD = {1'b0, 6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli; shamt[5] must be 0 in RV32C + end else if (immSH != 0) LInstrD = {1'b0, 25'b0, 7'b0010011}; // c.slli with rd = 0, immm != 0 is a HINT, treated as nop 5'b10001: if (P.ZCD_SUPPORTED) if (rds1 != 5'b0) LInstrD = {1'b0, immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp 5'b10010: if (rds1 != 5'b0) LInstrD = {1'b0, immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp 5'b10011: if (P.XLEN == 32) begin if (P.ZCF_SUPPORTED) LInstrD = {1'b0, immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp - end else + end else if (rds1 != 5'b0) LInstrD = {1'b0, immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000011}; // c.ldsp 5'b10100: if (instr16[12] == 0) - if (instr16[6:2] == 5'b00000) begin + if (rs2 == 5'b00000) begin if (rds1 != 5'b0) LInstrD = {1'b0, 7'b0000000, 5'b00000, rds1, 3'b000, 5'b00000, 7'b1100111}; // c.jr end else - LInstrD = {1'b0, 7'b0000000, rs2, 5'b00000, 3'b000, rds1, 7'b0110011}; // c.mv + if (rds1 != 5'b0) LInstrD = {1'b0, 7'b0000000, rs2, 5'b00000, 3'b000, rds1, 7'b0110011}; // c.mv + else LInstrD = {1'b0, 25'b0, 7'b0010011}; // c.mv with rd = 0 is a HINT, treated as nop else if (rs2 == 5'b00000) begin if (rds1 == 5'b00000) @@ -179,7 +187,8 @@ module decompress import cvw::*; #(parameter cvw_t P) ( else if (rds1 != 5'b0) LInstrD = {1'b0, 12'b0, rds1, 3'b000, 5'b00001, 7'b1100111}; // c.jalr end else - LInstrD = {1'b0, 7'b0000000, rs2, rds1, 3'b000, rds1, 7'b0110011}; // c.add + if (rds1 != 0) LInstrD = {1'b0, 7'b0000000, rs2, rds1, 3'b000, rds1, 7'b0110011}; // c.add + else LInstrD = {1'b0, 25'b0, 7'b0010011}; // c.add with rd = 0 is a HINT, treated as nop, even if it is a C.NTL 5'b10101: if (P.ZCD_SUPPORTED) LInstrD = {1'b0, immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp 5'b10110: LInstrD = {1'b0, immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100011}; // c.swsp From 945722cd5b15a23d2da79a68a9887d26a1681a93 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 18 Jul 2024 22:01:43 -0700 Subject: [PATCH 064/219] Neatly formatted decompress.sv --- src/ifu/decompress.sv | 159 ++++++++++++++++++------------------------ 1 file changed, 68 insertions(+), 91 deletions(-) diff --git a/src/ifu/decompress.sv b/src/ifu/decompress.sv index 10d59f7f2..2b0caf269 100644 --- a/src/ifu/decompress.sv +++ b/src/ifu/decompress.sv @@ -40,6 +40,7 @@ module decompress import cvw::*; #(parameter cvw_t P) ( logic [19:0] immCJ, immCILUI; logic [5:0] immSH; logic [1:0] op; + logic LegalCompInstrD; // Extract op and register source/destination fields assign instr16 = InstrRawD[15:0]; // instruction is already aligned @@ -76,132 +77,108 @@ module decompress import cvw::*; #(parameter cvw_t P) ( always_comb if (op == 2'b11) begin // noncompressed instruction - LInstrD = {1'b0, InstrRawD}; + LInstrD = {1'b1, InstrRawD}; end else begin // convert compressed instruction into uncompressed - LInstrD = {1'b1, 16'b0, instr16}; // if a legal instruction is not decoded, default to illegal and preserve 16-bit value for mtval + LInstrD = {1'b0, 16'b0, instr16}; // if a legal instruction is not decoded, default to illegal and preserve 16-bit value for mtval case ({op, instr16[15:13]}) - 5'b00000: if (immCIW != 0) LInstrD = {1'b0, immCIW, 5'b00010, 3'b000, rdp, 7'b0010011}; // c.addi4spn - 5'b00001: if (P.ZCD_SUPPORTED) - LInstrD = {1'b0, immCLD, rs1p, 3'b011, rdp, 7'b0000111}; // c.fld - 5'b00010: LInstrD = {1'b0, immCL, rs1p, 3'b010, rdp, 7'b0000011}; // c.lw + 5'b00000: if (immCIW != 0) LInstrD = {1'b1, immCIW, 5'b00010, 3'b000, rdp, 7'b0010011}; // c.addi4spn + 5'b00001: if (P.ZCD_SUPPORTED) LInstrD = {1'b1, immCLD, rs1p, 3'b011, rdp, 7'b0000111}; // c.fld + 5'b00010: LInstrD = {1'b1, immCL, rs1p, 3'b010, rdp, 7'b0000011}; // c.lw 5'b00011: if (P.XLEN==32) begin - if (P.ZCF_SUPPORTED) - LInstrD = {1'b0, immCL, rs1p, 3'b010, rdp, 7'b0000111}; // c.flw - end else - LInstrD = {1'b0, immCLD, rs1p, 3'b011, rdp, 7'b0000011}; // c.ld + if (P.ZCF_SUPPORTED) LInstrD = {1'b1, immCL, rs1p, 3'b010, rdp, 7'b0000111}; // c.flw + end else LInstrD = {1'b1, immCLD, rs1p, 3'b011, rdp, 7'b0000011}; // c.ld 5'b00100: if (P.ZCB_SUPPORTED) - if (instr16[12:10] == 3'b000) - LInstrD = {1'b0, 10'b0, instr16[5], instr16[6], rs1p, 3'b100, rdp, 7'b0000011}; // c.lbu + if (instr16[12:10] == 3'b000) LInstrD = {1'b1, 10'b0, instr16[5], instr16[6], rs1p, 3'b100, rdp, 7'b0000011}; // c.lbu else if (instr16[12:10] == 3'b001) begin - if (instr16[6]) - LInstrD = {1'b0, 10'b0, instr16[5], 1'b0, rs1p, 3'b001, rdp, 7'b0000011}; // c.lh - else - LInstrD = {1'b0, 10'b0, instr16[5], 1'b0, rs1p, 3'b101, rdp, 7'b0000011}; // c.lhu + if (instr16[6]) LInstrD = {1'b1, 10'b0, instr16[5], 1'b0, rs1p, 3'b001, rdp, 7'b0000011}; // c.lh + else LInstrD = {1'b1, 10'b0, instr16[5], 1'b0, rs1p, 3'b101, rdp, 7'b0000011}; // c.lhu end else if (instr16[12:10] == 3'b010) - LInstrD = {1'b0, 7'b0, rs2p, rs1p, 3'b000, 3'b000, instr16[5], instr16[6], 7'b0100011}; // c.sb + LInstrD = {1'b1, 7'b0, rs2p, rs1p, 3'b000, 3'b000, instr16[5], instr16[6], 7'b0100011}; // c.sb else if (instr16[12:10] == 3'b011 & instr16[6] == 1'b0) - LInstrD = {1'b0, 7'b0, rs2p, rs1p, 3'b001, 3'b000, instr16[5], 1'b0, 7'b0100011}; // c.sh - 5'b00101: if (P.ZCD_SUPPORTED) - LInstrD = {1'b0, immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100111}; // c.fsd - 5'b00110: LInstrD = {1'b0, immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100011}; // c.sw + LInstrD = {1'b1, 7'b0, rs2p, rs1p, 3'b001, 3'b000, instr16[5], 1'b0, 7'b0100011}; // c.sh + 5'b00101: if (P.ZCD_SUPPORTED) LInstrD = {1'b1, immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100111}; // c.fsd + 5'b00110: LInstrD = {1'b1, immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100011}; // c.sw 5'b00111: if (P.XLEN==32) begin - if (P.ZCF_SUPPORTED) - LInstrD = {1'b0, immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw - end else - LInstrD = {1'b0, immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100011}; //c.sd + if (P.ZCF_SUPPORTED) LInstrD = {1'b1, immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw + end else LInstrD = {1'b1, immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100011}; //c.sd 5'b01000: if (rds1 != 5'b0) - if (immCI[5:0] != 0) LInstrD = {1'b0, immCI, rds1, 3'b000, rds1, 7'b0010011}; // c.addi - else LInstrD = {1'b0, 25'b0, 7'b0010011}; // c.addi with imm = 0 is a HINT, treated as nop - else if (immCI[5:0] == 6'b0) LInstrD = {1'b0, 25'b0, 7'b0010011}; // c.nop - else LInstrD = {1'b0, 25'b0, 7'b0010011}; // c.nop with imm != 0 is a HINT, treated as nop - 5'b01001: if (P.XLEN==32) - LInstrD = {1'b0, immCJ, 5'b00001, 7'b1101111}; // c.jal - else if (rds1 != 5'b0) - LInstrD = {1'b0, immCI, rds1, 3'b000, rds1, 7'b0011011}; // c.addiw - 5'b01010: if (rds1 != 5'b0) LInstrD = {1'b0, immCI, 5'b00000, 3'b000, rds1, 7'b0010011}; // c.li - else LInstrD = {1'b0, 25'b0, 7'b0010011}; // c.li with rd = 0 is a HINT, treated as nop - 5'b01011: if (rds1 == 5'b00010) - LInstrD = {1'b0, immCIASP, rds1, 3'b000, rds1, 7'b0010011}; // c.addi16sp - else if (rds1 != 5'b0) - LInstrD = {1'b0, immCILUI, rds1, 7'b0110111}; // c.lui - else if (immCILUI[5:0] != 0) LInstrD = {1'b0, 25'b0, 7'b0010011}; // c.lui with rd = 0, imm!=0 is a HINT, treated as nop + if (immCI[5:0] != 0) LInstrD = {1'b1, immCI, rds1, 3'b000, rds1, 7'b0010011}; // c.addi + else LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.addi with imm = 0 is a HINT, treated as nop + else if (immCI[5:0] == 6'b0) LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.nop + else LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.nop with imm != 0 is a HINT, treated as nop + 5'b01001: if (P.XLEN==32) LInstrD = {1'b1, immCJ, 5'b00001, 7'b1101111}; // c.jal + else if (rds1 != 5'b0) LInstrD = {1'b1, immCI, rds1, 3'b000, rds1, 7'b0011011}; // c.addiw + 5'b01010: if (rds1 != 5'b0) LInstrD = {1'b1, immCI, 5'b00000, 3'b000, rds1, 7'b0010011}; // c.li + else LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.li with rd = 0 is a HINT, treated as nop + 5'b01011: if (rds1 == 5'b00010) LInstrD = {1'b1, immCIASP, rds1, 3'b000, rds1, 7'b0010011}; // c.addi16sp + else if (rds1 != 5'b0) LInstrD = {1'b1, immCILUI, rds1, 7'b0110111}; // c.lui + else if (immCILUI[5:0] != 0) LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.lui with rd = 0, imm!=0 is a HINT, treated as nop 5'b01100: if (instr16[11:10] == 2'b00) begin - if (P.XLEN == 64 | ~immSH[5]) LInstrD = {1'b0, 6'b000000, immSH, rds1p, 3'b101, rds1p, 7'b0010011}; // c.srli; shamt[5] must be 0 in RV32C + if (P.XLEN > 32 | ~immSH[5]) LInstrD = {1'b1, 6'b000000, immSH, rds1p, 3'b101, rds1p, 7'b0010011}; // c.srli; shamt[5] must be 0 in RV32C end else if (instr16[11:10] == 2'b01) begin - if (P.XLEN == 64 | ~immSH[5]) LInstrD = {1'b0, 6'b010000, immSH, rds1p, 3'b101, rds1p, 7'b0010011}; // c.srai; shamt[5] must be 0 in RV32C - end else if (instr16[11:10] == 2'b10) - LInstrD = {1'b0, immCI, rds1p, 3'b111, rds1p, 7'b0010011}; // c.andi - else if (instr16[12:10] == 3'b011) - if (instr16[6:5] == 2'b00) - LInstrD = {1'b0, 7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0110011}; // c.sub - else if (instr16[6:5] == 2'b01) - LInstrD = {1'b0, 7'b0000000, rs2p, rds1p, 3'b100, rds1p, 7'b0110011}; // c.xor - else if (instr16[6:5] == 2'b10) - LInstrD = {1'b0, 7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011}; // c.or - else // if (instr16[6:5] == 2'b11) - LInstrD = {1'b0, 7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011}; // c.and - else begin // (instr16[12:10] == 3'b111) + if (P.XLEN > 32 | ~immSH[5]) LInstrD = {1'b1, 6'b010000, immSH, rds1p, 3'b101, rds1p, 7'b0010011}; // c.srai; shamt[5] must be 0 in RV32C + end else if (instr16[11:10] == 2'b10) LInstrD = {1'b1, immCI, rds1p, 3'b111, rds1p, 7'b0010011}; // c.andi + else if (instr16[12:10] == 3'b011) begin + if (instr16[6:5] == 2'b00) LInstrD = {1'b1, 7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0110011}; // c.sub + else if (instr16[6:5] == 2'b01) LInstrD = {1'b1, 7'b0000000, rs2p, rds1p, 3'b100, rds1p, 7'b0110011}; // c.xor + else if (instr16[6:5] == 2'b10) LInstrD = {1'b1, 7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011}; // c.or + else LInstrD = {1'b1, 7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011}; // c.and + end else begin // (instr16[12:10] == 3'b111) if (instr16[6:5] == 2'b00 & P.XLEN > 32) - LInstrD = {1'b0, 7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.subw + LInstrD = {1'b1, 7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.subw else if (instr16[6:5] == 2'b01 & P.XLEN > 32) - LInstrD = {1'b0, 7'b0000000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.addw + LInstrD = {1'b1, 7'b0000000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.addw else if (instr16[6:2] == 5'b11000 & P.ZCB_SUPPORTED) - LInstrD = {1'b0, 12'b000011111111, rds1p, 3'b111, rds1p, 7'b0010011}; // c.zext.b = andi rd, rs1, 255 + LInstrD = {1'b1, 12'b000011111111, rds1p, 3'b111, rds1p, 7'b0010011}; // c.zext.b = andi rd, rs1, 255 else if (instr16[6:2] == 5'b11001 & P.ZCB_SUPPORTED & P.ZBB_SUPPORTED) - LInstrD = {1'b0, 12'b011000000100, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.b + LInstrD = {1'b1, 12'b011000000100, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.b else if (instr16[6:2] == 5'b11010 & P.ZCB_SUPPORTED & P.ZBB_SUPPORTED) - LInstrD = {1'b0, 7'b0000100, 5'b00000, rds1p, 3'b100, rds1p, 3'b011, P.XLEN > 32, 3'b011}; // c.zext.h + LInstrD = {1'b1, 7'b0000100, 5'b00000, rds1p, 3'b100, rds1p, 3'b011, P.XLEN > 32, 3'b011}; // c.zext.h else if (instr16[6:2] == 5'b11011 & P.ZCB_SUPPORTED & P.ZBB_SUPPORTED) - LInstrD = {1'b0, 12'b011000000101, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.h + LInstrD = {1'b1, 12'b011000000101, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.h else if (instr16[6:2] == 5'b11101 & P.ZCB_SUPPORTED) - LInstrD = {1'b0, 12'b111111111111, rds1p, 3'b100, rds1p, 7'b0010011}; // c.not = xori + LInstrD = {1'b1, 12'b111111111111, rds1p, 3'b100, rds1p, 7'b0010011}; // c.not = xori else if (instr16[6:2] == 5'b11100 & P.ZCB_SUPPORTED & P.ZBA_SUPPORTED & P.XLEN > 32) - LInstrD = {1'b0, 7'b0000100, 5'b00000, rds1p, 3'b000, rds1p, 7'b0111011}; // c.zext.w = add.uw rd, rs1, 0 + LInstrD = {1'b1, 7'b0000100, 5'b00000, rds1p, 3'b000, rds1p, 7'b0111011}; // c.zext.w = add.uw rd, rs1, 0 else if (instr16[6:5] == 2'b10 & P.ZCB_SUPPORTED & P.ZMMUL_SUPPORTED) - LInstrD = {1'b0, 7'b0000001, rs2p, rds1p, 3'b000, rds1p, 7'b0110011}; // c.mul + LInstrD = {1'b1, 7'b0000001, rs2p, rds1p, 3'b000, rds1p, 7'b0110011}; // c.mul end - 5'b01101: LInstrD = {1'b0, immCJ, 5'b00000, 7'b1101111}; // c.j - 5'b01110: LInstrD = {1'b0, immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011}; // c.beqz - 5'b01111: LInstrD = {1'b0, immCB[11:5], 5'b00000, rs1p, 3'b001, immCB[4:0], 7'b1100011}; // c.bnez + 5'b01101: LInstrD = {1'b1, immCJ, 5'b00000, 7'b1101111}; // c.j + 5'b01110: LInstrD = {1'b1, immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011}; // c.beqz + 5'b01111: LInstrD = {1'b1, immCB[11:5], 5'b00000, rs1p, 3'b001, immCB[4:0], 7'b1100011}; // c.bnez 5'b10000: if (rds1 != 5'b0) begin - if (P.XLEN == 64 | ~immSH[5]) LInstrD = {1'b0, 6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli; shamt[5] must be 0 in RV32C - end else if (immSH != 0) LInstrD = {1'b0, 25'b0, 7'b0010011}; // c.slli with rd = 0, immm != 0 is a HINT, treated as nop + if (P.XLEN > 32 | ~immSH[5]) LInstrD = {1'b1, 6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli; shamt[5] must be 0 in RV32C + end else if (immSH != 0) LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.slli with rd = 0, immm != 0 is a HINT, treated as nop 5'b10001: if (P.ZCD_SUPPORTED) - if (rds1 != 5'b0) LInstrD = {1'b0, immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp - 5'b10010: if (rds1 != 5'b0) LInstrD = {1'b0, immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp + if (rds1 != 5'b0) LInstrD = {1'b1, immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp + 5'b10010: if (rds1 != 5'b0) LInstrD = {1'b1, immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp 5'b10011: if (P.XLEN == 32) begin - if (P.ZCF_SUPPORTED) - LInstrD = {1'b0, immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp - end else if (rds1 != 5'b0) - LInstrD = {1'b0, immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000011}; // c.ldsp + if (P.ZCF_SUPPORTED) LInstrD = {1'b1, immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp + end else if (rds1 != 5'b0) LInstrD = {1'b1, immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000011}; // c.ldsp 5'b10100: if (instr16[12] == 0) if (rs2 == 5'b00000) begin - if (rds1 != 5'b0) LInstrD = {1'b0, 7'b0000000, 5'b00000, rds1, 3'b000, 5'b00000, 7'b1100111}; // c.jr + if (rds1 != 5'b0) LInstrD = {1'b1, 7'b0000000, 5'b00000, rds1, 3'b000, 5'b00000, 7'b1100111}; // c.jr end else - if (rds1 != 5'b0) LInstrD = {1'b0, 7'b0000000, rs2, 5'b00000, 3'b000, rds1, 7'b0110011}; // c.mv - else LInstrD = {1'b0, 25'b0, 7'b0010011}; // c.mv with rd = 0 is a HINT, treated as nop + if (rds1 != 5'b0) LInstrD = {1'b1, 7'b0000000, rs2, 5'b00000, 3'b000, rds1, 7'b0110011}; // c.mv + else LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.mv with rd = 0 is a HINT, treated as nop else if (rs2 == 5'b00000) begin - if (rds1 == 5'b00000) - LInstrD = {1'b0, 12'b1, 5'b00000, 3'b000, 5'b00000, 7'b1110011}; // c.ebreak - else - if (rds1 != 5'b0) LInstrD = {1'b0, 12'b0, rds1, 3'b000, 5'b00001, 7'b1100111}; // c.jalr + if (rds1 == 5'b00000) LInstrD = {1'b1, 12'b1, 5'b00000, 3'b000, 5'b00000, 7'b1110011}; // c.ebreak + else if (rds1 != 5'b0) LInstrD = {1'b1, 12'b0, rds1, 3'b000, 5'b00001, 7'b1100111}; // c.jalr end else - if (rds1 != 0) LInstrD = {1'b0, 7'b0000000, rs2, rds1, 3'b000, rds1, 7'b0110011}; // c.add - else LInstrD = {1'b0, 25'b0, 7'b0010011}; // c.add with rd = 0 is a HINT, treated as nop, even if it is a C.NTL - 5'b10101: if (P.ZCD_SUPPORTED) - LInstrD = {1'b0, immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp - 5'b10110: LInstrD = {1'b0, immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100011}; // c.swsp + if (rds1 != 0) LInstrD = {1'b1, 7'b0000000, rs2, rds1, 3'b000, rds1, 7'b0110011}; // c.add + else LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.add with rd = 0 is a HINT, treated as nop, even if it is a C.NTL + 5'b10101: if (P.ZCD_SUPPORTED) LInstrD = {1'b1, immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp + 5'b10110: LInstrD = {1'b1, immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100011}; // c.swsp 5'b10111: if (P.XLEN==32) begin - if (P.ZCF_SUPPORTED) - LInstrD = {1'b0, immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100111}; // c.fswsp - end else - LInstrD = {1'b0, immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100011}; // c.sdsp + if (P.ZCF_SUPPORTED) LInstrD = {1'b1, immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100111}; // c.fswsp + end else LInstrD = {1'b1, immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100011}; // c.sdsp default: ; // illegal instruction endcase end // extract instruction and illegal from LInstrD - assign {IllegalCompInstrD, InstrD} = LInstrD; + assign {LegalCompInstrD, InstrD} = LInstrD; + assign IllegalCompInstrD = ~LegalCompInstrD; endmodule From c64c12dc6c469c0349a7e20fc4f11e7f73eeb6db Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 18 Jul 2024 22:48:32 -0700 Subject: [PATCH 065/219] Detect illegal compressed immediates, hints --- src/ifu/decompress.sv | 118 +++++++++++++++++++++--------------------- 1 file changed, 60 insertions(+), 58 deletions(-) diff --git a/src/ifu/decompress.sv b/src/ifu/decompress.sv index 2b0caf269..798993d78 100644 --- a/src/ifu/decompress.sv +++ b/src/ifu/decompress.sv @@ -64,10 +64,10 @@ module decompress import cvw::*; #(parameter cvw_t P) ( assign immCJ = {instr16[12], instr16[8], instr16[10:9], instr16[6], instr16[7], instr16[2], instr16[11], instr16[5:3], {9{instr16[12]}}}; assign immCB = {{4{instr16[12]}}, instr16[6:5], instr16[2], instr16[11:10], instr16[4:3], instr16[12]}; assign immCI = {{7{instr16[12]}}, instr16[6:2]}; - assign immCILUI = {{15{instr16[12]}}, instr16[6:2]}; - assign immCIASP = {{3{instr16[12]}}, instr16[4:3], instr16[5], instr16[2], instr16[6], 4'b0000}; + assign immCILUI = {{15{instr16[12]}}, instr16[6:2]}; // c.lui + assign immCIASP = {{3{instr16[12]}}, instr16[4:3], instr16[5], instr16[2], instr16[6], 4'b0000}; // c.addi16sp assign immCIW = {2'b00, instr16[10:7], instr16[12:11], instr16[5], instr16[6], 2'b00}; - assign immSH = {instr16[12], instr16[6:2]}; + assign immSH = {instr16[12], instr16[6:2]}; // c. shift instructions: c.srli, c.srai, c.slli // only for RV128 // assign immCILSPQ = {2{instr16[5]}, instr16[5:2], instr16[12], instr16[6], 4'b0000}; @@ -81,97 +81,99 @@ module decompress import cvw::*; #(parameter cvw_t P) ( end else begin // convert compressed instruction into uncompressed LInstrD = {1'b0, 16'b0, instr16}; // if a legal instruction is not decoded, default to illegal and preserve 16-bit value for mtval case ({op, instr16[15:13]}) - 5'b00000: if (immCIW != 0) LInstrD = {1'b1, immCIW, 5'b00010, 3'b000, rdp, 7'b0010011}; // c.addi4spn - 5'b00001: if (P.ZCD_SUPPORTED) LInstrD = {1'b1, immCLD, rs1p, 3'b011, rdp, 7'b0000111}; // c.fld - 5'b00010: LInstrD = {1'b1, immCL, rs1p, 3'b010, rdp, 7'b0000011}; // c.lw + 5'b00000: if (immCIW != 0) LInstrD = {1'b1, immCIW, 5'b00010, 3'b000, rdp, 7'b0010011}; // c.addi4spn + 5'b00001: if (P.ZCD_SUPPORTED) LInstrD = {1'b1, immCLD, rs1p, 3'b011, rdp, 7'b0000111}; // c.fld + 5'b00010: LInstrD = {1'b1, immCL, rs1p, 3'b010, rdp, 7'b0000011}; // c.lw 5'b00011: if (P.XLEN==32) begin - if (P.ZCF_SUPPORTED) LInstrD = {1'b1, immCL, rs1p, 3'b010, rdp, 7'b0000111}; // c.flw - end else LInstrD = {1'b1, immCLD, rs1p, 3'b011, rdp, 7'b0000011}; // c.ld + if (P.ZCF_SUPPORTED) LInstrD = {1'b1, immCL, rs1p, 3'b010, rdp, 7'b0000111}; // c.flw + end else LInstrD = {1'b1, immCLD, rs1p, 3'b011, rdp, 7'b0000011}; // c.ld 5'b00100: if (P.ZCB_SUPPORTED) - if (instr16[12:10] == 3'b000) LInstrD = {1'b1, 10'b0, instr16[5], instr16[6], rs1p, 3'b100, rdp, 7'b0000011}; // c.lbu + if (instr16[12:10] == 3'b000) LInstrD = {1'b1, 10'b0, instr16[5], instr16[6], rs1p, 3'b100, rdp, 7'b0000011}; // c.lbu else if (instr16[12:10] == 3'b001) begin - if (instr16[6]) LInstrD = {1'b1, 10'b0, instr16[5], 1'b0, rs1p, 3'b001, rdp, 7'b0000011}; // c.lh - else LInstrD = {1'b1, 10'b0, instr16[5], 1'b0, rs1p, 3'b101, rdp, 7'b0000011}; // c.lhu + if (instr16[6]) LInstrD = {1'b1, 10'b0, instr16[5], 1'b0, rs1p, 3'b001, rdp, 7'b0000011}; // c.lh + else LInstrD = {1'b1, 10'b0, instr16[5], 1'b0, rs1p, 3'b101, rdp, 7'b0000011}; // c.lhu end else if (instr16[12:10] == 3'b010) LInstrD = {1'b1, 7'b0, rs2p, rs1p, 3'b000, 3'b000, instr16[5], instr16[6], 7'b0100011}; // c.sb else if (instr16[12:10] == 3'b011 & instr16[6] == 1'b0) LInstrD = {1'b1, 7'b0, rs2p, rs1p, 3'b001, 3'b000, instr16[5], 1'b0, 7'b0100011}; // c.sh - 5'b00101: if (P.ZCD_SUPPORTED) LInstrD = {1'b1, immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100111}; // c.fsd - 5'b00110: LInstrD = {1'b1, immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100011}; // c.sw + 5'b00101: if (P.ZCD_SUPPORTED) LInstrD = {1'b1, immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100111}; // c.fsd + 5'b00110: LInstrD = {1'b1, immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100011}; // c.sw 5'b00111: if (P.XLEN==32) begin - if (P.ZCF_SUPPORTED) LInstrD = {1'b1, immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw - end else LInstrD = {1'b1, immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100011}; //c.sd + if (P.ZCF_SUPPORTED) LInstrD = {1'b1, immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw + end else LInstrD = {1'b1, immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100011}; // c.sd 5'b01000: if (rds1 != 5'b0) - if (immCI[5:0] != 0) LInstrD = {1'b1, immCI, rds1, 3'b000, rds1, 7'b0010011}; // c.addi - else LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.addi with imm = 0 is a HINT, treated as nop - else if (immCI[5:0] == 6'b0) LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.nop - else LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.nop with imm != 0 is a HINT, treated as nop - 5'b01001: if (P.XLEN==32) LInstrD = {1'b1, immCJ, 5'b00001, 7'b1101111}; // c.jal - else if (rds1 != 5'b0) LInstrD = {1'b1, immCI, rds1, 3'b000, rds1, 7'b0011011}; // c.addiw - 5'b01010: if (rds1 != 5'b0) LInstrD = {1'b1, immCI, 5'b00000, 3'b000, rds1, 7'b0010011}; // c.li - else LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.li with rd = 0 is a HINT, treated as nop - 5'b01011: if (rds1 == 5'b00010) LInstrD = {1'b1, immCIASP, rds1, 3'b000, rds1, 7'b0010011}; // c.addi16sp - else if (rds1 != 5'b0) LInstrD = {1'b1, immCILUI, rds1, 7'b0110111}; // c.lui - else if (immCILUI[5:0] != 0) LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.lui with rd = 0, imm!=0 is a HINT, treated as nop + if (immCI[5:0] != 0) LInstrD = {1'b1, immCI, rds1, 3'b000, rds1, 7'b0010011}; // c.addi + else LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.addi with imm = 0 is a HINT, treated as nop + else if (immCI[5:0] == 6'b0) LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.nop = addi x0, x0, 0 + else LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.nop with imm != 0 is a HINT, treated as nop + 5'b01001: if (P.XLEN==32) LInstrD = {1'b1, immCJ, 5'b00001, 7'b1101111}; // c.jal + else if (rds1 != 5'b0) LInstrD = {1'b1, immCI, rds1, 3'b000, rds1, 7'b0011011}; // c.addiw + 5'b01010: if (rds1 != 5'b0) LInstrD = {1'b1, immCI, 5'b00000, 3'b000, rds1, 7'b0010011}; // c.li + else LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.li with rd = 0 is a HINT, treated as nop + 5'b01011: if (rds1 == 5'b00010) begin + if (immCIASP[9:4] != 6'b0) LInstrD = {1'b1, immCIASP, rds1, 3'b000, rds1, 7'b0010011}; // c.addi16sp + end else if (immCILUI[5:0] != 0) + if (rds1 != 5'b0) LInstrD = {1'b1, immCILUI, rds1, 7'b0110111}; // c.lui + else LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.lui with rd = 0, imm!=0 is a HINT, treated as nop 5'b01100: if (instr16[11:10] == 2'b00) begin - if (P.XLEN > 32 | ~immSH[5]) LInstrD = {1'b1, 6'b000000, immSH, rds1p, 3'b101, rds1p, 7'b0010011}; // c.srli; shamt[5] must be 0 in RV32C + if (P.XLEN > 32 | ~immSH[5]) LInstrD = {1'b1, 6'b000000, immSH, rds1p, 3'b101, rds1p, 7'b0010011}; // c.srli; shamt[5] must be 0 in RV32C end else if (instr16[11:10] == 2'b01) begin - if (P.XLEN > 32 | ~immSH[5]) LInstrD = {1'b1, 6'b010000, immSH, rds1p, 3'b101, rds1p, 7'b0010011}; // c.srai; shamt[5] must be 0 in RV32C - end else if (instr16[11:10] == 2'b10) LInstrD = {1'b1, immCI, rds1p, 3'b111, rds1p, 7'b0010011}; // c.andi + if (P.XLEN > 32 | ~immSH[5]) LInstrD = {1'b1, 6'b010000, immSH, rds1p, 3'b101, rds1p, 7'b0010011}; // c.srai; shamt[5] must be 0 in RV32C + end else if (instr16[11:10] == 2'b10) LInstrD = {1'b1, immCI, rds1p, 3'b111, rds1p, 7'b0010011}; // c.andi else if (instr16[12:10] == 3'b011) begin - if (instr16[6:5] == 2'b00) LInstrD = {1'b1, 7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0110011}; // c.sub - else if (instr16[6:5] == 2'b01) LInstrD = {1'b1, 7'b0000000, rs2p, rds1p, 3'b100, rds1p, 7'b0110011}; // c.xor - else if (instr16[6:5] == 2'b10) LInstrD = {1'b1, 7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011}; // c.or - else LInstrD = {1'b1, 7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011}; // c.and + if (instr16[6:5] == 2'b00) LInstrD = {1'b1, 7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0110011}; // c.sub + else if (instr16[6:5] == 2'b01) LInstrD = {1'b1, 7'b0000000, rs2p, rds1p, 3'b100, rds1p, 7'b0110011}; // c.xor + else if (instr16[6:5] == 2'b10) LInstrD = {1'b1, 7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011}; // c.or + else LInstrD = {1'b1, 7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011}; // c.and end else begin // (instr16[12:10] == 3'b111) if (instr16[6:5] == 2'b00 & P.XLEN > 32) - LInstrD = {1'b1, 7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.subw + LInstrD = {1'b1, 7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.subw else if (instr16[6:5] == 2'b01 & P.XLEN > 32) - LInstrD = {1'b1, 7'b0000000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.addw + LInstrD = {1'b1, 7'b0000000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.addw else if (instr16[6:2] == 5'b11000 & P.ZCB_SUPPORTED) - LInstrD = {1'b1, 12'b000011111111, rds1p, 3'b111, rds1p, 7'b0010011}; // c.zext.b = andi rd, rs1, 255 + LInstrD = {1'b1, 12'b000011111111, rds1p, 3'b111, rds1p, 7'b0010011}; // c.zext.b = andi rd, rs1, 255 else if (instr16[6:2] == 5'b11001 & P.ZCB_SUPPORTED & P.ZBB_SUPPORTED) - LInstrD = {1'b1, 12'b011000000100, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.b + LInstrD = {1'b1, 12'b011000000100, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.b else if (instr16[6:2] == 5'b11010 & P.ZCB_SUPPORTED & P.ZBB_SUPPORTED) LInstrD = {1'b1, 7'b0000100, 5'b00000, rds1p, 3'b100, rds1p, 3'b011, P.XLEN > 32, 3'b011}; // c.zext.h else if (instr16[6:2] == 5'b11011 & P.ZCB_SUPPORTED & P.ZBB_SUPPORTED) - LInstrD = {1'b1, 12'b011000000101, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.h + LInstrD = {1'b1, 12'b011000000101, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.h else if (instr16[6:2] == 5'b11101 & P.ZCB_SUPPORTED) - LInstrD = {1'b1, 12'b111111111111, rds1p, 3'b100, rds1p, 7'b0010011}; // c.not = xori + LInstrD = {1'b1, 12'b111111111111, rds1p, 3'b100, rds1p, 7'b0010011}; // c.not = xori else if (instr16[6:2] == 5'b11100 & P.ZCB_SUPPORTED & P.ZBA_SUPPORTED & P.XLEN > 32) - LInstrD = {1'b1, 7'b0000100, 5'b00000, rds1p, 3'b000, rds1p, 7'b0111011}; // c.zext.w = add.uw rd, rs1, 0 + LInstrD = {1'b1, 7'b0000100, 5'b00000, rds1p, 3'b000, rds1p, 7'b0111011}; // c.zext.w = add.uw rd, rs1, 0 else if (instr16[6:5] == 2'b10 & P.ZCB_SUPPORTED & P.ZMMUL_SUPPORTED) - LInstrD = {1'b1, 7'b0000001, rs2p, rds1p, 3'b000, rds1p, 7'b0110011}; // c.mul + LInstrD = {1'b1, 7'b0000001, rs2p, rds1p, 3'b000, rds1p, 7'b0110011}; // c.mul end 5'b01101: LInstrD = {1'b1, immCJ, 5'b00000, 7'b1101111}; // c.j - 5'b01110: LInstrD = {1'b1, immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011}; // c.beqz - 5'b01111: LInstrD = {1'b1, immCB[11:5], 5'b00000, rs1p, 3'b001, immCB[4:0], 7'b1100011}; // c.bnez + 5'b01110: LInstrD = {1'b1, immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011}; // c.beqz + 5'b01111: LInstrD = {1'b1, immCB[11:5], 5'b00000, rs1p, 3'b001, immCB[4:0], 7'b1100011}; // c.bnez 5'b10000: if (rds1 != 5'b0) begin - if (P.XLEN > 32 | ~immSH[5]) LInstrD = {1'b1, 6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli; shamt[5] must be 0 in RV32C - end else if (immSH != 0) LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.slli with rd = 0, immm != 0 is a HINT, treated as nop + if (P.XLEN > 32 | ~immSH[5]) LInstrD = {1'b1, 6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli; shamt[5] must be 0 in RV32C + end else if (immSH != 0) LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.slli with rd = 0, immm != 0 is a HINT, treated as nop 5'b10001: if (P.ZCD_SUPPORTED) - if (rds1 != 5'b0) LInstrD = {1'b1, immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp - 5'b10010: if (rds1 != 5'b0) LInstrD = {1'b1, immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp + if (rds1 != 5'b0) LInstrD = {1'b1, immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp + 5'b10010: if (rds1 != 5'b0) LInstrD = {1'b1, immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp 5'b10011: if (P.XLEN == 32) begin - if (P.ZCF_SUPPORTED) LInstrD = {1'b1, immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp - end else if (rds1 != 5'b0) LInstrD = {1'b1, immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000011}; // c.ldsp + if (P.ZCF_SUPPORTED) LInstrD = {1'b1, immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp + end else if (rds1 != 5'b0) LInstrD = {1'b1, immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000011}; // c.ldsp 5'b10100: if (instr16[12] == 0) if (rs2 == 5'b00000) begin - if (rds1 != 5'b0) LInstrD = {1'b1, 7'b0000000, 5'b00000, rds1, 3'b000, 5'b00000, 7'b1100111}; // c.jr + if (rds1 != 5'b0) LInstrD = {1'b1, 7'b0000000, 5'b00000, rds1, 3'b000, 5'b00000, 7'b1100111}; // c.jr end else - if (rds1 != 5'b0) LInstrD = {1'b1, 7'b0000000, rs2, 5'b00000, 3'b000, rds1, 7'b0110011}; // c.mv - else LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.mv with rd = 0 is a HINT, treated as nop + if (rds1 != 5'b0) LInstrD = {1'b1, 7'b0000000, rs2, 5'b00000, 3'b000, rds1, 7'b0110011}; // c.mv + else LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.mv with rd = 0 is a HINT, treated as nop else if (rs2 == 5'b00000) begin - if (rds1 == 5'b00000) LInstrD = {1'b1, 12'b1, 5'b00000, 3'b000, 5'b00000, 7'b1110011}; // c.ebreak - else if (rds1 != 5'b0) LInstrD = {1'b1, 12'b0, rds1, 3'b000, 5'b00001, 7'b1100111}; // c.jalr + if (rds1 == 5'b00000) LInstrD = {1'b1, 12'b1, 5'b00000, 3'b000, 5'b00000, 7'b1110011}; // c.ebreak + else if (rds1 != 5'b0) LInstrD = {1'b1, 12'b0, rds1, 3'b000, 5'b00001, 7'b1100111}; // c.jalr end else - if (rds1 != 0) LInstrD = {1'b1, 7'b0000000, rs2, rds1, 3'b000, rds1, 7'b0110011}; // c.add - else LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.add with rd = 0 is a HINT, treated as nop, even if it is a C.NTL + if (rds1 != 0) LInstrD = {1'b1, 7'b0000000, rs2, rds1, 3'b000, rds1, 7'b0110011}; // c.add + else LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.add with rd = 0 is a HINT, treated as nop, even if it is a C.NTL 5'b10101: if (P.ZCD_SUPPORTED) LInstrD = {1'b1, immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp - 5'b10110: LInstrD = {1'b1, immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100011}; // c.swsp + 5'b10110: LInstrD = {1'b1, immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100011}; // c.swsp 5'b10111: if (P.XLEN==32) begin - if (P.ZCF_SUPPORTED) LInstrD = {1'b1, immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100111}; // c.fswsp + if (P.ZCF_SUPPORTED) LInstrD = {1'b1, immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100111}; // c.fswsp end else LInstrD = {1'b1, immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100011}; // c.sdsp default: ; // illegal instruction endcase From 34e89e842cc0cda695542b376e8bbcfd72e53eb0 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Fri, 19 Jul 2024 11:35:12 -0500 Subject: [PATCH 066/219] Added initial spi code to fpga/zsbl --- fpga/zsbl/spi.c | 24 ++++++++++++++++++++++++ fpga/zsbl/spi.h | 45 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) create mode 100644 fpga/zsbl/spi.c create mode 100644 fpga/zsbl/spi.h diff --git a/fpga/zsbl/spi.c b/fpga/zsbl/spi.c new file mode 100644 index 000000000..4c3885fd0 --- /dev/null +++ b/fpga/zsbl/spi.c @@ -0,0 +1,24 @@ +#include "spi.h" + +void write_reg(uintptr_t addr, uint32_t value) { + volatile uint32_t * loc = (volatile uint32_t *) addr; + *loc = value; +} + +// Initialize Sifive FU540 based SPI Controller +void spi_init() { + // Disable interrupts by default + // write_reg(SPI_IE, 0); + + write_reg(SPI_TXMARK, 1); + write_reg(SPI_RXMARK, 0); + + write_reg(SPI_DELAY0, + SIFIVE_SPI_DELAY0_CSSCK(1) | + SIFIVE_SPI_DELAY0_SCKCS(1)); + + write_reg(SPI_DELAY1, + SIFIVE_SPI_DELAY1_INTERCS(1) | + SIFIVE_SPI_DELAY1_INTERXFR(0)); +} + diff --git a/fpga/zsbl/spi.h b/fpga/zsbl/spi.h new file mode 100644 index 000000000..97f3d58c3 --- /dev/null +++ b/fpga/zsbl/spi.h @@ -0,0 +1,45 @@ +#pragma once +#ifndef SPI_HEADER +#define SPI_HEADER + +#include + +/* register offsets */ +#define SPI_SCKDIV 0x00 /* Serial clock divisor */ +#define SPI_SCKMODE 0x04 /* Serial clock mode */ +#define SPI_CSID 0x10 /* Chip select ID */ +#define SPI_CSDEF 0x14 /* Chip select default */ +#define SPI_CSMODE 0x18 /* Chip select mode */ +#define SPI_DELAY0 0x28 /* Delay control 0 */ +#define SPI_DELAY1 0x2c /* Delay control 1 */ +#define SPI_FMT 0x40 /* Frame format */ +#define SPI_TXDATA 0x48 /* Tx FIFO data */ +#define SPI_RXDATA 0x4c /* Rx FIFO data */ +#define SPI_TXMARK 0x50 /* Tx FIFO [<35;39;29Mwatermark */ +#define SPI_RXMARK 0x54 /* Rx FIFO watermark */ + +/* Non-implemented +#define SPI_FCTRL 0x60 // SPI flash interface control +#define SPI_FFMT 0x64 // SPI flash instruction format +*/ +#define SPI_IE 0x70 /* Interrupt Enable Register */ +#define SPI_IP 0x74 /* Interrupt Pendings Register */ + +/* delay0 bits */ +#define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x)) +#define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU +#define SIFIVE_SPI_DELAY0_SCKCS(x) ((u32)(x) << 16) +#define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16) + +/* delay1 bits */ +#define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) +#define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU +#define SIFIVE_SPI_DELAY1_INTERXFR(x) ((u32)(x) << 16) +#define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16) + +void write_reg(uintptr_t addr, uint32_t value); +uint32_t read_reg(uintptr_t addr); +void spi_send_byte(uint8_t byte); +void spi_init(); + +#endif From e30691d5e2fa36e4275f2a891b01989a901ebbb8 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 18 Jul 2024 22:01:17 -0700 Subject: [PATCH 067/219] Add additional packages --- bin/wally-package-install.sh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index 39cdd76c1..4c8893b4f 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -48,7 +48,7 @@ fi if [ "$FAMILY" = rhel ]; then PACKAGE_MANAGER="dnf" UPDATE_COMMAND="sudo dnf update -y" - GENERAL_PACKAGES="git make cmake python3.12 python3-pip curl wget ftp tar pkgconf-pkg-config dialog mutt ssmtp" + GENERAL_PACKAGES="which rsync git make cmake python3.12 python3-pip curl wget ftp tar pkgconf-pkg-config dialog mutt ssmtp" GNU_PACKAGES="autoconf automake libmpc-devel mpfr-devel gmp-devel gawk bison flex texinfo gperf libtool patchutils bc gcc gcc-c++ zlib-devel expat-devel libslirp-devel" QEMU_PACKAGES="glib2-devel libfdt-devel pixman-devel bzip2 ninja-build" SPIKE_PACKAGES="dtc boost-regex boost-system" @@ -64,11 +64,11 @@ if [ "$FAMILY" = rhel ]; then elif [ "$FAMILY" = ubuntu ]; then PACKAGE_MANAGER=apt UPDATE_COMMAND="sudo apt update -y && sudo apt upgrade -y" - GENERAL_PACKAGES="git make cmake python3 python3-pip python3-venv curl wget ftp tar pkg-config dialog mutt ssmtp" + GENERAL_PACKAGES="rsync git make cmake python3 python3-pip python3-venv curl wget ftp tar pkg-config dialog mutt ssmtp" GNU_PACKAGES="autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat1-dev ninja-build libglib2.0-dev libslirp-dev" QEMU_PACKAGES="libfdt-dev libpixman-1-dev" SPIKE_PACKAGES="device-tree-compiler libboost-regex-dev libboost-system-dev" - VERILATOR_PACKAGES="help2man perl g++ clang ccache libgoogle-perftools-dev numactl perl-doc libfl2 libfl-dev zlib1g" + VERILATOR_PACKAGES="help2man perl g++ clang ccache libunwind-dev libgoogle-perftools-dev numactl perl-doc libfl2 libfl-dev zlib1g" SAIL_PACKAGES="opam z3" BUILDROOT_PACKAGES="ncurses-base ncurses-bin libncurses-dev gfortran" # Extra packages not availale in Ubuntu 20.04, nice for Verilator From 954247af92f6fd9e6a89aaf62ed42dcff72359e0 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 18 Jul 2024 22:05:56 -0700 Subject: [PATCH 068/219] Update setup scripts to be more verbose about errors --- bin/wally-tool-chain-install.sh | 7 ++++--- setup.csh | 10 +++++++--- setup.sh | 10 +++++++--- site-setup.csh | 7 ++++++- site-setup.sh | 9 ++++++++- 5 files changed, 32 insertions(+), 11 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 8648a59b3..8ffa67ed7 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -316,7 +316,7 @@ fi # but a binary release of it should be available soon, removing the need to use opam. section_header "Installing/Updating Sail Compiler" STATUS="Sail Compiler" -OPAMROOTISOK=1 # Silence warnings about running opam as root +export OPAMROOTISOK=1 # Silence warnings about running opam as root cd "$RISCV" opam init -y --disable-sandboxing opam update -y @@ -330,7 +330,7 @@ echo -e "${SUCCESS_COLOR}Sail Compiler successfully installed/updated${ENDC}" section_header "Installing/Updating RISC-V Sail Model" STATUS="RISC-V Sail Model" if [[ ((! -e sail-riscv) && ($(git clone https://github.com/riscv/sail-riscv.git) || true)) || ($(cd sail-riscv; git fetch; git rev-parse HEAD) != $(cd sail-riscv; git rev-parse origin/master)) || (! -e $RISCV/bin/riscv_sim_RV32) ]]; then - eval $(opam config env) + eval "$(opam config env)" cd sail-riscv git reset --hard && git clean -f && git checkout master && git pull export OPAMCLI=2.0 # Sail is not compatible with opam 2.1 as of 4/16/24 @@ -388,7 +388,8 @@ if [ ! -e "${RISCV}"/site-setup.sh ]; then fi echo -e "${SUCCESS_COLOR}Site setup script successfully downloaded${ENDC}" else - echo -e "${OK_COLOR}Site setup script already exists. Not checking for updates to avoid overwritng modifications${ENDC}" + echo -e "${OK_COLOR}Site setup script already exists. Not checking for updates to avoid overwritng modifications." + echo -e "You may need to manually update it if there were changes upstream.${ENDC}" fi echo -e "${SUCCESS_COLOR}${BOLD}\n\nINSTALLATION SUCCESSFUL\n\n${ENDC}" diff --git a/setup.csh b/setup.csh index da617202c..e84c2362c 100755 --- a/setup.csh +++ b/setup.csh @@ -11,9 +11,9 @@ alias extend 'if (-d \!:2) if ("$\!:1" \!~ *"\!:2"*) setenv \!:1 ${\!:1}:\!:2;ec alias prepend 'if (-d \!:2) if ("$\!:1" \!~ *"\!:2"*) setenv \!:1 "\!:2":${\!:1};echo Added \!:2 to \!:1' # Path to RISC-V Tools -if ( -e /opt/riscv ) then +if ( -d /opt/riscv ) then setenv RISCV /opt/riscv -else if ( -e ~/riscv ) then +else if ( -d ~/riscv ) then setenv RISCV ~/riscv else # set the $RISCV directory here and remove the subsequent two lines @@ -30,6 +30,10 @@ echo '$WALLY set to ' ${WALLY} extend PATH $WALLY/bin # load site licenses and tool locations -source $RISCV/site-setup.csh +if ( -e "${RISCV}"/site-setup.csh ) then + source $RISCV/site-setup.csh +else + echo "site-setup.csh not found in \$RISCV directory. Rerun wally-toolchain-install.sh to automatically download it." +fi echo "setup done" diff --git a/setup.sh b/setup.sh index d8b511c6f..7d511588f 100644 --- a/setup.sh +++ b/setup.sh @@ -14,9 +14,9 @@ echo "Executing Wally setup.sh" # Path to RISC-V Tools -if [ -e /opt/riscv ]; then +if [ -d /opt/riscv ]; then export RISCV=/opt/riscv -elif [ -e ~/riscv ]; then +elif [ -d ~/riscv ]; then export RISCV=~/riscv else # set the $RISCV directory here and remove the subsequent two lines @@ -34,6 +34,10 @@ echo \$WALLY set to "${WALLY}" export PATH=$WALLY/bin:$PATH # load site licenses and tool locations -source "${RISCV}"/site-setup.sh +if [ -e "${RISCV}"/site-setup.sh ]; then + source "${RISCV}"/site-setup.sh +else + echo "site-setup.sh not found in \$RISCV directory. Rerun wally-toolchain-install.sh to automatically download it." +fi echo "setup done" diff --git a/site-setup.csh b/site-setup.csh index 428ebb30e..6ee000438 100644 --- a/site-setup.csh +++ b/site-setup.csh @@ -25,7 +25,12 @@ extend LD_LIBRARY_PATH $RISCV/lib64 extend PATH $RISCV/bin # Activate riscv-python Virtual Environment -source "$RISCV"/riscv-python/bin/activate.csh +if ( -e "$RISCV"/riscv-python/bin/activate ) then + source "$RISCV"/riscv-python/bin/activate.csh +else + echo "Python virtual environment not found. Rerun wally-toolchain-install.sh to automatically create it." + exit 1 +fi # environment variables needed for RISCV-DV setenv RISCV_GCC `which riscv64-unknown-elf-gcc` # Copy this as it is diff --git a/site-setup.sh b/site-setup.sh index 4750e039d..768fc6013 100755 --- a/site-setup.sh +++ b/site-setup.sh @@ -27,7 +27,14 @@ export LD_LIBRARY_PATH=$RISCV/lib:$RISCV/lib64:$LD_LIBRARY_PATH export PATH=$PATH:$RISCV/bin # Activate riscv-python Virtual Environment -source "$RISCV"/riscv-python/bin/activate + +if [ -e "$RISCV"/riscv-python/bin/activate ]; then + source "$RISCV"/riscv-python/bin/activate +else + echo "Python virtual environment not found. Rerun wally-toolchain-install.sh to automatically create it." + exit 1 +fi + # environment variables needed for RISCV-DV export RISCV_GCC=$(which riscv64-unknown-elf-gcc) # Copy this as it is From 53b2a51c8967d29a84d83f66a90c72a3b262d590 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Fri, 19 Jul 2024 12:30:32 -0500 Subject: [PATCH 069/219] Added tentative spi_send_byte function. --- fpga/zsbl/spi.c | 27 +++++++++++++++++++++++++++ fpga/zsbl/spi.h | 2 +- 2 files changed, 28 insertions(+), 1 deletion(-) diff --git a/fpga/zsbl/spi.c b/fpga/zsbl/spi.c index 4c3885fd0..1400b8881 100644 --- a/fpga/zsbl/spi.c +++ b/fpga/zsbl/spi.c @@ -5,6 +5,10 @@ void write_reg(uintptr_t addr, uint32_t value) { *loc = value; } +void read_red(uintptr_t addr) { + return *(volatile uint32_t *) addr; +} + // Initialize Sifive FU540 based SPI Controller void spi_init() { // Disable interrupts by default @@ -22,3 +26,26 @@ void spi_init() { SIFIVE_SPI_DELAY1_INTERXFR(0)); } +// Sends and receives a single byte +uint8_t spi_send_byte(uint8_t byte) { + // Write byte to transfer fifo + write_reg(SPI_TXDATA, byte); + + /* Not sure how necessary this is. Will keep commented for now. + // Wait a decent amount of time for data to send + for (int i = 0; i < 100; i++) { + __asm__ volatile("nop"); + } + */ + + // Wait for data to come into receive fifo + while (read_reg(SPI_IP) != 2) {} + + // Read received data + result = read_reg(SPI_RXDATA); + + // Return result + return result; +} + + diff --git a/fpga/zsbl/spi.h b/fpga/zsbl/spi.h index 97f3d58c3..2bd2003c5 100644 --- a/fpga/zsbl/spi.h +++ b/fpga/zsbl/spi.h @@ -39,7 +39,7 @@ void write_reg(uintptr_t addr, uint32_t value); uint32_t read_reg(uintptr_t addr); -void spi_send_byte(uint8_t byte); +uint8_t spi_send_byte(uint8_t byte); void spi_init(); #endif From 6e4d6b7c078874843992c1e62c66222c82025e64 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 18 Jul 2024 22:32:03 -0700 Subject: [PATCH 070/219] Refactor git repo checks to use a function --- bin/wally-tool-chain-install.sh | 37 +++++++++++++++++++++++---------- 1 file changed, 26 insertions(+), 11 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 8ffa67ed7..99087a559 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -61,6 +61,20 @@ section_header() { printf "%$(tput cols)s${ENDC}" | tr ' ' '#' } +# Check if a git repository exists, is up to date, and has been installed +# Clones the repository if it doesn't exist +git_check() { + local repo=$1 + local url=$2 + local check=$3 + local branch="${4:-master}" + if [[ ((! -e $repo) && ($(git clone "$url") || true)) || ($(cd "$repo"; git fetch; git rev-parse HEAD) != $(cd repo; git rev-parse origin/"$branch")) || (! -e $check) ]]; then + return 1 + else + return 0 + fi +} + set -e # break on error trap error ERR # run error handler on error STATUS="setup" # keep track of what part of the installation is running for error messages @@ -199,7 +213,7 @@ fi section_header "Installing/Updating RISC-V GNU Toolchain" STATUS="RISC-V GNU Toolchain" cd "$RISCV" -if [[ ((! -e riscv-gnu-toolchain) && ($(git clone https://github.com/riscv/riscv-gnu-toolchain) || true)) || ($(cd riscv-gnu-toolchain; git fetch; git rev-parse HEAD) != $(cd riscv-gnu-toolchain; git rev-parse origin/master)) || (! -e $RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2) ]]; then +if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2"; then cd riscv-gnu-toolchain git reset --hard && git clean -f && git checkout master && git pull git pull @@ -222,7 +236,7 @@ section_header "Installing/Updating elf2hex" STATUS="elf2hex" cd "$RISCV" export PATH=$RISCV/bin:$PATH -if [[ ((! -e elf2hex) && ($(git clone https://github.com/sifive/elf2hex.git) || true)) || ($(cd elf2hex; git fetch; git rev-parse HEAD) != $(cd elf2hex; git rev-parse origin/master)) || (! -e $RISCV/bin/riscv64-unknown-elf-elf2bin) ]]; then +if git_check "elf2hex" "https://github.com/sifive/elf2hex.git" "$RISCV/bin/riscv64-unknown-elf-elf2bin"; then cd elf2hex git reset --hard && git clean -f && git checkout master && git pull autoreconf -i @@ -240,9 +254,10 @@ fi section_header "Installing/Updating QEMU" STATUS="QEMU" cd "$RISCV" -if [[ ((! -e qemu) && ($(git clone --recurse-submodules -j ${NUM_THREADS} https://github.com/qemu/qemu) || true)) || ($(cd qemu; git fetch; git rev-parse HEAD) != $(cd qemu; git rev-parse origin/master)) || (! -e $RISCV/include/qemu-plugin.h) ]]; then +if git_check "qemu" "https://github.com/qemu/qemu" "$RISCV/include/qemu-plugin.h"; then cd qemu git reset --hard && git clean -f && git checkout master && git pull --recurse-submodules -j ${NUM_THREADS} + submodule update --init --recursive ./configure --target-list=riscv64-softmmu --prefix="$RISCV" make -j ${NUM_THREADS} make install @@ -257,7 +272,7 @@ fi section_header "Installing/Updating SPIKE" STATUS="SPIKE" cd "$RISCV" -if [[ ((! -e riscv-isa-sim) && ($(git clone https://github.com/riscv-software-src/riscv-isa-sim) || true)) || ($(cd riscv-isa-sim; git fetch; git rev-parse HEAD) != $(cd riscv-isa-sim; git rev-parse origin/master)) || (! -e $RISCV/lib/pkgconfig/riscv-riscv.pc) ]]; then +if git_check "riscv-isa-sim" "https://github.com/riscv-software-src/riscv-isa-sim" "$RISCV/lib/pkgconfig/riscv-riscv.pc"; then cd riscv-isa-sim git reset --hard && git clean -f && git checkout master && git pull mkdir -p build @@ -278,13 +293,13 @@ fi section_header "Installing/Updating Verilator" STATUS="Verilator" cd "$RISCV" -if [[ ((! -e verilator) && ($(git clone https://github.com/verilator/verilator) || true)) || ($(cd verilator; git fetch; git rev-parse HEAD) != $(cd verilator; git rev-parse origin/master)) || (! -e $RISCV/share/pkgconfig/verilator.pc) ]]; then - unset VERILATOR_ROOT # For bash +if git_check "verilator" "https://github.com/verilator/verilator" "$RISCV/share/pkgconfig/verilator.pc"; then + unset VERILATOR_ROOT cd verilator git reset --hard && git clean -f && git checkout master && git pull - autoconf # Create ./configure script - ./configure --prefix="$RISCV" # Configure and create Makefile - make -j ${NUM_THREADS} # Build Verilator itself (if error, try just 'make') + autoconf + ./configure --prefix="$RISCV" + make -j ${NUM_THREADS} make install echo -e "${SUCCESS_COLOR}Verilator successfully installed${ENDC}" else @@ -329,7 +344,7 @@ echo -e "${SUCCESS_COLOR}Sail Compiler successfully installed/updated${ENDC}" # The RISC-V Sail Model is the golden reference model for RISC-V. It is written in Sail (described above) section_header "Installing/Updating RISC-V Sail Model" STATUS="RISC-V Sail Model" -if [[ ((! -e sail-riscv) && ($(git clone https://github.com/riscv/sail-riscv.git) || true)) || ($(cd sail-riscv; git fetch; git rev-parse HEAD) != $(cd sail-riscv; git rev-parse origin/master)) || (! -e $RISCV/bin/riscv_sim_RV32) ]]; then +if git_check "sail-riscv" "https://github.com/riscv/sail-riscv.git" "$RISCV/bin/riscv_sim_RV32"; then eval "$(opam config env)" cd sail-riscv git reset --hard && git clean -f && git checkout master && git pull @@ -358,7 +373,7 @@ section_header "Installing/Updating OSU Skywater 130 cell library" STATUS="OSU Skywater 130 cell library" mkdir -p "$RISCV"/cad/lib cd "$RISCV"/cad/lib -if [[ ((! -e sky130_osu_sc_t12) && ($(git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12) || true)) || ($(cd sky130_osu_sc_t12; git fetch; git rev-parse HEAD) != $(cd sky130_osu_sc_t12; git rev-parse origin/main)) ]]; then +if git_check "sky130_osu_sc_t12" "https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12" "$RISCV/cad/lib/sky130_osu_sc_t12" "main"; then cd sky130_osu_sc_t12 git reset --hard && git clean -f && git checkout main && git pull echo -e "${SUCCESS_COLOR}OSU Skywater library successfully installed${ENDC}" From f346a9990725193b4299908d06fa216f3b16d9ee Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 19 Jul 2024 10:11:44 -0700 Subject: [PATCH 071/219] Fix git_check return values --- bin/wally-tool-chain-install.sh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 99087a559..f3e3e64cb 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -69,9 +69,9 @@ git_check() { local check=$3 local branch="${4:-master}" if [[ ((! -e $repo) && ($(git clone "$url") || true)) || ($(cd "$repo"; git fetch; git rev-parse HEAD) != $(cd repo; git rev-parse origin/"$branch")) || (! -e $check) ]]; then - return 1 - else return 0 + else + return 1 fi } @@ -257,7 +257,7 @@ cd "$RISCV" if git_check "qemu" "https://github.com/qemu/qemu" "$RISCV/include/qemu-plugin.h"; then cd qemu git reset --hard && git clean -f && git checkout master && git pull --recurse-submodules -j ${NUM_THREADS} - submodule update --init --recursive + git submodule update --init --recursive ./configure --target-list=riscv64-softmmu --prefix="$RISCV" make -j ${NUM_THREADS} make install From a8848f02e88d0abb0215997a7b2853ec3ed032a4 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 19 Jul 2024 10:15:25 -0700 Subject: [PATCH 072/219] Use apt-get to avoid warning about unstable apt interface --- bin/wally-package-install.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index 4c8893b4f..64bbaafef 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -62,8 +62,8 @@ if [ "$FAMILY" = rhel ]; then # A newer version of gcc is required for qemu OTHER_PACKAGES="gcc-toolset-13" elif [ "$FAMILY" = ubuntu ]; then - PACKAGE_MANAGER=apt - UPDATE_COMMAND="sudo apt update -y && sudo apt upgrade -y" + PACKAGE_MANAGER=apt-get + UPDATE_COMMAND="sudo apt-get update -y && sudo apt-get upgrade -y --with-new-pkgs" GENERAL_PACKAGES="rsync git make cmake python3 python3-pip python3-venv curl wget ftp tar pkg-config dialog mutt ssmtp" GNU_PACKAGES="autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat1-dev ninja-build libglib2.0-dev libslirp-dev" QEMU_PACKAGES="libfdt-dev libpixman-1-dev" From c3614aa18922ae0d448a27596569ac93ec7e35e3 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 20 Jul 2024 00:24:26 -0700 Subject: [PATCH 073/219] Fix git_check function repo variable --- bin/wally-tool-chain-install.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index f3e3e64cb..2557d76c2 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -68,7 +68,7 @@ git_check() { local url=$2 local check=$3 local branch="${4:-master}" - if [[ ((! -e $repo) && ($(git clone "$url") || true)) || ($(cd "$repo"; git fetch; git rev-parse HEAD) != $(cd repo; git rev-parse origin/"$branch")) || (! -e $check) ]]; then + if [[ ((! -e $repo) && ($(git clone "$url") || true)) || ($(cd "$repo"; git fetch; git rev-parse HEAD) != $(cd $repo; git rev-parse origin/"$branch")) || (! -e $check) ]]; then return 0 else return 1 From f68cb47a5596654a4f95eb54ab34bdab59a996c3 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 20 Jul 2024 00:45:10 -0700 Subject: [PATCH 074/219] Use arithmetic comparisons where possible --- bin/wally-distro-check.sh | 18 +++++++++--------- bin/wally-package-install.sh | 20 ++++++++++---------- bin/wally-tool-chain-install.sh | 22 +++++++++++----------- 3 files changed, 30 insertions(+), 30 deletions(-) diff --git a/bin/wally-distro-check.sh b/bin/wally-distro-check.sh index 1bf8d666b..ce870ce83 100755 --- a/bin/wally-distro-check.sh +++ b/bin/wally-distro-check.sh @@ -49,27 +49,27 @@ test -e /etc/os-release && os_release="/etc/os-release" || os_release="/usr/lib/ source "$os_release" # Check for compatible distro -if [[ "$ID" = rhel || "$ID_LIKE" = *rhel* ]]; then - FAMILY=rhel +if [[ "$ID" == rhel || "$ID_LIKE" == *rhel* ]]; then + export FAMILY=rhel if [ "$ID" != rhel ] && [ "$ID" != rocky ] && [ "$ID" != almalinux ]; then printf "${WARNING_COLOR}%s\n${ENDC}" "For Red Hat family distros, the Wally install script has only been tested on RHEL, Rocky Linux," \ " and AlmaLinux. Your distro is $PRETTY_NAME. The regular Red Hat install will be attempted, but there will likely be issues." fi - if [ "${VERSION_ID:0:1}" = 8 ]; then - RHEL_VERSION=8 - elif [ "${VERSION_ID:0:1}" = 9 ]; then - RHEL_VERSION=9 + if (( "${VERSION_ID:0:1}" == 8 )); then + export RHEL_VERSION=8 + elif (( "${VERSION_ID:0:1}" = 9 )); then + export RHEL_VERSION=9 else echo "${FAIL_COLOR}The Wally install script is only compatible with versions 8 and 9 of RHEL, Rocky Linux, and AlmaLinux. You have version $VERSION.${ENDC}" exit 1 fi -elif [[ "$ID" = ubuntu || "$ID_LIKE" = *ubuntu* ]]; then - FAMILY=ubuntu +elif [[ "$ID" == ubuntu || "$ID_LIKE" == *ubuntu* ]]; then + export FAMILY=ubuntu if [ "$ID" != ubuntu ]; then printf "${WARNING_COLOR}%s\n${ENDC}" "For Ubuntu family distros, the Wally install script has only been tested on standard Ubuntu. Your distro " \ "is $PRETTY_NAME. The regular Ubuntu install will be attempted, but there may be issues." else - UBUNTU_VERSION="${VERSION_ID:0:2}" + export UBUNTU_VERSION="${VERSION_ID:0:2}" if (( UBUNTU_VERSION < 20 )); then echo "${FAIL_COLOR}The Wally install script is only compatible with versions 20.04, 22.04, and 24.04 of Ubuntu. You have version $VERSION.${ENDC}" exit 1 diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index 64bbaafef..6160e1046 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -45,7 +45,7 @@ fi # Generate list of packages to install and package manager commands based on distro # Packages are grouped by which tool requires them. If multiple tools need a package, it is included in the first tool only -if [ "$FAMILY" = rhel ]; then +if [ "$FAMILY" == rhel ]; then PACKAGE_MANAGER="dnf" UPDATE_COMMAND="sudo dnf update -y" GENERAL_PACKAGES="which rsync git make cmake python3.12 python3-pip curl wget ftp tar pkgconf-pkg-config dialog mutt ssmtp" @@ -55,13 +55,13 @@ if [ "$FAMILY" = rhel ]; then VERILATOR_PACKAGES="help2man perl clang ccache gperftools numactl mold" BUILDROOT_PACKAGES="ncurses-base ncurses ncurses-libs ncurses-devel gcc-gfortran" # Extra packages not availale in rhel8, nice for Verilator and needed for sail respectively - if [ "$RHEL_VERSION" = 9 ]; then + if (( RHEL_VERSION == 9 )); then VERILATOR_PACKAGES="$VERILATOR_PACKAGES perl-doc" SAIL_PACKAGES="z3" fi # A newer version of gcc is required for qemu OTHER_PACKAGES="gcc-toolset-13" -elif [ "$FAMILY" = ubuntu ]; then +elif [ "$FAMILY" == ubuntu ]; then PACKAGE_MANAGER=apt-get UPDATE_COMMAND="sudo apt-get update -y && sudo apt-get upgrade -y --with-new-pkgs" GENERAL_PACKAGES="rsync git make cmake python3 python3-pip python3-venv curl wget ftp tar pkg-config dialog mutt ssmtp" @@ -76,25 +76,25 @@ elif [ "$FAMILY" = ubuntu ]; then VERILATOR_PACKAGES="$VERILATOR_PACKAGES mold" fi # Newer version of gcc needed for Ubuntu 20.04 for Verilator - if [ "$UBUNTU_VERSION" = 20 ]; then + if (( UBUNTU_VERSION == 20 )); then OTHER_PACKAGES="gcc-10 g++-10 cpp-10" fi fi # Check if required packages are installed or install/update them depending on passed flag. -if [ "${1}" = "--check" ]; then +if [ "${1}" == "--check" ]; then printf "${SECTION_COLOR}%$(tput cols)s" | tr ' ' '#' printf "%$(tput cols)s" | tr ' ' '#' echo -e "Checking Dependencies from Package Manager" printf "%$(tput cols)s" | tr ' ' '#' printf "%$(tput cols)s${ENDC}" | tr ' ' '#' - if [ "$FAMILY" = rhel ]; then + if [ "$FAMILY" == rhel ]; then for pack in $GENERAL_PACKAGES $GNU_PACKAGES $QEMU_PACKAGES $SPIKE_PACKAGES $VERILATOR_PACKAGES $SAIL_PACKAGES $BUILDROOT_PACKAGES $OTHER_PACKAGES; do rpm -q "$pack" > /dev/null || (echo -e "${FAIL_COLOR}Missing packages detected (${WARNING_COLOR}$pack${FAIL_COLOR}). Run as root to auto-install or run wally-package-install.sh first.${ENDC}" && exit 1) done - elif [ "$FAMILY" = ubuntu ]; then + elif [ "$FAMILY" == ubuntu ]; then for pack in $GENERAL_PACKAGES $GNU_PACKAGES $QEMU_PACKAGES $SPIKE_PACKAGES $VERILATOR_PACKAGES $SAIL_PACKAGES $BUILDROOT_PACKAGES $OTHER_PACKAGES; do dpkg -l "$pack" | grep "ii" > /dev/null || (echo -e "${FAIL_COLOR}Missing packages detected (${WARNING_COLOR}$pack${FAIL_COLOR}). Run as root to auto-install or run wally-package-install.sh first." && exit 1) done @@ -111,14 +111,14 @@ else printf "%$(tput cols)s${ENDC}" | tr ' ' '#' # Enable extra repos necessary for rhel - if [ "$FAMILY" = rhel ]; then + if [ "$FAMILY" == rhel ]; then sudo dnf install -y dnf-plugins-core sudo dnf group install -y "Development Tools" - if [ "$ID" = rhel ]; then + if [ "$ID" == rhel ]; then sudo subscription-manager repos --enable "codeready-builder-for-rhel-$RHEL_VERSION-$(arch)-rpms" sudo dnf install -y "https://dl.fedoraproject.org/pub/epel/epel-release-latest-$RHEL_VERSION.noarch.rpm" else # RHEL clone - if [ "$RHEL_VERSION" = 8 ]; then + if (( RHEL_VERSION == 8 )); then sudo dnf config-manager -y --set-enabled powertools else # Version 9 sudo dnf config-manager -y --set-enabled crb diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 2557d76c2..c5accbcb4 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -86,13 +86,13 @@ dir="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" source "${dir}"/wally-distro-check.sh # Check if root -ROOT=$( [ "${EUID:=$(id -u)}" = 0 ] && echo true || echo false); +ROOT=$( [ "${EUID:=$(id -u)}" == 0 ] && echo true || echo false); # Set installation directory based on execution privileges # If the script is run as root, the default installation path is /opt/riscv # If the script is run as a user, the default installation path is ~/riscv # The installation path can be overridden with an argument passed to the script. -if [ "$ROOT" = true ]; then +if [ "$ROOT" == true ]; then export RISCV="${1:-/opt/riscv}" else export RISCV="${1:-$HOME/riscv}" @@ -110,16 +110,16 @@ echo "Installation path: $RISCV" # Install/update system packages if root. Otherwise, check that packages are already installed. STATUS="system packages" -if [ "$ROOT" = true ]; then +if [ "$ROOT" == true ]; then source "${dir}"/wally-package-install.sh else source "${dir}"/wally-package-install.sh --check fi # Enable newer version of gcc for older distros (required for QEMU/Verilator) -if [ "$FAMILY" = rhel ]; then +if [ "$FAMILY" == rhel ]; then source /opt/rh/gcc-toolset-13/enable -elif [ "$UBUNTU_VERSION" = 20 ]; then +elif (( UBUNTU_VERSION == 20 )); then mkdir -p "$RISCV"/gcc-10/bin for f in gcc cpp g++ gcc-ar gcc-nm gcc-ranlib gcov gcov-dump gcov-tool lto-dump; do ln -vsf /usr/bin/$f-10 "$RISCV"/gcc-10/bin/$f @@ -154,7 +154,7 @@ pip install -U sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText pip install -U riscv_isac # to generate new tests, such as quads with fp_dataset.py # z3 is needed for sail and not availabe from dnf for rhel 8 -if [ "$RHEL_VERSION" = 8 ]; then +if (( RHEL_VERSION == 8 )); then pip install -U z3-solver fi @@ -163,7 +163,7 @@ echo -e "${SUCCESS_COLOR}Python environment successfully configured.${ENDC}" # Extra dependecies needed for older distros that don't have new enough versions available from package manager -if [ "$RHEL_VERSION" = 8 ] || [ "$UBUNTU_VERSION" = 20 ]; then +if (( RHEL_VERSION == 8 )) || (( UBUNTU_VERSION == 20 )); then # Newer versin of glib required for Qemu. # Anything newer than this won't build on red hat 8 STATUS="glib" @@ -185,7 +185,7 @@ if [ "$RHEL_VERSION" = 8 ] || [ "$UBUNTU_VERSION" = 20 ]; then fi # Newer version of gmp needed for sail-riscv model -if [ "$RHEL_VERSION" = 8 ]; then +if (( RHEL_VERSION == 8 )); then STATUS="gmp" if [ ! -e "$RISCV"/include/gmp.h ]; then section_header "Installing gmp" @@ -308,7 +308,7 @@ fi cd "$RISCV" -if [ "$FAMILY" = rhel ]; then +if [ "$FAMILY" == rhel ]; then # Install opam from binary disribution on rhel as it is not available from dnf # Opam is needed to install the sail compiler section_header "Installing/Updating Opam" @@ -392,10 +392,10 @@ if [ ! -e "${RISCV}"/site-setup.sh ]; then wget https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.sh wget https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.csh # Add necessary lines to site-setup script to activate newer version of gcc for older distros - if [ "$FAMILY" = rhel ]; then + if [ "$FAMILY" == rhel ]; then echo "# Activate newer gcc version" >> site-setup.sh echo "source /opt/rh/gcc-toolset-13/enable" >> site-setup.sh - elif [ "$UBUNTU_VERSION" = 20 ]; then + elif (( UBUNTU_VERSION == 20 )); then echo "# Activate newer gcc version" >> site-setup.sh echo "export PATH=\$RISCV/gcc-10/bin:\$PATH" >> site-setup.sh echo "# Activate newer gcc version" >> site-setup.csh From 38c9c4749ec788b578b7fb55da918169b45d62e5 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 19 Jul 2024 23:46:05 -0700 Subject: [PATCH 075/219] Use array of packages instead of string --- bin/wally-package-install.sh | 42 ++++++++++++++++++------------------ 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index 6160e1046..52ce5a9e2 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -48,36 +48,36 @@ fi if [ "$FAMILY" == rhel ]; then PACKAGE_MANAGER="dnf" UPDATE_COMMAND="sudo dnf update -y" - GENERAL_PACKAGES="which rsync git make cmake python3.12 python3-pip curl wget ftp tar pkgconf-pkg-config dialog mutt ssmtp" - GNU_PACKAGES="autoconf automake libmpc-devel mpfr-devel gmp-devel gawk bison flex texinfo gperf libtool patchutils bc gcc gcc-c++ zlib-devel expat-devel libslirp-devel" - QEMU_PACKAGES="glib2-devel libfdt-devel pixman-devel bzip2 ninja-build" - SPIKE_PACKAGES="dtc boost-regex boost-system" - VERILATOR_PACKAGES="help2man perl clang ccache gperftools numactl mold" - BUILDROOT_PACKAGES="ncurses-base ncurses ncurses-libs ncurses-devel gcc-gfortran" + GENERAL_PACKAGES=(which rsync git make cmake python3.12 python3-pip curl wget ftp tar pkgconf-pkg-config dialog mutt ssmtp) + GNU_PACKAGES=(autoconf automake libmpc-devel mpfr-devel gmp-devel gawk bison flex texinfo gperf libtool patchutils bc gcc gcc-c++ zlib-devel expat-devel libslirp-devel) + QEMU_PACKAGES=(glib2-devel libfdt-devel pixman-devel bzip2 ninja-build) + SPIKE_PACKAGES=(dtc boost-regex boost-system) + VERILATOR_PACKAGES=(help2man perl clang ccache gperftools numactl mold) + BUILDROOT_PACKAGES=(ncurses-base ncurses ncurses-libs ncurses-devel gcc-gfortran) # Extra packages not availale in rhel8, nice for Verilator and needed for sail respectively if (( RHEL_VERSION == 9 )); then - VERILATOR_PACKAGES="$VERILATOR_PACKAGES perl-doc" - SAIL_PACKAGES="z3" + VERILATOR_PACKAGES+=(perl-doc) + SAIL_PACKAGES=(z3) fi # A newer version of gcc is required for qemu - OTHER_PACKAGES="gcc-toolset-13" + OTHER_PACKAGES=(gcc-toolset-13) elif [ "$FAMILY" == ubuntu ]; then PACKAGE_MANAGER=apt-get UPDATE_COMMAND="sudo apt-get update -y && sudo apt-get upgrade -y --with-new-pkgs" - GENERAL_PACKAGES="rsync git make cmake python3 python3-pip python3-venv curl wget ftp tar pkg-config dialog mutt ssmtp" - GNU_PACKAGES="autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat1-dev ninja-build libglib2.0-dev libslirp-dev" - QEMU_PACKAGES="libfdt-dev libpixman-1-dev" - SPIKE_PACKAGES="device-tree-compiler libboost-regex-dev libboost-system-dev" - VERILATOR_PACKAGES="help2man perl g++ clang ccache libunwind-dev libgoogle-perftools-dev numactl perl-doc libfl2 libfl-dev zlib1g" - SAIL_PACKAGES="opam z3" - BUILDROOT_PACKAGES="ncurses-base ncurses-bin libncurses-dev gfortran" + GENERAL_PACKAGES=(rsync git make cmake python3 python3-pip python3-venv curl wget ftp tar pkg-config dialog mutt ssmtp) + GNU_PACKAGES=(autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat1-dev ninja-build libglib2.0-dev libslirp-dev) + QEMU_PACKAGES=(libfdt-dev libpixman-1-dev) + SPIKE_PACKAGES=(device-tree-compiler libboost-regex-dev libboost-system-dev) + VERILATOR_PACKAGES=(help2man perl g++ clang ccache libunwind-dev libgoogle-perftools-dev numactl perl-doc libfl2 libfl-dev zlib1g) + SAIL_PACKAGES=(opam z3) + BUILDROOT_PACKAGES=(ncurses-base ncurses-bin libncurses-dev gfortran) # Extra packages not availale in Ubuntu 20.04, nice for Verilator if (( UBUNTU_VERSION >= 22 )); then - VERILATOR_PACKAGES="$VERILATOR_PACKAGES mold" + VERILATOR_PACKAGES+=(mold) fi # Newer version of gcc needed for Ubuntu 20.04 for Verilator if (( UBUNTU_VERSION == 20 )); then - OTHER_PACKAGES="gcc-10 g++-10 cpp-10" + OTHER_PACKAGES=(gcc-10 g++-10 cpp-10) fi fi @@ -91,11 +91,11 @@ if [ "${1}" == "--check" ]; then printf "%$(tput cols)s${ENDC}" | tr ' ' '#' if [ "$FAMILY" == rhel ]; then - for pack in $GENERAL_PACKAGES $GNU_PACKAGES $QEMU_PACKAGES $SPIKE_PACKAGES $VERILATOR_PACKAGES $SAIL_PACKAGES $BUILDROOT_PACKAGES $OTHER_PACKAGES; do + for pack in "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${SAIL_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OTHER_PACKAGES[@]}"; do rpm -q "$pack" > /dev/null || (echo -e "${FAIL_COLOR}Missing packages detected (${WARNING_COLOR}$pack${FAIL_COLOR}). Run as root to auto-install or run wally-package-install.sh first.${ENDC}" && exit 1) done elif [ "$FAMILY" == ubuntu ]; then - for pack in $GENERAL_PACKAGES $GNU_PACKAGES $QEMU_PACKAGES $SPIKE_PACKAGES $VERILATOR_PACKAGES $SAIL_PACKAGES $BUILDROOT_PACKAGES $OTHER_PACKAGES; do + for pack in "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${SAIL_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OTHER_PACKAGES[@]}"; do dpkg -l "$pack" | grep "ii" > /dev/null || (echo -e "${FAIL_COLOR}Missing packages detected (${WARNING_COLOR}$pack${FAIL_COLOR}). Run as root to auto-install or run wally-package-install.sh first." && exit 1) done fi @@ -130,6 +130,6 @@ else # Update and Upgrade tools eval "$UPDATE_COMMAND" # Install packages listed above using appropriate package manager - sudo "$PACKAGE_MANAGER" install -y $GENERAL_PACKAGES $GNU_PACKAGES $QEMU_PACKAGES $SPIKE_PACKAGES $VERILATOR_PACKAGES $SAIL_PACKAGES $BUILDROOT_PACKAGES $OTHER_PACKAGES + sudo "$PACKAGE_MANAGER" install -y "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${SAIL_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OTHER_PACKAGES[@]}" echo -e "${SUCCESS_COLOR}Packages successfully installed.${ENDC}" fi From 0746f8fe899a2e5548740e4fbffa02cf12ca2985 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 20 Jul 2024 01:34:53 -0700 Subject: [PATCH 076/219] Update opam installation to use /opt/riscv folder --- bin/wally-tool-chain-install.sh | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index c5accbcb4..7bf9c57ea 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -307,12 +307,13 @@ else fi -cd "$RISCV" if [ "$FAMILY" == rhel ]; then # Install opam from binary disribution on rhel as it is not available from dnf # Opam is needed to install the sail compiler section_header "Installing/Updating Opam" STATUS="Opam" + export OPAMROOTISOK=1 # Silence warnings about running opam as root + cd "$RISCV" mkdir -p opam cd opam wget https://raw.githubusercontent.com/ocaml/opam/master/shell/install.sh @@ -332,11 +333,12 @@ fi section_header "Installing/Updating Sail Compiler" STATUS="Sail Compiler" export OPAMROOTISOK=1 # Silence warnings about running opam as root +export OPAMROOT="$RISCV"/opam cd "$RISCV" -opam init -y --disable-sandboxing +opam init -y --disable-sandboxing --no-setup --compiler=5.1.0 +eval "$(opam config env)" opam update -y opam upgrade -y -opam switch create 5.1.0 || opam switch set 5.1.0 opam install sail -y echo -e "${SUCCESS_COLOR}Sail Compiler successfully installed/updated${ENDC}" @@ -345,7 +347,6 @@ echo -e "${SUCCESS_COLOR}Sail Compiler successfully installed/updated${ENDC}" section_header "Installing/Updating RISC-V Sail Model" STATUS="RISC-V Sail Model" if git_check "sail-riscv" "https://github.com/riscv/sail-riscv.git" "$RISCV/bin/riscv_sim_RV32"; then - eval "$(opam config env)" cd sail-riscv git reset --hard && git clean -f && git checkout master && git pull export OPAMCLI=2.0 # Sail is not compatible with opam 2.1 as of 4/16/24 From 37aa6acf5a7cdfeb1ca35ead09b15e4d584d520e Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 20 Jul 2024 01:36:33 -0700 Subject: [PATCH 077/219] update riscof link --- bin/wally-tool-chain-install.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 7bf9c57ea..e6ef13cb6 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -361,11 +361,11 @@ else fi -# RISCOF (https://github.com/riscv/riscof.git) +# RISCOF (https://github.com/riscv-software-src/riscof.git) # RISCOF is a RISC-V compliance test framework that is used to run the RISC-V Arch Tests. section_header "Installing/Updating RISCOF" STATUS="RISCOF" -pip3 install git+https://github.com/riscv/riscof.git +pip3 install git+https://github.com/riscv-software-src/riscof.git # OSU Skywater 130 cell library (https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12) From c7d869bc96022e4731fa305ec94c9e6e881f4dce Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Sat, 20 Jul 2024 14:00:43 -0500 Subject: [PATCH 078/219] Added inital spi based sd card code. Working on CRC7 code that works. --- fpga/zsbl/sd.c | 31 +++++++++++++++++++++++++++++++ fpga/zsbl/sd.h | 9 +++++++++ fpga/zsbl/spi.c | 1 - fpga/zsbl/spi.h | 1 + 4 files changed, 41 insertions(+), 1 deletion(-) create mode 100644 fpga/zsbl/sd.c create mode 100644 fpga/zsbl/sd.h diff --git a/fpga/zsbl/sd.c b/fpga/zsbl/sd.c new file mode 100644 index 000000000..4ffb53d67 --- /dev/null +++ b/fpga/zsbl/sd.c @@ -0,0 +1,31 @@ +#include "sd.h" +#include "spi.h" + +uint8_t crc7(uint8_t prev, uint8_t in) { + // CRC polynomial 0x89 + uint8_t remainder = prev & in; + remainder ^= (remainder >> 4) ^ (remainder >> 7); + remainder ^= remainder << 4; + return remainder & 0x7f; +} + +uint16_t crc16(uint16_t crc, uint8_t data) { + // CRC polynomial 0x11021 + crc = (uint8_t)(crc >> 8) | (crc << 8); + crc ^= data; + crc ^= (uint8_t)(crc >> 4) & 0xf; + crc ^= crc << 12; + crc ^= (crc & 0xff) << 5; + return crc; +} + +uint8_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc) { + spi_send_byte +} + +void init_sd(){ + init_spi(); + + +} + diff --git a/fpga/zsbl/sd.h b/fpga/zsbl/sd.h new file mode 100644 index 000000000..b1b27db14 --- /dev/null +++ b/fpga/zsbl/sd.h @@ -0,0 +1,9 @@ +#pragma once + +#include + +uint8_t crc7(uint8_t prev, uint8_t in); +uint16_t crc16(uint16_t crc, uint8_t data); +uint8_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc); +void init_sd(); + diff --git a/fpga/zsbl/spi.c b/fpga/zsbl/spi.c index 1400b8881..bf6d629b4 100644 --- a/fpga/zsbl/spi.c +++ b/fpga/zsbl/spi.c @@ -48,4 +48,3 @@ uint8_t spi_send_byte(uint8_t byte) { return result; } - diff --git a/fpga/zsbl/spi.h b/fpga/zsbl/spi.h index 2bd2003c5..6bae450ae 100644 --- a/fpga/zsbl/spi.h +++ b/fpga/zsbl/spi.h @@ -40,6 +40,7 @@ void write_reg(uintptr_t addr, uint32_t value); uint32_t read_reg(uintptr_t addr); uint8_t spi_send_byte(uint8_t byte); + void spi_init(); #endif From f30cc46ec52dec95b6222a5b6479593084e4401e Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 21 Jul 2024 08:26:07 -0700 Subject: [PATCH 079/219] Disable misaligned accesses in imperas configuration and check misaligned support requires D$ --- config/derivlist.txt | 2 ++ testbench/common/riscvassertions.sv | 1 + 2 files changed, 3 insertions(+) diff --git a/config/derivlist.txt b/config/derivlist.txt index 2fac6bcc2..1edd20b7b 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -1661,6 +1661,7 @@ derive imperas rv64gc ICACHE_SUPPORTED 0 DCACHE_SUPPORTED 0 VIRTMEM_SUPPORTED 0 +ZICCLSM_SUPPORTED 0 ZAAMO_SUPPORTED 0 ZALRSC_SUPPORTED 0 ZICBOM_SUPPORTED 0 @@ -1669,3 +1670,4 @@ SVPBMT_SUPPORTED 0 SVNAPOT_SUPPORTED 0 BOOTROM_BASE 64'h700012340010 BOOTROM_RANGE 64'h10 + diff --git a/testbench/common/riscvassertions.sv b/testbench/common/riscvassertions.sv index 404353909..0872ab1de 100644 --- a/testbench/common/riscvassertions.sv +++ b/testbench/common/riscvassertions.sv @@ -66,6 +66,7 @@ module riscvassertions import cvw::*; #(parameter cvw_t P); assert ((P.ZCF_SUPPORTED == 0) | ((P.F_SUPPORTED == 1) & (P.XLEN == 32))) else $fatal(1, "ZCF requires F and XLEN == 32"); assert ((P.ZCD_SUPPORTED == 0) | (P.D_SUPPORTED == 1)) else $fatal(1, "ZCD requires D"); assert ((P.LLEN == P.XLEN) | (P.DCACHE_SUPPORTED & P.DTIM_SUPPORTED == 0)) else $fatal(1, "LLEN > XLEN (D on RV32 or Q on RV64) requires data cache"); + assert ((P.ZICCLSM_SUPPORTED == 0) | (P.DCACHE_SUPPORTED == 1)) else $fatal(1, "ZICCLSM requires DCACHE_SUPPORTED"); end endmodule From 4ea5e3c4d4bdc15bc86dae91f36f598fc71df0d5 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 21 Jul 2024 10:06:00 -0700 Subject: [PATCH 080/219] Simplify version checking logic --- bin/wally-distro-check.sh | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/bin/wally-distro-check.sh b/bin/wally-distro-check.sh index ce870ce83..cec2ac509 100755 --- a/bin/wally-distro-check.sh +++ b/bin/wally-distro-check.sh @@ -55,11 +55,8 @@ if [[ "$ID" == rhel || "$ID_LIKE" == *rhel* ]]; then printf "${WARNING_COLOR}%s\n${ENDC}" "For Red Hat family distros, the Wally install script has only been tested on RHEL, Rocky Linux," \ " and AlmaLinux. Your distro is $PRETTY_NAME. The regular Red Hat install will be attempted, but there will likely be issues." fi - if (( "${VERSION_ID:0:1}" == 8 )); then - export RHEL_VERSION=8 - elif (( "${VERSION_ID:0:1}" = 9 )); then - export RHEL_VERSION=9 - else + export RHEL_VERSION="${VERSION_ID:0:1}" + if (( RHEL_VERSION < 8 )); then echo "${FAIL_COLOR}The Wally install script is only compatible with versions 8 and 9 of RHEL, Rocky Linux, and AlmaLinux. You have version $VERSION.${ENDC}" exit 1 fi @@ -68,12 +65,11 @@ elif [[ "$ID" == ubuntu || "$ID_LIKE" == *ubuntu* ]]; then if [ "$ID" != ubuntu ]; then printf "${WARNING_COLOR}%s\n${ENDC}" "For Ubuntu family distros, the Wally install script has only been tested on standard Ubuntu. Your distro " \ "is $PRETTY_NAME. The regular Ubuntu install will be attempted, but there may be issues." - else - export UBUNTU_VERSION="${VERSION_ID:0:2}" - if (( UBUNTU_VERSION < 20 )); then - echo "${FAIL_COLOR}The Wally install script is only compatible with versions 20.04, 22.04, and 24.04 of Ubuntu. You have version $VERSION.${ENDC}" - exit 1 - fi + fi + export UBUNTU_VERSION="${VERSION_ID:0:2}" + if (( UBUNTU_VERSION < 20 )); then + echo "${FAIL_COLOR}The Wally install script is only compatible with versions 20.04, 22.04, and 24.04 of Ubuntu. You have version $VERSION.${ENDC}" + exit 1 fi else printf "${FAIL_COLOR}%s\n${ENDC}" "The Wally install script is currently only compatible with Ubuntu and Red Hat family " \ From 76fbb2e94dd242fad8652795a70a97f239b71c10 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sun, 21 Jul 2024 10:08:51 -0700 Subject: [PATCH 081/219] Add --clean flag to install to remove git repositories and save space --- bin/wally-tool-chain-install.sh | 35 ++++++++++++++++++++++++++++++--- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index e6ef13cb6..804deee30 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -79,6 +79,12 @@ set -e # break on error trap error ERR # run error handler on error STATUS="setup" # keep track of what part of the installation is running for error messages +# Check for clean flag +if [ "$1" == "--clean" ]; then + clean=true + shift +fi + # Determine script directory to locate related scripts dir="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" @@ -219,6 +225,10 @@ if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain git pull ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" make -j ${NUM_THREADS} + if [ "$clean" ]; then + cd "$RISCV" + rm -rf riscv-gnu-toolchain + fi echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain successfully installed${ENDC}" else echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain already up to date${ENDC}" @@ -243,6 +253,10 @@ if git_check "elf2hex" "https://github.com/sifive/elf2hex.git" "$RISCV/bin/riscv ./configure --target=riscv64-unknown-elf --prefix="$RISCV" make make install + if [ "$clean" ]; then + cd "$RISCV" + rm -rf elf2hex + fi echo -e "${SUCCESS_COLOR}elf2hex successfully installed${ENDC}" else echo -e "${SUCCESS_COLOR}elf2hex already up to date${ENDC}" @@ -261,6 +275,10 @@ if git_check "qemu" "https://github.com/qemu/qemu" "$RISCV/include/qemu-plugin.h ./configure --target-list=riscv64-softmmu --prefix="$RISCV" make -j ${NUM_THREADS} make install + if [ "$clean" ]; then + cd "$RISCV" + rm -rf qemu + fi echo -e "${SUCCESS_COLOR}QEMU successfully installed${ENDC}" else echo -e "${SUCCESS_COLOR}QEMU already up to date${ENDC}" @@ -280,6 +298,10 @@ if git_check "riscv-isa-sim" "https://github.com/riscv-software-src/riscv-isa-si ../configure --prefix="$RISCV" make -j ${NUM_THREADS} make install + if [ "$clean" ]; then + cd "$RISCV" + rm -rf riscv-isa-sim + fi echo -e "${SUCCESS_COLOR}Spike successfully installed${ENDC}" else echo -e "${SUCCESS_COLOR}Spike already up to date${ENDC}" @@ -301,6 +323,10 @@ if git_check "verilator" "https://github.com/verilator/verilator" "$RISCV/share/ ./configure --prefix="$RISCV" make -j ${NUM_THREADS} make install + if [ "$clean" ]; then + cd "$RISCV" + rm -rf verilator + fi echo -e "${SUCCESS_COLOR}Verilator successfully installed${ENDC}" else echo -e "${SUCCESS_COLOR}Verilator already up to date${ENDC}" @@ -352,9 +378,12 @@ if git_check "sail-riscv" "https://github.com/riscv/sail-riscv.git" "$RISCV/bin/ export OPAMCLI=2.0 # Sail is not compatible with opam 2.1 as of 4/16/24 ARCH=RV64 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV64 ARCH=RV32 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV32 - cd "$RISCV" - ln -sf ../sail-riscv/c_emulator/riscv_sim_RV64 bin/riscv_sim_RV64 - ln -sf ../sail-riscv/c_emulator/riscv_sim_RV32 bin/riscv_sim_RV32 + cp -f c_emulator/riscv_sim_RV64 "$RISCV"/bin/riscv_sim_RV64 + cp -f c_emulator/riscv_sim_RV32 "$RISCV"/bin/riscv_sim_RV32 + if [ "$clean" ]; then + cd "$RISCV" + rm -rf sail-riscv + fi echo -e "${SUCCESS_COLOR}RISC-V Sail Model successfully installed${ENDC}" else echo -e "${SUCCESS_COLOR}RISC-V Sail Model already up to date${ENDC}" From 7fd8c6e29ae08d2f2ef0a00861527db5479d75b4 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 21 Jul 2024 19:45:22 -0700 Subject: [PATCH 082/219] Removed outdated wally-imperas files --- sim/questa/sim-imperas | 33 ------------- sim/questa/wally-imperas-cov.do | 79 ------------------------------ sim/questa/wally-imperas-no-idv.do | 48 ------------------ sim/questa/wally-imperas.do | 64 ------------------------ 4 files changed, 224 deletions(-) delete mode 100755 sim/questa/sim-imperas delete mode 100644 sim/questa/wally-imperas-cov.do delete mode 100644 sim/questa/wally-imperas-no-idv.do delete mode 100644 sim/questa/wally-imperas.do diff --git a/sim/questa/sim-imperas b/sim/questa/sim-imperas deleted file mode 100755 index 556cdebf6..000000000 --- a/sim/questa/sim-imperas +++ /dev/null @@ -1,33 +0,0 @@ -#!/bin/bash - -########################################### -## imperas-one-time.sh -## -## Written: Ross Thompson (ross1728@gmail.com) and Lee Moore (moore@imperas.com) -## Created: 31 January 2023 -## Modified: 31 January 2023 -## -## Purpose: Run wally with imperas -## -## A component of the CORE-V-WALLY configurable RISC-V project. -## https://github.com/openhwgroup/cvw -## -## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -## -## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -## -## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -## except in compliance with the License, or, at your option, the Apache License version 2.0. You -## may obtain a copy of the License at -## -## https://solderpad.org/licenses/SHL-2.1/ -## -## Unless required by applicable law or agreed to in writing, any work distributed under the -## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -## either express or implied. See the License for the specific language governing permissions -## and limitations under the License. -################################################################################################ -IMPERAS_TOOLS=$(pwd)/imperas.ic \ -OTHERFLAGS="+TRACE2LOG_ENABLE=1 VERBOSE=1" \ -TESTDIR=${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege/src/Lee.S/ \ -vsim -do "do wally-imperas.do rv64gc" diff --git a/sim/questa/wally-imperas-cov.do b/sim/questa/wally-imperas-cov.do deleted file mode 100644 index 1b83950d0..000000000 --- a/sim/questa/wally-imperas-cov.do +++ /dev/null @@ -1,79 +0,0 @@ -# wally.do -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Modification by Oklahoma State University & Harvey Mudd College -# Use with Testbench -# James Stine, 2008; David Harris 2021 -# Go Cowboys!!!!!! -# -# Takes 1:10 to run RV64IC tests using gui - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -# suppress spurious warnngs about -# "Extra checking for conflicts with always_comb done at vopt time" -# because vsim will run vopt - -# start and run simulation -# remove +acc flag for faster sim during regressions if there is no need to access internal signals - # *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings. -vlog +incdir+$env(WALLY)/config/$1 \ - +incdir+$env(WALLY)/config/deriv/$1 \ - +incdir+$env(WALLY)/config/shared \ - +define+USE_IMPERAS_DV \ - +define+IDV_INCLUDE_TRACE2COV \ - +define+INCLUDE_TRACE2COV +define+COVER_BASE_RV64I +define+COVER_LEVEL_DV_PR_EXT \ - +define+COVER_RV64I \ - +define+COVER_RV64M \ - +define+COVER_RV64A \ - +define+COVER_RV64F \ - +define+COVER_RV64D \ - +define+COVER_RV64ZICSR \ - +define+COVER_RV64C \ - +incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \ - +incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \ - $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviApiPkg.sv \ - $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvApiPkg.sv \ - $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviTrace.sv \ - $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvPkg.sv \ - $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2bin.sv \ - $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2api.sv \ - $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2log.sv \ - \ - +incdir+$env(IMPERAS_HOME)/ImpProprietary/source/host/riscvISACOV/source \ - $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv \ - \ - $env(WALLY)/src/cvw.sv \ - $env(WALLY)/testbench/testbench.sv \ - $env(WALLY)/testbench/common/*.sv \ - $env(WALLY)/src/*/*.sv \ - $env(WALLY)/src/*/*/*.sv \ - -suppress 2583 \ - -suppress 7063 \ - +acc -vopt +acc work.testbench -G DEBUG=1 -o workopt -eval vsim workopt +nowarn3829 -fatal 7 \ - -sv_lib $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model \ - +ElfFile=$env(TESTDIR)/ref/ref.elf $env(OTHERFLAGS) +TRACE2COV_ENABLE=1 - -coverage save -onexit $env(WALLY)/sim/questa/riscv.ucdb - - -view wave -#-- display input and output signals as hexidecimal values -# add log -recursive /* -# do wave.do - -run -all - -noview $env(WALLY)/testbench/testbench-imperas.sv -view wave - -#quit -f diff --git a/sim/questa/wally-imperas-no-idv.do b/sim/questa/wally-imperas-no-idv.do deleted file mode 100644 index 47d8bf07b..000000000 --- a/sim/questa/wally-imperas-no-idv.do +++ /dev/null @@ -1,48 +0,0 @@ -# wally.do -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Modification by Oklahoma State University & Harvey Mudd College -# Use with Testbench -# James Stine, 2008; David Harris 2021 -# Go Cowboys!!!!!! -# -# Takes 1:10 to run RV64IC tests using gui - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -# suppress spurious warnngs about -# "Extra checking for conflicts with always_comb done at vopt time" -# because vsim will run vopt - -# start and run simulation -# remove +acc flag for faster sim during regressions if there is no need to access internal signals - # *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings. -vlog +incdir+../config/$1 \ - +incdir+../config/shared \ - ../../external/ImperasDV-HMC/Imperas/ImpPublic/source/host/rvvi/rvviTrace.sv \ - ../src/cvw.sv \ - ../testbench/testbench_imperas.sv \ - ../testbench/common/*.sv \ - ../src/*/*.sv \ - ../src/*/*/*.sv \ - -suppress 2583 \ - -suppress 7063 -vopt +acc work.testbench -G DEBUG=1 -o workopt -eval vsim workopt +nowarn3829 -fatal 7 \ - +testDir=$env(TESTDIR) $env(OTHERFLAGS) -view wave -#-- display input and output signals as hexidecimal values -add log -recursive /* -do wave.do - -run -all - -noview ../testbench/testbench_imperas.sv -view wave diff --git a/sim/questa/wally-imperas.do b/sim/questa/wally-imperas.do deleted file mode 100644 index 118e44d10..000000000 --- a/sim/questa/wally-imperas.do +++ /dev/null @@ -1,64 +0,0 @@ -# wally.do -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Modification by Oklahoma State University & Harvey Mudd College -# Use with Testbench -# James Stine, 2008; David Harris 2021 -# Go Cowboys!!!!!! -# -# Takes 1:10 to run RV64IC tests using gui - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -# suppress spurious warnngs about -# "Extra checking for conflicts with always_comb done at vopt time" -# because vsim will run vopt - -# start and run simulation -# remove +acc flag for faster sim during regressions if there is no need to access internal signals - # *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings. - -vlog +incdir+../config/$1 \ - +incdir+../config/shared \ - +define+USE_IMPERAS_DV \ - +incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \ - +incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \ - $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviApiPkg.sv \ - $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviTrace.sv \ - $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvApiPkg.sv \ - $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvPkg.sv \ - $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvApiPkg.sv \ - $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2api.sv \ - $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2log.sv \ - $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv \ - $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2bin.sv \ - ../src/cvw.sv \ - ../testbench/testbench-imperas.sv \ - ../testbench/common/*.sv \ - ../src/*/*.sv \ - ../src/*/*/*.sv \ - -suppress 2583 \ - -suppress 7063 - -vopt +acc work.testbench -G DEBUG=1 -o workopt -eval vsim workopt +nowarn3829 -fatal 7 \ - -sv_lib $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model \ - +testDir=$env(TESTDIR) $env(OTHERFLAGS) -view wave -#-- display input and output signals as hexidecimal values -add log -recursive /* -do wave.do - -run -all - -noview ../testbench/testbench_imperas.sv -view wave - -#quit -f From af79fd57023ab412495de1847c4aca66a5b62475 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 21 Jul 2024 19:46:30 -0700 Subject: [PATCH 083/219] Fixed hazard and rd_maxval coverage generation --- tests/testgen/covergen.py | 165 +++++++++++++++++++++++--------------- 1 file changed, 100 insertions(+), 65 deletions(-) diff --git a/tests/testgen/covergen.py b/tests/testgen/covergen.py index 1e06e7b9c..0f7bb0d4e 100755 --- a/tests/testgen/covergen.py +++ b/tests/testgen/covergen.py @@ -37,7 +37,7 @@ def signedImm20(imm): imm = imm - 0x100000 return str(imm) -def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen): +def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, xlen): lines = "\n# Testcase " + str(desc) + "\n" if (rs1val < 0): rs1val = rs1val + 2**xlen @@ -45,30 +45,31 @@ def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, stor rs2val = rs2val + 2**xlen lines = lines + "li x" + str(rd) + ", " + formatstr.format(rdval) + " # initialize rd to a random value that should get changed\n" if (test in rtype): - lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1 to a random value \n" - lines = lines + "li x" + str(rs2) + ", " + formatstr.format(rs2val) + " # initialize rs2 to a random value\n" + lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1\n" + lines = lines + "li x" + str(rs2) + ", " + formatstr.format(rs2val) + " # initialize rs2\n" lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", x" + str(rs2) + " # perform operation\n" elif (test in shiftitype): - lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1 to a random value \n" + lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1\n" lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", " + shiftImm(immval, xlen) + " # perform operation\n" elif (test in itype): - lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1 to a random value \n" + lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1\n" lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", " + signedImm12(immval) + " # perform operation\n" elif (test in loaditype):#["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"] lines = lines + "auipc x" + str(rs1) + ", 0x20" + " # add upper immediate value to pc \n" - lines = lines + "addi x" + str(rs1) + ", x" + str(rs1) + ", " + signedImm12(immval) + " # add immediate to lower part of rs1 \n" - lines = lines + test + " x" + str(rd) + ", " + signedImm12(immval) + "(x" + str(rs1) + ") # perform operation \n" + lines = lines + "addi x" + str(rs1) + ", x" + str(rs1) + ", " + signedImm12(immval) + " # add immediate to lower part of rs1\n" + lines = lines + test + " x" + str(rd) + ", " + signedImm12(immval) + "(x" + str(rs1) + ") # perform operation\n" elif (test in stypes):#["sb", "sh", "sw", "sd"] #lines = lines + test + " x" + str(rs2) + ", " + signedImm12(immval) + "(x" + str(rs1) + ") # perform operation \n" #lines = lines + test + " x" + str(rs2) + ", " "0(x" + str(rs1) + ") # perform operation \n" - print("Error: %s type not implemented yet" % test) + #print("Error: %s type not implemented yet" % test) + pass elif (test in btypes):#["beq", "bne", "blt", "bge", "bltu", "bgeu"] if (randint(1,100) > 50): rs1val = rs2val lines = lines + "# same values in both registers\n" lines = lines + "nop\n" - lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1 to a random value that should get changed\n" - lines = lines + "li x" + str(rs2) + ", " + formatstr.format(rs2val) + " # initialize rs2 to a random value that should get changed\n" + lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1\n" + lines = lines + "li x" + str(rs2) + ", " + formatstr.format(rs2val) + " # initialize rs2\n" lines = lines + test + " x" + str(rs1) + ", x" + str(rs2) + ", some_label_for_sb_types_" + str(immval) + "+4" + " # perform operation \n" lines = lines + "addi x0, x1, 1\n" lines = lines + "some_label_for_sb_types_" + str(immval) + ":\n" @@ -79,6 +80,13 @@ def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, stor #print("Error: %s type not implemented yet" % test) f.write(lines) +def writeHazardVector(desc, rs1a, rs2a, rda, rs1b, rs2b, rdb, test): + # consecutive R-type instructions to trigger hazards + lines = "\n# Testcase " + str(desc) + "\n" + lines = lines + test + " x" + str(rda) + ", x" + str(rs1a) + ", x" + str(rs2a) + " # perform first operation\n" + lines = lines + test + " x" + str(rdb) + ", x" + str(rs1b) + ", x" + str(rs2b) + " # perform second operation\n" + f.write(lines) + def randomize(): rs1 = randint(1, 31) rs2 = randint(1, 31) @@ -93,157 +101,184 @@ def randomize(): rdval = randint(0, 2**xlen-1) return [rs1, rs2, rd, rs1val, rs2val, immval, rdval] -def make_rd(test, storecmd, xlen): +def make_rd(test, xlen): for r in range(32): [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize() desc = "cp_rd (Test destination rd = x" + str(r) + ")" - writeCovVector(desc, rs1, rs2, r, rs1val, rs2val, immval, rdval, test, storecmd, xlen) + writeCovVector(desc, rs1, rs2, r, rs1val, rs2val, immval, rdval, test, xlen) -def make_rs1(test, storecmd, xlen): +def make_rs1(test, xlen): for r in range(32): [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize() desc = "cp_rs1 (Test source rs1 = x" + str(r) + ")" - writeCovVector(desc, r, rs2, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen) + writeCovVector(desc, r, rs2, rd, rs1val, rs2val, immval, rdval, test, xlen) -def make_rs2(test, storecmd, xlen): +def make_rs2(test, xlen): for r in range(32): [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize() desc = "cp_rs2 (Test source rs2 = x" + str(r) + ")" - writeCovVector(desc, rs1, r, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen) + writeCovVector(desc, rs1, r, rd, rs1val, rs2val, immval, rdval, test, xlen) -def make_rd_rs1(test, storecmd, xlen): +def make_rd_rs1(test, xlen): for r in range(32): [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize() desc = "cmp_rd_rs1 (Test rd = rs1 = x" + str(r) + ")" - writeCovVector(desc, r, rs2, r, rs1val, rs2val, immval, rdval, test, storecmd, xlen) + writeCovVector(desc, r, rs2, r, rs1val, rs2val, immval, rdval, test, xlen) -def make_rd_rs2(test, storecmd, xlen): +def make_rd_rs2(test, xlen): for r in range(32): [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize() desc = "cmp_rd_rs2 (Test rd = rs1 = x" + str(r) + ")" - writeCovVector(desc, rs1, r, r, rs1val, rs2val, immval, rdval, test, storecmd, xlen) + writeCovVector(desc, rs1, r, r, rs1val, rs2val, immval, rdval, test, xlen) -def make_rd_rs1_rs2(test, storecmd, xlen): +def make_rd_rs1_rs2(test, xlen): for r in range(32): [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize() desc = "cmp_rd_rs1_rs2 (Test rd = rs1 = rs2 = x" + str(r) + ")" - writeCovVector(desc, r, r, r, rs1val, rs2val, immval, rdval, test, storecmd, xlen) + writeCovVector(desc, r, r, r, rs1val, rs2val, immval, rdval, test, xlen) -def make_rs1_rs2(test, storecmd, xlen): +def make_rs1_rs2(test, xlen): for r in range(32): [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize() desc = "cmp_rd_rs1_rs2 (Test rs1 = rs2 = x" + str(r) + ")" - writeCovVector(desc, r, r, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen) + writeCovVector(desc, r, r, rd, rs1val, rs2val, immval, rdval, test, xlen) -def make_rs1_maxvals(test, storecmd, xlen): +def make_rs1_maxvals(test, xlen): for v in [0, 2**(xlen-1), 2**(xlen-1)-1, 2**xlen-1, 1, 2**(xlen-1)+1]: [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize() desc = "cp_rs1_maxvals (Test source rs1 value = " + hex(v) + ")" - writeCovVector(desc, rs1, rs2, rd, v, rs2val, immval, rdval, test, storecmd, xlen) + writeCovVector(desc, rs1, rs2, rd, v, rs2val, immval, rdval, test, xlen) -def make_rs2_maxvals(test, storecmd, xlen): +def make_rs2_maxvals(test, xlen): for v in [0, 2**(xlen-1), 2**(xlen-1)-1, 2**xlen-1, 1, 2**(xlen-1)+1]: [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize() desc = "cp_rs2_maxvals (Test source rs2 value = " + hex(v) + ")" - writeCovVector(desc, rs1, rs2, rd, rs1val, v, immval, rdval, test, storecmd, xlen) + writeCovVector(desc, rs1, rs2, rd, rs1val, v, immval, rdval, test, xlen) -def make_rd_maxvals(test, storecmd, xlen): +def make_rd_maxvals(test, xlen): for v in [0, 2**(xlen-1), 2**(xlen-1)-1, 2**xlen-1, 1, 2**(xlen-1)+1]: + # rs1 = 0, rs2 = v, others are random [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize() desc = "cp_rd_maxvals (Test rd value = " + hex(v) + ")" - writeCovVector(desc, rs1, 0, rd, v, rs2val, immval, rdval, test, storecmd, xlen) + writeCovVector(desc, rs1, 0, rd, v, rs2val, immval, rdval, test, xlen) + # rs1, rs2 = v, others are random + [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize() + desc = "cp_rd_maxvals (Test rd value = " + hex(v) + ")" + writeCovVector(desc, rs1, rs2, rd, v, v, immval, rdval, test, xlen) + # rs1 = all 1s, rs2 = v, others are random + [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize() + desc = "cp_rd_maxvals (Test rd value = " + hex(v) + ")" + writeCovVector(desc, rs1, rs2, rd, -1, v, immval, rdval, test, xlen) -def make_rd_rs1_eqval(test, storecmd, xlen): +def make_rd_rs1_eqval(test, xlen): [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize() desc = "cmp_rdm_rs1_eqval (Test rs1 = rd = " + hex(rs1val) + ")" - writeCovVector(desc, rs1, 0, rd, rdval, rs2val, immval, rdval, test, storecmd, xlen) + writeCovVector(desc, rs1, 0, rd, rdval, rs2val, immval, rdval, test, xlen) -def make_rd_rs2_eqval(test, storecmd, xlen): +def make_rd_rs2_eqval(test, xlen): [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize() desc = "cmp_rd_rs2_eqval (Test rs2 = rd = " + hex(rs2val) + ")" - writeCovVector(desc, 0, rs2, rd, rs1val, rdval, immval, rdval, test, storecmd, xlen) + writeCovVector(desc, 0, rs2, rd, rs1val, rdval, immval, rdval, test, xlen) -def make_rs1_rs2_eqval(test, storecmd, xlen): +def make_rs1_rs2_eqval(test, xlen): [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize() desc = "cmp_rs1_rs2_eqval (Test rs1 = rs2 = " + hex(rs1val) + ")" - writeCovVector(desc, rs1, rs2, rd, rs1val, rs1val, immval, rdval, test, storecmd, xlen) + writeCovVector(desc, rs1, rs2, rd, rs1val, rs1val, immval, rdval, test, xlen) -#def make_cp_gpr_hazard(test, storecmd, xlen): -# pass # *** to be implemented *** +def make_cp_gpr_hazard(test, xlen): + for haz in ["raw", "waw", "war"]: + for src in range(2): + [rs1a, rs2a, rda, rs1vala, rs2vala, immvala, rdvala] = randomize() + [rs1b, rs2b, rdb, rs1valb, rs2valb, immvalb, rdvalb] = randomize() + # set up hazard + if (haz == "raw"): + if (src): + rs2b = rda + else: + rs1b = rda + elif (haz == "waw"): + rdb = rda + elif (haz == "war"): + if (src): + rdb = rs2a + else: + rdb = rs1a + desc = "cmp_gpr_hazard " + haz + " test" + writeHazardVector(desc, rs1a, rs2a, rda, rs1b, rs2b, rdb, test) -def make_rs1_sign(test, storecmd, xlen): +def make_rs1_sign(test, xlen): for v in [1, -1]: [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize() rs1val = abs(rs1val % 2**(xlen-1)) * v; desc = "cp_rs1_sign (Test source rs1 value = " + hex(rs1val) + ")" - writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen) + writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, xlen) -def make_rs2_sign(test, storecmd, xlen): +def make_rs2_sign(test, xlen): for v in [1, -1]: [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize() rs2val = abs(rs2val % 2**(xlen-1)) * v; desc = "cp_rs2_sign (Test source rs2 value = " + hex(rs2val) + ")" - writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen) + writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, xlen) -def make_cr_rs1_rs2_sign(test, storecmd, xlen): +def make_cr_rs1_rs2_sign(test, xlen): for v1 in [1, -1]: for v2 in [1, -1]: [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize() rs1val = abs(rs1val % 2**(xlen-1)) * v1; rs2val = abs(rs2val % 2**(xlen-1)) * v2; desc = "cr_rs1_rs2 (Test source rs1 = " + hex(rs1val) + " rs2 = " + hex(rs2val) + ")" - writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen) + writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, xlen) -def write_tests(coverpoints, test, storecmd, xlen): +def write_tests(coverpoints, test, xlen): for coverpoint in coverpoints: if (coverpoint == "cp_asm_count"): pass elif (coverpoint == "cp_rd"): - make_rd(test, storecmd, xlen) + make_rd(test, xlen) elif (coverpoint == "cp_rs1"): - make_rs1(test, storecmd, xlen) + make_rs1(test, xlen) elif (coverpoint == "cp_rs2"): - make_rs2(test, storecmd, xlen) + make_rs2(test, xlen) elif (coverpoint == "cmp_rd_rs1"): - make_rd_rs1(test, storecmd, xlen) + make_rd_rs1(test, xlen) elif (coverpoint == "cmp_rd_rs2"): - make_rd_rs2(test, storecmd, xlen) + make_rd_rs2(test, xlen) elif (coverpoint == "cmp_rd_rs1_rs2"): - make_rd_rs1_rs2(test, storecmd, xlen) + make_rd_rs1_rs2(test, xlen) elif (coverpoint == "cmp_rd_rs1_eq"): pass # duplicate of cmp_rd_rs1 elif (coverpoint == "cmp_rd_rs2_eq"): pass # duplicate of cmp_rd_rs2 elif (coverpoint == "cmp_rs1_rs2_eq"): - make_rs1_rs2(test, storecmd, xlen) + make_rs1_rs2(test, xlen) elif (coverpoint == "cp_rs1_maxvals"): - make_rs1_maxvals(test, storecmd, xlen) + make_rs1_maxvals(test, xlen) elif (coverpoint == "cp_rs2_maxvals"): - make_rs2_maxvals(test, storecmd, xlen) + make_rs2_maxvals(test, xlen) elif (coverpoint == "cp_rd_maxvals"): - make_rd_maxvals(test, storecmd, xlen) + make_rd_maxvals(test, xlen) elif (coverpoint == "cmp_rd_rs1_eqval"): - make_rd_rs1_eqval(test, storecmd, xlen) + make_rd_rs1_eqval(test, xlen) elif (coverpoint == "cmp_rd_rs2_eqval"): - make_rd_rs2_eqval(test, storecmd, xlen) + make_rd_rs2_eqval(test, xlen) elif (coverpoint == "cmp_rs1_rs2_eqval"): - make_rs1_rs2_eqval(test, storecmd, xlen) + make_rs1_rs2_eqval(test, xlen) elif (coverpoint == "cp_rs1_sign"): - make_rs1_sign(test, storecmd, xlen) + make_rs1_sign(test, xlen) elif (coverpoint == "cp_rs2_sign"): - make_rs2_sign(test, storecmd, xlen) + make_rs2_sign(test, xlen) elif (coverpoint == "cp_rd_sign"): pass #TODO hope already covered by rd_maxvals elif (coverpoint == "cr_rs1_rs2"): - make_cr_rs1_rs2_sign(test, storecmd, xlen) + make_cr_rs1_rs2_sign(test, xlen) + elif (coverpoint == "cp_gpr_hazard"): + make_cp_gpr_hazard(test, xlen) elif (coverpoint == "cp_rs1_toggle"): pass #TODO toggle not needed and seems to be covered by other things elif (coverpoint == "cp_rs2_toggle"): pass #TODO toggle not needed and seems to be covered by other things elif (coverpoint == "cp_rd_toggle"): pass #TODO toggle not needed and seems to be covered by other things - elif (coverpoint == "cp_gpr_hazard"): - pass #TODO not yet implemented elif (coverpoint == "cp_imm_sign"): pass #TODO elif (coverpoint == "cr_rs1_imm"): @@ -355,8 +390,8 @@ for xlen in xlens: #if (test not in rtests): # exit("Error: %s not implemented yet" % test) #else: - # write_rtype_arith_vectors(test, storecmd, xlen) - write_tests(coverpoints[test], test, storecmd, xlen) + # write_rtype_arith_vectors(test, xlen) + write_tests(coverpoints[test], test, xlen) # print footer line = "\n.EQU NUMTESTS," + str(1) + "\n\n" From da502d2d5af4b04808cee8db73981284c254c873 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 21 Jul 2024 19:47:00 -0700 Subject: [PATCH 084/219] Fixed makefile log typo --- sim/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/sim/Makefile b/sim/Makefile index 5635431ff..891ccb213 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -91,6 +91,7 @@ combine_functcov: cd ${SIM}/questa/fcov && rm -rf * cd ${SIM}/questa/fcov_ucdb && rm -rf * wsim rv64gc ${WALLY}/tests/functcov/rv64/I/WALLY-COV-add.elf --fcov > ${SIM}/questa/fcov_logs/add.log 2>&1 + wsim rv64gc ${WALLY}/tests/functcov/rv64/I/WALLY-COV-and.elf --fcov > ${SIM}/questa/fcov_logs/and.log 2>&1 #run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/fcov/add.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-add.elf >> ${SIM}/questa/fcov_logs/add.log 2>&1 #run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/fcov/and.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-and.elf >> ${SIM}/questa/fcov_logs/add.log 2>&1 From e949c9cfba1fe47de6a9fd5558a1b3f5740feebf Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 21 Jul 2024 19:47:23 -0700 Subject: [PATCH 085/219] Removed more obsolete imperas scripts --- sim/questa/run-imperas-linux.sh | 10 ---------- 1 file changed, 10 deletions(-) delete mode 100755 sim/questa/run-imperas-linux.sh diff --git a/sim/questa/run-imperas-linux.sh b/sim/questa/run-imperas-linux.sh deleted file mode 100755 index aebf6b9d0..000000000 --- a/sim/questa/run-imperas-linux.sh +++ /dev/null @@ -1,10 +0,0 @@ -#!/bin/bash - -#export RISCV=/scratch/moore/RISCV - -export IMPERAS_TOOLS=$(pwd)/imperas.ic -export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=100" -#export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10500000" -#export OTHERFLAGS="" - -vsim -do "do wally.do buildroot buildroot testbench --lockstep +acc -GDEBUG=1" From e91d2c8b1457efbcceb0efd769a850b9b5422ba0 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Mon, 22 Jul 2024 01:19:10 -0500 Subject: [PATCH 086/219] Corrected the CRC7 code with the right sequence of instructions. --- fpga/zsbl/sd.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/fpga/zsbl/sd.c b/fpga/zsbl/sd.c index 4ffb53d67..8781dd5c3 100644 --- a/fpga/zsbl/sd.c +++ b/fpga/zsbl/sd.c @@ -1,12 +1,15 @@ #include "sd.h" #include "spi.h" +// Parallel byte update CRC7-CCITT algorithm. +// The result is the CRC7 result, left shifted over by 1 +// which is perfect, since we append a 1 at the end anyway uint8_t crc7(uint8_t prev, uint8_t in) { // CRC polynomial 0x89 - uint8_t remainder = prev & in; + uint8_t remainder = prev ^ in; remainder ^= (remainder >> 4) ^ (remainder >> 7); - remainder ^= remainder << 4; - return remainder & 0x7f; + remainder = (remainder << 1) ^ (remainder << 4); + return remainder & 0xff; } uint16_t crc16(uint16_t crc, uint8_t data) { From c4400dfeb01e2d7f794506ba8d5aceb3e613e858 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 22 Jul 2024 08:45:08 -0700 Subject: [PATCH 087/219] Fixed WARL bug on MTVEC/STVEC alignment to 64 in vectored mode --- src/privileged/csrm.sv | 4 +++- src/privileged/csrs.sv | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index a964de2ea..f86b3f6d6 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -57,6 +57,7 @@ module csrm import cvw::*; #(parameter cvw_t P) ( logic [P.XLEN-1:0] MISA_REGW, MHARTID_REGW; logic [P.XLEN-1:0] MSCRATCH_REGW, MTVAL_REGW, MCAUSE_REGW; logic [P.XLEN-1:0] MENVCFGH_REGW; + logic [P.XLEN-1:0] TVECWriteValM; logic WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM; logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM; logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM; @@ -152,7 +153,8 @@ module csrm import cvw::*; #(parameter cvw_t P) ( assign IllegalCSRMWriteReadonlyM = UngatedCSRMWriteM & (CSRAdrM == MVENDORID | CSRAdrM == MARCHID | CSRAdrM == MIMPID | CSRAdrM == MHARTID | CSRAdrM == MCONFIGPTR); // CSRs - flopenr #(P.XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[P.XLEN-1:2], 1'b0, CSRWriteValM[0]}, MTVEC_REGW); + assign TVECWriteValM = CSRWriteValM[0] ? {CSRWriteValM[P.XLEN-1:6], 6'b000001} : {CSRWriteValM[P.XLEN-1:2], 2'b00}; + flopenr #(P.XLEN) MTVECreg(clk, reset, WriteMTVECM, TVECWriteValM, MTVEC_REGW); if (P.S_SUPPORTED) begin:deleg // DELEG registers should exist flopenr #(16) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM[15:0] & MEDELEG_MASK, MEDELEG_REGW); flopenr #(12) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM[11:0] & MIDELEG_MASK, MIDELEG_REGW); diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index ebd468ad6..4797f800b 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -78,6 +78,7 @@ module csrs import cvw::*; #(parameter cvw_t P) ( logic [P.XLEN-1:0] SSCRATCH_REGW, STVAL_REGW, SCAUSE_REGW; logic [P.XLEN-1:0] SENVCFG_WriteValM; + logic [P.XLEN-1:0] TVECWriteValM; logic [63:0] STIMECMP_REGW; @@ -100,7 +101,8 @@ module csrs import cvw::*; #(parameter cvw_t P) ( assign WriteSTIMECMPHM = CSRSWriteM & (CSRAdrM == STIMECMPH) & STCE & (P.XLEN == 32); // CSRs - flopenr #(P.XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[P.XLEN-1:2], 1'b0, CSRWriteValM[0]}, STVEC_REGW); + assign TVECWriteValM = CSRWriteValM[0] ? {CSRWriteValM[P.XLEN-1:6], 6'b000001} : {CSRWriteValM[P.XLEN-1:2], 2'b00}; // could share this with MTVEC, but reduces to 4-bit AND to mask bits [5:2] + flopenr #(P.XLEN) STVECreg(clk, reset, WriteSTVECM, TVECWriteValM, STVEC_REGW); flopenr #(P.XLEN) SSCRATCHreg(clk, reset, WriteSSCRATCHM, CSRWriteValM, SSCRATCH_REGW); flopenr #(P.XLEN) SEPCreg(clk, reset, WriteSEPCM, NextEPCM, SEPC_REGW); flopenr #(P.XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, {NextCauseM[4], {(P.XLEN-5){1'b0}}, NextCauseM[3:0]}, SCAUSE_REGW); From 757cc8a5f7b39e8e336a8016356a5b252adaa502 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 22 Jul 2024 08:49:54 -0700 Subject: [PATCH 088/219] Added QuestaFunctCoverage to merge functional coverage reports --- bin/regression-wally | 54 ++++++++++++++++++++++++++++++++++++-------- sim/Makefile | 7 ++++++ 2 files changed, 52 insertions(+), 9 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index 8d67e387b..21f30c9c0 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -282,6 +282,22 @@ def addTests(tests, sim): grepfile = grepfile) configs.append(tc) +def addLockstepTestsByDir(dir, config, sim): + sim_logdir = WALLY+ "/sim/" + sim + "/logs/" + cmdPrefix="wsim --sim " + sim + " " + coverStr + " " + config + for file in os.listdir(dir): + if file.endswith(".elf"): + fullfile = os.path.join(dir, file) + sim_log = sim_logdir + config + "_" + file + grepstring = "" + tc = TestCase( + name=file, + variant=config, + cmd=cmdPrefix + " " + fullfile + " > " + sim_log, + grepstr="Mismatches : 0", + grepfile = sim_log) + configs.append(tc) + def search_log_for_text(text, grepfile): """Search through the given log file for text, returning True if it is found or False if it is not""" grepwarn = "grep -H Warning: " + grepfile @@ -332,14 +348,15 @@ args = parser.parse_args() if (args.nightly): nightMode = "--nightly"; -# sims = [defaultsim] # uncomment to use only the default simulator - sims = ["questa", "verilator", "vcs"] # uncomment to exercise all simulators + sims = ["questa", "verilator", "vcs"] # exercise all simulators; can omit a sim if no license is available else: nightMode = "" sims = [defaultsim] if (args.ccov): # only run RV64GC tests in coverage mode coverStr = '--ccov' +elif (args.fcov): # only run RV64GC tests in lockstep in coverage mode + coverStr = '--fcov' else: coverStr = '' @@ -362,10 +379,20 @@ if (args.buildroot): addTests(tests_buildrootbootlockstep, "questa") # lockstep with Questa and ImperasDV runs overnight if (args.ccov): # only run RV64GC tests on Questa in code coverage mode - addTests(tests64gc_nofp, "questa") + addTests(tests64gc_nofp, coveragesim) if (args.fp): - addTests(tests64gc_fp, "questa") -else: + addTests(tests64gc_fp, coveragesim) +elif (args.fcov): # only run RV64GC tests on Questa in lockstep in functional coverage mode + addLockstepTestsByDir(WALLY+"/tests/functcov/rv64/I", "rv64gc", coveragesim) + #sim_log = WALLY + "/sim/questa/logs/fcov.log" + #tc = TestCase( + # name="lockstep_functcov", + # variant="rv64gc", + # cmd="iterelf " + WALLY + "/tests/functcov/rv64/I > " + sim_log, + # grepstr="SUCCESS! All tests ran without failures", + # grepfile = sim_log) + #configs.append(tc) +else: for sim in sims: if (not (args.buildroot and sim == defaultsim)): # skip short buildroot sim if running long one addTests(tests_buildrootshort, sim) @@ -375,7 +402,6 @@ else: # run derivative configurations and lockstep tests in nightly regression if (args.nightly): - addTests(derivconfigtests, defaultsim) sim_log = WALLY + "/sim/questa/logs/lockstep_coverage.log" tc = TestCase( name="lockstep_coverage", @@ -393,6 +419,7 @@ if (args.nightly): grepstr="SUCCESS! All tests ran without failures", grepfile = sim_log) configs.append(tc) + addTests(derivconfigtests, defaultsim) # testfloat tests if (args.testfloat): # for testfloat alone, just run testfloat tests @@ -474,16 +501,23 @@ def main(): if args.ccov: TIMEOUT_DUR = 20*60 # seconds os.system('rm -f questa/cov/*.ucdb') - elif args.nightly in sys.argv: + elif args.fcov: + TIMEOUT_DUR = 1*60 + os.system('rm -f questa/fcov_ucdb/* questa/fcov_logs/* questa/fcov/*') + elif args.nightly: TIMEOUT_DUR = 60*1440 # 1 day - elif args.testfloat in sys.argv: + elif args.testfloat: TIMEOUT_DUR = 30*60 # seconds else: TIMEOUT_DUR = 10*60 # seconds # Scale the number of concurrent processes to the number of test cases, but # max out at a limited number of concurrent processes to not overwhelm the system - with Pool(processes=min(len(configs),multiprocessing.cpu_count())) as pool: + if (args.lockstep or args.fcov): + ImperasDVLicenseCount = 8 # limit number of concurrent processes to avoid overloading ImperasDV licenses + else: + ImperasDVLicenseCount = 10000 # effectively no license limit for non-lockstep tests + with Pool(processes=min(len(configs),multiprocessing.cpu_count(), ImperasDVLicenseCount)) as pool: num_fail = 0 results = {} for config in configs: @@ -498,6 +532,8 @@ def main(): # Coverage report if args.ccov: os.system('make QuestaCodeCoverage') + if args.fcov: + os.system('make QuestaFunctCoverage') # Count the number of failures if num_fail: print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail) diff --git a/sim/Makefile b/sim/Makefile index 891ccb213..1197dfc2e 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -30,6 +30,13 @@ QuestaCodeCoverage: questa/ucdb/rv64gc_arch64i.ucdb # vcover report -recursive questa/ucdb/cov.ucdb > questa/cov/rv64gc_recursive.rpt vcover report -details -threshH 100 -html questa/ucdb/cov.ucdb +QuestaFunctCoverage: ${SIM}/questa/fcov_ucdb/rv64gc_WALLY-COV-add.elf.ucdb + vcover merge -out ${SIM}/questa/fcov_ucdb/fcov.ucdb ${SIM}/questa/fcov_ucdb/rv64gc_WALLY-COV-add.elf.ucdb ${SIM}/questa/fcov_ucdb/rv64gc_WALLY*.ucdb -logfile ${SIM}/questa/fcov_logs/log + vcover report -details -html ${SIM}/questa/fcov_ucdb/fcov.ucdb + vcover report ${SIM}/questa/fcov_ucdb/fcov.ucdb -details -cvg > ${SIM}/questa/fcov/fcov.log + vcover report ${SIM}/questa/fcov_ucdb/fcov.ucdb -testdetails -cvg > ${SIM}/questa/fcov/fcov.testdetails.log + vcover report ${SIM}/questa/fcov_ucdb/fcov.ucdb -details -cvg | egrep "Coverpoint|Covergroup|Cross|TYPE" > ${SIM}/questa/fcov/fcov.summary.log + grep "TOTAL COVERGROUP COVERAGE" ${SIM}/questa/fcov/fcov.log imperasdv_cov: touch ${SIM}/seed0.txt From 040b359813a7aa471985f2e55735af77b8845b47 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 22 Jul 2024 08:52:19 -0700 Subject: [PATCH 089/219] Added more RV64I coverage generation --- sim/questa/wally.do | 13 ++++---- tests/testgen/covergen.py | 63 ++++++++++++++++++++++++--------------- 2 files changed, 46 insertions(+), 30 deletions(-) diff --git a/sim/questa/wally.do b/sim/questa/wally.do index e5c85b92e..c7cba4925 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -122,13 +122,14 @@ if {$FunctCoverageIndex >= 0} { set FCdefineINCLUDE_TRACE2COV "+define+INCLUDE_TRACE2COV" set FCdefineCOVER_BASE_RV64I "+define+COVER_BASE_RV64I" set FCdefineCOVER_LEVEL_DV_PR_EXT "+define+COVER_LEVEL_DV_PR_EXT" + # Uncomment various cover statements below to control which extensions get functional coverage set FCdefineCOVER_RV64I "+define+COVER_RV64I" - set FCdefineCOVER_RV64M "+define+COVER_RV64M" - set FCdefineCOVER_RV64A "+define+COVER_RV64A" - set FCdefineCOVER_RV64F "+define+COVER_RV64F" - set FCdefineCOVER_RV64D "+define+COVER_RV64D" - set FCdefineCOVER_RV64ZICSR "+define+COVER_RV64ZICSR" - set FCdefineCOVER_RV64C "+define+COVER_RV64C" + #set FCdefineCOVER_RV64M "+define+COVER_RV64M" + #set FCdefineCOVER_RV64A "+define+COVER_RV64A" + #set FCdefineCOVER_RV64F "+define+COVER_RV64F" + #set FCdefineCOVER_RV64D "+define+COVER_RV64D" + #set FCdefineCOVER_RV64ZICSR "+define+COVER_RV64ZICSR" + #set FCdefineCOVER_RV64C "+define+COVER_RV64C" set FCdefineIDV_INCLUDE_TRACE2COV "+define+IDV_INCLUDE_TRACE2COV" set FCTRACE2COV "+TRACE2COV_ENABLE=1" set FCdefineIDV_TRACE2COV "+IDV_TRACE2COV=1" diff --git a/tests/testgen/covergen.py b/tests/testgen/covergen.py index 0f7bb0d4e..06cf1bb83 100755 --- a/tests/testgen/covergen.py +++ b/tests/testgen/covergen.py @@ -31,10 +31,8 @@ def signedImm12(imm): imm = imm - 0x1000 return str(imm) -def signedImm20(imm): +def unsignedImm20(imm): imm = imm % pow(2, 20) - if (imm & 0x80000): - imm = imm - 0x100000 return str(imm) def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, xlen): @@ -43,7 +41,7 @@ def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, xlen rs1val = rs1val + 2**xlen if (rs2val < 0): rs2val = rs2val + 2**xlen - lines = lines + "li x" + str(rd) + ", " + formatstr.format(rdval) + " # initialize rd to a random value that should get changed\n" + lines = lines + "li x" + str(rd) + ", " + formatstr.format(rdval) + " # initialize rd to a random value that should get changed; helps covering rd_toggle\n" if (test in rtype): lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1\n" lines = lines + "li x" + str(rs2) + ", " + formatstr.format(rs2val) + " # initialize rs2\n" @@ -55,15 +53,16 @@ def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, xlen lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1\n" lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", " + signedImm12(immval) + " # perform operation\n" elif (test in loaditype):#["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"] - lines = lines + "auipc x" + str(rs1) + ", 0x20" + " # add upper immediate value to pc \n" - lines = lines + "addi x" + str(rs1) + ", x" + str(rs1) + ", " + signedImm12(immval) + " # add immediate to lower part of rs1\n" - lines = lines + test + " x" + str(rd) + ", " + signedImm12(immval) + "(x" + str(rs1) + ") # perform operation\n" - elif (test in stypes):#["sb", "sh", "sw", "sd"] + pass + #lines = lines + "auipc x" + str(rs1) + ", 0x20" + " # add upper immediate value to pc \n" + #lines = lines + "addi x" + str(rs1) + ", x" + str(rs1) + ", " + signedImm12(-immval) + " # add immediate to lower part of rs1\n" + #lines = lines + test + " x" + str(rd) + ", " + signedImm12(immval) + "(x" + str(rs1) + ") # perform operation\n" + elif (test in stype):#["sb", "sh", "sw", "sd"] #lines = lines + test + " x" + str(rs2) + ", " + signedImm12(immval) + "(x" + str(rs1) + ") # perform operation \n" #lines = lines + test + " x" + str(rs2) + ", " "0(x" + str(rs1) + ") # perform operation \n" #print("Error: %s type not implemented yet" % test) pass - elif (test in btypes):#["beq", "bne", "blt", "bge", "bltu", "bgeu"] + elif (test in btype):#["beq", "bne", "blt", "bge", "bltu", "bgeu"] if (randint(1,100) > 50): rs1val = rs2val lines = lines + "# same values in both registers\n" @@ -75,6 +74,18 @@ def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, xlen lines = lines + "some_label_for_sb_types_" + str(immval) + ":\n" lines = lines + "addi x0, x2, 2\n" lines = lines + "nop\nnop\nnop\nnop\nnop\n" + elif (test in jtype):#["jal"] + lines = lines + "jal x" + str(rd) + ", 1f # perform operation\n" + lines = lines + "nop\n" + lines = lines + "1:\n" + elif (test in jalrtype):#["jalr"] + lines = lines + "la x" + str(rs1) + ", 1f\n" + lines = lines + "addi x" + str(rs1) + ", x" + str(rs1) + ", " + signedImm12(-immval) + " # add immediate to lower part of rs1\n" + lines = lines + "jalr x" + str(rd) + ", x" + str(rs1) + ", " + signedImm12(immval) + " # perform operation\n" + lines = lines + "nop\n" + lines = lines + "1:\n" + elif (test in utype):#["lui", "auipc"] + lines = lines + test + " x" + str(rd) + ", " + unsignedImm20(immval) + " # perform operation\n" else: pass #print("Error: %s type not implemented yet" % test) @@ -229,6 +240,11 @@ def make_cr_rs1_rs2_sign(test, xlen): desc = "cr_rs1_rs2 (Test source rs1 = " + hex(rs1val) + " rs2 = " + hex(rs2val) + ")" writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, xlen) +def make_imm_zero(test, xlen): + [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize() + desc = "cp_imm_zero" + writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, 0, rdval, test, xlen) + def write_tests(coverpoints, test, xlen): for coverpoint in coverpoints: if (coverpoint == "cp_asm_count"): @@ -280,7 +296,7 @@ def write_tests(coverpoints, test, xlen): elif (coverpoint == "cp_rd_toggle"): pass #TODO toggle not needed and seems to be covered by other things elif (coverpoint == "cp_imm_sign"): - pass #TODO + make_imm_zero(test, xlen) elif (coverpoint == "cr_rs1_imm"): pass #TODO (not if crosses are not needed) elif (coverpoint == "cp_imm_ones_zeros"): @@ -288,7 +304,7 @@ def write_tests(coverpoints, test, xlen): elif (coverpoint == "cp_mem_hazard"): pass #TODO elif (coverpoint == "cp_imm_zero"): - pass #TODO + make_imm_zero(test, xlen) elif (coverpoint == "cp_mem_unaligned"): pass #TODO elif (coverpoint == "cp_offset"): @@ -338,8 +354,11 @@ rtype = ["add", "sub", "sll", "slt", "sltu", "xor", "srl", "sra", "or", "and", loaditype = ["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"] shiftitype = ["slli", "srli", "srai"] itype = ["addi", "slti", "sltiu", "xori", "ori", "andi"] -stypes = ["sb", "sh", "sw", "sd"] -btypes = ["beq", "bne", "blt", "bge", "bltu", "bgeu"] +stype = ["sb", "sh", "sw", "sd"] +btype = ["beq", "bne", "blt", "bge", "bltu", "bgeu"] +jtype = ["jal"] +jalrtype = ["jalr"] +utype = ["lui", "auipc"] # TODO: auipc missing, check whatelse is missing in ^these^ types coverpoints = getcovergroups(coverdefdir, coverfiles) @@ -362,12 +381,11 @@ for xlen in xlens: else: storecmd = "sd" wordsize = 8 + WALLY = os.environ.get('WALLY') + pathname = WALLY+"/tests/functcov/rv" + str(xlen) + "/I/" + cmd = "mkdir -p " + pathname + " ; rm -f " + pathname + "/*" # make directory and remove old tests in dir + os.system(cmd) for test in coverpoints.keys(): -# pathname = "../wally-riscv-arch-test/riscv-test-suite/rv" + str(xlen) + "i_m/I/" - WALLY = os.environ.get('WALLY') - pathname = WALLY+"/tests/functcov/rv" + str(xlen) + "/I/" - cmd = "mkdir -p " + pathname - os.system(cmd) basename = "WALLY-COV-" + test fname = pathname + "/" + basename + ".S" @@ -375,9 +393,9 @@ for xlen in xlens: f = open(fname, "w") line = "///////////////////////////////////////////\n" f.write(line) - lines="// "+fname+ "\n// " + author + "\n" - f.write(lines) - line ="// Created " + str(datetime.now()) + line="// "+fname+ "\n// " + author + "\n" + f.write(line) + line ="// Created " + str(datetime.now()) + "\n" f.write(line) # insert generic header @@ -401,9 +419,6 @@ for xlen in xlens: f.write(line) # Finish -# lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n" -# lines = lines + "\nRV_COMPLIANCE_DATA_END\n" - f.write(lines) f.close() From 4c46315907b094190f3092d19f005942c8f620a7 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 22 Jul 2024 09:19:56 -0700 Subject: [PATCH 090/219] Fixed argument name in regression-wally --- bin/regression-wally | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/bin/regression-wally b/bin/regression-wally index 21f30c9c0..5a374b2d9 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -513,7 +513,8 @@ def main(): # Scale the number of concurrent processes to the number of test cases, but # max out at a limited number of concurrent processes to not overwhelm the system - if (args.lockstep or args.fcov): + # right now fcov, ccov, nightly all use Imperas + if (args.ccov or args.fcov or args.nightly): ImperasDVLicenseCount = 8 # limit number of concurrent processes to avoid overloading ImperasDV licenses else: ImperasDVLicenseCount = 10000 # effectively no license limit for non-lockstep tests From 556c210e76158e69e3308f755f58134f1798de17 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 22 Jul 2024 12:19:37 -0500 Subject: [PATCH 091/219] Added option to use rvvi ila --- fpga/generator/wally.tcl | 1 + 1 file changed, 1 insertion(+) diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index eff0a6cb9..9df775646 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -90,6 +90,7 @@ write_verilog -force -mode funcsim sim/syn-funcsim.v if {$board=="ArtyA7"} { source ../constraints/small-debug.xdc + #source ../constraints/small-debug-rvvi.xdc } else { # source ../constraints/vcu-small-debug.xdc From 00c30239bfaf5a78603d90151c37cbfbf7a8d7d0 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 22 Jul 2024 12:22:41 -0500 Subject: [PATCH 092/219] Cleaned up rvvisynth.sv --- src/rvvi/rvvisynth.sv | 126 ------------------------------------------ 1 file changed, 126 deletions(-) diff --git a/src/rvvi/rvvisynth.sv b/src/rvvi/rvvisynth.sv index 7700cc615..cbf7c30bf 100644 --- a/src/rvvi/rvvisynth.sv +++ b/src/rvvi/rvvisynth.sv @@ -69,132 +69,6 @@ module rvvisynth import cvw::*; #(parameter cvw_t P, logic [10+2*P.XLEN-1:0] Registers; logic [MAX_CSRS*(P.XLEN+12)-1:0] CSRs; - // get signals from the core. - if (`FPGA) begin -/* -----\/----- EXCLUDED -----\/----- - assign StallE = fpgaTop.wallypipelinedsoc.core.StallE; - assign StallM = fpgaTop.wallypipelinedsoc.core.StallM; - assign StallW = fpgaTop.wallypipelinedsoc.core.StallW; - assign FlushE = fpgaTop.wallypipelinedsoc.core.FlushE; - assign FlushM = fpgaTop.wallypipelinedsoc.core.FlushM; - assign FlushW = fpgaTop.wallypipelinedsoc.core.FlushW; - assign InstrValidM = fpgaTop.wallypipelinedsoc.core.ieu.InstrValidM; - assign InstrRawD = fpgaTop.wallypipelinedsoc.core.ifu.InstrRawD; - assign PCM = fpgaTop.wallypipelinedsoc.core.ifu.PCM; - assign Mcycle = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0]; - assign Minstret = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]; - assign TrapM = fpgaTop.wallypipelinedsoc.core.TrapM; - assign PrivilegeModeW = fpgaTop.wallypipelinedsoc.core.priv.priv.privmode.PrivilegeModeW; - assign GPRAddr = fpgaTop.wallypipelinedsoc.core.ieu.dp.regf.a3; - assign GPRWen = fpgaTop.wallypipelinedsoc.core.ieu.dp.regf.we3; - assign GPRValue = fpgaTop.wallypipelinedsoc.core.ieu.dp.regf.wd3; - assign FPRAddr = fpgaTop.wallypipelinedsoc.core.fpu.fpu.fregfile.a4; - assign FPRWen = fpgaTop.wallypipelinedsoc.core.fpu.fpu.fregfile.we4; - assign FPRValue = fpgaTop.wallypipelinedsoc.core.fpu.fpu.fregfile.wd4; - - assign CSRArray[0] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MSTATUS_REGW; // 12'h300 - assign CSRArray[1] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MSTATUSH_REGW; // 12'h310 - assign CSRArray[2] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MTVEC_REGW; // 12'h305 - assign CSRArray[3] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MEPC_REGW; // 12'h341 - assign CSRArray[4] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MCOUNTEREN_REGW; // 12'h306 - assign CSRArray[5] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW; // 12'h320 - assign CSRArray[6] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MEDELEG_REGW; // 12'h302 - assign CSRArray[7] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h303 - assign CSRArray[8] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIP_REGW; // 12'h344 - assign CSRArray[9] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIE_REGW; // 12'h304 - assign CSRArray[10] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MISA_REGW; // 12'h301 - assign CSRArray[11] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MENVCFG_REGW; // 12'h30A - assign CSRArray[12] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MHARTID_REGW; // 12'hF14 - assign CSRArray[13] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MSCRATCH_REGW; // 12'h340 - assign CSRArray[14] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MCAUSE_REGW; // 12'h342 - assign CSRArray[15] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MTVAL_REGW; // 12'h343 - assign CSRArray[16] = 0; // 12'hF11 - assign CSRArray[17] = 0; // 12'hF12 - assign CSRArray[18] = {{P.XLEN-12{1'b0}}, 12'h100}; //P.XLEN'h100; // 12'hF13 - assign CSRArray[19] = 0; // 12'hF15 - assign CSRArray[20] = 0; // 12'h34A - // supervisor CSRs - assign CSRArray[21] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW; // 12'h100 - assign CSRArray[22] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIE_REGW & 12'h222; // 12'h104 - assign CSRArray[23] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.STVEC_REGW; // 12'h105 - assign CSRArray[24] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SEPC_REGW; // 12'h141 - assign CSRArray[25] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW; // 12'h106 - assign CSRArray[26] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW; // 12'h10A - assign CSRArray[27] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SATP_REGW; // 12'h180 - assign CSRArray[28] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW; // 12'h140 - assign CSRArray[29] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.STVAL_REGW; // 12'h143 - assign CSRArray[30] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; // 12'h142 - assign CSRArray[31] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h144 - assign CSRArray[32] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW; // 12'h14D - // user CSRs - assign CSRArray[33] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FFLAGS_REGW; // 12'h001 - assign CSRArray[34] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FRM_REGW; // 12'h002 - assign CSRArray[35] = {fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FRM_REGW, fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; // 12'h003 - -----/\----- EXCLUDED -----/\----- */ - end else begin // if (`FPGA) -/* -----\/----- EXCLUDED -----\/----- - assign StallE = dut.core.StallE; - assign StallM = dut.core.StallM; - assign StallW = dut.core.StallW; - assign FlushE = dut.core.FlushE; - assign FlushM = dut.core.FlushM; - assign FlushW = dut.core.FlushW; - assign InstrValidM = dut.core.ieu.InstrValidM; - assign InstrRawD = dut.core.ifu.InstrRawD; - assign PCM = dut.core.ifu.PCM; - assign Mcycle = dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0]; - assign Minstret = dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]; - assign TrapM = dut.core.TrapM; - assign PrivilegeModeW = dut.core.priv.priv.privmode.PrivilegeModeW; - assign GPRAddr = dut.core.ieu.dp.regf.a3; - assign GPRWen = dut.core.ieu.dp.regf.we3; - assign GPRValue = dut.core.ieu.dp.regf.wd3; - assign FPRAddr = dut.core.fpu.fpu.fregfile.a4; - assign FPRWen = dut.core.fpu.fpu.fregfile.we4; - assign FPRValue = dut.core.fpu.fpu.fregfile.wd4; - - assign CSRArray[0] = dut.core.priv.priv.csr.csrm.MSTATUS_REGW; // 12'h300 - assign CSRArray[1] = dut.core.priv.priv.csr.csrm.MSTATUSH_REGW; // 12'h310 - assign CSRArray[2] = dut.core.priv.priv.csr.csrm.MTVEC_REGW; // 12'h305 - assign CSRArray[3] = dut.core.priv.priv.csr.csrm.MEPC_REGW; // 12'h341 - assign CSRArray[4] = dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW; // 12'h306 - assign CSRArray[5] = dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW; // 12'h320 - assign CSRArray[6] = dut.core.priv.priv.csr.csrm.MEDELEG_REGW; // 12'h302 - assign CSRArray[7] = dut.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h303 - assign CSRArray[8] = dut.core.priv.priv.csr.csrm.MIP_REGW; // 12'h344 - assign CSRArray[9] = dut.core.priv.priv.csr.csrm.MIE_REGW; // 12'h304 - assign CSRArray[10] = dut.core.priv.priv.csr.csrm.MISA_REGW; // 12'h301 - assign CSRArray[11] = dut.core.priv.priv.csr.csrm.MENVCFG_REGW; // 12'h30A - assign CSRArray[12] = dut.core.priv.priv.csr.csrm.MHARTID_REGW; // 12'hF14 - assign CSRArray[13] = dut.core.priv.priv.csr.csrm.MSCRATCH_REGW; // 12'h340 - assign CSRArray[14] = dut.core.priv.priv.csr.csrm.MCAUSE_REGW; // 12'h342 - assign CSRArray[15] = dut.core.priv.priv.csr.csrm.MTVAL_REGW; // 12'h343 - assign CSRArray[16] = 0; // 12'hF11 - assign CSRArray[17] = 0; // 12'hF12 - assign CSRArray[18] = {{P.XLEN-12{1'b0}}, 12'h100}; //P.XLEN'h100; // 12'hF13 - assign CSRArray[19] = 0; // 12'hF15 - assign CSRArray[20] = 0; // 12'h34A - // supervisor CSRs - assign CSRArray[21] = dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW; // 12'h100 - assign CSRArray[22] = dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222; // 12'h104 - assign CSRArray[23] = dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW; // 12'h105 - assign CSRArray[24] = dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW; // 12'h141 - assign CSRArray[25] = dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW; // 12'h106 - assign CSRArray[26] = dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW; // 12'h10A - assign CSRArray[27] = dut.core.priv.priv.csr.csrs.csrs.SATP_REGW; // 12'h180 - assign CSRArray[28] = dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW; // 12'h140 - assign CSRArray[29] = dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW; // 12'h143 - assign CSRArray[30] = dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; // 12'h142 - assign CSRArray[31] = dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & dut.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h144 - assign CSRArray[32] = dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW; // 12'h14D - // user CSRs - assign CSRArray[33] = dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW; // 12'h001 - assign CSRArray[34] = dut.core.priv.priv.csr.csru.csru.FRM_REGW; // 12'h002 - assign CSRArray[35] = {dut.core.priv.priv.csr.csru.csru.FRM_REGW, dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; // 12'h003 - -----/\----- EXCLUDED -----/\----- */ - end - - // assign XLENZeros = '0; // start out easy and just populate Required From a506d76149f83faeb96acb52efd10c4fe6265ea1 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Mon, 22 Jul 2024 12:36:39 -0500 Subject: [PATCH 093/219] Removed the old SDC. Added a second SPI peripheral that now will be used to control the SD card. SPI peripheral now outputs SPICLK. Removed references to the now non-existent external SDC in uncore. Removed all of the AXI Xilinx IP. --- fpga/src/fpgaTopArtyA7.sv | 828 ++++----------------------------- src/uncore/spi_apb.sv | 17 +- src/uncore/uncore.sv | 47 +- src/wally/wallypipelinedsoc.sv | 10 +- 4 files changed, 144 insertions(+), 758 deletions(-) diff --git a/fpga/src/fpgaTopArtyA7.sv b/fpga/src/fpgaTopArtyA7.sv index 9ddf958a7..6a2f055ba 100644 --- a/fpga/src/fpgaTopArtyA7.sv +++ b/fpga/src/fpgaTopArtyA7.sv @@ -29,38 +29,43 @@ import cvw::*; module fpgaTop - (input default_100mhz_clk, -(* mark_debug = "true" *) input resetn, - input south_reset, + (input default_100mhz_clk, + input resetn, + input south_reset, - input [3:0] GPI, - output [4:0] GPO, + // GPIO signals + input [3:0] GPI, + output [4:0] GPO, - input UARTSin, - output UARTSout, + // UART Signals + input UARTSin, + output UARTSout, - inout [3:0] SDCDat, - output SDCCLK, - inout SDCCmd, - input SDCCD, + // SDC Signals connecting to an SPI peripheral + input [3:0] SDCDat, + output SDCCLK, + output SDCCmd, + output SDCCD, - inout [15:0] ddr3_dq, - inout [1:0] ddr3_dqs_n, - inout [1:0] ddr3_dqs_p, - output [13:0] ddr3_addr, - output [2:0] ddr3_ba, - output ddr3_ras_n, - output ddr3_cas_n, - output ddr3_we_n, - output ddr3_reset_n, - output [0:0] ddr3_ck_p, - output [0:0] ddr3_ck_n, - output [0:0] ddr3_cke, - output [0:0] ddr3_cs_n, - output [1:0] ddr3_dm, - output [0:0] ddr3_odt + // Memory signals + inout [15:0] ddr3_dq, + inout [1:0] ddr3_dqs_n, + inout [1:0] ddr3_dqs_p, + output [13:0] ddr3_addr, + output [2:0] ddr3_ba, + output ddr3_ras_n, + output ddr3_cas_n, + output ddr3_we_n, + output ddr3_reset_n, + output [0:0] ddr3_ck_p, + output [0:0] ddr3_ck_n, + output [0:0] ddr3_cke, + output [0:0] ddr3_cs_n, + output [1:0] ddr3_dm, + output [0:0] ddr3_odt ); + // MMCM Signals wire CPUCLK; wire c0_ddr4_ui_clk_sync_rst; wire bus_struct_reset; @@ -69,6 +74,7 @@ module fpgaTop wire peripheral_aresetn; wire mb_reset; + // AHB Signals from Wally wire HCLKOpen; wire HRESETnOpen; wire [63:0] HRDATAEXT; @@ -87,12 +93,10 @@ module fpgaTop wire [3:0] HPROT; wire HMASTLOCK; + // GPIO Signals wire [31:0] GPIOIN, GPIOOUT, GPIOEN; - wire SDCCmdIn; - wire SDCCmdOE; - wire SDCCmdOut; - + // AHB to AXI Bridge Signals wire [3:0] m_axi_awid; wire [7:0] m_axi_awlen; wire [2:0] m_axi_awsize; @@ -100,40 +104,40 @@ module fpgaTop wire [3:0] m_axi_awcache; wire [31:0] m_axi_awaddr; wire [2:0] m_axi_awprot; - wire m_axi_awvalid; - wire m_axi_awready; - wire m_axi_awlock; + wire m_axi_awvalid; + wire m_axi_awready; + wire m_axi_awlock; wire [63:0] m_axi_wdata; wire [7:0] m_axi_wstrb; - wire m_axi_wlast; - wire m_axi_wvalid; - wire m_axi_wready; + wire m_axi_wlast; + wire m_axi_wvalid; + wire m_axi_wready; wire [3:0] m_axi_bid; wire [1:0] m_axi_bresp; - wire m_axi_bvalid; - wire m_axi_bready; + wire m_axi_bvalid; + wire m_axi_bready; wire [3:0] m_axi_arid; wire [7:0] m_axi_arlen; wire [2:0] m_axi_arsize; wire [1:0] m_axi_arburst; wire [2:0] m_axi_arprot; wire [3:0] m_axi_arcache; - wire m_axi_arvalid; + wire m_axi_arvalid; wire [31:0] m_axi_araddr; wire m_axi_arlock; - wire m_axi_arready; + wire m_axi_arready; wire [3:0] m_axi_rid; wire [63:0] m_axi_rdata; wire [1:0] m_axi_rresp; - wire m_axi_rvalid; - wire m_axi_rlast; - wire m_axi_rready; + wire m_axi_rvalid; + wire m_axi_rlast; + wire m_axi_rready; + // AXI Signals going out of Clock Converter wire [3:0] BUS_axi_arregion; wire [3:0] BUS_axi_arqos; wire [3:0] BUS_axi_awregion; wire [3:0] BUS_axi_awqos; - wire [3:0] BUS_axi_awid; wire [7:0] BUS_axi_awlen; wire [2:0] BUS_axi_awsize; @@ -173,250 +177,10 @@ module fpgaTop wire BUSCLK; wire sdio_reset_open; - // Crossbar to Bus ------------------------------------------------ - - wire s00_axi_aclk; - wire s00_axi_aresetn; - wire [3:0] s00_axi_awid; - wire [31:0]s00_axi_awaddr; - wire [7:0]s00_axi_awlen; - wire [2:0]s00_axi_awsize; - wire [1:0]s00_axi_awburst; - wire [0:0]s00_axi_awlock; - wire [3:0]s00_axi_awcache; - wire [2:0]s00_axi_awprot; - wire [3:0]s00_axi_awregion; - wire [3:0]s00_axi_awqos; - wire s00_axi_awvalid; - wire s00_axi_awready; - wire [63:0]s00_axi_wdata; - wire [7:0]s00_axi_wstrb; - wire s00_axi_wlast; - wire s00_axi_wvalid; - wire s00_axi_wready; - wire [1:0]s00_axi_bresp; - wire s00_axi_bvalid; - wire s00_axi_bready; - wire [3:0] s00_axi_arid; - wire [31:0]s00_axi_araddr; - wire [7:0]s00_axi_arlen; - wire [2:0]s00_axi_arsize; - wire [1:0]s00_axi_arburst; - wire [0:0]s00_axi_arlock; - wire [3:0]s00_axi_arcache; - wire [2:0]s00_axi_arprot; - wire [3:0]s00_axi_arregion; - wire [3:0]s00_axi_arqos; - wire s00_axi_arvalid; - wire s00_axi_arready; - wire [63:0]s00_axi_rdata; - wire [1:0]s00_axi_rresp; - wire s00_axi_rlast; - wire s00_axi_rvalid; - wire s00_axi_rready; - - wire [3:0] s00_axi_bid; - wire [3:0] s00_axi_rid; - - // 64to32 dwidth converter input interface------------------------- - wire s01_axi_aclk; - wire s01_axi_aresetn; - wire [3:0]s01_axi_awid; - wire [31:0]s01_axi_awaddr; - wire [7:0]s01_axi_awlen; - wire [2:0]s01_axi_awsize; - wire [1:0]s01_axi_awburst; - wire [0:0]s01_axi_awlock; - wire [3:0]s01_axi_awcache; - wire [2:0]s01_axi_awprot; - wire [3:0]s01_axi_awregion; - wire [3:0]s01_axi_awqos; // qos signals need to be 0 for SDC - wire s01_axi_awvalid; - wire s01_axi_awready; - wire [63:0]s01_axi_wdata; - wire [7:0]s01_axi_wstrb; - wire s01_axi_wlast; - wire s01_axi_wvalid; - wire s01_axi_wready; - wire [1:0]s01_axi_bresp; - wire s01_axi_bvalid; - wire s01_axi_bready; - wire [31:0]s01_axi_araddr; - wire [7:0]s01_axi_arlen; - wire [3:0] s01_axi_arid; - wire [2:0]s01_axi_arsize; - wire [1:0]s01_axi_arburst; - wire [0:0]s01_axi_arlock; - wire [3:0]s01_axi_arcache; - wire [2:0]s01_axi_arprot; - wire [3:0]s01_axi_arregion; - wire [3:0]s01_axi_arqos; // - wire s01_axi_arvalid; - wire s01_axi_arready; - wire [63:0]s01_axi_rdata; - wire [1:0]s01_axi_rresp; - wire s01_axi_rlast; - wire s01_axi_rvalid; - wire s01_axi_rready; - - // Output Interface - wire [31:0]axi4in_axi_awaddr; - wire [7:0]axi4in_axi_awlen; - wire [2:0]axi4in_axi_awsize; - wire [1:0]axi4in_axi_awburst; - wire [0:0]axi4in_axi_awlock; - wire [3:0]axi4in_axi_awcache; - wire [2:0]axi4in_axi_awprot; - wire [3:0]axi4in_axi_awregion; - wire [3:0]axi4in_axi_awqos; - wire axi4in_axi_awvalid; - wire axi4in_axi_awready; - wire [31:0]axi4in_axi_wdata; - wire [3:0]axi4in_axi_wstrb; - wire axi4in_axi_wlast; - wire axi4in_axi_wvalid; - wire axi4in_axi_wready; - wire [1:0]axi4in_axi_bresp; - wire axi4in_axi_bvalid; - wire axi4in_axi_bready; - wire [31:0]axi4in_axi_araddr; - wire [7:0]axi4in_axi_arlen; - wire [2:0]axi4in_axi_arsize; - wire [1:0]axi4in_axi_arburst; - wire [0:0]axi4in_axi_arlock; - wire [3:0]axi4in_axi_arcache; - wire [2:0]axi4in_axi_arprot; - wire [3:0]axi4in_axi_arregion; - wire [3:0]axi4in_axi_arqos; - wire axi4in_axi_arvalid; - wire axi4in_axi_arready; - wire [31:0]axi4in_axi_rdata; - wire [1:0]axi4in_axi_rresp; - wire axi4in_axi_rlast; - wire axi4in_axi_rvalid; - wire axi4in_axi_rready; - - // AXI4 to AXI4-Lite Protocol converter output - wire [31:0]SDCin_axi_awaddr; - wire [2:0]SDCin_axi_awprot; - wire SDCin_axi_awvalid; - wire SDCin_axi_awready; - wire [31:0]SDCin_axi_wdata; - wire [3:0]SDCin_axi_wstrb; - wire SDCin_axi_wvalid; - wire SDCin_axi_wready; - wire [1:0]SDCin_axi_bresp; - wire SDCin_axi_bvalid; - wire SDCin_axi_bready; - wire [31:0]SDCin_axi_araddr; - wire [2:0]SDCin_axi_arprot; - wire SDCin_axi_arvalid; - wire SDCin_axi_arready; - wire [31:0]SDCin_axi_rdata; - wire [1:0]SDCin_axi_rresp; - wire SDCin_axi_rvalid; - wire SDCin_axi_rready; - // ---------------------------------------------------------------- - - // 32to64 dwidth converter input interface ----------------------- - wire [31:0]SDCout_axi_awaddr; - wire [7:0]SDCout_axi_awlen; - wire [2:0]SDCout_axi_awsize; - wire [1:0]SDCout_axi_awburst; - wire [0:0]SDCout_axi_awlock; - wire [3:0]SDCout_axi_awcache; - wire [2:0]SDCout_axi_awprot; - wire [3:0]SDCout_axi_awregion; - wire [3:0]SDCout_axi_awqos; - wire SDCout_axi_awvalid; - wire SDCout_axi_awready; - wire [31:0]SDCout_axi_wdata; - wire [3:0]SDCout_axi_wstrb; - wire SDCout_axi_wlast; - wire SDCout_axi_wvalid; - wire SDCout_axi_wready; - wire [1:0]SDCout_axi_bresp; - wire SDCout_axi_bvalid; - wire SDCout_axi_bready; - wire [31:0]SDCout_axi_araddr; - wire [7:0]SDCout_axi_arlen; - wire [2:0]SDCout_axi_arsize; - wire [1:0]SDCout_axi_arburst; - wire [0:0]SDCout_axi_arlock; - wire [3:0]SDCout_axi_arcache; - wire [2:0]SDCout_axi_arprot; - wire [3:0]SDCout_axi_arregion; - wire [3:0]SDCout_axi_arqos; - wire SDCout_axi_arvalid; - wire SDCout_axi_arready; - wire [31:0]SDCout_axi_rdata; - wire [1:0]SDCout_axi_rresp; - wire SDCout_axi_rlast; - wire SDCout_axi_rvalid; - wire SDCout_axi_rready; - - // Output Interface - wire [3:0]m01_axi_awid; - wire [31:0]m01_axi_awaddr; - wire [7:0]m01_axi_awlen; - wire [2:0]m01_axi_awsize; - wire [1:0]m01_axi_awburst; - wire [0:0]m01_axi_awlock; - wire [3:0]m01_axi_awcache; - wire [2:0]m01_axi_awprot; - wire [3:0]m01_axi_awregion; - wire [3:0]m01_axi_awqos; - wire m01_axi_awvalid; - wire m01_axi_awready; - wire [63:0]m01_axi_wdata; - wire [7:0]m01_axi_wstrb; - wire m01_axi_wlast; - wire m01_axi_wvalid; - wire m01_axi_wready; - wire [3:0] m01_axi_bid; - wire [1:0]m01_axi_bresp; - wire m01_axi_bvalid; - wire m01_axi_bready; - wire [3:0] m01_axi_arid; - wire [31:0]m01_axi_araddr; - wire [7:0]m01_axi_arlen; - wire [2:0]m01_axi_arsize; - wire [1:0]m01_axi_arburst; - wire [0:0]m01_axi_arlock; - wire [3:0]m01_axi_arcache; - wire [2:0]m01_axi_arprot; - wire [3:0]m01_axi_arregion; - wire [3:0]m01_axi_arqos; - wire m01_axi_arvalid; - wire m01_axi_arready; - wire [3:0] m01_axi_rid; - wire [63:0]m01_axi_rdata; - wire [1:0]m01_axi_rresp; - wire m01_axi_rlast; - wire m01_axi_rvalid; - wire m01_axi_rready; - - // Old SDC input - // wire [3:0] SDCDatIn; - - // New SDC Command IOBUF connections - wire sd_cmd_i; - wire sd_cmd_reg_o; - wire sd_cmd_reg_t; - - // SD Card Interrupt signal - wire SDCIntr; - - // New SDC Data IOBUF connections - wire [3:0] sd_dat_i; - wire [3:0] sd_dat_reg_o; - wire sd_dat_reg_t; - - - wire c0_init_calib_complete; + wire c0_init_calib_complete; wire dbg_clk; wire [511 : 0] dbg_bus; - wire ui_clk_sync_rst; + wire ui_clk_sync_rst; wire CLK208; wire clk167; @@ -425,9 +189,9 @@ module fpgaTop wire app_sr_active; wire app_ref_ack; wire app_zq_ack; - wire mmcm_locked; + wire mmcm_locked; wire [11:0] device_temp; - wire mmcm1_locked; + wire mmcm1_locked; assign GPIOIN = {28'b0, GPI}; @@ -436,6 +200,11 @@ module fpgaTop assign cpu_reset = bus_struct_reset; assign calib = c0_init_calib_complete; + logic [3:0] SDCCS; + assign SDCCD = SDCCS[0]; + logic SDCIn; + assign SDCIn = SDCDat[0]; + // mmcm // the ddr3 mig7 requires 2 input clocks @@ -449,26 +218,7 @@ module fpgaTop .reset(1'b0), .locked(mmcm1_locked), .clk_in1(default_100mhz_clk)); - -/* -----\/----- EXCLUDED -----\/----- - // SD Card Tristate - IOBUF iobufSDCMD(.T(~SDCCmdOE), // iobuf's T is active low - .I(SDCCmdOut), - .O(SDCCmdIn), - .IO(SDCCmd)); - -----/\----- EXCLUDED -----/\----- */ - // IOBUFS for new SDC peripheral - IOBUF IOBUF_cmd (.O(sd_cmd_i), .IO(SDCCmd), .I(sd_cmd_reg_o), .T(sd_cmd_reg_t)); - genvar i; - generate - for (i = 0; i < 4; i = i + 1) begin - IOBUF iobufSDCDat(.T(sd_dat_reg_t), - .I(sd_dat_reg_o[i]), - .O(sd_dat_i[i]), - .IO(SDCDat[i]) ); - end - endgenerate // reset controller XILINX IP @@ -484,11 +234,9 @@ module fpgaTop .interconnect_aresetn(interconnect_aresetn), //open .peripheral_aresetn(peripheral_aresetn)); - // wally - // RT and JP: FIXME add sdc interrupt and HSELEXTSDC, remove old sdc after the new sdc ahb version is implemented - `include "parameter-defs.vh" - + + // Wally wallypipelinedsoc #(P) wallypipelinedsoc(.clk(CPUCLK), .reset_ext(bus_struct_reset), .reset(), .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, @@ -496,7 +244,7 @@ module fpgaTop .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, - .UARTSin, .UARTSout, .SDCIntr); + .UARTSin, .UARTSout, .SDCIn, .SDCCmd, .SDCCS, .SDCCLK); // ahb lite to axi bridge @@ -551,432 +299,49 @@ module fpgaTop .m_axi_rlast(m_axi_rlast), .m_axi_rready(m_axi_rready)); - // AXI Crossbar for arbitrating the SDC and CPU -------------- - xlnx_axi_crossbar xlnx_axi_crossbar_0 - (.aclk(CPUCLK), - .aresetn(peripheral_aresetn), - - // Connect Masters - .s_axi_awid({4'b1000, m_axi_awid}), - .s_axi_awaddr({m01_axi_awaddr, m_axi_awaddr}), - .s_axi_awlen({m01_axi_awlen, m_axi_awlen}), - .s_axi_awsize({m01_axi_awsize, m_axi_awsize}), - .s_axi_awburst({m01_axi_awburst, m_axi_awburst}), - .s_axi_awlock({m01_axi_awlock, m_axi_awlock}), - .s_axi_awcache({m01_axi_awcache, m_axi_awcache}), - .s_axi_awprot({m01_axi_awprot, m_axi_awprot}), - .s_axi_awqos(8'b0), - .s_axi_awvalid({m01_axi_awvalid, m_axi_awvalid}), - .s_axi_awready({m01_axi_awready, m_axi_awready}), - .s_axi_wdata({m01_axi_wdata, m_axi_wdata}), - .s_axi_wstrb({m01_axi_wstrb, m_axi_wstrb}), - .s_axi_wlast({m01_axi_wlast, m_axi_wlast}), - .s_axi_wvalid({m01_axi_wvalid, m_axi_wvalid}), - .s_axi_wready({m01_axi_wready, m_axi_wready}), - .s_axi_bid({m01_axi_bid, m_axi_bid}), - .s_axi_bresp({m01_axi_bresp, m_axi_bresp}), - .s_axi_bvalid({m01_axi_bvalid, m_axi_bvalid}), - .s_axi_bready({m01_axi_bready, m_axi_bready}), - .s_axi_arid({4'b1000, m_axi_arid}), - .s_axi_araddr({m01_axi_araddr, m_axi_araddr}), - .s_axi_arlen({m01_axi_arlen, m_axi_arlen}), - .s_axi_arsize({m01_axi_arsize, m_axi_arsize}), - .s_axi_arburst({m01_axi_arburst, m_axi_arburst}), - .s_axi_arlock({m01_axi_arlock, m_axi_arlock}), - .s_axi_arcache({m01_axi_arcache, m_axi_arcache}), - .s_axi_arprot({m01_axi_arprot, m_axi_arprot}), - .s_axi_arqos(8'b0), - .s_axi_arvalid({m01_axi_arvalid, m_axi_arvalid}), - .s_axi_arready({m01_axi_arready, m_axi_arready}), - .s_axi_rid({m01_axi_rid, m_axi_rid}), - .s_axi_rdata({m01_axi_rdata, m_axi_rdata}), - .s_axi_rresp({m01_axi_rresp, m_axi_rresp}), - .s_axi_rlast({m01_axi_rlast, m_axi_rlast}), - .s_axi_rvalid({m01_axi_rvalid, m_axi_rvalid}), - .s_axi_rready({m01_axi_rready, m_axi_rready}), - - // Connect Slaves - .m_axi_awid({s01_axi_awid, s00_axi_awid}), - .m_axi_awlen({s01_axi_awlen, s00_axi_awlen}), - .m_axi_awsize({s01_axi_awsize, s00_axi_awsize}), - .m_axi_awburst({s01_axi_awburst, s00_axi_awburst}), - .m_axi_awcache({s01_axi_awcache, s00_axi_awcache}), - .m_axi_awaddr({s01_axi_awaddr, s00_axi_awaddr}), - .m_axi_awprot({s01_axi_awprot, s00_axi_awprot}), - .m_axi_awregion({s01_axi_awregion, s00_axi_awregion}), - .m_axi_awqos({s01_axi_awqos, s00_axi_awqos}), - .m_axi_awvalid({s01_axi_awvalid, s00_axi_awvalid}), - .m_axi_awready({s01_axi_awready, s00_axi_awready}), - .m_axi_awlock({s01_axi_awlock, s00_axi_awlock}), - .m_axi_wdata({s01_axi_wdata, s00_axi_wdata}), - .m_axi_wstrb({s01_axi_wstrb, s00_axi_wstrb}), - .m_axi_wlast({s01_axi_wlast, s00_axi_wlast}), - .m_axi_wvalid({s01_axi_wvalid, s00_axi_wvalid}), - .m_axi_wready({s01_axi_wready, s00_axi_wready}), - .m_axi_bid({4'b1000, s00_axi_bid}), - .m_axi_bresp({s01_axi_bresp, s00_axi_bresp}), - .m_axi_bvalid({s01_axi_bvalid, s00_axi_bvalid}), - .m_axi_bready({s01_axi_bready, s00_axi_bready}), - .m_axi_arid({s01_axi_arid, s00_axi_arid}), - .m_axi_arlen({s01_axi_arlen, s00_axi_arlen}), - .m_axi_arsize({s01_axi_arsize, s00_axi_arsize}), - .m_axi_arburst({s01_axi_arburst, s00_axi_arburst}), - .m_axi_arprot({s01_axi_arprot, s00_axi_arprot}), - .m_axi_arregion({s01_axi_arregion, s00_axi_arregion}), - .m_axi_arqos({s01_axi_arqos, s00_axi_arqos}), - .m_axi_arcache({s01_axi_arcache, s00_axi_arcache}), - .m_axi_arvalid({s01_axi_arvalid, s00_axi_arvalid}), - .m_axi_araddr({s01_axi_araddr, s00_axi_araddr}), - .m_axi_arlock({s01_axi_arlock, s00_axi_arlock}), - .m_axi_arready({s01_axi_arready, s00_axi_arready}), - .m_axi_rid({4'b1000, s00_axi_rid}), - .m_axi_rdata({s01_axi_rdata, s00_axi_rdata}), - .m_axi_rresp({s01_axi_rresp, s00_axi_rresp}), - .m_axi_rvalid({s01_axi_rvalid, s00_axi_rvalid}), - .m_axi_rlast({s01_axi_rlast, s00_axi_rlast}), - .m_axi_rready({s01_axi_rready, s00_axi_rready}) - ); - - // ----------------------------------------------------- - - // SDC Implementation ---------------------------------- - // - // The SDC peripheral from Eugene Tarassov takes in an AXI4Lite - // interface and outputs an AXI4 interface. In order to convert from - // one to the other, we use these dwidth converters to make sure the - // bit widths match the rest of the bus. - - xlnx_axi_dwidth_conv_64to32 axi_conv_down - (.s_axi_aclk(CPUCLK), - .s_axi_aresetn(peripheral_aresetn), - - // Slave interface - .s_axi_awaddr(s01_axi_awaddr), - .s_axi_awlen(s01_axi_awlen), - .s_axi_awsize(s01_axi_awsize), - .s_axi_awburst(s01_axi_awburst), - .s_axi_awlock(s01_axi_awlock), - .s_axi_awcache(s01_axi_awcache), - .s_axi_awprot(s01_axi_awprot), - .s_axi_awregion(s01_axi_awregion), - .s_axi_awqos(4'b0), - .s_axi_awvalid(s01_axi_awvalid), - .s_axi_awready(s01_axi_awready), - .s_axi_wdata(s01_axi_wdata), - .s_axi_wstrb(s01_axi_wstrb), - .s_axi_wlast(s01_axi_wlast), - .s_axi_wvalid(s01_axi_wvalid), - .s_axi_wready(s01_axi_wready), - .s_axi_bresp(s01_axi_bresp), - .s_axi_bvalid(s01_axi_bvalid), - .s_axi_bready(s01_axi_bready), - .s_axi_araddr(s01_axi_araddr), - .s_axi_arlen(s01_axi_arlen), - .s_axi_arsize(s01_axi_arsize), - .s_axi_arburst(s01_axi_arburst), - .s_axi_arlock(s01_axi_arlock), - .s_axi_arcache(s01_axi_arcache), - .s_axi_arprot(s01_axi_arprot), - .s_axi_arregion(s01_axi_arregion), - .s_axi_arqos(4'b0), - .s_axi_arvalid(s01_axi_arvalid), - .s_axi_arready(s01_axi_arready), - .s_axi_rdata(s01_axi_rdata), - .s_axi_rresp(s01_axi_rresp), - .s_axi_rlast(s01_axi_rlast), - .s_axi_rvalid(s01_axi_rvalid), - .s_axi_rready(s01_axi_rready), - - // Master interface - .m_axi_awaddr(axi4in_axi_awaddr), - .m_axi_awlen(axi4in_axi_awlen), - .m_axi_awsize(axi4in_axi_awsize), - .m_axi_awburst(axi4in_axi_awburst), - .m_axi_awlock(axi4in_axi_awlock), - .m_axi_awcache(axi4in_axi_awcache), - .m_axi_awprot(axi4in_axi_awprot), - .m_axi_awregion(axi4in_axi_awregion), - .m_axi_awqos(axi4in_axi_awqos), - .m_axi_awvalid(axi4in_axi_awvalid), - .m_axi_awready(axi4in_axi_awready), - .m_axi_wdata(axi4in_axi_wdata), - .m_axi_wstrb(axi4in_axi_wstrb), - .m_axi_wlast(axi4in_axi_wlast), - .m_axi_wvalid(axi4in_axi_wvalid), - .m_axi_wready(axi4in_axi_wready), - .m_axi_bresp(axi4in_axi_bresp), - .m_axi_bvalid(axi4in_axi_bvalid), - .m_axi_bready(axi4in_axi_bready), - .m_axi_araddr(axi4in_axi_araddr), - .m_axi_arlen(axi4in_axi_arlen), - .m_axi_arsize(axi4in_axi_arsize), - .m_axi_arburst(axi4in_axi_arburst), - .m_axi_arlock(axi4in_axi_arlock), - .m_axi_arcache(axi4in_axi_arcache), - .m_axi_arprot(axi4in_axi_arprot), - .m_axi_arregion(axi4in_axi_arregion), - .m_axi_arqos(axi4in_axi_arqos), - .m_axi_arvalid(axi4in_axi_arvalid), - .m_axi_arready(axi4in_axi_arready), - .m_axi_rdata(axi4in_axi_rdata), - .m_axi_rresp(axi4in_axi_rresp), - .m_axi_rlast(axi4in_axi_rlast), - .m_axi_rvalid(axi4in_axi_rvalid), - .m_axi_rready(axi4in_axi_rready) - ); - - xlnx_axi_prtcl_conv axi4tolite - (.aclk(CPUCLK), - .aresetn(peripheral_aresetn), - - // AXI4 In - .s_axi_awaddr(axi4in_axi_awaddr), - .s_axi_awlen(axi4in_axi_awlen), - .s_axi_awsize(axi4in_axi_awsize), - .s_axi_awburst(axi4in_axi_awburst), - .s_axi_awlock(axi4in_axi_awlock), - .s_axi_awcache(axi4in_axi_awcache), - .s_axi_awprot(axi4in_axi_awprot), - .s_axi_awregion(axi4in_axi_awregion), - .s_axi_awqos(axi4in_axi_awqos), - .s_axi_awvalid(axi4in_axi_awvalid), - .s_axi_awready(axi4in_axi_awready), - .s_axi_wdata(axi4in_axi_wdata), - .s_axi_wstrb(axi4in_axi_wstrb), - .s_axi_wlast(axi4in_axi_wlast), - .s_axi_wvalid(axi4in_axi_wvalid), - .s_axi_wready(axi4in_axi_wready), - .s_axi_bresp(axi4in_axi_bresp), - .s_axi_bvalid(axi4in_axi_bvalid), - .s_axi_bready(axi4in_axi_bready), - .s_axi_araddr(axi4in_axi_araddr), - .s_axi_arlen(axi4in_axi_arlen), - .s_axi_arsize(axi4in_axi_arsize), - .s_axi_arburst(axi4in_axi_arburst), - .s_axi_arlock(axi4in_axi_arlock), - .s_axi_arcache(axi4in_axi_arcache), - .s_axi_arprot(axi4in_axi_arprot), - .s_axi_arregion(axi4in_axi_arregion), - .s_axi_arqos(axi4in_axi_arqos), - .s_axi_arvalid(axi4in_axi_arvalid), - .s_axi_arready(axi4in_axi_arready), - .s_axi_rdata(axi4in_axi_rdata), - .s_axi_rresp(axi4in_axi_rresp), - .s_axi_rlast(axi4in_axi_rlast), - .s_axi_rvalid(axi4in_axi_rvalid), - .s_axi_rready(axi4in_axi_rready), - - // AXI4Lite Out - .m_axi_awaddr(SDCin_axi_awaddr), - .m_axi_awprot(SDCin_axi_awprot), - .m_axi_awvalid(SDCin_axi_awvalid), - .m_axi_awready(SDCin_axi_awready), - .m_axi_wdata(SDCin_axi_wdata), - .m_axi_wstrb(SDCin_axi_wstrb), - .m_axi_wvalid(SDCin_axi_wvalid), - .m_axi_wready(SDCin_axi_wready), - .m_axi_bresp(SDCin_axi_bresp), - .m_axi_bvalid(SDCin_axi_bvalid), - .m_axi_bready(SDCin_axi_bready), - .m_axi_araddr(SDCin_axi_araddr), - .m_axi_arprot(SDCin_axi_arprot), - .m_axi_arvalid(SDCin_axi_arvalid), - .m_axi_arready(SDCin_axi_arready), - .m_axi_rdata(SDCin_axi_rdata), - .m_axi_rresp(SDCin_axi_rresp), - .m_axi_rvalid(SDCin_axi_rvalid), - .m_axi_rready(SDCin_axi_rready) - - ); - - - sdc_controller axiSDC - (.clock(CPUCLK), - .async_resetn(peripheral_aresetn), - - // Slave Interface - .s_axi_awaddr({8'b0, SDCin_axi_awaddr[7:0]}), - .s_axi_awvalid(SDCin_axi_awvalid), - .s_axi_awready(SDCin_axi_awready), - .s_axi_wdata(SDCin_axi_wdata), - .s_axi_wvalid(SDCin_axi_wvalid), - .s_axi_wready(SDCin_axi_wready), - .s_axi_bresp(SDCin_axi_bresp), - .s_axi_bvalid(SDCin_axi_bvalid), - .s_axi_bready(SDCin_axi_bready), - .s_axi_araddr({8'b0, SDCin_axi_araddr[7:0]}), - .s_axi_arvalid(SDCin_axi_arvalid), - .s_axi_arready(SDCin_axi_arready), - .s_axi_rdata(SDCin_axi_rdata), - .s_axi_rresp(SDCin_axi_rresp), - .s_axi_rvalid(SDCin_axi_rvalid), - .s_axi_rready(SDCin_axi_rready), - .sdio_reset(sdio_reset_open), - - // Master Interface - .m_axi_awaddr(SDCout_axi_awaddr), - .m_axi_awlen(SDCout_axi_awlen), - .m_axi_awvalid(SDCout_axi_awvalid), - .m_axi_awready(SDCout_axi_awready), - .m_axi_wdata(SDCout_axi_wdata), - .m_axi_wlast(SDCout_axi_wlast), - .m_axi_wvalid(SDCout_axi_wvalid), - .m_axi_wready(SDCout_axi_wready), - .m_axi_bresp(SDCout_axi_bresp), - .m_axi_bvalid(SDCout_axi_bvalid), - .m_axi_bready(SDCout_axi_bready), - .m_axi_araddr(SDCout_axi_araddr), - .m_axi_arlen(SDCout_axi_arlen), - .m_axi_arvalid(SDCout_axi_arvalid), - .m_axi_arready(SDCout_axi_arready), - .m_axi_rdata(SDCout_axi_rdata), - .m_axi_rlast(SDCout_axi_rlast), - .m_axi_rresp(SDCout_axi_rresp), - .m_axi_rvalid(SDCout_axi_rvalid), - .m_axi_rready(SDCout_axi_rready), - - // SDC interface - //.sdio_cmd(1'b0), - //.sdio_dat(4'b0), - //.sdio_cd(1'b0) - - .sd_dat_reg_t(sd_dat_reg_t), - .sd_dat_reg_o(sd_dat_reg_o), - .sd_dat_i(sd_dat_i), - - .sd_cmd_reg_t(sd_cmd_reg_t), - .sd_cmd_reg_o(sd_cmd_reg_o), - .sd_cmd_i(sd_cmd_i), - - .sdio_clk(SDCCLK), - .sdio_cd(SDCCD), - - .interrupt(SDCIntr) - ); - - xlnx_axi_dwidth_conv_32to64 axi_conv_up - (.s_axi_aclk(CPUCLK), - .s_axi_aresetn(peripheral_aresetn), - - // Slave interface - .s_axi_awaddr(SDCout_axi_awaddr), - .s_axi_awlen(SDCout_axi_awlen), - .s_axi_awsize(3'b010), - .s_axi_awburst(2'b01), - .s_axi_awlock(1'b0), - .s_axi_awcache(4'b0), - .s_axi_awprot(3'b0), - .s_axi_awregion(4'b0), - .s_axi_awqos(4'b0), - .s_axi_awvalid(SDCout_axi_awvalid), - .s_axi_awready(SDCout_axi_awready), - .s_axi_wdata(SDCout_axi_wdata), - .s_axi_wstrb(8'b11111111), - .s_axi_wlast(SDCout_axi_wlast), - .s_axi_wvalid(SDCout_axi_wvalid), - .s_axi_wready(SDCout_axi_wready), - .s_axi_bresp(SDCout_axi_bresp), - .s_axi_bvalid(SDCout_axi_bvalid), - .s_axi_bready(SDCout_axi_bready), - .s_axi_araddr(SDCout_axi_araddr), - .s_axi_arlen(SDCout_axi_arlen), - .s_axi_arsize(3'b010), - .s_axi_arburst(2'b01), - .s_axi_arlock(1'b0), - .s_axi_arcache(4'b0), - .s_axi_arprot(3'b0), - .s_axi_arregion(4'b0), - .s_axi_arqos(4'b0), - .s_axi_arvalid(SDCout_axi_arvalid), - .s_axi_arready(SDCout_axi_arready), - .s_axi_rdata(SDCout_axi_rdata), - .s_axi_rresp(SDCout_axi_rresp), - .s_axi_rlast(SDCout_axi_rlast), - .s_axi_rvalid(SDCout_axi_rvalid), - .s_axi_rready(SDCout_axi_rready), - - // Master interface - .m_axi_awaddr(m01_axi_awaddr), - .m_axi_awlen(m01_axi_awlen), - .m_axi_awsize(m01_axi_awsize), - .m_axi_awburst(m01_axi_awburst), - .m_axi_awlock(m01_axi_awlock), - .m_axi_awcache(m01_axi_awcache), - .m_axi_awprot(m01_axi_awprot), - .m_axi_awregion(m01_axi_awregion), - .m_axi_awqos(m01_axi_awqos), - .m_axi_awvalid(m01_axi_awvalid), - .m_axi_awready(m01_axi_awready), - .m_axi_wdata(m01_axi_wdata), - .m_axi_wstrb(m01_axi_wstrb), - .m_axi_wlast(m01_axi_wlast), - .m_axi_wvalid(m01_axi_wvalid), - .m_axi_wready(m01_axi_wready), - .m_axi_bresp(m01_axi_bresp), - .m_axi_bvalid(m01_axi_bvalid), - .m_axi_bready(m01_axi_bready), - .m_axi_araddr(m01_axi_araddr), - .m_axi_arlen(m01_axi_arlen), - .m_axi_arsize(m01_axi_arsize), - .m_axi_arburst(m01_axi_arburst), - .m_axi_arlock(m01_axi_arlock), - .m_axi_arcache(m01_axi_arcache), - .m_axi_arprot(m01_axi_arprot), - .m_axi_arregion(m01_axi_arregion), - .m_axi_arqos(m01_axi_arqos), - .m_axi_arvalid(m01_axi_arvalid), - .m_axi_arready(m01_axi_arready), - .m_axi_rdata(m01_axi_rdata), - .m_axi_rresp(m01_axi_rresp), - .m_axi_rlast(m01_axi_rlast), - .m_axi_rvalid(m01_axi_rvalid), - .m_axi_rready(m01_axi_rready) - ); - - // End SDC signals -------------------------------------------- - + // AXI Clock Converter xlnx_axi_clock_converter xlnx_axi_clock_converter_0 (.s_axi_aclk(CPUCLK), .s_axi_aresetn(peripheral_aresetn), - .s_axi_awid(s00_axi_awid), - .s_axi_awlen(s00_axi_awlen), - .s_axi_awsize(s00_axi_awsize), - .s_axi_awburst(s00_axi_awburst), - .s_axi_awcache(s00_axi_awcache), - .s_axi_awaddr(s00_axi_awaddr[30:0] ), - .s_axi_awprot(s00_axi_awprot), + .s_axi_awid(m_axi_awid), + .s_axi_awlen(m_axi_awlen), + .s_axi_awsize(m_axi_awsize), + .s_axi_awburst(m_axi_awburst), + .s_axi_awcache(m_axi_awcache), + .s_axi_awaddr(m_axi_awaddr[30:0] ), + .s_axi_awprot(m_axi_awprot), .s_axi_awregion(4'b0), // this could be a bug. bridge does not have these outputs .s_axi_awqos(4'b0), // this could be a bug. bridge does not have these outputs - .s_axi_awvalid(s00_axi_awvalid), - .s_axi_awready(s00_axi_awready), - .s_axi_awlock(s00_axi_awlock), - .s_axi_wdata(s00_axi_wdata), - .s_axi_wstrb(s00_axi_wstrb), - .s_axi_wlast(s00_axi_wlast), - .s_axi_wvalid(s00_axi_wvalid), - .s_axi_wready(s00_axi_wready), - .s_axi_bid(s00_axi_bid), - .s_axi_bresp(s00_axi_bresp), - .s_axi_bvalid(s00_axi_bvalid), - .s_axi_bready(s00_axi_bready), - .s_axi_arid(s00_axi_arid), - .s_axi_arlen(s00_axi_arlen), - .s_axi_arsize(s00_axi_arsize), - .s_axi_arburst(s00_axi_arburst), - .s_axi_arprot(s00_axi_arprot), + .s_axi_awvalid(m_axi_awvalid), + .s_axi_awready(m_axi_awready), + .s_axi_awlock(m_axi_awlock), + .s_axi_wdata(m_axi_wdata), + .s_axi_wstrb(m_axi_wstrb), + .s_axi_wlast(m_axi_wlast), + .s_axi_wvalid(m_axi_wvalid), + .s_axi_wready(m_axi_wready), + .s_axi_bid(m_axi_bid), + .s_axi_bresp(m_axi_bresp), + .s_axi_bvalid(m_axi_bvalid), + .s_axi_bready(m_axi_bready), + .s_axi_arid(m_axi_arid), + .s_axi_arlen(m_axi_arlen), + .s_axi_arsize(m_axi_arsize), + .s_axi_arburst(m_axi_arburst), + .s_axi_arprot(m_axi_arprot), .s_axi_arregion(4'b0), // this could be a bug. bridge does not have these outputs .s_axi_arqos(4'b0), // this could be a bug. bridge does not have these outputs - .s_axi_arcache(s00_axi_arcache), - .s_axi_arvalid(s00_axi_arvalid), - .s_axi_araddr(s00_axi_araddr[30:0]), - .s_axi_arlock(s00_axi_arlock), - .s_axi_arready(s00_axi_arready), - .s_axi_rid(s00_axi_rid), - .s_axi_rdata(s00_axi_rdata), - .s_axi_rresp(s00_axi_rresp), - .s_axi_rvalid(s00_axi_rvalid), - .s_axi_rlast(s00_axi_rlast), - .s_axi_rready(s00_axi_rready), + .s_axi_arcache(m_axi_arcache), + .s_axi_arvalid(m_axi_arvalid), + .s_axi_araddr(m_axi_araddr[30:0]), + .s_axi_arlock(m_axi_arlock), + .s_axi_arready(m_axi_arready), + .s_axi_rid(m_axi_rid), + .s_axi_rdata(m_axi_rdata), + .s_axi_rresp(m_axi_rresp), + .s_axi_rvalid(m_axi_rvalid), + .s_axi_rlast(m_axi_rlast), + .s_axi_rready(m_axi_rready), .m_axi_aclk(BUSCLK), .m_axi_aresetn(resetn), @@ -1020,6 +385,7 @@ module fpgaTop .m_axi_rlast(BUS_axi_rlast), .m_axi_rready(BUS_axi_rready)); + // DDR3 Controller xlnx_ddr3 xlnx_ddr3_c0 ( // ddr3 I/O diff --git a/src/uncore/spi_apb.sv b/src/uncore/spi_apb.sv index 94f188120..e9c04bca8 100644 --- a/src/uncore/spi_apb.sv +++ b/src/uncore/spi_apb.sv @@ -42,7 +42,8 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( output logic SPIOut, input logic SPIIn, output logic [3:0] SPICS, - output logic SPIIntr + output logic SPIIntr, + output logic SPICLK ); // register map @@ -99,7 +100,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( rsrstatetype ReceiveState; // Transmission signals - logic sck; + // logic sck; logic [11:0] DivCounter; // Counter for sck logic SCLKenable; // Flip flop enable high every sclk edge @@ -358,7 +359,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( assign DelayMode = SckMode[0] ? (state == DELAY_1) : (state == ACTIVE_1 & ReceiveShiftFull); assign ChipSelectInternal = (state == CS_INACTIVE | state == INTER_CS | DelayMode & ~|(Delay0[15:8])) ? ChipSelectDef : ~ChipSelectDef; - assign sck = (state == ACTIVE_0) ? ~SckMode[1] : SckMode[1]; + assign SPICLK = (state == ACTIVE_0) ? ~SckMode[1] : SckMode[1]; assign Active = (state == ACTIVE_0 | state == ACTIVE_1); assign SampleEdge = SckMode[0] ? (state == ACTIVE_1) : (state == ACTIVE_0); assign ZeroDelayHoldMode = ((ChipSelectMode == 2'b10) & (~|(Delay1[7:4]))); @@ -368,11 +369,11 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( // Signal tracks which edge of sck to shift data always_comb case(SckMode[1:0]) - 2'b00: ShiftEdge = ~sck & SCLKenable; - 2'b01: ShiftEdge = (sck & |(FrameCount) & SCLKenable); - 2'b10: ShiftEdge = sck & SCLKenable; - 2'b11: ShiftEdge = (~sck & |(FrameCount) & SCLKenable); - default: ShiftEdge = sck & SCLKenable; + 2'b00: ShiftEdge = ~SPICLK & SCLKenable; + 2'b01: ShiftEdge = (SPICLK & |(FrameCount) & SCLKenable); + 2'b10: ShiftEdge = SPICLK & SCLKenable; + 2'b11: ShiftEdge = (~SPICLK & |(FrameCount) & SCLKenable); + default: ShiftEdge = SPICLK & SCLKenable; endcase // Transmit shift register diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index 39a2be09a..dad558c19 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -46,7 +46,6 @@ module uncore import cvw::*; #(parameter cvw_t P)( output logic [P.AHBW-1:0] HRDATA, output logic HREADY, HRESP, output logic HSELEXT, - output logic HSELEXTSDC, // peripheral pins output logic MTimerInt, MSwInt, // Timer and software interrupts from CLINT output logic MExtInt, SExtInt, // External interrupts from PLIC @@ -55,16 +54,20 @@ module uncore import cvw::*; #(parameter cvw_t P)( output logic [31:0] GPIOOUT, GPIOEN, // GPIO pin output value and enable input logic UARTSin, // UART serial input output logic UARTSout, // UART serial output - input logic SDCIntr, input logic SPIIn, output logic SPIOut, - output logic [3:0] SPICS + output logic [3:0] SPICS, + output logic SPICLK, + input logic SDCIn, + output logic SDCCmd, + output logic [3:0] SDCCS, + output logic SDCCLK ); logic [P.XLEN-1:0] HREADRam, HREADSDC; logic [11:0] HSELRegions; - logic HSELDTIM, HSELIROM, HSELRam, HSELCLINT, HSELPLIC, HSELGPIO, HSELUART, HSELSPI; + logic HSELDTIM, HSELIROM, HSELRam, HSELCLINT, HSELPLIC, HSELGPIO, HSELUART,HSELSDC, HSELSPI; logic HSELDTIMD, HSELIROMD, HSELEXTD, HSELRamD, HSELCLINTD, HSELPLICD, HSELGPIOD, HSELUARTD, HSELSDCD, HSELSPID; logic HRESPRam, HRESPSDC; logic HREADYRam, HRESPSDCD; @@ -85,8 +88,8 @@ module uncore import cvw::*; #(parameter cvw_t P)( /* verilator lint_on UNDRIVEN */ logic [P.XLEN-1:0] HREADBRIDGE; logic HRESPBRIDGE, HREADYBRIDGE, HSELBRIDGE, HSELBRIDGED; - - (* mark_debug = "true" *) logic HSELEXTSDCD; + /* SDC Interrupt (SPI Controller) */ + logic SDCIntr; // Determine which region of physical memory (if any) is being accessed @@ -95,14 +98,14 @@ module uncore import cvw::*; #(parameter cvw_t P)( adrdecs #(P) adrdecs(HADDR, 1'b1, 1'b1, 1'b1, HSIZE[1:0], HSELRegions); // unswizzle HSEL signals - assign {HSELSPI, HSELEXTSDC, HSELPLIC, HSELUART, HSELGPIO, HSELCLINT, HSELRam, HSELBootRom, HSELEXT, HSELIROM, HSELDTIM} = HSELRegions[11:1]; + assign {HSELSPI, HSELSDC, HSELPLIC, HSELUART, HSELGPIO, HSELCLINT, HSELRam, HSELBootRom, HSELEXT, HSELIROM, HSELDTIM} = HSELRegions[11:1]; // AHB -> APB bridge - ahbapbbridge #(P, 5) ahbapbbridge ( - .HCLK, .HRESETn, .HSEL({HSELSPI, HSELUART, HSELPLIC, HSELCLINT, HSELGPIO}), .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HTRANS, .HREADY, + ahbapbbridge #(P, 6) ahbapbbridge ( + .HCLK, .HRESETn, .HSEL({HSELSPI, HSELUART, HSELPLIC, HSELCLINT, HSELGPIO, HSELSDC}), .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HTRANS, .HREADY, .HRDATA(HREADBRIDGE), .HRESP(HRESPBRIDGE), .HREADYOUT(HREADYBRIDGE), .PCLK, .PRESETn, .PSEL, .PWRITE, .PENABLE, .PADDR, .PWDATA, .PSTRB, .PREADY, .PRDATA); - assign HSELBRIDGE = HSELGPIO | HSELCLINT | HSELPLIC | HSELUART | HSELSPI; // if any of the bridge signals are selected + assign HSELBRIDGE = HSELGPIO | HSELCLINT | HSELPLIC | HSELUART | HSELSPI | HSELSDC; // if any of the bridge signals are selected // on-chip RAM if (P.UNCORE_RAM_SUPPORTED) begin : ram @@ -142,6 +145,7 @@ module uncore import cvw::*; #(parameter cvw_t P)( end else begin : gpio assign GPIOOUT = '0; assign GPIOEN = '0; assign GPIOIntr = 1'b0; end + if (P.UART_SUPPORTED == 1) begin : uartgen // Hack to work around Verilator bug https://github.com/verilator/verilator/issues/4769 uart_apb #(P) uart( .PCLK, .PRESETn, .PSEL(PSEL[3]), .PADDR(PADDR[2:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, @@ -152,28 +156,39 @@ module uncore import cvw::*; #(parameter cvw_t P)( end else begin : uart assign UARTSout = 1'b0; assign UARTIntr = 1'b0; end + if (P.SPI_SUPPORTED == 1) begin : spi spi_apb #(P) spi ( .PCLK, .PRESETn, .PSEL(PSEL[4]), .PADDR(PADDR[7:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, .PREADY(PREADY[4]), .PRDATA(PRDATA[4]), - .SPIOut, .SPIIn, .SPICS, .SPIIntr); + .SPIOut, .SPIIn, .SPICS, .SPICLK, .SPIIntr); end else begin : spi - assign SPIOut = 1'b0; assign SPICS = '0; assign SPIIntr = 1'b0; + assign SPIOut = 1'b0; assign SPICS = '0; assign SPIIntr = 1'b0; assign SPICLK = 1'b0; end + if (P.SDC_SUPPORTED == 1) begin : sdc + spi_apb #(P) sdc( + .PCLK, .PRESETN, .PSEL(.PSEL[5]), .PADDR(PADDR[7:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, + .PREADY(PREADY[5]), .PRDATA(PRDATA[5]), + .SPIOut(SDCCmd), .SPIIn(SDCIn), .SPICS(SDCCS), .SPICLK(SDCCLK), .SPIIntr(.SDCIntr)); + end else begin : sdc + assign SDCCmd = '0; assign SDCCD = 1'b0; assign SDCIntr = 1'b0; assign SDCCLK = 1'b0; + end + + // AHB Read Multiplexer assign HRDATA = ({P.XLEN{HSELRamD}} & HREADRam) | - ({P.XLEN{HSELEXTD | HSELEXTSDCD}} & HRDATAEXT) | + ({P.XLEN{HSELEXTD}} & HRDATAEXT) | ({P.XLEN{HSELBRIDGED}} & HREADBRIDGE) | ({P.XLEN{HSELBootRomD}} & HREADBootRom); assign HRESP = HSELRamD & HRESPRam | - (HSELEXTD | HSELEXTSDCD) & HRESPEXT | + HSELEXTD & HRESPEXT | HSELBRIDGE & HRESPBRIDGE | HSELBootRomD & HRESPBootRom; assign HREADY = HSELRamD & HREADYRam | - (HSELEXTD | HSELEXTSDCD) & HREADYEXT | + HSELEXTD & HREADYEXT | HSELBRIDGED & HREADYBRIDGE | HSELBootRomD & HREADYBootRom | HSELNoneD; // don't lock up the bus if no region is being accessed @@ -184,7 +199,7 @@ module uncore import cvw::*; #(parameter cvw_t P)( // device is ready. Hense this register must be selectively enabled by HREADY. // However on reset None must be seleted. flopenl #(12) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions, 12'b1, - {HSELSPID, HSELEXTSDCD, HSELPLICD, HSELUARTD, HSELGPIOD, HSELCLINTD, + {HSELSPID, HSELSDCD, HSELPLICD, HSELUARTD, HSELGPIOD, HSELCLINTD, HSELRamD, HSELBootRomD, HSELEXTD, HSELIROMD, HSELDTIMD, HSELNoneD}); flopenr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HREADY, HSELBRIDGE, HSELBRIDGED); endmodule diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index 9f5e5ee00..af9f0ff26 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -55,10 +55,14 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) ( output logic [31:0] GPIOEN, // output enables for GPIO input logic UARTSin, // UART serial data input output logic UARTSout, // UART serial data output - input logic SDCIntr, input logic SPIIn, // SPI pins in output logic SPIOut, // SPI pins out - output logic [3:0] SPICS // SPI chip select pins + output logic [3:0] SPICS, // SPI chip select pins + output logic SPICLK, // SPI clock + input logic SDCIn, // SDC DATA[0] to SPI DI + output logic SDCCmd, // SDC CMD from SPI DO + output logic [3:0] SDCCS, // SDC Card Detect from SPI CS + output logic SDCCLK // SDC Clock from SPI Clock ); // Uncore signals @@ -84,7 +88,7 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) ( .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, .HSELEXTSDC, .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, - .UARTSout, .MTIME_CLINT, .SDCIntr, .SPIIn, .SPIOut, .SPICS); + .UARTSout, .MTIME_CLINT, .SPIIn, .SPIOut, .SPICS, .SPICLK, .SDCIn, .SDCCmd, .SDCCS, .SDCCLK); end else begin assign {HRDATA, HREADY, HRESP, HSELEXT, HSELEXTSDC, MTimerInt, MSwInt, MExtInt, SExtInt, MTIME_CLINT, GPIOOUT, GPIOEN, UARTSout, SPIOut, SPICS} = '0; From cec39fd3aa66a8ccc8fee528287134f3ccdfd643 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Mon, 22 Jul 2024 13:05:16 -0500 Subject: [PATCH 094/219] Added new SDC clock constraint. --- fpga/constraints/constraints-ArtyA7.xdc | 63 +++++++++++++------------ 1 file changed, 33 insertions(+), 30 deletions(-) diff --git a/fpga/constraints/constraints-ArtyA7.xdc b/fpga/constraints/constraints-ArtyA7.xdc index 6fc660e8d..f466b0c30 100644 --- a/fpga/constraints/constraints-ArtyA7.xdc +++ b/fpga/constraints/constraints-ArtyA7.xdc @@ -4,6 +4,7 @@ # This clock is not used by wally or the AHB Bus. However it is used by the AXI BUS on the DD3 IP. #create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O] +create_generated_clock -name SPISDCClock -source [get_pins clk_out3_xlnx_mmcm] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncore.uncore/sdc.sdc/SPICLK] ##### clock ##### set_property PACKAGE_PIN E3 [get_ports {default_100mhz_clk}] @@ -74,41 +75,43 @@ set_property IOSTANDARD LVCMOS33 [get_ports {south_reset}] ##### SD Card I/O ##### #***** may have to switch to Pmod JB or JC. -set_property PACKAGE_PIN D4 [get_ports {SDCDat[3]}] -set_property PACKAGE_PIN D2 [get_ports {SDCDat[2]}] -set_property PACKAGE_PIN E2 [get_ports {SDCDat[1]}] -set_property PACKAGE_PIN F4 [get_ports {SDCDat[0]}] -set_property PACKAGE_PIN F3 [get_ports SDCCLK] -set_property PACKAGE_PIN D3 [get_ports {SDCCmd}] -set_property PACKAGE_PIN H2 [get_ports {SDCCD}] +#set_property PACKAGE_PIN D4 [get_ports {SDCDat[3]}] +#set_property PACKAGE_PIN D2 [get_ports {SDCDat[2]}] +#set_property PACKAGE_PIN E2 [get_ports {SDCDat[1]}] +#set_property PACKAGE_PIN F4 [get_ports {SDCDat[0]}] +#set_property PACKAGE_PIN F3 [get_ports SDCCLK] +#set_property PACKAGE_PIN D3 [get_ports {SDCCmd}] +#set_property PACKAGE_PIN H2 [get_ports {SDCCD}] +#set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[3]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[2]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[1]}] +#set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[0]}] +#set_property IOSTANDARD LVCMOS33 [get_ports SDCCLK] +#set_property IOSTANDARD LVCMOS33 [get_ports {SDCCmd}] +#set_property IOSTANDARD LVCMOS33 [get_ports {SDCCD}] +#set_property PULLUP true [get_ports {SDCDat[3]}] +#set_property PULLUP true [get_ports {SDCDat[2]}] +#set_property PULLUP true [get_ports {SDCDat[1]}] +#set_property PULLUP true [get_ports {SDCDat[0]}] +#set_property PULLUP true [get_ports {SDCCmd}] +#set_property PULLUP true [get_ports {SDCCD}] -set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[3]}] -set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[2]}] -set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[1]}] -set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[0]}] -set_property IOSTANDARD LVCMOS33 [get_ports SDCCLK] -set_property IOSTANDARD LVCMOS33 [get_ports {SDCCmd}] -set_property IOSTANDARD LVCMOS33 [get_ports {SDCCD}] -set_property PULLUP true [get_ports {SDCDat[3]}] -set_property PULLUP true [get_ports {SDCDat[2]}] -set_property PULLUP true [get_ports {SDCDat[1]}] -set_property PULLUP true [get_ports {SDCDat[0]}] -set_property PULLUP true [get_ports {SDCCmd}] -set_property PULLUP true [get_ports {SDCCD}] +set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[3]}] +set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[2]}] +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[1]}] +set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[0]}] +set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCClk}] +set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCmd}] +set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCD}] +set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCDat[*]}] +set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 21.000 [get_ports {SDCDat[*]}] -set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.500 [get_ports {SDCDat[*]}] -set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 21.000 [get_ports {SDCDat[*]}] +set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.000 [get_ports {SDCCmd}] +set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 6.000 [get_ports {SDCCmd}] -set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.500 [get_ports {SDCCmd}] -set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 14.000 [get_ports {SDCCmd}] - - -set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [get_ports {SDCCmd}] -set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 6.000 [get_ports {SDCCmd}] - -set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] 0.000 [get_ports SDCCLK] +set_output_delay -clock [get_clocks SPISDCClock] 0.000 [get_ports SDCCLK] #set_multicycle_path -from [get_pins xlnx_ddr3_c0/u_xlnx_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/init_calib_complete_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10 From 121342f4ccd3a3b62d1783fe0d141a24df895c34 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 22 Jul 2024 16:12:06 -0500 Subject: [PATCH 095/219] Updated the verilog-ethernet repo to remove most of the warnings. Updated the fpga constraints so the ILA is more useful when using RVVI. --- addins/verilog-ethernet | 2 +- fpga/constraints/small-debug-rvvi.xdc | 43 ++++++++++----------------- src/rvvi/rvvisynth.sv | 2 +- 3 files changed, 18 insertions(+), 29 deletions(-) diff --git a/addins/verilog-ethernet b/addins/verilog-ethernet index 43990ab4f..471394b80 160000 --- a/addins/verilog-ethernet +++ b/addins/verilog-ethernet @@ -1 +1 @@ -Subproject commit 43990ab4fd0c8d34dbc1be5cd8d4f3ed3e33f853 +Subproject commit 471394b80c95a4859cd55a0f253d5ea502371e98 diff --git a/fpga/constraints/small-debug-rvvi.xdc b/fpga/constraints/small-debug-rvvi.xdc index f8ebbfe0d..0441f4fa2 100644 --- a/fpga/constraints/small-debug-rvvi.xdc +++ b/fpga/constraints/small-debug-rvvi.xdc @@ -9,7 +9,7 @@ set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ] set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ] set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ] create_debug_port u_ila_0 trig_in -create_debug_port u_ila_0 trig_in_ack +create_debug_port u_ila_0 trig_in_ack #set_property port_width 1 [get_debug_ports u_ila_0/trig_in] #set_property port_width 1 [get_debug_ports u_ila_0/trig_in_ack] #set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/trig_in] @@ -17,14 +17,14 @@ connect_debug_port u_ila_0/trig_in [get_nets IlaTrigger] #connect_debug_port u_ila_0/trig_in_ack [get_nets IlaTriggerAck] connect_debug_port u_ila_0/clk [get_nets CPUCLK] -set_property port_width 32 [get_debug_ports u_ila_0/probe0] +set_property port_width 64 [get_debug_ports u_ila_0/probe0] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] -connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][0]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][1]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][2]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][3]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][4]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][5]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][6]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][7]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][8]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][9]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][10]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][11]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][12]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][13]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][14]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][15]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][16]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][17]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][18]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][19]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][20]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][21]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][22]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][23]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][24]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][25]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][26]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][27]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][28]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][29]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][30]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][31]} ]] +connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe1] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] -connect_debug_port u_ila_0/probe1 [get_nets [list rvvi_synth/RvviAxiWlast ]] +connect_debug_port u_ila_0/probe1 [get_nets [list wallypipelinedsoc/core/TrapM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe2] @@ -32,50 +32,39 @@ set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] connect_debug_port u_ila_0/probe2 [get_nets [list wallypipelinedsoc/core/InstrValidM ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe3] +set_property port_width 32 [get_debug_ports u_ila_0/probe3] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] -connect_debug_port u_ila_0/probe3 [get_nets [list {rvvi_synth/RvviAxiRlast}]] +connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe4] +set_property port_width 2 [get_debug_ports u_ila_0/probe4] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] -connect_debug_port u_ila_0/probe4 [get_nets [list {rvvi_synth/RvviAxiRvalid}]] +connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/lsu/MemRWM[0]} {wallypipelinedsoc/core/lsu/MemRWM[1]} ]] create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe5] +set_property port_width 64 [get_debug_ports u_ila_0/probe5] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] -connect_debug_port u_ila_0/probe5 [get_nets [list {rvvi_synth/packetizer/CurrState[0]} {rvvi_synth/packetizer/CurrState[1]} {rvvi_synth/packetizer/CurrState[2]} {rvvi_synth/packetizer/CurrState[3]}]] +connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/core/lsu/IEUAdrM[0]} {wallypipelinedsoc/core/lsu/IEUAdrM[1]} {wallypipelinedsoc/core/lsu/IEUAdrM[2]} {wallypipelinedsoc/core/lsu/IEUAdrM[3]} {wallypipelinedsoc/core/lsu/IEUAdrM[4]} {wallypipelinedsoc/core/lsu/IEUAdrM[5]} {wallypipelinedsoc/core/lsu/IEUAdrM[6]} {wallypipelinedsoc/core/lsu/IEUAdrM[7]} {wallypipelinedsoc/core/lsu/IEUAdrM[8]} {wallypipelinedsoc/core/lsu/IEUAdrM[9]} {wallypipelinedsoc/core/lsu/IEUAdrM[10]} {wallypipelinedsoc/core/lsu/IEUAdrM[11]} {wallypipelinedsoc/core/lsu/IEUAdrM[12]} {wallypipelinedsoc/core/lsu/IEUAdrM[13]} {wallypipelinedsoc/core/lsu/IEUAdrM[14]} {wallypipelinedsoc/core/lsu/IEUAdrM[15]} {wallypipelinedsoc/core/lsu/IEUAdrM[16]} {wallypipelinedsoc/core/lsu/IEUAdrM[17]} {wallypipelinedsoc/core/lsu/IEUAdrM[18]} {wallypipelinedsoc/core/lsu/IEUAdrM[19]} {wallypipelinedsoc/core/lsu/IEUAdrM[20]} {wallypipelinedsoc/core/lsu/IEUAdrM[21]} {wallypipelinedsoc/core/lsu/IEUAdrM[22]} {wallypipelinedsoc/core/lsu/IEUAdrM[23]} {wallypipelinedsoc/core/lsu/IEUAdrM[24]} {wallypipelinedsoc/core/lsu/IEUAdrM[25]} {wallypipelinedsoc/core/lsu/IEUAdrM[26]} {wallypipelinedsoc/core/lsu/IEUAdrM[27]} {wallypipelinedsoc/core/lsu/IEUAdrM[28]} {wallypipelinedsoc/core/lsu/IEUAdrM[29]} {wallypipelinedsoc/core/lsu/IEUAdrM[30]} {wallypipelinedsoc/core/lsu/IEUAdrM[31]} {wallypipelinedsoc/core/lsu/IEUAdrM[32]} {wallypipelinedsoc/core/lsu/IEUAdrM[33]} {wallypipelinedsoc/core/lsu/IEUAdrM[34]} {wallypipelinedsoc/core/lsu/IEUAdrM[35]} {wallypipelinedsoc/core/lsu/IEUAdrM[36]} {wallypipelinedsoc/core/lsu/IEUAdrM[37]} {wallypipelinedsoc/core/lsu/IEUAdrM[38]} {wallypipelinedsoc/core/lsu/IEUAdrM[39]} {wallypipelinedsoc/core/lsu/IEUAdrM[40]} {wallypipelinedsoc/core/lsu/IEUAdrM[41]} {wallypipelinedsoc/core/lsu/IEUAdrM[42]} {wallypipelinedsoc/core/lsu/IEUAdrM[43]} {wallypipelinedsoc/core/lsu/IEUAdrM[44]} {wallypipelinedsoc/core/lsu/IEUAdrM[45]} {wallypipelinedsoc/core/lsu/IEUAdrM[46]} {wallypipelinedsoc/core/lsu/IEUAdrM[47]} {wallypipelinedsoc/core/lsu/IEUAdrM[48]} {wallypipelinedsoc/core/lsu/IEUAdrM[49]} {wallypipelinedsoc/core/lsu/IEUAdrM[50]} {wallypipelinedsoc/core/lsu/IEUAdrM[51]} {wallypipelinedsoc/core/lsu/IEUAdrM[52]} {wallypipelinedsoc/core/lsu/IEUAdrM[53]} {wallypipelinedsoc/core/lsu/IEUAdrM[54]} {wallypipelinedsoc/core/lsu/IEUAdrM[55]} {wallypipelinedsoc/core/lsu/IEUAdrM[56]} {wallypipelinedsoc/core/lsu/IEUAdrM[57]} {wallypipelinedsoc/core/lsu/IEUAdrM[58]} {wallypipelinedsoc/core/lsu/IEUAdrM[59]} {wallypipelinedsoc/core/lsu/IEUAdrM[60]} {wallypipelinedsoc/core/lsu/IEUAdrM[61]} {wallypipelinedsoc/core/lsu/IEUAdrM[62]} {wallypipelinedsoc/core/lsu/IEUAdrM[63]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe6] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] -connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]] +connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsoc/core/lsu/ReadDataM[7]} {wallypipelinedsoc/core/lsu/ReadDataM[8]} {wallypipelinedsoc/core/lsu/ReadDataM[9]} {wallypipelinedsoc/core/lsu/ReadDataM[10]} {wallypipelinedsoc/core/lsu/ReadDataM[11]} {wallypipelinedsoc/core/lsu/ReadDataM[12]} {wallypipelinedsoc/core/lsu/ReadDataM[13]} {wallypipelinedsoc/core/lsu/ReadDataM[14]} {wallypipelinedsoc/core/lsu/ReadDataM[15]} {wallypipelinedsoc/core/lsu/ReadDataM[16]} {wallypipelinedsoc/core/lsu/ReadDataM[17]} {wallypipelinedsoc/core/lsu/ReadDataM[18]} {wallypipelinedsoc/core/lsu/ReadDataM[19]} {wallypipelinedsoc/core/lsu/ReadDataM[20]} {wallypipelinedsoc/core/lsu/ReadDataM[21]} {wallypipelinedsoc/core/lsu/ReadDataM[22]} {wallypipelinedsoc/core/lsu/ReadDataM[23]} {wallypipelinedsoc/core/lsu/ReadDataM[24]} {wallypipelinedsoc/core/lsu/ReadDataM[25]} {wallypipelinedsoc/core/lsu/ReadDataM[26]} {wallypipelinedsoc/core/lsu/ReadDataM[27]} {wallypipelinedsoc/core/lsu/ReadDataM[28]} {wallypipelinedsoc/core/lsu/ReadDataM[29]} {wallypipelinedsoc/core/lsu/ReadDataM[30]} {wallypipelinedsoc/core/lsu/ReadDataM[31]} {wallypipelinedsoc/core/lsu/ReadDataM[32]} {wallypipelinedsoc/core/lsu/ReadDataM[33]} {wallypipelinedsoc/core/lsu/ReadDataM[34]} {wallypipelinedsoc/core/lsu/ReadDataM[35]} {wallypipelinedsoc/core/lsu/ReadDataM[36]} {wallypipelinedsoc/core/lsu/ReadDataM[37]} {wallypipelinedsoc/core/lsu/ReadDataM[38]} {wallypipelinedsoc/core/lsu/ReadDataM[39]} {wallypipelinedsoc/core/lsu/ReadDataM[40]} {wallypipelinedsoc/core/lsu/ReadDataM[41]} {wallypipelinedsoc/core/lsu/ReadDataM[42]} {wallypipelinedsoc/core/lsu/ReadDataM[43]} {wallypipelinedsoc/core/lsu/ReadDataM[44]} {wallypipelinedsoc/core/lsu/ReadDataM[45]} {wallypipelinedsoc/core/lsu/ReadDataM[46]} {wallypipelinedsoc/core/lsu/ReadDataM[47]} {wallypipelinedsoc/core/lsu/ReadDataM[48]} {wallypipelinedsoc/core/lsu/ReadDataM[49]} {wallypipelinedsoc/core/lsu/ReadDataM[50]} {wallypipelinedsoc/core/lsu/ReadDataM[51]} {wallypipelinedsoc/core/lsu/ReadDataM[52]} {wallypipelinedsoc/core/lsu/ReadDataM[53]} {wallypipelinedsoc/core/lsu/ReadDataM[54]} {wallypipelinedsoc/core/lsu/ReadDataM[55]} {wallypipelinedsoc/core/lsu/ReadDataM[56]} {wallypipelinedsoc/core/lsu/ReadDataM[57]} {wallypipelinedsoc/core/lsu/ReadDataM[58]} {wallypipelinedsoc/core/lsu/ReadDataM[59]} {wallypipelinedsoc/core/lsu/ReadDataM[60]} {wallypipelinedsoc/core/lsu/ReadDataM[61]} {wallypipelinedsoc/core/lsu/ReadDataM[62]} {wallypipelinedsoc/core/lsu/ReadDataM[63]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe7] +set_property port_width 64 [get_debug_ports u_ila_0/probe7] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] -connect_debug_port u_ila_0/probe7 [get_nets [list {rvvi_synth/RvviAxiWvalid}]] +connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsoc/core/lsu/WriteDataM[7]} {wallypipelinedsoc/core/lsu/WriteDataM[8]} {wallypipelinedsoc/core/lsu/WriteDataM[9]} {wallypipelinedsoc/core/lsu/WriteDataM[10]} {wallypipelinedsoc/core/lsu/WriteDataM[11]} {wallypipelinedsoc/core/lsu/WriteDataM[12]} {wallypipelinedsoc/core/lsu/WriteDataM[13]} {wallypipelinedsoc/core/lsu/WriteDataM[14]} {wallypipelinedsoc/core/lsu/WriteDataM[15]} {wallypipelinedsoc/core/lsu/WriteDataM[16]} {wallypipelinedsoc/core/lsu/WriteDataM[17]} {wallypipelinedsoc/core/lsu/WriteDataM[18]} {wallypipelinedsoc/core/lsu/WriteDataM[19]} {wallypipelinedsoc/core/lsu/WriteDataM[20]} {wallypipelinedsoc/core/lsu/WriteDataM[21]} {wallypipelinedsoc/core/lsu/WriteDataM[22]} {wallypipelinedsoc/core/lsu/WriteDataM[23]} {wallypipelinedsoc/core/lsu/WriteDataM[24]} {wallypipelinedsoc/core/lsu/WriteDataM[25]} {wallypipelinedsoc/core/lsu/WriteDataM[26]} {wallypipelinedsoc/core/lsu/WriteDataM[27]} {wallypipelinedsoc/core/lsu/WriteDataM[28]} {wallypipelinedsoc/core/lsu/WriteDataM[29]} {wallypipelinedsoc/core/lsu/WriteDataM[30]} {wallypipelinedsoc/core/lsu/WriteDataM[31]} {wallypipelinedsoc/core/lsu/WriteDataM[32]} {wallypipelinedsoc/core/lsu/WriteDataM[33]} {wallypipelinedsoc/core/lsu/WriteDataM[34]} {wallypipelinedsoc/core/lsu/WriteDataM[35]} {wallypipelinedsoc/core/lsu/WriteDataM[36]} {wallypipelinedsoc/core/lsu/WriteDataM[37]} {wallypipelinedsoc/core/lsu/WriteDataM[38]} {wallypipelinedsoc/core/lsu/WriteDataM[39]} {wallypipelinedsoc/core/lsu/WriteDataM[40]} {wallypipelinedsoc/core/lsu/WriteDataM[41]} {wallypipelinedsoc/core/lsu/WriteDataM[42]} {wallypipelinedsoc/core/lsu/WriteDataM[43]} {wallypipelinedsoc/core/lsu/WriteDataM[44]} {wallypipelinedsoc/core/lsu/WriteDataM[45]} {wallypipelinedsoc/core/lsu/WriteDataM[46]} {wallypipelinedsoc/core/lsu/WriteDataM[47]} {wallypipelinedsoc/core/lsu/WriteDataM[48]} {wallypipelinedsoc/core/lsu/WriteDataM[49]} {wallypipelinedsoc/core/lsu/WriteDataM[50]} {wallypipelinedsoc/core/lsu/WriteDataM[51]} {wallypipelinedsoc/core/lsu/WriteDataM[52]} {wallypipelinedsoc/core/lsu/WriteDataM[53]} {wallypipelinedsoc/core/lsu/WriteDataM[54]} {wallypipelinedsoc/core/lsu/WriteDataM[55]} {wallypipelinedsoc/core/lsu/WriteDataM[56]} {wallypipelinedsoc/core/lsu/WriteDataM[57]} {wallypipelinedsoc/core/lsu/WriteDataM[58]} {wallypipelinedsoc/core/lsu/WriteDataM[59]} {wallypipelinedsoc/core/lsu/WriteDataM[60]} {wallypipelinedsoc/core/lsu/WriteDataM[61]} {wallypipelinedsoc/core/lsu/WriteDataM[62]} {wallypipelinedsoc/core/lsu/WriteDataM[63]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe8] +set_property port_width 32 [get_debug_ports u_ila_0/probe8] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] -connect_debug_port u_ila_0/probe8 [get_nets [list {RVVIStall}]] +connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][0]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][1]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][2]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][3]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][4]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][5]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][6]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][7]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][8]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][9]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][10]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][11]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][12]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][13]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][14]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][15]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][16]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][17]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][18]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][19]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][20]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][21]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][22]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][23]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][24]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][25]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][26]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][27]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][28]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][29]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][30]} {wallypipelinedsoc/core/priv.priv/csr/HPMCOUNTER_REGW[0][31]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe9] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] -connect_debug_port u_ila_0/probe9 [get_nets [list {rvvi_synth/valid}]] - -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe10] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] -connect_debug_port u_ila_0/probe10 [get_nets [list {rvvi_synth/RvviAxiWready}]] - -create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe11] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] -connect_debug_port u_ila_0/probe11 [get_nets [list {rvvi_synth/triggergen/CurrState[0]} {rvvi_synth/triggergen/CurrState[1]} {rvvi_synth/triggergen/CurrState[2]}]] - +connect_debug_port u_ila_0/probe9 [get_nets [list {RVVIStall}]] # the debug hub has issues with the clocks from the mmcm so lets give up an connect to the 100Mhz input clock. #connect_debug_port dbg_hub/clk [get_nets default_100mhz_clk] diff --git a/src/rvvi/rvvisynth.sv b/src/rvvi/rvvisynth.sv index cbf7c30bf..5ee8b8c52 100644 --- a/src/rvvi/rvvisynth.sv +++ b/src/rvvi/rvvisynth.sv @@ -44,7 +44,7 @@ module rvvisynth import cvw::*; #(parameter cvw_t P, input logic GPRWen, FPRWen, input logic [4:0] GPRAddr, FPRAddr, input logic [P.XLEN-1:0] GPRValue, FPRValue, - input logic [P.XLEN-1:0] CSRArray [TOTAL_CSRS-1:0], + input var logic [P.XLEN-1:0] CSRArray [TOTAL_CSRS-1:0], output logic valid, output logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi ); From b05052311f095a7e7021a3d1d5dd391dfcd1e5b0 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Mon, 22 Jul 2024 16:57:04 -0500 Subject: [PATCH 096/219] Added sd_cmd and utility SPI functions. --- fpga/zsbl/sd.c | 68 ++++++++++++++++++++++++++++++++++-- fpga/zsbl/sd.h | 3 +- fpga/zsbl/spi.c | 91 ++++++++++++++++++++++++++++++++++--------------- fpga/zsbl/spi.h | 53 +++++++++++++++++----------- 4 files changed, 164 insertions(+), 51 deletions(-) diff --git a/fpga/zsbl/sd.c b/fpga/zsbl/sd.c index 8781dd5c3..aacea0db9 100644 --- a/fpga/zsbl/sd.c +++ b/fpga/zsbl/sd.c @@ -12,6 +12,7 @@ uint8_t crc7(uint8_t prev, uint8_t in) { return remainder & 0xff; } +// Need to check this. This could be wrong as well. uint16_t crc16(uint16_t crc, uint8_t data) { // CRC polynomial 0x11021 crc = (uint8_t)(crc >> 8) | (crc << 8); @@ -22,13 +23,74 @@ uint16_t crc16(uint16_t crc, uint8_t data) { return crc; } -uint8_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc) { - spi_send_byte +uint64_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc) { + uint8_t response_len; + uint8_t i; + uint64_t r; + uint8_t rbyte; + + switch (cmd) { + case 0: + response_len = 1; + break; + case 8: + response_len = 7 + break; + default: + response_len = 1; + break; + } + + // Make interrupt pending after response fifo receives the correct + // response length. + write_reg(SPI_RXMARK, response_len); + + // Write all 6 bytes into transfer fifo + spi_sendbyte(0x40 | cmd); + spi_sendbyte(arg >> 24); + spi_sendbyte(arg >> 16); + spi_sendbyte(arg >> 8); + spi_sendbyte(arg); + spi_sendbyte(crc); + + // Wait for command to send + // The Transfer IP bit should go high when the txFIFO is empty + // while(!(read_reg(SPI_IP) & 1)) {} + waittx(); + + // Read the dummy rxFIFO entries to move the head back to the tail + for (i = 0; i < 6; i++) { + spi_readbyte(); + } + + // Send "dummy signals". Since SPI is duplex, + // useless bytes must be transferred + for (i = 0; i < response_len; i++) { + spi_sendbyte(0xFF); + } + + // Wait for transfer fifo again + waittx(); + + // Read rxfifo response + for (i = 0; i < response_len; i++) { + rbyte = spi_readbyte(); + r = r | (rbyte << ((response_len - 1 - i)*8)); + } + + return r; } +#define cmd0() sd_cmd( 0, 0x00000000, 0x95) +#define cmd8() sd_cmd( 8, 0x000001aa, 0x87) +// CMD55 has to be sent before ACMD41 (it means the next command is +// application specific) +#define cmd55() sd_cmd(55, 0x00000000, 0x65) +#defube acmd41() sd_cmd(41, 0x40000000, 0x77) + void init_sd(){ init_spi(); - + cmd0() } diff --git a/fpga/zsbl/sd.h b/fpga/zsbl/sd.h index b1b27db14..f08941364 100644 --- a/fpga/zsbl/sd.h +++ b/fpga/zsbl/sd.h @@ -4,6 +4,5 @@ uint8_t crc7(uint8_t prev, uint8_t in); uint16_t crc16(uint16_t crc, uint8_t data); -uint8_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc); +uint64_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc); void init_sd(); - diff --git a/fpga/zsbl/spi.c b/fpga/zsbl/spi.c index bf6d629b4..c812327f4 100644 --- a/fpga/zsbl/spi.c +++ b/fpga/zsbl/spi.c @@ -1,50 +1,87 @@ +/////////////////////////////////////////////////////////////////////// +// spi.c +// +// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024 +// +// Purpose: SPI Controller API for bootloader +// +// +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the +// “License”); you may not use this file except in compliance with the +// License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an “AS IS” BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +// implied. See the License for the specific language governing +// permissions and limitations under the License. +/////////////////////////////////////////////////////////////////////// + #include "spi.h" -void write_reg(uintptr_t addr, uint32_t value) { +// Write to a register +inline void write_reg(uintptr_t addr, uint32_t value) { volatile uint32_t * loc = (volatile uint32_t *) addr; *loc = value; } -void read_red(uintptr_t addr) { +// Read a register +inline void read_reg(uintptr_t addr) { return *(volatile uint32_t *) addr; } +// Queues a single byte in the transfer fifo +inline void spi_sendbyte(uint8_t byte) { + // Write byte to transfer fifo + write_reg(SPI_TXDATA, byte); +} + +inline uint8_t spi_readbyte() { + return read_reg(SPI_RXDATA); +} + +inline void waittx() { + while(!(read_reg(SPI_IP) & 1)) {} +} + +inline void waitrx() { + while(read_reg(SPI_IP) & 2)) {} +} + + // Initialize Sifive FU540 based SPI Controller void spi_init() { - // Disable interrupts by default - // write_reg(SPI_IE, 0); + // Enable interrupts + write_reg(SPI_IE, 0x3); + // Set TXMARK to 1. If the number of entries is < 1 + // IP's txwm field will go high. + // Set RXMARK to 0. If the number of entries is > 0 + // IP's rwxm field will go high. write_reg(SPI_TXMARK, 1); write_reg(SPI_RXMARK, 0); + // Set Delay 0 to default write_reg(SPI_DELAY0, SIFIVE_SPI_DELAY0_CSSCK(1) | SIFIVE_SPI_DELAY0_SCKCS(1)); + // Set Delay 1 to default write_reg(SPI_DELAY1, SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0)); + + // Initialize the SPI controller clock to + // div = (20MHz/(2*400kHz)) - 1 = 24 = 0x18 + write_reg(SPI_SCKDIV, 0x18); } - -// Sends and receives a single byte -uint8_t spi_send_byte(uint8_t byte) { - // Write byte to transfer fifo - write_reg(SPI_TXDATA, byte); - - /* Not sure how necessary this is. Will keep commented for now. - // Wait a decent amount of time for data to send - for (int i = 0; i < 100; i++) { - __asm__ volatile("nop"); - } - */ - - // Wait for data to come into receive fifo - while (read_reg(SPI_IP) != 2) {} - - // Read received data - result = read_reg(SPI_RXDATA); - - // Return result - return result; -} - diff --git a/fpga/zsbl/spi.h b/fpga/zsbl/spi.h index 6bae450ae..a035f0ab5 100644 --- a/fpga/zsbl/spi.h +++ b/fpga/zsbl/spi.h @@ -4,26 +4,28 @@ #include +#define SPI_BASE 0x13000 /* Base address of SPI device used for SDC */ + /* register offsets */ -#define SPI_SCKDIV 0x00 /* Serial clock divisor */ -#define SPI_SCKMODE 0x04 /* Serial clock mode */ -#define SPI_CSID 0x10 /* Chip select ID */ -#define SPI_CSDEF 0x14 /* Chip select default */ -#define SPI_CSMODE 0x18 /* Chip select mode */ -#define SPI_DELAY0 0x28 /* Delay control 0 */ -#define SPI_DELAY1 0x2c /* Delay control 1 */ -#define SPI_FMT 0x40 /* Frame format */ -#define SPI_TXDATA 0x48 /* Tx FIFO data */ -#define SPI_RXDATA 0x4c /* Rx FIFO data */ -#define SPI_TXMARK 0x50 /* Tx FIFO [<35;39;29Mwatermark */ -#define SPI_RXMARK 0x54 /* Rx FIFO watermark */ +#define SPI_SCKDIV SPI_BASE + 0x00 /* Serial clock divisor */ +#define SPI_SCKMODE SPI_BASE + 0x04 /* Serial clock mode */ +#define SPI_CSID SPI_BASE + 0x10 /* Chip select ID */ +#define SPI_CSDEF SPI_BASE + 0x14 /* Chip select default */ +#define SPI_CSMODE SPI_BASE + 0x18 /* Chip select mode */ +#define SPI_DELAY0 SPI_BASE + 0x28 /* Delay control 0 */ +#define SPI_DELAY1 SPI_BASE + 0x2c /* Delay control 1 */ +#define SPI_FMT SPI_BASE + 0x40 /* Frame format */ +#define SPI_TXDATA SPI_BASE + 0x48 /* Tx FIFO data */ +#define SPI_RXDATA SPI_BASE + 0x4c /* Rx FIFO data */ +#define SPI_TXMARK SPI_BASE + 0x50 /* Tx FIFO [<35;39;29Mwatermark */ +#define SPI_RXMARK SPI_BASE + 0x54 /* Rx FIFO watermark */ /* Non-implemented -#define SPI_FCTRL 0x60 // SPI flash interface control -#define SPI_FFMT 0x64 // SPI flash instruction format +#define SPI_FCTRL SPI_BASE + 0x60 // SPI flash interface control +#define SPI_FFMT SPI_BASE + 0x64 // SPI flash instruction format */ -#define SPI_IE 0x70 /* Interrupt Enable Register */ -#define SPI_IP 0x74 /* Interrupt Pendings Register */ +#define SPI_IE SPI_BASE + 0x70 /* Interrupt Enable Register */ +#define SPI_IP SPI_BASE + 0x74 /* Interrupt Pendings Register */ /* delay0 bits */ #define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x)) @@ -37,9 +39,22 @@ #define SIFIVE_SPI_DELAY1_INTERXFR(x) ((u32)(x) << 16) #define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16) -void write_reg(uintptr_t addr, uint32_t value); -uint32_t read_reg(uintptr_t addr); -uint8_t spi_send_byte(uint8_t byte); +/* csmode bits */ +#define SIFIVE_SPI_CSMODE_MODE_AUTO 0U +#define SIFIVE_SPI_CSMODE_MODE_HOLD 2U +#define SIFIVE_SPI_CSMODE_MODE_OFF 3U + + +#define WAITTX while(!(read_reg(SPI_IP) & 1) {} +#define WAITRX while(read_reg(SPI_IP) & 2) {} + +inline void write_reg(uintptr_t addr, uint32_t value); +inline uint32_t read_reg(uintptr_t addr); +inline void spi_sendbyte(uint8_t byte); +inline void waittx(); +inline void waitrx(); +uint8_t spi_txrx(uint8_t byte); +inline uint8_t spi_readbyte(); void spi_init(); From 8ca565ed53db8bd59e41c4bd434e773d13b187f3 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 22 Jul 2024 17:44:04 -0500 Subject: [PATCH 097/219] Updated for a better ILA rvvi debugger. --- config/derivlist.txt | 4 ++-- fpga/constraints/small-debug-rvvi.xdc | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/config/derivlist.txt b/config/derivlist.txt index 01ad315e5..048adcb21 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -57,9 +57,9 @@ EXT_MEM_RANGE 64'h0FFFFFFF SDC_SUPPORTED 1 PLIC_SDC_ID 32'd20 BPRED_SIZE 32'd12 -RVVI_SYNTH_SUPPORTED 0 +RVVI_SYNTH_SUPPORTED 1 RVVI_INIT_TIME_OUT 32'd100000000 -RVVI_PACKET_DELAY 32'd350 +RVVI_PACKET_DELAY 32'd400 # The syn configurations are trimmed down for faster synthesis. diff --git a/fpga/constraints/small-debug-rvvi.xdc b/fpga/constraints/small-debug-rvvi.xdc index 0441f4fa2..629cde561 100644 --- a/fpga/constraints/small-debug-rvvi.xdc +++ b/fpga/constraints/small-debug-rvvi.xdc @@ -1,5 +1,5 @@ create_debug_core u_ila_0 ila -set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_0] +set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_0] set_property C_TRIGIN_EN true [get_debug_cores u_ila_0] set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] From 8c8e1a3fef65caa525dcd114fa73c63bb6699098 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 22 Jul 2024 23:10:45 -0700 Subject: [PATCH 098/219] Update section header function usage --- bin/wally-distro-check.sh | 19 ++++++++++++++----- bin/wally-package-install.sh | 14 ++------------ bin/wally-tool-chain-install.sh | 9 --------- 3 files changed, 16 insertions(+), 26 deletions(-) diff --git a/bin/wally-distro-check.sh b/bin/wally-distro-check.sh index cec2ac509..73eb58fba 100755 --- a/bin/wally-distro-check.sh +++ b/bin/wally-distro-check.sh @@ -38,11 +38,20 @@ WARNING_COLOR='\033[93m' FAIL_COLOR='\033[91m' ENDC='\033[0m' # Reset to default color -printf "${SECTION_COLOR}%$(tput cols)s" | tr ' ' '#' -printf "%$(tput cols)s" | tr ' ' '#' -echo -e "Checking System Requirements and Configuring Installation" -printf "%$(tput cols)s" | tr ' ' '#' -printf "%$(tput cols)s${ENDC}" | tr ' ' '#' +# Print section header +section_header() { + if tput cols > /dev/null 2>&1; then + printf "${SECTION_COLOR}%$(tput cols)s" | tr ' ' '#' + printf "%$(tput cols)s" | tr ' ' '#' + echo -e "$1" + printf "%$(tput cols)s" | tr ' ' '#' + printf "%$(tput cols)s${ENDC}" | tr ' ' '#' + else + echo -e "${SECTION_COLOR}$1${ENDC}" + fi +} + +section_header "Checking System Requirements and Configuring Installation" # Get distribution information test -e /etc/os-release && os_release="/etc/os-release" || os_release="/usr/lib/os-release" diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index 52ce5a9e2..5228d6855 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -84,12 +84,7 @@ fi # Check if required packages are installed or install/update them depending on passed flag. if [ "${1}" == "--check" ]; then - printf "${SECTION_COLOR}%$(tput cols)s" | tr ' ' '#' - printf "%$(tput cols)s" | tr ' ' '#' - echo -e "Checking Dependencies from Package Manager" - printf "%$(tput cols)s" | tr ' ' '#' - printf "%$(tput cols)s${ENDC}" | tr ' ' '#' - + section_header "Checking Dependencies from Package Manager" if [ "$FAMILY" == rhel ]; then for pack in "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${SAIL_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OTHER_PACKAGES[@]}"; do rpm -q "$pack" > /dev/null || (echo -e "${FAIL_COLOR}Missing packages detected (${WARNING_COLOR}$pack${FAIL_COLOR}). Run as root to auto-install or run wally-package-install.sh first.${ENDC}" && exit 1) @@ -104,12 +99,7 @@ else # Check if root, otherwise exit with error message [ "${EUID:=$(id -u)}" -ne 0 ] && echo -e "\n${FAIL_COLOR}Must be run as root${ENDC}" && exit 1 - printf "${SECTION_COLOR}%$(tput cols)s" | tr ' ' '#' - printf "%$(tput cols)s" | tr ' ' '#' - echo -e ""Installing/Updating Dependencies from Package Manager"" - printf "%$(tput cols)s" | tr ' ' '#' - printf "%$(tput cols)s${ENDC}" | tr ' ' '#' - + section_header "Installing/Updating Dependencies from Package Manager" # Enable extra repos necessary for rhel if [ "$FAMILY" == rhel ]; then sudo dnf install -y dnf-plugins-core diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 804deee30..2a4b7c4e8 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -52,15 +52,6 @@ error() { exit 1 } -# Print section header -section_header() { - printf "${SECTION_COLOR}%$(tput cols)s" | tr ' ' '#' - printf "%$(tput cols)s" | tr ' ' '#' - echo -e "$1" - printf "%$(tput cols)s" | tr ' ' '#' - printf "%$(tput cols)s${ENDC}" | tr ' ' '#' -} - # Check if a git repository exists, is up to date, and has been installed # Clones the repository if it doesn't exist git_check() { From 4e8cc68d3e49c2212b0327e37474a867fd65fbb8 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 22 Jul 2024 21:35:21 -0700 Subject: [PATCH 099/219] Add DEBIAN_FRONTEND=noninteractive to apt --- bin/wally-package-install.sh | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index 5228d6855..75b12a0ed 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -47,7 +47,7 @@ fi # Packages are grouped by which tool requires them. If multiple tools need a package, it is included in the first tool only if [ "$FAMILY" == rhel ]; then PACKAGE_MANAGER="dnf" - UPDATE_COMMAND="sudo dnf update -y" + UPDATE_COMMAND="sudo $PACKAGE_MANAGER update -y" GENERAL_PACKAGES=(which rsync git make cmake python3.12 python3-pip curl wget ftp tar pkgconf-pkg-config dialog mutt ssmtp) GNU_PACKAGES=(autoconf automake libmpc-devel mpfr-devel gmp-devel gawk bison flex texinfo gperf libtool patchutils bc gcc gcc-c++ zlib-devel expat-devel libslirp-devel) QEMU_PACKAGES=(glib2-devel libfdt-devel pixman-devel bzip2 ninja-build) @@ -62,8 +62,8 @@ if [ "$FAMILY" == rhel ]; then # A newer version of gcc is required for qemu OTHER_PACKAGES=(gcc-toolset-13) elif [ "$FAMILY" == ubuntu ]; then - PACKAGE_MANAGER=apt-get - UPDATE_COMMAND="sudo apt-get update -y && sudo apt-get upgrade -y --with-new-pkgs" + PACKAGE_MANAGER="DEBIAN_FRONTEND=noninteractive apt-get" + UPDATE_COMMAND="sudo $PACKAGE_MANAGER update -y && sudo $PACKAGE_MANAGER upgrade -y --with-new-pkgs" GENERAL_PACKAGES=(rsync git make cmake python3 python3-pip python3-venv curl wget ftp tar pkg-config dialog mutt ssmtp) GNU_PACKAGES=(autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat1-dev ninja-build libglib2.0-dev libslirp-dev) QEMU_PACKAGES=(libfdt-dev libpixman-1-dev) @@ -120,6 +120,6 @@ else # Update and Upgrade tools eval "$UPDATE_COMMAND" # Install packages listed above using appropriate package manager - sudo "$PACKAGE_MANAGER" install -y "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${SAIL_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OTHER_PACKAGES[@]}" + sudo $PACKAGE_MANAGER install -y "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${SAIL_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OTHER_PACKAGES[@]}" echo -e "${SUCCESS_COLOR}Packages successfully installed.${ENDC}" fi From 16dd728ed68dbe01797f7a363ce1781b51fba902 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 22 Jul 2024 21:58:19 -0700 Subject: [PATCH 100/219] Use requirements file for pip packages --- bin/requirements.txt | 13 +++++++++++++ bin/wally-tool-chain-install.sh | 14 +++----------- 2 files changed, 16 insertions(+), 11 deletions(-) create mode 100644 bin/requirements.txt diff --git a/bin/requirements.txt b/bin/requirements.txt new file mode 100644 index 000000000..9f0f1428f --- /dev/null +++ b/bin/requirements.txt @@ -0,0 +1,13 @@ +adjustText>=1.2 +lief>=0.14.1 +Markdown>=3.6 +matplotlib>=3.9.0 +PyYAML>=5.2 +riscof @ git+https://github.com/riscv/riscof.git +riscv-config>=3.18.3 +riscv-isac>=0.18.0 +scikit-learn>=1.5.0 +scipy>=1.14.0 +Sphinx>=7.3.7 +sphinx-rtd-theme>=2.0.0 +testresources>=2.0.1 diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 2a4b7c4e8..1bc7e1942 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -144,11 +144,10 @@ fi source "$RISCV"/riscv-python/bin/activate # activate python virtual environment -# Install python packages +# Install python packages, including RISCOF (https://github.com/riscv-software-src/riscof.git) +# RISCOF is a RISC-V compliance test framework that is used to run the RISC-V Arch Tests. STATUS="python packages" -pip install -U pip -pip install -U sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown pyyaml testresources riscv_config -pip install -U riscv_isac # to generate new tests, such as quads with fp_dataset.py +pip install --upgrade pip && pip install -r "$dir"/requirements.txt # z3 is needed for sail and not availabe from dnf for rhel 8 if (( RHEL_VERSION == 8 )); then @@ -381,13 +380,6 @@ else fi -# RISCOF (https://github.com/riscv-software-src/riscof.git) -# RISCOF is a RISC-V compliance test framework that is used to run the RISC-V Arch Tests. -section_header "Installing/Updating RISCOF" -STATUS="RISCOF" -pip3 install git+https://github.com/riscv-software-src/riscof.git - - # OSU Skywater 130 cell library (https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12) # The OSU Skywater 130 cell library is a standard cell library that is used to synthesize Wally. section_header "Installing/Updating OSU Skywater 130 cell library" From d045fb6662269671744d72f2e05b8ca612f845c3 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 22 Jul 2024 22:37:23 -0700 Subject: [PATCH 101/219] Update python versions --- bin/wally-package-install.sh | 45 ++++++++++++++++++--------------- bin/wally-tool-chain-install.sh | 9 ++----- 2 files changed, 26 insertions(+), 28 deletions(-) diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index 75b12a0ed..001de99ba 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -46,14 +46,15 @@ fi # Generate list of packages to install and package manager commands based on distro # Packages are grouped by which tool requires them. If multiple tools need a package, it is included in the first tool only if [ "$FAMILY" == rhel ]; then + PYTHON_VERSION=python3.12 PACKAGE_MANAGER="dnf" UPDATE_COMMAND="sudo $PACKAGE_MANAGER update -y" - GENERAL_PACKAGES=(which rsync git make cmake python3.12 python3-pip curl wget ftp tar pkgconf-pkg-config dialog mutt ssmtp) - GNU_PACKAGES=(autoconf automake libmpc-devel mpfr-devel gmp-devel gawk bison flex texinfo gperf libtool patchutils bc gcc gcc-c++ zlib-devel expat-devel libslirp-devel) - QEMU_PACKAGES=(glib2-devel libfdt-devel pixman-devel bzip2 ninja-build) - SPIKE_PACKAGES=(dtc boost-regex boost-system) - VERILATOR_PACKAGES=(help2man perl clang ccache gperftools numactl mold) - BUILDROOT_PACKAGES=(ncurses-base ncurses ncurses-libs ncurses-devel gcc-gfortran) + GENERAL_PACKAGES+=(which rsync git make cmake "$PYTHON_VERSION" "$PYTHON_VERSION"-pip curl wget ftp tar pkgconf-pkg-config dialog mutt ssmtp) + GNU_PACKAGES+=(autoconf automake libmpc-devel mpfr-devel gmp-devel gawk bison flex texinfo gperf libtool patchutils bc gcc gcc-c++ zlib-devel expat-devel libslirp-devel) + QEMU_PACKAGES+=(glib2-devel libfdt-devel pixman-devel bzip2 ninja-build) + SPIKE_PACKAGES+=(dtc boost-regex boost-system) + VERILATOR_PACKAGES+=(help2man perl clang ccache gperftools numactl mold) + BUILDROOT_PACKAGES+=(ncurses-base ncurses ncurses-libs ncurses-devel gcc-gfortran) # Extra packages not availale in rhel8, nice for Verilator and needed for sail respectively if (( RHEL_VERSION == 9 )); then VERILATOR_PACKAGES+=(perl-doc) @@ -62,23 +63,25 @@ if [ "$FAMILY" == rhel ]; then # A newer version of gcc is required for qemu OTHER_PACKAGES=(gcc-toolset-13) elif [ "$FAMILY" == ubuntu ]; then + if (( UBUNTU_VERSION >= 24 )); then + PYTHON_VERSION=python3.12 + VERILATOR_PACKAGES+=(mold) # Not availale in Ubuntu 20.04, nice for Verilator + elif (( UBUNTU_VERSION == 22 )); then + PYTHON_VERSION=python3.11 + VERILATOR_PACKAGES+=(mold) # Not availale in Ubuntu 20.04, nice for Verilator + elif (( UBUNTU_VERSION == 20 )); then + PYTHON_VERSION=python3.11 + OTHER_PACKAGES+=(gcc-10 g++-10 cpp-10) # Newer version of gcc needed for Verilator + fi PACKAGE_MANAGER="DEBIAN_FRONTEND=noninteractive apt-get" UPDATE_COMMAND="sudo $PACKAGE_MANAGER update -y && sudo $PACKAGE_MANAGER upgrade -y --with-new-pkgs" - GENERAL_PACKAGES=(rsync git make cmake python3 python3-pip python3-venv curl wget ftp tar pkg-config dialog mutt ssmtp) - GNU_PACKAGES=(autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat1-dev ninja-build libglib2.0-dev libslirp-dev) - QEMU_PACKAGES=(libfdt-dev libpixman-1-dev) - SPIKE_PACKAGES=(device-tree-compiler libboost-regex-dev libboost-system-dev) - VERILATOR_PACKAGES=(help2man perl g++ clang ccache libunwind-dev libgoogle-perftools-dev numactl perl-doc libfl2 libfl-dev zlib1g) - SAIL_PACKAGES=(opam z3) - BUILDROOT_PACKAGES=(ncurses-base ncurses-bin libncurses-dev gfortran) - # Extra packages not availale in Ubuntu 20.04, nice for Verilator - if (( UBUNTU_VERSION >= 22 )); then - VERILATOR_PACKAGES+=(mold) - fi - # Newer version of gcc needed for Ubuntu 20.04 for Verilator - if (( UBUNTU_VERSION == 20 )); then - OTHER_PACKAGES=(gcc-10 g++-10 cpp-10) - fi + GENERAL_PACKAGES+=(rsync git make cmake "$PYTHON_VERSION" python3-pip "$PYTHON_VERSION"-venv curl wget ftp tar pkg-config dialog mutt ssmtp) + GNU_PACKAGES+=(autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat1-dev ninja-build libglib2.0-dev libslirp-dev) + QEMU_PACKAGES+=(libfdt-dev libpixman-1-dev) + SPIKE_PACKAGES+=(device-tree-compiler libboost-regex-dev libboost-system-dev) + VERILATOR_PACKAGES+=(help2man perl g++ clang ccache libunwind-dev libgoogle-perftools-dev numactl perl-doc libfl2 libfl-dev zlib1g) + SAIL_PACKAGES+=(opam z3) + BUILDROOT_PACKAGES+=(ncurses-base ncurses-bin libncurses-dev gfortran) fi diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 1bc7e1942..2511adfa0 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -59,7 +59,7 @@ git_check() { local url=$2 local check=$3 local branch="${4:-master}" - if [[ ((! -e $repo) && ($(git clone "$url") || true)) || ($(cd "$repo"; git fetch; git rev-parse HEAD) != $(cd $repo; git rev-parse origin/"$branch")) || (! -e $check) ]]; then + if [[ ((! -e $repo) && ($(git clone "$url") || true)) || ($(cd "$repo"; git fetch; git rev-parse HEAD) != $(cd "$repo"; git rev-parse origin/"$branch")) || (! -e $check) ]]; then return 0 else return 1 @@ -131,12 +131,7 @@ section_header "Setting up Python Environment" STATUS="python virtual environment" cd "$RISCV" if [ ! -e "$RISCV"/riscv-python/bin/activate ]; then - # If python3.12 is avaiable, use it. Otherise, use whatever version of python3 is installed. - if [ "$(which python3.12)" ]; then - python3.12 -m venv riscv-python - else - python3 -m venv riscv-python - fi + "$PYTHON_VERSION" -m venv riscv-python echo -e "${OK_COLOR}Python virtual environment created.\nInstalling pip packages.${ENDC}" else echo -e "${OK_COLOR}Python virtual environment already exists.\nUpdating pip packages.${ENDC}" From e4c38dd766d0f7966b4e1a7ef02b849dcdb9a02d Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 22 Jul 2024 22:46:00 -0700 Subject: [PATCH 102/219] Add logs and reduce console output --- bin/wally-tool-chain-install.sh | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 2511adfa0..a2c6a0413 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -209,7 +209,7 @@ if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain git reset --hard && git clean -f && git checkout master && git pull git pull ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" - make -j ${NUM_THREADS} + make -j ${NUM_THREADS} 2>&1 | tee "$RISCV"/logs/riscv-gnu-toolchain.log | grep -iE "(warning|error|fail|success|stamp)" if [ "$clean" ]; then cd "$RISCV" rm -rf riscv-gnu-toolchain @@ -236,7 +236,7 @@ if git_check "elf2hex" "https://github.com/sifive/elf2hex.git" "$RISCV/bin/riscv git reset --hard && git clean -f && git checkout master && git pull autoreconf -i ./configure --target=riscv64-unknown-elf --prefix="$RISCV" - make + make make install if [ "$clean" ]; then cd "$RISCV" @@ -258,8 +258,8 @@ if git_check "qemu" "https://github.com/qemu/qemu" "$RISCV/include/qemu-plugin.h git reset --hard && git clean -f && git checkout master && git pull --recurse-submodules -j ${NUM_THREADS} git submodule update --init --recursive ./configure --target-list=riscv64-softmmu --prefix="$RISCV" - make -j ${NUM_THREADS} - make install + make -j ${NUM_THREADS} 2>&1 | tee "$RISCV"/logs/qemu.log | grep -iE "(warning|error|fail|success)" + make install 2>&1 | tee -a "$RISCV"/logs/qemu.log | grep -iE "(warning|error|fail|success)" if [ "$clean" ]; then cd "$RISCV" rm -rf qemu @@ -281,8 +281,8 @@ if git_check "riscv-isa-sim" "https://github.com/riscv-software-src/riscv-isa-si mkdir -p build cd build ../configure --prefix="$RISCV" - make -j ${NUM_THREADS} - make install + make -j ${NUM_THREADS} 2>&1 | tee "$RISCV"/logs/spike.log | grep -iE "(warning|error|fail|success)" + make install 2>&1 | tee -a "$RISCV"/logs/spike.log | grep -iE "(warning|error|fail|success)" if [ "$clean" ]; then cd "$RISCV" rm -rf riscv-isa-sim @@ -306,8 +306,8 @@ if git_check "verilator" "https://github.com/verilator/verilator" "$RISCV/share/ git reset --hard && git clean -f && git checkout master && git pull autoconf ./configure --prefix="$RISCV" - make -j ${NUM_THREADS} - make install + make -j ${NUM_THREADS} 2>&1 | tee "$RISCV"/logs/verilator.log | grep -iE "(warning|error|fail|success)" + make install 2>&1 | tee -a "$RISCV"/logs/verilator.log | grep -iE "(warning|error|fail|success)" if [ "$clean" ]; then cd "$RISCV" rm -rf verilator @@ -361,8 +361,8 @@ if git_check "sail-riscv" "https://github.com/riscv/sail-riscv.git" "$RISCV/bin/ cd sail-riscv git reset --hard && git clean -f && git checkout master && git pull export OPAMCLI=2.0 # Sail is not compatible with opam 2.1 as of 4/16/24 - ARCH=RV64 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV64 - ARCH=RV32 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV32 + ARCH=RV64 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV64 2>&1 | tee "$RISCV"/logs/sail_model.log | grep -iE "(warning|error|fail|success)" + ARCH=RV32 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV32 2>&1 | tee -a "$RISCV"/logs/sail_model.log | grep -iE "(warning|error|fail|success)" cp -f c_emulator/riscv_sim_RV64 "$RISCV"/bin/riscv_sim_RV64 cp -f c_emulator/riscv_sim_RV32 "$RISCV"/bin/riscv_sim_RV32 if [ "$clean" ]; then @@ -415,4 +415,8 @@ else echo -e "You may need to manually update it if there were changes upstream.${ENDC}" fi +if [ "$clean" ]; then + rm -rf "$RISCV"/logs +fi + echo -e "${SUCCESS_COLOR}${BOLD}\n\nINSTALLATION SUCCESSFUL\n\n${ENDC}" From d096e2e4f8f9e6eb6d2daaf3f5f8f2f77733cfc0 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 23 Jul 2024 00:16:27 -0700 Subject: [PATCH 103/219] Fix python version for Ubuntu 20.04 --- bin/wally-package-install.sh | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index 001de99ba..ae70c1358 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -56,7 +56,7 @@ if [ "$FAMILY" == rhel ]; then VERILATOR_PACKAGES+=(help2man perl clang ccache gperftools numactl mold) BUILDROOT_PACKAGES+=(ncurses-base ncurses ncurses-libs ncurses-devel gcc-gfortran) # Extra packages not availale in rhel8, nice for Verilator and needed for sail respectively - if (( RHEL_VERSION == 9 )); then + if (( RHEL_VERSION >= 9 )); then VERILATOR_PACKAGES+=(perl-doc) SAIL_PACKAGES=(z3) fi @@ -66,11 +66,11 @@ elif [ "$FAMILY" == ubuntu ]; then if (( UBUNTU_VERSION >= 24 )); then PYTHON_VERSION=python3.12 VERILATOR_PACKAGES+=(mold) # Not availale in Ubuntu 20.04, nice for Verilator - elif (( UBUNTU_VERSION == 22 )); then + elif (( UBUNTU_VERSION >= 22 )); then PYTHON_VERSION=python3.11 VERILATOR_PACKAGES+=(mold) # Not availale in Ubuntu 20.04, nice for Verilator - elif (( UBUNTU_VERSION == 20 )); then - PYTHON_VERSION=python3.11 + elif (( UBUNTU_VERSION >= 20 )); then + PYTHON_VERSION=python3.9 OTHER_PACKAGES+=(gcc-10 g++-10 cpp-10) # Newer version of gcc needed for Verilator fi PACKAGE_MANAGER="DEBIAN_FRONTEND=noninteractive apt-get" From 36ffeb2dca1cb4c53e3724dbf946ad117b3da7f0 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 23 Jul 2024 01:03:10 -0700 Subject: [PATCH 104/219] Fix minimum scipy version for Ubuntu20.04 --- bin/requirements.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/requirements.txt b/bin/requirements.txt index 9f0f1428f..67b51ee2e 100644 --- a/bin/requirements.txt +++ b/bin/requirements.txt @@ -7,7 +7,7 @@ riscof @ git+https://github.com/riscv/riscof.git riscv-config>=3.18.3 riscv-isac>=0.18.0 scikit-learn>=1.5.0 -scipy>=1.14.0 +scipy>=1.13.0 Sphinx>=7.3.7 sphinx-rtd-theme>=2.0.0 testresources>=2.0.1 From a4a0a10879733874821032860cfeea7093a4f096 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 23 Jul 2024 04:38:13 -0700 Subject: [PATCH 105/219] Increased covergen.py functional coverage to 87.6% --- bin/regression-wally | 2 +- tests/testgen/covergen.py | 131 ++++++++++++++++++++++++-------- tests/testgen/covergen_footer.S | 6 ++ 3 files changed, 105 insertions(+), 34 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index 5a374b2d9..3040f584b 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -288,7 +288,7 @@ def addLockstepTestsByDir(dir, config, sim): for file in os.listdir(dir): if file.endswith(".elf"): fullfile = os.path.join(dir, file) - sim_log = sim_logdir + config + "_" + file + sim_log = sim_logdir + config + "_" + file + ".log" grepstring = "" tc = TestCase( name=file, diff --git a/tests/testgen/covergen.py b/tests/testgen/covergen.py index 06cf1bb83..2bf5f6a63 100755 --- a/tests/testgen/covergen.py +++ b/tests/testgen/covergen.py @@ -48,32 +48,48 @@ def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, xlen lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", x" + str(rs2) + " # perform operation\n" elif (test in shiftitype): lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1\n" - lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", " + shiftImm(immval, xlen) + " # perform operation\n" + if (test in shiftiwtype): + lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", " + shiftImm(immval, 32) + " # perform operation\n" + else: + lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", " + shiftImm(immval, xlen) + " # perform operation\n" elif (test in itype): lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1\n" lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", " + signedImm12(immval) + " # perform operation\n" elif (test in loaditype):#["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"] - pass - #lines = lines + "auipc x" + str(rs1) + ", 0x20" + " # add upper immediate value to pc \n" - #lines = lines + "addi x" + str(rs1) + ", x" + str(rs1) + ", " + signedImm12(-immval) + " # add immediate to lower part of rs1\n" - #lines = lines + test + " x" + str(rd) + ", " + signedImm12(immval) + "(x" + str(rs1) + ") # perform operation\n" + if (rs1 != 0): + lines = lines + "li x" + str(rs2) + ", " + formatstr.format(rs2val) + " # initialize rs2\n" + lines = lines + "la x" + str(rs1) + ", scratch" + " # base address \n" + lines = lines + "addi x" + str(rs1) + ", x" + str(rs1) + ", " + signedImm12(-immval) + " # sub immediate from rs1 to counter offset\n" + if (xlen == 32): + storeop = "sw" + else: + storeop = "sd" + lines = lines + storeop + " x" + str(rs2) + ", " + signedImm12(immval) +" (x" + str(rs1) + ") # store value to put someting in memory\n" + lines = lines + test + " x" + str(rd) + ", " + signedImm12(immval) + "(x" + str(rs1) + ") # perform operation\n" +# lines = lines + test + " x" + str(rd) + ", 0(x" + str(rs1) + ") # perform operation\n" elif (test in stype):#["sb", "sh", "sw", "sd"] - #lines = lines + test + " x" + str(rs2) + ", " + signedImm12(immval) + "(x" + str(rs1) + ") # perform operation \n" - #lines = lines + test + " x" + str(rs2) + ", " "0(x" + str(rs1) + ") # perform operation \n" - #print("Error: %s type not implemented yet" % test) - pass + if (rs1 != 0): + if (rs2 == rs1): # make sure registers are different so they don't conflict + rs2 = (rs1 + 1) % 32 + if (rs2 == 0): + rs2 = 1 + lines = lines + "li x" + str(rs2) + ", " + formatstr.format(rs2val) + " # initialize rs2\n" + lines = lines + "la x" + str(rs1) + ", scratch" + " # base address \n" + lines = lines + "addi x" + str(rs1) + ", x" + str(rs1) + ", " + signedImm12(-immval) + " # sub immediate from rs1 to counter offset\n" + lines = lines + test + " x" + str(rs2) + ", " + signedImm12(immval) + "(x" + str(rs1) + ") # perform operation \n" elif (test in btype):#["beq", "bne", "blt", "bge", "bltu", "bgeu"] - if (randint(1,100) > 50): - rs1val = rs2val - lines = lines + "# same values in both registers\n" - lines = lines + "nop\n" - lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1\n" - lines = lines + "li x" + str(rs2) + ", " + formatstr.format(rs2val) + " # initialize rs2\n" - lines = lines + test + " x" + str(rs1) + ", x" + str(rs2) + ", some_label_for_sb_types_" + str(immval) + "+4" + " # perform operation \n" - lines = lines + "addi x0, x1, 1\n" - lines = lines + "some_label_for_sb_types_" + str(immval) + ":\n" - lines = lines + "addi x0, x2, 2\n" - lines = lines + "nop\nnop\nnop\nnop\nnop\n" + for same in range(2): + if (same): + rs1val = rs2val + lines = lines + "# same values in both registers\n" + lines = lines + "nop\n" + lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1\n" + lines = lines + "li x" + str(rs2) + ", " + formatstr.format(rs2val) + " # initialize rs2\n" + lines = lines + test + " x" + str(rs1) + ", x" + str(rs2) + ", some_label_for_btype_" + str(immval) + str(same) + " # perform operation \n" + lines = lines + "addi x0, x1, 1\n" + lines = lines + "some_label_for_btype_" + str(immval)+ str(same) + ":\n" + lines = lines + "addi x0, x2, 2\n" + lines = lines + "nop\nnop\nnop\nnop\nnop\n" elif (test in jtype):#["jal"] lines = lines + "jal x" + str(rd) + ", 1f # perform operation\n" lines = lines + "nop\n" @@ -151,7 +167,7 @@ def make_rd_rs1_rs2(test, xlen): def make_rs1_rs2(test, xlen): for r in range(32): [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize() - desc = "cmp_rd_rs1_rs2 (Test rs1 = rs2 = x" + str(r) + ")" + desc = "cmp_rs1_rs2 (Test rs1 = rs2 = x" + str(r) + ")" writeCovVector(desc, r, r, rd, rs1val, rs2val, immval, rdval, test, xlen) def make_rs1_maxvals(test, xlen): @@ -171,15 +187,15 @@ def make_rd_maxvals(test, xlen): # rs1 = 0, rs2 = v, others are random [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize() desc = "cp_rd_maxvals (Test rd value = " + hex(v) + ")" - writeCovVector(desc, rs1, 0, rd, v, rs2val, immval, rdval, test, xlen) + writeCovVector(desc, rs1, 0, rd, v, rs2val, 0, rdval, test, xlen) # rs1, rs2 = v, others are random [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize() desc = "cp_rd_maxvals (Test rd value = " + hex(v) + ")" - writeCovVector(desc, rs1, rs2, rd, v, v, immval, rdval, test, xlen) + writeCovVector(desc, rs1, rs2, rd, v, v, v, rdval, test, xlen) # rs1 = all 1s, rs2 = v, others are random [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize() desc = "cp_rd_maxvals (Test rd value = " + hex(v) + ")" - writeCovVector(desc, rs1, rs2, rd, -1, v, immval, rdval, test, xlen) + writeCovVector(desc, rs1, rs2, rd, v, -1, -1, rdval, test, xlen) def make_rd_rs1_eqval(test, xlen): [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize() @@ -245,6 +261,53 @@ def make_imm_zero(test, xlen): desc = "cp_imm_zero" writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, 0, rdval, test, xlen) +def make_j_imm_ones_zeros(test, xlen): + for align in range(2,19): + lines = "\n# Testcase cp_imm_ones_zeros " + str(align) + "\n" + lines = lines + "li x1, " + formatstr.format(randint(0, 2**xlen-1)) + "\n" + lines = lines + "jal x20, 1f # jump to aligned address to stress immediate\n" + lines = lines + ".align " + str(align) + "\n" + lines = lines + "1:\n" + f.write(lines) + +def make_offset(test, xlen): + if (test in btype): + lines = "\n# Testcase cp_offset\n" + lines = lines + "j 2f # jump past backward branch target\n" + lines = lines + "1: j 3f # backward branch target: jump past backward branch\n" + lines = lines + "2: " + test + " x0, x0, 1b # backward branch\n" + lines = lines + "3: nop # done with sequence\n" + f.write(lines) + +def make_mem_hazard(test, xlen): + lines = "\n# Testcase mem_hazard (no dependency)\n" + lines = lines + "la x1, scratch\n" + lines = lines + test + " x2, 0(x1)\n" + f.write(lines) + +def make_cr_rs1_imm(test, xlen): + desc = "cp_cr_rs1_imm" + [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize() + for s1 in range(2): + for s2 in range(3): + if (s1): + rs1v = -abs(rs1val) + else: + rs1v = abs(rs1val) + if (s2 == 0): + immv = 0 + elif (s2 == 1): + immv = abs(immval) + else: + immv = -abs(immval) + writeCovVector(desc, rs1, rs2, rd, rs1v, rs2val, immv, rdval, test, xlen) + +def make_imm_shift(test, xlen): + desc = "cp_imm_shift" + for shift in range(0, xlen): + [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize() + writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, shift, rdval, test, xlen) + def write_tests(coverpoints, test, xlen): for coverpoint in coverpoints: if (coverpoint == "cp_asm_count"): @@ -298,23 +361,24 @@ def write_tests(coverpoints, test, xlen): elif (coverpoint == "cp_imm_sign"): make_imm_zero(test, xlen) elif (coverpoint == "cr_rs1_imm"): - pass #TODO (not if crosses are not needed) + make_cr_rs1_imm(test, xlen) elif (coverpoint == "cp_imm_ones_zeros"): - pass #TODO + if (test in jtype): + make_j_imm_ones_zeros(test, xlen) elif (coverpoint == "cp_mem_hazard"): - pass #TODO + make_mem_hazard(test, xlen) elif (coverpoint == "cp_imm_zero"): make_imm_zero(test, xlen) elif (coverpoint == "cp_mem_unaligned"): - pass #TODO + pass # seems this should be part of privileged tests elif (coverpoint == "cp_offset"): - pass #TODO + make_offset(test, xlen) elif (coverpoint == "cr_nord_rs1_rs2"): pass #TODO (not if crosses are not needed) elif (coverpoint == "cp_imm_shift"): - pass #TODO + make_imm_shift(test, xlen) elif (coverpoint == "cp_rd_boolean"): - pass #TODO + pass # covered by other generators else: print("Warning: " + coverpoint + " not implemented yet for " + test) @@ -352,8 +416,9 @@ rtype = ["add", "sub", "sll", "slt", "sltu", "xor", "srl", "sra", "or", "and", "mul", "mulh", "mulhsu", "mulhu", "div", "divu", "rem", "remu", "mulw", "divw", "divuw", "remw", "remuw"] loaditype = ["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"] -shiftitype = ["slli", "srli", "srai"] -itype = ["addi", "slti", "sltiu", "xori", "ori", "andi"] +shiftitype = ["slli", "srli", "srai", "slliw", "srliw", "sraiw"] +shiftiwtype = ["slliw", "srliw", "sraiw"] +itype = ["addi", "slti", "sltiu", "xori", "ori", "andi", "addiw"] stype = ["sb", "sh", "sw", "sd"] btype = ["beq", "bne", "blt", "bge", "bltu", "bgeu"] jtype = ["jal"] diff --git a/tests/testgen/covergen_footer.S b/tests/testgen/covergen_footer.S index 2e4abbbfc..9da7e65af 100644 --- a/tests/testgen/covergen_footer.S +++ b/tests/testgen/covergen_footer.S @@ -2,4 +2,10 @@ self_loop: j self_loop +.data + +.align 4 +scratch: + .bss 8 + .end From bb74a0f96b9ad3239385e1ba814844e273e345b9 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 23 Jul 2024 12:23:04 -0500 Subject: [PATCH 106/219] Resolved more lint errors in the rvvi synthesized hardware. --- src/rvvi/csrindextoaddr.sv | 77 +++++++++++++++++++++++++++++++++++++ src/rvvi/packetizer.sv | 2 +- src/wally/csrindextoaddr.sv | 77 ------------------------------------- 3 files changed, 78 insertions(+), 78 deletions(-) create mode 100644 src/rvvi/csrindextoaddr.sv delete mode 100644 src/wally/csrindextoaddr.sv diff --git a/src/rvvi/csrindextoaddr.sv b/src/rvvi/csrindextoaddr.sv new file mode 100644 index 000000000..0a843f491 --- /dev/null +++ b/src/rvvi/csrindextoaddr.sv @@ -0,0 +1,77 @@ +/////////////////////////////////////////// +// csrindextoaddr.sv +// +// Written: Rose Thompson ross1728@gmail.com +// Created: 24 January 2024 +// Modified: 24 January 2024 +// +// Purpose: Converts the rvvi CSR index into the CSR address +// +// Documentation: +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module csrindextoaddr #(parameter TOTAL_CSRS = 36) ( + input logic [TOTAL_CSRS-1:0] CSRWen, + output logic [11:0] CSRAddr); + + always_comb begin + case(CSRWen) + 36'h0_0000_0000: CSRAddr = 12'h000; + 36'h0_0000_0001: CSRAddr = 12'h300; + 36'h0_0000_0002: CSRAddr = 12'h310; + 36'h0_0000_0004: CSRAddr = 12'h305; + 36'h0_0000_0008: CSRAddr = 12'h341; + 36'h0_0000_0010: CSRAddr = 12'h306; + 36'h0_0000_0020: CSRAddr = 12'h320; + 36'h0_0000_0040: CSRAddr = 12'h302; + 36'h0_0000_0080: CSRAddr = 12'h303; + 36'h0_0000_0100: CSRAddr = 12'h344; + 36'h0_0000_0200: CSRAddr = 12'h304; + 36'h0_0000_0400: CSRAddr = 12'h301; + 36'h0_0000_0800: CSRAddr = 12'h30A; + 36'h0_0000_1000: CSRAddr = 12'hF14; + 36'h0_0000_2000: CSRAddr = 12'h340; + 36'h0_0000_4000: CSRAddr = 12'h342; + 36'h0_0000_8000: CSRAddr = 12'h343; + 36'h0_0001_0000: CSRAddr = 12'hF11; + 36'h0_0002_0000: CSRAddr = 12'hF12; + 36'h0_0004_0000: CSRAddr = 12'hF13; + 36'h0_0008_0000: CSRAddr = 12'hF15; + 36'h0_0010_0000: CSRAddr = 12'h34A; + 36'h0_0020_0000: CSRAddr = 12'h100; + 36'h0_0040_0000: CSRAddr = 12'h104; + 36'h0_0080_0000: CSRAddr = 12'h105; + 36'h0_0100_0000: CSRAddr = 12'h141; + 36'h0_0200_0000: CSRAddr = 12'h106; + 36'h0_0400_0000: CSRAddr = 12'h10A; + 36'h0_0800_0000: CSRAddr = 12'h180; + 36'h0_1000_0000: CSRAddr = 12'h140; + 36'h0_2000_0000: CSRAddr = 12'h143; + 36'h0_4000_0000: CSRAddr = 12'h142; + 36'h0_8000_0000: CSRAddr = 12'h144; + 36'h1_0000_0000: CSRAddr = 12'h14D; + 36'h2_0000_0000: CSRAddr = 12'h001; + 36'h4_0000_0000: CSRAddr = 12'h002; + 36'h8_0000_0000: CSRAddr = 12'h003; + default : CSRAddr = 12'h000; + endcase + end +endmodule + diff --git a/src/rvvi/packetizer.sv b/src/rvvi/packetizer.sv index cf99b9038..97c57415e 100644 --- a/src/rvvi/packetizer.sv +++ b/src/rvvi/packetizer.sv @@ -129,7 +129,7 @@ module packetizer import cvw::*; #(parameter cvw_t P, assign Tag = 32'b0; assign EthType = 16'h005c; - assign RvviAxiWdata = TotalFrameWords[WordCount]; + assign RvviAxiWdata = TotalFrameWords[WordCount[4:0]]; assign RvviAxiWstrb = '1; assign RvviAxiWlast = BurstDone & (CurrState == STATE_TRANS); assign RvviAxiWvalid = (CurrState == STATE_TRANS); diff --git a/src/wally/csrindextoaddr.sv b/src/wally/csrindextoaddr.sv deleted file mode 100644 index 8b2d9e6b7..000000000 --- a/src/wally/csrindextoaddr.sv +++ /dev/null @@ -1,77 +0,0 @@ -/////////////////////////////////////////// -// csrindextoaddr.sv -// -// Written: Rose Thompson ross1728@gmail.com -// Created: 24 January 2024 -// Modified: 24 January 2024 -// -// Purpose: Converts the rvvi CSR index into the CSR address -// -// Documentation: -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module csrindextoaddr #(parameter TOTAL_CSRS = 36) ( - input logic [TOTAL_CSRS-1:0] CSRWen, - output logic [11:0] CSRAddr); - - always_comb begin - case(CSRWen) - 36'h0_0000_0000: CSRAddr = 13'h000; - 36'h0_0000_0001: CSRAddr = 13'h300; - 36'h0_0000_0002: CSRAddr = 13'h310; - 36'h0_0000_0004: CSRAddr = 13'h305; - 36'h0_0000_0008: CSRAddr = 13'h341; - 36'h0_0000_0010: CSRAddr = 13'h306; - 36'h0_0000_0020: CSRAddr = 13'h320; - 36'h0_0000_0040: CSRAddr = 13'h302; - 36'h0_0000_0080: CSRAddr = 13'h303; - 36'h0_0000_0100: CSRAddr = 13'h344; - 36'h0_0000_0200: CSRAddr = 13'h304; - 36'h0_0000_0400: CSRAddr = 13'h301; - 36'h0_0000_0800: CSRAddr = 13'h30A; - 36'h0_0000_1000: CSRAddr = 13'hF14; - 36'h0_0000_2000: CSRAddr = 13'h340; - 36'h0_0000_4000: CSRAddr = 13'h342; - 36'h0_0000_8000: CSRAddr = 13'h343; - 36'h0_0001_0000: CSRAddr = 13'hF11; - 36'h0_0002_0000: CSRAddr = 13'hF12; - 36'h0_0004_0000: CSRAddr = 13'hF13; - 36'h0_0008_0000: CSRAddr = 13'hF15; - 36'h0_0010_0000: CSRAddr = 13'h34A; - 36'h0_0020_0000: CSRAddr = 13'h100; - 36'h0_0040_0000: CSRAddr = 13'h104; - 36'h0_0080_0000: CSRAddr = 13'h105; - 36'h0_0100_0000: CSRAddr = 13'h141; - 36'h0_0200_0000: CSRAddr = 13'h106; - 36'h0_0400_0000: CSRAddr = 13'h10A; - 36'h0_0800_0000: CSRAddr = 13'h180; - 36'h0_1000_0000: CSRAddr = 13'h140; - 36'h0_2000_0000: CSRAddr = 13'h143; - 36'h0_4000_0000: CSRAddr = 13'h142; - 36'h0_8000_0000: CSRAddr = 13'h144; - 36'h1_0000_0000: CSRAddr = 13'h14D; - 36'h2_0000_0000: CSRAddr = 13'h001; - 36'h4_0000_0000: CSRAddr = 13'h002; - 36'h8_0000_0000: CSRAddr = 13'h003; - default : CSRAddr = 13'h000; - endcase - end -endmodule - From 825dbefcb24f0831c418b0fb5e124e123f5a1f00 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 23 Jul 2024 12:26:03 -0500 Subject: [PATCH 107/219] Fixed bus width error. Have to check this FPGA to make sure this didn't break anything. --- src/rvvi/packetizer.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/rvvi/packetizer.sv b/src/rvvi/packetizer.sv index 97c57415e..54dc9a27f 100644 --- a/src/rvvi/packetizer.sv +++ b/src/rvvi/packetizer.sv @@ -42,7 +42,7 @@ module packetizer import cvw::*; #(parameter cvw_t P, input logic RvviAxiWready ); - localparam TotalFrameLengthBits = 2*48+32+16+187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12); + localparam TotalFrameLengthBits = 2*48+17+16+187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12); localparam TotalFrameLengthBytes = TotalFrameLengthBits / 8; logic [9:0] WordCount; @@ -121,7 +121,7 @@ module packetizer import cvw::*; #(parameter cvw_t P, end assign Length = {4'b0, BytesInFrame}; - assign TotalFrame = {16'b0, rvviDelay, EthType, DstMac, SrcMac}; + assign TotalFrame = {17'b0, rvviDelay, EthType, DstMac, SrcMac}; // *** fix me later assign DstMac = 48'h8F54_0000_1654; // made something up From c463201d6837a2bb33afaabe9c23eb977bd65cc6 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 23 Jul 2024 13:03:21 -0500 Subject: [PATCH 108/219] Moved all rvvi files to rvvi directory. --- src/{wally => rvvi}/regchangedetect.sv | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename src/{wally => rvvi}/regchangedetect.sv (100%) diff --git a/src/wally/regchangedetect.sv b/src/rvvi/regchangedetect.sv similarity index 100% rename from src/wally/regchangedetect.sv rename to src/rvvi/regchangedetect.sv From 1eff86b7ae342557494011a81e69ea909bf90f03 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 23 Jul 2024 13:18:03 -0500 Subject: [PATCH 109/219] Down to 3 verilator warnings in rvvisynth and a 40 warnings in verilog-ethernet. --- src/{wally => rvvi}/priorityaomux.sv | 0 src/rvvi/rvvisynth.sv | 9 ++++++--- 2 files changed, 6 insertions(+), 3 deletions(-) rename src/{wally => rvvi}/priorityaomux.sv (100%) diff --git a/src/wally/priorityaomux.sv b/src/rvvi/priorityaomux.sv similarity index 100% rename from src/wally/priorityaomux.sv rename to src/rvvi/priorityaomux.sv diff --git a/src/rvvi/rvvisynth.sv b/src/rvvi/rvvisynth.sv index 5ee8b8c52..a98160d47 100644 --- a/src/rvvi/rvvisynth.sv +++ b/src/rvvi/rvvisynth.sv @@ -30,7 +30,8 @@ `define FPGA 0 module rvvisynth import cvw::*; #(parameter cvw_t P, - parameter integer MAX_CSRS, TOTAL_CSRS = 36)( + parameter integer MAX_CSRS = 3, + parameter integer TOTAL_CSRS = 36)( input logic clk, reset, input logic StallE, StallM, StallW, FlushE, FlushM, FlushW, // required @@ -64,6 +65,7 @@ module rvvisynth import cvw::*; #(parameter cvw_t P, logic [TOTAL_CSRS-1:0] CSRWen [MAX_CSRS-1:0]; logic [11:0] CSRAddr [MAX_CSRS-1:0]; logic [MAX_CSRS-1:0] EnabledCSRs; + logic [MAX_CSRS-1:0] CSRCountShort; logic [11:0] CSRCount; logic [177+P.XLEN-1:0] Required; logic [10+2*P.XLEN-1:0] Registers; @@ -94,7 +96,7 @@ module rvvisynth import cvw::*; #(parameter cvw_t P, // 3. Then use priorityaomux to collect CSR values and addresses for compating into the compressed rvvi format // step 2 - genvar index; + genvar index; for (index = 0; index < TOTAL_CSRS; index = index + 1) begin regchangedetect #(P.XLEN) changedetect(clk, reset, CSRArray[index], CSRArrayWen[index]); end @@ -109,7 +111,8 @@ module rvvisynth import cvw::*; #(parameter cvw_t P, assign CSRs[(index+1) * (P.XLEN + 12)- 1: index * (P.XLEN + 12)] = {CSRValue[index], CSRAddr[index]}; assign EnabledCSRs[index] = |CSRWenShort; end - assign CSRCount = +EnabledCSRs; + assign CSRCountShort = +EnabledCSRs; + assign CSRCount = {{{12-MAX_CSRS}{1'b0}}, CSRCountShort}; assign rvvi = {CSRs, Registers, Required}; endmodule From bf65cd2817b7a49a1dfb0bf16b2362f253da4fd9 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Tue, 23 Jul 2024 14:18:42 -0500 Subject: [PATCH 110/219] Added uart print functions and the Wally banner. SD card can now be initialized. Removed old code from boot.c --- fpga/zsbl/boot.c | 441 ++++------------------------------------------- fpga/zsbl/boot.h | 10 ++ fpga/zsbl/sd.c | 76 ++++++-- fpga/zsbl/sd.h | 10 ++ fpga/zsbl/uart.c | 96 +++++++++++ fpga/zsbl/uart.h | 26 +++ 6 files changed, 239 insertions(+), 420 deletions(-) create mode 100644 fpga/zsbl/uart.c create mode 100644 fpga/zsbl/uart.h diff --git a/fpga/zsbl/boot.c b/fpga/zsbl/boot.c index 6e4780f55..484bddaac 100644 --- a/fpga/zsbl/boot.c +++ b/fpga/zsbl/boot.c @@ -2,421 +2,54 @@ #include "boot.h" #include "gpt.h" -/* Card type flags (card_type) */ -#define CT_MMC 0x01 /* MMC ver 3 */ -#define CT_SD1 0x02 /* SD ver 1 */ -#define CT_SD2 0x04 /* SD ver 2 */ -#define CT_SDC (CT_SD1|CT_SD2) /* SD */ -#define CT_BLOCK 0x08 /* Block addressing */ +/* int disk_read(BYTE * buf, LBA_t sector, UINT count, BYTE card_type) { */ -#define CMD0 (0) /* GO_IDLE_STATE */ -#define CMD1 (1) /* SEND_OP_COND */ -#define CMD2 (2) /* SEND_CID */ -#define CMD3 (3) /* RELATIVE_ADDR */ -#define CMD4 (4) -#define CMD5 (5) /* SLEEP_WAKE (SDC) */ -#define CMD6 (6) /* SWITCH_FUNC */ -#define CMD7 (7) /* SELECT */ -#define CMD8 (8) /* SEND_IF_COND */ -#define CMD9 (9) /* SEND_CSD */ -#define CMD10 (10) /* SEND_CID */ -#define CMD11 (11) -#define CMD12 (12) /* STOP_TRANSMISSION */ -#define CMD13 (13) -#define CMD15 (15) -#define CMD16 (16) /* SET_BLOCKLEN */ -#define CMD17 (17) /* READ_SINGLE_BLOCK */ -#define CMD18 (18) /* READ_MULTIPLE_BLOCK */ -#define CMD19 (19) -#define CMD20 (20) -#define CMD23 (23) -#define CMD24 (24) -#define CMD25 (25) -#define CMD27 (27) -#define CMD28 (28) -#define CMD29 (29) -#define CMD30 (30) -#define CMD32 (32) -#define CMD33 (33) -#define CMD38 (38) -#define CMD42 (42) -#define CMD55 (55) /* APP_CMD */ -#define CMD56 (56) -#define ACMD6 (0x80+6) /* define the data bus width */ -#define ACMD41 (0x80+41) /* SEND_OP_COND (ACMD) */ +/* /\* This is not needed. This has everything to do with the FAT */ +/* filesystem stuff that I'm not including. All I need to do is */ +/* initialize the SD card and read from it. Anything in here that is */ +/* checking for potential errors, I'm going to have to temporarily */ +/* do without. */ +/* *\/ */ +/* // if (!count) return RES_PARERR; */ +/* /\* if (drv_status & STA_NOINIT) return RES_NOTRDY; *\/ */ -// Capability bits -#define SDC_CAPABILITY_SD_4BIT 0x0001 -#define SDC_CAPABILITY_SD_RESET 0x0002 -#define SDC_CAPABILITY_ADDR 0xff00 - -// Control bits -#define SDC_CONTROL_SD_4BIT 0x0001 -#define SDC_CONTROL_SD_RESET 0x0002 - -// Card detect bits -#define SDC_CARD_INSERT_INT_EN 0x0001 -#define SDC_CARD_INSERT_INT_REQ 0x0002 -#define SDC_CARD_REMOVE_INT_EN 0x0004 -#define SDC_CARD_REMOVE_INT_REQ 0x0008 - -// Command status bits -#define SDC_CMD_INT_STATUS_CC 0x0001 // Command complete -#define SDC_CMD_INT_STATUS_EI 0x0002 // Any error -#define SDC_CMD_INT_STATUS_CTE 0x0004 // Timeout -#define SDC_CMD_INT_STATUS_CCRC 0x0008 // CRC error -#define SDC_CMD_INT_STATUS_CIE 0x0010 // Command code check error - -// Data status bits -#define SDC_DAT_INT_STATUS_TRS 0x0001 // Transfer complete -#define SDC_DAT_INT_STATUS_ERR 0x0002 // Any error -#define SDC_DAT_INT_STATUS_CTE 0x0004 // Timeout -#define SDC_DAT_INT_STATUS_CRC 0x0008 // CRC error -#define SDC_DAT_INT_STATUS_CFE 0x0010 // Data FIFO underrun or overrun - - -#define ERR_EOF 30 -#define ERR_NOT_ELF 31 -#define ERR_ELF_BITS 32 -#define ERR_ELF_ENDIANNESS 33 -#define ERR_CMD_CRC 34 -#define ERR_CMD_CHECK 35 -#define ERR_DATA_CRC 36 -#define ERR_DATA_FIFO 37 -#define ERR_BUF_ALIGNMENT 38 -#define FR_DISK_ERR 39 -#define FR_TIMEOUT 40 - -struct sdc_regs { - volatile uint32_t argument; - volatile uint32_t command; - volatile uint32_t response1; - volatile uint32_t response2; - volatile uint32_t response3; - volatile uint32_t response4; - volatile uint32_t data_timeout; - volatile uint32_t control; - volatile uint32_t cmd_timeout; - volatile uint32_t clock_divider; - volatile uint32_t software_reset; - volatile uint32_t power_control; - volatile uint32_t capability; - volatile uint32_t cmd_int_status; - volatile uint32_t cmd_int_enable; - volatile uint32_t dat_int_status; - volatile uint32_t dat_int_enable; - volatile uint32_t block_size; - volatile uint32_t block_count; - volatile uint32_t card_detect; - volatile uint32_t res_50; - volatile uint32_t res_54; - volatile uint32_t res_58; - volatile uint32_t res_5c; - volatile uint64_t dma_addres; -}; - -#define MAX_BLOCK_CNT 0x1000 - -#define SDC 0x00013000; - -// static struct sdc_regs * const regs __attribute__((section(".rodata"))) = (struct sdc_regs *)0x00013000; - -// static int errno __attribute__((section(".bss"))); -// static DSTATUS drv_status __attribute__((section(".bss"))); -// static BYTE card_type __attribute__((section(".bss"))); -// static uint32_t response[4] __attribute__((section(".bss"))); -// static int alt_mem __attribute__((section(".bss"))); - -/*static const char * errno_to_str(void) { - switch (errno) { - case ERR_EOF: return "Unexpected EOF"; - case ERR_NOT_ELF: return "Not an ELF file"; - case ERR_ELF_BITS: return "Wrong ELF word size"; - case ERR_ELF_ENDIANNESS: return "Wrong ELF endianness"; - case ERR_CMD_CRC: return "Command CRC error"; - case ERR_CMD_CHECK: return "Command code check error"; - case ERR_DATA_CRC: return "Data CRC error"; - case ERR_DATA_FIFO: return "Data FIFO error"; - case ERR_BUF_ALIGNMENT: return "Bad buffer alignment"; - case FR_DISK_ERR: return "Disk error"; - case FR_TIMEOUT: return "Timeout"; - } - return "Unknown error code"; - }*/ - -static void usleep(unsigned us) { - uintptr_t cycles0; - uintptr_t cycles1; - asm volatile ("csrr %0, 0xB00" : "=r" (cycles0)); - for (;;) { - asm volatile ("csrr %0, 0xB00" : "=r" (cycles1)); - if (cycles1 - cycles0 >= us * 100) break; - } -} - -static int sdc_cmd_finish(unsigned cmd, uint32_t * response) { - struct sdc_regs * regs = (struct sdc_regs *)SDC; +/* uint32_t response[4]; */ +/* struct sdc_regs * regs = (struct sdc_regs *)SDC; */ - while (1) { - unsigned status = regs->cmd_int_status; - if (status) { - // clear interrupts - regs->cmd_int_status = 0; - while (regs->software_reset != 0) {} - if (status == SDC_CMD_INT_STATUS_CC) { - // get response - response[0] = regs->response1; - response[1] = regs->response2; - response[2] = regs->response3; - response[3] = regs->response4; - return 0; - } - /* errno = FR_DISK_ERR; - if (status & SDC_CMD_INT_STATUS_CTE) errno = FR_TIMEOUT; - if (status & SDC_CMD_INT_STATUS_CCRC) errno = ERR_CMD_CRC; - if (status & SDC_CMD_INT_STATUS_CIE) errno = ERR_CMD_CHECK;*/ - break; - } - } - return -1; -} +/* /\* Convert LBA to byte address if needed *\/ */ +/* if (!(card_type & CT_BLOCK)) sector *= 512; */ +/* while (count > 0) { */ +/* UINT bcnt = count > MAX_BLOCK_CNT ? MAX_BLOCK_CNT : count; */ +/* unsigned bytes = bcnt * 512; */ +/* if (send_data_cmd(bcnt == 1 ? CMD17 : CMD18, sector, buf, bcnt, response) < 0) return 1; */ +/* if (bcnt > 1 && send_cmd(CMD12, 0, response) < 0) return 1; */ +/* sector += (card_type & CT_BLOCK) ? bcnt : bytes; */ +/* count -= bcnt; */ +/* buf += bytes; */ +/* } */ -static int sdc_data_finish(void) { - int status; - struct sdc_regs * regs = (struct sdc_regs *)SDC; - - while ((status = regs->dat_int_status) == 0) {} - regs->dat_int_status = 0; - while (regs->software_reset != 0) {} +/* return 0;; */ +/* } */ - if (status == SDC_DAT_INT_STATUS_TRS) return 0; - /* errno = FR_DISK_ERR; - if (status & SDC_DAT_INT_STATUS_CTE) errno = FR_TIMEOUT; - if (status & SDC_DAT_INT_STATUS_CRC) errno = ERR_DATA_CRC; - if (status & SDC_DAT_INT_STATUS_CFE) errno = ERR_DATA_FIFO;*/ - return -1; -} - -static int send_data_cmd(unsigned cmd, unsigned arg, void * buf, unsigned blocks, uint32_t * response) { - struct sdc_regs * regs = (struct sdc_regs *)SDC; +int disk_read(BYTE * buf, LBA_t sector, UINT count) { - unsigned command = (cmd & 0x3f) << 8; - switch (cmd) { - case CMD0: - case CMD4: - case CMD15: - // No responce - break; - case CMD11: - case CMD13: - case CMD16: - case CMD17: - case CMD18: - case CMD19: - case CMD23: - case CMD24: - case CMD25: - case CMD27: - case CMD30: - case CMD32: - case CMD33: - case CMD42: - case CMD55: - case CMD56: - case ACMD6: - // R1 - command |= 1; // 48 bits - command |= 1 << 3; // resp CRC - command |= 1 << 4; // resp OPCODE - break; - case CMD7: - case CMD12: - case CMD20: - case CMD28: - case CMD29: - case CMD38: - // R1b - command |= 1; // 48 bits - command |= 1 << 2; // busy - command |= 1 << 3; // resp CRC - command |= 1 << 4; // resp OPCODE - break; - case CMD2: - case CMD9: - case CMD10: - // R2 - command |= 2; // 136 bits - command |= 1 << 3; // resp CRC - break; - case ACMD41: - // R3 - command |= 1; // 48 bits - break; - case CMD3: - // R6 - command |= 1; // 48 bits - command |= 1 << 2; // busy - command |= 1 << 3; // resp CRC - command |= 1 << 4; // resp OPCODE - break; - case CMD8: - // R7 - command |= 1; // 48 bits - command |= 1 << 3; // resp CRC - command |= 1 << 4; // resp OPCODE - break; - } - - if (blocks) { - command |= 1 << 5; - if ((intptr_t)buf & 3) { - // errno = ERR_BUF_ALIGNMENT; - return -1; - } - regs->dma_addres = (uint64_t)(intptr_t)buf; - regs->block_size = 511; - regs->block_count = blocks - 1; - regs->data_timeout = 0x1FFFFFF; - } - - regs->command = command; - regs->cmd_timeout = 0xFFFFF; - regs->argument = arg; - - if (sdc_cmd_finish(cmd, response) < 0) return -1; - if (blocks) return sdc_data_finish(); - - return 0; -} - -#define send_cmd(cmd, arg, response) send_data_cmd(cmd, arg, NULL, 0, response) - -static BYTE ini_sd(void) { - struct sdc_regs * regs = (struct sdc_regs *)SDC; - unsigned rca; - BYTE card_type; - uint32_t response[4]; - - /* Reset controller */ - regs->software_reset = 1; - while ((regs->software_reset & 1) == 0) {} - - // This clock divider is meant to initialize the card at - // 400kHz - - // 22MHz/400kHz = 55 (base 10) = 0x37 - 0x01 = 0x36 - regs->clock_divider = 0x36; - regs->software_reset = 0; - while (regs->software_reset) {} - usleep(5000); - - card_type = 0; - // drv_status = STA_NOINIT; - - if (regs->capability & SDC_CAPABILITY_SD_RESET) { - /* Power cycle SD card */ - regs->control |= SDC_CONTROL_SD_RESET; - usleep(1000000); - regs->control &= ~SDC_CONTROL_SD_RESET; - usleep(100000); - } - - /* Enter Idle state */ - send_cmd(CMD0, 0, response); - - card_type = CT_SD1; - if (send_cmd(CMD8, 0x1AA, response) == 0) { - if ((response[0] & 0xfff) != 0x1AA) { - // errno = ERR_CMD_CHECK; - return -1; - } - card_type = CT_SD2; - } - - /* Wait for leaving idle state (ACMD41 with HCS bit) */ - while (1) { - /* ACMD41, Set Operating Conditions: Host High Capacity & 3.3V */ - if (send_cmd(CMD55, 0, response) < 0 || send_cmd(ACMD41, 0x40300000, response) < 0) return -1; - if (response[0] & (1 << 31)) { - if (response[0] & (1 << 30)) card_type |= CT_BLOCK; - break; - } - } - - /* Enter Identification state */ - if (send_cmd(CMD2, 0, response) < 0) return -1; - - /* Get RCA (Relative Card Address) */ - rca = 0x1234; - if (send_cmd(CMD3, rca << 16, response) < 0) return -1; - rca = response[0] >> 16; - - /* Select card */ - if (send_cmd(CMD7, rca << 16, response) < 0) return -1; - - /* Clock 25MHz */ - // 22Mhz/2 = 11Mhz - regs->clock_divider = 1; - usleep(10000); - - /* Bus width 1-bit */ - regs->control = 0; - if (send_cmd(CMD55, rca << 16, response) < 0 || send_cmd(ACMD6, 0, response) < 0) return -1; - - /* Set R/W block length to 512 */ - if (send_cmd(CMD16, 512, response) < 0) return -1; - - // drv_status &= ~STA_NOINIT; - return card_type; -} - -int disk_read(BYTE * buf, LBA_t sector, UINT count, BYTE card_type) { - - /* This is not needed. This has everything to do with the FAT - filesystem stuff that I'm not including. All I need to do is - initialize the SD card and read from it. Anything in here that is - checking for potential errors, I'm going to have to temporarily - do without. - */ - // if (!count) return RES_PARERR; - /* if (drv_status & STA_NOINIT) return RES_NOTRDY; */ - - uint32_t response[4]; - struct sdc_regs * regs = (struct sdc_regs *)SDC; - - /* Convert LBA to byte address if needed */ - if (!(card_type & CT_BLOCK)) sector *= 512; - while (count > 0) { - UINT bcnt = count > MAX_BLOCK_CNT ? MAX_BLOCK_CNT : count; - unsigned bytes = bcnt * 512; - if (send_data_cmd(bcnt == 1 ? CMD17 : CMD18, sector, buf, bcnt, response) < 0) return 1; - if (bcnt > 1 && send_cmd(CMD12, 0, response) < 0) return 1; - sector += (card_type & CT_BLOCK) ? bcnt : bytes; - count -= bcnt; - buf += bytes; - } - - return 0;; } +// copyFlash: -------------------------------------------------------- +// A lot happens in this function: +// * The Wally banner is printed +// * The peripherals are initialized void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) { - BYTE card_type; int ret = 0; - - card_type = ini_sd(); - // BYTE * buf = (BYTE *)Dst; - - // if (disk_read(buf, (LBA_t)address, (UINT)numBlocks, card_type) < 0) /* UART Print function?*/; + // Initialize UART for messages + init_uart(); + + // Print the wally banner + print_uart(BANNER); + + + init_sd(); ret = gpt_load_partitions(card_type); } - -/* -int main() { - ini_sd(); - - - return 0; -} -*/ diff --git a/fpga/zsbl/boot.h b/fpga/zsbl/boot.h index 77d403145..cb0f4e7f3 100644 --- a/fpga/zsbl/boot.h +++ b/fpga/zsbl/boot.h @@ -19,6 +19,16 @@ typedef QWORD LBA_t; #define OPENSBI_ADDRESS 0x80000000 // FW_TEXT_START #define KERNEL_ADDRESS 0x80200000 // FW_JUMP_ADDR +#define BANNER " █▀█ █▀█ █▀█ █▀▀ █ █\n" \ +" █ █ █ █▄▀ █▄▄ ▄▄▄ █ █\n" \ +" █▄█ █▄█ █ █ █▄▄ ▀▄▀\n" \ +" ____ ____ ____ ___ ___ ____ ___\n" \ +" \\ \\ / / / \\ | | | | \\ \\ / /\n" \ +" \\ \\ __ / / / \\ | | | | \\ \\/ /\n" \ +" \\ \\/ \\/ / / /\\ \\ | | | | \\ /\n" \ +" \\ / / ____ \\ | |___ | |___ | |\n" \ +" \\___/\\___/ /___/ \\___\\|_______||_______| |___|\n\n" + // Export disk_read int disk_read(BYTE * buf, LBA_t sector, UINT count, BYTE card_type); diff --git a/fpga/zsbl/sd.c b/fpga/zsbl/sd.c index aacea0db9..4669aeb0b 100644 --- a/fpga/zsbl/sd.c +++ b/fpga/zsbl/sd.c @@ -1,5 +1,6 @@ #include "sd.h" #include "spi.h" +#include "uart.h" // Parallel byte update CRC7-CCITT algorithm. // The result is the CRC7 result, left shifted over by 1 @@ -23,27 +24,44 @@ uint16_t crc16(uint16_t crc, uint8_t data) { return crc; } +// sd_cmd ------------------------------------------------------------ +// Sends SD card command using SPI mode. +// This function: +// * Chooses the response length based on the input command +// * Makes use of SPI's full duplex. For every byte sent, +// a byte is received. Thus for every byte sent as part of +// a command, a useless byte must be read from the receive +// FIFO. +// * Takes advantage of the Sifive SPI peripheral spec's +// watermark and interrupt features to determine when a +// transfer is complete. This should save on cycles since +// no arbitrary delays need to be added. uint64_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc) { uint8_t response_len; uint8_t i; uint64_t r; uint8_t rbyte; - + + // Initialize the response with 0's. + r = 0; + + // Choose response length based on cmd input. + // Most commands return an R1 format response. switch (cmd) { - case 0: - response_len = 1; - break; case 8: - response_len = 7 + response_len = R7_RESPONSE; break; + case 12: + response_len = R1B_RESPONSE; default: - response_len = 1; + response_len = R1_RESPONSE; break; } // Make interrupt pending after response fifo receives the correct - // response length. - write_reg(SPI_RXMARK, response_len); + // response length. Probably unecessary so let's wait and see what + // happens. + // write_reg(SPI_RXMARK, response_len); // Write all 6 bytes into transfer fifo spi_sendbyte(0x40 | cmd); @@ -79,18 +97,44 @@ uint64_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc) { } return r; -} +} // sd_cmd -#define cmd0() sd_cmd( 0, 0x00000000, 0x95) -#define cmd8() sd_cmd( 8, 0x000001aa, 0x87) -// CMD55 has to be sent before ACMD41 (it means the next command is -// application specific) -#define cmd55() sd_cmd(55, 0x00000000, 0x65) -#defube acmd41() sd_cmd(41, 0x40000000, 0x77) +// Utility defines for CMD0, CMD8, CMD55, and ACMD41 +#define CMD0() sd_cmd( 0, 0x00000000, 0x95) // Reset SD card into IDLE state +#define CMD8() sd_cmd( 8, 0x000001aa, 0x87) // +#define CMD55() sd_cmd(55, 0x00000000, 0x65) // +#define ACMD41() sd_cmd(41, 0x40000000, 0x77) // +// init_sd: ---------------------------------------------------------- +// This first initializes the SPI peripheral then initializes the SD +// card itself. We use the uart to display anything that goes wrong. void init_sd(){ init_spi(); - cmd0() + uint64_t r; + + print_uart("Initializing SD Card in SPI mode"); + + // Reset SD Card command + // Initializes SD card into SPI mode if CS is asserted '0' + if (!(( r = CMD0() ) & 0x10) ) { + print_uart("SD ERROR: "); + print_uart_byte(r & 0xff); + print_uart("\r\n"); + } + + // + if (!(( r = CMD8() ) & 0x10 )) { + print_uart("SD ERROR: "); + print_uart_byte(r & 0xff); + print_uart("\r\n"); + } + + do { + CMD55(); + r = ACMD41(); + } while (r == 0x1); + + print_uart("SD card is initialized"); } diff --git a/fpga/zsbl/sd.h b/fpga/zsbl/sd.h index f08941364..a70d203e7 100644 --- a/fpga/zsbl/sd.h +++ b/fpga/zsbl/sd.h @@ -2,6 +2,16 @@ #include +// Command names +#define SD_CMD_STOP_TRANSMISSION 12 +#define SD_CMD_READ_BLOCK_MULTIPLE 18 +#define SD_DATA_TOKEN 0xfe + +// Response lengths in bytes +#define R1_RESPONSE 1 +#define R7_RESPONSE 7 +#define R1B_RESPONSE 2 + uint8_t crc7(uint8_t prev, uint8_t in); uint16_t crc16(uint16_t crc, uint8_t data); uint64_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc); diff --git a/fpga/zsbl/uart.c b/fpga/zsbl/uart.c new file mode 100644 index 000000000..a08690069 --- /dev/null +++ b/fpga/zsbl/uart.c @@ -0,0 +1,96 @@ +#include "uart.h" + + +void write_reg_u8(uintptr_t addr, uint8_t value) +{ + volatile uint8_t *loc_addr = (volatile uint8_t *)addr; + *loc_addr = value; +} + +uint8_t read_reg_u8(uintptr_t addr) +{ + return *(volatile uint8_t *)addr; +} + +int is_transmit_empty() +{ + return read_reg_u8(UART_LINE_STATUS) & 0x20; +} + +int is_receive_empty() +{ + return !(read_reg_u8(UART_LINE_STATUS) & 0x1); +} + +void write_serial(char a) +{ + while (is_transmit_empty() == 0) {}; + + write_reg_u8(UART_THR, a); +} + +void init_uart(uint32_t freq, uint32_t baud) +{ + uint32_t divisor = freq / (baud << 4); + + write_reg_u8(UART_IER, 0x00); // Disable all interrupts + write_reg_u8(UART_LCR, 0x80); // Enable DLAB (set baud rate divisor) + write_reg_u8(UART_DLL, divisor); // divisor (lo byte) + write_reg_u8(UART_DLM, (divisor >> 8) & 0xFF); // divisor (hi byte) + write_reg_u8(UART_LCR, 0x03); // 8 bits, no parity, one stop bit + write_reg_u8(UART_FCR, 0xC7); // Enable FIFO, clear them, with 14-byte threshold +} + +void print_uart(const char *str) +{ + const char *cur = &str[0]; + while (*cur != '\0') + { + write_serial((uint8_t)*cur); + ++cur; + } +} + +uint8_t bin_to_hex_table[16] = { + '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F'}; + +void bin_to_hex(uint8_t inp, uint8_t res[2]) +{ + res[1] = bin_to_hex_table[inp & 0xf]; + res[0] = bin_to_hex_table[(inp >> 4) & 0xf]; + return; +} + +void print_uart_int(uint32_t addr) +{ + int i; + for (i = 3; i > -1; i--) + { + uint8_t cur = (addr >> (i * 8)) & 0xff; + uint8_t hex[2]; + bin_to_hex(cur, hex); + write_serial(hex[0]); + write_serial(hex[1]); + } +} + +void print_uart_addr(uint64_t addr) +{ + int i; + for (i = 7; i > -1; i--) + { + uint8_t cur = (addr >> (i * 8)) & 0xff; + uint8_t hex[2]; + bin_to_hex(cur, hex); + write_serial(hex[0]); + write_serial(hex[1]); + } +} + +void print_uart_byte(uint8_t byte) +{ + uint8_t hex[2]; + bin_to_hex(byte, hex); + write_serial(hex[0]); + write_serial(hex[1]); +} diff --git a/fpga/zsbl/uart.h b/fpga/zsbl/uart.h new file mode 100644 index 000000000..18710e76b --- /dev/null +++ b/fpga/zsbl/uart.h @@ -0,0 +1,26 @@ +#pragma once +#include + +#define UART_BASE 0x10000000 + +#define UART_RBR UART_BASE + 0x00 +#define UART_THR UART_BASE + 0x00 +#define UART_IER UART_BASE + 0x01 +#define UART_IIR UART_BASE + 0x02 +#define UART_FCR UART_BASE + 0x02 +#define UART_LCR UART_BASE + 0x03 +#define UART_MCR UART_BASE + 0x04 +#define UART_LSR UART_BASE + 0x05 +#define UART_MSR UART_BASE + 0x06 +#define UART_SCR UART_BASE + 0x07 +#define UART_DLL UART_BASE + 0x00 +#define UART_DLM UART_BASE + 0x01 + +void init_uart(); +void write_reg_u8(uintptr_t addr, uint8_t value); +uint8_t read_reg_u8(uintptr_t addr); +int read_serial(uint8_t *res); +void print_uart(const char* str); +void print_uart_int(uint32_t addr); +void print_uart_addr(uint64_t addr); +void print_uart_byte(uint8_t byte); From 9ccb0eb027679351e81d9cf41d0cfd494fe05e24 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Tue, 23 Jul 2024 15:46:18 -0500 Subject: [PATCH 111/219] Removed references to card_type. --- fpga/zsbl/gpt.c | 12 ++++++------ fpga/zsbl/gpt.h | 2 +- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/fpga/zsbl/gpt.c b/fpga/zsbl/gpt.c index 97e3e4e46..65f56924b 100644 --- a/fpga/zsbl/gpt.c +++ b/fpga/zsbl/gpt.c @@ -10,7 +10,7 @@ */ -int gpt_load_partitions(BYTE card_type) { +int gpt_load_partitions() { // In this version of the GPT partition code // I'm going to assume that the SD card is already initialized. @@ -21,7 +21,7 @@ int gpt_load_partitions(BYTE card_type) { int ret = 0; //ret = disk_read(/* BYTE * buf, LBA_t sector, UINT count, BYTE card_type */); - ret = disk_read(lba1_buf, 1, 1, card_type); + ret = disk_read(lba1_buf, 1, 1); /* Possible error handling with UART message if ( ret != 0 ) { @@ -31,16 +31,16 @@ int gpt_load_partitions(BYTE card_type) { gpt_pth_t *lba1 = (gpt_pth_t *)lba1_buf; BYTE lba2_buf[512]; - ret = disk_read(lba2_buf, (LBA_t)lba1->partition_entries_lba, 1, card_type); + ret = disk_read(lba2_buf, (LBA_t)lba1->partition_entries_lba, 1); // Load parition entries for the relevant boot partitions. partition_entries_t *fdt = (partition_entries_t *)(lba2_buf); partition_entries_t *opensbi = (partition_entries_t *)(lba2_buf + 128); partition_entries_t *kernel = (partition_entries_t *)(lba2_buf + 256); - ret = disk_read((BYTE *)FDT_ADDRESS, fdt->first_lba, fdt->last_lba - fdt->first_lba + 1, card_type); - ret = disk_read((BYTE *)OPENSBI_ADDRESS, opensbi->first_lba, opensbi->last_lba - opensbi->first_lba + 1, card_type); - ret = disk_read((BYTE *)KERNEL_ADDRESS, kernel->first_lba,kernel->last_lba - kernel->first_lba + 1, card_type); + ret = disk_read((BYTE *)FDT_ADDRESS, fdt->first_lba, fdt->last_lba - fdt->first_lba + 1); + ret = disk_read((BYTE *)OPENSBI_ADDRESS, opensbi->first_lba, opensbi->last_lba - opensbi->first_lba + 1); + ret = disk_read((BYTE *)KERNEL_ADDRESS, kernel->first_lba,kernel->last_lba - kernel->first_lba + 1); return 0; } diff --git a/fpga/zsbl/gpt.h b/fpga/zsbl/gpt.h index 4aefae229..5ce5e1d4b 100644 --- a/fpga/zsbl/gpt.h +++ b/fpga/zsbl/gpt.h @@ -37,4 +37,4 @@ typedef struct partition_entries } partition_entries_t; // Find boot partition and load it to the destination -int gpt_load_partitions(BYTE card_type); +int gpt_load_partitions(); From 57eeba5c8ca7efa6f202ab915259b2c8ddb7720e Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Tue, 23 Jul 2024 15:47:23 -0500 Subject: [PATCH 112/219] Progress made on implementing new disk read function. --- fpga/zsbl/boot.c | 25 ++++++++++++++++++++++++- fpga/zsbl/sd.c | 1 + fpga/zsbl/spi.c | 18 ++++++++++++++++++ fpga/zsbl/spi.h | 2 +- 4 files changed, 44 insertions(+), 2 deletions(-) diff --git a/fpga/zsbl/boot.c b/fpga/zsbl/boot.c index 484bddaac..16f7c0430 100644 --- a/fpga/zsbl/boot.c +++ b/fpga/zsbl/boot.c @@ -1,6 +1,9 @@ #include #include "boot.h" #include "gpt.h" +#include "uart.h" +#include "spi.h" +#include "sd.h" /* int disk_read(BYTE * buf, LBA_t sector, UINT count, BYTE card_type) { */ @@ -32,7 +35,27 @@ /* } */ int disk_read(BYTE * buf, LBA_t sector, UINT count) { + uint64_t r; + UINT i; + uint8_t crc = 0; + crc = crc7(crc, 0x40 | SD_CMD_READ_BLOCK_MULTIPLE); + crc = crc7(crc, (sector >> 24) & 0xff); + crc = crc7(crc, (sector >> 16) & 0xff); + crc = crc7(crc, (sector >> 8) & 0xff); + crc = crc7(crc, sector & 0xff); + crc = crc | 1; + + if (sd_cmd(18, sector &, crc) != 0x00) { + print_uart("disk_read: CMD18 failed. r = "); + print_byte(r & 0xff); + return -1; + } + + // Begin reading + for (i = 0; i < count; i++) { + + } } // copyFlash: -------------------------------------------------------- @@ -48,7 +71,7 @@ void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) { // Print the wally banner print_uart(BANNER); - + // Intialize the SD card init_sd(); ret = gpt_load_partitions(card_type); diff --git a/fpga/zsbl/sd.c b/fpga/zsbl/sd.c index 4669aeb0b..c2a6eed54 100644 --- a/fpga/zsbl/sd.c +++ b/fpga/zsbl/sd.c @@ -99,6 +99,7 @@ uint64_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc) { return r; } // sd_cmd + // Utility defines for CMD0, CMD8, CMD55, and ACMD41 #define CMD0() sd_cmd( 0, 0x00000000, 0x95) // Reset SD card into IDLE state #define CMD8() sd_cmd( 8, 0x000001aa, 0x87) // diff --git a/fpga/zsbl/spi.c b/fpga/zsbl/spi.c index c812327f4..687a98ceb 100644 --- a/fpga/zsbl/spi.c +++ b/fpga/zsbl/spi.c @@ -58,6 +58,24 @@ inline void waitrx() { while(read_reg(SPI_IP) & 2)) {} } +uint64_t spi_read64() { + uint64_t r; + uint8_t rbyte; + int i; + + for (i = 0; i < 8; i++) { + spi_sendbyte(0xFF); + } + + waittx(); + + for (i = 0; i < 8; i++) { + rbyte = spi_readbyte(); + r = r | (rbyte << ((8 - 1 - i)*8)); + } + + return r; +} // Initialize Sifive FU540 based SPI Controller void spi_init() { diff --git a/fpga/zsbl/spi.h b/fpga/zsbl/spi.h index a035f0ab5..e91bcc0ea 100644 --- a/fpga/zsbl/spi.h +++ b/fpga/zsbl/spi.h @@ -55,7 +55,7 @@ inline void waittx(); inline void waitrx(); uint8_t spi_txrx(uint8_t byte); inline uint8_t spi_readbyte(); - +uint64_t spi_read64(); void spi_init(); #endif From 54e02896088bb6303830e2330a2775c75a33d99c Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 23 Jul 2024 16:16:11 -0500 Subject: [PATCH 113/219] Fixed bugs in the rvvi synth logic which encoded csr instructions. --- src/rvvi/rvvisynth.sv | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/src/rvvi/rvvisynth.sv b/src/rvvi/rvvisynth.sv index a98160d47..d4847c9d4 100644 --- a/src/rvvi/rvvisynth.sv +++ b/src/rvvi/rvvisynth.sv @@ -102,14 +102,26 @@ module rvvisynth import cvw::*; #(parameter cvw_t P, end // step 3a - for(index = 0; index < MAX_CSRS; index = index + 1) begin + logic [TOTAL_CSRS-1:0] CSRWenPriorityMatrix [MAX_CSRS-1:0]; + logic [TOTAL_CSRS-1:0] CSRWenFilterMatrix [MAX_CSRS-1:0]; + + priorityaomux #(TOTAL_CSRS, P.XLEN) firstpriorityaomux(CSRArrayWen, CSRArray, CSRValue[0], CSRWenPriorityMatrix[0]); + assign CSRWenFilterMatrix[0] = CSRArrayWen; + + for(index = 1; index < MAX_CSRS; index = index + 1) begin +/* -----\/----- EXCLUDED -----\/----- logic [MAX_CSRS-index-1:0] CSRWenShort; priorityaomux #(MAX_CSRS-index, P.XLEN) priorityaomux(CSRArrayWen[MAX_CSRS-1:index], CSRArray[MAX_CSRS-1:index], CSRValue[index], CSRWenShort); assign CSRWen[index] = {{{index}{1'b0}}, CSRWenShort}; + -----/\----- EXCLUDED -----/\----- */ + priorityaomux #(TOTAL_CSRS, P.XLEN) priorityaomux(CSRWenFilterMatrix[index], CSRArray, CSRValue[index], CSRWenPriorityMatrix[index]); + assign CSRWenFilterMatrix[index] = CSRWenFilterMatrix[index-1] & ~CSRWenPriorityMatrix[index-1]; + end + for(index = 0; index < MAX_CSRS; index = index + 1) begin // step 3b - csrindextoaddr #(TOTAL_CSRS) csrindextoaddr(CSRWen[index], CSRAddr[index]); + csrindextoaddr #(TOTAL_CSRS) csrindextoaddr(CSRWenPriorityMatrix[index], CSRAddr[index]); assign CSRs[(index+1) * (P.XLEN + 12)- 1: index * (P.XLEN + 12)] = {CSRValue[index], CSRAddr[index]}; - assign EnabledCSRs[index] = |CSRWenShort; + assign EnabledCSRs[index] = |CSRWenPriorityMatrix[index]; end assign CSRCountShort = +EnabledCSRs; assign CSRCount = {{{12-MAX_CSRS}{1'b0}}, CSRCountShort}; From 57ea39d6857b5227c19bb46f51a0d64fead0ea9f Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 23 Jul 2024 16:22:23 -0500 Subject: [PATCH 114/219] Fixed rvvi csr counting. --- src/rvvi/rvvisynth.sv | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/rvvi/rvvisynth.sv b/src/rvvi/rvvisynth.sv index d4847c9d4..7bdc05d10 100644 --- a/src/rvvi/rvvisynth.sv +++ b/src/rvvi/rvvisynth.sv @@ -123,7 +123,15 @@ module rvvisynth import cvw::*; #(parameter cvw_t P, assign CSRs[(index+1) * (P.XLEN + 12)- 1: index * (P.XLEN + 12)] = {CSRValue[index], CSRAddr[index]}; assign EnabledCSRs[index] = |CSRWenPriorityMatrix[index]; end - assign CSRCountShort = +EnabledCSRs; + + integer index2; + always_comb begin + CSRCountShort = '0; + for(index2 = 0; index2 < MAX_CSRS; index2++) begin + CSRCountShort += EnabledCSRs[index2]; + end + end + assign CSRCount = {{{12-MAX_CSRS}{1'b0}}, CSRCountShort}; assign rvvi = {CSRs, Registers, Required}; From ab00ea5a5cffd862d855e067d57fb4ab3928bb68 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Tue, 23 Jul 2024 16:32:29 -0500 Subject: [PATCH 115/219] Added sd_read64 to help with block reads and crc checking. --- fpga/zsbl/sd.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/fpga/zsbl/sd.c b/fpga/zsbl/sd.c index c2a6eed54..87e78e7fe 100644 --- a/fpga/zsbl/sd.c +++ b/fpga/zsbl/sd.c @@ -99,6 +99,25 @@ uint64_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc) { return r; } // sd_cmd +uint64_t sd_read64(uint16_t * crc) { + uint64_t r; + uint8_t rbyte; + int i; + + for (i = 0; i < 8; i++) { + spi_sendbyte(0xFF); + } + + waittx(); + + for (i = 0; i < 8; i++) { + rbyte = spi_readbyte(); + *crc = crc16(*crc, rbyte); + r = r | (rbyte << ((8 - 1 - i)*8)); + } + + return r; +} // Utility defines for CMD0, CMD8, CMD55, and ACMD41 #define CMD0() sd_cmd( 0, 0x00000000, 0x95) // Reset SD card into IDLE state From a8b9e7776b4d2fd029f0a2b6f75566ce45d2d81d Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Tue, 23 Jul 2024 16:32:52 -0500 Subject: [PATCH 116/219] Added some minor error checking to gpt.c. --- fpga/zsbl/gpt.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/fpga/zsbl/gpt.c b/fpga/zsbl/gpt.c index 65f56924b..90948935b 100644 --- a/fpga/zsbl/gpt.c +++ b/fpga/zsbl/gpt.c @@ -38,9 +38,26 @@ int gpt_load_partitions() { partition_entries_t *opensbi = (partition_entries_t *)(lba2_buf + 128); partition_entries_t *kernel = (partition_entries_t *)(lba2_buf + 256); + // Load device tree ret = disk_read((BYTE *)FDT_ADDRESS, fdt->first_lba, fdt->last_lba - fdt->first_lba + 1); + if (ret < 0) { + print_uart("Failed to load device tree!"); + return -1; + } + + // Load OpenSBI ret = disk_read((BYTE *)OPENSBI_ADDRESS, opensbi->first_lba, opensbi->last_lba - opensbi->first_lba + 1); + if (ret < 0) { + print_uart("Failed to load OpenSBI!"); + return -1; + } + + // Load Linux ret = disk_read((BYTE *)KERNEL_ADDRESS, kernel->first_lba,kernel->last_lba - kernel->first_lba + 1); + if (ret < 0) { + print_uart("Failed to load Linux!"); + return -1; + } return 0; } From 5f0addd69a25a0b1384ea6cd64f0419058f8f311 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Tue, 23 Jul 2024 16:33:49 -0500 Subject: [PATCH 117/219] Initial pass on SPI based bootloader code finished. --- fpga/zsbl/boot.c | 32 +++++++++++++++++++++++++++++++- fpga/zsbl/sd.h | 1 + fpga/zsbl/spi.c | 6 ++++++ 3 files changed, 38 insertions(+), 1 deletion(-) diff --git a/fpga/zsbl/boot.c b/fpga/zsbl/boot.c index 16f7c0430..96bde4205 100644 --- a/fpga/zsbl/boot.c +++ b/fpga/zsbl/boot.c @@ -52,10 +52,40 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) { return -1; } - // Begin reading + // Begin reading blocks for (i = 0; i < count; i++) { + uint16_t crc, crc_exp; + + // Read the data token + r = spi_readbyte(); + if (r != SD_DATA_TOKEN) { + print_uart("Didn't receive data token first thing. Shoot: "); + print_byte(r & 0xff); + return -1; + } + + // Read block into memory. + for (int j = 0; j < 8; j++) { + *buf = sd_read64(&crc); + buf = buf + 64; + } + + // Read CRC16 and check + crc_exp = ((uint16_t)spi_txrx(0xff) << 8); + crc_exp |= spi_txrx(0xff); + + if (crc != crc_exp) { + print_uart("Stinking CRC16 didn't match on block "); + print_int(i); + print_uart("\r\n"); + return -1; + } } + + sd_cmd(SD_CMD_STOP_TRANSMISSION, 0, 0x01); + spi_txrx(0xff); + return 0; } // copyFlash: -------------------------------------------------------- diff --git a/fpga/zsbl/sd.h b/fpga/zsbl/sd.h index a70d203e7..37e4a2c94 100644 --- a/fpga/zsbl/sd.h +++ b/fpga/zsbl/sd.h @@ -15,4 +15,5 @@ uint8_t crc7(uint8_t prev, uint8_t in); uint16_t crc16(uint16_t crc, uint8_t data); uint64_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc); +uint64_t sd_read64(uint16_t * crc); void init_sd(); diff --git a/fpga/zsbl/spi.c b/fpga/zsbl/spi.c index 687a98ceb..76985a350 100644 --- a/fpga/zsbl/spi.c +++ b/fpga/zsbl/spi.c @@ -58,6 +58,12 @@ inline void waitrx() { while(read_reg(SPI_IP) & 2)) {} } +uint8_t spi_txrx(uint8_t byte) { + spi_sendbyte(0xFF); + waittx(); + return spi_readbyte(); +} + uint64_t spi_read64() { uint64_t r; uint8_t rbyte; From e8e71ad643370f6401e6253cb31b1fdd639b57b4 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 23 Jul 2024 16:35:05 -0500 Subject: [PATCH 118/219] Code cleanup. --- src/rvvi/rvvisynth.sv | 7 ------- 1 file changed, 7 deletions(-) diff --git a/src/rvvi/rvvisynth.sv b/src/rvvi/rvvisynth.sv index 7bdc05d10..83c865529 100644 --- a/src/rvvi/rvvisynth.sv +++ b/src/rvvi/rvvisynth.sv @@ -27,8 +27,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`define FPGA 0 - module rvvisynth import cvw::*; #(parameter cvw_t P, parameter integer MAX_CSRS = 3, parameter integer TOTAL_CSRS = 36)( @@ -109,11 +107,6 @@ module rvvisynth import cvw::*; #(parameter cvw_t P, assign CSRWenFilterMatrix[0] = CSRArrayWen; for(index = 1; index < MAX_CSRS; index = index + 1) begin -/* -----\/----- EXCLUDED -----\/----- - logic [MAX_CSRS-index-1:0] CSRWenShort; - priorityaomux #(MAX_CSRS-index, P.XLEN) priorityaomux(CSRArrayWen[MAX_CSRS-1:index], CSRArray[MAX_CSRS-1:index], CSRValue[index], CSRWenShort); - assign CSRWen[index] = {{{index}{1'b0}}, CSRWenShort}; - -----/\----- EXCLUDED -----/\----- */ priorityaomux #(TOTAL_CSRS, P.XLEN) priorityaomux(CSRWenFilterMatrix[index], CSRArray, CSRValue[index], CSRWenPriorityMatrix[index]); assign CSRWenFilterMatrix[index] = CSRWenFilterMatrix[index-1] & ~CSRWenPriorityMatrix[index-1]; end From dcb2edf8888175f078d10b80c491a7df264bafac Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Tue, 23 Jul 2024 17:00:32 -0500 Subject: [PATCH 119/219] Fixed syntax bugs. inline functions are now static and in the spi.h header. --- fpga/zsbl/boot.c | 10 +++++----- fpga/zsbl/boot.h | 2 +- fpga/zsbl/sd.c | 2 +- fpga/zsbl/spi.c | 46 +++++++++++++++++++++++----------------------- fpga/zsbl/spi.h | 48 ++++++++++++++++++++++++++++++++++++++---------- fpga/zsbl/uart.c | 4 ++-- 6 files changed, 70 insertions(+), 42 deletions(-) diff --git a/fpga/zsbl/boot.c b/fpga/zsbl/boot.c index 96bde4205..786879c49 100644 --- a/fpga/zsbl/boot.c +++ b/fpga/zsbl/boot.c @@ -46,9 +46,9 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) { crc = crc7(crc, sector & 0xff); crc = crc | 1; - if (sd_cmd(18, sector &, crc) != 0x00) { + if (sd_cmd(18, sector & 0xffffffff, crc) != 0x00) { print_uart("disk_read: CMD18 failed. r = "); - print_byte(r & 0xff); + print_uart_byte(r & 0xff); return -1; } @@ -60,7 +60,7 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) { r = spi_readbyte(); if (r != SD_DATA_TOKEN) { print_uart("Didn't receive data token first thing. Shoot: "); - print_byte(r & 0xff); + print_uart_byte(r & 0xff); return -1; } @@ -76,7 +76,7 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) { if (crc != crc_exp) { print_uart("Stinking CRC16 didn't match on block "); - print_int(i); + print_uart_int(i); print_uart("\r\n"); return -1; } @@ -104,5 +104,5 @@ void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) { // Intialize the SD card init_sd(); - ret = gpt_load_partitions(card_type); + ret = gpt_load_partitions(); } diff --git a/fpga/zsbl/boot.h b/fpga/zsbl/boot.h index cb0f4e7f3..2048ca47c 100644 --- a/fpga/zsbl/boot.h +++ b/fpga/zsbl/boot.h @@ -30,7 +30,7 @@ typedef QWORD LBA_t; " \\___/\\___/ /___/ \\___\\|_______||_______| |___|\n\n" // Export disk_read -int disk_read(BYTE * buf, LBA_t sector, UINT count, BYTE card_type); +int disk_read(BYTE * buf, LBA_t sector, UINT count); #endif // WALLYBOOT diff --git a/fpga/zsbl/sd.c b/fpga/zsbl/sd.c index 87e78e7fe..585b98281 100644 --- a/fpga/zsbl/sd.c +++ b/fpga/zsbl/sd.c @@ -129,7 +129,7 @@ uint64_t sd_read64(uint16_t * crc) { // This first initializes the SPI peripheral then initializes the SD // card itself. We use the uart to display anything that goes wrong. void init_sd(){ - init_spi(); + spi_init(); uint64_t r; diff --git a/fpga/zsbl/spi.c b/fpga/zsbl/spi.c index 76985a350..cbb9fa2eb 100644 --- a/fpga/zsbl/spi.c +++ b/fpga/zsbl/spi.c @@ -30,33 +30,29 @@ #include "spi.h" // Write to a register -inline void write_reg(uintptr_t addr, uint32_t value) { - volatile uint32_t * loc = (volatile uint32_t *) addr; - *loc = value; -} +/* inline void write_reg(uintptr_t addr, uint32_t value) { */ +/* volatile uint32_t * loc = (volatile uint32_t *) addr; */ +/* *loc = value; */ +/* } */ -// Read a register -inline void read_reg(uintptr_t addr) { - return *(volatile uint32_t *) addr; -} +/* // Read a register */ +/* inline uint32_t read_reg(uintptr_t addr) { */ +/* return *(volatile uint32_t *) addr; */ +/* } */ -// Queues a single byte in the transfer fifo -inline void spi_sendbyte(uint8_t byte) { - // Write byte to transfer fifo - write_reg(SPI_TXDATA, byte); -} +/* // Queues a single byte in the transfer fifo */ +/* inline void spi_sendbyte(uint8_t byte) { */ +/* // Write byte to transfer fifo */ +/* write_reg(SPI_TXDATA, byte); */ +/* } */ -inline uint8_t spi_readbyte() { - return read_reg(SPI_RXDATA); -} +/* inline void waittx() { */ +/* while(!(read_reg(SPI_IP) & 1)) {} */ +/* } */ -inline void waittx() { - while(!(read_reg(SPI_IP) & 1)) {} -} - -inline void waitrx() { - while(read_reg(SPI_IP) & 2)) {} -} +/* inline void waitrx() { */ +/* while(read_reg(SPI_IP) & 2) {} */ +/* } */ uint8_t spi_txrx(uint8_t byte) { spi_sendbyte(0xFF); @@ -64,6 +60,10 @@ uint8_t spi_txrx(uint8_t byte) { return spi_readbyte(); } +/* inline uint8_t spi_readbyte() { */ +/* return read_reg(SPI_RXDATA); */ +/* } */ + uint64_t spi_read64() { uint64_t r; uint8_t rbyte; diff --git a/fpga/zsbl/spi.h b/fpga/zsbl/spi.h index e91bcc0ea..bc85c768f 100644 --- a/fpga/zsbl/spi.h +++ b/fpga/zsbl/spi.h @@ -28,15 +28,15 @@ #define SPI_IP SPI_BASE + 0x74 /* Interrupt Pendings Register */ /* delay0 bits */ -#define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x)) +#define SIFIVE_SPI_DELAY0_CSSCK(x) ((uint32_t)(x)) #define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU -#define SIFIVE_SPI_DELAY0_SCKCS(x) ((u32)(x) << 16) +#define SIFIVE_SPI_DELAY0_SCKCS(x) ((uint32_t)(x) << 16) #define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16) /* delay1 bits */ -#define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x)) +#define SIFIVE_SPI_DELAY1_INTERCS(x) ((uint32_t)(x)) #define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU -#define SIFIVE_SPI_DELAY1_INTERXFR(x) ((u32)(x) << 16) +#define SIFIVE_SPI_DELAY1_INTERXFR(x) ((uint32_t)(x) << 16) #define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16) /* csmode bits */ @@ -48,14 +48,42 @@ #define WAITTX while(!(read_reg(SPI_IP) & 1) {} #define WAITRX while(read_reg(SPI_IP) & 2) {} -inline void write_reg(uintptr_t addr, uint32_t value); -inline uint32_t read_reg(uintptr_t addr); -inline void spi_sendbyte(uint8_t byte); -inline void waittx(); -inline void waitrx(); +// inline void write_reg(uintptr_t addr, uint32_t value); +//inline uint32_t read_reg(uintptr_t addr); +//inline void spi_sendbyte(uint8_t byte); +//inline void waittx(); +//inline void waitrx(); uint8_t spi_txrx(uint8_t byte); -inline uint8_t spi_readbyte(); +//inline uint8_t spi_readbyte(); uint64_t spi_read64(); void spi_init(); +static inline void write_reg(uintptr_t addr, uint32_t value) { + volatile uint32_t * loc = (volatile uint32_t *) addr; + *loc = value; +} + +// Read a register +static inline uint32_t read_reg(uintptr_t addr) { + return *(volatile uint32_t *) addr; +} + +// Queues a single byte in the transfer fifo +static inline void spi_sendbyte(uint8_t byte) { + // Write byte to transfer fifo + write_reg(SPI_TXDATA, byte); +} + +static inline void waittx() { + while(!(read_reg(SPI_IP) & 1)) {} +} + +static inline void waitrx() { + while(read_reg(SPI_IP) & 2) {} +} + +static inline uint8_t spi_readbyte() { + return read_reg(SPI_RXDATA); +} + #endif diff --git a/fpga/zsbl/uart.c b/fpga/zsbl/uart.c index a08690069..be3270e28 100644 --- a/fpga/zsbl/uart.c +++ b/fpga/zsbl/uart.c @@ -14,12 +14,12 @@ uint8_t read_reg_u8(uintptr_t addr) int is_transmit_empty() { - return read_reg_u8(UART_LINE_STATUS) & 0x20; + return read_reg_u8(UART_LSR) & 0x20; } int is_receive_empty() { - return !(read_reg_u8(UART_LINE_STATUS) & 0x1); + return !(read_reg_u8(UART_LSR) & 0x1); } void write_serial(char a) From f1cc7dd5a378111c05f84f80601bd79fe5589442 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Tue, 23 Jul 2024 17:26:39 -0500 Subject: [PATCH 120/219] Fixed verilog bugs. --- fpga/src/fpgaTopArtyA7.sv | 3 +-- src/uncore/uncore.sv | 4 ++-- src/wally/wallypipelinedsoc.sv | 5 ++--- 3 files changed, 5 insertions(+), 7 deletions(-) diff --git a/fpga/src/fpgaTopArtyA7.sv b/fpga/src/fpgaTopArtyA7.sv index 6a2f055ba..31848f33e 100644 --- a/fpga/src/fpgaTopArtyA7.sv +++ b/fpga/src/fpgaTopArtyA7.sv @@ -80,7 +80,6 @@ module fpgaTop wire [63:0] HRDATAEXT; wire HREADYEXT; wire HRESPEXT; - wire HSELEXTSDC; // TEMP BOOT SIGNAL - JACOB wire HSELEXT; wire [55:0] HADDR; wire [63:0] HWDATA; @@ -240,7 +239,7 @@ module fpgaTop wallypipelinedsoc #(P) wallypipelinedsoc(.clk(CPUCLK), .reset_ext(bus_struct_reset), .reset(), .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, - .HSELEXTSDC, .HCLK(HCLKOpen), .HRESETn(HRESETnOpen), + .HCLK(HCLKOpen), .HRESETn(HRESETnOpen), .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index dad558c19..c3414352f 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -168,9 +168,9 @@ module uncore import cvw::*; #(parameter cvw_t P)( if (P.SDC_SUPPORTED == 1) begin : sdc spi_apb #(P) sdc( - .PCLK, .PRESETN, .PSEL(.PSEL[5]), .PADDR(PADDR[7:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, + .PCLK, .PRESETn, .PSEL(PSEL[5]), .PADDR(PADDR[7:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, .PREADY(PREADY[5]), .PRDATA(PRDATA[5]), - .SPIOut(SDCCmd), .SPIIn(SDCIn), .SPICS(SDCCS), .SPICLK(SDCCLK), .SPIIntr(.SDCIntr)); + .SPIOut(SDCCmd), .SPIIn(SDCIn), .SPICS(SDCCS), .SPICLK(SDCCLK), .SPIIntr(SDCIntr)); end else begin : sdc assign SDCCmd = '0; assign SDCCD = 1'b0; assign SDCIntr = 1'b0; assign SDCCLK = 1'b0; end diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index af9f0ff26..7ad173b78 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -35,7 +35,6 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) ( input logic [P.AHBW-1:0] HRDATAEXT, input logic HREADYEXT, HRESPEXT, output logic HSELEXT, - output logic HSELEXTSDC, // outputs to external memory, shared with uncore memory output logic HCLK, HRESETn, output logic [P.PA_BITS-1:0] HADDR, @@ -86,11 +85,11 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) ( if (P.BUS_SUPPORTED) begin : uncoregen // Hack to work around Verilator bug https://github.com/verilator/verilator/issues/4769 uncore #(P) uncore(.HCLK, .HRESETn, .TIMECLK, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, - .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, .HSELEXTSDC, + .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, .UARTSout, .MTIME_CLINT, .SPIIn, .SPIOut, .SPICS, .SPICLK, .SDCIn, .SDCCmd, .SDCCS, .SDCCLK); end else begin - assign {HRDATA, HREADY, HRESP, HSELEXT, HSELEXTSDC, MTimerInt, MSwInt, MExtInt, SExtInt, + assign {HRDATA, HREADY, HRESP, HSELEXT, MTimerInt, MSwInt, MExtInt, SExtInt, MTIME_CLINT, GPIOOUT, GPIOEN, UARTSout, SPIOut, SPICS} = '0; end From 6c212ebf0efa671199abefcd2a64863dbf495e73 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 23 Jul 2024 17:39:38 -0500 Subject: [PATCH 121/219] Changes are confirmed to work on the FPGA. --- src/rvvi/rvvisynth.sv | 2 +- testbench/testbench.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/rvvi/rvvisynth.sv b/src/rvvi/rvvisynth.sv index 83c865529..f42e9c1a8 100644 --- a/src/rvvi/rvvisynth.sv +++ b/src/rvvi/rvvisynth.sv @@ -28,7 +28,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module rvvisynth import cvw::*; #(parameter cvw_t P, - parameter integer MAX_CSRS = 3, + parameter integer MAX_CSRS = 5, parameter integer TOTAL_CSRS = 36)( input logic clk, reset, input logic StallE, StallM, StallW, FlushE, FlushM, FlushW, diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 4885a6121..318d3d016 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -604,7 +604,7 @@ module testbench; end if(P.RVVI_SYNTH_SUPPORTED) begin : rvvi_synth - localparam MAX_CSRS = 3; + localparam MAX_CSRS = 5; logic valid; logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi; From 9404a339ee202e24162f377ac626a953170f323f Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 23 Jul 2024 17:44:37 -0500 Subject: [PATCH 122/219] Handled all remaining verilator warnings in the rvvi synth code. Now it's time to take on the verilog-ethernet warnings. --- src/rvvi/rvvisynth.sv | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/rvvi/rvvisynth.sv b/src/rvvi/rvvisynth.sv index f42e9c1a8..0c0214b3f 100644 --- a/src/rvvi/rvvisynth.sv +++ b/src/rvvi/rvvisynth.sv @@ -88,6 +88,9 @@ module rvvisynth import cvw::*; #(parameter cvw_t P, {FPRWen, GPRWen} == 2'b10 ? {XLENZeros, 5'b0, FPRValue, FPRAddr} : '0; + /* verilator lint_off UNOPTFLAT */ + // For some reason verilator complains about CSRWenFilterMatrix being in a circular loop when it is not. + // the CSRs are complex // 1. we need to get the CSR values // 2. we check if the CSR value changes by registering the value then XORing with the old value. @@ -121,9 +124,12 @@ module rvvisynth import cvw::*; #(parameter cvw_t P, always_comb begin CSRCountShort = '0; for(index2 = 0; index2 < MAX_CSRS; index2++) begin + /* verilator lint_off WIDTHEXPAND */ CSRCountShort += EnabledCSRs[index2]; + /* verilator lint_on WIDTHEXPAND */ end end + /* verilator lint_on UNOPTFLAT */ assign CSRCount = {{{12-MAX_CSRS}{1'b0}}, CSRCountShort}; assign rvvi = {CSRs, Registers, Required}; From 47452ddaaa35479804263f75f62fb576ed40818a Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 23 Jul 2024 01:58:19 -0700 Subject: [PATCH 123/219] Remove hardcoded /opt/riscv --- bin/libppa.pl | 4 ++-- linux/sdcard/Makefile | 2 -- linux/sdcard/flash-sd.sh | 1 - linux/sdcard/make-img.sh | 1 - sim/Makefile | 6 +++--- sim/buildrootBugFinder.py | 5 +++-- testbench/testbench.sv | 6 +++--- 7 files changed, 11 insertions(+), 14 deletions(-) diff --git a/bin/libppa.pl b/bin/libppa.pl index bb3d4b729..eddfc3686 100755 --- a/bin/libppa.pl +++ b/bin/libppa.pl @@ -43,7 +43,7 @@ my @cr; my @cf; my @rt; my @ft; my $libpath; my $libbase; my $cellname; my @corners; # Sky130 -$libpath ="/opt/riscv/cad/lib/sky130_osu_sc_t12/12T_ms/lib"; +$libpath ="$ENV{RISCV}/cad/lib/sky130_osu_sc_t12/12T_ms/lib"; $libbase = "sky130_osu_sc_12T_ms_"; $cellname = "sky130_osu_sc_12T_ms__inv_1"; @corners = ("TT_1P8_25C.ccs", "tt_1P80_25C.ccs", "tt_1P62_25C.ccs", "tt_1P89_25C.ccs", "ss_1P60_-40C.ccs", "ss_1P60_100C.ccs", "ss_1P60_150C.ccs", "ff_1P95_-40C.ccs", "ff_1P95_100C.ccs", "ff_1P95_150C.ccs"); @@ -53,7 +53,7 @@ foreach my $corner (@corners) { } # Sky90 -$libpath ="/opt/riscv/cad/lib/sky90/sky90_sc/V1.7.4/lib"; +$libpath ="$ENV{RISCV}/cad/lib/sky90/sky90_sc/V1.7.4/lib"; $libbase = "scc9gena_"; $cellname = "scc9gena_inv_1"; @corners = ("tt_1.2v_25C", "tt_1.08v_25C", "tt_1.32v_25C", "tt_1.2v_-40C", "tt_1.2v_85C", "tt_1.2v_125C", "ss_1.2v_25C", "ss_1.08v_-40C", "ss_1.08v_25C", "ss_1.08v_125C", "ff_1.2v_25C", "ff_1.32v_-40C", "ff_1.32v_25C", "ff_1.32v_125C"); diff --git a/linux/sdcard/Makefile b/linux/sdcard/Makefile index 7c6c012f9..643514815 100644 --- a/linux/sdcard/Makefile +++ b/linux/sdcard/Makefile @@ -1,5 +1,3 @@ -RISCV := /opt/riscv - .PHONY: all clean all: diff --git a/linux/sdcard/flash-sd.sh b/linux/sdcard/flash-sd.sh index 7019611a9..7a2c58d42 100755 --- a/linux/sdcard/flash-sd.sh +++ b/linux/sdcard/flash-sd.sh @@ -25,7 +25,6 @@ ERRORTEXT="$BOLDRED"ERROR:"$NC" WARNINGTEXT="$BOLDYELLOW"Warning:"$NC" # Default values for buildroot and device tree -RISCV=/opt/riscv BUILDROOT=$RISCV/buildroot DEVICE_TREE=wally-vcu108.dtb MNT_DIR=wallyimg diff --git a/linux/sdcard/make-img.sh b/linux/sdcard/make-img.sh index 12a9084d4..df6193f16 100755 --- a/linux/sdcard/make-img.sh +++ b/linux/sdcard/make-img.sh @@ -9,7 +9,6 @@ NC='\033[0m' NAME="$GREEN"${0:2}"$NC" # File location variables -RISCV=/opt/riscv IMAGES=$RISCV/buildroot/output/images FW_JUMP=$IMAGES/fw_jump.bin LINUX_KERNEL=$IMAGES/Image diff --git a/sim/Makefile b/sim/Makefile index 5635431ff..1807a280f 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -34,9 +34,9 @@ QuestaCodeCoverage: questa/ucdb/rv64gc_arch64i.ucdb imperasdv_cov: touch ${SIM}/seed0.txt echo "0" > ${SIM}/seed0.txt -# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --verbose --seed 0 --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m -# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${SIM}/seed0.txt --coverdb ${SIM}/cov/rv64gc_arch64i.ucdb --verbose -# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${SIM}/seed0.txt --coverdb ${SIM}/questa/riscv.ucdb --verbose +# ${RISCV}/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --verbose --seed 0 --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m +# ${RISCV}/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${SIM}/seed0.txt --coverdb ${SIM}/cov/rv64gc_arch64i.ucdb --verbose +# ${RISCV}/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${SIM}/seed0.txt --coverdb ${SIM}/questa/riscv.ucdb --verbose run-elf-cov.bash --elf ${WALLY}/tests/riscvdv/asm_test/riscv_arithmetic_basic_test_0.elf --seed ${SIM}/questa/seed0.txt --coverdb ${SIM}/questa/riscv.ucdb --verbose vcover report -details -html ${SIM}/questa/riscv.ucdb diff --git a/sim/buildrootBugFinder.py b/sim/buildrootBugFinder.py index 55613e64b..ee9fe0603 100755 --- a/sim/buildrootBugFinder.py +++ b/sim/buildrootBugFinder.py @@ -2,9 +2,10 @@ import sys, os, subprocess def main(): + RISCV = os.environ.get("RISCV") maxGoodCount = 400e6 # num instrs that execute sucessfully starting from 0 currInstrCount = maxGoodCount - linuxTestvectors = "/opt/riscv/linux-testvectors" + linuxTestvectors = RISCV+"/linux-testvectors" if not os.path.exists(linuxTestvectors): sys.stderr.write("Error: Linux testvectors not found at "+linuxTestvectors+"\n") exit(1) @@ -22,7 +23,7 @@ def main(): break checkpoint = checkpointList[0] logFile = logDir+"checkpoint"+str(checkpoint)+".log" - runCommand="{\nvsim -c < Date: Tue, 23 Jul 2024 23:40:03 -0700 Subject: [PATCH 124/219] Fix logging --- bin/wally-tool-chain-install.sh | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index a2c6a0413..258c9bab0 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -100,7 +100,7 @@ export PATH=$PATH:$RISCV/bin:/usr/bin export PKG_CONFIG_PATH=$RISCV/lib64/pkgconfig:$RISCV/lib/pkgconfig:$RISCV/share/pkgconfig:$RISCV/lib/x86_64-linux-gnu/pkgconfig:$PKG_CONFIG_PATH # Create installation directory -mkdir -p "$RISCV" +mkdir -p "$RISCV"/logs echo "Running as root: $ROOT" echo "Installation path: $RISCV" @@ -209,7 +209,7 @@ if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain git reset --hard && git clean -f && git checkout master && git pull git pull ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" - make -j ${NUM_THREADS} 2>&1 | tee "$RISCV"/logs/riscv-gnu-toolchain.log | grep -iE "(warning|error|fail|success|stamp)" + make -j ${NUM_THREADS} 2>&1 | tee "$RISCV"/logs/riscv-gnu-toolchain.log | (grep -iE "(warning|error|fail|success|stamp)" || true) if [ "$clean" ]; then cd "$RISCV" rm -rf riscv-gnu-toolchain @@ -258,8 +258,8 @@ if git_check "qemu" "https://github.com/qemu/qemu" "$RISCV/include/qemu-plugin.h git reset --hard && git clean -f && git checkout master && git pull --recurse-submodules -j ${NUM_THREADS} git submodule update --init --recursive ./configure --target-list=riscv64-softmmu --prefix="$RISCV" - make -j ${NUM_THREADS} 2>&1 | tee "$RISCV"/logs/qemu.log | grep -iE "(warning|error|fail|success)" - make install 2>&1 | tee -a "$RISCV"/logs/qemu.log | grep -iE "(warning|error|fail|success)" + make -j ${NUM_THREADS} 2>&1 | tee "$RISCV"/logs/qemu.log | (grep -iE "(warning|error|fail|success)" || true) + make install 2>&1 | tee -a "$RISCV"/logs/qemu.log | (grep -iE "(warning|error|fail|success)" || true) if [ "$clean" ]; then cd "$RISCV" rm -rf qemu @@ -281,8 +281,8 @@ if git_check "riscv-isa-sim" "https://github.com/riscv-software-src/riscv-isa-si mkdir -p build cd build ../configure --prefix="$RISCV" - make -j ${NUM_THREADS} 2>&1 | tee "$RISCV"/logs/spike.log | grep -iE "(warning|error|fail|success)" - make install 2>&1 | tee -a "$RISCV"/logs/spike.log | grep -iE "(warning|error|fail|success)" + make -j ${NUM_THREADS} 2>&1 | tee "$RISCV"/logs/spike.log | (grep -iE "(warning|error|fail|success)" || true) + make install 2>&1 | tee -a "$RISCV"/logs/spike.log | (grep -iE "(warning|error|fail|success)" || true) if [ "$clean" ]; then cd "$RISCV" rm -rf riscv-isa-sim @@ -306,8 +306,8 @@ if git_check "verilator" "https://github.com/verilator/verilator" "$RISCV/share/ git reset --hard && git clean -f && git checkout master && git pull autoconf ./configure --prefix="$RISCV" - make -j ${NUM_THREADS} 2>&1 | tee "$RISCV"/logs/verilator.log | grep -iE "(warning|error|fail|success)" - make install 2>&1 | tee -a "$RISCV"/logs/verilator.log | grep -iE "(warning|error|fail|success)" + make -j ${NUM_THREADS} 2>&1 | tee "$RISCV"/logs/verilator.log | (grep -iE "(warning|error|fail|success)" || true) + make install 2>&1 | tee -a "$RISCV"/logs/verilator.log | (grep -iE "(warning|error|fail|success)" || true) if [ "$clean" ]; then cd "$RISCV" rm -rf verilator @@ -361,8 +361,8 @@ if git_check "sail-riscv" "https://github.com/riscv/sail-riscv.git" "$RISCV/bin/ cd sail-riscv git reset --hard && git clean -f && git checkout master && git pull export OPAMCLI=2.0 # Sail is not compatible with opam 2.1 as of 4/16/24 - ARCH=RV64 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV64 2>&1 | tee "$RISCV"/logs/sail_model.log | grep -iE "(warning|error|fail|success)" - ARCH=RV32 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV32 2>&1 | tee -a "$RISCV"/logs/sail_model.log | grep -iE "(warning|error|fail|success)" + ARCH=RV64 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV64 2>&1 | tee "$RISCV"/logs/sail_model.log | (grep -iE "(warning|error|fail|success)" || true) + ARCH=RV32 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV32 2>&1 | tee -a "$RISCV"/logs/sail_model.log | (grep -iE "(warning|error|fail|success)" || true) cp -f c_emulator/riscv_sim_RV64 "$RISCV"/bin/riscv_sim_RV64 cp -f c_emulator/riscv_sim_RV32 "$RISCV"/bin/riscv_sim_RV32 if [ "$clean" ]; then From d08deddcc4e5bdaa1c840ef2c9bbfc94b6120f6f Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 23 Jul 2024 21:49:31 -0700 Subject: [PATCH 125/219] Update logging grep --- bin/wally-tool-chain-install.sh | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 258c9bab0..6788acb34 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -209,7 +209,7 @@ if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain git reset --hard && git clean -f && git checkout master && git pull git pull ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" - make -j ${NUM_THREADS} 2>&1 | tee "$RISCV"/logs/riscv-gnu-toolchain.log | (grep -iE "(warning|error|fail|success|stamp)" || true) + make -j ${NUM_THREADS} 2>&1 | tee "$RISCV"/logs/riscv-gnu-toolchain.log | (grep -iE "(\bwarning|\berror|\bfail|\bsuccess|\bstamp)" || true) if [ "$clean" ]; then cd "$RISCV" rm -rf riscv-gnu-toolchain @@ -236,8 +236,8 @@ if git_check "elf2hex" "https://github.com/sifive/elf2hex.git" "$RISCV/bin/riscv git reset --hard && git clean -f && git checkout master && git pull autoreconf -i ./configure --target=riscv64-unknown-elf --prefix="$RISCV" - make - make install + make 2>&1 | tee "$RISCV"/logs/elf2hex.log | (grep -iE "(\bwarning|\berror|\bfail|\bsuccess)" || true) + make install 2>&1 | tee -a "$RISCV"/logs/elf2hex.log | (grep -iE "(\bwarning|\berror|\bfail|\bsuccess)" || true) if [ "$clean" ]; then cd "$RISCV" rm -rf elf2hex @@ -258,8 +258,8 @@ if git_check "qemu" "https://github.com/qemu/qemu" "$RISCV/include/qemu-plugin.h git reset --hard && git clean -f && git checkout master && git pull --recurse-submodules -j ${NUM_THREADS} git submodule update --init --recursive ./configure --target-list=riscv64-softmmu --prefix="$RISCV" - make -j ${NUM_THREADS} 2>&1 | tee "$RISCV"/logs/qemu.log | (grep -iE "(warning|error|fail|success)" || true) - make install 2>&1 | tee -a "$RISCV"/logs/qemu.log | (grep -iE "(warning|error|fail|success)" || true) + make -j ${NUM_THREADS} 2>&1 | tee "$RISCV"/logs/qemu.log | (grep -iE "(\bwarning|\berror|\bfail|\bsuccess)" || true) + make install 2>&1 | tee -a "$RISCV"/logs/qemu.log | (grep -iE "(\bwarning|\berror|\bfail|\bsuccess)" || true) if [ "$clean" ]; then cd "$RISCV" rm -rf qemu @@ -281,8 +281,8 @@ if git_check "riscv-isa-sim" "https://github.com/riscv-software-src/riscv-isa-si mkdir -p build cd build ../configure --prefix="$RISCV" - make -j ${NUM_THREADS} 2>&1 | tee "$RISCV"/logs/spike.log | (grep -iE "(warning|error|fail|success)" || true) - make install 2>&1 | tee -a "$RISCV"/logs/spike.log | (grep -iE "(warning|error|fail|success)" || true) + make -j ${NUM_THREADS} 2>&1 | tee "$RISCV"/logs/spike.log | (grep -iE "(\bwarning|\berror|\bfail|\bsuccess)" || true) + make install 2>&1 | tee -a "$RISCV"/logs/spike.log | (grep -iE "(\bwarning|\berror|\bfail|\bsuccess)" || true) if [ "$clean" ]; then cd "$RISCV" rm -rf riscv-isa-sim @@ -306,8 +306,8 @@ if git_check "verilator" "https://github.com/verilator/verilator" "$RISCV/share/ git reset --hard && git clean -f && git checkout master && git pull autoconf ./configure --prefix="$RISCV" - make -j ${NUM_THREADS} 2>&1 | tee "$RISCV"/logs/verilator.log | (grep -iE "(warning|error|fail|success)" || true) - make install 2>&1 | tee -a "$RISCV"/logs/verilator.log | (grep -iE "(warning|error|fail|success)" || true) + make -j ${NUM_THREADS} 2>&1 | tee "$RISCV"/logs/verilator.log | (grep -iE "(\bwarning|\berror|\bfail|\bsuccess)" || true) + make install 2>&1 | tee -a "$RISCV"/logs/verilator.log | (grep -iE "(\bwarning|\berror|\bfail|\bsuccess)" || true) if [ "$clean" ]; then cd "$RISCV" rm -rf verilator @@ -361,8 +361,8 @@ if git_check "sail-riscv" "https://github.com/riscv/sail-riscv.git" "$RISCV/bin/ cd sail-riscv git reset --hard && git clean -f && git checkout master && git pull export OPAMCLI=2.0 # Sail is not compatible with opam 2.1 as of 4/16/24 - ARCH=RV64 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV64 2>&1 | tee "$RISCV"/logs/sail_model.log | (grep -iE "(warning|error|fail|success)" || true) - ARCH=RV32 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV32 2>&1 | tee -a "$RISCV"/logs/sail_model.log | (grep -iE "(warning|error|fail|success)" || true) + ARCH=RV64 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV64 2>&1 | tee "$RISCV"/logs/sail_model.log | (grep -iE "(\bwarning|\berror|\bfail|\bsuccess)" || true) + ARCH=RV32 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV32 2>&1 | tee -a "$RISCV"/logs/sail_model.log | (grep -iE "(\bwarning|\berror|\bfail|\bsuccess)" || true) cp -f c_emulator/riscv_sim_RV64 "$RISCV"/bin/riscv_sim_RV64 cp -f c_emulator/riscv_sim_RV32 "$RISCV"/bin/riscv_sim_RV32 if [ "$clean" ]; then From bb5c9f9ead7128f0572c99a233b9fac768e88372 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 23 Jul 2024 22:56:07 -0700 Subject: [PATCH 126/219] Switch to logger function and fix exit codes --- bin/wally-tool-chain-install.sh | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 6788acb34..cf86f0427 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -45,6 +45,7 @@ WARNING_COLOR='\033[93m' FAIL_COLOR='\033[91m' ENDC='\033[0m' # Reset to default color +## Helper functions # Error handler error() { echo -e "${FAIL_COLOR}Error: $STATUS installation failed" @@ -66,6 +67,12 @@ git_check() { fi } +# Log output to a file and only print lines with keywords +logger() { + local log="$RISCV/logs/$1.log" + cat < /dev/stdin | tee -a "$log" | (grep -iE --color=never "(\bwarning|\berror|\bfail|\bsuccess|\bstamp)" || true) +} + set -e # break on error trap error ERR # run error handler on error STATUS="setup" # keep track of what part of the installation is running for error messages @@ -209,7 +216,7 @@ if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain git reset --hard && git clean -f && git checkout master && git pull git pull ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" - make -j ${NUM_THREADS} 2>&1 | tee "$RISCV"/logs/riscv-gnu-toolchain.log | (grep -iE "(\bwarning|\berror|\bfail|\bsuccess|\bstamp)" || true) + make -j ${NUM_THREADS} 2>&1 | logger riscv-gnu-toolchain; [ "${PIPESTATUS[0]}" == 0 ] if [ "$clean" ]; then cd "$RISCV" rm -rf riscv-gnu-toolchain @@ -236,8 +243,8 @@ if git_check "elf2hex" "https://github.com/sifive/elf2hex.git" "$RISCV/bin/riscv git reset --hard && git clean -f && git checkout master && git pull autoreconf -i ./configure --target=riscv64-unknown-elf --prefix="$RISCV" - make 2>&1 | tee "$RISCV"/logs/elf2hex.log | (grep -iE "(\bwarning|\berror|\bfail|\bsuccess)" || true) - make install 2>&1 | tee -a "$RISCV"/logs/elf2hex.log | (grep -iE "(\bwarning|\berror|\bfail|\bsuccess)" || true) + make 2>&1 | logger elf2hex; [ "${PIPESTATUS[0]}" == 0 ] + make install 2>&1 | logger elf2hex; [ "${PIPESTATUS[0]}" == 0 ] if [ "$clean" ]; then cd "$RISCV" rm -rf elf2hex @@ -258,8 +265,8 @@ if git_check "qemu" "https://github.com/qemu/qemu" "$RISCV/include/qemu-plugin.h git reset --hard && git clean -f && git checkout master && git pull --recurse-submodules -j ${NUM_THREADS} git submodule update --init --recursive ./configure --target-list=riscv64-softmmu --prefix="$RISCV" - make -j ${NUM_THREADS} 2>&1 | tee "$RISCV"/logs/qemu.log | (grep -iE "(\bwarning|\berror|\bfail|\bsuccess)" || true) - make install 2>&1 | tee -a "$RISCV"/logs/qemu.log | (grep -iE "(\bwarning|\berror|\bfail|\bsuccess)" || true) + make -j ${NUM_THREADS} 2>&1 | logger qemu; [ "${PIPESTATUS[0]}" == 0 ] + make install 2>&1 | logger qemu; [ "${PIPESTATUS[0]}" == 0 ] if [ "$clean" ]; then cd "$RISCV" rm -rf qemu @@ -281,8 +288,8 @@ if git_check "riscv-isa-sim" "https://github.com/riscv-software-src/riscv-isa-si mkdir -p build cd build ../configure --prefix="$RISCV" - make -j ${NUM_THREADS} 2>&1 | tee "$RISCV"/logs/spike.log | (grep -iE "(\bwarning|\berror|\bfail|\bsuccess)" || true) - make install 2>&1 | tee -a "$RISCV"/logs/spike.log | (grep -iE "(\bwarning|\berror|\bfail|\bsuccess)" || true) + make -j ${NUM_THREADS} 2>&1 | logger spike; [ "${PIPESTATUS[0]}" == 0 ] + make install 2>&1 | logger spike; [ "${PIPESTATUS[0]}" == 0 ] if [ "$clean" ]; then cd "$RISCV" rm -rf riscv-isa-sim @@ -306,8 +313,8 @@ if git_check "verilator" "https://github.com/verilator/verilator" "$RISCV/share/ git reset --hard && git clean -f && git checkout master && git pull autoconf ./configure --prefix="$RISCV" - make -j ${NUM_THREADS} 2>&1 | tee "$RISCV"/logs/verilator.log | (grep -iE "(\bwarning|\berror|\bfail|\bsuccess)" || true) - make install 2>&1 | tee -a "$RISCV"/logs/verilator.log | (grep -iE "(\bwarning|\berror|\bfail|\bsuccess)" || true) + make -j ${NUM_THREADS} 2>&1 | logger verilator; [ "${PIPESTATUS[0]}" == 0 ] + make install 2>&1 | logger verilator; [ "${PIPESTATUS[0]}" == 0 ] if [ "$clean" ]; then cd "$RISCV" rm -rf verilator @@ -361,8 +368,8 @@ if git_check "sail-riscv" "https://github.com/riscv/sail-riscv.git" "$RISCV/bin/ cd sail-riscv git reset --hard && git clean -f && git checkout master && git pull export OPAMCLI=2.0 # Sail is not compatible with opam 2.1 as of 4/16/24 - ARCH=RV64 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV64 2>&1 | tee "$RISCV"/logs/sail_model.log | (grep -iE "(\bwarning|\berror|\bfail|\bsuccess)" || true) - ARCH=RV32 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV32 2>&1 | tee -a "$RISCV"/logs/sail_model.log | (grep -iE "(\bwarning|\berror|\bfail|\bsuccess)" || true) + ARCH=RV64 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV64 2>&1 | logger sailModel; [ "${PIPESTATUS[0]}" == 0 ] + ARCH=RV32 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV32 2>&1 | logger sailModel; [ "${PIPESTATUS[0]}" == 0 ] cp -f c_emulator/riscv_sim_RV64 "$RISCV"/bin/riscv_sim_RV64 cp -f c_emulator/riscv_sim_RV32 "$RISCV"/bin/riscv_sim_RV32 if [ "$clean" ]; then From 27f89fcdbdcc50a2c3021cdd6a6c5eb3b323be1b Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 24 Jul 2024 10:13:03 -0500 Subject: [PATCH 127/219] Updated verilog-ethernet to remove all verilator warnings or at least suppress them. --- addins/verilog-ethernet | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/verilog-ethernet b/addins/verilog-ethernet index 471394b80..c180b22ed 160000 --- a/addins/verilog-ethernet +++ b/addins/verilog-ethernet @@ -1 +1 @@ -Subproject commit 471394b80c95a4859cd55a0f253d5ea502371e98 +Subproject commit c180b22ed5f4112d0ef35b2c5ac1acc45f9ebb5d From b1a711ae0f87622ce7bf484e06979c88d4f31678 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 24 Jul 2024 12:47:50 -0500 Subject: [PATCH 128/219] Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim. --- bin/wsim | 4 ++++ config/derivlist.txt | 4 ---- config/rv32e/config.vh | 5 ----- config/rv32gc/config.vh | 5 ----- config/rv32i/config.vh | 5 ----- config/rv32imc/config.vh | 5 ----- config/rv64gc/config.vh | 5 ----- config/rv64i/config.vh | 5 ----- config/shared/parameter-defs.vh | 5 +---- fpga/generator/wally.tcl | 4 ++-- fpga/src/fpgaTopArtyA7.sv | 8 +++++--- src/cvw.sv | 4 ---- src/rvvi/packetizer.sv | 9 ++++++--- testbench/testbench.sv | 12 ++++++------ 14 files changed, 24 insertions(+), 56 deletions(-) diff --git a/bin/wsim b/bin/wsim index b70d0e26f..b2288deb4 100755 --- a/bin/wsim +++ b/bin/wsim @@ -33,6 +33,7 @@ parser.add_argument("--vcd", "-v", help="Generate testbench.vcd", action="store_ parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true") parser.add_argument("--locksteplog", "-b", help="Retired instruction number to be begin logging.", default=0) parser.add_argument("--covlog", "-d", help="Log coverage after n instructions.", default=0) +parser.add_argument("--rvvi", "-r", help="Simulate rvvi hardware interface and ethernet.", action="store_true") args = parser.parse_args() print("Config=" + args.config + " tests=" + args.testsuite + " sim=" + args.sim + " gui=" + str(args.gui) + " args='" + args.args + "'") ElfFile="" @@ -64,6 +65,9 @@ if (args.gui or args.ccov or args.fcov or args.lockstep): if (args.vcd): args.args += " -DMAKEVCD=1" +if (args.rvvi): + args.args += " -GRVVI_SYNTH_SUPPORTED=1" + # if lockstep is enabled, then we need to pass the Imperas lockstep arguments if(int(args.locksteplog) >= 1): EnableLog = 1 else: EnableLog = 0 diff --git a/config/derivlist.txt b/config/derivlist.txt index 048adcb21..1edd20b7b 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -57,10 +57,6 @@ EXT_MEM_RANGE 64'h0FFFFFFF SDC_SUPPORTED 1 PLIC_SDC_ID 32'd20 BPRED_SIZE 32'd12 -RVVI_SYNTH_SUPPORTED 1 -RVVI_INIT_TIME_OUT 32'd100000000 -RVVI_PACKET_DELAY 32'd400 - # The syn configurations are trimmed down for faster synthesis. deriv syn_rv32e rv32e diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh index 1234bbcdf..4ec0123d1 100644 --- a/config/rv32e/config.vh +++ b/config/rv32e/config.vh @@ -225,9 +225,4 @@ localparam DIVCOPIES = 32'd4; // Memory synthesis configuration localparam logic USE_SRAM = 0; -// debug tools -localparam logic RVVI_SYNTH_SUPPORTED = 0; -localparam [31:0] RVVI_INIT_TIME_OUT = 32'd4; -localparam [31:0] RVVI_PACKET_DELAY = 32'd2; - `include "config-shared.vh" diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index 9f5809383..c861759d9 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -225,9 +225,4 @@ localparam DIVCOPIES = 32'd2; // Memory synthesis configuration localparam logic USE_SRAM = 0; -// debug tools -localparam logic RVVI_SYNTH_SUPPORTED = 0; -localparam [31:0] RVVI_INIT_TIME_OUT = 32'd4; -localparam [31:0] RVVI_PACKET_DELAY = 32'd2; - `include "config-shared.vh" diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh index 6bfea805e..01818afc2 100644 --- a/config/rv32i/config.vh +++ b/config/rv32i/config.vh @@ -225,9 +225,4 @@ localparam DIVCOPIES = 32'd4; // Memory synthesis configuration localparam logic USE_SRAM = 0; -// debug tools -localparam logic RVVI_SYNTH_SUPPORTED = 0; -localparam [31:0] RVVI_INIT_TIME_OUT = 32'd4; -localparam [31:0] RVVI_PACKET_DELAY = 32'd2; - `include "config-shared.vh" diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh index 3918c702c..05a8fd242 100644 --- a/config/rv32imc/config.vh +++ b/config/rv32imc/config.vh @@ -225,9 +225,4 @@ localparam DIVCOPIES = 32'd4; // Memory synthesis configuration localparam logic USE_SRAM = 0; -// debug tools -localparam logic RVVI_SYNTH_SUPPORTED = 0; -localparam [31:0] RVVI_INIT_TIME_OUT = 32'd4; -localparam [31:0] RVVI_PACKET_DELAY = 32'd2; - `include "config-shared.vh" diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index 86036aaa7..b8ed8dc47 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -225,9 +225,4 @@ localparam DIVCOPIES = 32'd4; // Memory synthesis configuration localparam logic USE_SRAM = 0; -// debug tools -localparam logic RVVI_SYNTH_SUPPORTED = 0; -localparam [31:0] RVVI_INIT_TIME_OUT = 32'd4; -localparam [31:0] RVVI_PACKET_DELAY = 32'd2; - `include "config-shared.vh" diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh index 0e13f9ea1..94360877f 100644 --- a/config/rv64i/config.vh +++ b/config/rv64i/config.vh @@ -225,9 +225,4 @@ localparam DIVCOPIES = 32'd4; // Memory synthesis configuration localparam logic USE_SRAM = 0; -// debug tools -localparam logic RVVI_SYNTH_SUPPORTED = 0; -localparam [31:0] RVVI_INIT_TIME_OUT = 32'd4; -localparam [31:0] RVVI_PACKET_DELAY = 32'd2; - `include "config-shared.vh" diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh index 14b5ee45c..c80b00232 100644 --- a/config/shared/parameter-defs.vh +++ b/config/shared/parameter-defs.vh @@ -200,9 +200,6 @@ localparam cvw_t P = '{ DURLEN : DURLEN, DIVb : DIVb, DIVBLEN : DIVBLEN, - INTDIVb : INTDIVb, - RVVI_SYNTH_SUPPORTED : RVVI_SYNTH_SUPPORTED, - RVVI_INIT_TIME_OUT : RVVI_INIT_TIME_OUT, - RVVI_PACKET_DELAY : RVVI_PACKET_DELAY + INTDIVb : INTDIVb }; diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index 9df775646..93c2788a2 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -89,8 +89,8 @@ report_clock_interaction -file re write_verilog -force -mode funcsim sim/syn-funcsim.v if {$board=="ArtyA7"} { - source ../constraints/small-debug.xdc - #source ../constraints/small-debug-rvvi.xdc + #source ../constraints/small-debug.xdc + source ../constraints/small-debug-rvvi.xdc } else { # source ../constraints/vcu-small-debug.xdc diff --git a/fpga/src/fpgaTopArtyA7.sv b/fpga/src/fpgaTopArtyA7.sv index 314b141a5..9413cedec 100644 --- a/fpga/src/fpgaTopArtyA7.sv +++ b/fpga/src/fpgaTopArtyA7.sv @@ -28,7 +28,7 @@ import cvw::*; -module fpgaTop +module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) (input default_100mhz_clk, (* mark_debug = "true" *) input resetn, input south_reset, @@ -1117,9 +1117,11 @@ module fpgaTop (* mark_debug = "true" *) logic IlaTrigger; - if(P.RVVI_SYNTH_SUPPORTED) begin : rvvi_synth + if(RVVI_SYNTH_SUPPORTED) begin : rvvi_synth localparam MAX_CSRS = 3; localparam TOTAL_CSRS = 36; + localparam [31:0] RVVI_INIT_TIME_OUT = 32'd100000000; + localparam [31:0] RVVI_PACKET_DELAY = 32'd400; // pipeline controlls logic StallE, StallM, StallW, FlushE, FlushM, FlushW; @@ -1218,7 +1220,7 @@ module fpgaTop logic tx_error_underflow, tx_fifo_overflow, tx_fifo_bad_frame, tx_fifo_good_frame, rx_error_bad_frame; logic rx_error_bad_fcs, rx_fifo_overflow, rx_fifo_bad_frame, rx_fifo_good_frame; - packetizer #(P, MAX_CSRS) packetizer(.rvvi, .valid, .m_axi_aclk(CPUCLK), .m_axi_aresetn(~bus_struct_reset), .RVVIStall, + packetizer #(P, MAX_CSRS, RVVI_INIT_TIME_OUT, RVVI_PACKET_DELAY) packetizer(.rvvi, .valid, .m_axi_aclk(CPUCLK), .m_axi_aresetn(~bus_struct_reset), .RVVIStall, .RvviAxiWdata, .RvviAxiWstrb, .RvviAxiWlast, .RvviAxiWvalid, .RvviAxiWready); eth_mac_mii_fifo #(.TARGET("XILINX"), .CLOCK_INPUT_STYLE("BUFG"), .AXIS_DATA_WIDTH(32), .TX_FIFO_DEPTH(1024)) ethernet(.rst(bus_struct_reset), .logic_clk(CPUCLK), .logic_rst(bus_struct_reset), diff --git a/src/cvw.sv b/src/cvw.sv index 7a64be7ba..ed0493484 100644 --- a/src/cvw.sv +++ b/src/cvw.sv @@ -296,10 +296,6 @@ typedef struct packed { int DIVBLEN ; // integer division/remainder constants int INTDIVb ; -// debug tools - logic RVVI_SYNTH_SUPPORTED; - logic [31:0] RVVI_INIT_TIME_OUT; - logic [31:0] RVVI_PACKET_DELAY; } cvw_t; endpackage diff --git a/src/rvvi/packetizer.sv b/src/rvvi/packetizer.sv index 54dc9a27f..cd3103fa4 100644 --- a/src/rvvi/packetizer.sv +++ b/src/rvvi/packetizer.sv @@ -28,7 +28,10 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module packetizer import cvw::*; #(parameter cvw_t P, - parameter integer MAX_CSRS)( + parameter integer MAX_CSRS, + parameter logic [31:0] RVVI_INIT_TIME_OUT = 32'd4, + parameter logic [31:0] RVVI_PACKET_DELAY = 32'd2 +)( input logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi, input logic valid, input logic m_axi_aclk, m_axi_aresetn, @@ -100,8 +103,8 @@ module packetizer import cvw::*; #(parameter cvw_t P, // have to count at least 250 ms after reset pulled to wait for the phy to actually be ready // at 20MHz 250 ms is 250e-3 / (1/20e6) = 5,000,000. counter #(32) rstcounter(m_axi_aclk, RstCountRst, RstCountEn, RstCount); - assign CountFlag = RstCount == P.RVVI_INIT_TIME_OUT; - assign DelayFlag = RstCount == P.RVVI_PACKET_DELAY; + assign CountFlag = RstCount == RVVI_INIT_TIME_OUT; + assign DelayFlag = RstCount == RVVI_PACKET_DELAY; counter #(32) framecounter(m_axi_aclk, ~m_axi_aresetn, (RvviAxiWready & RvviAxiWlast), FrameCount); diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 318d3d016..a32a294d0 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -33,9 +33,6 @@ `include "idv/idv.svh" `endif -// *** bug replace with config? -`define RVVI_SYNTH_SUPPORTED 1 - import cvw::*; module testbench; @@ -46,6 +43,7 @@ module testbench; parameter BPRED_LOGGER=0; parameter I_CACHE_ADDR_LOGGER=0; parameter D_CACHE_ADDR_LOGGER=0; + parameter RVVI_SYNTH_SUPPORTED=0; `ifdef USE_IMPERAS_DV import idvPkg::*; @@ -603,9 +601,11 @@ module testbench; clk = 1'b1; # 5; clk = 1'b0; # 5; end - if(P.RVVI_SYNTH_SUPPORTED) begin : rvvi_synth + if(RVVI_SYNTH_SUPPORTED) begin : rvvi_synth localparam MAX_CSRS = 5; - logic valid; + localparam logic [31:0] RVVI_INIT_TIME_OUT = 32'd4; + localparam logic [31:0] RVVI_PACKET_DELAY = 32'd2; + logic valid; logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi; localparam TOTAL_CSRS = 36; @@ -702,7 +702,7 @@ module testbench; logic tx_error_underflow, tx_fifo_overflow, tx_fifo_bad_frame, tx_fifo_good_frame, rx_error_bad_frame; logic rx_error_bad_fcs, rx_fifo_overflow, rx_fifo_bad_frame, rx_fifo_good_frame; - packetizer #(P, MAX_CSRS) packetizer(.rvvi, .valid, .m_axi_aclk(clk), .m_axi_aresetn(~reset), .RVVIStall, + packetizer #(P, MAX_CSRS, RVVI_INIT_TIME_OUT, RVVI_PACKET_DELAY) packetizer(.rvvi, .valid, .m_axi_aclk(clk), .m_axi_aresetn(~reset), .RVVIStall, .RvviAxiWdata, .RvviAxiWstrb, .RvviAxiWlast, .RvviAxiWvalid, .RvviAxiWready); eth_mac_mii_fifo #("GENERIC", "BUFG", 32) ethernet(.rst(reset), .logic_clk(clk), .logic_rst(reset), From d0a5b278b78b26e5c26259bec93d4460706711e9 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 24 Jul 2024 13:10:57 -0500 Subject: [PATCH 129/219] Factored out the rvvi testbench code into rvvitbwrapper. --- fpga/src/fpgaTopArtyA7.sv | 2 +- testbench/common/rvvitbwrapper.sv | 170 ++++++++++++++++++++++++++++++ testbench/testbench.sv | 126 +--------------------- 3 files changed, 174 insertions(+), 124 deletions(-) create mode 100644 testbench/common/rvvitbwrapper.sv diff --git a/fpga/src/fpgaTopArtyA7.sv b/fpga/src/fpgaTopArtyA7.sv index 9413cedec..827ca1438 100644 --- a/fpga/src/fpgaTopArtyA7.sv +++ b/fpga/src/fpgaTopArtyA7.sv @@ -28,7 +28,7 @@ import cvw::*; -module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) +module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 1) (input default_100mhz_clk, (* mark_debug = "true" *) input resetn, input south_reset, diff --git a/testbench/common/rvvitbwrapper.sv b/testbench/common/rvvitbwrapper.sv new file mode 100644 index 000000000..708cd0e7b --- /dev/null +++ b/testbench/common/rvvitbwrapper.sv @@ -0,0 +1,170 @@ +/////////////////////////////////////////// +// loggers.sv +// +// Written: Rose Thompson ross1728@gmail.com +// Modified: 24 July 2024 +// +// Purpose: Wraps all the synthesizable rvvi hardware into a single module for the testbench. +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module rvvitbwrapper import cvw::*; #(parameter cvw_t P, + parameter MAX_CSRS = 5, + parameter logic [31:0] RVVI_INIT_TIME_OUT = 32'd4, + parameter logic [31:0] RVVI_PACKET_DELAY = 32'd2)( + input logic clk, + input logic reset, + output logic RVVIStall, + input logic mii_tx_clk, + output logic [3:0] mii_txd, + output logic mii_tx_en, mii_tx_er, + input logic mii_rx_clk, + input logic [3:0] mii_rxd, + input logic mii_rx_dv, + input logic mii_rx_er +); + + logic valid; + logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi; + + localparam TOTAL_CSRS = 36; + + // pipeline controlls + logic StallE, StallM, StallW, FlushE, FlushM, FlushW; + // required + logic [P.XLEN-1:0] PCM; + logic InstrValidM; + logic [31:0] InstrRawD; + logic [63:0] Mcycle, Minstret; + logic TrapM; + logic [1:0] PrivilegeModeW; + // registers gpr and fpr + logic GPRWen, FPRWen; + logic [4:0] GPRAddr, FPRAddr; + logic [P.XLEN-1:0] GPRValue, FPRValue; + logic [P.XLEN-1:0] CSRArray [TOTAL_CSRS-1:0]; + + // axi 4 write data channel + logic [31:0] RvviAxiWdata; + logic [3:0] RvviAxiWstrb; + logic RvviAxiWlast; + logic RvviAxiWvalid; + logic RvviAxiWready; + + logic tx_error_underflow, tx_fifo_overflow, tx_fifo_bad_frame, tx_fifo_good_frame, rx_error_bad_frame; + logic rx_error_bad_fcs, rx_fifo_overflow, rx_fifo_bad_frame, rx_fifo_good_frame; + + logic MiiTxEnDelay; + logic EthernetTXCounterEn; + logic [31:0] EthernetTXCount; + + assign StallE = dut.core.StallE; + assign StallM = dut.core.StallM; + assign StallW = dut.core.StallW; + assign FlushE = dut.core.FlushE; + assign FlushM = dut.core.FlushM; + assign FlushW = dut.core.FlushW; + assign InstrValidM = dut.core.ieu.InstrValidM; + assign InstrRawD = dut.core.ifu.InstrRawD; + assign PCM = dut.core.ifu.PCM; + assign Mcycle = dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0]; + assign Minstret = dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]; + assign TrapM = dut.core.TrapM; + assign PrivilegeModeW = dut.core.priv.priv.privmode.PrivilegeModeW; + assign GPRAddr = dut.core.ieu.dp.regf.a3; + assign GPRWen = dut.core.ieu.dp.regf.we3; + assign GPRValue = dut.core.ieu.dp.regf.wd3; + assign FPRAddr = dut.core.fpu.fpu.fregfile.a4; + assign FPRWen = dut.core.fpu.fpu.fregfile.we4; + assign FPRValue = dut.core.fpu.fpu.fregfile.wd4; + + assign CSRArray[0] = dut.core.priv.priv.csr.csrm.MSTATUS_REGW; // 12'h300 + assign CSRArray[1] = dut.core.priv.priv.csr.csrm.MSTATUSH_REGW; // 12'h310 + assign CSRArray[2] = dut.core.priv.priv.csr.csrm.MTVEC_REGW; // 12'h305 + assign CSRArray[3] = dut.core.priv.priv.csr.csrm.MEPC_REGW; // 12'h341 + assign CSRArray[4] = dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW; // 12'h306 + assign CSRArray[5] = dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW; // 12'h320 + assign CSRArray[6] = dut.core.priv.priv.csr.csrm.MEDELEG_REGW; // 12'h302 + assign CSRArray[7] = dut.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h303 + assign CSRArray[8] = dut.core.priv.priv.csr.csrm.MIP_REGW; // 12'h344 + assign CSRArray[9] = dut.core.priv.priv.csr.csrm.MIE_REGW; // 12'h304 + assign CSRArray[10] = dut.core.priv.priv.csr.csrm.MISA_REGW; // 12'h301 + assign CSRArray[11] = dut.core.priv.priv.csr.csrm.MENVCFG_REGW; // 12'h30A + assign CSRArray[12] = dut.core.priv.priv.csr.csrm.MHARTID_REGW; // 12'hF14 + assign CSRArray[13] = dut.core.priv.priv.csr.csrm.MSCRATCH_REGW; // 12'h340 + assign CSRArray[14] = dut.core.priv.priv.csr.csrm.MCAUSE_REGW; // 12'h342 + assign CSRArray[15] = dut.core.priv.priv.csr.csrm.MTVAL_REGW; // 12'h343 + assign CSRArray[16] = 0; // 12'hF11 + assign CSRArray[17] = 0; // 12'hF12 + assign CSRArray[18] = {{P.XLEN-12{1'b0}}, 12'h100}; //P.XLEN'h100; // 12'hF13 + assign CSRArray[19] = 0; // 12'hF15 + assign CSRArray[20] = 0; // 12'h34A + // supervisor CSRs + assign CSRArray[21] = dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW; // 12'h100 + assign CSRArray[22] = dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222; // 12'h104 + assign CSRArray[23] = dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW; // 12'h105 + assign CSRArray[24] = dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW; // 12'h141 + assign CSRArray[25] = dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW; // 12'h106 + assign CSRArray[26] = dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW; // 12'h10A + assign CSRArray[27] = dut.core.priv.priv.csr.csrs.csrs.SATP_REGW; // 12'h180 + assign CSRArray[28] = dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW; // 12'h140 + assign CSRArray[29] = dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW; // 12'h143 + assign CSRArray[30] = dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; // 12'h142 + assign CSRArray[31] = dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & dut.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h144 + assign CSRArray[32] = dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW; // 12'h14D + // user CSRs + assign CSRArray[33] = dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW; // 12'h001 + assign CSRArray[34] = dut.core.priv.priv.csr.csru.csru.FRM_REGW; // 12'h002 + assign CSRArray[35] = {dut.core.priv.priv.csr.csru.csru.FRM_REGW, dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; // 12'h003 + + rvvisynth #(P, MAX_CSRS, TOTAL_CSRS) rvvisynth(.clk, .reset, .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW, + .PCM, .InstrValidM, .InstrRawD, .Mcycle, .Minstret, .TrapM, + .PrivilegeModeW, .GPRWen, .FPRWen, .GPRAddr, .FPRAddr, .GPRValue, .FPRValue, .CSRArray, + .valid, .rvvi); + + packetizer #(P, MAX_CSRS, RVVI_INIT_TIME_OUT, RVVI_PACKET_DELAY) packetizer(.rvvi, .valid, .m_axi_aclk(clk), .m_axi_aresetn(~reset), .RVVIStall, + .RvviAxiWdata, .RvviAxiWstrb, .RvviAxiWlast, .RvviAxiWvalid, .RvviAxiWready); + + eth_mac_mii_fifo #("GENERIC", "BUFG", 32) ethernet(.rst(reset), .logic_clk(clk), .logic_rst(reset), + .tx_axis_tdata(RvviAxiWdata), .tx_axis_tkeep(RvviAxiWstrb), .tx_axis_tvalid(RvviAxiWvalid), .tx_axis_tready(RvviAxiWready), + .tx_axis_tlast(RvviAxiWlast), .tx_axis_tuser('0), .rx_axis_tdata(), .rx_axis_tkeep(), .rx_axis_tvalid(), .rx_axis_tready(1'b1), + .rx_axis_tlast(), .rx_axis_tuser(), + + .mii_rx_clk(clk), + .mii_rxd('0), + .mii_rx_dv('0), + .mii_rx_er('0), + .mii_tx_clk(clk), + .mii_txd, + .mii_tx_en, + .mii_tx_er, + + // status + .tx_error_underflow, .tx_fifo_overflow, .tx_fifo_bad_frame, .tx_fifo_good_frame, .rx_error_bad_frame, + .rx_error_bad_fcs, .rx_fifo_overflow, .rx_fifo_bad_frame, .rx_fifo_good_frame, + .cfg_ifg(8'd12), .cfg_tx_enable(1'b1), .cfg_rx_enable(1'b1)); + + flopr #(1) txedgereg(clk, reset, mii_tx_en, MiiTxEnDelay); + assign EthernetTXCounterEn = ~mii_tx_en & MiiTxEnDelay; + counter #(32) ethernexttxcounter(clk, reset, EthernetTXCounterEn, EthernetTXCount); + +endmodule + + + diff --git a/testbench/testbench.sv b/testbench/testbench.sv index a32a294d0..55bb35843 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -605,133 +605,13 @@ module testbench; localparam MAX_CSRS = 5; localparam logic [31:0] RVVI_INIT_TIME_OUT = 32'd4; localparam logic [31:0] RVVI_PACKET_DELAY = 32'd2; - logic valid; - logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi; - - localparam TOTAL_CSRS = 36; - - // pipeline controlls - logic StallE, StallM, StallW, FlushE, FlushM, FlushW; - // required - logic [P.XLEN-1:0] PCM; - logic InstrValidM; - logic [31:0] InstrRawD; - logic [63:0] Mcycle, Minstret; - logic TrapM; - logic [1:0] PrivilegeModeW; - // registers gpr and fpr - logic GPRWen, FPRWen; - logic [4:0] GPRAddr, FPRAddr; - logic [P.XLEN-1:0] GPRValue, FPRValue; - logic [P.XLEN-1:0] CSRArray [TOTAL_CSRS-1:0]; - - assign StallE = dut.core.StallE; - assign StallM = dut.core.StallM; - assign StallW = dut.core.StallW; - assign FlushE = dut.core.FlushE; - assign FlushM = dut.core.FlushM; - assign FlushW = dut.core.FlushW; - assign InstrValidM = dut.core.ieu.InstrValidM; - assign InstrRawD = dut.core.ifu.InstrRawD; - assign PCM = dut.core.ifu.PCM; - assign Mcycle = dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0]; - assign Minstret = dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]; - assign TrapM = dut.core.TrapM; - assign PrivilegeModeW = dut.core.priv.priv.privmode.PrivilegeModeW; - assign GPRAddr = dut.core.ieu.dp.regf.a3; - assign GPRWen = dut.core.ieu.dp.regf.we3; - assign GPRValue = dut.core.ieu.dp.regf.wd3; - assign FPRAddr = dut.core.fpu.fpu.fregfile.a4; - assign FPRWen = dut.core.fpu.fpu.fregfile.we4; - assign FPRValue = dut.core.fpu.fpu.fregfile.wd4; - - assign CSRArray[0] = dut.core.priv.priv.csr.csrm.MSTATUS_REGW; // 12'h300 - assign CSRArray[1] = dut.core.priv.priv.csr.csrm.MSTATUSH_REGW; // 12'h310 - assign CSRArray[2] = dut.core.priv.priv.csr.csrm.MTVEC_REGW; // 12'h305 - assign CSRArray[3] = dut.core.priv.priv.csr.csrm.MEPC_REGW; // 12'h341 - assign CSRArray[4] = dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW; // 12'h306 - assign CSRArray[5] = dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW; // 12'h320 - assign CSRArray[6] = dut.core.priv.priv.csr.csrm.MEDELEG_REGW; // 12'h302 - assign CSRArray[7] = dut.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h303 - assign CSRArray[8] = dut.core.priv.priv.csr.csrm.MIP_REGW; // 12'h344 - assign CSRArray[9] = dut.core.priv.priv.csr.csrm.MIE_REGW; // 12'h304 - assign CSRArray[10] = dut.core.priv.priv.csr.csrm.MISA_REGW; // 12'h301 - assign CSRArray[11] = dut.core.priv.priv.csr.csrm.MENVCFG_REGW; // 12'h30A - assign CSRArray[12] = dut.core.priv.priv.csr.csrm.MHARTID_REGW; // 12'hF14 - assign CSRArray[13] = dut.core.priv.priv.csr.csrm.MSCRATCH_REGW; // 12'h340 - assign CSRArray[14] = dut.core.priv.priv.csr.csrm.MCAUSE_REGW; // 12'h342 - assign CSRArray[15] = dut.core.priv.priv.csr.csrm.MTVAL_REGW; // 12'h343 - assign CSRArray[16] = 0; // 12'hF11 - assign CSRArray[17] = 0; // 12'hF12 - assign CSRArray[18] = {{P.XLEN-12{1'b0}}, 12'h100}; //P.XLEN'h100; // 12'hF13 - assign CSRArray[19] = 0; // 12'hF15 - assign CSRArray[20] = 0; // 12'h34A - // supervisor CSRs - assign CSRArray[21] = dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW; // 12'h100 - assign CSRArray[22] = dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222; // 12'h104 - assign CSRArray[23] = dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW; // 12'h105 - assign CSRArray[24] = dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW; // 12'h141 - assign CSRArray[25] = dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW; // 12'h106 - assign CSRArray[26] = dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW; // 12'h10A - assign CSRArray[27] = dut.core.priv.priv.csr.csrs.csrs.SATP_REGW; // 12'h180 - assign CSRArray[28] = dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW; // 12'h140 - assign CSRArray[29] = dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW; // 12'h143 - assign CSRArray[30] = dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; // 12'h142 - assign CSRArray[31] = dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & dut.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h144 - assign CSRArray[32] = dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW; // 12'h14D - // user CSRs - assign CSRArray[33] = dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW; // 12'h001 - assign CSRArray[34] = dut.core.priv.priv.csr.csru.csru.FRM_REGW; // 12'h002 - assign CSRArray[35] = {dut.core.priv.priv.csr.csru.csru.FRM_REGW, dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; // 12'h003 - - rvvisynth #(P, MAX_CSRS, TOTAL_CSRS) rvvisynth(.clk, .reset, .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW, - .PCM, .InstrValidM, .InstrRawD, .Mcycle, .Minstret, .TrapM, - .PrivilegeModeW, .GPRWen, .FPRWen, .GPRAddr, .FPRAddr, .GPRValue, .FPRValue, .CSRArray, - .valid, .rvvi); - - // axi 4 write data channel - logic [31:0] RvviAxiWdata; - logic [3:0] RvviAxiWstrb; - logic RvviAxiWlast; - logic RvviAxiWvalid; - logic RvviAxiWready; logic [3:0] mii_txd; logic mii_tx_en, mii_tx_er; - - logic tx_error_underflow, tx_fifo_overflow, tx_fifo_bad_frame, tx_fifo_good_frame, rx_error_bad_frame; - logic rx_error_bad_fcs, rx_fifo_overflow, rx_fifo_bad_frame, rx_fifo_good_frame; - - packetizer #(P, MAX_CSRS, RVVI_INIT_TIME_OUT, RVVI_PACKET_DELAY) packetizer(.rvvi, .valid, .m_axi_aclk(clk), .m_axi_aresetn(~reset), .RVVIStall, - .RvviAxiWdata, .RvviAxiWstrb, .RvviAxiWlast, .RvviAxiWvalid, .RvviAxiWready); - - eth_mac_mii_fifo #("GENERIC", "BUFG", 32) ethernet(.rst(reset), .logic_clk(clk), .logic_rst(reset), - .tx_axis_tdata(RvviAxiWdata), .tx_axis_tkeep(RvviAxiWstrb), .tx_axis_tvalid(RvviAxiWvalid), .tx_axis_tready(RvviAxiWready), - .tx_axis_tlast(RvviAxiWlast), .tx_axis_tuser('0), .rx_axis_tdata(), .rx_axis_tkeep(), .rx_axis_tvalid(), .rx_axis_tready(1'b1), - .rx_axis_tlast(), .rx_axis_tuser(), - - .mii_rx_clk(clk), - .mii_rxd('0), - .mii_rx_dv('0), - .mii_rx_er('0), - .mii_tx_clk(clk), - .mii_txd, - .mii_tx_en, - .mii_tx_er, - - // status - .tx_error_underflow, .tx_fifo_overflow, .tx_fifo_bad_frame, .tx_fifo_good_frame, .rx_error_bad_frame, - .rx_error_bad_fcs, .rx_fifo_overflow, .rx_fifo_bad_frame, .rx_fifo_good_frame, - .cfg_ifg(8'd12), .cfg_tx_enable(1'b1), .cfg_rx_enable(1'b1) - ); - - logic MiiTxEnDelay; - logic EthernetTXCounterEn; - logic [31:0] EthernetTXCount; - flopr #(1) txedgereg(clk, reset, mii_tx_en, MiiTxEnDelay); - assign EthernetTXCounterEn = ~mii_tx_en & MiiTxEnDelay; - counter #(32) ethernexttxcounter(clk, reset, EthernetTXCounterEn, EthernetTXCount); + rvvitbwrapper #(P, MAX_CSRS, RVVI_INIT_TIME_OUT, RVVI_PACKET_DELAY) + rvvitbwrapper(.clk, .reset, .RVVIStall, .mii_tx_clk(clk), .mii_txd, .mii_tx_en, .mii_tx_er, + .mii_rx_clk(clk), .mii_rxd('0), .mii_rx_dv('0), .mii_rx_er('0)); end else begin assign RVVIStall = '0; end From 5cae55561e3a819dd4b9ec3d19c0620b8ded71fd Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 24 Jul 2024 13:30:25 -0500 Subject: [PATCH 130/219] Removed unused file. --- fpga/rvvidaemon/send-copy.c | 133 ------------------------------------ 1 file changed, 133 deletions(-) delete mode 100644 fpga/rvvidaemon/send-copy.c diff --git a/fpga/rvvidaemon/send-copy.c b/fpga/rvvidaemon/send-copy.c deleted file mode 100644 index 5d7f85ee8..000000000 --- a/fpga/rvvidaemon/send-copy.c +++ /dev/null @@ -1,133 +0,0 @@ - -/* - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define DEST_MAC0 0x43 -#define DEST_MAC1 0x68 -#define DEST_MAC2 0x11 -#define DEST_MAC3 0x11 -#define DEST_MAC4 0x02 -#define DEST_MAC5 0x45 - -#define SRC_MAC0 0x54 -#define SRC_MAC1 0x16 -#define SRC_MAC2 0x00 -#define SRC_MAC3 0x00 -#define SRC_MAC4 0x54 -#define SRC_MAC5 0x8F - -#define DEFAULT_IF "eth0" -#define BUF_SIZ 1024 -#define ETHER_TYPE 0x5c00 // The type defined in packetizer.sv - -int main(int argc, char *argv[]) -{ - int sockfd; - struct ifreq if_idx; - struct ifreq if_mac; - int tx_len = 0; - char sendbuf[BUF_SIZ]; - struct ether_header *eh = (struct ether_header *) sendbuf; - struct iphdr *iph = (struct iphdr *) (sendbuf + sizeof(struct ether_header)); - struct sockaddr_ll socket_address; - char ifName[IFNAMSIZ]; - - /* Get interface name */ - if (argc > 1) - strcpy(ifName, argv[1]); - else - strcpy(ifName, DEFAULT_IF); - - /* Open RAW socket to send on */ - //if ((sockfd = socket(AF_PACKET, SOCK_RAW, IPPROTO_RAW)) == -1) { - if ((sockfd = socket(AF_PACKET, SOCK_RAW, htons(ETHER_TYPE))) == -1) { - perror("socket"); - } - - /* Get the index of the interface to send on */ - memset(&if_idx, 0, sizeof(struct ifreq)); - strncpy(if_idx.ifr_name, ifName, IFNAMSIZ-1); - if (ioctl(sockfd, SIOCGIFINDEX, &if_idx) < 0) - perror("SIOCGIFINDEX"); - /* Get the MAC address of the interface to send on */ - memset(&if_mac, 0, sizeof(struct ifreq)); - strncpy(if_mac.ifr_name, ifName, IFNAMSIZ-1); - if (ioctl(sockfd, SIOCGIFHWADDR, &if_mac) < 0) - perror("SIOCGIFHWADDR"); - - /* Construct the Ethernet header */ - memset(sendbuf, 0, BUF_SIZ); - /* Ethernet header */ - /* eh->ether_shost[0] = ((uint8_t *)&if_mac.ifr_hwaddr.sa_data)[0]; */ - /* eh->ether_shost[1] = ((uint8_t *)&if_mac.ifr_hwaddr.sa_data)[1]; */ - /* eh->ether_shost[2] = ((uint8_t *)&if_mac.ifr_hwaddr.sa_data)[2]; */ - /* eh->ether_shost[3] = ((uint8_t *)&if_mac.ifr_hwaddr.sa_data)[3]; */ - /* eh->ether_shost[4] = ((uint8_t *)&if_mac.ifr_hwaddr.sa_data)[4]; */ - /* eh->ether_shost[5] = ((uint8_t *)&if_mac.ifr_hwaddr.sa_data)[5]; */ - eh->ether_shost[0] = SRC_MAC0; - eh->ether_shost[1] = SRC_MAC1; - eh->ether_shost[2] = SRC_MAC2; - eh->ether_shost[3] = SRC_MAC3; - eh->ether_shost[4] = SRC_MAC4; - eh->ether_shost[5] = SRC_MAC5; - eh->ether_dhost[0] = DEST_MAC0; - eh->ether_dhost[1] = DEST_MAC1; - eh->ether_dhost[2] = DEST_MAC2; - eh->ether_dhost[3] = DEST_MAC3; - eh->ether_dhost[4] = DEST_MAC4; - eh->ether_dhost[5] = DEST_MAC5; - /* Ethertype field */ - //eh->ether_type = htons(ETH_P_IP); - eh->ether_type = htons(ETHER_TYPE); - tx_len += sizeof(struct ether_header); - - /* Packet data */ - sendbuf[tx_len++] = 0xde; - sendbuf[tx_len++] = 0xad; - sendbuf[tx_len++] = 0xbe; - sendbuf[tx_len++] = 0xef; - - /* Index of the network device */ - socket_address.sll_ifindex = if_idx.ifr_ifindex; - /* Address length*/ - socket_address.sll_halen = ETH_ALEN; - /* Destination MAC */ - socket_address.sll_addr[0] = DEST_MAC0; - socket_address.sll_addr[1] = DEST_MAC1; - socket_address.sll_addr[2] = DEST_MAC2; - socket_address.sll_addr[3] = DEST_MAC3; - socket_address.sll_addr[4] = DEST_MAC4; - socket_address.sll_addr[5] = DEST_MAC5; - - int i; - printf("buffer: "); - for(i=0;i Date: Wed, 24 Jul 2024 13:32:46 -0500 Subject: [PATCH 131/219] Fixed the reset bug in wallyTracer. --- testbench/common/wallyTracer.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 8c72a6816..80f7af651 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -274,7 +274,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); // Initially connecting the writeback stage signals, but may need to use M stage // and gate on ~FlushW. - assign valid = InstrValidW & ~StallW; + assign valid = InstrValidW & ~StallW & ~reset; assign rvvi.clk = clk; assign rvvi.valid[0][0] = valid; assign rvvi.order[0][0] = CSRArray[12'hB02]; // TODO: IMPERAS Should be event order From bbf90b1f4bc01e0f6fb1344dee0853ac7e51135f Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 24 Jul 2024 19:55:18 -0700 Subject: [PATCH 132/219] Add cpio to installation for buildroot --- bin/wally-package-install.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index ae70c1358..c2a3bb1aa 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -54,7 +54,7 @@ if [ "$FAMILY" == rhel ]; then QEMU_PACKAGES+=(glib2-devel libfdt-devel pixman-devel bzip2 ninja-build) SPIKE_PACKAGES+=(dtc boost-regex boost-system) VERILATOR_PACKAGES+=(help2man perl clang ccache gperftools numactl mold) - BUILDROOT_PACKAGES+=(ncurses-base ncurses ncurses-libs ncurses-devel gcc-gfortran) + BUILDROOT_PACKAGES+=(ncurses-base ncurses ncurses-libs ncurses-devel gcc-gfortran cpio) # Extra packages not availale in rhel8, nice for Verilator and needed for sail respectively if (( RHEL_VERSION >= 9 )); then VERILATOR_PACKAGES+=(perl-doc) @@ -81,7 +81,7 @@ elif [ "$FAMILY" == ubuntu ]; then SPIKE_PACKAGES+=(device-tree-compiler libboost-regex-dev libboost-system-dev) VERILATOR_PACKAGES+=(help2man perl g++ clang ccache libunwind-dev libgoogle-perftools-dev numactl perl-doc libfl2 libfl-dev zlib1g) SAIL_PACKAGES+=(opam z3) - BUILDROOT_PACKAGES+=(ncurses-base ncurses-bin libncurses-dev gfortran) + BUILDROOT_PACKAGES+=(ncurses-base ncurses-bin libncurses-dev gfortran cpio) fi From 85b98af95860b07676b4664cc143f9a0f2a8ded8 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 23 Jul 2024 02:00:11 -0700 Subject: [PATCH 133/219] Build testvectors with buildroot --- linux/Makefile | 4 ++-- linux/testvector-generation/genInitMem.sh | 22 +++++++++++----------- 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/linux/Makefile b/linux/Makefile index 6f7b6c7fb..06bc30752 100644 --- a/linux/Makefile +++ b/linux/Makefile @@ -29,9 +29,9 @@ OBJDUMPS := $(foreach name, $(OBJDUMPS), $(DIS)/$(name).objdump) .PHONY: all generate disassemble install clean cleanDTB cleanDriver test -all: clean download Image disassemble install +all: clean download Image disassemble install dumptvs -all_nosudo: clean download Image disassemble install_nosudo +all_nosudo: clean download Image disassemble install_nosudo dumptvs_nosudo Image: bash -c "unset LD_LIBRARY_PATH; make -C $(BUILDROOT) --jobs;" diff --git a/linux/testvector-generation/genInitMem.sh b/linux/testvector-generation/genInitMem.sh index b9c1d8c41..c4c3c7291 100755 --- a/linux/testvector-generation/genInitMem.sh +++ b/linux/testvector-generation/genInitMem.sh @@ -10,20 +10,20 @@ rawUntrimmedBootmemFile="$tvDir/untrimmedBootmemFileGDB.bin" untrimmedBootmemFile="$tvDir/untrimmedBootmemFile.bin" DEVICE_TREE=${imageDir}/wally-virt.dtb -if [ ! -d "$tvDir" ]; then - echo "Error: linux testvector directory $tvDir not found!">&2 - echo "Please create it. For example:">&2 - echo " sudo mkdir -p $tvDir">&2 +if ! mkdir -p "$tvDir"; then + echo "Error: unable to create linux testvector directory $tvDir!">&2 + echo "Please try running as sudo.">&2 exit 1 fi -test -w $tvDir -if [ ! $? -eq 0 ]; then - echo "Error: insuffcient write privileges for linux testvector directory $tvDir !">&2 - echo "Please chmod it. For example:">&2 - echo " sudo chmod -R a+rw $tvDir">&2 - exit 1 +if ! test -w "$tvDir"; then + echo "Using sudo to gain access to $tvDir" + if ! sudo chmod -R a+rw "$tvDir"; then + echo "Error: insuffcient write privileges for linux testvector directory $tvDir !">&2 + echo "Please chmod it. For example:">&2 + echo " sudo chmod -R a+rw $tvDir">&2 + exit 1 + fi fi - echo "Launching QEMU in replay mode!" (qemu-system-riscv64 \ -M virt -m 256M -dtb $DEVICE_TREE \ From e6b3257862a69006a408e27c6817fdc4c2e3f1f8 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 23 Jul 2024 18:39:25 -0700 Subject: [PATCH 134/219] Build nproc linux --- linux/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/linux/Makefile b/linux/Makefile index 06bc30752..89f31a3da 100644 --- a/linux/Makefile +++ b/linux/Makefile @@ -34,7 +34,7 @@ all: clean download Image disassemble install dumptvs all_nosudo: clean download Image disassemble install_nosudo dumptvs_nosudo Image: - bash -c "unset LD_LIBRARY_PATH; make -C $(BUILDROOT) --jobs;" + bash -c "unset LD_LIBRARY_PATH; make -C $(BUILDROOT) --jobs ${shell nproc --ignore 1};" $(MAKE) generate install: From 676c6b88a0f146d0e69b5a0b3a11f7441199f481 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 23 Jul 2024 22:57:53 -0700 Subject: [PATCH 135/219] Automatically determine number of threads to use in wally-tool-chain-install --- bin/wally-tool-chain-install.sh | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index cf86f0427..3b6903299 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -29,11 +29,8 @@ ## and limitations under the License. ################################################################################################ -# MODIFY FOR YOUR MACHINE # Increasing NUM_THREADS will speed up parallel compilation of the tools -#NUM_THREADS=2 # for low memory machines > 16GiB -NUM_THREADS=8 # for >= 32GiB -#NUM_THREADS=16 # for >= 64GiB +NUM_THREADS=$(nproc --ignore 1) # One less than the total number of threads # Colors BOLD='\033[1m' From a9cd457536d8e76aff7f0ddbc494d45dfcaf49d5 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 24 Jul 2024 00:22:28 -0700 Subject: [PATCH 136/219] Update buildroot makefile to test for write access to $RISCV and remove separate sudo/no_sudo versions (just run the makefile as sudo if needed) --- linux/Makefile | 28 ++++++++--------------- linux/testvector-generation/genInitMem.sh | 8 +------ 2 files changed, 11 insertions(+), 25 deletions(-) diff --git a/linux/Makefile b/linux/Makefile index 89f31a3da..a1c8999f1 100644 --- a/linux/Makefile +++ b/linux/Makefile @@ -1,4 +1,3 @@ -#BUILDROOT := ${RISCV}/buildroot-test BUILDROOT := buildroot IMAGES := ${BUILDROOT}/output/images WALLY := $(shell dirname $(shell pwd)) @@ -27,36 +26,29 @@ BINARIES := fw_jump.elf vmlinux busybox OBJDUMPS := $(foreach name, $(BINARIES), $(basename $(name) .elf)) OBJDUMPS := $(foreach name, $(OBJDUMPS), $(DIS)/$(name).objdump) -.PHONY: all generate disassemble install clean cleanDTB cleanDriver test +.PHONY: all generate disassemble install clean cleanDTB cleanDriver check_write_permissions -all: clean download Image disassemble install dumptvs +all: check_write_permissions clean download Image disassemble install dumptvs -all_nosudo: clean download Image disassemble install_nosudo dumptvs_nosudo +check_write_permissions: + @mkdir -p $(RISCV)/.test || \ + (echo "ERROR: Cannot write to '$(RISCV)'." \ + "Make sure you have write permissions (you may need to run as sudo).'" \ + && exit 1) + @rm -r $(RISCV)/.test Image: bash -c "unset LD_LIBRARY_PATH; make -C $(BUILDROOT) --jobs ${shell nproc --ignore 1};" $(MAKE) generate -install: - sudo rm -rf $(RISCV)/$(BUILDROOT) - sudo mv $(BUILDROOT) $(RISCV)/$(BUILDROOT) - -install_nosudo: +install: check_write_permissions rm -rf $(RISCV)/$(BUILDROOT) mv $(BUILDROOT) $(RISCV)/$(BUILDROOT) -dumptvs: - sudo mkdir -p $(RISCV)/linux-testvectors - cd testvector-generation; sudo ./genInitMem.sh - -dumptvs_nosudo: +dumptvs: check_write_permissions mkdir -p $(RISCV)/linux-testvectors cd testvector-generation; ./genInitMem.sh -# Temp rule for debugging -test: - echo $(shell find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/linux-[0-9]+\.[0-9]+\.[0-9]+$$") - generate: $(DTB) $(IMAGES) $(IMAGES)/%.dtb: ./devicetree/%.dts diff --git a/linux/testvector-generation/genInitMem.sh b/linux/testvector-generation/genInitMem.sh index c4c3c7291..61f570482 100755 --- a/linux/testvector-generation/genInitMem.sh +++ b/linux/testvector-generation/genInitMem.sh @@ -7,7 +7,6 @@ ramFile="$tvDir/ram.bin" rawBootmemFile="$tvDir/bootmemGDB.bin" bootmemFile="$tvDir/bootmem.bin" rawUntrimmedBootmemFile="$tvDir/untrimmedBootmemFileGDB.bin" -untrimmedBootmemFile="$tvDir/untrimmedBootmemFile.bin" DEVICE_TREE=${imageDir}/wally-virt.dtb if ! mkdir -p "$tvDir"; then @@ -24,6 +23,7 @@ if ! test -w "$tvDir"; then exit 1 fi fi + echo "Launching QEMU in replay mode!" (qemu-system-riscv64 \ -M virt -m 256M -dtb $DEVICE_TREE \ @@ -44,15 +44,10 @@ echo "Launching QEMU in replay mode!" -ex "kill" \ -ex "q" -#-ex "printf \"Warning - please verify that the second half of $rawUntrimmedBootmemFile is all 0s\n\"" \ -#-ex "printf \"Creating $rawUntrimmedBootmemFile\n\"" \ -#-ex "dump binary memory $rawUntrimmedBootmemFile 0x1000 0x2fff" \ - echo "Changing Endianness" make fixBinMem ./fixBinMem "$rawRamFile" "$ramFile" ./fixBinMem "$rawBootmemFile" "$bootmemFile" -#./fixBinMem "$rawUntrimmedBootmemFile" "$untrimmedBootmemFile" # doesn't seem to be used for anything rm -f "$rawRamFile" "$rawBootmemFile" "$rawUntrimmedBootmemFile" echo "genInitMem.sh completed!" @@ -60,4 +55,3 @@ echo "You may want to restrict write access to $tvDir now and give cad ownership echo "Run the following:" echo " sudo chown -R cad:cad $tvDir" echo " sudo chmod -R go-w $tvDir" - From 4b86f859046b31f3b2cc147476e760fb1a69eb8f Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 24 Jul 2024 01:09:12 -0700 Subject: [PATCH 137/219] Linux readme updates --- linux/Makefile | 5 ++--- linux/README.MD | 40 ++++++++++++++++------------------------ 2 files changed, 18 insertions(+), 27 deletions(-) diff --git a/linux/Makefile b/linux/Makefile index a1c8999f1..10c24defc 100644 --- a/linux/Makefile +++ b/linux/Makefile @@ -33,7 +33,7 @@ all: check_write_permissions clean download Image disassemble install dumptvs check_write_permissions: @mkdir -p $(RISCV)/.test || \ (echo "ERROR: Cannot write to '$(RISCV)'." \ - "Make sure you have write permissions (you may need to run as sudo).'" \ + "Make sure you have write permissions (you may need to run as sudo).'" >&2 \ && exit 1) @rm -r $(RISCV)/.test @@ -60,7 +60,7 @@ $(IMAGES): $(RISCV): @ echo "ERROR: No $(RISCV) directory. Make sure you have installed the Wally Toolchain." - @ echo "this can be done with /bin/wally-tool-chain-install.sh" + @ echo "and sourced setup.sh" # Disassembly rules --------------------------------------------------- @@ -93,7 +93,6 @@ $(IMAGES)/busybox: # Generating new Buildroot directories -------------------------------- -# This directive should be run as: make install BUILDROOT=path/to/buildroot download: $(BUILDROOT)/package/fpga-axi-sdc $(WALLYBOARD) cp $(WALLYBOARD)/main.config $(BUILDROOT)/.config diff --git a/linux/README.MD b/linux/README.MD index 2b9ec3ab3..e052df9ae 100644 --- a/linux/README.MD +++ b/linux/README.MD @@ -9,31 +9,25 @@ ## Setting up Buildroot -In order to generate the Linux and boot stage binaries compatible with Wally, Buildroot is used for cross-compilation. To set up a Buildroot directory, configuration files for Buildroot, Linux, and Busybox must be copied into the correct locations inside the main Buildroot directory. This can be done automatically using the Makefile inside Wally's Linux subdirectory (this one). To install and patch a fresh Buildroot directory, type: +In order to generate the Linux and boot stage binaries compatible with Wally, Buildroot is used for cross-compilation. - $ make install BUILDROOT=path/to/buildroot +To set up a Buildroot directory, configuration files for Buildroot, Linux, and Busybox must be copied into the correct locations inside the main Buildroot directory. Buildroot and device tree binaries must be generated as well. This can all be done automatically using the Makefile inside Wally's Linux subdirectory (this one). To install a new buildroot directory, build the Buildroot binaries, generate the device tree binaries, generate test-vectors for simulation, and install the buildroot package needed to build the SD card driver for Linux, run: -You can override the `BUILDROOT` variable to place buildroot where you want it. By default it will be placed at `/opt/riscv/buildroot`. In addition to copying the configuration files, it will install the buildroot package needed to build the SD card driver for Linux. - -To install a new buildroot directory, build the binaries, and generate the device tree binaries in one command, use: - - $ make BUILDROOT=path/to/buildroot - -Or simply use the default buildroot location in `/opt/riscv`: - $ make - -Note that the `$RISCV` variable cannot be set prior to building in buildroot or the build will fail. It is best to run `source ./setup.sh` to alter your `$PATH` and set the `$RISCV` variable after buildroot has succesfully built the binaries. If you're new to buildroot, you can find the binaries in `/output/images`. +This installs to the `$RISCV` directory. + +Optionally, you can override the `BUILDROOT` variable to use a different buildroot source directory. + + $ make install BUILDROOT=path/to/buildroot + ## Generating Device Tree Binaries -The device tree files for the various FPGA's Wally supports, as well as QEMU's device tree for the virt machine, are located in the `./devicetree` subdirectory. These device tree files are necessary for the boot process. In order to build the device tree binaries (.dtb) from the device tree sources (.dts), we can build all of them at once using: +The device tree files for the various FPGA's Wally supports, as well as QEMU's device tree for the virt machine, are located in the `./devicetree` subdirectory. These device tree files are necessary for the boot process. - $ make generate BUILDROOT=path/to/buildroot - - Or for the default buildroot location: - - $ make generate +They are built automatically using the main `make` command. To build the device tree binaries (.dtb) from the device tree sources (.dts) separately, we can build all of them at once using: + + $ make generate #optionally override BUILDROOT The .dts files will end up in the `/output/images` folder of your chosen buildroot directory. @@ -41,21 +35,19 @@ The .dts files will end up in the `/output/images` folder of your cho By using the `riscv64-unknown-elf-objdump` utility, we can disassemble the binaries in `/output/images` so that we can explore the resulting machine code instructions and see what assembly or C code the instructions came from, along with the corresponding addresses. This is useful during debugging in order to trace how code is being executed. -To create the disassembled binaries, run: +The disassembled binaries are built automatically using the main `make` command. To create the disassembled binaries separately, run: - $ make disassemble BUILDROOT=path/to/buildroot + $ make disassemble #optionally override BUILDROOT You'll find the resulting disassembled files in `/output/images/disassembly`. ## Creating a Bootable SD Card -To flash a bootable sd card for Wally's bootloader, use the `flash-sd.sh` script located in `/linux/sdcard`. The script allows you to specify which buildroot directory you would like to use and to specify the device tree. By default it is set up for the default location of buildroot in `/opt/riscv` and uses the vcu108 device tree. To use the script with your own buildroot directory and device tree, type: +To flash a bootable sd card for Wally's bootloader, use the `flash-sd.sh` script located in `/linux/sdcard`. The script allows you to specify which buildroot directory you would like to use and to specify the device tree. By default it is set up for the default location of buildroot in `$RISCV` and uses the vcu108 device tree. To use the script with your own buildroot directory and device tree, type: $ cd sdcard $ ./flash-sd.sh -b -d - for example +for example $ ./flash-sd.sh -b ~/repos/buildroot -d wally-vcu118.dtb /dev/sdb - - From 0107a400d175a06c653cfd824e83ef2f602d1836 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Wed, 24 Jul 2024 22:43:16 -0500 Subject: [PATCH 138/219] Added uart header to gpt.c. --- fpga/zsbl/gpt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/fpga/zsbl/gpt.c b/fpga/zsbl/gpt.c index 90948935b..c308ea878 100644 --- a/fpga/zsbl/gpt.c +++ b/fpga/zsbl/gpt.c @@ -1,5 +1,6 @@ #include "gpt.h" #include "boot.h" +#include "uart.h" #include /* PSUEDOCODE From 286d80de7e45c6cbb53b4dfacd37c202876e9c84 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Wed, 24 Jul 2024 22:43:47 -0500 Subject: [PATCH 139/219] Initialized UART with Arty frequency and baud rate. Will make this dynamic in the future --- fpga/zsbl/boot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/zsbl/boot.c b/fpga/zsbl/boot.c index 786879c49..e8065f732 100644 --- a/fpga/zsbl/boot.c +++ b/fpga/zsbl/boot.c @@ -96,7 +96,7 @@ void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) { int ret = 0; // Initialize UART for messages - init_uart(); + init_uart(20000000, 115200); // Print the wally banner print_uart(BANNER); From d15be492cb5cce505f04ef9c450915a8b668fb45 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Wed, 24 Jul 2024 22:44:27 -0500 Subject: [PATCH 140/219] Masked lower byte when writing to DLL. --- fpga/zsbl/uart.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/zsbl/uart.c b/fpga/zsbl/uart.c index be3270e28..7ff40e516 100644 --- a/fpga/zsbl/uart.c +++ b/fpga/zsbl/uart.c @@ -35,7 +35,7 @@ void init_uart(uint32_t freq, uint32_t baud) write_reg_u8(UART_IER, 0x00); // Disable all interrupts write_reg_u8(UART_LCR, 0x80); // Enable DLAB (set baud rate divisor) - write_reg_u8(UART_DLL, divisor); // divisor (lo byte) + write_reg_u8(UART_DLL, divisor & 0xFF); // divisor (lo byte) write_reg_u8(UART_DLM, (divisor >> 8) & 0xFF); // divisor (hi byte) write_reg_u8(UART_LCR, 0x03); // 8 bits, no parity, one stop bit write_reg_u8(UART_FCR, 0xC7); // Enable FIFO, clear them, with 14-byte threshold From 2caf9e93be6693a0ff45056b97ee003e83ab24c8 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Wed, 24 Jul 2024 22:46:24 -0500 Subject: [PATCH 141/219] Removed old axi IP from fpga Makefile. Added sed for data.mem file loaded into uncore ram. --- fpga/generator/Makefile | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile index df4ed0e2a..7865d33ee 100644 --- a/fpga/generator/Makefile +++ b/fpga/generator/Makefile @@ -1,14 +1,14 @@ dst := IP # vcu118 -#export XILINX_PART := xcvu9p-flga2104-2L-e -#export XILINX_BOARD := xilinx.com:vcu118:part0:2.4 -#export board := vcu118 +# export XILINX_PART := xcvu9p-flga2104-2L-e +# export XILINX_BOARD := xilinx.com:vcu118:part0:2.4 +# export board := vcu118 # vcu108 -#export XILINX_PART := xcvu095-ffva2104-2-e -#export XILINX_BOARD := xilinx.com:vcu108:part0:1.2 -#export board := vcu108 +# export XILINX_PART := xcvu095-ffva2104-2-e +# export XILINX_BOARD := xilinx.com:vcu108:part0:1.7 +# export board := vcu108 # Arty A7 export XILINX_PART := xc7a100tcsg324-1 @@ -40,11 +40,11 @@ IP_Arty: $(dst)/xlnx_proc_sys_reset.log \ $(dst)/xlnx_ddr3-$(board).log \ $(dst)/xlnx_mmcm.log \ $(dst)/xlnx_axi_clock_converter.log \ - $(dst)/xlnx_ahblite_axi_bridge.log \ - $(dst)/xlnx_axi_crossbar.log \ - $(dst)/xlnx_axi_dwidth_conv_32to64.log \ - $(dst)/xlnx_axi_dwidth_conv_64to32.log \ - $(dst)/xlnx_axi_prtcl_conv.log + $(dst)/xlnx_ahblite_axi_bridge.log +#$(dst)/xlnx_axi_crossbar.log \ +#$(dst)/xlnx_axi_dwidth_conv_32to64.log \ +#$(dst)/xlnx_axi_dwidth_conv_64to32.log \ +#$(dst)/xlnx_axi_prtcl_conv.log PreProcessFiles: @@ -59,6 +59,7 @@ PreProcessFiles: # This line allows the Bootloader to be loaded in a Block RAM on the FPGA sed -i "s/bit \[DATA_WIDTH-1:0\].*ROM.*/(\* rom_style=\"block\" \*) &/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv + sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/ram1p1rwbe.sv $(dst)/%.log: %.tcl mkdir -p IP From ebdf25a53b0936b04adcd9e17598acaed111e4bd Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Wed, 24 Jul 2024 22:47:15 -0500 Subject: [PATCH 142/219] Commented out references to old axi IP from wally.tcl. --- fpga/generator/wally.tcl | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index eff0a6cb9..9acdad4b6 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -27,10 +27,10 @@ read_ip IP/xlnx_proc_sys_reset.srcs/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_s read_ip IP/xlnx_ahblite_axi_bridge.srcs/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge.xci read_ip IP/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter.xci # Added crossbar - Jacob Pease <2023-01-12 Thu> -read_ip IP/xlnx_axi_crossbar.srcs/sources_1/ip/xlnx_axi_crossbar/xlnx_axi_crossbar.xci -read_ip IP/xlnx_axi_dwidth_conv_32to64.srcs/sources_1/ip/xlnx_axi_dwidth_conv_32to64/xlnx_axi_dwidth_conv_32to64.xci -read_ip IP/xlnx_axi_dwidth_conv_64to32.srcs/sources_1/ip/xlnx_axi_dwidth_conv_64to32/xlnx_axi_dwidth_conv_64to32.xci -read_ip IP/xlnx_axi_prtcl_conv.srcs/sources_1/ip/xlnx_axi_prtcl_conv/xlnx_axi_prtcl_conv.xci +#read_ip IP/xlnx_axi_crossbar.srcs/sources_1/ip/xlnx_axi_crossbar/xlnx_axi_crossbar.xci +#read_ip IP/xlnx_axi_dwidth_conv_32to64.srcs/sources_1/ip/xlnx_axi_dwidth_conv_32to64/xlnx_axi_dwidth_conv_32to64.xci +#read_ip IP/xlnx_axi_dwidth_conv_64to32.srcs/sources_1/ip/xlnx_axi_dwidth_conv_64to32/xlnx_axi_dwidth_conv_64to32.xci +#read_ip IP/xlnx_axi_prtcl_conv.srcs/sources_1/ip/xlnx_axi_prtcl_conv/xlnx_axi_prtcl_conv.xci if {$board=="ArtyA7"} { read_ip IP/xlnx_ddr3.srcs/sources_1/ip/xlnx_ddr3/xlnx_ddr3.xci @@ -89,8 +89,8 @@ report_clock_interaction -file re write_verilog -force -mode funcsim sim/syn-funcsim.v if {$board=="ArtyA7"} { - source ../constraints/small-debug.xdc - + #source ../constraints/small-debug.xdc + source ../constraints/medium-debug.xdc } else { # source ../constraints/vcu-small-debug.xdc source ../constraints/debug6.xdc From 0dae881a0dadd83d9bb5a5a139819be9664f618d Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Wed, 24 Jul 2024 22:48:31 -0500 Subject: [PATCH 143/219] Fixed SDCCLK name discrepency. --- fpga/constraints/constraints-ArtyA7.xdc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/constraints/constraints-ArtyA7.xdc b/fpga/constraints/constraints-ArtyA7.xdc index f466b0c30..4e156601b 100644 --- a/fpga/constraints/constraints-ArtyA7.xdc +++ b/fpga/constraints/constraints-ArtyA7.xdc @@ -101,7 +101,7 @@ set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33 PULLUP true} [get_ports { set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[2]}] set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[1]}] set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[0]}] -set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCClk}] +set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCLK}] set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCmd}] set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCD}] From f7dd49cc6cef8f075f8dc5ceabf1d913f07caad8 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 25 Jul 2024 06:59:58 -0700 Subject: [PATCH 144/219] Issue #894: trap on floating-point ops with reserved rounding modes --- src/fpu/fctrl.sv | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index 8595fd29e..eed90ddcf 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -81,6 +81,7 @@ module fctrl import cvw::*; #(parameter cvw_t P) ( logic [1:0] Fmt, Fmt2; // format - before possible reduction logic SupportedFmt; // is the format supported logic SupportedFmt2; // is the source format supported for fp -> fp + logic SupportedRM; // is the rounding mode supported logic FCvtIntD, FCvtIntM; // convert to integer operation logic ZfaD; // Zfa variants of instructions logic ZfaFRoundNXD; // Zfa froundnx instruction @@ -93,14 +94,16 @@ module fctrl import cvw::*; #(parameter cvw_t P) ( (Fmt == 2'b10 & P.ZFH_SUPPORTED) | (Fmt == 2'b11 & P.Q_SUPPORTED)); assign SupportedFmt2 = (Fmt2 == 2'b00 | (Fmt2 == 2'b01 & P.D_SUPPORTED) | (Fmt2 == 2'b10 & P.ZFH_SUPPORTED) | (Fmt2 == 2'b11 & P.Q_SUPPORTED)); + // rounding modes 5 and 6 are reserved. Rounding mode 7 is dynamic, and is reserved if FRM is 5, 6, or 7 + assign SupportedRM = ~(Funct3D == 3'b101 | Funct3D == 3'b110 | (Funct3D == 3'b111 & (FRM_REGW == 3'b101 | FRM_REGW == 3'b110 | FRM_REGW == 3'b111))); // decode the instruction // FRegWrite_FWriteInt_FResSel_PostProcSel_FOpCtrl_FDivStart_IllegalFPUInstr_FCvtInt_Zfa_FroundNX always_comb if (STATUS_FS == 2'b00) // FPU instructions are illegal when FPU is disabled ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0_0_0; - else if (OpD != 7'b0000111 & OpD != 7'b0100111 & ~SupportedFmt) - ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0_0_0; // for anything other than loads and stores, check for supported format + else if (OpD != 7'b0000111 & OpD != 7'b0100111 & (~SupportedFmt | ~SupportedRM)) + ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0_0_0; // for anything other than loads and stores, check for supported format and rounding mode else begin ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0_0_0; // default: non-implemented instruction /* verilator lint_off CASEINCOMPLETE */ // default value above has priority so no other default needed From 5bf7250687ddde2fb31062a2182921cab81c3a96 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 25 Jul 2024 09:09:13 -0700 Subject: [PATCH 145/219] Issue #894: trap on floating-point ops with reserved rounding modes: detect Zfa flt --- src/fpu/fctrl.sv | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index eed90ddcf..ab9cad093 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -95,8 +95,11 @@ module fctrl import cvw::*; #(parameter cvw_t P) ( assign SupportedFmt2 = (Fmt2 == 2'b00 | (Fmt2 == 2'b01 & P.D_SUPPORTED) | (Fmt2 == 2'b10 & P.ZFH_SUPPORTED) | (Fmt2 == 2'b11 & P.Q_SUPPORTED)); // rounding modes 5 and 6 are reserved. Rounding mode 7 is dynamic, and is reserved if FRM is 5, 6, or 7 - assign SupportedRM = ~(Funct3D == 3'b101 | Funct3D == 3'b110 | (Funct3D == 3'b111 & (FRM_REGW == 3'b101 | FRM_REGW == 3'b110 | FRM_REGW == 3'b111))); - + assign SupportedRM = ~(Funct3D == 3'b101 | Funct3D == 3'b110 | (Funct3D == 3'b111 & (FRM_REGW == 3'b101 | FRM_REGW == 3'b110 | FRM_REGW == 3'b111))) | + (OpD == 7'b1010011 & Funct3D == 3'b101 & Funct7D[6:2] == 5'b10100 & P.ZFA_SUPPORTED); // Zfa fltq has a funny rounding mode + /*assign SupportedRM = ~(Funct3D == 3'b101 | Funct3D == 3'b110 | (Funct3D == 3'b111 & (FRM_REGW == 3'b101 | FRM_REGW == 3'b110 | FRM_REGW == 3'b111))) | + (OpD == 7'b1010011 & P.ZFA_SUPPORTED); +*/ // decode the instruction // FRegWrite_FWriteInt_FResSel_PostProcSel_FOpCtrl_FDivStart_IllegalFPUInstr_FCvtInt_Zfa_FroundNX always_comb From 336a413f3185b089223a75d3b1d43e8f12465611 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Thu, 25 Jul 2024 11:19:15 -0500 Subject: [PATCH 146/219] Added ability to split boot.memfile into boot.mem and data.mem. --- fpga/zsbl/Makefile | 9 ++++++-- src/generic/mem/ram1p1rwbe.sv | 23 +++++++++++++++++---- src/uncore/uncore.sv | 10 ++++----- testbench/testbench.sv | 39 ++++++++++++++++++++++++++++------- 4 files changed, 63 insertions(+), 18 deletions(-) diff --git a/fpga/zsbl/Makefile b/fpga/zsbl/Makefile index 37323b813..85bfc67eb 100644 --- a/fpga/zsbl/Makefile +++ b/fpga/zsbl/Makefile @@ -17,6 +17,7 @@ OBJECTS := $(patsubst $(SRCDIR)/%,$(BUILDDIR)/%,$(OBJECTS)) TARGETDIR := bin TARGET := $(TARGETDIR)/boot +MEMFILES := $(TARGETDIR/boot.mem $(TARGETDIR)/data.mem ROOT := .. LIBRARY_DIRS := LIBRARY_FILES := @@ -37,7 +38,7 @@ AR=riscv64-unknown-elf-ar #Default Make -all: directories $(TARGET).memfile +all: directories $(TARGET).memfile #Remake remake: clean all @@ -48,7 +49,7 @@ directories: @mkdir -p $(BUILDDIR) clean: - rm -rf $(BUILDDIR) $(TARGETDIR) *.memfile *.objdump + rm -rf $(BUILDDIR) $(TARGETDIR) *.memfile *.objdump boot.mem data.mem #Needed for building additional library projects @@ -112,3 +113,7 @@ $(TARGET).memfile: $(TARGET) extractFunctionRadix.sh $<.objdump mkdir -p ../../imperas-riscv-tests/work/rv64BP/ cp -f $(TARGETDIR)/* ../../imperas-riscv-tests/work/rv64BP/ + @echo 'Splitting memfile.' + ./splitfile.sh $@ + mv boot.mem ../src/boot.mem + mv data.mem ../src/data.mem diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index d333048b7..e2e76288b 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -83,11 +83,26 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE end else begin: ram bit [WIDTH-1:0] RAM[DEPTH-1:0]; - if (PRELOAD_ENABLED) begin - initial begin - RAM[0] = 64'h00600100d2e3ca40; + // if (PRELOAD_ENABLED) begin + // initial begin + // RAM[0] = 64'h00600100d2e3ca40; + // end + // end + + initial + if (PRELOAD_ENABLED) begin + if (WIDTH == 64) begin + `ifdef VERILATOR + // because Verilator doesn't automatically accept $WALLY from shell + string WALLY_DIR = getenvval("WALLY"); + $readmemh({WALLY_DIR,"/fpga/src/data.mem"}, RAM, 0); // load boot ROM for FPGA + `else + $readmemh({"$WALLY/fpga/src/data.mem"}, RAM, 0); // load boot ROM for FPGA + `endif + end else begin // put something in the ROM so it is not optimized away + RAM[0] = 'h00002197; + end end - end // Combinational read: register address and read after clock edge logic [$clog2(DEPTH)-1:0] addrd; diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index c3414352f..7de407c63 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -78,13 +78,13 @@ module uncore import cvw::*; #(parameter cvw_t P)( logic SDCIntM; logic PCLK, PRESETn, PWRITE, PENABLE; - logic [4:0] PSEL; + logic [5:0] PSEL; logic [31:0] PADDR; logic [P.XLEN-1:0] PWDATA; logic [P.XLEN/8-1:0] PSTRB; /* verilator lint_off UNDRIVEN */ // undriven in rv32e configuration - logic [4:0] PREADY; - logic [4:0][P.XLEN-1:0] PRDATA; + logic [5:0] PREADY; + logic [5:0][P.XLEN-1:0] PRDATA; /* verilator lint_on UNDRIVEN */ logic [P.XLEN-1:0] HREADBRIDGE; logic HRESPBRIDGE, HREADYBRIDGE, HSELBRIDGE, HSELBRIDGED; @@ -102,7 +102,7 @@ module uncore import cvw::*; #(parameter cvw_t P)( // AHB -> APB bridge ahbapbbridge #(P, 6) ahbapbbridge ( - .HCLK, .HRESETn, .HSEL({HSELSPI, HSELUART, HSELPLIC, HSELCLINT, HSELGPIO, HSELSDC}), .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HTRANS, .HREADY, + .HCLK, .HRESETn, .HSEL({HSELSDC, HSELSPI, HSELUART, HSELPLIC, HSELCLINT, HSELGPIO}), .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HTRANS, .HREADY, .HRDATA(HREADBRIDGE), .HRESP(HRESPBRIDGE), .HREADYOUT(HREADYBRIDGE), .PCLK, .PRESETn, .PSEL, .PWRITE, .PENABLE, .PADDR, .PWDATA, .PSTRB, .PREADY, .PRDATA); assign HSELBRIDGE = HSELGPIO | HSELCLINT | HSELPLIC | HSELUART | HSELSPI | HSELSDC; // if any of the bridge signals are selected @@ -172,7 +172,7 @@ module uncore import cvw::*; #(parameter cvw_t P)( .PREADY(PREADY[5]), .PRDATA(PRDATA[5]), .SPIOut(SDCCmd), .SPIIn(SDCIn), .SPICS(SDCCS), .SPICLK(SDCCLK), .SPIIntr(SDCIntr)); end else begin : sdc - assign SDCCmd = '0; assign SDCCD = 1'b0; assign SDCIntr = 1'b0; assign SDCCLK = 1'b0; + assign SDCCmd = '0; assign SDCCS = 1'b0; assign SDCIntr = 1'b0; assign SDCCLK = 1'b0; end diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 3bf8f1a2e..c8e659670 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -76,8 +76,7 @@ module testbench; // DUT signals logic [P.AHBW-1:0] HRDATAEXT; - logic HREADYEXT, HRESPEXT; - logic HSELEXTSDC; + logic HREADYEXT, HRESPEXT; logic [P.PA_BITS-1:0] HADDR; logic [P.AHBW-1:0] HWDATA; logic [P.XLEN/8-1:0] HWSTRB; @@ -93,7 +92,11 @@ module testbench; logic UARTSin, UARTSout; logic SPIIn, SPIOut; logic [3:0] SPICS; - logic SDCIntr; + logic SPICLK; + logic SDCCmd; + logic SDCIn; + logic [3:0] SDCCS; + logic SDCCLK; logic HREADY; logic HSELEXT; @@ -371,6 +374,11 @@ module testbench; uartoutfile = $fopen(uartoutfilename, "w"); // delete UART output file ProgramAddrMapFile = {RISCV_DIR, "/buildroot/output/images/disassembly/vmlinux.objdump.addr"}; ProgramLabelMapFile = {RISCV_DIR, "/buildroot/output/images/disassembly/vmlinux.objdump.lab"}; + end else if(TEST == "fpga") begin + bootmemfilename = {WALLY_DIR, "/fpga/src/boot.mem"}; + memfilename = {WALLY_DIR, "/fpga/src/data.mem"}; + ProgramAddrMapFile = {WALLY_DIR, "/fpga/zsbl/bin/boot.objdump.addr"}; + ProgramLabelMapFile = {WALLY_DIR, "/fpga/zsbl/bin/boot.objdump.lab"}; end else if(ElfFile != "none") begin elffilename = ElfFile; memfilename = {ElfFile, ".memfile"}; @@ -505,6 +513,23 @@ module testbench; end readResult = $fread(dut.uncoregen.uncore.ram.ram.memory.ram.RAM, memFile); $fclose(memFile); + end else if (TEST == "fpga") begin + memFile = $fopen(bootmemfilename, "rb"); + if (memFile == 0) begin + $display("Error: Could not open file %s", memfilename); + $finish; + end + if (P.BOOTROM_SUPPORTED) begin + readResult = $fread(dut.uncoregen.uncore.bootrom.bootrom.memory.ROM, memFile); + end + $fclose(memFile); + memFile = $fopen(memfilename, "rb"); + if (memFile == 0) begin + $display("Error: Could not open file %s", memfilename); + $finish; + end + readResult = $fread(dut.uncoregen.uncore.ram.ram.memory.ram.RAM, memFile); + $fclose(memFile); end else begin uncoreMemFile = $fopen(memfilename, "r"); // Is there a better way to test if a file exists? if (uncoreMemFile == 0) begin @@ -584,15 +609,15 @@ module testbench; assign SDCDat = sd_dat_reg_t ? sd_dat_reg_o : sd_dat_i; assign SDCDatIn = SDCDat; -----/\----- EXCLUDED -----/\----- */ - assign SDCIntr = 1'b0; end else begin - assign SDCIntr = 1'b0; + assign SDCIn = 1'b1; + end - wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC, + wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, - .UARTSin, .UARTSout, .SDCIntr, .SPIIn, .SPIOut, .SPICS); + .UARTSin, .UARTSout, .SPIIn, .SPIOut, .SPICS, .SPICLK, .SDCIn, .SDCCmd, .SDCCS, .SDCCLK); // generate clock to sequence tests always begin From d5af25ffbf03b27c336468ed19e24296254aa96c Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 25 Jul 2024 09:19:23 -0700 Subject: [PATCH 147/219] CHeck legal rnum field when decoding aes64ks1i --- src/ieu/bmu/bmuctrl.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index d482616ef..d4a8afe23 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -238,7 +238,7 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) ( if ((P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED) & P.XLEN == 64) begin // ZKND and ZKNE shared instructions casez({OpD, Funct7D, Funct3D}) - 17'b0010011_0011000_001: if (Rs2D[4] == 1'b1) + 17'b0010011_0011000_001: if (Rs2D[4] == 1'b1 & $unsigned(Rs2D[3:0]) <= 10) BMUControlsD = `BMUCTRLW'b000_0111_0010_1_0_0_0_1_0_0_0_0_0; // aes64ks1i - key schedule istr1 17'b0110011_0111111_000: BMUControlsD = `BMUCTRLW'b000_0111_0011_1_0_0_0_1_0_0_0_0_0; // aes64ks2 - key schedule istr2 endcase From faa13789201fa202e5b83d26e857c2f0de1b6210 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 25 Jul 2024 09:43:54 -0700 Subject: [PATCH 148/219] Legalized PMPconfig WARL --- src/privileged/csrm.sv | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index f86b3f6d6..24132ab93 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -106,7 +106,10 @@ module csrm import cvw::*; #(parameter cvw_t P) ( genvar i; if (P.PMP_ENTRIES > 0) begin:pmp logic [P.PMP_ENTRIES-1:0] WritePMPCFGM; - logic [P.PMP_ENTRIES-1:0] WritePMPADDRM ; + logic [P.PMP_ENTRIES-1:0] WritePMPADDRM; + logic [7:0] CSRPMPWriteValM[P.PMP_ENTRIES-1:0]; + logic [7:0] CSRPMPLegalizedWriteValM[P.PMP_ENTRIES-1:0]; + logic [1:0] CSRPMPWRLegalizedWriteValM[P.PMP_ENTRIES-1:0]; logic [P.PMP_ENTRIES-1:0] ADDRLocked, CFGLocked; for(i=0; i Date: Thu, 25 Jul 2024 10:08:34 -0700 Subject: [PATCH 149/219] Updated ImperasTG derived config to turn off peripherals --- config/derivlist.txt | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/config/derivlist.txt b/config/derivlist.txt index 1edd20b7b..c689d2cb9 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -1657,7 +1657,7 @@ IDIV_ON_FPU 1 # imperas used for a smart memory # VCS doesn't like removing the bootrom, but make it tiny in a random unused location -derive imperas rv64gc +derive ImperasTG rv64gc ICACHE_SUPPORTED 0 DCACHE_SUPPORTED 0 VIRTMEM_SUPPORTED 0 @@ -1668,6 +1668,13 @@ ZICBOM_SUPPORTED 0 ZICBOZ_SUPPORTED 0 SVPBMT_SUPPORTED 0 SVNAPOT_SUPPORTED 0 -BOOTROM_BASE 64'h700012340010 +BOOTROM_BASE 64'h700012340080 BOOTROM_RANGE 64'h10 +CLINT_SUPPORTED 0 +GPIO_SUPPORTED 0 +UART_SUPPORTED 0 +PLIC_SUPPORTED 0 +SPI_SUPPORTED 0 + + From a36e846b0251f533ba2988da6ca2d95ce17b6e17 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Thu, 25 Jul 2024 13:04:27 -0500 Subject: [PATCH 150/219] Changed formatting and added new UART divsor calculation from OpenSBI. --- fpga/zsbl/uart.c | 91 ++++++++++++++++++++++++------------------------ 1 file changed, 45 insertions(+), 46 deletions(-) diff --git a/fpga/zsbl/uart.c b/fpga/zsbl/uart.c index 7ff40e516..1330bc1d9 100644 --- a/fpga/zsbl/uart.c +++ b/fpga/zsbl/uart.c @@ -3,94 +3,93 @@ void write_reg_u8(uintptr_t addr, uint8_t value) { - volatile uint8_t *loc_addr = (volatile uint8_t *)addr; - *loc_addr = value; + volatile uint8_t *loc_addr = (volatile uint8_t *)addr; + *loc_addr = value; } uint8_t read_reg_u8(uintptr_t addr) { - return *(volatile uint8_t *)addr; + return *(volatile uint8_t *)addr; } int is_transmit_empty() { - return read_reg_u8(UART_LSR) & 0x20; + return read_reg_u8(UART_LSR) & 0x20; } int is_receive_empty() { - return !(read_reg_u8(UART_LSR) & 0x1); + return !(read_reg_u8(UART_LSR) & 0x1); } void write_serial(char a) { - while (is_transmit_empty() == 0) {}; + while (is_transmit_empty() == 0) {}; - write_reg_u8(UART_THR, a); + write_reg_u8(UART_THR, a); } void init_uart(uint32_t freq, uint32_t baud) { - uint32_t divisor = freq / (baud << 4); + // Alternative divisor calculation. From OpenSBI code. + // Reduces error for every possible frequency. + uint32_t divisor = (freq + 8 * baud) /(baud << 4); - write_reg_u8(UART_IER, 0x00); // Disable all interrupts - write_reg_u8(UART_LCR, 0x80); // Enable DLAB (set baud rate divisor) - write_reg_u8(UART_DLL, divisor & 0xFF); // divisor (lo byte) - write_reg_u8(UART_DLM, (divisor >> 8) & 0xFF); // divisor (hi byte) - write_reg_u8(UART_LCR, 0x03); // 8 bits, no parity, one stop bit - write_reg_u8(UART_FCR, 0xC7); // Enable FIFO, clear them, with 14-byte threshold + write_reg_u8(UART_IER, 0x00); // Disable all interrupts + write_reg_u8(UART_LCR, 0x80); // Enable DLAB (set baud rate divisor) + write_reg_u8(UART_DLL, divisor & 0xFF); // divisor (lo byte) + write_reg_u8(UART_DLM, (divisor >> 8) & 0xFF); // divisor (hi byte) + write_reg_u8(UART_LCR, 0x03); // 8 bits, no parity, one stop bit + write_reg_u8(UART_FCR, 0xC7); // Enable FIFO, clear them, with 14-byte threshold } void print_uart(const char *str) { - const char *cur = &str[0]; - while (*cur != '\0') - { - write_serial((uint8_t)*cur); - ++cur; - } + const char *cur = &str[0]; + while (*cur != '\0') { + write_serial((uint8_t)*cur); + ++cur; + } } uint8_t bin_to_hex_table[16] = { - '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F'}; + '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F'}; void bin_to_hex(uint8_t inp, uint8_t res[2]) { - res[1] = bin_to_hex_table[inp & 0xf]; - res[0] = bin_to_hex_table[(inp >> 4) & 0xf]; - return; + res[1] = bin_to_hex_table[inp & 0xf]; + res[0] = bin_to_hex_table[(inp >> 4) & 0xf]; + return; } void print_uart_int(uint32_t addr) { - int i; - for (i = 3; i > -1; i--) - { - uint8_t cur = (addr >> (i * 8)) & 0xff; - uint8_t hex[2]; - bin_to_hex(cur, hex); - write_serial(hex[0]); - write_serial(hex[1]); - } + int i; + for (i = 3; i > -1; i--) { + uint8_t cur = (addr >> (i * 8)) & 0xff; + uint8_t hex[2]; + bin_to_hex(cur, hex); + write_serial(hex[0]); + write_serial(hex[1]); + } } void print_uart_addr(uint64_t addr) { - int i; - for (i = 7; i > -1; i--) - { - uint8_t cur = (addr >> (i * 8)) & 0xff; - uint8_t hex[2]; - bin_to_hex(cur, hex); - write_serial(hex[0]); - write_serial(hex[1]); - } + int i; + for (i = 7; i > -1; i--) { + uint8_t cur = (addr >> (i * 8)) & 0xff; + uint8_t hex[2]; + bin_to_hex(cur, hex); + write_serial(hex[0]); + write_serial(hex[1]); + } } void print_uart_byte(uint8_t byte) { - uint8_t hex[2]; - bin_to_hex(byte, hex); - write_serial(hex[0]); - write_serial(hex[1]); + uint8_t hex[2]; + bin_to_hex(byte, hex); + write_serial(hex[0]); + write_serial(hex[1]); } From 3975f60299c18bfb4f5fce2be64d552f3752c3d2 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Thu, 25 Jul 2024 13:05:57 -0500 Subject: [PATCH 151/219] Added carriage returns to line feed characters. UART messages print properly now. --- fpga/zsbl/boot.c | 5 ++++- fpga/zsbl/boot.h | 18 +++++++++--------- fpga/zsbl/gpt.c | 6 +++--- fpga/zsbl/sd.c | 4 ++-- 4 files changed, 18 insertions(+), 15 deletions(-) diff --git a/fpga/zsbl/boot.c b/fpga/zsbl/boot.c index e8065f732..5b022cea3 100644 --- a/fpga/zsbl/boot.c +++ b/fpga/zsbl/boot.c @@ -49,6 +49,7 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) { if (sd_cmd(18, sector & 0xffffffff, crc) != 0x00) { print_uart("disk_read: CMD18 failed. r = "); print_uart_byte(r & 0xff); + print_uart("\r\n"); return -1; } @@ -61,6 +62,7 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) { if (r != SD_DATA_TOKEN) { print_uart("Didn't receive data token first thing. Shoot: "); print_uart_byte(r & 0xff); + print_uart("\r\n"); return -1; } @@ -97,7 +99,8 @@ void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) { // Initialize UART for messages init_uart(20000000, 115200); - + + print_uart("Booting wally.\r\n"); // Print the wally banner print_uart(BANNER); diff --git a/fpga/zsbl/boot.h b/fpga/zsbl/boot.h index 2048ca47c..087550326 100644 --- a/fpga/zsbl/boot.h +++ b/fpga/zsbl/boot.h @@ -19,15 +19,15 @@ typedef QWORD LBA_t; #define OPENSBI_ADDRESS 0x80000000 // FW_TEXT_START #define KERNEL_ADDRESS 0x80200000 // FW_JUMP_ADDR -#define BANNER " █▀█ █▀█ █▀█ █▀▀ █ █\n" \ -" █ █ █ █▄▀ █▄▄ ▄▄▄ █ █\n" \ -" █▄█ █▄█ █ █ █▄▄ ▀▄▀\n" \ -" ____ ____ ____ ___ ___ ____ ___\n" \ -" \\ \\ / / / \\ | | | | \\ \\ / /\n" \ -" \\ \\ __ / / / \\ | | | | \\ \\/ /\n" \ -" \\ \\/ \\/ / / /\\ \\ | | | | \\ /\n" \ -" \\ / / ____ \\ | |___ | |___ | |\n" \ -" \\___/\\___/ /___/ \\___\\|_______||_______| |___|\n\n" +#define BANNER " █▀█ █▀█ █▀█ █▀▀ █ █\r\n" \ +" █ █ █ █▄▀ █▄▄ ▄▄▄ █ █\r\n" \ +" █▄█ █▄█ █ █ █▄▄ ▀▄▀\r\n" \ +" ____ ____ ____ ___ ___ ____ ___\r\n" \ +" \\ \\ / / / \\ | | | | \\ \\ / /\r\n" \ +" \\ \\ __ / / / \\ | | | | \\ \\/ /\r\n" \ +" \\ \\/ \\/ / / /\\ \\ | | | | \\ /\r\n" \ +" \\ / / ____ \\ | |___ | |___ | |\r\n" \ +" \\___/\\___/ /___/ \\___\\|_______||_______| |___|\r\n\r\n" // Export disk_read int disk_read(BYTE * buf, LBA_t sector, UINT count); diff --git a/fpga/zsbl/gpt.c b/fpga/zsbl/gpt.c index c308ea878..a52dc9048 100644 --- a/fpga/zsbl/gpt.c +++ b/fpga/zsbl/gpt.c @@ -42,21 +42,21 @@ int gpt_load_partitions() { // Load device tree ret = disk_read((BYTE *)FDT_ADDRESS, fdt->first_lba, fdt->last_lba - fdt->first_lba + 1); if (ret < 0) { - print_uart("Failed to load device tree!"); + print_uart("Failed to load device tree!\r\n"); return -1; } // Load OpenSBI ret = disk_read((BYTE *)OPENSBI_ADDRESS, opensbi->first_lba, opensbi->last_lba - opensbi->first_lba + 1); if (ret < 0) { - print_uart("Failed to load OpenSBI!"); + print_uart("Failed to load OpenSBI!\r\n"); return -1; } // Load Linux ret = disk_read((BYTE *)KERNEL_ADDRESS, kernel->first_lba,kernel->last_lba - kernel->first_lba + 1); if (ret < 0) { - print_uart("Failed to load Linux!"); + print_uart("Failed to load Linux!\r\n"); return -1; } diff --git a/fpga/zsbl/sd.c b/fpga/zsbl/sd.c index 585b98281..02ee4d3bf 100644 --- a/fpga/zsbl/sd.c +++ b/fpga/zsbl/sd.c @@ -133,7 +133,7 @@ void init_sd(){ uint64_t r; - print_uart("Initializing SD Card in SPI mode"); + print_uart("Initializing SD Card in SPI mode.\r\n"); // Reset SD Card command // Initializes SD card into SPI mode if CS is asserted '0' @@ -155,6 +155,6 @@ void init_sd(){ r = ACMD41(); } while (r == 0x1); - print_uart("SD card is initialized"); + print_uart("SD card is initialized.\n\r"); } From 22d20770063843a2390bb9cf256cc973b8f7cd36 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 25 Jul 2024 21:16:00 -0700 Subject: [PATCH 152/219] Cleanup --- bin/wally-distro-check.sh | 4 ++-- bin/wally-package-install.sh | 4 ++-- bin/wally-tool-chain-install.sh | 10 ++++------ 3 files changed, 8 insertions(+), 10 deletions(-) diff --git a/bin/wally-distro-check.sh b/bin/wally-distro-check.sh index 73eb58fba..92d284b05 100755 --- a/bin/wally-distro-check.sh +++ b/bin/wally-distro-check.sh @@ -62,7 +62,7 @@ if [[ "$ID" == rhel || "$ID_LIKE" == *rhel* ]]; then export FAMILY=rhel if [ "$ID" != rhel ] && [ "$ID" != rocky ] && [ "$ID" != almalinux ]; then printf "${WARNING_COLOR}%s\n${ENDC}" "For Red Hat family distros, the Wally install script has only been tested on RHEL, Rocky Linux," \ - " and AlmaLinux. Your distro is $PRETTY_NAME. The regular Red Hat install will be attempted, but there will likely be issues." + " and AlmaLinux. Your distro is $PRETTY_NAME. The regular Red Hat install will be attempted, but there may be issues." fi export RHEL_VERSION="${VERSION_ID:0:1}" if (( RHEL_VERSION < 8 )); then @@ -77,7 +77,7 @@ elif [[ "$ID" == ubuntu || "$ID_LIKE" == *ubuntu* ]]; then fi export UBUNTU_VERSION="${VERSION_ID:0:2}" if (( UBUNTU_VERSION < 20 )); then - echo "${FAIL_COLOR}The Wally install script is only compatible with versions 20.04, 22.04, and 24.04 of Ubuntu. You have version $VERSION.${ENDC}" + echo "${FAIL_COLOR}The Wally install script has only been tested with versions 20.04 LTS, 22.04 LTS, and 24.04 LTS of Ubuntu. You have version $VERSION.${ENDC}" exit 1 fi else diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index c2a3bb1aa..ed0de2ced 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -54,7 +54,7 @@ if [ "$FAMILY" == rhel ]; then QEMU_PACKAGES+=(glib2-devel libfdt-devel pixman-devel bzip2 ninja-build) SPIKE_PACKAGES+=(dtc boost-regex boost-system) VERILATOR_PACKAGES+=(help2man perl clang ccache gperftools numactl mold) - BUILDROOT_PACKAGES+=(ncurses-base ncurses ncurses-libs ncurses-devel gcc-gfortran cpio) + BUILDROOT_PACKAGES+=(ncurses-base ncurses ncurses-libs ncurses-devel gcc-gfortran cpio) # gfortran is only needed for compiling spec benchmarks on buildroot linux # Extra packages not availale in rhel8, nice for Verilator and needed for sail respectively if (( RHEL_VERSION >= 9 )); then VERILATOR_PACKAGES+=(perl-doc) @@ -81,7 +81,7 @@ elif [ "$FAMILY" == ubuntu ]; then SPIKE_PACKAGES+=(device-tree-compiler libboost-regex-dev libboost-system-dev) VERILATOR_PACKAGES+=(help2man perl g++ clang ccache libunwind-dev libgoogle-perftools-dev numactl perl-doc libfl2 libfl-dev zlib1g) SAIL_PACKAGES+=(opam z3) - BUILDROOT_PACKAGES+=(ncurses-base ncurses-bin libncurses-dev gfortran cpio) + BUILDROOT_PACKAGES+=(ncurses-base ncurses-bin libncurses-dev gfortran cpio) # gfortran is only needed for compiling spec benchmarks on buildroot linux fi diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 3b6903299..6b92581ce 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -159,7 +159,7 @@ echo -e "${SUCCESS_COLOR}Python environment successfully configured.${ENDC}" # Extra dependecies needed for older distros that don't have new enough versions available from package manager if (( RHEL_VERSION == 8 )) || (( UBUNTU_VERSION == 20 )); then - # Newer versin of glib required for Qemu. + # Newer versin of glib required for QEMU. # Anything newer than this won't build on red hat 8 STATUS="glib" if [ ! -e "$RISCV"/include/glib-2.0 ]; then @@ -211,8 +211,7 @@ cd "$RISCV" if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2"; then cd riscv-gnu-toolchain git reset --hard && git clean -f && git checkout master && git pull - git pull - ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" + ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" make -j ${NUM_THREADS} 2>&1 | logger riscv-gnu-toolchain; [ "${PIPESTATUS[0]}" == 0 ] if [ "$clean" ]; then cd "$RISCV" @@ -321,10 +320,9 @@ else echo -e "${SUCCESS_COLOR}Verilator already up to date${ENDC}" fi - +# Install opam from binary disribution on rhel as it is not available from dnf +# Opam is needed to install the sail compiler if [ "$FAMILY" == rhel ]; then - # Install opam from binary disribution on rhel as it is not available from dnf - # Opam is needed to install the sail compiler section_header "Installing/Updating Opam" STATUS="Opam" export OPAMROOTISOK=1 # Silence warnings about running opam as root From e851812608c68678e122c5ad2612987486113e48 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 25 Jul 2024 21:33:31 -0700 Subject: [PATCH 153/219] Replace /opt/riscv after merge --- fpga/rvvidaemon/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fpga/rvvidaemon/Makefile b/fpga/rvvidaemon/Makefile index 26f705a20..e7a40df63 100644 --- a/fpga/rvvidaemon/Makefile +++ b/fpga/rvvidaemon/Makefile @@ -1,10 +1,10 @@ all: rvvidaemon rvvidaemon: rvvidaemon.o - gcc $^ /opt/riscv/ImperasDV-OpenHW/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model.so -o rvvidaemon + gcc $^ $(RISCV)/ImperasDV-OpenHW/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model.so -o rvvidaemon %.o:%.c - gcc -I/opt/riscv/ImperasDV-OpenHW/ImpProprietary/include/host -I/opt/riscv/ImperasDV-OpenHW/ImpPublic/include/host/rvvi/ -c $^ -o $@ + gcc -I$(RISCV)/ImperasDV-OpenHW/ImpProprietary/include/host -I$(RISCV)/ImperasDV-OpenHW/ImpPublic/include/host/rvvi/ -c $^ -o $@ clean: rm *.o rvvidaemon From fed45d9eb69aa64fa20e36f2ddbeb0202cb97b8d Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 25 Jul 2024 21:35:52 -0700 Subject: [PATCH 154/219] Move verilator stack limit to setup.sh/csh insteaed of site-setup --- setup.csh | 3 +++ setup.sh | 3 +++ site-setup.csh | 3 --- site-setup.sh | 3 --- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/setup.csh b/setup.csh index e84c2362c..6b9fa6020 100755 --- a/setup.csh +++ b/setup.csh @@ -29,6 +29,9 @@ echo '$WALLY set to ' ${WALLY} # utility functions in Wally repository extend PATH $WALLY/bin +# Verilator needs a larger stack to simulate CORE-V Wally +limit stacksize unlimited + # load site licenses and tool locations if ( -e "${RISCV}"/site-setup.csh ) then source $RISCV/site-setup.csh diff --git a/setup.sh b/setup.sh index 7d511588f..390af63c4 100644 --- a/setup.sh +++ b/setup.sh @@ -33,6 +33,9 @@ echo \$WALLY set to "${WALLY}" # utility functions in Wally repository export PATH=$WALLY/bin:$PATH +# Verilator needs a larger stack to simulate CORE-V Wally +ulimit -c 300000 + # load site licenses and tool locations if [ -e "${RISCV}"/site-setup.sh ]; then source "${RISCV}"/site-setup.sh diff --git a/site-setup.csh b/site-setup.csh index 6ee000438..a656a7c0e 100644 --- a/site-setup.csh +++ b/site-setup.csh @@ -37,9 +37,6 @@ setenv RISCV_GCC `which riscv64-unknown-elf-gcc` # Copy this as it setenv RISCV_OBJCOPY `which riscv64-unknown-elf-objcopy` # Copy this as it is setenv SPIKE_PATH $RISCV/bin # Change this for your path to riscv-isa-sim (spike) -# Verilator needs a larger stack to simulate CORE-V Wally -limit stacksize unlimited - # Imperas; put this in if you are using it #set path = ($RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64 $path) #setenv LD_LIBRARY_PATH $RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH # remove if no imperas diff --git a/site-setup.sh b/site-setup.sh index 768fc6013..8a4043baa 100755 --- a/site-setup.sh +++ b/site-setup.sh @@ -41,9 +41,6 @@ export RISCV_GCC=$(which riscv64-unknown-elf-gcc) # Copy this as it export RISCV_OBJCOPY=$(which riscv64-unknown-elf-objcopy) # Copy this as it is export SPIKE_PATH=$RISCV/bin # Change this for your path to riscv-isa-sim (spike) -# Verilator needs a larger stack to simulate CORE-V Wally -ulimit -c 300000 - # Imperas OVPsim; put this in if you are using it #export PATH=$RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:$PATH #export LD_LIBRARY_PATH=$RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH From 518650a7561947398ca138eee70586638e6effcc Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 25 Jul 2024 22:26:34 -0700 Subject: [PATCH 155/219] Attempt to fix buildroot makefile --- linux/Makefile | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/linux/Makefile b/linux/Makefile index 10c24defc..f2ad871fb 100644 --- a/linux/Makefile +++ b/linux/Makefile @@ -75,12 +75,16 @@ disassemble: echo "Ignore error about dev/console when extracting rootfs from rootfs.cpio" -cpio -i -D $(BUILDROOT)/output/images/disassembly/rootfs < $(BUILDROOT)/output/images/rootfs.cpio + +$(DIS)/%.objdump: SHELL:=/bin/bash $(DIS)/%.objdump: $(IMAGES)/%.elf - riscv64-unknown-elf-objdump -DS $< >> $@ + source ../setup.sh && \ + riscv64-unknown-elf-objdump -DS $< >> $@ && \ extractFunctionRadix.sh $@ $(DIS)/%.objdump: $(IMAGES)/% - riscv64-unknown-elf-objdump -S $< >> $@ + source ../setup.sh && \ + riscv64-unknown-elf-objdump -S $< >> $@ && \ extractFunctionRadix.sh $@ $(IMAGES)/vmlinux: From 07113eed9f61fb386e9959463c32a5a2f61733a0 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 26 Jul 2024 10:56:25 -0700 Subject: [PATCH 156/219] Add libncurses* to Ubuntu for Vivado --- bin/wally-package-install.sh | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index ed0de2ced..caf4f12d0 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -54,7 +54,7 @@ if [ "$FAMILY" == rhel ]; then QEMU_PACKAGES+=(glib2-devel libfdt-devel pixman-devel bzip2 ninja-build) SPIKE_PACKAGES+=(dtc boost-regex boost-system) VERILATOR_PACKAGES+=(help2man perl clang ccache gperftools numactl mold) - BUILDROOT_PACKAGES+=(ncurses-base ncurses ncurses-libs ncurses-devel gcc-gfortran cpio) # gfortran is only needed for compiling spec benchmarks on buildroot linux + BUILDROOT_PACKAGES+=(ncurses-base ncurses ncurses-libs ncurses-devel gcc-gfortran cpio) # gcc-gfortran is only needed for compiling spec benchmarks on buildroot linux # Extra packages not availale in rhel8, nice for Verilator and needed for sail respectively if (( RHEL_VERSION >= 9 )); then VERILATOR_PACKAGES+=(perl-doc) @@ -82,6 +82,7 @@ elif [ "$FAMILY" == ubuntu ]; then VERILATOR_PACKAGES+=(help2man perl g++ clang ccache libunwind-dev libgoogle-perftools-dev numactl perl-doc libfl2 libfl-dev zlib1g) SAIL_PACKAGES+=(opam z3) BUILDROOT_PACKAGES+=(ncurses-base ncurses-bin libncurses-dev gfortran cpio) # gfortran is only needed for compiling spec benchmarks on buildroot linux + VIVADO_PACKAGES+=(libncurses*) # Vivado hangs on the third stage of installation without this fi @@ -123,6 +124,6 @@ else # Update and Upgrade tools eval "$UPDATE_COMMAND" # Install packages listed above using appropriate package manager - sudo $PACKAGE_MANAGER install -y "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${SAIL_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OTHER_PACKAGES[@]}" + sudo $PACKAGE_MANAGER install -y "${GENERAL_PACKAGES[@]}" "${GNU_PACKAGES[@]}" "${QEMU_PACKAGES[@]}" "${SPIKE_PACKAGES[@]}" "${VERILATOR_PACKAGES[@]}" "${SAIL_PACKAGES[@]}" "${BUILDROOT_PACKAGES[@]}" "${OTHER_PACKAGES[@]}" "${VIVADO_PACKAGES[@]}" echo -e "${SUCCESS_COLOR}Packages successfully installed.${ENDC}" fi From ec7e3d4f3b18d89f5103e197c5101c4b5317630d Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 26 Jul 2024 11:05:12 -0700 Subject: [PATCH 157/219] Remove ftp from installation --- bin/wally-package-install.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bin/wally-package-install.sh b/bin/wally-package-install.sh index caf4f12d0..8fea2d27b 100755 --- a/bin/wally-package-install.sh +++ b/bin/wally-package-install.sh @@ -49,7 +49,7 @@ if [ "$FAMILY" == rhel ]; then PYTHON_VERSION=python3.12 PACKAGE_MANAGER="dnf" UPDATE_COMMAND="sudo $PACKAGE_MANAGER update -y" - GENERAL_PACKAGES+=(which rsync git make cmake "$PYTHON_VERSION" "$PYTHON_VERSION"-pip curl wget ftp tar pkgconf-pkg-config dialog mutt ssmtp) + GENERAL_PACKAGES+=(which rsync git make cmake "$PYTHON_VERSION" "$PYTHON_VERSION"-pip curl wget tar pkgconf-pkg-config dialog mutt ssmtp) GNU_PACKAGES+=(autoconf automake libmpc-devel mpfr-devel gmp-devel gawk bison flex texinfo gperf libtool patchutils bc gcc gcc-c++ zlib-devel expat-devel libslirp-devel) QEMU_PACKAGES+=(glib2-devel libfdt-devel pixman-devel bzip2 ninja-build) SPIKE_PACKAGES+=(dtc boost-regex boost-system) @@ -75,7 +75,7 @@ elif [ "$FAMILY" == ubuntu ]; then fi PACKAGE_MANAGER="DEBIAN_FRONTEND=noninteractive apt-get" UPDATE_COMMAND="sudo $PACKAGE_MANAGER update -y && sudo $PACKAGE_MANAGER upgrade -y --with-new-pkgs" - GENERAL_PACKAGES+=(rsync git make cmake "$PYTHON_VERSION" python3-pip "$PYTHON_VERSION"-venv curl wget ftp tar pkg-config dialog mutt ssmtp) + GENERAL_PACKAGES+=(rsync git make cmake "$PYTHON_VERSION" python3-pip "$PYTHON_VERSION"-venv curl wget tar pkg-config dialog mutt ssmtp) GNU_PACKAGES+=(autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat1-dev ninja-build libglib2.0-dev libslirp-dev) QEMU_PACKAGES+=(libfdt-dev libpixman-1-dev) SPIKE_PACKAGES+=(device-tree-compiler libboost-regex-dev libboost-system-dev) From ab885287bbd1e6d07c92426fb8a6bf6657d0090f Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 26 Jul 2024 11:46:09 -0700 Subject: [PATCH 158/219] Actually fix buildroot makefile --- linux/Makefile | 28 +++++++++++++++-------- linux/testvector-generation/genInitMem.sh | 4 ++-- 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/linux/Makefile b/linux/Makefile index f2ad871fb..6126db7c5 100644 --- a/linux/Makefile +++ b/linux/Makefile @@ -6,6 +6,13 @@ DIS := ${IMAGES}/disassembly BRPACKAGES := $(WALLYLINUX)/buildroot-packages BR2023 := $(WALLYLINUX)/buildroot-config-src/buildroot-2023.05.1 +# set sudo if needed depending on $RISCV +ifeq ($(shell mkdir -p $(RISCV)/.test > /dev/null 2>&1 ; echo $$?), 0) + SUDO := +else + SUDO := sudo +endif + # Buildroot Config Stuff WALLYBOARDSRC := $(WALLYLINUX)/buildroot-config-src/wally WALLYBOARD := $(BUILDROOT)/board/wally @@ -16,7 +23,7 @@ FPGA_AXI_SDC := ${WALLYLINUX}/buildroot-packages/fpga-axi-sdc DRIVER := ${PACKAGE_SOURCE}/fpga-axi-sdc.c PATCHFILE := $(BRPACKAGES)/package-2023.05.1.patch -# Device tree files +# Device tree files DTS ?= $(shell find devicetree -type f -regex ".*\.dts" | sort) DTB := $(DTS:%.dts=%.dtb) DTB := $(foreach name, $(DTB), $(IMAGES)/$(shell basename $(name))) @@ -31,23 +38,26 @@ OBJDUMPS := $(foreach name, $(OBJDUMPS), $(DIS)/$(name).objdump) all: check_write_permissions clean download Image disassemble install dumptvs check_write_permissions: - @mkdir -p $(RISCV)/.test || \ - (echo "ERROR: Cannot write to '$(RISCV)'." \ - "Make sure you have write permissions (you may need to run as sudo).'" >&2 \ +ifeq ($(SUDO), sudo) + @echo "Cannot write to '$(RISCV)'." \ + "Using sudo (you may be prompted for your password several times throughout the install)" +endif + @$(SUDO) mkdir -p $(RISCV)/.test || \ + (echo "ERROR: Still unable to write to '$(RISCV)'." >&2 \ && exit 1) - @rm -r $(RISCV)/.test + @$(SUDO) rm -r $(RISCV)/.test Image: bash -c "unset LD_LIBRARY_PATH; make -C $(BUILDROOT) --jobs ${shell nproc --ignore 1};" $(MAKE) generate install: check_write_permissions - rm -rf $(RISCV)/$(BUILDROOT) - mv $(BUILDROOT) $(RISCV)/$(BUILDROOT) + $(SUDO) rm -rf $(RISCV)/$(BUILDROOT) + $(SUDO) mv $(BUILDROOT) $(RISCV)/$(BUILDROOT) dumptvs: check_write_permissions - mkdir -p $(RISCV)/linux-testvectors - cd testvector-generation; ./genInitMem.sh + $(SUDO) mkdir -p $(RISCV)/linux-testvectors + cd testvector-generation; $(SUDO) ./genInitMem.sh generate: $(DTB) $(IMAGES) diff --git a/linux/testvector-generation/genInitMem.sh b/linux/testvector-generation/genInitMem.sh index 61f570482..ee565cd3c 100755 --- a/linux/testvector-generation/genInitMem.sh +++ b/linux/testvector-generation/genInitMem.sh @@ -26,9 +26,9 @@ fi echo "Launching QEMU in replay mode!" (qemu-system-riscv64 \ --M virt -m 256M -dtb $DEVICE_TREE \ +-M virt -m 256M -dtb "$DEVICE_TREE" \ -nographic \ --bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \ +-bios "$imageDir"/fw_jump.elf -kernel "$imageDir"/Image -append "root=/dev/vda ro" -initrd "$imageDir"/rootfs.cpio \ -gdb tcp::$tcpPort -S) \ & riscv64-unknown-elf-gdb --quiet \ -ex "set pagination off" \ From 0266743582691f006bab1c1dd26533ccd49dd338 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 26 Jul 2024 12:39:36 -0700 Subject: [PATCH 159/219] Add buildroot to wally-tool-chain-install --- bin/wally-tool-chain-install.sh | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 6b92581ce..573c6dbc6 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -388,7 +388,25 @@ if git_check "sky130_osu_sc_t12" "https://foss-eda-tools.googlesource.com/skywat git reset --hard && git clean -f && git checkout main && git pull echo -e "${SUCCESS_COLOR}OSU Skywater library successfully installed${ENDC}" else - echo -e "${SUCCESS_COLOR}OSU Skywater library already up to date${ENDC}" + echo -e "${SUCCESS_COLOR}OSU Skywater library already up to date.${ENDC}" +fi + + +# Buildroot and Linux testvectors +# Buildroot is used to boot a minimal versio of Linux on Wally. +# Testvectors are generated using QEMU. +section_header "Installing Buildroot and Creating Linux testvectors" +STATUS="Buildroot" +cd "$dir"/../linux +if [ ! -e "$RISCV"/buildroot ]; then + make 2>&1 | logger buildroot; [ "${PIPESTATUS[0]}" == 0 ] + echo -e "${SUCCESS_COLOR}Buildroot successfully installed!${ENDC}" +elif [ ! -e "$RISCV"/linux-testvectors ]; then + echo -e "${OK_COLOR}Buildroot already exists, but Linix testvectors are missing. Generating them now.${ENDC}" + make dumptvs 2>&1 | logger buildroot; [ "${PIPESTATUS[0]}" == 0 ] + echo -e "${SUCCESS_COLOR}Linux testvectors successfully generated!${ENDC}" +else + echo -e "${OK_COLOR}Buildroot and Linux testvectors already exist.${ENDC}" fi From 47f4b563a1ef00cc5bda8b50b9e26094985c989e Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 26 Jul 2024 13:36:49 -0700 Subject: [PATCH 160/219] Clean up install script comments --- bin/wally-tool-chain-install.sh | 62 +++++++++++++++++---------------- 1 file changed, 32 insertions(+), 30 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 573c6dbc6..f879c37fa 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -136,7 +136,7 @@ STATUS="python virtual environment" cd "$RISCV" if [ ! -e "$RISCV"/riscv-python/bin/activate ]; then "$PYTHON_VERSION" -m venv riscv-python - echo -e "${OK_COLOR}Python virtual environment created.\nInstalling pip packages.${ENDC}" + echo -e "${OK_COLOR}Python virtual environment created!\nInstalling pip packages.${ENDC}" else echo -e "${OK_COLOR}Python virtual environment already exists.\nUpdating pip packages.${ENDC}" fi @@ -154,7 +154,7 @@ if (( RHEL_VERSION == 8 )); then fi source "$RISCV"/riscv-python/bin/activate # reload python virtual environment -echo -e "${SUCCESS_COLOR}Python environment successfully configured.${ENDC}" +echo -e "${SUCCESS_COLOR}Python environment successfully configured!${ENDC}" # Extra dependecies needed for older distros that don't have new enough versions available from package manager @@ -175,7 +175,7 @@ if (( RHEL_VERSION == 8 )) || (( UBUNTU_VERSION == 20 )); then meson install -C _build cd "$RISCV" rm -rf glib-2.70.5 - echo -e "${SUCCESS_COLOR}glib successfully installed${ENDC}" + echo -e "${SUCCESS_COLOR}glib successfully installed!${ENDC}" fi fi @@ -190,11 +190,11 @@ if (( RHEL_VERSION == 8 )); then rm gmp-6.3.0.tar.xz cd gmp-6.3.0 ./configure --prefix="$RISCV" - make -j ${NUM_THREADS} + make -j "${NUM_THREADS}" make install cd "$RISCV" rm -rf gmp-6.3.0 - echo -e "${SUCCESS_COLOR}gmp successfully installed${ENDC}" + echo -e "${SUCCESS_COLOR}gmp successfully installed!${ENDC}" fi fi @@ -211,15 +211,15 @@ cd "$RISCV" if git_check "riscv-gnu-toolchain" "https://github.com/riscv/riscv-gnu-toolchain" "$RISCV/riscv-gnu-toolchain/stamps/build-gcc-newlib-stage2"; then cd riscv-gnu-toolchain git reset --hard && git clean -f && git checkout master && git pull - ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" - make -j ${NUM_THREADS} 2>&1 | logger riscv-gnu-toolchain; [ "${PIPESTATUS[0]}" == 0 ] + ./configure --prefix="${RISCV}" --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" + make -j "${NUM_THREADS}" 2>&1 | logger riscv-gnu-toolchain; [ "${PIPESTATUS[0]}" == 0 ] if [ "$clean" ]; then cd "$RISCV" rm -rf riscv-gnu-toolchain fi - echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain successfully installed${ENDC}" + echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain successfully installed/updated!${ENDC}" else - echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain already up to date${ENDC}" + echo -e "${SUCCESS_COLOR}RISC-V GNU Toolchain already up to date.${ENDC}" fi @@ -245,9 +245,9 @@ if git_check "elf2hex" "https://github.com/sifive/elf2hex.git" "$RISCV/bin/riscv cd "$RISCV" rm -rf elf2hex fi - echo -e "${SUCCESS_COLOR}elf2hex successfully installed${ENDC}" + echo -e "${SUCCESS_COLOR}elf2hex successfully installed/updated!${ENDC}" else - echo -e "${SUCCESS_COLOR}elf2hex already up to date${ENDC}" + echo -e "${SUCCESS_COLOR}elf2hex already up to date.${ENDC}" fi @@ -258,18 +258,18 @@ STATUS="QEMU" cd "$RISCV" if git_check "qemu" "https://github.com/qemu/qemu" "$RISCV/include/qemu-plugin.h"; then cd qemu - git reset --hard && git clean -f && git checkout master && git pull --recurse-submodules -j ${NUM_THREADS} + git reset --hard && git clean -f && git checkout master && git pull --recurse-submodules -j "${NUM_THREADS}" git submodule update --init --recursive ./configure --target-list=riscv64-softmmu --prefix="$RISCV" - make -j ${NUM_THREADS} 2>&1 | logger qemu; [ "${PIPESTATUS[0]}" == 0 ] + make -j "${NUM_THREADS}" 2>&1 | logger qemu; [ "${PIPESTATUS[0]}" == 0 ] make install 2>&1 | logger qemu; [ "${PIPESTATUS[0]}" == 0 ] if [ "$clean" ]; then cd "$RISCV" rm -rf qemu fi - echo -e "${SUCCESS_COLOR}QEMU successfully installed${ENDC}" + echo -e "${SUCCESS_COLOR}QEMU successfully installed/updated!${ENDC}" else - echo -e "${SUCCESS_COLOR}QEMU already up to date${ENDC}" + echo -e "${SUCCESS_COLOR}QEMU already up to date.${ENDC}" fi @@ -284,15 +284,15 @@ if git_check "riscv-isa-sim" "https://github.com/riscv-software-src/riscv-isa-si mkdir -p build cd build ../configure --prefix="$RISCV" - make -j ${NUM_THREADS} 2>&1 | logger spike; [ "${PIPESTATUS[0]}" == 0 ] + make -j "${NUM_THREADS}" 2>&1 | logger spike; [ "${PIPESTATUS[0]}" == 0 ] make install 2>&1 | logger spike; [ "${PIPESTATUS[0]}" == 0 ] if [ "$clean" ]; then cd "$RISCV" rm -rf riscv-isa-sim fi - echo -e "${SUCCESS_COLOR}Spike successfully installed${ENDC}" + echo -e "${SUCCESS_COLOR}Spike successfully installed/updated!${ENDC}" else - echo -e "${SUCCESS_COLOR}Spike already up to date${ENDC}" + echo -e "${SUCCESS_COLOR}Spike already up to date.${ENDC}" fi @@ -309,17 +309,18 @@ if git_check "verilator" "https://github.com/verilator/verilator" "$RISCV/share/ git reset --hard && git clean -f && git checkout master && git pull autoconf ./configure --prefix="$RISCV" - make -j ${NUM_THREADS} 2>&1 | logger verilator; [ "${PIPESTATUS[0]}" == 0 ] + make -j "${NUM_THREADS}" 2>&1 | logger verilator; [ "${PIPESTATUS[0]}" == 0 ] make install 2>&1 | logger verilator; [ "${PIPESTATUS[0]}" == 0 ] if [ "$clean" ]; then cd "$RISCV" rm -rf verilator fi - echo -e "${SUCCESS_COLOR}Verilator successfully installed${ENDC}" + echo -e "${SUCCESS_COLOR}Verilator successfully installed/updated!${ENDC}" else - echo -e "${SUCCESS_COLOR}Verilator already up to date${ENDC}" + echo -e "${SUCCESS_COLOR}Verilator already up to date.${ENDC}" fi + # Install opam from binary disribution on rhel as it is not available from dnf # Opam is needed to install the sail compiler if [ "$FAMILY" == rhel ]; then @@ -333,7 +334,7 @@ if [ "$FAMILY" == rhel ]; then printf '%s\n' "$RISCV"/bin Y | sh install.sh # the print command provides $RISCV/bin as the installation path when prompted cd "$RISCV" rm -rf opam - echo -e "${SUCCESS_COLOR}Opam successfully installed/updated${ENDC}" + echo -e "${SUCCESS_COLOR}Opam successfully installed/updated!${ENDC}" fi # Sail Compiler (https://github.com/rems-project/sail) @@ -353,7 +354,7 @@ eval "$(opam config env)" opam update -y opam upgrade -y opam install sail -y -echo -e "${SUCCESS_COLOR}Sail Compiler successfully installed/updated${ENDC}" +echo -e "${SUCCESS_COLOR}Sail Compiler successfully installed/updated!${ENDC}" # RISC-V Sail Model (https://github.com/riscv/sail-riscv) # The RISC-V Sail Model is the golden reference model for RISC-V. It is written in Sail (described above) @@ -363,17 +364,17 @@ if git_check "sail-riscv" "https://github.com/riscv/sail-riscv.git" "$RISCV/bin/ cd sail-riscv git reset --hard && git clean -f && git checkout master && git pull export OPAMCLI=2.0 # Sail is not compatible with opam 2.1 as of 4/16/24 - ARCH=RV64 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV64 2>&1 | logger sailModel; [ "${PIPESTATUS[0]}" == 0 ] - ARCH=RV32 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV32 2>&1 | logger sailModel; [ "${PIPESTATUS[0]}" == 0 ] + ARCH=RV64 make -j "${NUM_THREADS}" c_emulator/riscv_sim_RV64 2>&1 | logger sailModel; [ "${PIPESTATUS[0]}" == 0 ] + ARCH=RV32 make -j "${NUM_THREADS}" c_emulator/riscv_sim_RV32 2>&1 | logger sailModel; [ "${PIPESTATUS[0]}" == 0 ] cp -f c_emulator/riscv_sim_RV64 "$RISCV"/bin/riscv_sim_RV64 cp -f c_emulator/riscv_sim_RV32 "$RISCV"/bin/riscv_sim_RV32 if [ "$clean" ]; then cd "$RISCV" rm -rf sail-riscv fi - echo -e "${SUCCESS_COLOR}RISC-V Sail Model successfully installed${ENDC}" + echo -e "${SUCCESS_COLOR}RISC-V Sail Model successfully installed/updated!${ENDC}" else - echo -e "${SUCCESS_COLOR}RISC-V Sail Model already up to date${ENDC}" + echo -e "${SUCCESS_COLOR}RISC-V Sail Model already up to date.${ENDC}" fi @@ -386,7 +387,7 @@ cd "$RISCV"/cad/lib if git_check "sky130_osu_sc_t12" "https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12" "$RISCV/cad/lib/sky130_osu_sc_t12" "main"; then cd sky130_osu_sc_t12 git reset --hard && git clean -f && git checkout main && git pull - echo -e "${SUCCESS_COLOR}OSU Skywater library successfully installed${ENDC}" + echo -e "${SUCCESS_COLOR}OSU Skywater library successfully installed!${ENDC}" else echo -e "${SUCCESS_COLOR}OSU Skywater library already up to date.${ENDC}" fi @@ -429,7 +430,8 @@ if [ ! -e "${RISCV}"/site-setup.sh ]; then echo "# Activate newer gcc version" >> site-setup.csh echo "prepend PATH \$RISCV/gcc-10/bin" >> site-setup.csh fi - echo -e "${SUCCESS_COLOR}Site setup script successfully downloaded${ENDC}" + echo -e "${SUCCESS_COLOR}Site setup script successfully downloaded!${ENDC}" + echo -e "${WARNING_COLOR}Make sure to edit the environment variables in $RISCV/site-setup.sh (or .csh) to point to your installation of EDA tools and licensce files.${ENDC}" else echo -e "${OK_COLOR}Site setup script already exists. Not checking for updates to avoid overwritng modifications." echo -e "You may need to manually update it if there were changes upstream.${ENDC}" @@ -439,4 +441,4 @@ if [ "$clean" ]; then rm -rf "$RISCV"/logs fi -echo -e "${SUCCESS_COLOR}${BOLD}\n\nINSTALLATION SUCCESSFUL\n\n${ENDC}" +echo -e "${SUCCESS_COLOR}${BOLD}\n\nINSTALLATION SUCCESSFUL!!!\n\n${ENDC}" \ No newline at end of file From ea16f132f5c84e034c1deac8b79e6c94703e64bc Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 26 Jul 2024 13:37:48 -0700 Subject: [PATCH 161/219] Create LD_LIBRARY_PATH if blank --- site-setup.csh | 6 +++++- site-setup.sh | 13 ++++++++----- 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/site-setup.csh b/site-setup.csh index a656a7c0e..707b54970 100644 --- a/site-setup.csh +++ b/site-setup.csh @@ -17,7 +17,11 @@ extend PATH $SNPSPATH extend PATH $VCSPATH # GCC -extend LD_LIBRARY_PATH $RISCV/riscv64-unknown-elf/lib +if ( ! $?LD_LIBRARY_PATH ) then + setenv LD_LIBRARY_PATH $RISCV/riscv64-unknown-elf/lib +else + extend LD_LIBRARY_PATH $RISCV/riscv64-unknown-elf/lib +endif # RISC-V Tools extend LD_LIBRARY_PATH $RISCV/lib diff --git a/site-setup.sh b/site-setup.sh index 8a4043baa..109aedb03 100755 --- a/site-setup.sh +++ b/site-setup.sh @@ -20,14 +20,17 @@ export VCS_HOME=/cad/synopsys/vcs/U-2023.03-SP2-4 # Change thi export PATH=$QUESTA_HOME/bin:$DC_HOME/bin:$VCS_HOME/bin:$PATH # GCC -export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RISCV/riscv64-unknown-elf/lib +if [ -z "$LD_LIBRARY_PATH" ]; then + export LD_LIBRARY_PATH=$RISCV/riscv64-unknown-elf/lib +else + export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RISCV/riscv64-unknown-elf/lib +fi # RISC-V Tools export LD_LIBRARY_PATH=$RISCV/lib:$RISCV/lib64:$LD_LIBRARY_PATH export PATH=$PATH:$RISCV/bin # Activate riscv-python Virtual Environment - if [ -e "$RISCV"/riscv-python/bin/activate ]; then source "$RISCV"/riscv-python/bin/activate else @@ -35,16 +38,16 @@ else exit 1 fi - -# environment variables needed for RISCV-DV +# Environment variables needed for RISCV-DV export RISCV_GCC=$(which riscv64-unknown-elf-gcc) # Copy this as it is export RISCV_OBJCOPY=$(which riscv64-unknown-elf-objcopy) # Copy this as it is -export SPIKE_PATH=$RISCV/bin # Change this for your path to riscv-isa-sim (spike) +export SPIKE_PATH=$RISCV/bin # Copy this as it is # Imperas OVPsim; put this in if you are using it #export PATH=$RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:$PATH #export LD_LIBRARY_PATH=$RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH +# Imperas DV setup export IDV=$RISCV/ImperasDV-OpenHW if [ -e "$IDV" ]; then # echo "Imperas exists" From 1a205412cb3ae93af6b07daba26b389ed65df53f Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 26 Jul 2024 13:38:30 -0700 Subject: [PATCH 162/219] csh fixes --- site-setup.csh | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/site-setup.csh b/site-setup.csh index 707b54970..bd747dfc9 100644 --- a/site-setup.csh +++ b/site-setup.csh @@ -13,8 +13,8 @@ setenv VCSPATH /cad/synopsys/vcs/U-2023.03-SP2-4/bin # Change this # Tools # Questa and Synopsys extend PATH $QUESTAPATH -extend PATH $SNPSPATH -extend PATH $VCSPATH +extend PATH $SNPSPATH +extend PATH $VCSPATH # GCC if ( ! $?LD_LIBRARY_PATH ) then @@ -34,7 +34,7 @@ if ( -e "$RISCV"/riscv-python/bin/activate ) then else echo "Python virtual environment not found. Rerun wally-toolchain-install.sh to automatically create it." exit 1 -fi +endif # environment variables needed for RISCV-DV setenv RISCV_GCC `which riscv64-unknown-elf-gcc` # Copy this as it is @@ -55,4 +55,3 @@ if ($?IDV) then setupImperas ${IMPERAS_HOME} extend PATH $IDV/scripts/cvw endif - From 0224419d41e79cb3a429d37b14d363f952fa604d Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 26 Jul 2024 15:46:08 -0700 Subject: [PATCH 163/219] Additional linux makefile cleanup --- linux/Makefile | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/linux/Makefile b/linux/Makefile index 6126db7c5..06b42e3fb 100644 --- a/linux/Makefile +++ b/linux/Makefile @@ -48,16 +48,19 @@ endif @$(SUDO) rm -r $(RISCV)/.test Image: - bash -c "unset LD_LIBRARY_PATH; make -C $(BUILDROOT) --jobs ${shell nproc --ignore 1};" + bash -c "unset LD_LIBRARY_PATH; $(MAKE) -C $(BUILDROOT)" $(MAKE) generate + @echo "Buildroot Image successfully generated." install: check_write_permissions $(SUDO) rm -rf $(RISCV)/$(BUILDROOT) $(SUDO) mv $(BUILDROOT) $(RISCV)/$(BUILDROOT) + @echo "Buildroot successfully installed." dumptvs: check_write_permissions $(SUDO) mkdir -p $(RISCV)/linux-testvectors cd testvector-generation; $(SUDO) ./genInitMem.sh + @echo "Testvectors successfully generated." generate: $(DTB) $(IMAGES) @@ -79,11 +82,12 @@ disassemble: rm -rf $(BUILDROOT)/output/images/disassembly find $(BUILDROOT)/output/build/linux-* -maxdepth 1 -name "vmlinux" | xargs cp -t $(BUILDROOT)/output/images/ mkdir -p $(DIS) - make -j $(OBJDUMPS) + $(MAKE) $(OBJDUMPS) # extract rootfs mkdir -p $(BUILDROOT)/output/images/disassembly/rootfs - echo "Ignore error about dev/console when extracting rootfs from rootfs.cpio" + @echo "Ignore error about dev/console when extracting rootfs from rootfs.cpio" -cpio -i -D $(BUILDROOT)/output/images/disassembly/rootfs < $(BUILDROOT)/output/images/rootfs.cpio + @echo "Disassembly successfully completed." $(DIS)/%.objdump: SHELL:=/bin/bash @@ -109,6 +113,7 @@ $(IMAGES)/busybox: download: $(BUILDROOT)/package/fpga-axi-sdc $(WALLYBOARD) cp $(WALLYBOARD)/main.config $(BUILDROOT)/.config + @echo "Buildroot successfully download." # CONFIG DEPENDENCIES 2023.05.1 --------------------------------------- $(WALLYBOARD): $(BUILDROOT) From f98b25a9e30b3ecff88e0d00be63c682ac5bcd52 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 26 Jul 2024 16:56:16 -0700 Subject: [PATCH 164/219] Update LD_LIBRARY_PATH in wally-tool-chain-install script --- bin/wally-tool-chain-install.sh | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index f879c37fa..40207e409 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -398,6 +398,11 @@ fi # Testvectors are generated using QEMU. section_header "Installing Buildroot and Creating Linux testvectors" STATUS="Buildroot" +if [ -z "$LD_LIBRARY_PATH" ]; then + export LD_LIBRARY_PATH=$RISCV/lib:$RISCV/lib64:$RISCV/riscv64-unknown-elf/lib +else + export LD_LIBRARY_PATH=$RISCV/lib:$RISCV/lib64:$LD_LIBRARY_PATH:$RISCV/riscv64-unknown-elf/lib +fi cd "$dir"/../linux if [ ! -e "$RISCV"/buildroot ]; then make 2>&1 | logger buildroot; [ "${PIPESTATUS[0]}" == 0 ] From 34b7f3d65c064387c564bd927efb5e22456870bf Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 26 Jul 2024 17:20:56 -0700 Subject: [PATCH 165/219] Updates to linux testvector generation --- linux/Makefile | 10 +++------- linux/testvector-generation/genInitMem.sh | 1 + 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/linux/Makefile b/linux/Makefile index 06b42e3fb..6decffe7e 100644 --- a/linux/Makefile +++ b/linux/Makefile @@ -59,7 +59,7 @@ install: check_write_permissions dumptvs: check_write_permissions $(SUDO) mkdir -p $(RISCV)/linux-testvectors - cd testvector-generation; $(SUDO) ./genInitMem.sh + cd testvector-generation; ./genInitMem.sh @echo "Testvectors successfully generated." generate: $(DTB) $(IMAGES) @@ -89,16 +89,12 @@ disassemble: -cpio -i -D $(BUILDROOT)/output/images/disassembly/rootfs < $(BUILDROOT)/output/images/rootfs.cpio @echo "Disassembly successfully completed." - -$(DIS)/%.objdump: SHELL:=/bin/bash $(DIS)/%.objdump: $(IMAGES)/%.elf - source ../setup.sh && \ - riscv64-unknown-elf-objdump -DS $< >> $@ && \ + riscv64-unknown-elf-objdump -DS $< >> $@ extractFunctionRadix.sh $@ $(DIS)/%.objdump: $(IMAGES)/% - source ../setup.sh && \ - riscv64-unknown-elf-objdump -S $< >> $@ && \ + riscv64-unknown-elf-objdump -S $< >> $@ extractFunctionRadix.sh $@ $(IMAGES)/vmlinux: diff --git a/linux/testvector-generation/genInitMem.sh b/linux/testvector-generation/genInitMem.sh index ee565cd3c..1274a4240 100755 --- a/linux/testvector-generation/genInitMem.sh +++ b/linux/testvector-generation/genInitMem.sh @@ -1,4 +1,5 @@ #!/bin/bash +set -e tcpPort=1235 imageDir=$RISCV/buildroot/output/images tvDir=$RISCV/linux-testvectors From 9631c262dc89ece749637e4dd92caa232c049b02 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 26 Jul 2024 18:33:09 -0700 Subject: [PATCH 166/219] Update linux makefile wiht path to wally bin --- linux/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/linux/Makefile b/linux/Makefile index 6decffe7e..d195dfa41 100644 --- a/linux/Makefile +++ b/linux/Makefile @@ -91,11 +91,11 @@ disassemble: $(DIS)/%.objdump: $(IMAGES)/%.elf riscv64-unknown-elf-objdump -DS $< >> $@ - extractFunctionRadix.sh $@ + $(WALLY)/bin/extractFunctionRadix.sh $@ $(DIS)/%.objdump: $(IMAGES)/% riscv64-unknown-elf-objdump -S $< >> $@ - extractFunctionRadix.sh $@ + $(WALLY)/bin/extractFunctionRadix.sh $@ $(IMAGES)/vmlinux: linuxDir=$$(find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/linux-[0-9]+\.[0-9]+\.[0-9]+$$") ;\ From 9857ed4fe238d5ea43bf480bda79d15cf02e6949 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 26 Jul 2024 22:33:22 -0700 Subject: [PATCH 167/219] Update logger to filter more text from buildroot install --- bin/wally-tool-chain-install.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 40207e409..d24fa0722 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -67,7 +67,7 @@ git_check() { # Log output to a file and only print lines with keywords logger() { local log="$RISCV/logs/$1.log" - cat < /dev/stdin | tee -a "$log" | (grep -iE --color=never "(\bwarning|\berror|\bfail|\bsuccess|\bstamp)" || true) + cat < /dev/stdin | tee -a "$log" | (grep -iE --color=never "(\bwarning|\berror|\bfail|\bsuccess|\bstamp)" || true) | (grep -viE --color=never "(Wno-error)" || true) } set -e # break on error From 5f2b608035c18bfeb0d3e607b2739c4201315f2c Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 26 Jul 2024 22:37:47 -0700 Subject: [PATCH 168/219] Don't delete logs in --clean mode --- bin/wally-tool-chain-install.sh | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index d24fa0722..3753ff9ec 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -442,8 +442,4 @@ else echo -e "You may need to manually update it if there were changes upstream.${ENDC}" fi -if [ "$clean" ]; then - rm -rf "$RISCV"/logs -fi - -echo -e "${SUCCESS_COLOR}${BOLD}\n\nINSTALLATION SUCCESSFUL!!!\n\n${ENDC}" \ No newline at end of file +echo -e "${SUCCESS_COLOR}${BOLD}\n\nINSTALLATION SUCCESSFUL!!!\n\n${ENDC}" From 97c1050bcce52637a428f8d336581d56c7e8febe Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 27 Jul 2024 11:28:27 -0700 Subject: [PATCH 169/219] Remove opam folder when install with --clean --- bin/wally-tool-chain-install.sh | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 3753ff9ec..6f6e6f722 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -371,6 +371,7 @@ if git_check "sail-riscv" "https://github.com/riscv/sail-riscv.git" "$RISCV/bin/ if [ "$clean" ]; then cd "$RISCV" rm -rf sail-riscv + rm -rf opam fi echo -e "${SUCCESS_COLOR}RISC-V Sail Model successfully installed/updated!${ENDC}" else @@ -406,9 +407,9 @@ fi cd "$dir"/../linux if [ ! -e "$RISCV"/buildroot ]; then make 2>&1 | logger buildroot; [ "${PIPESTATUS[0]}" == 0 ] - echo -e "${SUCCESS_COLOR}Buildroot successfully installed!${ENDC}" + echo -e "${SUCCESS_COLOR}Buildroot successfully installed and Linux testvectors created!${ENDC}" elif [ ! -e "$RISCV"/linux-testvectors ]; then - echo -e "${OK_COLOR}Buildroot already exists, but Linix testvectors are missing. Generating them now.${ENDC}" + echo -e "${OK_COLOR}Buildroot already exists, but Linux testvectors are missing. Generating them now.${ENDC}" make dumptvs 2>&1 | logger buildroot; [ "${PIPESTATUS[0]}" == 0 ] echo -e "${SUCCESS_COLOR}Linux testvectors successfully generated!${ENDC}" else From 561843d3be9b88705fb2f8050c961b057ca779f8 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Sat, 27 Jul 2024 11:35:59 -0700 Subject: [PATCH 170/219] Update LD_LIBRARY_PATH to fix qemu on Ubuntu 20.04 --- bin/wally-tool-chain-install.sh | 4 ++-- site-setup.csh | 1 + site-setup.sh | 6 +++--- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 6f6e6f722..dfda570bc 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -400,9 +400,9 @@ fi section_header "Installing Buildroot and Creating Linux testvectors" STATUS="Buildroot" if [ -z "$LD_LIBRARY_PATH" ]; then - export LD_LIBRARY_PATH=$RISCV/lib:$RISCV/lib64:$RISCV/riscv64-unknown-elf/lib + export LD_LIBRARY_PATH=$RISCV/lib:$RISCV/lib64:$RISCV/riscv64-unknown-elf/lib:$RISCV/lib/x86_64-linux-gnu/ else - export LD_LIBRARY_PATH=$RISCV/lib:$RISCV/lib64:$LD_LIBRARY_PATH:$RISCV/riscv64-unknown-elf/lib + export LD_LIBRARY_PATH=$RISCV/lib:$RISCV/lib64:$LD_LIBRARY_PATH:$RISCV/riscv64-unknown-elf/lib:$RISCV/lib/x86_64-linux-gnu/ fi cd "$dir"/../linux if [ ! -e "$RISCV"/buildroot ]; then diff --git a/site-setup.csh b/site-setup.csh index bd747dfc9..c8435ddf5 100644 --- a/site-setup.csh +++ b/site-setup.csh @@ -26,6 +26,7 @@ endif # RISC-V Tools extend LD_LIBRARY_PATH $RISCV/lib extend LD_LIBRARY_PATH $RISCV/lib64 +extend LD_LIBRARY_PATH $RISCV/lib/x86_64-linux-gnu/ extend PATH $RISCV/bin # Activate riscv-python Virtual Environment diff --git a/site-setup.sh b/site-setup.sh index 109aedb03..f6a499aec 100755 --- a/site-setup.sh +++ b/site-setup.sh @@ -27,7 +27,7 @@ else fi # RISC-V Tools -export LD_LIBRARY_PATH=$RISCV/lib:$RISCV/lib64:$LD_LIBRARY_PATH +export LD_LIBRARY_PATH=$RISCV/lib:$RISCV/lib64:$LD_LIBRARY_PATH:$RISCV/lib/x86_64-linux-gnu/ export PATH=$PATH:$RISCV/bin # Activate riscv-python Virtual Environment @@ -54,7 +54,7 @@ if [ -e "$IDV" ]; then export IMPERAS_HOME=$IDV/Imperas export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC export ROOTDIR=~/ - source ${IMPERAS_HOME}/bin/setup.sh - setupImperas ${IMPERAS_HOME} + source "${IMPERAS_HOME}"/bin/setup.sh + setupImperas "${IMPERAS_HOME}" export PATH=$IDV/scripts/cvw:$PATH fi From a263f836f2d322c0f4a5db4e1303e282e741c31b Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Wed, 31 Jul 2024 10:58:15 -0500 Subject: [PATCH 171/219] Added extra UART macros and functions for code readability and the ability to print decimal numbers. --- fpga/zsbl/uart.c | 68 +++++++++++++++++++++++++++++++++++------------- fpga/zsbl/uart.h | 20 +++++++++++++- 2 files changed, 69 insertions(+), 19 deletions(-) diff --git a/fpga/zsbl/uart.c b/fpga/zsbl/uart.c index 1330bc1d9..d7ac9b558 100644 --- a/fpga/zsbl/uart.c +++ b/fpga/zsbl/uart.c @@ -62,10 +62,10 @@ void bin_to_hex(uint8_t inp, uint8_t res[2]) return; } -void print_uart_int(uint32_t addr) +void print_uart_hex(uint64_t addr, int n) { int i; - for (i = 3; i > -1; i--) { + for (i = n - 1; i > -1; i--) { uint8_t cur = (addr >> (i * 8)) & 0xff; uint8_t hex[2]; bin_to_hex(cur, hex); @@ -74,22 +74,54 @@ void print_uart_int(uint32_t addr) } } -void print_uart_addr(uint64_t addr) -{ - int i; - for (i = 7; i > -1; i--) { - uint8_t cur = (addr >> (i * 8)) & 0xff; - uint8_t hex[2]; - bin_to_hex(cur, hex); - write_serial(hex[0]); - write_serial(hex[1]); +void print_uart_dec(uint64_t addr) { + + // floor(log(2^64)) = 19 + char str[19] = {'\0'}; + uint8_t length = 0; + + uint64_t cur = addr; + while (cur != 0) { + char digit = bin_to_hex_table[cur % 10]; + // write_serial(digit); + str[length] = digit; + cur = cur/10; + length++; + } + + for (int i = length; i > -1; i--) { + write_serial(str[i]); } } -void print_uart_byte(uint8_t byte) -{ - uint8_t hex[2]; - bin_to_hex(byte, hex); - write_serial(hex[0]); - write_serial(hex[1]); -} +/* void print_uart_int(uint32_t addr) */ +/* { */ +/* int i; */ +/* for (i = 3; i > -1; i--) { */ +/* uint8_t cur = (addr >> (i * 8)) & 0xff; */ +/* uint8_t hex[2]; */ +/* bin_to_hex(cur, hex); */ +/* write_serial(hex[0]); */ +/* write_serial(hex[1]); */ +/* } */ +/* } */ + +/* void print_uart_addr(uint64_t addr) */ +/* { */ +/* int i; */ +/* for (i = 7; i > -1; i--) { */ +/* uint8_t cur = (addr >> (i * 8)) & 0xff; */ +/* uint8_t hex[2]; */ +/* bin_to_hex(cur, hex); */ +/* write_serial(hex[0]); */ +/* write_serial(hex[1]); */ +/* } */ +/* } */ + +/* void print_uart_byte(uint8_t byte) */ +/* { */ +/* uint8_t hex[2]; */ +/* bin_to_hex(byte, hex); */ +/* write_serial(hex[0]); */ +/* write_serial(hex[1]); */ +/* } */ diff --git a/fpga/zsbl/uart.h b/fpga/zsbl/uart.h index 18710e76b..ee399885f 100644 --- a/fpga/zsbl/uart.h +++ b/fpga/zsbl/uart.h @@ -16,11 +16,29 @@ #define UART_DLL UART_BASE + 0x00 #define UART_DLM UART_BASE + 0x01 -void init_uart(); +void init_uart(uint32_t freq, uint32_t baud); void write_reg_u8(uintptr_t addr, uint8_t value); uint8_t read_reg_u8(uintptr_t addr); int read_serial(uint8_t *res); void print_uart(const char* str); void print_uart_int(uint32_t addr); +void print_uart_dec(uint64_t addr); void print_uart_addr(uint64_t addr); +void print_uart_hex(uint64_t addr, int n); void print_uart_byte(uint8_t byte); + +#define print_uart_int(addr) print_uart_hex(addr, 4) +#define print_uart_addr(addr) print_uart_hex(addr, 8) +#define print_uart_byte(addr) print_uart_hex(addr, 1) +#define print_r7(addr) print_uart_hex(addr, 5) +#define print_r1(addr) print_uart_byte(addr) + +// Print line with numbers utility macros +#define println(msg) print_uart(msg "\r\n"); +#define println_with_dec(msg, num) print_uart(msg); print_uart_dec(num); print_uart("\r\n") +#define println_with_byte(msg, num) print_uart(msg); print_uart_byte(num); print_uart("\r\n") +#define println_with_int(msg, num) print_uart(msg); print_uart_int(num); print_uart("\r\n") +#define println_with_addr(msg, num) print_uart(msg); print_uart_addr(num); print_uart("\r\n") +#define println_with_r1(msg, num) print_uart(msg); print_r1(num); print_uart("\r\n") +#define println_with_r7(msg, num) print_uart(msg); print_r7(num); print_uart("\r\n") + From c4ae17c6797ecdb734be059df83634e70922d2ad Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Wed, 31 Jul 2024 10:59:41 -0500 Subject: [PATCH 172/219] Cleaned up code formatting a bit and added ability to set the SD card clock speed. --- fpga/zsbl/sd.c | 65 ++++++++++++++++++++++++++++++++++++++------------ fpga/zsbl/sd.h | 4 ++-- 2 files changed, 52 insertions(+), 17 deletions(-) diff --git a/fpga/zsbl/sd.c b/fpga/zsbl/sd.c index 02ee4d3bf..cacf40438 100644 --- a/fpga/zsbl/sd.c +++ b/fpga/zsbl/sd.c @@ -62,8 +62,14 @@ uint64_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc) { // response length. Probably unecessary so let's wait and see what // happens. // write_reg(SPI_RXMARK, response_len); + + // Chip select must remain asserted during transaction + if (cmd != SD_CMD_STOP_TRANSMISSION) { + write_reg(SPI_CSMODE, SIFIVE_SPI_CSMODE_MODE_HOLD); + } - // Write all 6 bytes into transfer fifo + // Write all 7 bytes into transfer fifo + // spi_sendbyte(0xff); spi_sendbyte(0x40 | cmd); spi_sendbyte(arg >> 24); spi_sendbyte(arg >> 16); @@ -77,7 +83,7 @@ uint64_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc) { waittx(); // Read the dummy rxFIFO entries to move the head back to the tail - for (i = 0; i < 6; i++) { + for (i = 0; i < 7; i++) { spi_readbyte(); } @@ -90,12 +96,24 @@ uint64_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc) { // Wait for transfer fifo again waittx(); + // Wait for actual response from SD card + // All responses start with a 0. Output of SDCIn is high, unless + // a message is being transferred. + do { + rbyte = spi_txrx(0xff); + } while ( (rbyte & 0x80) != 0 ); + + r = r | (rbyte << ((response_len - 1)*8)); + // Read rxfifo response - for (i = 0; i < response_len; i++) { + for (i = 1; i < response_len; i++) { rbyte = spi_readbyte(); r = r | (rbyte << ((response_len - 1 - i)*8)); } + if (cmd != 18) { + write_reg(SPI_CSMODE, SIFIVE_SPI_CSMODE_MODE_AUTO); + } return r; } // sd_cmd @@ -128,33 +146,50 @@ uint64_t sd_read64(uint16_t * crc) { // init_sd: ---------------------------------------------------------- // This first initializes the SPI peripheral then initializes the SD // card itself. We use the uart to display anything that goes wrong. -void init_sd(){ +int init_sd(uint32_t freq, uint32_t sdclk){ spi_init(); uint64_t r; + uint32_t newClockDiv; - print_uart("Initializing SD Card in SPI mode.\r\n"); + println("Initializing SD Card in SPI mode."); + // This is necessary. This is the card's pre-init state initialization. + write_reg(SPI_CSMODE, SIFIVE_SPI_CSMODE_MODE_OFF); + for (int i = 0; i < 10; i++) { + spi_txrx(0xff); + } + write_reg(SPI_CSMODE, SIFIVE_SPI_CSMODE_MODE_AUTO); + // CMD0 -------------------------------------------------------------- // Reset SD Card command // Initializes SD card into SPI mode if CS is asserted '0' - if (!(( r = CMD0() ) & 0x10) ) { - print_uart("SD ERROR: "); - print_uart_byte(r & 0xff); - print_uart("\r\n"); - } + // We expect to get the R1 response 0x01 which means that the + // card has been put into the idle state. + print_uart("CMD0: "); + do { + r = CMD0(); + } while ( r != 0x01 ); + println_with_r1("Success, r = 0x", r & 0xff); + // CMD8 ------------------------------------------------------------- // - if (!(( r = CMD8() ) & 0x10 )) { - print_uart("SD ERROR: "); - print_uart_byte(r & 0xff); - print_uart("\r\n"); + print_uart("CMD8: "); + r = CMD8(); + if ((r & 0x000000ff0000ffff) != 0x01000001aa) { + println_with_r7("Failed, 0x", r); } + println_with_r7("Success, 0x", r); + // ACMD41 ----------------------------------------------------------- + print_uart("ACMD41: "); do { CMD55(); r = ACMD41(); } while (r == 0x1); + println_with_r1("Success, r = 0x", r & 0xff); - print_uart("SD card is initialized.\n\r"); + println_with_dec("New clock frequency: ", (uint64_t)sdclk); + spi_set_clock(freq, sdclk); + println("SD card is initialized."); } diff --git a/fpga/zsbl/sd.h b/fpga/zsbl/sd.h index 37e4a2c94..f695b83e5 100644 --- a/fpga/zsbl/sd.h +++ b/fpga/zsbl/sd.h @@ -9,11 +9,11 @@ // Response lengths in bytes #define R1_RESPONSE 1 -#define R7_RESPONSE 7 +#define R7_RESPONSE 5 #define R1B_RESPONSE 2 uint8_t crc7(uint8_t prev, uint8_t in); uint16_t crc16(uint16_t crc, uint8_t data); uint64_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc); uint64_t sd_read64(uint16_t * crc); -void init_sd(); +int init_sd(uint32_t freq, uint32_t sdclk); From ee980e39f306cebc9eb2ce7af2c3a0acd8352d91 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Wed, 31 Jul 2024 11:00:44 -0500 Subject: [PATCH 173/219] Added function to set SPI clock speed. --- fpga/zsbl/spi.c | 7 ++++++- fpga/zsbl/spi.h | 5 +---- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/fpga/zsbl/spi.c b/fpga/zsbl/spi.c index cbb9fa2eb..b8829b12e 100644 --- a/fpga/zsbl/spi.c +++ b/fpga/zsbl/spi.c @@ -83,8 +83,13 @@ uint64_t spi_read64() { return r; } +void spi_set_clock(uint32_t clkin, uint32_t clkout) { + uint32_t div = (clkin/(2*clkout)) - 1; + write_reg(SPI_SCKDIV, div); +} + // Initialize Sifive FU540 based SPI Controller -void spi_init() { +void spi_init(uint32_t clkin) { // Enable interrupts write_reg(SPI_IE, 0x3); diff --git a/fpga/zsbl/spi.h b/fpga/zsbl/spi.h index bc85c768f..a662fce86 100644 --- a/fpga/zsbl/spi.h +++ b/fpga/zsbl/spi.h @@ -44,10 +44,6 @@ #define SIFIVE_SPI_CSMODE_MODE_HOLD 2U #define SIFIVE_SPI_CSMODE_MODE_OFF 3U - -#define WAITTX while(!(read_reg(SPI_IP) & 1) {} -#define WAITRX while(read_reg(SPI_IP) & 2) {} - // inline void write_reg(uintptr_t addr, uint32_t value); //inline uint32_t read_reg(uintptr_t addr); //inline void spi_sendbyte(uint8_t byte); @@ -57,6 +53,7 @@ uint8_t spi_txrx(uint8_t byte); //inline uint8_t spi_readbyte(); uint64_t spi_read64(); void spi_init(); +void spi_set_clock(uint32_t clkin, uint32_t clkout); static inline void write_reg(uintptr_t addr, uint32_t value) { volatile uint32_t * loc = (volatile uint32_t *) addr; From 38071d826736f527820b94d8492492898171bf3e Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Wed, 31 Jul 2024 11:12:05 -0500 Subject: [PATCH 174/219] Updated formatting of gpt.c and boot.c. --- fpga/zsbl/boot.c | 40 ++++++++++++++++++++++++++-------------- fpga/zsbl/gpt.c | 21 +++++---------------- fpga/zsbl/uart.h | 3 +++ 3 files changed, 34 insertions(+), 30 deletions(-) diff --git a/fpga/zsbl/boot.c b/fpga/zsbl/boot.c index 5b022cea3..7b2e9af7d 100644 --- a/fpga/zsbl/boot.c +++ b/fpga/zsbl/boot.c @@ -34,10 +34,12 @@ /* return 0;; */ /* } */ +#define SYSTEMCLOCK 20000000 + int disk_read(BYTE * buf, LBA_t sector, UINT count) { uint64_t r; UINT i; - + uint8_t crc = 0; crc = crc7(crc, 0x40 | SD_CMD_READ_BLOCK_MULTIPLE); crc = crc7(crc, (sector >> 24) & 0xff); @@ -46,25 +48,29 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) { crc = crc7(crc, sector & 0xff); crc = crc | 1; - if (sd_cmd(18, sector & 0xffffffff, crc) != 0x00) { - print_uart("disk_read: CMD18 failed. r = "); - print_uart_byte(r & 0xff); + if ((r = sd_cmd(18, sector & 0xffffffff, crc) & 0xff) != 0x00) { + print_uart("disk_read: CMD18 failed. r = 0x"); + print_uart_byte(r); print_uart("\r\n"); return -1; } + // write_reg(SPI_CSMODE, SIFIVE_SPI_CSMODE_MODE_HOLD); // Begin reading blocks for (i = 0; i < count; i++) { uint16_t crc, crc_exp; // Read the data token r = spi_readbyte(); - if (r != SD_DATA_TOKEN) { - print_uart("Didn't receive data token first thing. Shoot: "); - print_uart_byte(r & 0xff); - print_uart("\r\n"); - return -1; - } + /* if (r != SD_DATA_TOKEN) { */ + /* print_uart("Didn't receive data token first thing. Shoot: "); */ + /* print_uart_byte(r & 0xff); */ + /* print_uart("\r\n"); */ + /* return -1; */ + /* } */ + + // Wait for data token + while((r & 0xff) != SD_DATA_TOKEN); // Read block into memory. for (int j = 0; j < 8; j++) { @@ -77,7 +83,7 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) { crc_exp |= spi_txrx(0xff); if (crc != crc_exp) { - print_uart("Stinking CRC16 didn't match on block "); + print_uart("Stinking CRC16 didn't match on block read.\r\n"); print_uart_int(i); print_uart("\r\n"); return -1; @@ -86,7 +92,8 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) { } sd_cmd(SD_CMD_STOP_TRANSMISSION, 0, 0x01); - spi_txrx(0xff); + // write_reg(SPI_CSMODE, SIFIVE_SPI_CSMODE_MODE_AUTO); + //spi_txrx(0xff); return 0; } @@ -100,12 +107,17 @@ void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) { // Initialize UART for messages init_uart(20000000, 115200); - print_uart("Booting wally.\r\n"); // Print the wally banner print_uart(BANNER); + /* print_uart("System clock speed: "); */ + /* print_uart_dec(SYSTEMCLOCK); */ + /* print_uart("\r\n"); */ + + println_with_dec("Hello, does this work? Here's the clock: ", SYSTEMCLOCK); + // Intialize the SD card - init_sd(); + init_sd(SYSTEMCLOCK, SYSTEMCLOCK/2); ret = gpt_load_partitions(); } diff --git a/fpga/zsbl/gpt.c b/fpga/zsbl/gpt.c index a52dc9048..9af396469 100644 --- a/fpga/zsbl/gpt.c +++ b/fpga/zsbl/gpt.c @@ -3,18 +3,7 @@ #include "uart.h" #include -/* PSUEDOCODE - - Need to load GPT LBA 1 and read through the partition entries. - I need to find each of the relevant partition entries, possibly - by their partition names. - -*/ - int gpt_load_partitions() { - // In this version of the GPT partition code - // I'm going to assume that the SD card is already initialized. - // size_t block_size = 512/8; // long int lba1_buf[block_size]; @@ -22,15 +11,12 @@ int gpt_load_partitions() { int ret = 0; //ret = disk_read(/* BYTE * buf, LBA_t sector, UINT count, BYTE card_type */); + println("Getting GPT information."); ret = disk_read(lba1_buf, 1, 1); - /* Possible error handling with UART message - if ( ret != 0 ) { - - }*/ - gpt_pth_t *lba1 = (gpt_pth_t *)lba1_buf; + println("Getting partition entries."); BYTE lba2_buf[512]; ret = disk_read(lba2_buf, (LBA_t)lba1->partition_entries_lba, 1); @@ -40,6 +26,7 @@ int gpt_load_partitions() { partition_entries_t *kernel = (partition_entries_t *)(lba2_buf + 256); // Load device tree + println_with_int("Loading device tree at: 0x", FDT_ADDRESS); ret = disk_read((BYTE *)FDT_ADDRESS, fdt->first_lba, fdt->last_lba - fdt->first_lba + 1); if (ret < 0) { print_uart("Failed to load device tree!\r\n"); @@ -47,6 +34,7 @@ int gpt_load_partitions() { } // Load OpenSBI + println_with_int("Loading OpenSBI at: 0x", OPENSBI_ADDRESS); ret = disk_read((BYTE *)OPENSBI_ADDRESS, opensbi->first_lba, opensbi->last_lba - opensbi->first_lba + 1); if (ret < 0) { print_uart("Failed to load OpenSBI!\r\n"); @@ -54,6 +42,7 @@ int gpt_load_partitions() { } // Load Linux + println_with_int("Loading Linux Kernel at: 0x", KERNEL_ADDRESS); ret = disk_read((BYTE *)KERNEL_ADDRESS, kernel->first_lba,kernel->last_lba - kernel->first_lba + 1); if (ret < 0) { print_uart("Failed to load Linux!\r\n"); diff --git a/fpga/zsbl/uart.h b/fpga/zsbl/uart.h index ee399885f..515a9dccd 100644 --- a/fpga/zsbl/uart.h +++ b/fpga/zsbl/uart.h @@ -1,6 +1,7 @@ #pragma once #include +// UART register addresses #define UART_BASE 0x10000000 #define UART_RBR UART_BASE + 0x00 @@ -16,6 +17,7 @@ #define UART_DLL UART_BASE + 0x00 #define UART_DLM UART_BASE + 0x01 +// Primary function prototypes void init_uart(uint32_t freq, uint32_t baud); void write_reg_u8(uintptr_t addr, uint8_t value); uint8_t read_reg_u8(uintptr_t addr); @@ -27,6 +29,7 @@ void print_uart_addr(uint64_t addr); void print_uart_hex(uint64_t addr, int n); void print_uart_byte(uint8_t byte); +// Print numbers in hex with specified widths #define print_uart_int(addr) print_uart_hex(addr, 4) #define print_uart_addr(addr) print_uart_hex(addr, 8) #define print_uart_byte(addr) print_uart_hex(addr, 1) From fcd88d6e6f4c0a1adc334f2d84eb2a8c82e93ee7 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Fri, 2 Aug 2024 15:14:30 -0500 Subject: [PATCH 175/219] Added functions to read registers and print information on failure. Also added a getTime function for a pretty boot display. --- fpga/zsbl/fail.c | 19 +++++++++++++++++++ fpga/zsbl/fail.h | 4 ++++ fpga/zsbl/riscv.S | 29 +++++++++++++++++++++++++++++ fpga/zsbl/riscv.h | 7 +++++++ fpga/zsbl/time.c | 20 ++++++++++++++++++++ fpga/zsbl/time.h | 5 +++++ 6 files changed, 84 insertions(+) create mode 100644 fpga/zsbl/fail.c create mode 100644 fpga/zsbl/fail.h create mode 100644 fpga/zsbl/riscv.S create mode 100644 fpga/zsbl/riscv.h create mode 100644 fpga/zsbl/time.c create mode 100644 fpga/zsbl/time.h diff --git a/fpga/zsbl/fail.c b/fpga/zsbl/fail.c new file mode 100644 index 000000000..4e6cd8db0 --- /dev/null +++ b/fpga/zsbl/fail.c @@ -0,0 +1,19 @@ +#include "fail.h" +#include "uart.h" +#include "riscv.h" +#include "time.h" + +void fail() { + // Get address that led to failure + register uint64_t addr; + asm volatile ("mv %0, ra" : "=r"(addr) : : "memory"); + + // Print message + print_time(); + println_with_addr("Failed at: 0x", addr); + + // Loop forever + while(1) { + + } +} diff --git a/fpga/zsbl/fail.h b/fpga/zsbl/fail.h new file mode 100644 index 000000000..da1a2e405 --- /dev/null +++ b/fpga/zsbl/fail.h @@ -0,0 +1,4 @@ +#pragma once +#include + +void fail(); diff --git a/fpga/zsbl/riscv.S b/fpga/zsbl/riscv.S new file mode 100644 index 000000000..7f400b1b2 --- /dev/null +++ b/fpga/zsbl/riscv.S @@ -0,0 +1,29 @@ +.section .text +.globl read_mcycle +.type read_mcycle, @function +read_mcycle: + csrr a0, mcycle + ret + +.section .text +.globl get_ra +.type get_ra, @function +get_ra: + mv a0, ra + ret + +.section .text +.globl set_status_fs +.type set_status_fs, @function +set_status_fs: + lui t1, 0x6 + csrs mstatus, t1 + ret + +.section .text +.globl clear_status_fs +.type clear_status_fs, @function +clear_status_fs: + lui t1, 0x6 + csrc mstatus, t1 + ret diff --git a/fpga/zsbl/riscv.h b/fpga/zsbl/riscv.h new file mode 100644 index 000000000..a27cd48d6 --- /dev/null +++ b/fpga/zsbl/riscv.h @@ -0,0 +1,7 @@ +#pragma once +#include + +uint64_t read_mcycle(); +uint64_t get_ra(); +void set_status_fs(); +void clear_status_fs(); diff --git a/fpga/zsbl/time.c b/fpga/zsbl/time.c new file mode 100644 index 000000000..43ac085b7 --- /dev/null +++ b/fpga/zsbl/time.c @@ -0,0 +1,20 @@ +#include "time.h" +#include "boot.h" +#include "riscv.h" +#include "uart.h" + +float getTime() { + set_status_fs(); + float numCycles = (float)read_mcycle(); + float ret = numCycles/SYSTEMCLOCK; + // clear_status_fs(); + return ret; +} + +void print_time() { + print_uart("["); + set_status_fs(); + print_uart_float(getTime(),5); + clear_status_fs(); + print_uart("] "); +} diff --git a/fpga/zsbl/time.h b/fpga/zsbl/time.h new file mode 100644 index 000000000..6cd928b88 --- /dev/null +++ b/fpga/zsbl/time.h @@ -0,0 +1,5 @@ +#pragma once +#include + +float getTime(); +void print_time(); From 897f6561cd53fa3875ddd4a14bc4697369f562c7 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Fri, 2 Aug 2024 15:19:52 -0500 Subject: [PATCH 176/219] New bootloader now works. Added special print functions and print messages. sdclk is set to 3MHz after initialization currently. --- fpga/zsbl/boot.c | 92 +++++++++++++++++++++++++++++++++++------------- fpga/zsbl/boot.h | 2 ++ fpga/zsbl/gpt.c | 8 +++++ fpga/zsbl/sd.c | 63 ++++++++++++++++++++++++--------- fpga/zsbl/spi.c | 6 +++- fpga/zsbl/spi.h | 1 + fpga/zsbl/uart.c | 40 +++++++++++++++++++-- fpga/zsbl/uart.h | 11 ++++++ 8 files changed, 179 insertions(+), 44 deletions(-) diff --git a/fpga/zsbl/boot.c b/fpga/zsbl/boot.c index 7b2e9af7d..e47b34e2f 100644 --- a/fpga/zsbl/boot.c +++ b/fpga/zsbl/boot.c @@ -4,6 +4,9 @@ #include "uart.h" #include "spi.h" #include "sd.h" +#include "time.h" +#include "riscv.h" +#include "fail.h" /* int disk_read(BYTE * buf, LBA_t sector, UINT count, BYTE card_type) { */ @@ -34,11 +37,31 @@ /* return 0;; */ /* } */ -#define SYSTEMCLOCK 20000000 +// Need to convert this +/* void print_progress(size_t count, size_t max) { */ +/* const int bar_width = 50; */ + +/* float progress = (float) count / max; */ +/* int bar_length = progress * bar_width; */ + +/* printf("\r["); */ +/* for (int i = 0; i < bar_length; ++i) { */ +/* printf("#"); */ +/* } */ +/* for (int i = bar_length; i < bar_width; ++i) { */ +/* printf("-"); */ +/* } */ +/* printf("] %.2f%%", progress * 100); */ + +/* fflush(stdout); */ +/* } */ int disk_read(BYTE * buf, LBA_t sector, UINT count) { uint64_t r; UINT i; + volatile uint8_t *p = buf; + + UINT modulus = count/50; uint8_t crc = 0; crc = crc7(crc, 0x40 | SD_CMD_READ_BLOCK_MULTIPLE); @@ -52,48 +75,69 @@ int disk_read(BYTE * buf, LBA_t sector, UINT count) { print_uart("disk_read: CMD18 failed. r = 0x"); print_uart_byte(r); print_uart("\r\n"); - return -1; + fail(); + // return -1; } + print_uart("\r Blocks loaded: "); + print_uart("0"); + print_uart("/"); + print_uart_dec(count); // write_reg(SPI_CSMODE, SIFIVE_SPI_CSMODE_MODE_HOLD); // Begin reading blocks for (i = 0; i < count; i++) { uint16_t crc, crc_exp; - - // Read the data token - r = spi_readbyte(); - /* if (r != SD_DATA_TOKEN) { */ - /* print_uart("Didn't receive data token first thing. Shoot: "); */ - /* print_uart_byte(r & 0xff); */ - /* print_uart("\r\n"); */ - /* return -1; */ - /* } */ + uint64_t n = 0; // Wait for data token - while((r & 0xff) != SD_DATA_TOKEN); + while((r = spi_dummy()) != SD_DATA_TOKEN); + // println_with_byte("Received data token: 0x", r & 0xff); + // println_with_dec("Block ", i); // Read block into memory. - for (int j = 0; j < 8; j++) { - *buf = sd_read64(&crc); - buf = buf + 64; - } - + /* for (int j = 0; j < 64; j++) { */ + /* *buf = sd_read64(&crc); */ + /* println_with_addr("0x", *buf); */ + /* buf = buf + 64; */ + /* } */ + crc = 0; + n = 512; + do { + uint8_t x = spi_dummy(); + *p++ = x; + crc = crc16(crc, x); + } while (--n > 0); + // Read CRC16 and check - crc_exp = ((uint16_t)spi_txrx(0xff) << 8); - crc_exp |= spi_txrx(0xff); + crc_exp = ((uint16_t)spi_dummy() << 8); + crc_exp |= spi_dummy(); if (crc != crc_exp) { print_uart("Stinking CRC16 didn't match on block read.\r\n"); print_uart_int(i); print_uart("\r\n"); - return -1; + //return -1; + fail(); } - + + if ( (i % modulus) == 0 ) { + print_uart("\r Blocks loaded: "); + print_uart_dec(i); + print_uart("/"); + print_uart_dec(count); + } + } sd_cmd(SD_CMD_STOP_TRANSMISSION, 0, 0x01); + + print_uart("\r Blocks loaded: "); + print_uart_dec(count); + print_uart("/"); + print_uart_dec(count); // write_reg(SPI_CSMODE, SIFIVE_SPI_CSMODE_MODE_AUTO); //spi_txrx(0xff); + print_uart("\r\n"); return 0; } @@ -106,7 +150,7 @@ void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) { // Initialize UART for messages init_uart(20000000, 115200); - + // Print the wally banner print_uart(BANNER); @@ -114,10 +158,8 @@ void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) { /* print_uart_dec(SYSTEMCLOCK); */ /* print_uart("\r\n"); */ - println_with_dec("Hello, does this work? Here's the clock: ", SYSTEMCLOCK); - // Intialize the SD card - init_sd(SYSTEMCLOCK, SYSTEMCLOCK/2); + init_sd(SYSTEMCLOCK, 3000000); ret = gpt_load_partitions(); } diff --git a/fpga/zsbl/boot.h b/fpga/zsbl/boot.h index 087550326..25b8a5fcc 100644 --- a/fpga/zsbl/boot.h +++ b/fpga/zsbl/boot.h @@ -32,5 +32,7 @@ typedef QWORD LBA_t; // Export disk_read int disk_read(BYTE * buf, LBA_t sector, UINT count); +#define SYSTEMCLOCK 20000000 + #endif // WALLYBOOT diff --git a/fpga/zsbl/gpt.c b/fpga/zsbl/gpt.c index 9af396469..99f74ec3a 100644 --- a/fpga/zsbl/gpt.c +++ b/fpga/zsbl/gpt.c @@ -11,11 +11,13 @@ int gpt_load_partitions() { int ret = 0; //ret = disk_read(/* BYTE * buf, LBA_t sector, UINT count, BYTE card_type */); + print_time(); println("Getting GPT information."); ret = disk_read(lba1_buf, 1, 1); gpt_pth_t *lba1 = (gpt_pth_t *)lba1_buf; + print_time(); println("Getting partition entries."); BYTE lba2_buf[512]; ret = disk_read(lba2_buf, (LBA_t)lba1->partition_entries_lba, 1); @@ -26,6 +28,7 @@ int gpt_load_partitions() { partition_entries_t *kernel = (partition_entries_t *)(lba2_buf + 256); // Load device tree + print_time(); println_with_int("Loading device tree at: 0x", FDT_ADDRESS); ret = disk_read((BYTE *)FDT_ADDRESS, fdt->first_lba, fdt->last_lba - fdt->first_lba + 1); if (ret < 0) { @@ -34,6 +37,7 @@ int gpt_load_partitions() { } // Load OpenSBI + print_time(); println_with_int("Loading OpenSBI at: 0x", OPENSBI_ADDRESS); ret = disk_read((BYTE *)OPENSBI_ADDRESS, opensbi->first_lba, opensbi->last_lba - opensbi->first_lba + 1); if (ret < 0) { @@ -42,6 +46,7 @@ int gpt_load_partitions() { } // Load Linux + print_time(); println_with_int("Loading Linux Kernel at: 0x", KERNEL_ADDRESS); ret = disk_read((BYTE *)KERNEL_ADDRESS, kernel->first_lba,kernel->last_lba - kernel->first_lba + 1); if (ret < 0) { @@ -49,5 +54,8 @@ int gpt_load_partitions() { return -1; } + print_time(); + println("Done! Flashing LEDs and jumping to OpenSBI..."); + return 0; } diff --git a/fpga/zsbl/sd.c b/fpga/zsbl/sd.c index cacf40438..484fd65c0 100644 --- a/fpga/zsbl/sd.c +++ b/fpga/zsbl/sd.c @@ -1,6 +1,8 @@ #include "sd.h" #include "spi.h" #include "uart.h" +#include "fail.h" +#include "time.h" // Parallel byte update CRC7-CCITT algorithm. // The result is the CRC7 result, left shifted over by 1 @@ -36,9 +38,11 @@ uint16_t crc16(uint16_t crc, uint8_t data) { // watermark and interrupt features to determine when a // transfer is complete. This should save on cycles since // no arbitrary delays need to be added. + uint64_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc) { uint8_t response_len; uint8_t i; + uint8_t shiftAmnt; uint64_t r; uint8_t rbyte; @@ -53,6 +57,7 @@ uint64_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc) { break; case 12: response_len = R1B_RESPONSE; + break; default: response_len = R1_RESPONSE; break; @@ -70,6 +75,7 @@ uint64_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc) { // Write all 7 bytes into transfer fifo // spi_sendbyte(0xff); + spi_dummy(); spi_sendbyte(0x40 | cmd); spi_sendbyte(arg >> 24); spi_sendbyte(arg >> 16); @@ -89,30 +95,34 @@ uint64_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc) { // Send "dummy signals". Since SPI is duplex, // useless bytes must be transferred - for (i = 0; i < response_len; i++) { - spi_sendbyte(0xFF); - } + /* for (i = 0; i < response_len; i++) { */ + /* spi_sendbyte(0xFF); */ + /* } */ - // Wait for transfer fifo again - waittx(); + /* // Wait for transfer fifo again */ + /* waittx(); */ // Wait for actual response from SD card // All responses start with a 0. Output of SDCIn is high, unless // a message is being transferred. do { - rbyte = spi_txrx(0xff); + rbyte = spi_dummy(); } while ( (rbyte & 0x80) != 0 ); - r = r | (rbyte << ((response_len - 1)*8)); + // Note about the compiler. In order to compile as sll instead of + // sllw, the number to shift has to be a 64 bit number. + r = ((uint64_t)rbyte) << ((response_len - 1)*8); // Read rxfifo response for (i = 1; i < response_len; i++) { - rbyte = spi_readbyte(); - r = r | (rbyte << ((response_len - 1 - i)*8)); + rbyte = spi_dummy(); + r = r | (((uint64_t)rbyte) << ((response_len - 1 - i)*8)); } if (cmd != 18) { write_reg(SPI_CSMODE, SIFIVE_SPI_CSMODE_MODE_AUTO); + } else { + spi_dummy(); } return r; } // sd_cmd @@ -122,16 +132,16 @@ uint64_t sd_read64(uint16_t * crc) { uint8_t rbyte; int i; - for (i = 0; i < 8; i++) { - spi_sendbyte(0xFF); - } + /* for (i = 0; i < 8; i++) { */ + /* spi_sendbyte(0xFF); */ + /* } */ - waittx(); + /* waittx(); */ for (i = 0; i < 8; i++) { - rbyte = spi_readbyte(); + rbyte = spi_dummy(); *crc = crc16(*crc, rbyte); - r = r | (rbyte << ((8 - 1 - i)*8)); + r = r | ((uint64_t)(rbyte) << ((8 - 1 - i)*8)); } return r; @@ -147,11 +157,15 @@ uint64_t sd_read64(uint16_t * crc) { // This first initializes the SPI peripheral then initializes the SD // card itself. We use the uart to display anything that goes wrong. int init_sd(uint32_t freq, uint32_t sdclk){ + print_time(); + println("Initializing SPI Controller."); spi_init(); uint64_t r; uint32_t newClockDiv; + int n; + print_time(); println("Initializing SD Card in SPI mode."); // This is necessary. This is the card's pre-init state initialization. write_reg(SPI_CSMODE, SIFIVE_SPI_CSMODE_MODE_OFF); @@ -165,31 +179,48 @@ int init_sd(uint32_t freq, uint32_t sdclk){ // Initializes SD card into SPI mode if CS is asserted '0' // We expect to get the R1 response 0x01 which means that the // card has been put into the idle state. + print_time(); print_uart("CMD0: "); + n = 0; do { r = CMD0(); + n++; + if (n == 1000) { + fail(); + } } while ( r != 0x01 ); println_with_r1("Success, r = 0x", r & 0xff); // CMD8 ------------------------------------------------------------- - // + // + print_time(); print_uart("CMD8: "); r = CMD8(); if ((r & 0x000000ff0000ffff) != 0x01000001aa) { println_with_r7("Failed, 0x", r); + fail(); } println_with_r7("Success, 0x", r); // ACMD41 ----------------------------------------------------------- + print_time(); print_uart("ACMD41: "); + n = 0; do { CMD55(); r = ACMD41(); + n++; + if (n == 1000) { + fail(); + } } while (r == 0x1); println_with_r1("Success, r = 0x", r & 0xff); + print_time(); println_with_dec("New clock frequency: ", (uint64_t)sdclk); spi_set_clock(freq, sdclk); + + print_time(); println("SD card is initialized."); } diff --git a/fpga/zsbl/spi.c b/fpga/zsbl/spi.c index b8829b12e..5b23c85b6 100644 --- a/fpga/zsbl/spi.c +++ b/fpga/zsbl/spi.c @@ -55,11 +55,15 @@ /* } */ uint8_t spi_txrx(uint8_t byte) { - spi_sendbyte(0xFF); + spi_sendbyte(byte); waittx(); return spi_readbyte(); } +uint8_t spi_dummy() { + return spi_txrx(0xff); +} + /* inline uint8_t spi_readbyte() { */ /* return read_reg(SPI_RXDATA); */ /* } */ diff --git a/fpga/zsbl/spi.h b/fpga/zsbl/spi.h index a662fce86..d2bf1191c 100644 --- a/fpga/zsbl/spi.h +++ b/fpga/zsbl/spi.h @@ -50,6 +50,7 @@ //inline void waittx(); //inline void waitrx(); uint8_t spi_txrx(uint8_t byte); +uint8_t spi_dummy(); //inline uint8_t spi_readbyte(); uint64_t spi_read64(); void spi_init(); diff --git a/fpga/zsbl/uart.c b/fpga/zsbl/uart.c index d7ac9b558..8c25f17ca 100644 --- a/fpga/zsbl/uart.c +++ b/fpga/zsbl/uart.c @@ -1,6 +1,5 @@ #include "uart.h" - void write_reg_u8(uintptr_t addr, uint8_t value) { volatile uint8_t *loc_addr = (volatile uint8_t *)addr; @@ -78,7 +77,7 @@ void print_uart_dec(uint64_t addr) { // floor(log(2^64)) = 19 char str[19] = {'\0'}; - uint8_t length = 0; + uint8_t length = 1; uint64_t cur = addr; while (cur != 0) { @@ -94,6 +93,43 @@ void print_uart_dec(uint64_t addr) { } } +// Print a floating point number on the UART +void print_uart_float(float num, int precision) { + char str[32] = {'\0'}; + char digit; + uint8_t length = precision + 1; + int i; + uint64_t cur; + + str[precision] = '.'; + + int pow = 1; + + // Calculate power for precision + for (i = 0; i < precision; i++) { + pow = pow * 10; + } + + cur = (uint64_t)(num * pow); + for (i = 0; i < precision; i++) { + digit = bin_to_hex_table[cur % 10]; + str[i] = digit; + cur = cur / 10; + } + + cur = (uint64_t)num; + do { + digit = bin_to_hex_table[cur % 10]; + str[length] = digit; + cur = cur/10; + length++; + } while (cur != 0); + + for (i = length; i > -1; i--) { + write_serial(str[i]); + } +} + /* void print_uart_int(uint32_t addr) */ /* { */ /* int i; */ diff --git a/fpga/zsbl/uart.h b/fpga/zsbl/uart.h index 515a9dccd..cbdcc5941 100644 --- a/fpga/zsbl/uart.h +++ b/fpga/zsbl/uart.h @@ -1,5 +1,7 @@ #pragma once #include +#include "riscv.h" +#include "time.h" // UART register addresses #define UART_BASE 0x10000000 @@ -28,6 +30,8 @@ void print_uart_dec(uint64_t addr); void print_uart_addr(uint64_t addr); void print_uart_hex(uint64_t addr, int n); void print_uart_byte(uint8_t byte); +void print_uart_float(float num, int precision); +// void print_time(); // Print numbers in hex with specified widths #define print_uart_int(addr) print_uart_hex(addr, 4) @@ -44,4 +48,11 @@ void print_uart_byte(uint8_t byte); #define println_with_addr(msg, num) print_uart(msg); print_uart_addr(num); print_uart("\r\n") #define println_with_r1(msg, num) print_uart(msg); print_r1(num); print_uart("\r\n") #define println_with_r7(msg, num) print_uart(msg); print_r7(num); print_uart("\r\n") +#define println_with_float(msg, num) print_uart(msg); set_status_fs(); print_uart_float(num,5); clear_status_fs(); print_uart("\r\n") + +/* #define print_time() print_uart("["); \ */ +/* set_status_fs(); \ */ +/* print_uart_float(getTime(),5); \ */ +/* clear_status_fs(); \ */ +/* print_uart("] ") */ From 1e20d5aea66ff581f0e1b111aa03982a5daa5d95 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Fri, 2 Aug 2024 15:21:15 -0500 Subject: [PATCH 177/219] Added preload pointing to data.mem in ram1p1rwbe.sv --- src/generic/mem/ram1p1rwbe.sv | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index e2e76288b..287607c9e 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -89,6 +89,10 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE // end // end + `ifdef VERILATOR + import "DPI-C" function string getenvval(input string env_name); + `endif + initial if (PRELOAD_ENABLED) begin if (WIDTH == 64) begin From 11a057b0b35c849c7d184f957c228be957fcbb61 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Fri, 2 Aug 2024 15:33:57 -0500 Subject: [PATCH 178/219] Updated wally source files for zsbl testing. --- config/derivlist.txt | 3 ++- fpga/constraints/constraints-ArtyA7.xdc | 17 +++++++++++------ src/uncore/spi_apb.sv | 18 +++++++++++------- src/uncore/uncore.sv | 2 +- src/wally/wallypipelinedsoc.sv | 2 +- testbench/wallywrapper.sv | 16 ++++++++++------ 6 files changed, 36 insertions(+), 22 deletions(-) diff --git a/config/derivlist.txt b/config/derivlist.txt index 1edd20b7b..9d864f1f5 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -50,7 +50,8 @@ PLIC_NUM_SRC 32'd53 deriv fpga buildroot BOOTROM_PRELOAD 1 UNCORE_RAM_BASE 64'h2000 -UNCORE_RAM_RANGE 64'hFFF +UNCORE_RAM_RANGE 64'h1FFF +BOOTROM_RANGE 64'hFFF EXT_MEM_SUPPORTED 1 EXT_MEM_BASE 64'h80000000 EXT_MEM_RANGE 64'h0FFFFFFF diff --git a/fpga/constraints/constraints-ArtyA7.xdc b/fpga/constraints/constraints-ArtyA7.xdc index 4e156601b..b8f98d430 100644 --- a/fpga/constraints/constraints-ArtyA7.xdc +++ b/fpga/constraints/constraints-ArtyA7.xdc @@ -97,16 +97,21 @@ set_property IOSTANDARD LVCMOS33 [get_ports {south_reset}] #set_property PULLUP true [get_ports {SDCCmd}] #set_property PULLUP true [get_ports {SDCCD}] -set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[3]}] -set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[2]}] -set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[1]}] -set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[0]}] +# SDCDat[3] +set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCS}] +# set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[2]}] +# set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[1]}] +# SDCDat[0] +set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCIn}] set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCLK}] set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCmd}] set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCD}] -set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCDat[*]}] -set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 21.000 [get_ports {SDCDat[*]}] +set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCCS}] +set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 21.000 [get_ports {SDCCS}] + +set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCIn}] +set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 21.000 [get_ports {SDCIn}] set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.000 [get_ports {SDCCmd}] set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 6.000 [get_ports {SDCCmd}] diff --git a/src/uncore/spi_apb.sv b/src/uncore/spi_apb.sv index e9c04bca8..cadb49dfb 100644 --- a/src/uncore/spi_apb.sv +++ b/src/uncore/spi_apb.sv @@ -148,6 +148,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( // APB access assign Entry = {PADDR[7:2],2'b00}; // 32-bit word-aligned accesses assign Memwrite = PWRITE & PENABLE & PSEL; // Only write in access phase + // JACOB: This shouldn't behave this way assign PREADY = TransmitInactive; // Tie PREADY to transmission for hardware interlock // Account for subword read/write circuitry @@ -366,22 +367,25 @@ module spi_apb import cvw::*; #(parameter cvw_t P) ( assign TransmitInactive = ((state == INTER_CS) | (state == CS_INACTIVE) | (state == INTER_XFR) | (ReceiveShiftFullDelayPCLK & ZeroDelayHoldMode)); assign Active0 = (state == ACTIVE_0); - // Signal tracks which edge of sck to shift data + // Signal tracks which edge of sck to shift data + // Jacob: We need to confirm that this represents the actual polarity and phase options for sampling. + // The first option now samples on the leading edge and shifts on the falling edge like it's supposed to. + // We need to confirm the validity of the other options. always_comb case(SckMode[1:0]) - 2'b00: ShiftEdge = ~SPICLK & SCLKenable; - 2'b01: ShiftEdge = (SPICLK & |(FrameCount) & SCLKenable); - 2'b10: ShiftEdge = SPICLK & SCLKenable; - 2'b11: ShiftEdge = (~SPICLK & |(FrameCount) & SCLKenable); + 2'b00: ShiftEdge = SPICLK & SCLKenable; + 2'b01: ShiftEdge = (SPICLK & |(FrameCount) & SCLKenable); // Probably wrong + 2'b10: ShiftEdge = ~SPICLK & SCLKenable; // Probably wrong + 2'b11: ShiftEdge = (~SPICLK & |(FrameCount) & SCLKenable); // Probably wrong default: ShiftEdge = SPICLK & SCLKenable; endcase // Transmit shift register assign TransmitDataEndian = Format[0] ? {TransmitFIFOReadData[0], TransmitFIFOReadData[1], TransmitFIFOReadData[2], TransmitFIFOReadData[3], TransmitFIFOReadData[4], TransmitFIFOReadData[5], TransmitFIFOReadData[6], TransmitFIFOReadData[7]} : TransmitFIFOReadData[7:0]; always_ff @(posedge PCLK) - if(~PRESETn) TransmitShiftReg <= 8'b0; + if(~PRESETn) TransmitShiftReg <= 8'b0; // Temporarily changing to 1s else if (TransmitShiftRegLoad) TransmitShiftReg <= TransmitDataEndian; - else if (ShiftEdge & Active) TransmitShiftReg <= {TransmitShiftReg[6:0], 1'b0}; + else if (ShiftEdge & Active) TransmitShiftReg <= {TransmitShiftReg[6:0], TransmitShiftReg[0]}; // Temporarily changing to 1s assign SPIOut = TransmitShiftReg[7]; diff --git a/src/uncore/uncore.sv b/src/uncore/uncore.sv index 7de407c63..21dd956ed 100644 --- a/src/uncore/uncore.sv +++ b/src/uncore/uncore.sv @@ -172,7 +172,7 @@ module uncore import cvw::*; #(parameter cvw_t P)( .PREADY(PREADY[5]), .PRDATA(PRDATA[5]), .SPIOut(SDCCmd), .SPIIn(SDCIn), .SPICS(SDCCS), .SPICLK(SDCCLK), .SPIIntr(SDCIntr)); end else begin : sdc - assign SDCCmd = '0; assign SDCCS = 1'b0; assign SDCIntr = 1'b0; assign SDCCLK = 1'b0; + assign SDCCmd = '0; assign SDCCS = 4'b0; assign SDCIntr = 1'b0; assign SDCCLK = 1'b0; end diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index 7ad173b78..77845aff3 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -90,7 +90,7 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) ( .UARTSout, .MTIME_CLINT, .SPIIn, .SPIOut, .SPICS, .SPICLK, .SDCIn, .SDCCmd, .SDCCS, .SDCCLK); end else begin assign {HRDATA, HREADY, HRESP, HSELEXT, MTimerInt, MSwInt, MExtInt, SExtInt, - MTIME_CLINT, GPIOOUT, GPIOEN, UARTSout, SPIOut, SPICS} = '0; + MTIME_CLINT, GPIOOUT, GPIOEN, UARTSout, SPIOut, SPICS, SPICLK, SDCCmd, SDCCS, SDCCLK} = '0; end endmodule diff --git a/testbench/wallywrapper.sv b/testbench/wallywrapper.sv index 2794240be..b326bb810 100644 --- a/testbench/wallywrapper.sv +++ b/testbench/wallywrapper.sv @@ -32,7 +32,7 @@ module wallywrapper import cvw::*;( input logic clk, input logic reset_ext, input logic SPIIn, - input logic SDCIntr + input logic SDCIn ); `include "parameter-defs.vh" @@ -56,10 +56,14 @@ module wallywrapper import cvw::*;( logic UARTSin, UARTSout; logic SPIOut; logic [3:0] SPICS; + logic SPICLK; + + logic SDCCmd; + logic [3:0] SDCCS; + logic SDCCLK; logic HREADY; logic HSELEXT; - logic HSELEXTSDC; // instantiate device to be tested @@ -71,9 +75,9 @@ module wallywrapper import cvw::*;( assign HRDATAEXT = 0; - wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, .HSELEXTSDC, - .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, - .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, - .UARTSin, .UARTSout, .SPIIn, .SPIOut, .SPICS, .SDCIntr); + wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, + .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, + .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, + .UARTSin, .UARTSout, .SPIIn, .SPIOut, .SPICS, .SPICLK, .SDCIn, .SDCCmd, .SDCCS, .SDCCLK); endmodule From 83b0a83d5cbe169f3e62b851e00084b9885a3990 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Fri, 2 Aug 2024 15:35:18 -0500 Subject: [PATCH 179/219] Removed HSELEXTSDC and fixed SD card pin definitions. --- fpga/src/fpgaTopArtyA7.sv | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/fpga/src/fpgaTopArtyA7.sv b/fpga/src/fpgaTopArtyA7.sv index 31848f33e..712f67869 100644 --- a/fpga/src/fpgaTopArtyA7.sv +++ b/fpga/src/fpgaTopArtyA7.sv @@ -42,10 +42,11 @@ module fpgaTop output UARTSout, // SDC Signals connecting to an SPI peripheral - input [3:0] SDCDat, + input SDCIn, output SDCCLK, output SDCCmd, - output SDCCD, + output SDCCS, + input SDCCD, // Memory signals inout [15:0] ddr3_dq, @@ -199,10 +200,8 @@ module fpgaTop assign cpu_reset = bus_struct_reset; assign calib = c0_init_calib_complete; - logic [3:0] SDCCS; - assign SDCCD = SDCCS[0]; - logic SDCIn; - assign SDCIn = SDCDat[0]; + logic [3:0] SDCCSin; + assign SDCCS = SDCCSin[0]; // mmcm @@ -243,14 +242,14 @@ module fpgaTop .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, - .UARTSin, .UARTSout, .SDCIn, .SDCCmd, .SDCCS, .SDCCLK); + .UARTSin, .UARTSout, .SDCIn, .SDCCmd, .SDCCS(SDCCSin), .SDCCLK); // ahb lite to axi bridge xlnx_ahblite_axi_bridge xlnx_ahblite_axi_bridge_0 (.s_ahb_hclk(CPUCLK), .s_ahb_hresetn(peripheral_aresetn), - .s_ahb_hsel(HSELEXT | HSELEXTSDC), + .s_ahb_hsel(HSELEXT), .s_ahb_haddr(HADDR[31:0]), .s_ahb_hprot(HPROT), .s_ahb_htrans(HTRANS), From ad9c98c19cd46a3f05fc26d086f70b1faead83e7 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Fri, 2 Aug 2024 15:36:06 -0500 Subject: [PATCH 180/219] Added file necessary to split boot.mem into boot.mem and data.mem. --- fpga/zsbl/splitfile.sh | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100755 fpga/zsbl/splitfile.sh diff --git a/fpga/zsbl/splitfile.sh b/fpga/zsbl/splitfile.sh new file mode 100755 index 000000000..1e367c872 --- /dev/null +++ b/fpga/zsbl/splitfile.sh @@ -0,0 +1,18 @@ +# Acquired from here. +# https://stackoverflow.com/questions/3066948/how-to-file-split-at-a-line-number +file_name=$1 + +# set first K lines: +K=512 + +# line count (N): +N=$(wc -l < $file_name) + +# length of the bottom file: +L=$(( $N - $K )) + +# create the top of file: +head -n $K $file_name > boot.mem + +# create bottom of file: +tail -n $L $file_name > data.mem From 665396fdb3f1b8d0435207987c9b04926d1e9db1 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Tue, 6 Aug 2024 16:57:57 -0500 Subject: [PATCH 181/219] SD card is now mountable on the fpga. The relevant files have been added. The most important changes are in the buildroot linux configuration and device tree. --- fpga/constraints/constraints-ArtyA7.xdc | 8 ++- fpga/src/fpgaTopArtyA7.sv | 3 +- fpga/zsbl/boot.c | 2 +- linux/Makefile | 2 +- .../buildroot-2023.05.1/linux.config | 13 ++--- linux/devicetree/wally-artya7.dts | 51 ++++++++++++++----- 6 files changed, 55 insertions(+), 24 deletions(-) diff --git a/fpga/constraints/constraints-ArtyA7.xdc b/fpga/constraints/constraints-ArtyA7.xdc index b8f98d430..394c58dda 100644 --- a/fpga/constraints/constraints-ArtyA7.xdc +++ b/fpga/constraints/constraints-ArtyA7.xdc @@ -35,6 +35,7 @@ set_property IOSTANDARD LVCMOS33 [get_ports {GPO[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {GPO[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {GPO[0]}] set_max_delay -to [get_ports {GPO[*]}] 20.000 + set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 0.000 [get_ports {GPO[*]}] set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [get_ports {GPO[*]}] @@ -106,18 +107,21 @@ set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33 PULLUP true} [get_ports { set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCLK}] set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCmd}] set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCD}] +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCWP}] + set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCCS}] -set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 21.000 [get_ports {SDCCS}] +set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCCS}] set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCIn}] -set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 21.000 [get_ports {SDCIn}] +set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCIn}] set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.000 [get_ports {SDCCmd}] set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 6.000 [get_ports {SDCCmd}] set_output_delay -clock [get_clocks SPISDCClock] 0.000 [get_ports SDCCLK] + #set_multicycle_path -from [get_pins xlnx_ddr3_c0/u_xlnx_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/init_calib_complete_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10 set_max_delay -datapath_only -from [get_pins xlnx_ddr3_c0/u_xlnx_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/init_calib_complete_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 20.000 diff --git a/fpga/src/fpgaTopArtyA7.sv b/fpga/src/fpgaTopArtyA7.sv index 712f67869..5d038ad0f 100644 --- a/fpga/src/fpgaTopArtyA7.sv +++ b/fpga/src/fpgaTopArtyA7.sv @@ -47,6 +47,7 @@ module fpgaTop output SDCCmd, output SDCCS, input SDCCD, + input SDCWP, // Memory signals inout [15:0] ddr3_dq, @@ -194,7 +195,7 @@ module fpgaTop wire mmcm1_locked; - assign GPIOIN = {28'b0, GPI}; + assign GPIOIN = {25'b0, SDCCD, SDCWP, 1'b0, GPI}; assign GPO = GPIOOUT[4:0]; assign ahblite_resetn = peripheral_aresetn; assign cpu_reset = bus_struct_reset; diff --git a/fpga/zsbl/boot.c b/fpga/zsbl/boot.c index e47b34e2f..52473ab46 100644 --- a/fpga/zsbl/boot.c +++ b/fpga/zsbl/boot.c @@ -159,7 +159,7 @@ void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) { /* print_uart("\r\n"); */ // Intialize the SD card - init_sd(SYSTEMCLOCK, 3000000); + init_sd(SYSTEMCLOCK, 5000000); ret = gpt_load_partitions(); } diff --git a/linux/Makefile b/linux/Makefile index 6f7b6c7fb..b0b15ce7b 100644 --- a/linux/Makefile +++ b/linux/Makefile @@ -102,7 +102,7 @@ $(IMAGES)/busybox: # Generating new Buildroot directories -------------------------------- # This directive should be run as: make install BUILDROOT=path/to/buildroot -download: $(BUILDROOT)/package/fpga-axi-sdc $(WALLYBOARD) +download: $(WALLYBOARD) cp $(WALLYBOARD)/main.config $(BUILDROOT)/.config # CONFIG DEPENDENCIES 2023.05.1 --------------------------------------- diff --git a/linux/buildroot-config-src/buildroot-2023.05.1/linux.config b/linux/buildroot-config-src/buildroot-2023.05.1/linux.config index e348cde78..047be24c2 100644 --- a/linux/buildroot-config-src/buildroot-2023.05.1/linux.config +++ b/linux/buildroot-config-src/buildroot-2023.05.1/linux.config @@ -2,7 +2,7 @@ # Automatically generated file; DO NOT EDIT. # Linux/riscv 6.6.0 Kernel Configuration # -CONFIG_CC_VERSION_TEXT="riscv64-buildroot-linux-gnu-gcc.br_real (Buildroot 2023.05.3-dirty) 12.3.0" +CONFIG_CC_VERSION_TEXT="riscv64-buildroot-linux-gnu-gcc.br_real (Buildroot 2023.05.3) 12.3.0" CONFIG_CC_IS_GCC=y CONFIG_GCC_VERSION=120300 CONFIG_CLANG_VERSION=0 @@ -1042,7 +1042,7 @@ CONFIG_MMC_BLOCK_MINORS=8 # # CONFIG_MMC_DEBUG is not set # CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_SPI is not set +CONFIG_MMC_SPI=y # CONFIG_MMC_DW is not set # CONFIG_MMC_USDHI6ROL0 is not set # CONFIG_MMC_CQHCI is not set @@ -1455,7 +1455,7 @@ CONFIG_CRYPTO_HASH2=y # CONFIG_CRYPTO_POLY1305 is not set # CONFIG_CRYPTO_RMD160 is not set # CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set +CONFIG_CRYPTO_SHA256=y # CONFIG_CRYPTO_SHA512 is not set # CONFIG_CRYPTO_SHA3 is not set # CONFIG_CRYPTO_SM3_GENERIC is not set @@ -1527,13 +1527,14 @@ CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 # CONFIG_CRYPTO_LIB_POLY1305 is not set # CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_LIB_SHA256=y # end of Crypto library routines # CONFIG_CRC_CCITT is not set CONFIG_CRC16=y # CONFIG_CRC_T10DIF is not set # CONFIG_CRC64_ROCKSOFT is not set -# CONFIG_CRC_ITU_T is not set +CONFIG_CRC_ITU_T=y CONFIG_CRC32=y # CONFIG_CRC32_SELFTEST is not set CONFIG_CRC32_SLICEBY8=y @@ -1542,7 +1543,7 @@ CONFIG_CRC32_SLICEBY8=y # CONFIG_CRC32_BIT is not set # CONFIG_CRC64 is not set # CONFIG_CRC4 is not set -# CONFIG_CRC7 is not set +CONFIG_CRC7=y # CONFIG_LIBCRC32C is not set # CONFIG_CRC8 is not set # CONFIG_RANDOM32_SELFTEST is not set @@ -1599,7 +1600,7 @@ CONFIG_PRINTK_TIME=y # CONFIG_STACKTRACE_BUILD_ID is not set CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 CONFIG_CONSOLE_LOGLEVEL_QUIET=4 -CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_DYNAMIC_DEBUG is not set # CONFIG_DYNAMIC_DEBUG_CORE is not set diff --git a/linux/devicetree/wally-artya7.dts b/linux/devicetree/wally-artya7.dts index 87933bcc0..99b8ff00d 100644 --- a/linux/devicetree/wally-artya7.dts +++ b/linux/devicetree/wally-artya7.dts @@ -5,11 +5,11 @@ #size-cells = <0x02>; compatible = "wally-virt"; model = "wally-virt,qemu"; - + chosen { linux,initrd-end = <0x85c43a00>; linux,initrd-start = <0x84200000>; - bootargs = "root=/dev/vda ro console=ttyS0,115200"; + bootargs = "root=/dev/vda ro console=ttyS0,115200 loglevel=7"; stdout-path = "/soc/uart@10000000"; }; @@ -51,6 +51,25 @@ compatible = "simple-bus"; ranges; + refclk: refclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0x1312D00>; + clock-output-names = "xtal"; + }; + + gpio0: gpio@10060000 { + compatible = "sifive,gpio0"; + interrupt-parent = <0x03>; + interrupts = <3>; + reg = <0x00 0x10060000 0x00 0x1000>; + reg-names = "control"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + uart@10000000 { interrupts = <0x0a>; interrupt-parent = <0x03>; @@ -70,18 +89,24 @@ #address-cells = <0x00>; }; - mmc@13000 { - interrupts = <0x14>; - compatible = "riscv,axi-sd-card-1.0"; - reg = <0x00 0x13000 0x00 0x7F>; - fifo-depth = <256>; - bus-width = <4>; + spi@13000 { + compatible = "sifive,spi0"; interrupt-parent = <0x03>; - clock = <0x1312D00>; - max-frequency = <0x1312D00>; - cap-sd-highspeed; - cap-mmc-highspeed; - no-sdio; + interrupts = <0x14>; + reg = <0x0 0x13000 0x0 0x1000>; + reg-names = "control"; + clocks = <&refclk>; + + #address-cells = <1>; + #size-cells = <0>; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <5000000>; + voltage-ranges = <3300 3300>; + disable-wp; + // gpios = <&gpio0 6 1>; + }; }; clint@2000000 { From 954e21148f8aac040f9ed9d8742b1d58754276e2 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Tue, 6 Aug 2024 17:11:08 -0500 Subject: [PATCH 182/219] Removed line referring to local file in wally.tcl. --- fpga/generator/wally.tcl | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index 465d0c73a..b2e1e359e 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -92,8 +92,7 @@ if {$board=="ArtyA7"} { #source ../constraints/small-debug.xdc source ../constraints/small-debug-rvvi.xdc } else { - # source ../constraints/vcu-small-debug.xdc - source ../constraints/debug6.xdc + source ../constraints/vcu-small-debug.xdc } From 280b5baa59a5fdad57e1cae8eec4ef3f199c5da2 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Tue, 6 Aug 2024 17:28:50 -0500 Subject: [PATCH 183/219] Added header to new bootloader files. --- fpga/zsbl/boot.c | 77 ++++++++++++++++++----------------------------- fpga/zsbl/boot.h | 29 ++++++++++++++++++ fpga/zsbl/fail.c | 30 ++++++++++++++++++ fpga/zsbl/fail.h | 29 ++++++++++++++++++ fpga/zsbl/gpt.c | 29 ++++++++++++++++++ fpga/zsbl/gpt.h | 29 ++++++++++++++++++ fpga/zsbl/riscv.S | 29 ++++++++++++++++++ fpga/zsbl/riscv.h | 29 ++++++++++++++++++ fpga/zsbl/sd.c | 29 ++++++++++++++++++ fpga/zsbl/sd.h | 30 ++++++++++++++++++ fpga/zsbl/spi.c | 29 ------------------ fpga/zsbl/time.c | 29 ++++++++++++++++++ fpga/zsbl/time.h | 29 ++++++++++++++++++ fpga/zsbl/uart.c | 30 ++++++++++++++++++ fpga/zsbl/uart.h | 29 ++++++++++++++++++ 15 files changed, 409 insertions(+), 77 deletions(-) diff --git a/fpga/zsbl/boot.c b/fpga/zsbl/boot.c index 52473ab46..566393cb6 100644 --- a/fpga/zsbl/boot.c +++ b/fpga/zsbl/boot.c @@ -1,3 +1,32 @@ +/////////////////////////////////////////////////////////////////////// +// boot.c +// +// Written: Jacob Pease jacob.pease@okstate.edu 7/22/2024 +// +// Purpose: Main bootloader entry point +// +// +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the +// “License”); you may not use this file except in compliance with the +// License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an “AS IS” BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +// implied. See the License for the specific language governing +// permissions and limitations under the License. +/////////////////////////////////////////////////////////////////////// + #include #include "boot.h" #include "gpt.h" @@ -8,54 +37,6 @@ #include "riscv.h" #include "fail.h" -/* int disk_read(BYTE * buf, LBA_t sector, UINT count, BYTE card_type) { */ - -/* /\* This is not needed. This has everything to do with the FAT */ -/* filesystem stuff that I'm not including. All I need to do is */ -/* initialize the SD card and read from it. Anything in here that is */ -/* checking for potential errors, I'm going to have to temporarily */ -/* do without. */ -/* *\/ */ -/* // if (!count) return RES_PARERR; */ -/* /\* if (drv_status & STA_NOINIT) return RES_NOTRDY; *\/ */ - -/* uint32_t response[4]; */ -/* struct sdc_regs * regs = (struct sdc_regs *)SDC; */ - -/* /\* Convert LBA to byte address if needed *\/ */ -/* if (!(card_type & CT_BLOCK)) sector *= 512; */ -/* while (count > 0) { */ -/* UINT bcnt = count > MAX_BLOCK_CNT ? MAX_BLOCK_CNT : count; */ -/* unsigned bytes = bcnt * 512; */ -/* if (send_data_cmd(bcnt == 1 ? CMD17 : CMD18, sector, buf, bcnt, response) < 0) return 1; */ -/* if (bcnt > 1 && send_cmd(CMD12, 0, response) < 0) return 1; */ -/* sector += (card_type & CT_BLOCK) ? bcnt : bytes; */ -/* count -= bcnt; */ -/* buf += bytes; */ -/* } */ - -/* return 0;; */ -/* } */ - -// Need to convert this -/* void print_progress(size_t count, size_t max) { */ -/* const int bar_width = 50; */ - -/* float progress = (float) count / max; */ -/* int bar_length = progress * bar_width; */ - -/* printf("\r["); */ -/* for (int i = 0; i < bar_length; ++i) { */ -/* printf("#"); */ -/* } */ -/* for (int i = bar_length; i < bar_width; ++i) { */ -/* printf("-"); */ -/* } */ -/* printf("] %.2f%%", progress * 100); */ - -/* fflush(stdout); */ -/* } */ - int disk_read(BYTE * buf, LBA_t sector, UINT count) { uint64_t r; UINT i; diff --git a/fpga/zsbl/boot.h b/fpga/zsbl/boot.h index 25b8a5fcc..0c09a1e52 100644 --- a/fpga/zsbl/boot.h +++ b/fpga/zsbl/boot.h @@ -1,3 +1,32 @@ +/////////////////////////////////////////////////////////////////////// +// boot.h +// +// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024 +// +// Purpose: Header for boot.c, main bootloader entry point +// +// +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the +// “License”); you may not use this file except in compliance with the +// License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an “AS IS” BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +// implied. See the License for the specific language governing +// permissions and limitations under the License. +/////////////////////////////////////////////////////////////////////// + #ifndef WALLYBOOT #define WALLYBOOT 10000 diff --git a/fpga/zsbl/fail.c b/fpga/zsbl/fail.c index 4e6cd8db0..4430c4a8f 100644 --- a/fpga/zsbl/fail.c +++ b/fpga/zsbl/fail.c @@ -1,3 +1,33 @@ +/////////////////////////////////////////////////////////////////////// +// fail.c +// +// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024 +// +// Purpose: Prints information on the uart when a fatal bug is +// encountered. Will expand this later. +// +// +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the +// “License”); you may not use this file except in compliance with the +// License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an “AS IS” BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +// implied. See the License for the specific language governing +// permissions and limitations under the License. +/////////////////////////////////////////////////////////////////////// + #include "fail.h" #include "uart.h" #include "riscv.h" diff --git a/fpga/zsbl/fail.h b/fpga/zsbl/fail.h index da1a2e405..c965265d1 100644 --- a/fpga/zsbl/fail.h +++ b/fpga/zsbl/fail.h @@ -1,3 +1,32 @@ +/////////////////////////////////////////////////////////////////////// +// fail.h +// +// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024 +// +// Purpose: Function prototype for fail, +// +// +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the +// “License”); you may not use this file except in compliance with the +// License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an “AS IS” BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +// implied. See the License for the specific language governing +// permissions and limitations under the License. +/////////////////////////////////////////////////////////////////////// + #pragma once #include diff --git a/fpga/zsbl/gpt.c b/fpga/zsbl/gpt.c index 99f74ec3a..e21176f05 100644 --- a/fpga/zsbl/gpt.c +++ b/fpga/zsbl/gpt.c @@ -1,3 +1,32 @@ +/////////////////////////////////////////////////////////////////////// +// gpt.c +// +// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024 +// +// Purpose: Code to read GPT Partitions off of an SD card. +// +// +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the +// “License”); you may not use this file except in compliance with the +// License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an “AS IS” BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +// implied. See the License for the specific language governing +// permissions and limitations under the License. +/////////////////////////////////////////////////////////////////////// + #include "gpt.h" #include "boot.h" #include "uart.h" diff --git a/fpga/zsbl/gpt.h b/fpga/zsbl/gpt.h index 5ce5e1d4b..8cd3ecc11 100644 --- a/fpga/zsbl/gpt.h +++ b/fpga/zsbl/gpt.h @@ -1,3 +1,32 @@ +/////////////////////////////////////////////////////////////////////// +// gpt.h +// +// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024 +// +// Purpose: Header for gpt.c, contains gpt structs +// +// +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the +// “License”); you may not use this file except in compliance with the +// License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an “AS IS” BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +// implied. See the License for the specific language governing +// permissions and limitations under the License. +/////////////////////////////////////////////////////////////////////// + #pragma once #include diff --git a/fpga/zsbl/riscv.S b/fpga/zsbl/riscv.S index 7f400b1b2..b2d86599c 100644 --- a/fpga/zsbl/riscv.S +++ b/fpga/zsbl/riscv.S @@ -1,3 +1,32 @@ +/////////////////////////////////////////////////////////////////////// +// riscv.S +// +// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024 +// +// Purpose: Basic utility functions for reading registers +// +// +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the +// “License”); you may not use this file except in compliance with the +// License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an “AS IS” BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +// implied. See the License for the specific language governing +// permissions and limitations under the License. +/////////////////////////////////////////////////////////////////////// + .section .text .globl read_mcycle .type read_mcycle, @function diff --git a/fpga/zsbl/riscv.h b/fpga/zsbl/riscv.h index a27cd48d6..543fe5cde 100644 --- a/fpga/zsbl/riscv.h +++ b/fpga/zsbl/riscv.h @@ -1,3 +1,32 @@ +/////////////////////////////////////////////////////////////////////// +// riscv.h +// +// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024 +// +// Purpose: Function prototypes for riscv utility functions +// +// +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the +// “License”); you may not use this file except in compliance with the +// License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an “AS IS” BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +// implied. See the License for the specific language governing +// permissions and limitations under the License. +/////////////////////////////////////////////////////////////////////// + #pragma once #include diff --git a/fpga/zsbl/sd.c b/fpga/zsbl/sd.c index 484fd65c0..1f95d8477 100644 --- a/fpga/zsbl/sd.c +++ b/fpga/zsbl/sd.c @@ -1,3 +1,32 @@ +/////////////////////////////////////////////////////////////////////// +// sd.c +// +// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024 +// +// Purpose: SD Card protocol functions +// +// +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the +// “License”); you may not use this file except in compliance with the +// License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an “AS IS” BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +// implied. See the License for the specific language governing +// permissions and limitations under the License. +/////////////////////////////////////////////////////////////////////// + #include "sd.h" #include "spi.h" #include "uart.h" diff --git a/fpga/zsbl/sd.h b/fpga/zsbl/sd.h index f695b83e5..f66686560 100644 --- a/fpga/zsbl/sd.h +++ b/fpga/zsbl/sd.h @@ -1,3 +1,33 @@ +/////////////////////////////////////////////////////////////////////// +// sd.h +// +// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024 +// +// Purpose: Header file for SD card protocol functions. Defines some +// useful macros. +// +// +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the +// “License”); you may not use this file except in compliance with the +// License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an “AS IS” BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +// implied. See the License for the specific language governing +// permissions and limitations under the License. +/////////////////////////////////////////////////////////////////////// + #pragma once #include diff --git a/fpga/zsbl/spi.c b/fpga/zsbl/spi.c index 5b23c85b6..04d609648 100644 --- a/fpga/zsbl/spi.c +++ b/fpga/zsbl/spi.c @@ -29,31 +29,6 @@ #include "spi.h" -// Write to a register -/* inline void write_reg(uintptr_t addr, uint32_t value) { */ -/* volatile uint32_t * loc = (volatile uint32_t *) addr; */ -/* *loc = value; */ -/* } */ - -/* // Read a register */ -/* inline uint32_t read_reg(uintptr_t addr) { */ -/* return *(volatile uint32_t *) addr; */ -/* } */ - -/* // Queues a single byte in the transfer fifo */ -/* inline void spi_sendbyte(uint8_t byte) { */ -/* // Write byte to transfer fifo */ -/* write_reg(SPI_TXDATA, byte); */ -/* } */ - -/* inline void waittx() { */ -/* while(!(read_reg(SPI_IP) & 1)) {} */ -/* } */ - -/* inline void waitrx() { */ -/* while(read_reg(SPI_IP) & 2) {} */ -/* } */ - uint8_t spi_txrx(uint8_t byte) { spi_sendbyte(byte); waittx(); @@ -64,10 +39,6 @@ uint8_t spi_dummy() { return spi_txrx(0xff); } -/* inline uint8_t spi_readbyte() { */ -/* return read_reg(SPI_RXDATA); */ -/* } */ - uint64_t spi_read64() { uint64_t r; uint8_t rbyte; diff --git a/fpga/zsbl/time.c b/fpga/zsbl/time.c index 43ac085b7..c265eea05 100644 --- a/fpga/zsbl/time.c +++ b/fpga/zsbl/time.c @@ -1,3 +1,32 @@ +/////////////////////////////////////////////////////////////////////// +// time.c +// +// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024 +// +// Purpose: Gets and prints the current time. +// +// +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the +// “License”); you may not use this file except in compliance with the +// License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an “AS IS” BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +// implied. See the License for the specific language governing +// permissions and limitations under the License. +/////////////////////////////////////////////////////////////////////// + #include "time.h" #include "boot.h" #include "riscv.h" diff --git a/fpga/zsbl/time.h b/fpga/zsbl/time.h index 6cd928b88..8bf7064af 100644 --- a/fpga/zsbl/time.h +++ b/fpga/zsbl/time.h @@ -1,3 +1,32 @@ +/////////////////////////////////////////////////////////////////////// +// spi.c +// +// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024 +// +// Purpose: Time function prototypes +// +// +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the +// “License”); you may not use this file except in compliance with the +// License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an “AS IS” BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +// implied. See the License for the specific language governing +// permissions and limitations under the License. +/////////////////////////////////////////////////////////////////////// + #pragma once #include diff --git a/fpga/zsbl/uart.c b/fpga/zsbl/uart.c index 8c25f17ca..580265d98 100644 --- a/fpga/zsbl/uart.c +++ b/fpga/zsbl/uart.c @@ -1,3 +1,33 @@ +/////////////////////////////////////////////////////////////////////// +// uart.c +// +// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024 +// +// Purpose: Uart printing functions, as well as functions for printing +// hex, decimal, and floating point numbers. +// +// +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the +// “License”); you may not use this file except in compliance with the +// License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an “AS IS” BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +// implied. See the License for the specific language governing +// permissions and limitations under the License. +/////////////////////////////////////////////////////////////////////// + #include "uart.h" void write_reg_u8(uintptr_t addr, uint8_t value) diff --git a/fpga/zsbl/uart.h b/fpga/zsbl/uart.h index cbdcc5941..96c55ffe8 100644 --- a/fpga/zsbl/uart.h +++ b/fpga/zsbl/uart.h @@ -1,3 +1,32 @@ +/////////////////////////////////////////////////////////////////////// +// uart.h +// +// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024 +// +// Purpose: Header for the UART functions. +// +// +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the +// “License”); you may not use this file except in compliance with the +// License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an “AS IS” BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +// implied. See the License for the specific language governing +// permissions and limitations under the License. +/////////////////////////////////////////////////////////////////////// + #pragma once #include #include "riscv.h" From 2dc7e0f76fa4cceca5fffc8612244365f7e9c40a Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Tue, 6 Aug 2024 17:36:42 -0500 Subject: [PATCH 184/219] Added and extra header and changed the comments to be accurate in ram1p1rwbe.sv --- fpga/zsbl/splitfile.sh | 32 +++++++++++++++++++++++++++++++- src/generic/mem/ram1p1rwbe.sv | 6 +++--- 2 files changed, 34 insertions(+), 4 deletions(-) diff --git a/fpga/zsbl/splitfile.sh b/fpga/zsbl/splitfile.sh index 1e367c872..fc943576c 100755 --- a/fpga/zsbl/splitfile.sh +++ b/fpga/zsbl/splitfile.sh @@ -1,5 +1,35 @@ +####################################################################### +# splitfile.sh +# +# Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024 +# +# Purpose: Used to split boot.mem into two sections for FPGA +# +# +# +# A component of the Wally configurable RISC-V project. +# +# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the +# “License”); you may not use this file except in compliance with the +# License, or, at your option, the Apache License version 2.0. You +# may obtain a copy of the License at +# +# https://solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work +# distributed under the License is distributed on an “AS IS” BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +###################################################################### + + # Acquired from here. -# https://stackoverflow.com/questions/3066948/how-to-file-split-at-a-line-number +# https:##stackoverflow.com#questions#3066948#how-to-file-split-at-a-line-number file_name=$1 # set first K lines: diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index 287607c9e..d17262d22 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -99,11 +99,11 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE `ifdef VERILATOR // because Verilator doesn't automatically accept $WALLY from shell string WALLY_DIR = getenvval("WALLY"); - $readmemh({WALLY_DIR,"/fpga/src/data.mem"}, RAM, 0); // load boot ROM for FPGA + $readmemh({WALLY_DIR,"/fpga/src/data.mem"}, RAM, 0); // load boot RAM for FPGA `else - $readmemh({"$WALLY/fpga/src/data.mem"}, RAM, 0); // load boot ROM for FPGA + $readmemh({"$WALLY/fpga/src/data.mem"}, RAM, 0); // load boot RAM for FPGA `endif - end else begin // put something in the ROM so it is not optimized away + end else begin // put something in the RAM so it is not optimized away RAM[0] = 'h00002197; end end From 0303314f4e34c6aee826d17283cc877c22460bf7 Mon Sep 17 00:00:00 2001 From: Huda-10xe Date: Wed, 7 Aug 2024 14:19:05 +0500 Subject: [PATCH 185/219] Adding RVVI Functional Coverage Support --- .gitignore | 3 +++ .gitmodules | 3 +++ bin/regression-wally | 12 ++++++++++++ bin/wsim | 7 +++++-- cvw-arch-verif | 1 + sim/questa/wally.do | 21 ++++++++++++++++++++- testbench/testbench.sv | 12 ++++++++++++ tests/riscof/Makefile | 9 +++++++++ 8 files changed, 65 insertions(+), 3 deletions(-) create mode 160000 cvw-arch-verif diff --git a/.gitignore b/.gitignore index 3a6dad8b0..3d3d875f0 100644 --- a/.gitignore +++ b/.gitignore @@ -193,6 +193,9 @@ config/deriv docs/docker/buildroot-config-src docs/docker/testvector-generation sim/questa/cov +sim/questa/fcovrvvi +sim/questa/fcovrvvi_logs +sim/questa/fcovrvvi_ucdb sim/covhtmlreport/ sim/questa/logs sim/questa/wkdir diff --git a/.gitmodules b/.gitmodules index 69054d830..e2c94791f 100644 --- a/.gitmodules +++ b/.gitmodules @@ -34,3 +34,6 @@ sparseCheckout = true path = addins/verilog-ethernet url = https://github.com/ross144/verilog-ethernet.git +[submodule "cvw-arch-verif"] + path = cvw-arch-verif + url = https://github.com/openhwgroup/cvw-arch-verif diff --git a/bin/regression-wally b/bin/regression-wally index 3040f584b..e83c3b5fa 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -340,6 +340,7 @@ defaultsim = "verilator" # Default simulator for all other tests parser = argparse.ArgumentParser() parser.add_argument("--ccov", help="Code Coverage", action="store_true") parser.add_argument("--fcov", help="Functional Coverage", action="store_true") +parser.add_argument("--fcovrvvi", help="Functional Coverage RVVI", action="store_true") parser.add_argument("--nightly", help="Run large nightly regression", action="store_true") parser.add_argument("--buildroot", help="Include Buildroot Linux boot test (takes many hours, done along with --nightly)", action="store_true") parser.add_argument("--testfloat", help="Include Testfloat floating-point unit tests", action="store_true") @@ -357,6 +358,8 @@ if (args.ccov): # only run RV64GC tests in coverage mode coverStr = '--ccov' elif (args.fcov): # only run RV64GC tests in lockstep in coverage mode coverStr = '--fcov' +elif (args.fcovrvvi): # only run RV64GC tests in rvvi coverage mode + coverStr = '--fcovrvvi' else: coverStr = '' @@ -392,6 +395,10 @@ elif (args.fcov): # only run RV64GC tests on Questa in lockstep in functional c # grepstr="SUCCESS! All tests ran without failures", # grepfile = sim_log) #configs.append(tc) +elif (args.fcovrvvi): # only run RV64GC tests on Questa in rvvi coverage mode + addTests(tests64gc_nofp, coveragesim) + if (args.fp): + addTests(tests64gc_fp, coveragesim) else: for sim in sims: if (not (args.buildroot and sim == defaultsim)): # skip short buildroot sim if running long one @@ -501,6 +508,9 @@ def main(): if args.ccov: TIMEOUT_DUR = 20*60 # seconds os.system('rm -f questa/cov/*.ucdb') + elif args.fcovrvvi: + TIMEOUT_DUR = 20*60 + os.system('rm -f questa/fcovrvvi_ucdb/* questa/fcovrvvi_logs/* questa/fcovrvvi/*') elif args.fcov: TIMEOUT_DUR = 1*60 os.system('rm -f questa/fcov_ucdb/* questa/fcov_logs/* questa/fcov/*') @@ -535,6 +545,8 @@ def main(): os.system('make QuestaCodeCoverage') if args.fcov: os.system('make QuestaFunctCoverage') + if args.fcovrvvi: + os.system('make QuestaFunctCoverageRvvi') # Count the number of failures if num_fail: print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail) diff --git a/bin/wsim b/bin/wsim index b2288deb4..d837bca85 100755 --- a/bin/wsim +++ b/bin/wsim @@ -28,6 +28,7 @@ parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testb parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true") parser.add_argument("--ccov", "-c", help="Code Coverage", action="store_true") parser.add_argument("--fcov", "-f", help="Functional Coverage, implies lockstep", action="store_true") +parser.add_argument("--fcovrvvi", "-fr", help="Functional Coverage RVVI", action="store_true") parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="") parser.add_argument("--vcd", "-v", help="Generate testbench.vcd", action="store_true") parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true") @@ -57,7 +58,7 @@ if(args.testsuite.endswith('.elf') and args.elf == ""): # No --elf argument; che # Validate arguments -if (args.gui or args.ccov or args.fcov or args.lockstep): +if (args.gui or args.ccov or args.fcov or args.fcovrvvi or args.lockstep): if args.sim not in ["questa", "vcs"]: print("Option only supported for Questa and VCS") exit(1) @@ -95,10 +96,12 @@ if (args.ccov): flags += " --ccov" if (args.fcov): flags += " --fcov" +if (args.fcovrvvi): + flags += "--fcovrvvi" # create the output sub-directories. regressionDir = WALLY + '/sim/' -for d in ["logs", "wkdir", "cov", "ucdb", "fcov", "fcov_ucdb"]: +for d in ["logs", "wkdir", "cov", "ucdb", "fcov", "fcov_ucdb", "fcovrvvi", "fcovrvvi_ucdb"]: try: os.mkdir(regressionDir+args.sim+"/"+d) except: diff --git a/cvw-arch-verif b/cvw-arch-verif new file mode 160000 index 000000000..2a4f56ec9 --- /dev/null +++ b/cvw-arch-verif @@ -0,0 +1 @@ +Subproject commit 2a4f56ec97db7cdd6fd13fb928122d408fefbf1e diff --git a/sim/questa/wally.do b/sim/questa/wally.do index 632e2c156..43892c356 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -31,6 +31,7 @@ set WALLY $::env(WALLY) set CONFIG ${WALLY}/config set SRC ${WALLY}/src set TB ${WALLY}/testbench +set FCRVVI ${WALLY}/addins/cvw-arch-verif/fcov # create library if [file exists ${WKDIR}] { @@ -39,11 +40,16 @@ if [file exists ${WKDIR}] { vlib ${WKDIR} # Create directory for coverage data mkdir -p cov +# Create directory for functional coverage data +mkdir ${WALLY}/addins/cvw-arch-verif/work set ccov 0 set CoverageVoptArg "" set CoverageVsimArg "" +set FuncCovRVVI 0 +set FCdefineRVVI_COVERAGE "" + set FunctCoverage 0 set riscvISACOVsrc "" set FCdefineINCLUDE_TRACE2COV "" @@ -113,6 +119,13 @@ if {$CoverageIndex >= 0} { set lst [lreplace $lst $CoverageIndex $CoverageIndex] } +set FCoverageIndexRVVI [lsearch -exact $lst "--fcovrvvi"] +if {$FCoverageIndexRVVI >= 0} { + set FuncCovRVVI 1 + set FCdefineRVVI_COVERAGE "+define+RVVI_COVERAGE" + set lst [lreplace $lst $FCoverageIndexRVVI $FCoverageIndexRVVI] +} + # if +coverage found set flag and remove from list set FunctCoverageIndex [lsearch -exact $lst "--fcov"] if {$FunctCoverageIndex >= 0} { @@ -172,6 +185,7 @@ if {$DEBUG > 0} { echo "GUI = $GUI" echo "ccov = $ccov" echo "lockstep = $lockstep" + echo "FuncCovRVVI = $FuncCovRVVI" echo "FunctCoverage = $FunctCoverage" echo "remaining list = $lst" echo "Extra +args = $PlusArgs" @@ -197,7 +211,7 @@ set temp3 [lindex $PlusArgs 3] # "Extra checking for conflicts with always_comb done at vopt time" # because vsim will run vopt -vlog -lint -work ${WKDIR} +incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared ${lockstepvoptstring} ${FCdefineIDV_INCLUDE_TRACE2COV} ${FCdefineINCLUDE_TRACE2COV} ${ImperasPubInc} ${ImperasPrivInc} ${rvviFiles} ${FCdefineCOVER_BASE_RV64I} ${FCdefineCOVER_LEVEL_DV_PR_EXT} ${FCdefineCOVER_RV64I} ${FCdefineCOVER_RV64M} ${FCdefineCOVER_RV64A} ${FCdefineCOVER_RV64F} ${FCdefineCOVER_RV64D} ${FCdefineCOVER_RV64ZICSR} ${FCdefineCOVER_RV64C} ${idvFiles} ${riscvISACOVsrc} ${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 +vlog -lint -work ${WKDIR} +incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared ${lockstepvoptstring} ${FCdefineIDV_INCLUDE_TRACE2COV} ${FCdefineINCLUDE_TRACE2COV} ${ImperasPubInc} ${ImperasPrivInc} ${rvviFiles} ${FCdefineCOVER_BASE_RV64I} ${FCdefineCOVER_LEVEL_DV_PR_EXT} ${FCdefineCOVER_RV64I} ${FCdefineCOVER_RV64M} ${FCdefineCOVER_RV64A} ${FCdefineCOVER_RV64F} ${FCdefineCOVER_RV64D} ${FCdefineCOVER_RV64ZICSR} ${FCdefineCOVER_RV64C} ${FCdefineRVVI_COVERAGE} ${idvFiles} ${riscvISACOVsrc} ${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv +incdir+${FCRVVI}/common +incdir+${FCRVVI} ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals @@ -224,6 +238,11 @@ if {$FunctCoverage} { coverage save -onexit ${UCDB} } +if {$FuncCovRVVI} { + set UCDB ${WALLY}/addins/cvw-arch-verif/work/${CFG}_${TESTSUITE}.ucdb + coverage save -onexit ${UCDB} +} + run -all if {$ccov} { diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 89d3b06d5..c53e0a842 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -33,6 +33,12 @@ `include "idv/idv.svh" `endif +`ifdef RVVI_COVERAGE + `include "RISCV_trace_data.svh" + `include "rvvicov.svh" + `include "wrapper.sv" +`endif + import cvw::*; module testbench; @@ -982,6 +988,12 @@ test_pmp_coverage #(P) pmp_inst(clk); /* verilator lint_on WIDTHTRUNC */ /* verilator lint_on WIDTHEXPAND */ +`ifdef RVVI_COVERAGE + rvviTrace #(.XLEN(P.XLEN), .FLEN(P.FLEN)) rvvi(); + wallyTracer #(P) wallyTracer(rvvi); + wrapper #(P) wrap(clk); +`endif + endmodule /* verilator lint_on STMTDLY */ diff --git a/tests/riscof/Makefile b/tests/riscof/Makefile index aaa8a8344..1d42cf10c 100644 --- a/tests/riscof/Makefile +++ b/tests/riscof/Makefile @@ -4,13 +4,18 @@ work_dir = ./riscof_work work = ./work arch_workdir = $(work)/riscv-arch-test wally_workdir = $(work)/wally-riscv-arch-test +custom_test_dir = ../../addins/cvw-arch-verif/test +submodule_work_dir = ../../addins/cvw-arch-verif/riscof_work current_dir = $(shell pwd) #XLEN ?= 64 all: root arch32 wally32 arch32e arch64 wally64 + wally-riscv-arch-test: root wally64 wally32 +custom: new_test + root: mkdir -p $(work_dir) mkdir -p $(work) @@ -47,6 +52,9 @@ wally64: quad64: riscof run --work-dir=$(work_dir) --config=config64.ini --suite=$(wally_dir)/riscv-test-suite/rv64i_m/Q/riscv-ctg/tests/ --env=$(wally_dir)/riscv-test-suite/env + +new_test: + riscof run --work-dir=$(submodule_work_dir) --config=config64.ini --suite=$(custom_test_dir)/ --env=$(wally_dir)/riscv-test-suite/env --no-browser #wally32e: # riscof run --work-dir=$(work_dir) --config=config32e.ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run @@ -66,3 +74,4 @@ clean: rm -rf $(work_dir) rm -rf $(wally_workdir) rm -rf $(arch_workdir) + rm -rf $(submodule_wor_dir) From 94e923ef4656ff327bc88e35553a975b75d74bf3 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 8 Aug 2024 00:00:52 -0700 Subject: [PATCH 186/219] Additional Linux README updates --- linux/Makefile | 3 --- linux/README.MD | 29 ++++++++++++++++++----------- 2 files changed, 18 insertions(+), 14 deletions(-) diff --git a/linux/Makefile b/linux/Makefile index 65632a0d0..033629255 100644 --- a/linux/Makefile +++ b/linux/Makefile @@ -76,8 +76,6 @@ $(RISCV): @ echo "and sourced setup.sh" # Disassembly rules --------------------------------------------------- - - disassemble: rm -rf $(BUILDROOT)/output/images/disassembly find $(BUILDROOT)/output/build/linux-* -maxdepth 1 -name "vmlinux" | xargs cp -t $(BUILDROOT)/output/images/ @@ -106,7 +104,6 @@ $(IMAGES)/busybox: cp $$busyboxDir/busybox $@ ;\ # Generating new Buildroot directories -------------------------------- - download: $(WALLYBOARD) cp $(WALLYBOARD)/main.config $(BUILDROOT)/.config @echo "Buildroot successfully download." diff --git a/linux/README.MD b/linux/README.MD index e052df9ae..ba7fb8dd4 100644 --- a/linux/README.MD +++ b/linux/README.MD @@ -5,30 +5,31 @@ 1. [Setting up Buildroot](#buildroot) 2. [Generating Device Tree Binaries](#devicetree) 3. [Disassembling the Binaries for Debugging](#disassembly) -4. [Creating a Bootable SD Card](#sdcard) +4. [Generating test-vectors for regression](#testvectors) +5. [Creating a Bootable SD Card](#sdcard) ## Setting up Buildroot -In order to generate the Linux and boot stage binaries compatible with Wally, Buildroot is used for cross-compilation. +In order to generate the Linux and boot stage binaries compatible with Wally, Buildroot is used for cross-compilation. To set up a Buildroot directory, configuration files for Buildroot, Linux, and Busybox must be copied into the correct locations inside the main Buildroot directory. Buildroot and device tree binaries must be generated as well. This can all be done automatically using the Makefile inside Wally's Linux subdirectory (this one). To install a new buildroot directory, build the Buildroot binaries, generate the device tree binaries, generate test-vectors for simulation, and install the buildroot package needed to build the SD card driver for Linux, run: $ make -This installs to the `$RISCV` directory. +This installs to the `$RISCV` directory. Buildroot itself is installed to `$RISCV/buildroot` and the test-vectors are installed to `$RISCV/linux-testvectors`. + +Optionally, you can override the `BUILDROOT` variable to install a different buildroot source directory. -Optionally, you can override the `BUILDROOT` variable to use a different buildroot source directory. - $ make install BUILDROOT=path/to/buildroot - + ## Generating Device Tree Binaries -The device tree files for the various FPGA's Wally supports, as well as QEMU's device tree for the virt machine, are located in the `./devicetree` subdirectory. These device tree files are necessary for the boot process. +The device tree files for the various FPGA's Wally supports, as well as QEMU's device tree for the virt machine, are located in the `./devicetree` subdirectory. These device tree files are necessary for the boot process. They are built automatically using the main `make` command. To build the device tree binaries (.dtb) from the device tree sources (.dts) separately, we can build all of them at once using: $ make generate #optionally override BUILDROOT - + The .dts files will end up in the `/output/images` folder of your chosen buildroot directory. ## Disassembling the Binaries for Debugging @@ -38,16 +39,22 @@ By using the `riscv64-unknown-elf-objdump` utility, we can disassemble the binar The disassembled binaries are built automatically using the main `make` command. To create the disassembled binaries separately, run: $ make disassemble #optionally override BUILDROOT - + You'll find the resulting disassembled files in `/output/images/disassembly`. +## Generate Memory Files for Linux Boot + +Running a linux boot simulation uses a preloaded bootrom and ram memory. We use QEMU to generate these preloaded memory files. The files are output to $RISCV/linux-testvectors. The memory files are generated automatically when using the main `make` command. Alternatively, they can be generated by running + + make dumptvs + ## Creating a Bootable SD Card To flash a bootable sd card for Wally's bootloader, use the `flash-sd.sh` script located in `/linux/sdcard`. The script allows you to specify which buildroot directory you would like to use and to specify the device tree. By default it is set up for the default location of buildroot in `$RISCV` and uses the vcu108 device tree. To use the script with your own buildroot directory and device tree, type: $ cd sdcard $ ./flash-sd.sh -b -d - + for example - + $ ./flash-sd.sh -b ~/repos/buildroot -d wally-vcu118.dtb /dev/sdb From 2c3dc9e8ee99e501df00511d79a16d5fb51fc55b Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 8 Aug 2024 00:01:14 -0700 Subject: [PATCH 187/219] setup.sh updates --- setup.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/setup.sh b/setup.sh index 390af63c4..9f0fca993 100644 --- a/setup.sh +++ b/setup.sh @@ -22,7 +22,7 @@ else # set the $RISCV directory here and remove the subsequent two lines # export RISCV= echo "\$RISCV directory not found. Checked /opt/riscv and ~/riscv. Edit setup.sh to point to your custom \$RISCV directory." - exit 1; + exit 1 fi echo \$RISCV set to "${RISCV}" @@ -33,7 +33,7 @@ echo \$WALLY set to "${WALLY}" # utility functions in Wally repository export PATH=$WALLY/bin:$PATH -# Verilator needs a larger stack to simulate CORE-V Wally +# Verilator needs a larger core file size to simulate CORE-V Wally ulimit -c 300000 # load site licenses and tool locations From ef51fdae3addd6d63c21a43f50056d3c836706f8 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 8 Aug 2024 00:45:20 -0700 Subject: [PATCH 188/219] README updates with updated installation flow --- README.md | 42 +++++++++++++++++++++++++++++++----------- site-setup.sh | 4 ++-- 2 files changed, 33 insertions(+), 13 deletions(-) diff --git a/README.md b/README.md index 032304c25..39b5c6780 100644 --- a/README.md +++ b/README.md @@ -60,9 +60,27 @@ Build the tests and run a regression simulation to prove everything is installed # Toolchain Installation and Configuration (Sys Admin) -This section describes the open source toolchain installation. The current version of the toolchain has been tested on Ubuntu (versions 20.04, 22.04, and 24.04) and on Red Hat/Rocky/AlmaLinux (versions 8 and 9). +This section describes the open source toolchain installation. + +### Compatibility +The current version of the toolchain has been tested on Ubuntu (versions 20.04 LTS, 22.04 LTS, and 24.04 LTS) and on Red Hat/Rocky/AlmaLinux (versions 8 and 9). + NOTE: Ubuntu 22.04LTS is incompatible with Synopsys Design Compiler. +### Overview +The toolchain installation script installs the following tools: +- [RISC-V GNU Toolchain](https://github.com/riscv-collab/riscv-gnu-toolchain): GCC and accompanying compiler tools +- [elf2hex](https://github.com/sifive/elf2hex): executable file to hexadecimal converter +- [QEMU](https://www.qemu.org/docs/master/system/target-riscv.html): emulator +- [Spike](https://github.com/riscv-software-src/riscv-isa-sim): functional RISC-V model +- [Verilator](https://github.com/verilator/verilator): open-source Verilog simulator + - NOTE: Verilator does not currently work reliably for simulating Wally on Ubuntu 20.04 LTS and Red Hat 8 +- [RISC-V Sail Model](https://github.com/riscv/sail-riscv): golden reference model for RISC-V +- [OSU Skywater 130 cell library](https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12): standard cell library +- [RISCOF](https://github.com/riscv-software-src/riscof.git): RISC-V compliance test framework + +Additionally, Buildroot Linux is built for Wally and linux test-vectors are generated for simulation. See the [Linux README](linux/README.md) for more details. + ### Installation The tools can be installed by running @@ -75,27 +93,29 @@ If a user-level installation is desired, the script can instead be run by any us $ sudo $WALLY/bin/wally-package-install.sh -In either case, the installation directory can be overridden by passing the desired directory as an argument to the installation script. For example, +In either case, the installation directory can be overridden by passing the desired directory as the last argument to the installation script. For example, $ sudo $WALLY/bin/wally-tool-chain-install.sh /home/riscv -See wally-tool-chain-install.sh for a detailed description of each component, -or to issue the commands one at a time to install on the command line. +See `wally-tool-chain-install.sh` for a detailed description of each component, or to issue the commands one at a time to install on the command line. + +**NOTE:** The complete installation process requires ~55 GB of free space. If the `--clean` flag is passed as the first argument to the installation script then the final consumed space is only ~26 GB, but upgrading the tools requires reinstalling from scratch. ### Configuration `$WALLY/setup.sh` sources `$RISCV/site-setup.sh`. If the toolchain was installed in either of the default locations (`/opt/riscv` or `~/riscv`), `$RISCV` will automatically be set to the correct path when `setup.sh` is run. If a custom installation directory was used, then `$WALLY/setup.sh` must be modified to set the correct path. `$RISCV/site-setup.sh` allows for customization of the site specific information such as commercial licenses and PATH variables. It is automatically copied into your `$RISCV` folder when the installation script is run. -Change the following lines to point to the path and license server for your Siemens Questa and Synopsys Design Compiler installation and license server. If you only have Questa, you can still simulate but cannot run logic synthesis. If Questa or Design Compiler are already setup on this system then don't set these variables. +Change the following lines to point to the path and license server for your Siemens Questa and Synopsys Design Compiler and VCS installations and license servers. If you only have Questa or VCS, you can still simulate but cannot run logic synthesis. If Questa, VSC, or Design Compiler are already setup on this system then don't set these variables. export MGLS_LICENSE_FILE=.. # Change this to your Siemens license server export SNPSLMD_LICENSE_FILE=.. # Change this to your Synopsys license server - export QUESTAPATH=.. # Change this for your path to Questa - export SNPSPATH=.. # Change this for your path to Design Compiler + export QUESTA_HOME=.. # Change this for your path to Questa + export DC_HOME=.. # Change this for your path to Synopsys Design Compiler + export VCS_HOME=.. # Change this for your path to Synopsys VCS -## Installing EDA Tools +# Installing EDA Tools Electronic Design Automation (EDA) tools are vital to implementations of System on Chip architectures as well as validating different designs. Open-source and commercial tools exist for multiple strategies and although the one can spend a lifetime using combinations of different tools, only a small subset of tools is utilized for this text. The tools are chosen because of their ease in access as well as their repeatability for accomplishing many of the tasks utilized to design Wally. It is anticipated that additional tools may be documented later after this is text is published to improve use and access. @@ -105,12 +125,12 @@ Note: Some EDA tools utilize `LM_LICENSE_FILE` for their environmental variable Although most EDA tools are Linux-friendly, they tend to have issues when not installed on recommended OS flavors. Both Red Hat Enterprise Linux and SUSE Linux products typically tend to be recommended for installing commercial-based EDA tools and are recommended for utilizing complex simulation and architecture exploration. Questa can also be installed on Microsoft Windows as well as Mac OS with a Virtual Machine such as Parallels. -#### Siemens Questa +### Siemens Questa Siemens Questa simulates behavioral, RTL and gate-level HDL. To install Siemens Questa first go to a web browser and navigate to https://eda.sw.siemens.com/en-US/ic/questa/simulation/advanced-simulator/. Click Sign In and log in with your credentials and the product can easily be downloaded and installed. Some Windows-based installations also require gcc libraries that are typically provided as a compressed zip download through Siemens. -#### Synopsys Design Compiler (DC) +### Synopsys Design Compiler (DC) Many commercial synthesis and place and route tools require a common installer. These installers are provided by the EDA vendor and Synopsys has one called Synopsys Installer. To use Synopsys Installer, you will need to acquire a license through Synopsys that is typically Called Synopsys Common Licensing (SCL). Both the Synopsys Installer, license key file, and Design Compiler can all be downloaded through Synopsys Solvnet. First open a web browser, log into Synsopsy Solvnet, and download the installer and Design Compiler installation files. Then, install the Installer @@ -148,7 +168,7 @@ If you want to implement your own version of the chip, your tool and license com Startups can expect to spend more than $1 million on CAD tools to get a chip to market. Commercial CAD tools are not realistically available to individuals without a university or company connection. -## Adding Cron Job for nightly builds +# Adding Cron Job for nightly builds If you want to add a cronjob you can do the following: 1) Set up the email client `mutt` for your distribution diff --git a/site-setup.sh b/site-setup.sh index f6a499aec..5a76087a9 100755 --- a/site-setup.sh +++ b/site-setup.sh @@ -10,10 +10,10 @@ # license servers and commercial CAD tool paths # Must edit these based on your local environment. export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu # Change this to your Siemens license server for Questa -export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server for Design Compiler +export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server export QUESTA_HOME=/cad/mentor/questa_sim-2023.4/questasim # Change this for your path to Questa, excluding bin export DC_HOME=/cad/synopsys/SYN # Change this for your path to Synopsys Design Compiler, excluding bin -export VCS_HOME=/cad/synopsys/vcs/U-2023.03-SP2-4 # Change this for your path to Synopsys VCS, exccluding bin +export VCS_HOME=/cad/synopsys/vcs/U-2023.03-SP2-4 # Change this for your path to Synopsys VCS, excluding bin # Tools # Questa and Synopsys From 2efc129ba938cec24a6c602c0352eb7506abedba Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 6 Aug 2024 23:35:22 -0700 Subject: [PATCH 189/219] Temporary fix for riscv-software-src/riscof#122 --- bin/requirements.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/bin/requirements.txt b/bin/requirements.txt index 67b51ee2e..0f72b5af1 100644 --- a/bin/requirements.txt +++ b/bin/requirements.txt @@ -3,6 +3,7 @@ lief>=0.14.1 Markdown>=3.6 matplotlib>=3.9.0 PyYAML>=5.2 +riscv-isac @ git+https://github.com/riscv-software-src/riscv-isac@dev riscof @ git+https://github.com/riscv/riscof.git riscv-config>=3.18.3 riscv-isac>=0.18.0 From 77b45f2d75804245d058bbcbe4562455ab5bf580 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 8 Aug 2024 05:25:28 -0700 Subject: [PATCH 190/219] Fix creating cvw-arch-verif work directory --- .gitmodules | 2 +- cvw-arch-verif => addins/cvw-arch-verif | 0 sim/questa/wally.do | 2 +- 3 files changed, 2 insertions(+), 2 deletions(-) rename cvw-arch-verif => addins/cvw-arch-verif (100%) diff --git a/.gitmodules b/.gitmodules index e2c94791f..f95a898bb 100644 --- a/.gitmodules +++ b/.gitmodules @@ -35,5 +35,5 @@ path = addins/verilog-ethernet url = https://github.com/ross144/verilog-ethernet.git [submodule "cvw-arch-verif"] - path = cvw-arch-verif + path = addins/cvw-arch-verif url = https://github.com/openhwgroup/cvw-arch-verif diff --git a/cvw-arch-verif b/addins/cvw-arch-verif similarity index 100% rename from cvw-arch-verif rename to addins/cvw-arch-verif diff --git a/sim/questa/wally.do b/sim/questa/wally.do index 43892c356..db1cbbae1 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -41,7 +41,7 @@ vlib ${WKDIR} # Create directory for coverage data mkdir -p cov # Create directory for functional coverage data -mkdir ${WALLY}/addins/cvw-arch-verif/work +mkdir -p ${WALLY}/addins/cvw-arch-verif/work set ccov 0 set CoverageVoptArg "" From fa98ae8c307183763822d0ca8c62ff88b6b46cdb Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 8 Aug 2024 05:27:35 -0700 Subject: [PATCH 191/219] Depricate conditional generation based on A_SUPPORTED, which is now computed from ZALRSC_SUPPORTED and ZAAMO_SUPPORTED --- src/ieu/controller.sv | 6 +++--- src/ieu/datapath.sv | 4 ++-- src/ieu/extend.sv | 2 +- src/ifu/ifu.sv | 2 +- src/lsu/atomic.sv | 4 ++-- src/lsu/lsu.sv | 2 +- testbench/common/riscvassertions.sv | 2 +- testbench/testbench.sv | 8 ++++---- 8 files changed, 15 insertions(+), 15 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 74f5162ba..19f96c98d 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -265,11 +265,11 @@ module controller import cvw::*; #(parameter cvw_t P) ( 7'b0100111: if (FLSFunctD) ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0_1; // fsw - only legal if FP supported 7'b0101111: if (AFunctD) begin - if ((P.A_SUPPORTED | P.ZALRSC_SUPPORTED) & InstrD[31:27] == 5'b00010 & Rs2D == 5'b0) + if (P.ZALRSC_SUPPORTED & InstrD[31:27] == 5'b00010 & Rs2D == 5'b0) ControlsD = `CTRLW'b1_000_00_10_001_0_0_0_0_0_0_0_0_0_01_0_0; // lr - else if ((P.A_SUPPORTED | P.ZALRSC_SUPPORTED) & InstrD[31:27] == 5'b00011) + else if (P.ZALRSC_SUPPORTED & InstrD[31:27] == 5'b00011) ControlsD = `CTRLW'b1_101_01_01_100_0_0_0_0_0_0_0_0_0_01_0_0; // sc - else if ((P.A_SUPPORTED | P.ZAAMO_SUPPORTED) & AMOFunctD) + else if (P.ZAAMO_SUPPORTED & AMOFunctD) ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0_0; // amo end 7'b0110011: if (RFunctD) diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index c04d0a4a6..65eafe7f7 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -138,6 +138,6 @@ module datapath import cvw::*; #(parameter cvw_t P) ( mux5 #(P.XLEN) resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, ResultW); // handle Store Conditional result if atomic extension supported - if (P.A_SUPPORTED | P.ZALRSC_SUPPORTED) assign SCResultW = {{(P.XLEN-1){1'b0}}, SquashSCW}; - else assign SCResultW = '0; + if (P.ZALRSC_SUPPORTED) assign SCResultW = {{(P.XLEN-1){1'b0}}, SquashSCW}; + else assign SCResultW = '0; endmodule diff --git a/src/ieu/extend.sv b/src/ieu/extend.sv index 437797859..cbe567ae3 100644 --- a/src/ieu/extend.sv +++ b/src/ieu/extend.sv @@ -48,7 +48,7 @@ module extend import cvw::*; #(parameter cvw_t P) ( // U-type (lui, auipc) 3'b100: ImmExtD = {{(P.XLEN-31){InstrD[31]}}, InstrD[30:12], 12'b0}; // Store Conditional: zero offset - 3'b101: if (P.A_SUPPORTED | P.ZICBOM_SUPPORTED | P.ZICBOZ_SUPPORTED) ImmExtD = '0; + 3'b101: if (P.ZALRSC_SUPPORTED | P.ZAAMO_SUPPORTED | P.ZICBOM_SUPPORTED | P.ZICBOZ_SUPPORTED) ImmExtD = '0; else ImmExtD = undefined; default: ImmExtD = undefined; // undefined endcase diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index ed2830868..695603758 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -400,7 +400,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( flopenr #(P.XLEN) PCEReg(clk, reset, ~StallE, PCD, PCE); // InstrM is only needed with CSRs or atomic operations - if (P.ZICSR_SUPPORTED | P.A_SUPPORTED) begin + if (P.ZICSR_SUPPORTED | P.ZAAMO_SUPPORTED | P.ZALRSC_SUPPORTED) begin mux2 #(32) FlushInstrMMux(InstrE, nop, FlushM, NextInstrE); flopenr #(32) InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM); end else assign InstrM = '0; diff --git a/src/lsu/atomic.sv b/src/lsu/atomic.sv index e318260ab..1e3419dec 100644 --- a/src/lsu/atomic.sv +++ b/src/lsu/atomic.sv @@ -49,14 +49,14 @@ module atomic import cvw::*; #(parameter cvw_t P) ( logic MemReadM; // AMO ALU - if (P.A_SUPPORTED | P.ZAAMO_SUPPORTED) begin + if (P.ZAAMO_SUPPORTED) begin amoalu #(P) amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResultM); mux2 #(P.XLEN) wdmux(IHWriteDataM, AMOResultM, LSUAtomicM[1], IMAWriteDataM); end else assign IMAWriteDataM = IHWriteDataM; // LRSC unit - if (P.A_SUPPORTED | P.ZALRSC_SUPPORTED) begin + if (P.ZALRSC_SUPPORTED) begin assign MemReadM = PreLSURWM[1] & ~IgnoreRequest; lrsc #(P) lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM); end else begin diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index cbe144cbc..900b63eda 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -392,7 +392,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( // Atomic operations ///////////////////////////////////////////////////////////////////////////////////////////// - if (P.A_SUPPORTED | P.ZAAMO_SUPPORTED | P.ZALRSC_SUPPORTED) begin:atomic + if (P.ZAAMO_SUPPORTED | P.ZALRSC_SUPPORTED) begin:atomic atomic #(P) atomic(.clk, .reset, .StallW, .ReadDataM(ReadDataM[P.XLEN-1:0]), .IHWriteDataM, .PAdrM, .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest, .IMAWriteDataM, .SquashSCW, .LSURWM); diff --git a/testbench/common/riscvassertions.sv b/testbench/common/riscvassertions.sv index 0872ab1de..c0f13d8ff 100644 --- a/testbench/common/riscvassertions.sv +++ b/testbench/common/riscvassertions.sv @@ -51,7 +51,7 @@ module riscvassertions import cvw::*; #(parameter cvw_t P); assert ((P.DCACHE_SUPPORTED == 0 & P.ICACHE_SUPPORTED == 0) | P.BUS_SUPPORTED) else $fatal(1, "Dcache and Icache requires DBUS_SUPPORTED."); assert (P.DCACHE_LINELENINBITS <= P.XLEN*16 | (!P.DCACHE_SUPPORTED)) else $fatal(1, "DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 16"); assert (P.DCACHE_LINELENINBITS % 4 == 0) else $fatal(1, "DCACHE_LINELENINBITS must hold 4, 8, or 16 words"); - assert (P.DCACHE_SUPPORTED | (P.A_SUPPORTED == 0)) else $fatal(1, "Atomic extension (A) requires cache on Wally."); + assert (P.DCACHE_SUPPORTED | (P.ZAAMO_SUPPORTED == 0 & P.ZALRSC_SUPPORTED == 0)) else $fatal(1, "Atomic extension (ZAAMO/ZALRSC) requires cache on Wally."); assert (P.IDIV_ON_FPU == 0 | P.F_SUPPORTED) else $fatal(1, "IDIV on FPU needs F_SUPPORTED"); assert (P.SSTC_SUPPORTED == 0 | (P.S_SUPPORTED)) else $fatal(1, "SSTC requires S_SUPPORTED"); assert ((P.M_SUPPORTED == 0) | (P.ZMMUL_SUPPORTED == 1)) else $fatal(1, "M requires ZMMUL"); diff --git a/testbench/testbench.sv b/testbench/testbench.sv index c53e0a842..f3ca4e536 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -145,7 +145,7 @@ module testbench; if (P.ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv}; else tests = {arch64c}; "arch64m": if (P.M_SUPPORTED) tests = arch64m; - "arch64a_amo": if (P.A_SUPPORTED | P.ZAAMO_SUPPORTED) tests = arch64a_amo; + "arch64a_amo": if (P.ZAAMO_SUPPORTED) tests = arch64a_amo; "arch64f": if (P.F_SUPPORTED) tests = arch64f; "arch64d": if (P.D_SUPPORTED) tests = arch64d; "arch64f_fma": if (P.F_SUPPORTED) tests = arch64f_fma; @@ -159,7 +159,7 @@ module testbench; "imperas64d": if (P.D_SUPPORTED) tests = imperas64d; "imperas64m": if (P.M_SUPPORTED) tests = imperas64m; "wally64q": if (P.Q_SUPPORTED) tests = wally64q; - "wally64a_lrsc": if (P.A_SUPPORTED | P.ZALRSC_SUPPORTED) tests = wally64a_lrsc; + "wally64a_lrsc": if (P.ZALRSC_SUPPORTED) tests = wally64a_lrsc; "imperas64c": if (P.C_SUPPORTED) tests = imperas64c; else tests = imperas64iNOc; "custom": tests = custom; @@ -198,7 +198,7 @@ module testbench; if (P.ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv}; else tests = {arch32c}; "arch32m": if (P.M_SUPPORTED) tests = arch32m; - "arch32a_amo": if (P.A_SUPPORTED | P.ZAAMO_SUPPORTED) tests = arch32a_amo; + "arch32a_amo": if (P.ZAAMO_SUPPORTED) tests = arch32a_amo; "arch32f": if (P.F_SUPPORTED) tests = arch32f; "arch32d": if (P.D_SUPPORTED) tests = arch32d; "arch32f_fma": if (P.F_SUPPORTED) tests = arch32f_fma; @@ -210,7 +210,7 @@ module testbench; "imperas32i": tests = imperas32i; "imperas32f": if (P.F_SUPPORTED) tests = imperas32f; "imperas32m": if (P.M_SUPPORTED) tests = imperas32m; - "wally32a_lrsc": if (P.A_SUPPORTED | P.ZALRSC_SUPPORTED) tests = wally32a_lrsc; + "wally32a_lrsc": if (P.ZALRSC_SUPPORTED) tests = wally32a_lrsc; "imperas32c": if (P.C_SUPPORTED) tests = imperas32c; else tests = imperas32iNOc; "wally32i": tests = wally32i; From ed0c826d74504c8a8a1eb92372d3542f1cdd89b4 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Thu, 8 Aug 2024 13:50:11 -0500 Subject: [PATCH 192/219] Turned off RVVI by default. --- fpga/src/fpgaTopArtyA7.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/src/fpgaTopArtyA7.sv b/fpga/src/fpgaTopArtyA7.sv index fa2aa59a9..9133baa25 100644 --- a/fpga/src/fpgaTopArtyA7.sv +++ b/fpga/src/fpgaTopArtyA7.sv @@ -28,7 +28,7 @@ import cvw::*; -module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 1) +module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) (input default_100mhz_clk, (* mark_debug = "true" *) input resetn, input south_reset, From 8c96c0602276f2078dc876ed3d0650343260b5f0 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Thu, 8 Aug 2024 13:52:53 -0500 Subject: [PATCH 193/219] Commented out rvvi debug probes in wally.tcl. --- fpga/generator/wally.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index b2e1e359e..a5e60a3d5 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -89,8 +89,8 @@ report_clock_interaction -file re write_verilog -force -mode funcsim sim/syn-funcsim.v if {$board=="ArtyA7"} { - #source ../constraints/small-debug.xdc - source ../constraints/small-debug-rvvi.xdc + source ../constraints/small-debug.xdc + #source ../constraints/small-debug-rvvi.xdc } else { source ../constraints/vcu-small-debug.xdc } From 16e2d6586555de68dd13359a528e46cff31bea59 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 8 Aug 2024 20:27:51 -0700 Subject: [PATCH 194/219] Remove boot.mem --- fpga/src/boot.mem | 513 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-0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -0000000000000000 -00600100d2e3ca40 From 3a4018fa3d3981a4a4dcb087ab8fd7af96187ef2 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 8 Aug 2024 20:53:40 -0700 Subject: [PATCH 195/219] Add zsbl to makefile --- .gitignore | 2 ++ Makefile | 6 +++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 3d3d875f0..85d753d82 100644 --- a/.gitignore +++ b/.gitignore @@ -106,6 +106,8 @@ sim/sd_model.log fpga/src/sdc/* fpga/src/sdc.tar.gz fpga/src/CopiedFiles_do_not_add_to_repo/* +fpga/src/boot.mem +fpga/src/data.mem sim/branch.log /fpga/generator/sim/imp-funcsim.v /fpga/generator/sim/imp-timesim.sdf diff --git a/Makefile b/Makefile index b0f01c49c..b385d0d12 100644 --- a/Makefile +++ b/Makefile @@ -5,7 +5,8 @@ SIM = ${WALLY}/sim all: - make riscof + make riscof + make zsbl make testfloat # make verify # make coverage @@ -20,6 +21,9 @@ testfloat: cd ${WALLY}/addins/TestFloat-3e/build/Linux-x86_64-GCC; make cd ${WALLY}/tests/fp; ./create_all_vectors.sh +zsbl: + $(MAKE) -C ${WALLY}/fpga/zsbl + verify: cd ${SIM}; ./regression-wally cd ${SIM}/sim; ./sim-testfloat-batch all From a59a5f2f4c2bfb02e7309250c511fd8c524a4e6f Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 8 Aug 2024 21:03:59 -0700 Subject: [PATCH 196/219] Updated regression to avoid iter-elf --- Makefile | 5 ++++- bin/regression-wally | 29 +++-------------------------- 2 files changed, 7 insertions(+), 27 deletions(-) diff --git a/Makefile b/Makefile index b0f01c49c..06538bd5c 100644 --- a/Makefile +++ b/Makefile @@ -8,7 +8,7 @@ all: make riscof make testfloat # make verify -# make coverage + make coverage # make benchmarks # riscof builds the riscv-arch-test and wally-riscv-arch-test suites @@ -35,6 +35,9 @@ coremark: embench: cd ${WALLY}/benchmarks/embench; make; make run +coverage: + make -C tests/coverage + clean: make clean -C sim diff --git a/bin/regression-wally b/bin/regression-wally index 95c3a7c99..5cd8bf76c 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -284,7 +284,7 @@ def addTests(tests, sim): def addLockstepTestsByDir(dir, config, sim): sim_logdir = WALLY+ "/sim/" + sim + "/logs/" - cmdPrefix="wsim --sim " + sim + " " + coverStr + " " + config + cmdPrefix="wsim --lockstep --sim " + sim + " " + coverStr + " " + config for file in os.listdir(dir): if file.endswith(".elf"): fullfile = os.path.join(dir, file) @@ -387,14 +387,6 @@ if (args.ccov): # only run RV64GC tests on Questa in code coverage mode addTests(tests64gc_fp, coveragesim) elif (args.fcov): # only run RV64GC tests on Questa in lockstep in functional coverage mode addLockstepTestsByDir(WALLY+"/tests/functcov/rv64/I", "rv64gc", coveragesim) - #sim_log = WALLY + "/sim/questa/logs/fcov.log" - #tc = TestCase( - # name="lockstep_functcov", - # variant="rv64gc", - # cmd="iterelf " + WALLY + "/tests/functcov/rv64/I > " + sim_log, - # grepstr="SUCCESS! All tests ran without failures", - # grepfile = sim_log) - #configs.append(tc) elif (args.fcovrvvi): # only run RV64GC tests on Questa in rvvi coverage mode addTests(tests64gc_nofp, coveragesim) if (args.fp): @@ -409,23 +401,8 @@ else: # run derivative configurations and lockstep tests in nightly regression if (args.nightly): - sim_log = WALLY + "/sim/questa/logs/lockstep_coverage.log" - tc = TestCase( - name="lockstep_coverage", - variant="rv64gc", - cmd="iterelf " + WALLY + "/tests/coverage > " + sim_log, - grepstr="SUCCESS! All tests ran without failures", - grepfile = sim_log) - configs.append(tc) - - sim_log = WALLY + "/sim/questa/logs/lockstep_wally-riscv-arch-test.log" - tc = TestCase( - name="lockstep_wally-riscv-arch-test", - variant="rv64gc", - cmd="iterelf " + WALLY + "/tests/riscof/work/wally-riscv-arch-test/rv64i_m > " + sim_log, - grepstr="SUCCESS! All tests ran without failures", - grepfile = sim_log) - configs.append(tc) + addLockstepTestsByDir(WALLY+"/tests/coverage", "rv64gc", "questa") + addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m", "rv64gc", "questa") addTests(derivconfigtests, defaultsim) # testfloat tests From b334dc50a44e780ef2f604c98c18626c40cc3fe0 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 8 Aug 2024 21:45:57 -0700 Subject: [PATCH 197/219] Fixed fldsp decompress with rd = 0 --- src/ifu/decompress.sv | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/ifu/decompress.sv b/src/ifu/decompress.sv index 798993d78..77e8ef219 100644 --- a/src/ifu/decompress.sv +++ b/src/ifu/decompress.sv @@ -151,8 +151,7 @@ module decompress import cvw::*; #(parameter cvw_t P) ( 5'b10000: if (rds1 != 5'b0) begin if (P.XLEN > 32 | ~immSH[5]) LInstrD = {1'b1, 6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli; shamt[5] must be 0 in RV32C end else if (immSH != 0) LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.slli with rd = 0, immm != 0 is a HINT, treated as nop - 5'b10001: if (P.ZCD_SUPPORTED) - if (rds1 != 5'b0) LInstrD = {1'b1, immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp + 5'b10001: if (P.ZCD_SUPPORTED) LInstrD = {1'b1, immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp 5'b10010: if (rds1 != 5'b0) LInstrD = {1'b1, immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp 5'b10011: if (P.XLEN == 32) begin if (P.ZCF_SUPPORTED) LInstrD = {1'b1, immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp From 5f0bc114fd39bc808c2a022ffddf9e33d7a65e89 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 8 Aug 2024 22:03:45 -0700 Subject: [PATCH 198/219] filter more console output --- bin/wally-tool-chain-install.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index dfda570bc..071d02599 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -67,7 +67,7 @@ git_check() { # Log output to a file and only print lines with keywords logger() { local log="$RISCV/logs/$1.log" - cat < /dev/stdin | tee -a "$log" | (grep -iE --color=never "(\bwarning|\berror|\bfail|\bsuccess|\bstamp)" || true) | (grep -viE --color=never "(Wno-error)" || true) + cat < /dev/stdin | tee -a "$log" | (grep -iE --color=never "(\bwarning|\berror|\bfail|\bsuccess|\bstamp)" || true) | (grep -viE --color=never "(_warning|warning_|_error|error_|-warning|warning-|-error|error-|Werror|error.o|warning flags)" || true) } set -e # break on error From 1f39b60619eca4cd091af79d0307028fc5e23e94 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 8 Aug 2024 22:04:27 -0700 Subject: [PATCH 199/219] Update python venv prompt --- bin/wally-tool-chain-install.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 071d02599..962f9ed3f 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -67,7 +67,7 @@ git_check() { # Log output to a file and only print lines with keywords logger() { local log="$RISCV/logs/$1.log" - cat < /dev/stdin | tee -a "$log" | (grep -iE --color=never "(\bwarning|\berror|\bfail|\bsuccess|\bstamp)" || true) | (grep -viE --color=never "(_warning|warning_|_error|error_|-warning|warning-|-error|error-|Werror|error.o|warning flags)" || true) + cat < /dev/stdin | tee -a "$log" | (grep -iE --color=never "(\bwarning|\berror|\bfail|\bsuccess|\bstamp)" || true) | (grep -viE --color=never "(_warning|warning_|_error|error_|-warning|warning-|-error|error-|Werror|error\.o|warning flags)" || true) } set -e # break on error @@ -135,7 +135,7 @@ section_header "Setting up Python Environment" STATUS="python virtual environment" cd "$RISCV" if [ ! -e "$RISCV"/riscv-python/bin/activate ]; then - "$PYTHON_VERSION" -m venv riscv-python + "$PYTHON_VERSION" -m venv riscv-python --prompt cvw echo -e "${OK_COLOR}Python virtual environment created!\nInstalling pip packages.${ENDC}" else echo -e "${OK_COLOR}Python virtual environment already exists.\nUpdating pip packages.${ENDC}" From e18d6b2744d4c8b09be68643bf52a2b756d74c8d Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 9 Aug 2024 06:18:38 -0700 Subject: [PATCH 200/219] Fixed lockstep simulation of directory of ELF files --- bin/regression-wally | 45 ++++++++++++++++++++++++++++++++------------ bin/wsim | 10 +++++++++- sim/questa/wally.do | 2 +- 3 files changed, 43 insertions(+), 14 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index 5cd8bf76c..cd4844b08 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -229,6 +229,13 @@ bpredtests = [ ["bpred_GSHARE_10_10_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"] ] +# list of tests not supported by ImperasDV yet that should be waived during lockstep testing +lockstepwaivers = [ + "WALLY-q-01.S_ref.elf", # Q extension is not supported by ImperasDV + "WALLY-cbom-01.S_ref.elf", # cbom extension is not supported by ImperasDV because there is no cache model in ImperasDV + "coverage_ieu.elf" # Issue 881: ImperasDV misinterprets 0x6BF05013 as a grevi rather than an illegal instruction +] + ################################## # Data Types & Functions ################################## @@ -282,21 +289,35 @@ def addTests(tests, sim): grepfile = grepfile) configs.append(tc) + def addLockstepTestsByDir(dir, config, sim): sim_logdir = WALLY+ "/sim/" + sim + "/logs/" cmdPrefix="wsim --lockstep --sim " + sim + " " + coverStr + " " + config - for file in os.listdir(dir): - if file.endswith(".elf"): - fullfile = os.path.join(dir, file) - sim_log = sim_logdir + config + "_" + file + ".log" - grepstring = "" - tc = TestCase( - name=file, - variant=config, - cmd=cmdPrefix + " " + fullfile + " > " + sim_log, - grepstr="Mismatches : 0", - grepfile = sim_log) - configs.append(tc) + if (os.path.isdir(dir)): + for dirpath, dirnames, filenames in os.walk(os.path.abspath(dir)): + for file in filenames: + if file.endswith(".elf"): + fullfile = os.path.join(dirpath, file) + fields = fullfile.rsplit('/', 3) + if (fields[2] == "ref"): + shortelf = fields[1] + "_" + fields[3] + else: + shortelf = fields[2] + "_" + fields[3] + if (shortelf in lockstepwaivers): # skip tests that itch bugs in ImperasDV + print(f"{bcolors.WARNING}Skipping waived test {shortelf}{bcolors.ENDC}") + continue + sim_log = sim_logdir + config + "_" + shortelf + ".log" + grepstring = "" + tc = TestCase( + name=file, + variant=config, + cmd=cmdPrefix + " " + fullfile + " > " + sim_log, + grepstr="Mismatches : 0", + grepfile = sim_log) + configs.append(tc) + else: + print("Error: Directory not found: " + dir) + exit(1) def search_log_for_text(text, grepfile): """Search through the given log file for text, returning True if it is found or False if it is not""" diff --git a/bin/wsim b/bin/wsim index e35ec6841..986957a3c 100755 --- a/bin/wsim +++ b/bin/wsim @@ -49,7 +49,15 @@ elif (args.elf != ""): if(args.testsuite.endswith('.elf') and args.elf == ""): # No --elf argument; check if testsuite has a .elf extension and use that instead if (os.path.isfile(args.testsuite)): ElfFile = "+ElfFile=" + os.path.abspath(args.testsuite) - if ('/' in args.testsuite): + # extract the elf name from the path to be the test suite + fields = args.testsuite.rsplit('/', 3) + # if the name is just ref.elf in a deep path (riscv-arch-test/wally-riscv-arch-test), then use the directory name as the test suite to make it unique; otherwise work directory will have duplicates. + if (len(fields) > 3): + if (fields[2] == "ref"): + args.testsuite = fields[1] + "_" + fields[3] + else: + args.testsuite = fields[2] + "_" + fields[3] + elif ('/' in args.testsuite): args.testsuite=args.testsuite.rsplit('/', 1)[1] # strip off path if present else: print("ELF file not found: " + args.testsuite) diff --git a/sim/questa/wally.do b/sim/questa/wally.do index db1cbbae1..35b728d83 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -222,7 +222,7 @@ vopt $accFlag wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} ${ParamArgs} vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} $temp0 $temp1 $temp2 $temp3 -fatal 7 ${SVLib} ${SVLibPath} ${OtherFlags} ${FCTRACE2COV} ${FCdefineIDV_TRACE2COV} -suppress 3829 ${CoverageVsimArg} # vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829 -# power add generates the logging necessary for said generation. +# power add generates the logging necessary for saif generation. # power add -r /dut/core/* if { ${GUI} } { add log -recursive /* From f534a75a093de26da211873cf23ecc7e7803ee5e Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 8 Aug 2024 23:44:40 -0700 Subject: [PATCH 201/219] Update gcc activation method for old distros --- bin/wally-tool-chain-install.sh | 12 +----------- site-setup.csh | 5 +++++ site-setup.sh | 7 +++++++ 3 files changed, 13 insertions(+), 11 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 962f9ed3f..c5dd0fbd3 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -426,16 +426,6 @@ cd "$RISCV" if [ ! -e "${RISCV}"/site-setup.sh ]; then wget https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.sh wget https://raw.githubusercontent.com/openhwgroup/cvw/main/site-setup.csh - # Add necessary lines to site-setup script to activate newer version of gcc for older distros - if [ "$FAMILY" == rhel ]; then - echo "# Activate newer gcc version" >> site-setup.sh - echo "source /opt/rh/gcc-toolset-13/enable" >> site-setup.sh - elif (( UBUNTU_VERSION == 20 )); then - echo "# Activate newer gcc version" >> site-setup.sh - echo "export PATH=\$RISCV/gcc-10/bin:\$PATH" >> site-setup.sh - echo "# Activate newer gcc version" >> site-setup.csh - echo "prepend PATH \$RISCV/gcc-10/bin" >> site-setup.csh - fi echo -e "${SUCCESS_COLOR}Site setup script successfully downloaded!${ENDC}" echo -e "${WARNING_COLOR}Make sure to edit the environment variables in $RISCV/site-setup.sh (or .csh) to point to your installation of EDA tools and licensce files.${ENDC}" else @@ -443,4 +433,4 @@ else echo -e "You may need to manually update it if there were changes upstream.${ENDC}" fi -echo -e "${SUCCESS_COLOR}${BOLD}\n\nINSTALLATION SUCCESSFUL!!!\n\n${ENDC}" +echo -e "${SUCCESS_COLOR}${BOLD}\n\nWALLY INSTALLATION SUCCESSFUL!!!\n\n${ENDC}" diff --git a/site-setup.csh b/site-setup.csh index c8435ddf5..867485a8d 100644 --- a/site-setup.csh +++ b/site-setup.csh @@ -56,3 +56,8 @@ if ($?IDV) then setupImperas ${IMPERAS_HOME} extend PATH $IDV/scripts/cvw endif + +# Use newer gcc version for older distros +if ( -e $RISCV/gcc-10 ) then + prepend PATH \$RISCV/gcc-10/bin # Ubuntu 20.04 LTS +endif diff --git a/site-setup.sh b/site-setup.sh index 5a76087a9..e2affd031 100755 --- a/site-setup.sh +++ b/site-setup.sh @@ -58,3 +58,10 @@ if [ -e "$IDV" ]; then setupImperas "${IMPERAS_HOME}" export PATH=$IDV/scripts/cvw:$PATH fi + +# Use newer gcc version for older distros +if [ -e /opt/rh/gcc-toolset-13/enable ]; then + source /opt/rh/gcc-toolset-13/enable # Red Hat Family +elif [ -e $RISCV/gcc-10 ]; then + export PATH=$RISCV/gcc-10/bin:$PATH # Ubuntu 20.04 LTS +fi From 564ce83e118998af22b112560e17000405d1bb11 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 9 Aug 2024 20:15:28 -0700 Subject: [PATCH 202/219] Update linker scripts to avoid hardcoded /opt/riscv --- fpga/zsbl/Makefile | 2 +- fpga/zsbl/linker1000.x | 1 - tests/custom/boot/Makefile | 2 +- tests/custom/cacheTest/Makefile | 2 +- tests/custom/crt0/Makefile | 2 +- tests/custom/fpga-blink-led/Makefile | 2 +- tests/custom/fpga-test-dram/Makefile | 2 +- tests/custom/fpga-test-sdc/Makefile | 2 +- tests/custom/james_mm/Makefile | 2 +- tests/custom/linker.x | 1 - tests/custom/linker1000.x | 1 - tests/custom/linker8000-0000.x | 1 - tests/custom/lpddrtest/Makefile | 2 +- tests/custom/mibench_qsort/Makefile | 2 +- tests/custom/sieve/Makefile | 2 +- tests/custom/simple/Makefile | 2 +- 16 files changed, 12 insertions(+), 16 deletions(-) diff --git a/fpga/zsbl/Makefile b/fpga/zsbl/Makefile index 85bfc67eb..fa22eb607 100644 --- a/fpga/zsbl/Makefile +++ b/fpga/zsbl/Makefile @@ -24,7 +24,7 @@ LIBRARY_FILES := MARCH :=-march=rv64imfdc_zifencei MABI :=-mabi=lp64d -LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles +LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -L $(RISCV)/riscv64-unknown-elf/lib LINKER :=linker1000.x diff --git a/fpga/zsbl/linker1000.x b/fpga/zsbl/linker1000.x index 6d9e948a6..b479e73dd 100644 --- a/fpga/zsbl/linker1000.x +++ b/fpga/zsbl/linker1000.x @@ -2,7 +2,6 @@ OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv", "elf64-littleriscv") OUTPUT_ARCH(riscv) ENTRY(_start) -SEARCH_DIR("/opt/riscv/riscv64-unknown-elf/lib"); SECTIONS { /* Read-only sections, merged into text segment: */ diff --git a/tests/custom/boot/Makefile b/tests/custom/boot/Makefile index 6fe9d2256..d4ebaa7f7 100644 --- a/tests/custom/boot/Makefile +++ b/tests/custom/boot/Makefile @@ -23,7 +23,7 @@ LIBRARY_FILES := MARCH :=-march=rv64imfdc MABI :=-mabi=lp64d -LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles +LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -L $(RISCV)/riscv64-unknown-elf/lib LINKER :=$(ROOT)/linker1000.x diff --git a/tests/custom/cacheTest/Makefile b/tests/custom/cacheTest/Makefile index f5ad40232..393cfd0ec 100644 --- a/tests/custom/cacheTest/Makefile +++ b/tests/custom/cacheTest/Makefile @@ -7,7 +7,7 @@ LIBRARY_FILES := crt0 MARCH :=-march=rv64imfdc MABI :=-mabi=lp64d LINKER := ${ROOT}/linker8000-0000.x -LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map +LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map -L $(RISCV)/riscv64-unknown-elf/lib CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany -mstrict-align -O2 CC=riscv64-unknown-elf-gcc diff --git a/tests/custom/crt0/Makefile b/tests/custom/crt0/Makefile index 0b6a3af23..ec6d662cf 100644 --- a/tests/custom/crt0/Makefile +++ b/tests/custom/crt0/Makefile @@ -6,7 +6,7 @@ LIBRARY_FILES := MARCH :=-march=rv64imfdc MABI :=-mabi=lp64d -LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles +LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -L $(RISCV)/riscv64-unknown-elf/lib LINKER := ${ROOT}/linker.x AFLAGS =$(MARCH) $(MABI) -W diff --git a/tests/custom/fpga-blink-led/Makefile b/tests/custom/fpga-blink-led/Makefile index df7544416..3ccf1927d 100644 --- a/tests/custom/fpga-blink-led/Makefile +++ b/tests/custom/fpga-blink-led/Makefile @@ -23,7 +23,7 @@ LIBRARY_FILES := MARCH :=-march=rv64imfdc MABI :=-mabi=lp64d -LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles +LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -L $(RISCV)/riscv64-unknown-elf/lib LINKER :=$(ROOT)/linker1000.x diff --git a/tests/custom/fpga-test-dram/Makefile b/tests/custom/fpga-test-dram/Makefile index df7544416..3ccf1927d 100644 --- a/tests/custom/fpga-test-dram/Makefile +++ b/tests/custom/fpga-test-dram/Makefile @@ -23,7 +23,7 @@ LIBRARY_FILES := MARCH :=-march=rv64imfdc MABI :=-mabi=lp64d -LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles +LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -L $(RISCV)/riscv64-unknown-elf/lib LINKER :=$(ROOT)/linker1000.x diff --git a/tests/custom/fpga-test-sdc/Makefile b/tests/custom/fpga-test-sdc/Makefile index 32affba87..a5e24a56e 100644 --- a/tests/custom/fpga-test-sdc/Makefile +++ b/tests/custom/fpga-test-sdc/Makefile @@ -23,7 +23,7 @@ LIBRARY_FILES := MARCH :=-march=rv64imfdc MABI :=-mabi=lp64d -LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles +LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -L $(RISCV)/riscv64-unknown-elf/lib LINKER :=$(ROOT)/linker1000.x diff --git a/tests/custom/james_mm/Makefile b/tests/custom/james_mm/Makefile index d13a3ad8d..adc5c1ef6 100644 --- a/tests/custom/james_mm/Makefile +++ b/tests/custom/james_mm/Makefile @@ -6,7 +6,7 @@ LIBRARY_FILES := crt0 MARCH :=-march=rv64imfdc MABI :=-mabi=lp64d -LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map +LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map -L $(RISCV)/riscv64-unknown-elf/lib LINKER := ${ROOT}/linker8000-0000.x CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany -mstrict-align -O2 diff --git a/tests/custom/linker.x b/tests/custom/linker.x index f448109cc..95618b722 100644 --- a/tests/custom/linker.x +++ b/tests/custom/linker.x @@ -2,7 +2,6 @@ OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv", "elf64-littleriscv") OUTPUT_ARCH(riscv) ENTRY(_start) -SEARCH_DIR("/opt/riscv/riscv64-unknown-elf/lib"); SECTIONS { /* Read-only sections, merged into text segment: */ diff --git a/tests/custom/linker1000.x b/tests/custom/linker1000.x index 6d9e948a6..b479e73dd 100644 --- a/tests/custom/linker1000.x +++ b/tests/custom/linker1000.x @@ -2,7 +2,6 @@ OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv", "elf64-littleriscv") OUTPUT_ARCH(riscv) ENTRY(_start) -SEARCH_DIR("/opt/riscv/riscv64-unknown-elf/lib"); SECTIONS { /* Read-only sections, merged into text segment: */ diff --git a/tests/custom/linker8000-0000.x b/tests/custom/linker8000-0000.x index 548c9d45c..3635f8d27 100644 --- a/tests/custom/linker8000-0000.x +++ b/tests/custom/linker8000-0000.x @@ -2,7 +2,6 @@ OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv", "elf64-littleriscv") OUTPUT_ARCH(riscv) ENTRY(_start) -SEARCH_DIR("/opt/riscv/riscv64-unknown-elf/lib"); SECTIONS { /* Read-only sections, merged into text segment: */ diff --git a/tests/custom/lpddrtest/Makefile b/tests/custom/lpddrtest/Makefile index 71710fcb5..50d2aae07 100644 --- a/tests/custom/lpddrtest/Makefile +++ b/tests/custom/lpddrtest/Makefile @@ -7,7 +7,7 @@ LIBRARY_FILES := crt0 MARCH :=-march=rv64imfdczicbom MABI :=-mabi=lp64d LINKER := ${ROOT}/linker8000-0000.x -LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map +LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map -L $(RISCV)/riscv64-unknown-elf/lib CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany -mstrict-align -O2 CC=riscv64-unknown-elf-gcc diff --git a/tests/custom/mibench_qsort/Makefile b/tests/custom/mibench_qsort/Makefile index a738265da..0f9bba726 100644 --- a/tests/custom/mibench_qsort/Makefile +++ b/tests/custom/mibench_qsort/Makefile @@ -6,7 +6,7 @@ LIBRARY_FILES := crt0 MARCH :=-march=rv64ic MABI :=-mabi=lp64 -LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map +LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map -L $(RISCV)/riscv64-unknown-elf/lib LINKER := ${ROOT}/linker8000-0000.x CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany -mstrict-align -O2 diff --git a/tests/custom/sieve/Makefile b/tests/custom/sieve/Makefile index c000b04eb..4c7c675af 100644 --- a/tests/custom/sieve/Makefile +++ b/tests/custom/sieve/Makefile @@ -6,7 +6,7 @@ LIBRARY_FILES := crt0 MARCH :=-march=rv64ic MABI :=-mabi=lp64 -LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map +LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map -L $(RISCV)/riscv64-unknown-elf/lib LINKER := ${ROOT}/linker8000-0000.x CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany -mstrict-align -O2 diff --git a/tests/custom/simple/Makefile b/tests/custom/simple/Makefile index 2c8c2bdab..6281df7d8 100644 --- a/tests/custom/simple/Makefile +++ b/tests/custom/simple/Makefile @@ -7,7 +7,7 @@ LIBRARY_FILES := crt0 MARCH :=-march=rv64imfdczicbom MABI :=-mabi=lp64d LINKER := ${ROOT}/linker8000-0000.x -LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map +LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map -L $(RISCV)/riscv64-unknown-elf/lib CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany -mstrict-align -O2 CC=riscv64-unknown-elf-gcc From 705ee60618d32a3d6d0d0a0fc9bd9fb162e46662 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 13 Aug 2024 06:45:45 -0700 Subject: [PATCH 203/219] Fixed c.slli hint discovered by Lee (Issue 910) --- src/ifu/decompress.sv | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/ifu/decompress.sv b/src/ifu/decompress.sv index 77e8ef219..6d49e0e0a 100644 --- a/src/ifu/decompress.sv +++ b/src/ifu/decompress.sv @@ -148,9 +148,12 @@ module decompress import cvw::*; #(parameter cvw_t P) ( 5'b01101: LInstrD = {1'b1, immCJ, 5'b00000, 7'b1101111}; // c.j 5'b01110: LInstrD = {1'b1, immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011}; // c.beqz 5'b01111: LInstrD = {1'b1, immCB[11:5], 5'b00000, rs1p, 3'b001, immCB[4:0], 7'b1100011}; // c.bnez - 5'b10000: if (rds1 != 5'b0) begin - if (P.XLEN > 32 | ~immSH[5]) LInstrD = {1'b1, 6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli; shamt[5] must be 0 in RV32C - end else if (immSH != 0) LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.slli with rd = 0, immm != 0 is a HINT, treated as nop + 5'b10000: if (immSH != 0) begin + if (P.XLEN > 32 | ~immSH[5]) begin // shamt[5] = 1 is reserved in RV32C + if (rds1 != 5'b0) LInstrD = {1'b1, 6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli + else LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.slli with rd = 0 is a HINT, treated as nop + end + end else LInstrD = {1'b1, 25'b0, 7'b0010011}; // c.slli with immm = 0 is a HINT, treated as nop 5'b10001: if (P.ZCD_SUPPORTED) LInstrD = {1'b1, immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp 5'b10010: if (rds1 != 5'b0) LInstrD = {1'b1, immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp 5'b10011: if (P.XLEN == 32) begin From 125884eb743912e2f31626675d3f251789f633d8 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 13 Aug 2024 07:34:58 -0700 Subject: [PATCH 204/219] Fixes mstatus.FS to also be set when a FP operation sets a floating-point flag even if it doesnt write a FP register --- sim/imperas.ic | 5 ++++- src/privileged/csr.sv | 8 ++++---- src/privileged/csrsr.sv | 4 ++-- src/privileged/csru.sv | 4 ++-- 4 files changed, 12 insertions(+), 9 deletions(-) diff --git a/sim/imperas.ic b/sim/imperas.ic index 6ea5725a0..3ad843cf4 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -68,6 +68,9 @@ --override cpu/PMP_registers=16 --override cpu/PMP_undefined=T +# mstatus.FS is set dirty on any write to a FPR, or when a fp operation signals an exception +--override cpu/mstatus_fs_mode=rvfs_write_nz + # PMA Settings # 'r': read access allowed # 'w': write access allowed @@ -101,7 +104,7 @@ # Add Imperas simulator application instruction tracing # uncomment these to provide tracing -#--verbose --trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange # --traceafter 300000000 +--verbose --trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange # --traceafter 300000000 --override cpu/debugflags=6 --override cpu/verbose=1 --override cpu/show_c_prefix=T diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index 13dedffa2..ad3dab32d 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -110,7 +110,7 @@ module csr import cvw::*; #(parameter cvw_t P) ( logic WriteMSTATUSM, WriteMSTATUSHM, WriteSSTATUSM; logic CSRMWriteM, CSRSWriteM, CSRUWriteM; logic UngatedCSRMWriteM; - logic WriteFRMM, WriteFFLAGSM; + logic WriteFRMM, SetOrWriteFFLAGSM; logic [P.XLEN-1:0] UnalignedNextEPCM, NextEPCM, NextMtvalM; logic [4:0] NextCauseM; logic [11:0] CSRAdrM; @@ -222,7 +222,7 @@ module csr import cvw::*; #(parameter cvw_t P) ( csrsr #(P) csrsr(.clk, .reset, .StallW, .WriteMSTATUSM, .WriteMSTATUSHM, .WriteSSTATUSM, .TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW, - .mretM, .sretM, .WriteFRMM, .WriteFFLAGSM, .CSRWriteValM, .SelHPTW, + .mretM, .sretM, .WriteFRMM, .SetOrWriteFFLAGSM, .CSRWriteValM, .SelHPTW, .MSTATUS_REGW, .SSTATUS_REGW, .MSTATUSH_REGW, .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TW, .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM, @@ -267,14 +267,14 @@ module csr import cvw::*; #(parameter cvw_t P) ( if (P.F_SUPPORTED) begin:csru csru #(P) csru(.clk, .reset, .InstrValidNotFlushedM, .CSRUWriteM, .CSRAdrM, .CSRWriteValM, .STATUS_FS, .CSRUReadValM, - .SetFflagsM, .FRM_REGW, .WriteFRMM, .WriteFFLAGSM, + .SetFflagsM, .FRM_REGW, .WriteFRMM, .SetOrWriteFFLAGSM, .IllegalCSRUAccessM); end else begin assign FRM_REGW = '0; assign CSRUReadValM = '0; assign IllegalCSRUAccessM = 1'b1; assign WriteFRMM = 1'b0; - assign WriteFFLAGSM = 1'b0; + assign SetOrWriteFFLAGSM = 1'b0; end if (P.ZICNTR_SUPPORTED) begin:counters diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv index dc970921e..d0a7b00c6 100644 --- a/src/privileged/csrsr.sv +++ b/src/privileged/csrsr.sv @@ -34,7 +34,7 @@ module csrsr import cvw::*; #(parameter cvw_t P) ( input logic TrapM, FRegWriteM, input logic [1:0] NextPrivilegeModeM, PrivilegeModeW, input logic mretM, sretM, - input logic WriteFRMM, WriteFFLAGSM, + input logic WriteFRMM, SetOrWriteFFLAGSM, input logic [P.XLEN-1:0] CSRWriteValM, input logic SelHPTW, output logic [P.XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, MSTATUSH_REGW, @@ -209,6 +209,6 @@ module csrsr import cvw::*; #(parameter cvw_t P) ( STATUS_SPIE <= P.S_SUPPORTED & CSRWriteValM[5]; STATUS_SIE <= P.S_SUPPORTED & CSRWriteValM[1]; STATUS_UBE <= CSRWriteValM[6] & P.U_SUPPORTED & P.BIGENDIAN_SUPPORTED; - end else if (FRegWriteM | WriteFRMM | WriteFFLAGSM) STATUS_FS_INT <= 2'b11; + end else if (FRegWriteM | WriteFRMM | SetOrWriteFFLAGSM) STATUS_FS_INT <= 2'b11; end endmodule diff --git a/src/privileged/csru.sv b/src/privileged/csru.sv index eeb364a89..86a9089e8 100644 --- a/src/privileged/csru.sv +++ b/src/privileged/csru.sv @@ -37,7 +37,7 @@ module csru import cvw::*; #(parameter cvw_t P) ( output logic [P.XLEN-1:0] CSRUReadValM, input logic [4:0] SetFflagsM, output logic [2:0] FRM_REGW, - output logic WriteFRMM, WriteFFLAGSM, + output logic WriteFRMM, SetOrWriteFFLAGSM, output logic IllegalCSRUAccessM ); @@ -48,7 +48,7 @@ module csru import cvw::*; #(parameter cvw_t P) ( logic [4:0] FFLAGS_REGW; logic [2:0] NextFRMM; logic [4:0] NextFFLAGSM; - logic SetOrWriteFFLAGSM; + logic WriteFFLAGSM; // Write enables assign WriteFRMM = CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FRM | CSRAdrM == FCSR); From 5946f833d2c383367d30e5a0932f42fd4d7e4fe6 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 15 Aug 2024 06:49:19 -0700 Subject: [PATCH 205/219] Added header for imperas.ic --- sim/imperas.ic | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/sim/imperas.ic b/sim/imperas.ic index 3ad843cf4..aee25eabf 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -1,3 +1,8 @@ +# imperas.ic +# Initialization file for ImperasDV lock step simulation +# David_Harris@hmc.edu 15 August 2024 +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + #--mpdconsole #--gdbconsole #--showoverrides From e5d262063fbec5bae2a9dff8fb8ac4298db89c7d Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 15 Aug 2024 10:43:20 -0700 Subject: [PATCH 206/219] Detect illegal writes to URO HPM counters --- src/privileged/csrc.sv | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/privileged/csrc.sv b/src/privileged/csrc.sv index d8ce0e709..848cb7e01 100644 --- a/src/privileged/csrc.sv +++ b/src/privileged/csrc.sv @@ -159,11 +159,11 @@ module csrc import cvw::*; #(parameter cvw_t P) ( if (P.XLEN==64) begin // 64-bit counter reads // Veri lator doesn't realize this only occurs for XLEN=64 /* verilator lint_off WIDTH */ - if (CSRAdrM == TIME) CSRCReadValM = MTIME_CLINT; // TIME register is a shadow of the memory-mapped MTIME from the CLINT + if (CSRAdrM == TIME & ~CSRWriteM) CSRCReadValM = MTIME_CLINT; // TIME register is a shadow of the memory-mapped MTIME from the CLINT /* verilator lint_on WIDTH */ else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+P.COUNTERS & CSRAdrM != MTIME) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM]; - else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+P.COUNTERS) + else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+P.COUNTERS & ~CSRWriteM) // read-only CSRCReadValM = HPMCOUNTER_REGW[CounterNumM]; else begin CSRCReadValM = '0; @@ -172,16 +172,16 @@ module csrc import cvw::*; #(parameter cvw_t P) ( end else begin // 32-bit counter reads // Veril ator doesn't realize this only occurs for XLEN=32 /* verilator lint_off WIDTH */ - if (CSRAdrM == TIME) CSRCReadValM = MTIME_CLINT[31:0];// TIME register is a shadow of the memory-mapped MTIME from the CLINT - else if (CSRAdrM == TIMEH) CSRCReadValM = MTIME_CLINT[63:32]; + if (CSRAdrM == TIME & ~CSRWriteM) CSRCReadValM = MTIME_CLINT[31:0];// TIME register is a shadow of the memory-mapped MTIME from the CLINT + else if (CSRAdrM == TIMEH & ~CSRWriteM) CSRCReadValM = MTIME_CLINT[63:32]; /* verilator lint_on WIDTH */ else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+P.COUNTERS & CSRAdrM != MTIME) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM]; - else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+P.COUNTERS) + else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+P.COUNTERS & ~CSRWriteM) // read-only CSRCReadValM = HPMCOUNTER_REGW[CounterNumM]; else if (CSRAdrM >= MHPMCOUNTERHBASE & CSRAdrM < MHPMCOUNTERHBASE+P.COUNTERS & CSRAdrM != MTIMEH) CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM]; - else if (CSRAdrM >= HPMCOUNTERHBASE & CSRAdrM < HPMCOUNTERHBASE+P.COUNTERS) + else if (CSRAdrM >= HPMCOUNTERHBASE & CSRAdrM < HPMCOUNTERHBASE+P.COUNTERS & ~CSRWriteM) // read-only CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM]; else begin CSRCReadValM = '0; From d9d5fc0827c50d7cbfa6711ca06a57199d08b088 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 15 Aug 2024 11:14:22 -0700 Subject: [PATCH 207/219] Refactor gitignore --- .gitignore | 300 ++++++++++++++++++++--------------------------------- 1 file changed, 112 insertions(+), 188 deletions(-) diff --git a/.gitignore b/.gitignore index 85d753d82..ec5520c64 100644 --- a/.gitignore +++ b/.gitignore @@ -1,78 +1,46 @@ +# General file extensions to ignore +.nfs* +*.objdump* +*.o +*.d +*.a +*.vstf +*.vcd +*.signature.output +*.dtb +*.log +*.map +*.elf* +*.list + +# General directories to ignore +.vscode/ +__pycache__/ **/work* -**/wally_*.log /**/obj_dir* /**/gmon* -.nfs* - -__pycache__/ -.vscode/ - #External repos addins/riscv-arch-test/Makefile.include addins/riscv-tests/target addins/TestFloat-3e/build/Linux-x86_64-GCC/* - -#vsim work files to ignore -transcript -vsim.wlf -wlft* -wlft* -/imperas-riscv-tests/FunctionRadix_32.addr -/imperas-riscv-tests/FunctionRadix_64.addr -/imperas-riscv-tests/FunctionRadix.addr -/imperas-riscv-tests/ProgramMap.txt -/imperas-riscv-tests/logs -*.o -*.d -*.vstf -testsBP/*/*/*.elf* -testsBP/*/OBJ/* -testsBP/*/*.a -tests/wally-riscv-arch-test/riscv-test-suite/*/I/*/* -tests/riscof/riscof_work/ +# Tests tests/riscof/config32.ini tests/riscof/config32e.ini tests/riscof/config64.ini -tests/linux-testgen/linux-testvectors/* -!tests/linux-testgen/linux-testvectors/tvCopier.py -!tests/linux-testgen/linux-testvectors/tvLinker.sh -!tests/linux-testgen/linux-testvectors/tvUnlinker.sh -tests/linux-testgen/buildroot -tests/linux-testgen/buildroot-image-output -tests/linux-testgen/buildroot-config-src/main.config.old -tests/linux-testgen/buildroot-config-src/linux.config.old -tests/linux-testgen/buildroot-config-src/busybox.config.old +tests/riscof/riscof_work/ +tests/wally-riscv-arch-test/riscv-test-suite/*/I/*/** +tests/fp/vectors/*.tv +tests/fp/combined_IF_vectors/IF_vectors/*.tv +tests/custom/*/*/ +tests/custom/*/*/*.memfile +tests/riscvdv +tests/functcov + +# Linux linux/buildroot linux/testvector-generation/boottrace.S -linux/testvector-generation/boottrace_disasm.log -sim/slack-notifier/slack-webhook-url.txt -fpga/generator/IP -fpga/generator/vivado.* -fpga/generator/.Xil/* -fpga/generator/WallyFPGA* -fpga/generator/reports/ -fpga/generator/*.log -fpga/generator/*.jou -*.objdump* -*.signature.output -examples/asm/sumtest/sumtest -examples/asm/example/example -examples/C/sum/sum -examples/C/fir/fir -examples/fp/softfloat_demo/softfloat_demo -examples/fp/softfloat_demo/softfloat_demoDP -examples/fp/softfloat_demo/softfloat_demoQP -examples/fp/softfloat_demo/softfloat_demoSP -examples/fp/fpcalc/fpcalc -examples/fp/sqrttest/sqrttest -examples/C/inline/inline -examples/C/mcmodel/mcmodel -examples/C/sum_mixed/sum_mixed -examples/asm/trap/trap -examples/asm/etc/pause -src/fma/fma16_testgen linux/devicetree/debug/* !linux/devicetree/debug/dump-dts.sh linux/testvector-generation/genCheckpoint.gdb @@ -80,10 +48,30 @@ linux/testvector-generation/silencePipe linux/testvector-generation/silencePipe.control linux/testvector-generation/fixBinMem linux/testvector-generation/qemu-serial -*.dtb + +# FPGA +fpga/generator/IP +fpga/generator/vivado.* +fpga/generator/.Xil/* +fpga/generator/WallyFPGA* +fpga/generator/reports/ +fpga/generator/*.jou +fpga/src/sdc/* +fpga/src/sdc.tar.gz +fpga/src/CopiedFiles_do_not_add_to_repo/* +fpga/generator/sim/imp-funcsim.v +fpga/generator/sim/imp-timesim.sdf +fpga/generator/sim/imp-timesim.v +fpga/generator/sim/syn-funcsim.v +fpga/rvvidaemon/rvvidaemon +fpga/zsbl/OBJ/* +fpga/zsbl/bin/* +fpga/src/boot.mem +fpga/src/data.mem + +# Synthesis synthDC/WORK synthDC/alib-52 -synthDC/*.log synthDC/*.svf synthDC/runs/ synthDC/newRuns @@ -92,128 +80,51 @@ synthDC/ppa/plots synthDC/wallyplots/ synthDC/runArchive synthDC/hdl -sim/power.saif -tests/fp/vectors synthDC/Summary.csv -tests/custom/work -tests/custom/*/*/*.list -tests/custom/*/*/*.elf -tests/custom/*/*/*.map -tests/custom/*/*/*.memfile -tests/custom/crt0/*.a -tests/custom/*/*.elf* -sim/sd_model.log -fpga/src/sdc/* -fpga/src/sdc.tar.gz -fpga/src/CopiedFiles_do_not_add_to_repo/* -fpga/src/boot.mem -fpga/src/data.mem -sim/branch.log -/fpga/generator/sim/imp-funcsim.v -/fpga/generator/sim/imp-timesim.sdf -/fpga/generator/sim/imp-timesim.v -/fpga/generator/sim/syn-funcsim.v -external -sim/results -tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/src/*.S -tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/Makefrag -sim/branch_BP_GSHARE10.log -sim/branch_BP_GSHARE16.log -sim/questa/imperas.log -sim/results-error/ -sim/test1.rep -sim/questa/vsim.log -tests/coverage/*.elf -*.elf.memfile -sim/*Cache.log -sim/branch -tests/fp/combined_IF_vectors/IF_vectors/*.tv -/sim/branch-march14.tar.gz -/sim/gshareforward-no-class -/sim/lint-wally_32 -/sim/lint-wally_32e -/sim/local16.txt -/sim/localhistory_m6k10_results_april24.txt -/sim/log.log -/sim/obj_dir/Vtestbench.cpp -/sim/obj_dir/Vtestbench.h -/sim/obj_dir/Vtestbench.mk -/sim/obj_dir/Vtestbench__ConstPool_0.cpp -/sim/obj_dir/Vtestbench__Syms.cpp -/sim/obj_dir/Vtestbench__Syms.h -/sim/obj_dir/Vtestbench___024root.h -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__0.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__0__Slow.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__1.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__10.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__11.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__1__Slow.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__2.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__2__Slow.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__3.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__3__Slow.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__4.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__4__Slow.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__5.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__5__Slow.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__6.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__7.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__8.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__9.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hfc24d085__0.cpp -/sim/obj_dir/Vtestbench___024root__DepSet_hfc24d085__0__Slow.cpp -/sim/obj_dir/Vtestbench___024root__Slow.cpp -/sim/obj_dir/Vtestbench___024unit.h -/sim/obj_dir/Vtestbench___024unit__DepSet_hf87c9ffd__0__Slow.cpp -/sim/obj_dir/Vtestbench___024unit__Slow.cpp -/sim/obj_dir/Vtestbench__verFiles.dat -/sim/obj_dir/Vtestbench_classes.mk -/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9.h -/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h34d4af8f__0.cpp -/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h34d4af8f__0__Slow.cpp -/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__0.cpp -/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__0__Slow.cpp -/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__1.cpp -/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__Slow.cpp -/sim/obj_dir/Vtestbench_tlbram__Pz1_T20.h -/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_h3df7cb71__0.cpp -/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_hab70f5b0__0.cpp -/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_hab70f5b0__0__Slow.cpp -/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__Slow.cpp -sim/bp-results/*.log -sim/branch*.log -/tests/custom/fpga-test-sdc/bin/fpga-test-sdc + +# Benchmarks benchmarks/embench/wally*.json benchmarks/embench/run* -sim/cfi.log +benchmarks/coremark/coremark_results.csv + +# Simulation +sim/*.svg +sim/power.saif +sim/results +sim/results-error/ +sim/test1.rep +sim/branch +sim/branch-march14.tar.gz +sim/gshareforward-no-class +sim/local16.txt +sim/localhistory_m6k10_results_april24.txt sim/cfi/* sim/branch/* -sim/obj_dir -examples/verilog/fulladder/obj_dir -examples/verilog/fulladder/fulladder.vcd -config/deriv -docs/docker/buildroot-config-src -docs/docker/testvector-generation -sim/questa/cov -sim/questa/fcovrvvi -sim/questa/fcovrvvi_logs -sim/questa/fcovrvvi_ucdb sim/covhtmlreport/ + +# Questa sim/questa/logs sim/questa/wkdir sim/questa/ucdb -sim/questa/fcov +sim/questa/cov +sim/questa/fcov +sim/questa/fcovrvvi +sim/questa/fcovrvvi_logs +sim/questa/fcovrvvi_ucdb sim/questa/fcov_logs sim/questa/fcov_ucdb -sim/verilator/logs -sim/verilator/wkdir +sim/questa/functcov_logs +sim/questa/functcov_ucdbs +sim/questa/functcov +sim/questa/riscv.ucdb +transcript +vsim.wlf +wlft* + +# VCS sim/vcs/logs sim/vcs/wkdir sim/vcs/ucdb -benchmarks/coremark/coremark_results.csv -fpga/zsbl/OBJ/* -fpga/zsbl/bin/* -sim/*.svg sim/vcs/csrc sim/vcs/profileReport* sim/vcs/program.out @@ -222,17 +133,13 @@ sim/vcs/simprofile_dir sim/vcs/ucli.key sim/vcs/verdi_config_file sim/vcs/vcdplus.vpd -sim/*/testbench.vcd -sim/questa/imperas.log -sim/questa/functcov.log -sim/questa/functcov_logs/* -sim/questa/functcov_ucdbs/* -sim/questa/functcov -sim/questa/riscv.ucdb -sim/questa/riscv.ucdb.log -sim/questa/riscv.ucdb.summary.log -sim/questa/riscv.ucdb.testdetails.log -tests/riscvdv +sim/vcs/simprofile* + +# Verilator +sim/verilator/logs +sim/verilator/wkdir + +# Examples examples/verilog/fulladder/csrc/ examples/verilog/fulladder/profileReport.html examples/verilog/fulladder/profileReport.json @@ -242,10 +149,27 @@ examples/verilog/fulladder/simprofile_dir/ examples/verilog/fulladder/simv.daidir/ examples/verilog/fulladder/ucli.key examples/verilog/fulladder/verdi_config_file +examples/fp/softfloat_demo/softfloat_demo +examples/fp/softfloat_demo/softfloat_demoDP +examples/fp/softfloat_demo/softfloat_demoQP +examples/fp/softfloat_demo/softfloat_demoSP +examples/fp/fpcalc/fpcalc +examples/fp/sqrttest/sqrttest examples/crypto/gfmul/gfmul -tests/functcov -tests/functcov/* -tests/functcov/*/* -sim/vcs/simprofile* -sim/verilator/verilator.log -/fpga/rvvidaemon/rvvidaemon +examples/C/fir/fir +examples/C/inline/inline +examples/C/mcmodel/mcmodel_medany +examples/C/mcmodel/mcmodel_medlow +examples/C/sum/sum +examples/C/sum_mixed/sum_mixed +examples/asm/sumtest/sumtest +examples/asm/example/example +examples/asm/trap/trap +examples/asm/etc/pause + +# Other +external +config/deriv +sim/slack-notifier/slack-webhook-url.txt +docs/docker/buildroot-config-src +docs/docker/testvector-generation From 09122f91c8874b26129a805f258015d15ebfb87f Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 13 Aug 2024 23:25:17 -0700 Subject: [PATCH 208/219] Update root Makefile --- Makefile | 37 +++++++++++++------------------------ 1 file changed, 13 insertions(+), 24 deletions(-) diff --git a/Makefile b/Makefile index 2ac48b2ed..f6c5b3eae 100644 --- a/Makefile +++ b/Makefile @@ -4,45 +4,34 @@ SIM = ${WALLY}/sim -all: - make riscof - make zsbl - make testfloat -# make verify - make coverage -# make benchmarks +.PHONY: all riscof testfloat zsbl benchmarks coremark embench coverage clean + +all: riscof testfloat zsbl coverage # benchmarks # riscof builds the riscv-arch-test and wally-riscv-arch-test suites riscof: - make -C sim + $(MAKE) -C sim testfloat: - cd ${WALLY}/addins/SoftFloat-3e/build/Linux-x86_64-GCC; make - cd ${WALLY}/addins/TestFloat-3e/build/Linux-x86_64-GCC; make - cd ${WALLY}/tests/fp; ./create_all_vectors.sh + $(MAKE) -C ${WALLY}/addins/SoftFloat-3e/build/Linux-x86_64-GCC + $(MAKE) -C ${WALLY}/addins/TestFloat-3e/build/Linux-x86_64-GCC + cd ${WALLY}/tests/fp && ./create_all_vectors.sh zsbl: $(MAKE) -C ${WALLY}/fpga/zsbl -verify: - cd ${SIM}; ./regression-wally - cd ${SIM}/sim; ./sim-testfloat-batch all - make imperasdv - benchmarks: - make coremark - make embench + $(MAKE) coremark + $(MAKE) embench coremark: - cd ${WALLY}/benchmarks/coremark; make; make run + cd ${WALLY}/benchmarks/coremark; $(MAKE); #$(MAKE) run embench: - cd ${WALLY}/benchmarks/embench; make; make run + cd ${WALLY}/benchmarks/embench; $(MAKE); #$(MAKE) run coverage: - make -C tests/coverage - + $(MAKE) -C tests/coverage clean: - make clean -C sim - + $(MAKE) clean -C sim From 8ca4a5f20e00933fb644fddf845ef7a010745c15 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 15 Aug 2024 11:56:55 -0700 Subject: [PATCH 209/219] FPGA Makefile refactoring --- fpga/generator/Makefile | 59 +++++++++++++++++++++++++---------------- 1 file changed, 36 insertions(+), 23 deletions(-) diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile index 5fbbfec33..3f33d55dd 100644 --- a/fpga/generator/Makefile +++ b/fpga/generator/Makefile @@ -1,43 +1,42 @@ dst := IP -# vcu118 -# export XILINX_PART := xcvu9p-flga2104-2L-e -# export XILINX_BOARD := xilinx.com:vcu118:part0:2.4 -# export board := vcu118 +all: ArtyA7 -# vcu108 -# export XILINX_PART := xcvu095-ffva2104-2-e -# export XILINX_BOARD := xilinx.com:vcu108:part0:1.7 -# export board := vcu108 +.PHONY: ArtyA7 vcu118 vcu108 -# Arty A7 -export XILINX_PART := xc7a100tcsg324-1 -export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1 -export board := ArtyA7 +ArtyA7: export XILINX_PART := xc7a100tcsg324-1 +ArtyA7: export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1 +ArtyA7: export board := ArtyA7 +ArtyA7: FPGA_Arty -# for Arty A7 and S7 boards -all: FPGA_Arty +vcu118: export XILINX_PART := xcvu9p-flga2104-2L-e +vcu118: export XILINX_BOARD := xilinx.com:vcu118:part0:2.4 +vcu118: export board := vcu118 +vcu118: FPGA_VCU -# VCU 108 and VCU 118 boards -#all: FPGA_VCU +vcu108: export XILINX_PART := xcvu095-ffva2104-2-e +vcu108: export XILINX_BOARD := xilinx.com:vcu108:part0:1.7 +vcu108: export board := vcu108 +vcu108: FPGA_VCU +.PHONY: FPGA_Arty FPGA_VCU FPGA_Arty: PreProcessFiles IP_Arty vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log - FPGA_VCU: PreProcessFiles IP_VCU vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log +# Generate IP Blocks +.PHONY: IP_Arty IP_VCU IP_VCU: $(dst)/xlnx_proc_sys_reset.log \ - $(dst)/xlnx_ddr4-$(board).log \ + MEM_VCU \ $(dst)/xlnx_axi_clock_converter.log \ $(dst)/xlnx_ahblite_axi_bridge.log \ $(dst)/xlnx_axi_crossbar.log \ $(dst)/xlnx_axi_dwidth_conv_32to64.log \ $(dst)/xlnx_axi_dwidth_conv_64to32.log \ $(dst)/xlnx_axi_prtcl_conv.log - IP_Arty: $(dst)/xlnx_proc_sys_reset.log \ - $(dst)/xlnx_ddr3-$(board).log \ + MEM_Arty \ $(dst)/xlnx_mmcm.log \ $(dst)/xlnx_axi_clock_converter.log \ $(dst)/xlnx_ahblite_axi_bridge.log @@ -46,7 +45,15 @@ IP_Arty: $(dst)/xlnx_proc_sys_reset.log \ #$(dst)/xlnx_axi_dwidth_conv_64to32.log \ #$(dst)/xlnx_axi_prtcl_conv.log +# Generate Memory IP Blocks +.PHONY: MEM_VCU MEM_Arty +MEM_VCU: + $(MAKE) $(dst)/xlnx_ddr4-$(board).log +MEM_Arty: + $(MAKE) $(dst)/xlnx_ddr3-$(board).log +# Copy files and make necessary modifications +.PHONY: PreProcessFiles PreProcessFiles: $(MAKE) -C ../../sim deriv rm -rf ../src/CopiedFiles_do_not_add_to_repo/ @@ -63,18 +70,24 @@ PreProcessFiles: sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/ram1p1rwbe.sv +# Generate Individual IP Blocks $(dst)/%.log: %.tcl mkdir -p IP cd IP;\ vivado -mode batch -source ../$*.tcl | tee $*.log +# Clean +.PHONY: cleanIP cleanLogs cleanFPGA cleanAll cleanIP: rm -rf IP - cleanLogs: rm -rf *.jou *.log - cleanFPGA: rm -rf WallyFPGA.* reports sim .Xil - cleanAll: cleanIP cleanLogs cleanFPGA + +# Aliases +.PHONY: arty artya7 VCU118 VCU108 +arty artya7: ArtyA7 +VCU118: vcu118 +VCU108: vcu108 From 00edbd0d95ac4e193c7e7c6638c3d485739711e5 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 15 Aug 2024 18:53:26 -0700 Subject: [PATCH 210/219] Testfloat vector generation refactoring --- Makefile | 12 +- tests/fp/Makefile | 34 +++ tests/fp/README.md | 328 +++++++++++----------- tests/fp/create_all_vectors.sh | 8 - tests/fp/create_vectors.sh | 483 --------------------------------- tests/fp/remove_spaces.sh | 483 --------------------------------- tests/fp/vectors/Makefile | 81 ++++++ tests/fp/{ => vectors}/case.sh | 0 8 files changed, 278 insertions(+), 1151 deletions(-) create mode 100755 tests/fp/Makefile delete mode 100755 tests/fp/create_all_vectors.sh delete mode 100755 tests/fp/create_vectors.sh delete mode 100755 tests/fp/remove_spaces.sh create mode 100755 tests/fp/vectors/Makefile rename tests/fp/{ => vectors}/case.sh (100%) diff --git a/Makefile b/Makefile index f6c5b3eae..c39c7b689 100644 --- a/Makefile +++ b/Makefile @@ -4,18 +4,19 @@ SIM = ${WALLY}/sim -.PHONY: all riscof testfloat zsbl benchmarks coremark embench coverage clean +.PHONY: all riscof testfloat combined_IF_vectors zsbl benchmarks coremark embench coverage clean -all: riscof testfloat zsbl coverage # benchmarks +all: riscof testfloat combined_IF_vectors zsbl coverage # benchmarks # riscof builds the riscv-arch-test and wally-riscv-arch-test suites riscof: $(MAKE) -C sim testfloat: - $(MAKE) -C ${WALLY}/addins/SoftFloat-3e/build/Linux-x86_64-GCC - $(MAKE) -C ${WALLY}/addins/TestFloat-3e/build/Linux-x86_64-GCC - cd ${WALLY}/tests/fp && ./create_all_vectors.sh + $(MAKE) -C ${WALLY}/tests/fp vectors + +combined_IF_vectors: testfloat riscof + $(MAKE) -C ${WALLY}/tests/fp combined_IF_vectors zsbl: $(MAKE) -C ${WALLY}/fpga/zsbl @@ -35,3 +36,4 @@ coverage: clean: $(MAKE) clean -C sim + $(MAKE) clean -C ${WALLY}/tests/fp diff --git a/tests/fp/Makefile b/tests/fp/Makefile new file mode 100755 index 000000000..d9e87d47c --- /dev/null +++ b/tests/fp/Makefile @@ -0,0 +1,34 @@ +# Jordan Carlin, jcarlin@hmc.edu, August 2024 +# Testfloat vector Makefile for CORE-V-Wally +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +SOFTFLOAT_DIR := ${WALLY}/addins/SoftFloat-3e/build/Linux-x86_64-GCC +TESTFLOAT_DIR := ${WALLY}/addins/TestFloat-3e/build/Linux-x86_64-GCC + +.PHONY: all softfloat testfloat vectors combined_IF_vectors clean + +all: vectors combined_IF_vectors + +softfloat: ${SOFTFLOAT_DIR}/softfloat.a + +testfloat: ${TESTFLOAT_DIR}/testfloat + +vectors: testfloat + $(MAKE) -C ${WALLY}/tests/fp/vectors + +combined_IF_vectors: ${WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/M/src vectors + cd ${WALLY}/tests/fp/combined_IF_vectors \ + && ./create_IF_vectors.sh + +clean: + $(MAKE) -C ${WALLY}/tests/fp/vectors clean + rm -f ${WALLY}/tests/fp/combined_IF_vectors/IF_vectors/*.tv + +${SOFTFLOAT_DIR}/softfloat.a: + $(MAKE) -C ${SOFTFLOAT_DIR} + +${TESTFLOAT_DIR}/testfloat: ${SOFTFLOAT_DIR}/softfloat.a + $(MAKE) -C ${TESTFLOAT_DIR} + +${WALLY}/tests/riscof/work/riscv-arch-test/rv32i_m/M/src: + @$(error "riscv-arch-tests must be generated first. Run make from $$WALLY") diff --git a/tests/fp/README.md b/tests/fp/README.md index 3508bcee4..ae60d0b5e 100644 --- a/tests/fp/README.md +++ b/tests/fp/README.md @@ -1,187 +1,171 @@ james.stine@okstate.edu 14 Jan 2022 -These are the testvectors (TV) to test the floating-point units using +These are the testvectors (TV) to test the floating-point unit using Berkeley TestFloat written originally by John Hauser. TestFloat requires both TestFloat and SoftFloat. -The locations at time of this README is found here: +The locations of these tools at time of this README is found here: TestFloat-3e: http://www.jhauser.us/arithmetic/TestFloat.html SoftFloat-3e: http://www.jhauser.us/arithmetic/SoftFloat.html -These files have been compiled on a x86_64 environment by going into -the build/Linux-x86_64-GCC directory and typing make. A script -createX.sh (e.g., create_vectors32.sh) has been included that create -the TV for each rounding mode and operation. These scripts must be -run in the build directory of TestFloat. +These tools have been compiled on a x86_64 environment by going into +their respective build/Linux-x86_64-GCC directories and running make. -A set of scripts is also include that runs everything from the -baseline directory. Please change the BUILD and OUTPUT variable to -change your baseline program where its compiled and where you want to -output the vectors. By default, the vectors are output into the -vectors subdirectory. +The makefile in the vectors subdirectory of this directory will generate TV +for each rounding mode and operation. It also puts an underscore between each +vector instead of a space to allow SystemVerilog readmemh to read correctly. -After each TV has been created a script (included) is run called -undy.sh that puts an underscore between vector to allow SystemVerilog -readmemh to read correctly. - -./undy.sh file.tv - -To remove all the underscores from all the TV files, one can run the -command that will add underscores appropriately to all the files. - -cd vectors -../undy.sh \* - -Note: due to size, the fxx_fma_xx.tv vectors are not included. -However, they can easily be created with the create scripts. +The makefile at the top level of this directory will compile SoftFloat and +TestFloat and then generate all of the TVs. It also generates TVs for the +combined integer floating-point divider. Although not needed, a case.sh script is included to change the case of the hex output. This is for those that do not like to see -hexadecimal capitalized :P. +hexadecimal capitalized :P. - 46464 185856 836352 f16_add_rd.tv - 46464 185856 836352 f16_add_rne.tv - 46464 185856 836352 f16_add_ru.tv - 46464 185856 836352 f16_add_rz.tv - 46464 185856 836352 f16_div_rd.tv - 46464 185856 836352 f16_div_rne.tv - 46464 185856 836352 f16_div_ru.tv - 46464 185856 836352 f16_div_rz.tv - 46464 185856 836352 f16_mul_rd.tv - 46464 185856 836352 f16_mul_rne.tv - 46464 185856 836352 f16_mul_ru.tv - 46464 185856 836352 f16_mul_rz.tv - 408 1224 5304 f16_sqrt_rd.tv - 408 1224 5304 f16_sqrt_rne.tv - 408 1224 5304 f16_sqrt_ru.tv - 408 1224 5304 f16_sqrt_rz.tv - 46464 185856 836352 f16_sub_rd.tv - 46464 185856 836352 f16_sub_rne.tv - 46464 185856 836352 f16_sub_ru.tv - 46464 185856 836352 f16_sub_rz.tv - 46464 185856 1393920 f32_add_rd.tv - 46464 185856 1393920 f32_add_rne.tv - 46464 185856 1393920 f32_add_ru.tv - 46464 185856 1393920 f32_add_rz.tv - 46464 185856 1068672 f32_cmp_eq_signaling.tv - 46464 185856 1068672 f32_cmp_eq.tv - 46464 185856 1068672 f32_cmp_le_quiet.tv - 46464 185856 1068672 f32_cmp_le.tv - 46464 185856 1068672 f32_cmp_lt_quiet.tv - 46464 185856 1068672 f32_cmp_lt.tv - 46464 185856 1393920 f32_div_rd.tv - 46464 185856 1393920 f32_div_rne.tv - 46464 185856 1393920 f32_div_ru.tv - 46464 185856 1393920 f32_div_rz.tv - 600 1800 17400 f32_f64_rd.tv - 600 1800 17400 f32_f64_rne.tv - 600 1800 17400 f32_f64_ru.tv - 600 1800 17400 f32_f64_rz.tv - 600 1800 12600 f32_i32_rd.tv - 600 1800 12600 f32_i32_rne.tv - 600 1800 12600 f32_i32_ru.tv - 600 1800 12600 f32_i32_rz.tv - 600 1800 17400 f32_i64_rd.tv - 600 1800 17400 f32_i64_rne.tv - 600 1800 17400 f32_i64_ru.tv - 600 1800 17400 f32_i64_rz.tv - 46464 185856 1393920 f32_mul_rd.tv - 46464 185856 1393920 f32_mul_rne.tv - 46464 185856 1393920 f32_mul_ru.tv - 46464 185856 1393920 f32_mul_rz.tv - 600 1800 12600 f32_sqrt_rd.tv - 600 1800 12600 f32_sqrt_rne.tv - 600 1800 12600 f32_sqrt_ru.tv - 600 1800 12600 f32_sqrt_rz.tv - 46464 185856 1393920 f32_sub_rd.tv - 46464 185856 1393920 f32_sub_rne.tv - 46464 185856 1393920 f32_sub_ru.tv - 46464 185856 1393920 f32_sub_rz.tv - 600 1800 12600 f32_ui32_rd.tv - 600 1800 12600 f32_ui32_rne.tv - 600 1800 12600 f32_ui32_ru.tv - 600 1800 12600 f32_ui32_rz.tv - 600 1800 17400 f32_ui64_rd.tv - 600 1800 17400 f32_ui64_rne.tv - 600 1800 17400 f32_ui64_ru.tv - 600 1800 17400 f32_ui64_rz.tv - 46464 185856 2509056 f64_add_rd.tv - 46464 185856 2509056 f64_add_rne.tv - 46464 185856 2509056 f64_add_ru.tv - 46464 185856 2509056 f64_add_rz.tv - 46464 185856 1812096 f64_cmp_eq_signaling.tv - 46464 185856 1812096 f64_cmp_eq.tv - 46464 185856 1812096 f64_cmp_le_quiet.tv - 46464 185856 1812096 f64_cmp_le.tv - 46464 185856 1812096 f64_cmp_lt_quiet.tv - 46464 185856 1812096 f64_cmp_lt.tv - 46464 185856 2509056 f64_div_rd.tv - 46464 185856 2509056 f64_div_rne.tv - 46464 185856 2509056 f64_div_ru.tv - 46464 185856 2509056 f64_div_rz.tv - 768 2304 22272 f64_f32_rd.tv - 768 2304 22272 f64_f32_rne.tv - 768 2304 22272 f64_f32_ru.tv - 768 2304 22272 f64_f32_rz.tv - 768 2304 22272 f64_i32_rd.tv - 768 2304 22272 f64_i32_rne.tv - 768 2304 22272 f64_i32_ru.tv - 768 2304 22272 f64_i32_rz.tv - 768 2304 28416 f64_i64_rd.tv - 768 2304 28416 f64_i64_rne.tv - 768 2304 28416 f64_i64_ru.tv - 768 2304 28416 f64_i64_rz.tv - 46464 185856 2509056 f64_mul_rd.tv - 46464 185856 2509056 f64_mul_rne.tv - 46464 185856 2509056 f64_mul_ru.tv - 46464 185856 2509056 f64_mul_rz.tv - 768 2304 28416 f64_sqrt_rd.tv - 768 2304 28416 f64_sqrt_rne.tv - 768 2304 28416 f64_sqrt_ru.tv - 768 2304 28416 f64_sqrt_rz.tv - 46464 185856 2509056 f64_sub_rd.tv - 46464 185856 2509056 f64_sub_rne.tv - 46464 185856 2509056 f64_sub_ru.tv - 46464 185856 2509056 f64_sub_rz.tv - 768 2304 22272 f64_ui32_rd.tv - 768 2304 22272 f64_ui32_rne.tv - 768 2304 22272 f64_ui32_ru.tv - 768 2304 22272 f64_ui32_rz.tv - 768 2304 28416 f64_ui64_rd.tv - 768 2304 28416 f64_ui64_rne.tv - 768 2304 28416 f64_ui64_ru.tv - 768 2304 28416 f64_ui64_rz.tv - 372 1116 7812 i32_f32_rd.tv - 372 1116 7812 i32_f32_rne.tv - 372 1116 7812 i32_f32_ru.tv - 372 1116 7812 i32_f32_rz.tv - 372 1116 10788 i32_f64_rd.tv - 372 1116 10788 i32_f64_rne.tv - 372 1116 10788 i32_f64_ru.tv - 372 1116 10788 i32_f64_rz.tv - 756 2268 21924 i64_f32_rd.tv - 756 2268 21924 i64_f32_rne.tv - 756 2268 21924 i64_f32_ru.tv - 756 2268 21924 i64_f32_rz.tv - 756 2268 27972 i64_f64_rd.tv - 756 2268 27972 i64_f64_rne.tv - 756 2268 27972 i64_f64_ru.tv - 756 2268 27972 i64_f64_rz.tv - 372 1116 7812 ui32_f32_rd.tv - 372 1116 7812 ui32_f32_rne.tv - 372 1116 7812 ui32_f32_ru.tv - 372 1116 7812 ui32_f32_rz.tv - 372 1116 10788 ui32_f64_rd.tv - 372 1116 10788 ui32_f64_rne.tv - 372 1116 10788 ui32_f64_ru.tv - 372 1116 10788 ui32_f64_rz.tv - 756 2268 21924 ui64_f32_rd.tv - 756 2268 21924 ui64_f32_rne.tv - 756 2268 21924 ui64_f32_ru.tv - 756 2268 21924 ui64_f32_rz.tv - 756 2268 27972 ui64_f64_rd.tv - 756 2268 27972 ui64_f64_rne.tv - 756 2268 27972 ui64_f64_ru.tv - 756 2268 27972 ui64_f64_rz.tv - 2840352 11308896 94651296 total + 46464 185856 836352 f16_add_rd.tv + 46464 185856 836352 f16_add_rne.tv + 46464 185856 836352 f16_add_ru.tv + 46464 185856 836352 f16_add_rz.tv + 46464 185856 836352 f16_div_rd.tv + 46464 185856 836352 f16_div_rne.tv + 46464 185856 836352 f16_div_ru.tv + 46464 185856 836352 f16_div_rz.tv + 46464 185856 836352 f16_mul_rd.tv + 46464 185856 836352 f16_mul_rne.tv + 46464 185856 836352 f16_mul_ru.tv + 46464 185856 836352 f16_mul_rz.tv + 408 1224 5304 f16_sqrt_rd.tv + 408 1224 5304 f16_sqrt_rne.tv + 408 1224 5304 f16_sqrt_ru.tv + 408 1224 5304 f16_sqrt_rz.tv + 46464 185856 836352 f16_sub_rd.tv + 46464 185856 836352 f16_sub_rne.tv + 46464 185856 836352 f16_sub_ru.tv + 46464 185856 836352 f16_sub_rz.tv + 46464 185856 1393920 f32_add_rd.tv + 46464 185856 1393920 f32_add_rne.tv + 46464 185856 1393920 f32_add_ru.tv + 46464 185856 1393920 f32_add_rz.tv + 46464 185856 1068672 f32_cmp_eq_signaling.tv + 46464 185856 1068672 f32_cmp_eq.tv + 46464 185856 1068672 f32_cmp_le_quiet.tv + 46464 185856 1068672 f32_cmp_le.tv + 46464 185856 1068672 f32_cmp_lt_quiet.tv + 46464 185856 1068672 f32_cmp_lt.tv + 46464 185856 1393920 f32_div_rd.tv + 46464 185856 1393920 f32_div_rne.tv + 46464 185856 1393920 f32_div_ru.tv + 46464 185856 1393920 f32_div_rz.tv + 600 1800 17400 f32_f64_rd.tv + 600 1800 17400 f32_f64_rne.tv + 600 1800 17400 f32_f64_ru.tv + 600 1800 17400 f32_f64_rz.tv + 600 1800 12600 f32_i32_rd.tv + 600 1800 12600 f32_i32_rne.tv + 600 1800 12600 f32_i32_ru.tv + 600 1800 12600 f32_i32_rz.tv + 600 1800 17400 f32_i64_rd.tv + 600 1800 17400 f32_i64_rne.tv + 600 1800 17400 f32_i64_ru.tv + 600 1800 17400 f32_i64_rz.tv + 46464 185856 1393920 f32_mul_rd.tv + 46464 185856 1393920 f32_mul_rne.tv + 46464 185856 1393920 f32_mul_ru.tv + 46464 185856 1393920 f32_mul_rz.tv + 600 1800 12600 f32_sqrt_rd.tv + 600 1800 12600 f32_sqrt_rne.tv + 600 1800 12600 f32_sqrt_ru.tv + 600 1800 12600 f32_sqrt_rz.tv + 46464 185856 1393920 f32_sub_rd.tv + 46464 185856 1393920 f32_sub_rne.tv + 46464 185856 1393920 f32_sub_ru.tv + 46464 185856 1393920 f32_sub_rz.tv + 600 1800 12600 f32_ui32_rd.tv + 600 1800 12600 f32_ui32_rne.tv + 600 1800 12600 f32_ui32_ru.tv + 600 1800 12600 f32_ui32_rz.tv + 600 1800 17400 f32_ui64_rd.tv + 600 1800 17400 f32_ui64_rne.tv + 600 1800 17400 f32_ui64_ru.tv + 600 1800 17400 f32_ui64_rz.tv + 46464 185856 2509056 f64_add_rd.tv + 46464 185856 2509056 f64_add_rne.tv + 46464 185856 2509056 f64_add_ru.tv + 46464 185856 2509056 f64_add_rz.tv + 46464 185856 1812096 f64_cmp_eq_signaling.tv + 46464 185856 1812096 f64_cmp_eq.tv + 46464 185856 1812096 f64_cmp_le_quiet.tv + 46464 185856 1812096 f64_cmp_le.tv + 46464 185856 1812096 f64_cmp_lt_quiet.tv + 46464 185856 1812096 f64_cmp_lt.tv + 46464 185856 2509056 f64_div_rd.tv + 46464 185856 2509056 f64_div_rne.tv + 46464 185856 2509056 f64_div_ru.tv + 46464 185856 2509056 f64_div_rz.tv + 768 2304 22272 f64_f32_rd.tv + 768 2304 22272 f64_f32_rne.tv + 768 2304 22272 f64_f32_ru.tv + 768 2304 22272 f64_f32_rz.tv + 768 2304 22272 f64_i32_rd.tv + 768 2304 22272 f64_i32_rne.tv + 768 2304 22272 f64_i32_ru.tv + 768 2304 22272 f64_i32_rz.tv + 768 2304 28416 f64_i64_rd.tv + 768 2304 28416 f64_i64_rne.tv + 768 2304 28416 f64_i64_ru.tv + 768 2304 28416 f64_i64_rz.tv + 46464 185856 2509056 f64_mul_rd.tv + 46464 185856 2509056 f64_mul_rne.tv + 46464 185856 2509056 f64_mul_ru.tv + 46464 185856 2509056 f64_mul_rz.tv + 768 2304 28416 f64_sqrt_rd.tv + 768 2304 28416 f64_sqrt_rne.tv + 768 2304 28416 f64_sqrt_ru.tv + 768 2304 28416 f64_sqrt_rz.tv + 46464 185856 2509056 f64_sub_rd.tv + 46464 185856 2509056 f64_sub_rne.tv + 46464 185856 2509056 f64_sub_ru.tv + 46464 185856 2509056 f64_sub_rz.tv + 768 2304 22272 f64_ui32_rd.tv + 768 2304 22272 f64_ui32_rne.tv + 768 2304 22272 f64_ui32_ru.tv + 768 2304 22272 f64_ui32_rz.tv + 768 2304 28416 f64_ui64_rd.tv + 768 2304 28416 f64_ui64_rne.tv + 768 2304 28416 f64_ui64_ru.tv + 768 2304 28416 f64_ui64_rz.tv + 372 1116 7812 i32_f32_rd.tv + 372 1116 7812 i32_f32_rne.tv + 372 1116 7812 i32_f32_ru.tv + 372 1116 7812 i32_f32_rz.tv + 372 1116 10788 i32_f64_rd.tv + 372 1116 10788 i32_f64_rne.tv + 372 1116 10788 i32_f64_ru.tv + 372 1116 10788 i32_f64_rz.tv + 756 2268 21924 i64_f32_rd.tv + 756 2268 21924 i64_f32_rne.tv + 756 2268 21924 i64_f32_ru.tv + 756 2268 21924 i64_f32_rz.tv + 756 2268 27972 i64_f64_rd.tv + 756 2268 27972 i64_f64_rne.tv + 756 2268 27972 i64_f64_ru.tv + 756 2268 27972 i64_f64_rz.tv + 372 1116 7812 ui32_f32_rd.tv + 372 1116 7812 ui32_f32_rne.tv + 372 1116 7812 ui32_f32_ru.tv + 372 1116 7812 ui32_f32_rz.tv + 372 1116 10788 ui32_f64_rd.tv + 372 1116 10788 ui32_f64_rne.tv + 372 1116 10788 ui32_f64_ru.tv + 372 1116 10788 ui32_f64_rz.tv + 756 2268 21924 ui64_f32_rd.tv + 756 2268 21924 ui64_f32_rne.tv + 756 2268 21924 ui64_f32_ru.tv + 756 2268 21924 ui64_f32_rz.tv + 756 2268 27972 ui64_f64_rd.tv + 756 2268 27972 ui64_f64_rne.tv + 756 2268 27972 ui64_f64_ru.tv + 756 2268 27972 ui64_f64_rz.tv + 2840352 11308896 94651296 total diff --git a/tests/fp/create_all_vectors.sh b/tests/fp/create_all_vectors.sh deleted file mode 100755 index bbade6d11..000000000 --- a/tests/fp/create_all_vectors.sh +++ /dev/null @@ -1,8 +0,0 @@ -#!/bin/sh - -mkdir -p vectors -./create_vectors.sh -./remove_spaces.sh - -# to create tvs for evaluation of combined IFdivsqrt -cd combined_IF_vectors; ./create_IF_vectors.sh \ No newline at end of file diff --git a/tests/fp/create_vectors.sh b/tests/fp/create_vectors.sh deleted file mode 100755 index 3ca574fc8..000000000 --- a/tests/fp/create_vectors.sh +++ /dev/null @@ -1,483 +0,0 @@ -#!/bin/sh -BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC" -OUTPUT="./vectors" -echo "Creating ui32_to_f16 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui32_to_f16 > $OUTPUT/ui32_to_f16_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui32_to_f16 > $OUTPUT/ui32_to_f16_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui32_to_f16 > $OUTPUT/ui32_to_f16_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui32_to_f16 > $OUTPUT/ui32_to_f16_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui32_to_f16 > $OUTPUT/ui32_to_f16_rnm.tv -echo "Creating ui32_to_f32 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui32_to_f32 > $OUTPUT/ui32_to_f32_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui32_to_f32 > $OUTPUT/ui32_to_f32_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui32_to_f32 > $OUTPUT/ui32_to_f32_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui32_to_f32 > $OUTPUT/ui32_to_f32_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui32_to_f32 > $OUTPUT/ui32_to_f32_rnm.tv -echo "Creating ui32_to_f64 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui32_to_f64 > $OUTPUT/ui32_to_f64_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui32_to_f64 > $OUTPUT/ui32_to_f64_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui32_to_f64 > $OUTPUT/ui32_to_f64_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui32_to_f64 > $OUTPUT/ui32_to_f64_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui32_to_f64 > $OUTPUT/ui32_to_f64_rnm.tv -echo "Creating ui32_to_f128 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui32_to_f128 > $OUTPUT/ui32_to_f128_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui32_to_f128 > $OUTPUT/ui32_to_f128_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui32_to_f128 > $OUTPUT/ui32_to_f128_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui32_to_f128 > $OUTPUT/ui32_to_f128_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui32_to_f128 > $OUTPUT/ui32_to_f128_rnm.tv -echo "Creating ui64_to_f16 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui64_to_f16 > $OUTPUT/ui64_to_f16_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui64_to_f16 > $OUTPUT/ui64_to_f16_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui64_to_f16 > $OUTPUT/ui64_to_f16_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui64_to_f16 > $OUTPUT/ui64_to_f16_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui64_to_f16 > $OUTPUT/ui64_to_f16_rnm.tv -echo "Creating ui64_to_f32 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui64_to_f32 > $OUTPUT/ui64_to_f32_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui64_to_f32 > $OUTPUT/ui64_to_f32_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui64_to_f32 > $OUTPUT/ui64_to_f32_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui64_to_f32 > $OUTPUT/ui64_to_f32_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui64_to_f32 > $OUTPUT/ui64_to_f32_rnm.tv -echo "Creating ui64_to_f64 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui64_to_f64 > $OUTPUT/ui64_to_f64_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui64_to_f64 > $OUTPUT/ui64_to_f64_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui64_to_f64 > $OUTPUT/ui64_to_f64_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui64_to_f64 > $OUTPUT/ui64_to_f64_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui64_to_f64 > $OUTPUT/ui64_to_f64_rnm.tv -echo "Creating ui64_to_f128 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui64_to_f128 > $OUTPUT/ui64_to_f128_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui64_to_f128 > $OUTPUT/ui64_to_f128_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui64_to_f128 > $OUTPUT/ui64_to_f128_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui64_to_f128 > $OUTPUT/ui64_to_f128_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui64_to_f128 > $OUTPUT/ui64_to_f128_rnm.tv -echo "Creating i32_to_f16 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i32_to_f16 > $OUTPUT/i32_to_f16_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i32_to_f16 > $OUTPUT/i32_to_f16_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax i32_to_f16 > $OUTPUT/i32_to_f16_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin i32_to_f16 > $OUTPUT/i32_to_f16_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i32_to_f16 > $OUTPUT/i32_to_f16_rnm.tv -echo "Creating i32_to_f32 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i32_to_f32 > $OUTPUT/i32_to_f32_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i32_to_f32 > $OUTPUT/i32_to_f32_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax i32_to_f32 > $OUTPUT/i32_to_f32_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin i32_to_f32 > $OUTPUT/i32_to_f32_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i32_to_f32 > $OUTPUT/i32_to_f32_rnm.tv -echo "Creating i32_to_f64 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i32_to_f64 > $OUTPUT/i32_to_f64_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i32_to_f64 > $OUTPUT/i32_to_f64_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax i32_to_f64 > $OUTPUT/i32_to_f64_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin i32_to_f64 > $OUTPUT/i32_to_f64_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i32_to_f64 > $OUTPUT/i32_to_f64_rnm.tv -echo "Creating i32_to_f128 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i32_to_f128 > $OUTPUT/i32_to_f128_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i32_to_f128 > $OUTPUT/i32_to_f128_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax i32_to_f128 > $OUTPUT/i32_to_f128_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin i32_to_f128 > $OUTPUT/i32_to_f128_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i32_to_f128 > $OUTPUT/i32_to_f128_rnm.tv -echo "Creating i64_to_f16 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i64_to_f16 > $OUTPUT/i64_to_f16_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i64_to_f16 > $OUTPUT/i64_to_f16_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax i64_to_f16 > $OUTPUT/i64_to_f16_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin i64_to_f16 > $OUTPUT/i64_to_f16_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i64_to_f16 > $OUTPUT/i64_to_f16_rnm.tv -echo "Creating i64_to_f32 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i64_to_f32 > $OUTPUT/i64_to_f32_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i64_to_f32 > $OUTPUT/i64_to_f32_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax i64_to_f32 > $OUTPUT/i64_to_f32_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin i64_to_f32 > $OUTPUT/i64_to_f32_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i64_to_f32 > $OUTPUT/i64_to_f32_rnm.tv -echo "Creating i64_to_f64 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i64_to_f64 > $OUTPUT/i64_to_f64_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i64_to_f64 > $OUTPUT/i64_to_f64_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax i64_to_f64 > $OUTPUT/i64_to_f64_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin i64_to_f64 > $OUTPUT/i64_to_f64_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i64_to_f64 > $OUTPUT/i64_to_f64_rnm.tv -echo "Creating i64_to_f128 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i64_to_f128 > $OUTPUT/i64_to_f128_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i64_to_f128 > $OUTPUT/i64_to_f128_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax i64_to_f128 > $OUTPUT/i64_to_f128_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin i64_to_f128 > $OUTPUT/i64_to_f128_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i64_to_f128 > $OUTPUT/i64_to_f128_rnm.tv -echo "Creating f16_to_ui32 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f16_to_ui32 > $OUTPUT/f16_to_ui32_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f16_to_ui32 > $OUTPUT/f16_to_ui32_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f16_to_ui32 > $OUTPUT/f16_to_ui32_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f16_to_ui32 > $OUTPUT/f16_to_ui32_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f16_to_ui32 > $OUTPUT/f16_to_ui32_rnm.tv -echo "Creating f32_to_ui32 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f32_to_ui32 > $OUTPUT/f32_to_ui32_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f32_to_ui32 > $OUTPUT/f32_to_ui32_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f32_to_ui32 > $OUTPUT/f32_to_ui32_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f32_to_ui32 > $OUTPUT/f32_to_ui32_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f32_to_ui32 > $OUTPUT/f32_to_ui32_rnm.tv -echo "Creating f64_to_ui32 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f64_to_ui32 > $OUTPUT/f64_to_ui32_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f64_to_ui32 > $OUTPUT/f64_to_ui32_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f64_to_ui32 > $OUTPUT/f64_to_ui32_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f64_to_ui32 > $OUTPUT/f64_to_ui32_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f64_to_ui32 > $OUTPUT/f64_to_ui32_rnm.tv -echo "Creating f128_to_ui32 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f128_to_ui32 > $OUTPUT/f128_to_ui32_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f128_to_ui32 > $OUTPUT/f128_to_ui32_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f128_to_ui32 > $OUTPUT/f128_to_ui32_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f128_to_ui32 > $OUTPUT/f128_to_ui32_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f128_to_ui32 > $OUTPUT/f128_to_ui32_rnm.tv -echo "Creating f16_to_ui64 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f16_to_ui64 > $OUTPUT/f16_to_ui64_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f16_to_ui64 > $OUTPUT/f16_to_ui64_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f16_to_ui64 > $OUTPUT/f16_to_ui64_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f16_to_ui64 > $OUTPUT/f16_to_ui64_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f16_to_ui64 > $OUTPUT/f16_to_ui64_rnm.tv -echo "Creating f32_to_ui64 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f32_to_ui64 > $OUTPUT/f32_to_ui64_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f32_to_ui64 > $OUTPUT/f32_to_ui64_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f32_to_ui64 > $OUTPUT/f32_to_ui64_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f32_to_ui64 > $OUTPUT/f32_to_ui64_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f32_to_ui64 > $OUTPUT/f32_to_ui64_rnm.tv -echo "Creating f64_to_ui64 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f64_to_ui64 > $OUTPUT/f64_to_ui64_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f64_to_ui64 > $OUTPUT/f64_to_ui64_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f64_to_ui64 > $OUTPUT/f64_to_ui64_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f64_to_ui64 > $OUTPUT/f64_to_ui64_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f64_to_ui64 > $OUTPUT/f64_to_ui64_rnm.tv -echo "Creating f128_to_ui64 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f128_to_ui64 > $OUTPUT/f128_to_ui64_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f128_to_ui64 > $OUTPUT/f128_to_ui64_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f128_to_ui64 > $OUTPUT/f128_to_ui64_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f128_to_ui64 > $OUTPUT/f128_to_ui64_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f128_to_ui64 > $OUTPUT/f128_to_ui64_rnm.tv -echo "Creating f16_to_i32 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f16_to_i32 > $OUTPUT/f16_to_i32_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f16_to_i32 > $OUTPUT/f16_to_i32_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f16_to_i32 > $OUTPUT/f16_to_i32_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f16_to_i32 > $OUTPUT/f16_to_i32_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f16_to_i32 > $OUTPUT/f16_to_i32_rnm.tv -echo "Creating f32_to_i32 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f32_to_i32 > $OUTPUT/f32_to_i32_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f32_to_i32 > $OUTPUT/f32_to_i32_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f32_to_i32 > $OUTPUT/f32_to_i32_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f32_to_i32 > $OUTPUT/f32_to_i32_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f32_to_i32 > $OUTPUT/f32_to_i32_rnm.tv -echo "Creating f64_to_i32 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f64_to_i32 > $OUTPUT/f64_to_i32_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f64_to_i32 > $OUTPUT/f64_to_i32_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f64_to_i32 > $OUTPUT/f64_to_i32_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f64_to_i32 > $OUTPUT/f64_to_i32_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f64_to_i32 > $OUTPUT/f64_to_i32_rnm.tv -echo "Creating f128_to_i32 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f128_to_i32 > $OUTPUT/f128_to_i32_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f128_to_i32 > $OUTPUT/f128_to_i32_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f128_to_i32 > $OUTPUT/f128_to_i32_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f128_to_i32 > $OUTPUT/f128_to_i32_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f128_to_i32 > $OUTPUT/f128_to_i32_rnm.tv -echo "Creating f16_to_i64 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f16_to_i64 > $OUTPUT/f16_to_i64_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f16_to_i64 > $OUTPUT/f16_to_i64_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f16_to_i64 > $OUTPUT/f16_to_i64_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f16_to_i64 > $OUTPUT/f16_to_i64_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f16_to_i64 > $OUTPUT/f16_to_i64_rnm.tv -echo "Creating f32_to_i64 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f32_to_i64 > $OUTPUT/f32_to_i64_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f32_to_i64 > $OUTPUT/f32_to_i64_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f32_to_i64 > $OUTPUT/f32_to_i64_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f32_to_i64 > $OUTPUT/f32_to_i64_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f32_to_i64 > $OUTPUT/f32_to_i64_rnm.tv -echo "Creating f64_to_i64 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f64_to_i64 > $OUTPUT/f64_to_i64_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f64_to_i64 > $OUTPUT/f64_to_i64_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f64_to_i64 > $OUTPUT/f64_to_i64_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f64_to_i64 > $OUTPUT/f64_to_i64_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f64_to_i64 > $OUTPUT/f64_to_i64_rnm.tv -echo "Creating f128_to_i64 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f128_to_i64 > $OUTPUT/f128_to_i64_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f128_to_i64 > $OUTPUT/f128_to_i64_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f128_to_i64 > $OUTPUT/f128_to_i64_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f128_to_i64 > $OUTPUT/f128_to_i64_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f128_to_i64 > $OUTPUT/f128_to_i64_rnm.tv -echo "Creating f16_to_f32 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f16_to_f32 > $OUTPUT/f16_to_f32_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f16_to_f32 > $OUTPUT/f16_to_f32_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax f16_to_f32 > $OUTPUT/f16_to_f32_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin f16_to_f32 > $OUTPUT/f16_to_f32_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f16_to_f32 > $OUTPUT/f16_to_f32_rnm.tv -echo "Creating f16_to_f64 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f16_to_f64 > $OUTPUT/f16_to_f64_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f16_to_f64 > $OUTPUT/f16_to_f64_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax f16_to_f64 > $OUTPUT/f16_to_f64_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin f16_to_f64 > $OUTPUT/f16_to_f64_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f16_to_f64 > $OUTPUT/f16_to_f64_rnm.tv -echo "Creating f16_to_f128 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f16_to_f128 > $OUTPUT/f16_to_f128_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f16_to_f128 > $OUTPUT/f16_to_f128_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax f16_to_f128 > $OUTPUT/f16_to_f128_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin f16_to_f128 > $OUTPUT/f16_to_f128_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f16_to_f128 > $OUTPUT/f16_to_f128_rnm.tv -echo "Creating f32_to_f16 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f32_to_f16 > $OUTPUT/f32_to_f16_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f32_to_f16 > $OUTPUT/f32_to_f16_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax f32_to_f16 > $OUTPUT/f32_to_f16_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin f32_to_f16 > $OUTPUT/f32_to_f16_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f32_to_f16 > $OUTPUT/f32_to_f16_rnm.tv -echo "Creating f32_to_f64 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f32_to_f64 > $OUTPUT/f32_to_f64_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f32_to_f64 > $OUTPUT/f32_to_f64_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax f32_to_f64 > $OUTPUT/f32_to_f64_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin f32_to_f64 > $OUTPUT/f32_to_f64_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f32_to_f64 > $OUTPUT/f32_to_f64_rnm.tv -echo "Creating f32_to_f128 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f32_to_f128 > $OUTPUT/f32_to_f128_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f32_to_f128 > $OUTPUT/f32_to_f128_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax f32_to_f128 > $OUTPUT/f32_to_f128_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin f32_to_f128 > $OUTPUT/f32_to_f128_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f32_to_f128 > $OUTPUT/f32_to_f128_rnm.tv -echo "Creating f64_to_f16 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f64_to_f16 > $OUTPUT/f64_to_f16_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f64_to_f16 > $OUTPUT/f64_to_f16_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax f64_to_f16 > $OUTPUT/f64_to_f16_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin f64_to_f16 > $OUTPUT/f64_to_f16_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f64_to_f16 > $OUTPUT/f64_to_f16_rnm.tv -echo "Creating f64_to_f32 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f64_to_f32 > $OUTPUT/f64_to_f32_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f64_to_f32 > $OUTPUT/f64_to_f32_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax f64_to_f32 > $OUTPUT/f64_to_f32_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin f64_to_f32 > $OUTPUT/f64_to_f32_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f64_to_f32 > $OUTPUT/f64_to_f32_rnm.tv -echo "Creating f64_to_f128 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f64_to_f128 > $OUTPUT/f64_to_f128_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f64_to_f128 > $OUTPUT/f64_to_f128_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax f64_to_f128 > $OUTPUT/f64_to_f128_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin f64_to_f128 > $OUTPUT/f64_to_f128_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f64_to_f128 > $OUTPUT/f64_to_f128_rnm.tv -echo "Creating f128_to_f16 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f128_to_f16 > $OUTPUT/f128_to_f16_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f128_to_f16 > $OUTPUT/f128_to_f16_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax f128_to_f16 > $OUTPUT/f128_to_f16_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin f128_to_f16 > $OUTPUT/f128_to_f16_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f128_to_f16 > $OUTPUT/f128_to_f16_rnm.tv -echo "Creating f128_to_f32 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f128_to_f32 > $OUTPUT/f128_to_f32_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f128_to_f32 > $OUTPUT/f128_to_f32_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax f128_to_f32 > $OUTPUT/f128_to_f32_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin f128_to_f32 > $OUTPUT/f128_to_f32_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f128_to_f32 > $OUTPUT/f128_to_f32_rnm.tv -echo "Creating f128_to_f64 convert vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f128_to_f64 > $OUTPUT/f128_to_f64_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f128_to_f64 > $OUTPUT/f128_to_f64_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax f128_to_f64 > $OUTPUT/f128_to_f64_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin f128_to_f64 > $OUTPUT/f128_to_f64_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f128_to_f64 > $OUTPUT/f128_to_f64_rnm.tv -echo "Creating f16_add vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_add > $OUTPUT/f16_add_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_add > $OUTPUT/f16_add_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_add > $OUTPUT/f16_add_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_add > $OUTPUT/f16_add_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_add > $OUTPUT/f16_add_rnm.tv -echo "Creating f32_add vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_add > $OUTPUT/f32_add_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_add > $OUTPUT/f32_add_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_add > $OUTPUT/f32_add_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_add > $OUTPUT/f32_add_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_add > $OUTPUT/f32_add_rnm.tv -echo "Creating f64_add vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_add > $OUTPUT/f64_add_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_add > $OUTPUT/f64_add_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_add > $OUTPUT/f64_add_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_add > $OUTPUT/f64_add_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_add > $OUTPUT/f64_add_rnm.tv -echo "Creating f128_add vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_add > $OUTPUT/f128_add_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_add > $OUTPUT/f128_add_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_add > $OUTPUT/f128_add_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_add > $OUTPUT/f128_add_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_add > $OUTPUT/f128_add_rnm.tv -echo "Creating f16_sub vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_sub > $OUTPUT/f16_sub_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_sub > $OUTPUT/f16_sub_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_sub > $OUTPUT/f16_sub_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_sub > $OUTPUT/f16_sub_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_sub > $OUTPUT/f16_sub_rnm.tv -echo "Creating f32_sub vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_sub > $OUTPUT/f32_sub_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_sub > $OUTPUT/f32_sub_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_sub > $OUTPUT/f32_sub_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_sub > $OUTPUT/f32_sub_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_sub > $OUTPUT/f32_sub_rnm.tv -echo "Creating f64_sub vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_sub > $OUTPUT/f64_sub_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_sub > $OUTPUT/f64_sub_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_sub > $OUTPUT/f64_sub_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_sub > $OUTPUT/f64_sub_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_sub > $OUTPUT/f64_sub_rnm.tv -echo "Creating f128_sub vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_sub > $OUTPUT/f128_sub_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_sub > $OUTPUT/f128_sub_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_sub > $OUTPUT/f128_sub_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_sub > $OUTPUT/f128_sub_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_sub > $OUTPUT/f128_sub_rnm.tv -echo "Creating f16_mul vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_mul > $OUTPUT/f16_mul_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_mul > $OUTPUT/f16_mul_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_mul > $OUTPUT/f16_mul_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_mul > $OUTPUT/f16_mul_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_mul > $OUTPUT/f16_mul_rnm.tv -echo "Creating f32_mul vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_mul > $OUTPUT/f32_mul_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_mul > $OUTPUT/f32_mul_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_mul > $OUTPUT/f32_mul_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_mul > $OUTPUT/f32_mul_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_mul > $OUTPUT/f32_mul_rnm.tv -echo "Creating f64_mul vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_mul > $OUTPUT/f64_mul_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_mul > $OUTPUT/f64_mul_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_mul > $OUTPUT/f64_mul_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_mul > $OUTPUT/f64_mul_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_mul > $OUTPUT/f64_mul_rnm.tv -echo "Creating f128_mul vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_mul > $OUTPUT/f128_mul_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_mul > $OUTPUT/f128_mul_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_mul > $OUTPUT/f128_mul_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_mul > $OUTPUT/f128_mul_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_mul > $OUTPUT/f128_mul_rnm.tv -echo "Creating f16_div vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_div > $OUTPUT/f16_div_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_div > $OUTPUT/f16_div_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_div > $OUTPUT/f16_div_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_div > $OUTPUT/f16_div_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_div > $OUTPUT/f16_div_rnm.tv -echo "Creating f32_div vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_div > $OUTPUT/f32_div_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_div > $OUTPUT/f32_div_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_div > $OUTPUT/f32_div_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_div > $OUTPUT/f32_div_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_div > $OUTPUT/f32_div_rnm.tv -echo "Creating f64_div vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_div > $OUTPUT/f64_div_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_div > $OUTPUT/f64_div_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_div > $OUTPUT/f64_div_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_div > $OUTPUT/f64_div_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_div > $OUTPUT/f64_div_rnm.tv -echo "Creating f128_div vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_div > $OUTPUT/f128_div_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_div > $OUTPUT/f128_div_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_div > $OUTPUT/f128_div_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_div > $OUTPUT/f128_div_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_div > $OUTPUT/f128_div_rnm.tv -echo "Creating f16_sqrt vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f16_sqrt > $OUTPUT/f16_sqrt_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f16_sqrt > $OUTPUT/f16_sqrt_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax f16_sqrt > $OUTPUT/f16_sqrt_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin f16_sqrt > $OUTPUT/f16_sqrt_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f16_sqrt > $OUTPUT/f16_sqrt_rnm.tv -echo "Creating f32_sqrt vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f32_sqrt > $OUTPUT/f32_sqrt_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f32_sqrt > $OUTPUT/f32_sqrt_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax f32_sqrt > $OUTPUT/f32_sqrt_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin f32_sqrt > $OUTPUT/f32_sqrt_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f32_sqrt > $OUTPUT/f32_sqrt_rnm.tv -echo "Creating f64_sqrt vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f64_sqrt > $OUTPUT/f64_sqrt_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f64_sqrt > $OUTPUT/f64_sqrt_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax f64_sqrt > $OUTPUT/f64_sqrt_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin f64_sqrt > $OUTPUT/f64_sqrt_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f64_sqrt > $OUTPUT/f64_sqrt_rnm.tv -echo "Creating f128_sqrt vectors" -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f128_sqrt > $OUTPUT/f128_sqrt_rne.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f128_sqrt > $OUTPUT/f128_sqrt_rz.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmax f128_sqrt > $OUTPUT/f128_sqrt_ru.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rmin f128_sqrt > $OUTPUT/f128_sqrt_rd.tv -$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f128_sqrt > $OUTPUT/f128_sqrt_rnm.tv -echo "Creating f16_eq vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_eq > $OUTPUT/f16_eq_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_eq > $OUTPUT/f16_eq_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_eq > $OUTPUT/f16_eq_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_eq > $OUTPUT/f16_eq_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_eq > $OUTPUT/f16_eq_rnm.tv -echo "Creating f32_eq vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_eq > $OUTPUT/f32_eq_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_eq > $OUTPUT/f32_eq_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_eq > $OUTPUT/f32_eq_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_eq > $OUTPUT/f32_eq_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_eq > $OUTPUT/f32_eq_rnm.tv -echo "Creating f64_eq vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_eq > $OUTPUT/f64_eq_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_eq > $OUTPUT/f64_eq_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_eq > $OUTPUT/f64_eq_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_eq > $OUTPUT/f64_eq_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_eq > $OUTPUT/f64_eq_rnm.tv -echo "Creating f128_eq vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_eq > $OUTPUT/f128_eq_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_eq > $OUTPUT/f128_eq_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_eq > $OUTPUT/f128_eq_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_eq > $OUTPUT/f128_eq_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_eq > $OUTPUT/f128_eq_rnm.tv -echo "Creating f16_le vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_le > $OUTPUT/f16_le_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_le > $OUTPUT/f16_le_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_le > $OUTPUT/f16_le_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_le > $OUTPUT/f16_le_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_le > $OUTPUT/f16_le_rnm.tv -echo "Creating f32_le vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_le > $OUTPUT/f32_le_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_le > $OUTPUT/f32_le_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_le > $OUTPUT/f32_le_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_le > $OUTPUT/f32_le_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_le > $OUTPUT/f32_le_rnm.tv -echo "Creating f64_le vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_le > $OUTPUT/f64_le_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_le > $OUTPUT/f64_le_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_le > $OUTPUT/f64_le_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_le > $OUTPUT/f64_le_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_le > $OUTPUT/f64_le_rnm.tv -echo "Creating f128_le vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_le > $OUTPUT/f128_le_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_le > $OUTPUT/f128_le_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_le > $OUTPUT/f128_le_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_le > $OUTPUT/f128_le_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_le > $OUTPUT/f128_le_rnm.tv -echo "Creating f16_lt vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_lt > $OUTPUT/f16_lt_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_lt > $OUTPUT/f16_lt_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_lt > $OUTPUT/f16_lt_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_lt > $OUTPUT/f16_lt_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_lt > $OUTPUT/f16_lt_rnm.tv -echo "Creating f32_lt vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_lt > $OUTPUT/f32_lt_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_lt > $OUTPUT/f32_lt_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_lt > $OUTPUT/f32_lt_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_lt > $OUTPUT/f32_lt_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_lt > $OUTPUT/f32_lt_rnm.tv -echo "Creating f64_lt vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_lt > $OUTPUT/f64_lt_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_lt > $OUTPUT/f64_lt_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_lt > $OUTPUT/f64_lt_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_lt > $OUTPUT/f64_lt_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_lt > $OUTPUT/f64_lt_rnm.tv -echo "Creating f128_lt vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_lt > $OUTPUT/f128_lt_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_lt > $OUTPUT/f128_lt_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_lt > $OUTPUT/f128_lt_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_lt > $OUTPUT/f128_lt_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_lt > $OUTPUT/f128_lt_rnm.tv -echo "Creating f16_mulAdd vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_mulAdd > $OUTPUT/f16_mulAdd_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_mulAdd > $OUTPUT/f16_mulAdd_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_mulAdd > $OUTPUT/f16_mulAdd_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_mulAdd > $OUTPUT/f16_mulAdd_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_mulAdd > $OUTPUT/f16_mulAdd_rnm.tv -echo "Creating f32_mulAdd vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_mulAdd > $OUTPUT/f32_mulAdd_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_mulAdd > $OUTPUT/f32_mulAdd_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_mulAdd > $OUTPUT/f32_mulAdd_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_mulAdd > $OUTPUT/f32_mulAdd_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_mulAdd > $OUTPUT/f32_mulAdd_rnm.tv -echo "Creating f64_mulAdd vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_mulAdd > $OUTPUT/f64_mulAdd_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_mulAdd > $OUTPUT/f64_mulAdd_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_mulAdd > $OUTPUT/f64_mulAdd_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_mulAdd > $OUTPUT/f64_mulAdd_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_mulAdd > $OUTPUT/f64_mulAdd_rnm.tv -echo "Creating f128_mulAdd vectors" -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_mulAdd > $OUTPUT/f128_mulAdd_rne.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_mulAdd > $OUTPUT/f128_mulAdd_rz.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_mulAdd > $OUTPUT/f128_mulAdd_ru.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_mulAdd > $OUTPUT/f128_mulAdd_rd.tv -$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_mulAdd > $OUTPUT/f128_mulAdd_rnm.tv diff --git a/tests/fp/remove_spaces.sh b/tests/fp/remove_spaces.sh deleted file mode 100755 index ed6106fd6..000000000 --- a/tests/fp/remove_spaces.sh +++ /dev/null @@ -1,483 +0,0 @@ -#!/bin/sh -BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC" -OUTPUT="./vectors" -echo "Editing ui32_to_f16 test vectors" -sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_rne.tv -sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_rz.tv -sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_ru.tv -sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_rd.tv -sed -i 's/ /_/g' $OUTPUT/ui32_to_f16_rnm.tv -echo "Editing ui32_to_f32 test vectors" -sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_rne.tv -sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_rz.tv -sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_ru.tv -sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_rd.tv -sed -i 's/ /_/g' $OUTPUT/ui32_to_f32_rnm.tv -echo "Editing ui32_to_f64 test vectors" -sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_rne.tv -sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_rz.tv -sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_ru.tv -sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_rd.tv -sed -i 's/ /_/g' $OUTPUT/ui32_to_f64_rnm.tv -echo "Editing ui32_to_f128 test vectors" -sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_rne.tv -sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_rz.tv -sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_ru.tv -sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_rd.tv -sed -i 's/ /_/g' $OUTPUT/ui32_to_f128_rnm.tv -echo "Editing ui64_to_f16 test vectors" -sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_rne.tv -sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_rz.tv -sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_ru.tv -sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_rd.tv -sed -i 's/ /_/g' $OUTPUT/ui64_to_f16_rnm.tv -echo "Editing ui64_to_f32 test vectors" -sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_rne.tv -sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_rz.tv -sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_ru.tv -sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_rd.tv -sed -i 's/ /_/g' $OUTPUT/ui64_to_f32_rnm.tv -echo "Editing ui64_to_f64 test vectors" -sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_rne.tv -sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_rz.tv -sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_ru.tv -sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_rd.tv -sed -i 's/ /_/g' $OUTPUT/ui64_to_f64_rnm.tv -echo "Editing ui64_to_f128 test vectors" -sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_rne.tv -sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_rz.tv -sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_ru.tv -sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_rd.tv -sed -i 's/ /_/g' $OUTPUT/ui64_to_f128_rnm.tv -echo "Editing i32_to_f16 test vectors" -sed -i 's/ /_/g' $OUTPUT/i32_to_f16_rne.tv -sed -i 's/ /_/g' $OUTPUT/i32_to_f16_rz.tv -sed -i 's/ /_/g' $OUTPUT/i32_to_f16_ru.tv -sed -i 's/ /_/g' $OUTPUT/i32_to_f16_rd.tv -sed -i 's/ /_/g' $OUTPUT/i32_to_f16_rnm.tv -echo "Editing i32_to_f32 test vectors" -sed -i 's/ /_/g' $OUTPUT/i32_to_f32_rne.tv -sed -i 's/ /_/g' $OUTPUT/i32_to_f32_rz.tv -sed -i 's/ /_/g' $OUTPUT/i32_to_f32_ru.tv -sed -i 's/ /_/g' $OUTPUT/i32_to_f32_rd.tv -sed -i 's/ /_/g' $OUTPUT/i32_to_f32_rnm.tv -echo "Editing i32_to_f64 test vectors" -sed -i 's/ /_/g' $OUTPUT/i32_to_f64_rne.tv -sed -i 's/ /_/g' $OUTPUT/i32_to_f64_rz.tv -sed -i 's/ /_/g' $OUTPUT/i32_to_f64_ru.tv -sed -i 's/ /_/g' $OUTPUT/i32_to_f64_rd.tv -sed -i 's/ /_/g' $OUTPUT/i32_to_f64_rnm.tv -echo "Editing i32_to_f128 test vectors" -sed -i 's/ /_/g' $OUTPUT/i32_to_f128_rne.tv -sed -i 's/ /_/g' $OUTPUT/i32_to_f128_rz.tv -sed -i 's/ /_/g' $OUTPUT/i32_to_f128_ru.tv -sed -i 's/ /_/g' $OUTPUT/i32_to_f128_rd.tv -sed -i 's/ /_/g' $OUTPUT/i32_to_f128_rnm.tv -echo "Editing i64_to_f16 test vectors" -sed -i 's/ /_/g' $OUTPUT/i64_to_f16_rne.tv -sed -i 's/ /_/g' $OUTPUT/i64_to_f16_rz.tv -sed -i 's/ /_/g' $OUTPUT/i64_to_f16_ru.tv -sed -i 's/ /_/g' $OUTPUT/i64_to_f16_rd.tv -sed -i 's/ /_/g' $OUTPUT/i64_to_f16_rnm.tv -echo "Editing i64_to_f32 test vectors" -sed -i 's/ /_/g' $OUTPUT/i64_to_f32_rne.tv -sed -i 's/ /_/g' $OUTPUT/i64_to_f32_rz.tv -sed -i 's/ /_/g' $OUTPUT/i64_to_f32_ru.tv -sed -i 's/ /_/g' $OUTPUT/i64_to_f32_rd.tv -sed -i 's/ /_/g' $OUTPUT/i64_to_f32_rnm.tv -echo "Editing i64_to_f64 test vectors" -sed -i 's/ /_/g' $OUTPUT/i64_to_f64_rne.tv -sed -i 's/ /_/g' $OUTPUT/i64_to_f64_rz.tv -sed -i 's/ /_/g' $OUTPUT/i64_to_f64_ru.tv -sed -i 's/ /_/g' $OUTPUT/i64_to_f64_rd.tv -sed -i 's/ /_/g' $OUTPUT/i64_to_f64_rnm.tv -echo "Editing i64_to_f128 test vectors" -sed -i 's/ /_/g' $OUTPUT/i64_to_f128_rne.tv -sed -i 's/ /_/g' $OUTPUT/i64_to_f128_rz.tv -sed -i 's/ /_/g' $OUTPUT/i64_to_f128_ru.tv -sed -i 's/ /_/g' $OUTPUT/i64_to_f128_rd.tv -sed -i 's/ /_/g' $OUTPUT/i64_to_f128_rnm.tv -echo "Editing f16_to_ui32 test vectors" -sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_rne.tv -sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_rz.tv -sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_ru.tv -sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_rd.tv -sed -i 's/ /_/g' $OUTPUT/f16_to_ui32_rnm.tv -echo "Editing f32_to_ui32 test vectors" -sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_rne.tv -sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_rz.tv -sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_ru.tv -sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_rd.tv -sed -i 's/ /_/g' $OUTPUT/f32_to_ui32_rnm.tv -echo "Editing f64_to_ui32 test vectors" -sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_rne.tv -sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_rz.tv -sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_ru.tv -sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_rd.tv -sed -i 's/ /_/g' $OUTPUT/f64_to_ui32_rnm.tv -echo "Editing f128_to_ui32 test vectors" -sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_rne.tv -sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_rz.tv -sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_ru.tv -sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_rd.tv -sed -i 's/ /_/g' $OUTPUT/f128_to_ui32_rnm.tv -echo "Editing f16_to_ui64 test vectors" -sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_rne.tv -sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_rz.tv -sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_ru.tv -sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_rd.tv -sed -i 's/ /_/g' $OUTPUT/f16_to_ui64_rnm.tv -echo "Editing f32_to_ui64 test vectors" -sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_rne.tv -sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_rz.tv -sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_ru.tv -sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_rd.tv -sed -i 's/ /_/g' $OUTPUT/f32_to_ui64_rnm.tv -echo "Editing f64_to_ui64 test vectors" -sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_rne.tv -sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_rz.tv -sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_ru.tv -sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_rd.tv -sed -i 's/ /_/g' $OUTPUT/f64_to_ui64_rnm.tv -echo "Editing f128_to_ui64 test vectors" -sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_rne.tv -sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_rz.tv -sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_ru.tv -sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_rd.tv -sed -i 's/ /_/g' $OUTPUT/f128_to_ui64_rnm.tv -echo "Editing f16_to_i32 test vectors" -sed -i 's/ /_/g' $OUTPUT/f16_to_i32_rne.tv -sed -i 's/ /_/g' $OUTPUT/f16_to_i32_rz.tv -sed -i 's/ /_/g' $OUTPUT/f16_to_i32_ru.tv -sed -i 's/ /_/g' $OUTPUT/f16_to_i32_rd.tv -sed -i 's/ /_/g' $OUTPUT/f16_to_i32_rnm.tv -echo "Editing f32_to_i32 test vectors" -sed -i 's/ /_/g' $OUTPUT/f32_to_i32_rne.tv -sed -i 's/ /_/g' $OUTPUT/f32_to_i32_rz.tv -sed -i 's/ /_/g' $OUTPUT/f32_to_i32_ru.tv -sed -i 's/ /_/g' $OUTPUT/f32_to_i32_rd.tv -sed -i 's/ /_/g' $OUTPUT/f32_to_i32_rnm.tv -echo "Editing f64_to_i32 test vectors" -sed -i 's/ /_/g' $OUTPUT/f64_to_i32_rne.tv -sed -i 's/ /_/g' $OUTPUT/f64_to_i32_rz.tv -sed -i 's/ /_/g' $OUTPUT/f64_to_i32_ru.tv -sed -i 's/ /_/g' $OUTPUT/f64_to_i32_rd.tv -sed -i 's/ /_/g' $OUTPUT/f64_to_i32_rnm.tv -echo "Editing f128_to_i32 test vectors" -sed -i 's/ /_/g' $OUTPUT/f128_to_i32_rne.tv -sed -i 's/ /_/g' $OUTPUT/f128_to_i32_rz.tv -sed -i 's/ /_/g' $OUTPUT/f128_to_i32_ru.tv -sed -i 's/ /_/g' $OUTPUT/f128_to_i32_rd.tv -sed -i 's/ /_/g' $OUTPUT/f128_to_i32_rnm.tv -echo "Editing f16_to_i64 test vectors" -sed -i 's/ /_/g' $OUTPUT/f16_to_i64_rne.tv -sed -i 's/ /_/g' $OUTPUT/f16_to_i64_rz.tv -sed -i 's/ /_/g' $OUTPUT/f16_to_i64_ru.tv -sed -i 's/ /_/g' $OUTPUT/f16_to_i64_rd.tv -sed -i 's/ /_/g' $OUTPUT/f16_to_i64_rnm.tv -echo "Editing f32_to_i64 test vectors" -sed -i 's/ /_/g' $OUTPUT/f32_to_i64_rne.tv -sed -i 's/ /_/g' $OUTPUT/f32_to_i64_rz.tv -sed -i 's/ /_/g' $OUTPUT/f32_to_i64_ru.tv -sed -i 's/ /_/g' $OUTPUT/f32_to_i64_rd.tv -sed -i 's/ /_/g' $OUTPUT/f32_to_i64_rnm.tv -echo "Editing f64_to_i64 test vectors" -sed -i 's/ /_/g' $OUTPUT/f64_to_i64_rne.tv -sed -i 's/ /_/g' $OUTPUT/f64_to_i64_rz.tv -sed -i 's/ /_/g' $OUTPUT/f64_to_i64_ru.tv -sed -i 's/ /_/g' $OUTPUT/f64_to_i64_rd.tv -sed -i 's/ /_/g' $OUTPUT/f64_to_i64_rnm.tv -echo "Editing f128_to_i64 test vectors" -sed -i 's/ /_/g' $OUTPUT/f128_to_i64_rne.tv -sed -i 's/ /_/g' $OUTPUT/f128_to_i64_rz.tv -sed -i 's/ /_/g' $OUTPUT/f128_to_i64_ru.tv -sed -i 's/ /_/g' $OUTPUT/f128_to_i64_rd.tv -sed -i 's/ /_/g' $OUTPUT/f128_to_i64_rnm.tv -echo "Editing f16_to_f32 test vectors" -sed -i 's/ /_/g' $OUTPUT/f16_to_f32_rne.tv -sed -i 's/ /_/g' $OUTPUT/f16_to_f32_rz.tv -sed -i 's/ /_/g' $OUTPUT/f16_to_f32_ru.tv -sed -i 's/ /_/g' $OUTPUT/f16_to_f32_rd.tv -sed -i 's/ /_/g' $OUTPUT/f16_to_f32_rnm.tv -echo "Editing f16_to_f64 test vectors" -sed -i 's/ /_/g' $OUTPUT/f16_to_f64_rne.tv -sed -i 's/ /_/g' $OUTPUT/f16_to_f64_rz.tv -sed -i 's/ /_/g' $OUTPUT/f16_to_f64_ru.tv -sed -i 's/ /_/g' $OUTPUT/f16_to_f64_rd.tv -sed -i 's/ /_/g' $OUTPUT/f16_to_f64_rnm.tv -echo "Editing f16_to_f128 test vectors" -sed -i 's/ /_/g' $OUTPUT/f16_to_f128_rne.tv -sed -i 's/ /_/g' $OUTPUT/f16_to_f128_rz.tv -sed -i 's/ /_/g' $OUTPUT/f16_to_f128_ru.tv -sed -i 's/ /_/g' $OUTPUT/f16_to_f128_rd.tv -sed -i 's/ /_/g' $OUTPUT/f16_to_f128_rnm.tv -echo "Editing f32_to_f16 test vectors" -sed -i 's/ /_/g' $OUTPUT/f32_to_f16_rne.tv -sed -i 's/ /_/g' $OUTPUT/f32_to_f16_rz.tv -sed -i 's/ /_/g' $OUTPUT/f32_to_f16_ru.tv -sed -i 's/ /_/g' $OUTPUT/f32_to_f16_rd.tv -sed -i 's/ /_/g' $OUTPUT/f32_to_f16_rnm.tv -echo "Editing f32_to_f64 test vectors" -sed -i 's/ /_/g' $OUTPUT/f32_to_f64_rne.tv -sed -i 's/ /_/g' $OUTPUT/f32_to_f64_rz.tv -sed -i 's/ /_/g' $OUTPUT/f32_to_f64_ru.tv -sed -i 's/ /_/g' $OUTPUT/f32_to_f64_rd.tv -sed -i 's/ /_/g' $OUTPUT/f32_to_f64_rnm.tv -echo "Editing f32_to_f128 test vectors" -sed -i 's/ /_/g' $OUTPUT/f32_to_f128_rne.tv -sed -i 's/ /_/g' $OUTPUT/f32_to_f128_rz.tv -sed -i 's/ /_/g' $OUTPUT/f32_to_f128_ru.tv -sed -i 's/ /_/g' $OUTPUT/f32_to_f128_rd.tv -sed -i 's/ /_/g' $OUTPUT/f32_to_f128_rnm.tv -echo "Editing f64_to_f16 test vectors" -sed -i 's/ /_/g' $OUTPUT/f64_to_f16_rne.tv -sed -i 's/ /_/g' $OUTPUT/f64_to_f16_rz.tv -sed -i 's/ /_/g' $OUTPUT/f64_to_f16_ru.tv -sed -i 's/ /_/g' $OUTPUT/f64_to_f16_rd.tv -sed -i 's/ /_/g' $OUTPUT/f64_to_f16_rnm.tv -echo "Editing f64_to_f32 test vectors" -sed -i 's/ /_/g' $OUTPUT/f64_to_f32_rne.tv -sed -i 's/ /_/g' $OUTPUT/f64_to_f32_rz.tv -sed -i 's/ /_/g' $OUTPUT/f64_to_f32_ru.tv -sed -i 's/ /_/g' $OUTPUT/f64_to_f32_rd.tv -sed -i 's/ /_/g' $OUTPUT/f64_to_f32_rnm.tv -echo "Editing f64_to_f128 test vectors" -sed -i 's/ /_/g' $OUTPUT/f64_to_f128_rne.tv -sed -i 's/ /_/g' $OUTPUT/f64_to_f128_rz.tv -sed -i 's/ /_/g' $OUTPUT/f64_to_f128_ru.tv -sed -i 's/ /_/g' $OUTPUT/f64_to_f128_rd.tv -sed -i 's/ /_/g' $OUTPUT/f64_to_f128_rnm.tv -echo "Editing f128_to_f16 test vectors" -sed -i 's/ /_/g' $OUTPUT/f128_to_f16_rne.tv -sed -i 's/ /_/g' $OUTPUT/f128_to_f16_rz.tv -sed -i 's/ /_/g' $OUTPUT/f128_to_f16_ru.tv -sed -i 's/ /_/g' $OUTPUT/f128_to_f16_rd.tv -sed -i 's/ /_/g' $OUTPUT/f128_to_f16_rnm.tv -echo "Editing f128_to_f32 test vectors" -sed -i 's/ /_/g' $OUTPUT/f128_to_f32_rne.tv -sed -i 's/ /_/g' $OUTPUT/f128_to_f32_rz.tv -sed -i 's/ /_/g' $OUTPUT/f128_to_f32_ru.tv -sed -i 's/ /_/g' $OUTPUT/f128_to_f32_rd.tv -sed -i 's/ /_/g' $OUTPUT/f128_to_f32_rnm.tv -echo "Editing f128_to_f64 test vectors" -sed -i 's/ /_/g' $OUTPUT/f128_to_f64_rne.tv -sed -i 's/ /_/g' $OUTPUT/f128_to_f64_rz.tv -sed -i 's/ /_/g' $OUTPUT/f128_to_f64_ru.tv -sed -i 's/ /_/g' $OUTPUT/f128_to_f64_rd.tv -sed -i 's/ /_/g' $OUTPUT/f128_to_f64_rnm.tv -echo "Editing f16_add test vectors" -sed -i 's/ /_/g' $OUTPUT/f16_add_rne.tv -sed -i 's/ /_/g' $OUTPUT/f16_add_rz.tv -sed -i 's/ /_/g' $OUTPUT/f16_add_ru.tv -sed -i 's/ /_/g' $OUTPUT/f16_add_rd.tv -sed -i 's/ /_/g' $OUTPUT/f16_add_rnm.tv -echo "Editing f32_add test vectors" -sed -i 's/ /_/g' $OUTPUT/f32_add_rne.tv -sed -i 's/ /_/g' $OUTPUT/f32_add_rz.tv -sed -i 's/ /_/g' $OUTPUT/f32_add_ru.tv -sed -i 's/ /_/g' $OUTPUT/f32_add_rd.tv -sed -i 's/ /_/g' $OUTPUT/f32_add_rnm.tv -echo "Editing f64_add test vectors" -sed -i 's/ /_/g' $OUTPUT/f64_add_rne.tv -sed -i 's/ /_/g' $OUTPUT/f64_add_rz.tv -sed -i 's/ /_/g' $OUTPUT/f64_add_ru.tv -sed -i 's/ /_/g' $OUTPUT/f64_add_rd.tv -sed -i 's/ /_/g' $OUTPUT/f64_add_rnm.tv -echo "Editing f128_add test vectors" -sed -i 's/ /_/g' $OUTPUT/f128_add_rne.tv -sed -i 's/ /_/g' $OUTPUT/f128_add_rz.tv -sed -i 's/ /_/g' $OUTPUT/f128_add_ru.tv -sed -i 's/ /_/g' $OUTPUT/f128_add_rd.tv -sed -i 's/ /_/g' $OUTPUT/f128_add_rnm.tv -echo "Editing f16_sub test vectors" -sed -i 's/ /_/g' $OUTPUT/f16_sub_rne.tv -sed -i 's/ /_/g' $OUTPUT/f16_sub_rz.tv -sed -i 's/ /_/g' $OUTPUT/f16_sub_ru.tv -sed -i 's/ /_/g' $OUTPUT/f16_sub_rd.tv -sed -i 's/ /_/g' $OUTPUT/f16_sub_rnm.tv -echo "Editing f32_sub test vectors" -sed -i 's/ /_/g' $OUTPUT/f32_sub_rne.tv -sed -i 's/ /_/g' $OUTPUT/f32_sub_rz.tv -sed -i 's/ /_/g' $OUTPUT/f32_sub_ru.tv -sed -i 's/ /_/g' $OUTPUT/f32_sub_rd.tv -sed -i 's/ /_/g' $OUTPUT/f32_sub_rnm.tv -echo "Editing f64_sub test vectors" -sed -i 's/ /_/g' $OUTPUT/f64_sub_rne.tv -sed -i 's/ /_/g' $OUTPUT/f64_sub_rz.tv -sed -i 's/ /_/g' $OUTPUT/f64_sub_ru.tv -sed -i 's/ /_/g' $OUTPUT/f64_sub_rd.tv -sed -i 's/ /_/g' $OUTPUT/f64_sub_rnm.tv -echo "Editing f128_sub test vectors" -sed -i 's/ /_/g' $OUTPUT/f128_sub_rne.tv -sed -i 's/ /_/g' $OUTPUT/f128_sub_rz.tv -sed -i 's/ /_/g' $OUTPUT/f128_sub_ru.tv -sed -i 's/ /_/g' $OUTPUT/f128_sub_rd.tv -sed -i 's/ /_/g' $OUTPUT/f128_sub_rnm.tv -echo "Editing f16_mul test vectors" -sed -i 's/ /_/g' $OUTPUT/f16_mul_rne.tv -sed -i 's/ /_/g' $OUTPUT/f16_mul_rz.tv -sed -i 's/ /_/g' $OUTPUT/f16_mul_ru.tv -sed -i 's/ /_/g' $OUTPUT/f16_mul_rd.tv -sed -i 's/ /_/g' $OUTPUT/f16_mul_rnm.tv -echo "Editing f32_mul test vectors" -sed -i 's/ /_/g' $OUTPUT/f32_mul_rne.tv -sed -i 's/ /_/g' $OUTPUT/f32_mul_rz.tv -sed -i 's/ /_/g' $OUTPUT/f32_mul_ru.tv -sed -i 's/ /_/g' $OUTPUT/f32_mul_rd.tv -sed -i 's/ /_/g' $OUTPUT/f32_mul_rnm.tv -echo "Editing f64_mul test vectors" -sed -i 's/ /_/g' $OUTPUT/f64_mul_rne.tv -sed -i 's/ /_/g' $OUTPUT/f64_mul_rz.tv -sed -i 's/ /_/g' $OUTPUT/f64_mul_ru.tv -sed -i 's/ /_/g' $OUTPUT/f64_mul_rd.tv -sed -i 's/ /_/g' $OUTPUT/f64_mul_rnm.tv -echo "Editing f128_mul test vectors" -sed -i 's/ /_/g' $OUTPUT/f128_mul_rne.tv -sed -i 's/ /_/g' $OUTPUT/f128_mul_rz.tv -sed -i 's/ /_/g' $OUTPUT/f128_mul_ru.tv -sed -i 's/ /_/g' $OUTPUT/f128_mul_rd.tv -sed -i 's/ /_/g' $OUTPUT/f128_mul_rnm.tv -echo "Editing f16_div test vectors" -sed -i 's/ /_/g' $OUTPUT/f16_div_rne.tv -sed -i 's/ /_/g' $OUTPUT/f16_div_rz.tv -sed -i 's/ /_/g' $OUTPUT/f16_div_ru.tv -sed -i 's/ /_/g' $OUTPUT/f16_div_rd.tv -sed -i 's/ /_/g' $OUTPUT/f16_div_rnm.tv -echo "Editing f32_div test vectors" -sed -i 's/ /_/g' $OUTPUT/f32_div_rne.tv -sed -i 's/ /_/g' $OUTPUT/f32_div_rz.tv -sed -i 's/ /_/g' $OUTPUT/f32_div_ru.tv -sed -i 's/ /_/g' $OUTPUT/f32_div_rd.tv -sed -i 's/ /_/g' $OUTPUT/f32_div_rnm.tv -echo "Editing f64_div test vectors" -sed -i 's/ /_/g' $OUTPUT/f64_div_rne.tv -sed -i 's/ /_/g' $OUTPUT/f64_div_rz.tv -sed -i 's/ /_/g' $OUTPUT/f64_div_ru.tv -sed -i 's/ /_/g' $OUTPUT/f64_div_rd.tv -sed -i 's/ /_/g' $OUTPUT/f64_div_rnm.tv -echo "Editing f128_div test vectors" -sed -i 's/ /_/g' $OUTPUT/f128_div_rne.tv -sed -i 's/ /_/g' $OUTPUT/f128_div_rz.tv -sed -i 's/ /_/g' $OUTPUT/f128_div_ru.tv -sed -i 's/ /_/g' $OUTPUT/f128_div_rd.tv -sed -i 's/ /_/g' $OUTPUT/f128_div_rnm.tv -echo "Editing f16_sqrt test vectors" -sed -i 's/ /_/g' $OUTPUT/f16_sqrt_rne.tv -sed -i 's/ /_/g' $OUTPUT/f16_sqrt_rz.tv -sed -i 's/ /_/g' $OUTPUT/f16_sqrt_ru.tv -sed -i 's/ /_/g' $OUTPUT/f16_sqrt_rd.tv -sed -i 's/ /_/g' $OUTPUT/f16_sqrt_rnm.tv -echo "Editing f32_sqrt test vectors" -sed -i 's/ /_/g' $OUTPUT/f32_sqrt_rne.tv -sed -i 's/ /_/g' $OUTPUT/f32_sqrt_rz.tv -sed -i 's/ /_/g' $OUTPUT/f32_sqrt_ru.tv -sed -i 's/ /_/g' $OUTPUT/f32_sqrt_rd.tv -sed -i 's/ /_/g' $OUTPUT/f32_sqrt_rnm.tv -echo "Editing f64_sqrt test vectors" -sed -i 's/ /_/g' $OUTPUT/f64_sqrt_rne.tv -sed -i 's/ /_/g' $OUTPUT/f64_sqrt_rz.tv -sed -i 's/ /_/g' $OUTPUT/f64_sqrt_ru.tv -sed -i 's/ /_/g' $OUTPUT/f64_sqrt_rd.tv -sed -i 's/ /_/g' $OUTPUT/f64_sqrt_rnm.tv -echo "Editing f128_sqrt test vectors" -sed -i 's/ /_/g' $OUTPUT/f128_sqrt_rne.tv -sed -i 's/ /_/g' $OUTPUT/f128_sqrt_rz.tv -sed -i 's/ /_/g' $OUTPUT/f128_sqrt_ru.tv -sed -i 's/ /_/g' $OUTPUT/f128_sqrt_rd.tv -sed -i 's/ /_/g' $OUTPUT/f128_sqrt_rnm.tv -echo "Editing f16_eq test vectors" -sed -i 's/ /_/g' $OUTPUT/f16_eq_rne.tv -sed -i 's/ /_/g' $OUTPUT/f16_eq_rz.tv -sed -i 's/ /_/g' $OUTPUT/f16_eq_ru.tv -sed -i 's/ /_/g' $OUTPUT/f16_eq_rd.tv -sed -i 's/ /_/g' $OUTPUT/f16_eq_rnm.tv -echo "Editing f32_eq test vectors" -sed -i 's/ /_/g' $OUTPUT/f32_eq_rne.tv -sed -i 's/ /_/g' $OUTPUT/f32_eq_rz.tv -sed -i 's/ /_/g' $OUTPUT/f32_eq_ru.tv -sed -i 's/ /_/g' $OUTPUT/f32_eq_rd.tv -sed -i 's/ /_/g' $OUTPUT/f32_eq_rnm.tv -echo "Editing f64_eq test vectors" -sed -i 's/ /_/g' $OUTPUT/f64_eq_rne.tv -sed -i 's/ /_/g' $OUTPUT/f64_eq_rz.tv -sed -i 's/ /_/g' $OUTPUT/f64_eq_ru.tv -sed -i 's/ /_/g' $OUTPUT/f64_eq_rd.tv -sed -i 's/ /_/g' $OUTPUT/f64_eq_rnm.tv -echo "Editing f128_eq test vectors" -sed -i 's/ /_/g' $OUTPUT/f128_eq_rne.tv -sed -i 's/ /_/g' $OUTPUT/f128_eq_rz.tv -sed -i 's/ /_/g' $OUTPUT/f128_eq_ru.tv -sed -i 's/ /_/g' $OUTPUT/f128_eq_rd.tv -sed -i 's/ /_/g' $OUTPUT/f128_eq_rnm.tv -echo "Editing f16_le test vectors" -sed -i 's/ /_/g' $OUTPUT/f16_le_rne.tv -sed -i 's/ /_/g' $OUTPUT/f16_le_rz.tv -sed -i 's/ /_/g' $OUTPUT/f16_le_ru.tv -sed -i 's/ /_/g' $OUTPUT/f16_le_rd.tv -sed -i 's/ /_/g' $OUTPUT/f16_le_rnm.tv -echo "Editing f32_le test vectors" -sed -i 's/ /_/g' $OUTPUT/f32_le_rne.tv -sed -i 's/ /_/g' $OUTPUT/f32_le_rz.tv -sed -i 's/ /_/g' $OUTPUT/f32_le_ru.tv -sed -i 's/ /_/g' $OUTPUT/f32_le_rd.tv -sed -i 's/ /_/g' $OUTPUT/f32_le_rnm.tv -echo "Editing f64_le test vectors" -sed -i 's/ /_/g' $OUTPUT/f64_le_rne.tv -sed -i 's/ /_/g' $OUTPUT/f64_le_rz.tv -sed -i 's/ /_/g' $OUTPUT/f64_le_ru.tv -sed -i 's/ /_/g' $OUTPUT/f64_le_rd.tv -sed -i 's/ /_/g' $OUTPUT/f64_le_rnm.tv -echo "Editing f128_le test vectors" -sed -i 's/ /_/g' $OUTPUT/f128_le_rne.tv -sed -i 's/ /_/g' $OUTPUT/f128_le_rz.tv -sed -i 's/ /_/g' $OUTPUT/f128_le_ru.tv -sed -i 's/ /_/g' $OUTPUT/f128_le_rd.tv -sed -i 's/ /_/g' $OUTPUT/f128_le_rnm.tv -echo "Editing f16_lt test vectors" -sed -i 's/ /_/g' $OUTPUT/f16_lt_rne.tv -sed -i 's/ /_/g' $OUTPUT/f16_lt_rz.tv -sed -i 's/ /_/g' $OUTPUT/f16_lt_ru.tv -sed -i 's/ /_/g' $OUTPUT/f16_lt_rd.tv -sed -i 's/ /_/g' $OUTPUT/f16_lt_rnm.tv -echo "Editing f32_lt test vectors" -sed -i 's/ /_/g' $OUTPUT/f32_lt_rne.tv -sed -i 's/ /_/g' $OUTPUT/f32_lt_rz.tv -sed -i 's/ /_/g' $OUTPUT/f32_lt_ru.tv -sed -i 's/ /_/g' $OUTPUT/f32_lt_rd.tv -sed -i 's/ /_/g' $OUTPUT/f32_lt_rnm.tv -echo "Editing f64_lt test vectors" -sed -i 's/ /_/g' $OUTPUT/f64_lt_rne.tv -sed -i 's/ /_/g' $OUTPUT/f64_lt_rz.tv -sed -i 's/ /_/g' $OUTPUT/f64_lt_ru.tv -sed -i 's/ /_/g' $OUTPUT/f64_lt_rd.tv -sed -i 's/ /_/g' $OUTPUT/f64_lt_rnm.tv -echo "Editing f128_lt test vectors" -sed -i 's/ /_/g' $OUTPUT/f128_lt_rne.tv -sed -i 's/ /_/g' $OUTPUT/f128_lt_rz.tv -sed -i 's/ /_/g' $OUTPUT/f128_lt_ru.tv -sed -i 's/ /_/g' $OUTPUT/f128_lt_rd.tv -sed -i 's/ /_/g' $OUTPUT/f128_lt_rnm.tv -echo "Editing f16_mulAdd test vectors" -sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rne.tv -sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rz.tv -sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_ru.tv -sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rd.tv -sed -i 's/ /_/g' $OUTPUT/f16_mulAdd_rnm.tv -echo "Editing f32_mulAdd test vectors" -sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rne.tv -sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rz.tv -sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_ru.tv -sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rd.tv -sed -i 's/ /_/g' $OUTPUT/f32_mulAdd_rnm.tv -echo "Editing f64_mulAdd test vectors" -sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rne.tv -sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rz.tv -sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_ru.tv -sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rd.tv -sed -i 's/ /_/g' $OUTPUT/f64_mulAdd_rnm.tv -echo "Editing f128_mulAdd test vectors" -sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rne.tv -sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rz.tv -sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_ru.tv -sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rd.tv -sed -i 's/ /_/g' $OUTPUT/f128_mulAdd_rnm.tv diff --git a/tests/fp/vectors/Makefile b/tests/fp/vectors/Makefile new file mode 100755 index 000000000..8d61c85ef --- /dev/null +++ b/tests/fp/vectors/Makefile @@ -0,0 +1,81 @@ +.DELETE_ON_ERROR: +SHELL := /bin/bash + +TESTFLOAT_DIR := ${WALLY}/addins/TestFloat-3e/build/Linux-x86_64-GCC +TESTFLOAT_GEN_CMD := ${TESTFLOAT_DIR}/testfloat_gen -tininessafter -level + +# List of testvectors to generate. Each rounding mode will be generated for each test. +convert := ui32_to_f16 ui32_to_f32 ui32_to_f64 ui32_to_f128 \ + ui64_to_f16 ui64_to_f32 ui64_to_f64 ui64_to_f128 \ + i32_to_f16 i32_to_f32 i32_to_f64 i32_to_f128 \ + i64_to_f16 i64_to_f32 i64_to_f64 i64_to_f128 \ + f16_to_ui32 f32_to_ui32 f64_to_ui32 f128_to_ui32 \ + f16_to_ui64 f32_to_ui64 f64_to_ui64 f128_to_ui64 \ + f16_to_i32 f32_to_i32 f64_to_i32 f128_to_i32 \ + f16_to_i64 f32_to_i64 f64_to_i64 f128_to_i64 \ + f16_to_f32 f16_to_f64 f16_to_f128 \ + f32_to_f16 f32_to_f64 f32_to_f128 \ + f64_to_f16 f64_to_f32 f64_to_f128 \ + f128_to_f16 f128_to_f32 f128_to_f64 +add := f16_add f32_add f64_add f128_add +sub := f16_sub f32_sub f64_sub f128_sub +mul := f16_mul f32_mul f64_mul f128_mul +div := f16_div f32_div f64_div f128_div +sqrt := f16_sqrt f32_sqrt f64_sqrt f128_sqrt +eq := f16_eq f32_eq f64_eq f128_eq +le := f16_le f32_le f64_le f128_le +lt := f16_lt f32_lt f64_lt f128_lt +mulAdd := f16_mulAdd f32_mulAdd f64_mulAdd f128_mulAdd + +tests := $(convert) $(add) $(sub) $(mul) $(div) $(sqrt) $(eq) $(le) $(lt) $(mulAdd) + + +.PHONY: all rne rz ru rd rnm clean + +all: rne rz ru rd rnm + +# Generate test vectors for each rounding mode +rne: $(addsuffix _rne.tv, $(tests)) +rz: $(addsuffix _rz.tv, $(tests)) +ru: $(addsuffix _ru.tv, $(tests)) +rd: $(addsuffix _rd.tv, $(tests)) +rnm: $(addsuffix _rnm.tv, $(tests)) + +# Rules to generate individual test vectors, broken up by rounding mode +%_rne.tv: ${TESTFLOAT_GEN} + @echo Creating $*_rne.tv vectors + @if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi ; \ + ${TESTFLOAT_GEN_CMD} $$level -rnear_even $* > $@ + @sed -i 's/ /_/g' $@ + +%_rz.tv: ${TESTFLOAT_GEN} + @echo Creating $*_rz.tv vectors + @if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi ; \ + ${TESTFLOAT_GEN_CMD} $$level -rminMag $* > $@ + @sed -i 's/ /_/g' $@ + +%_ru.tv: ${TESTFLOAT_GEN} + @echo Creating $*_ru.tv vectors + @if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi ; \ + ${TESTFLOAT_GEN_CMD} $$level -rmax $* > $@ + @sed -i 's/ /_/g' $@ + +%_rd.tv: ${TESTFLOAT_GEN} + @echo Creating $*_rd.tv vectors + @if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi ; \ + ${TESTFLOAT_GEN_CMD} $$level -rmin $* > $@ + @sed -i 's/ /_/g' $@ + +%_rnm.tv: ${TESTFLOAT_GEN} + @echo Creating $*_rnm.tv vectors + @if [[ "$*" =~ "to" ]] || [[ "$*" =~ "sqrt" ]] ; then level=2 ; else level=1 ; fi ; \ + ${TESTFLOAT_GEN_CMD} $$level -rnear_maxMag $* > $@ + @sed -i 's/ /_/g' $@ + +# Generate TestFloat first if necessary +${TESTFLOAT_GEN}: + $(MAKE) -C ${WALLY}/tests/fp testfloat + +clean: + rm -f *.tv + rm -f sed* diff --git a/tests/fp/case.sh b/tests/fp/vectors/case.sh similarity index 100% rename from tests/fp/case.sh rename to tests/fp/vectors/case.sh From 02f93655baf06710cffa4f0fcb532e944acf10b4 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 15 Aug 2024 19:01:13 -0700 Subject: [PATCH 211/219] Remove compiled softfloat binary --- .../build/Linux-x86_64-GCC/softfloat.a | Bin 571590 -> 0 bytes 1 file changed, 0 insertions(+), 0 deletions(-) delete mode 100644 addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a diff --git a/addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a b/addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a deleted file mode 100644 index 69cd932a8c39140eb3b940cb0e8e364b76562fb6..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 571590 zcmeFa4SZC^y*ECa_W;d_tuIuqEG@RAw}m9c2v%hm6FiF>OBF1SZ$KbHDguQKVxLw* zlPIT{%5Al^_x857|Jy#+r?>U#y%*72F&mV(wi-xP)O#(y6cbW0XbTaQ{J+0BGiPUK zcal9T)}yk zEbtk|#{HDBPfufP;y%XC`vzm5yNa>!nT${iD1!ryl}W3PRM zu|H2|?8pcf2voB`(U~mpp%+--v}r7G*6A$p@f;TT)DtXFel-hJPhf$IKF$KujpJajm1%LiIEO5hq7FddWtC9a!;IG@w0^dgZ509|GPo8FhU%bHr|B3X?Utxi5 zzhHsi-_HWieUk-VLH@o17WgyDefI^HGxF;!=alPN&N&yboO4T9&V+iFGx--RXX*%+ zGvk{q=ZY09=h~mLoJCi&od5luDAL;T)qmh;o+SkAv)%yRzy z2+MhRGs}s8gXL_S&T@WtKg;?3Dwgvc(qBZGJ)dSduN`GMZ|-L~M=oc%fe*9X!lf*? zWCqJU?UO9`tY5L*vA40@Pwi*96JB7s=Uu>ZFGRjezQl58+{$vl@GX`*2k?2HX1R-i zxAb9_yJ|Dby>%zcz3l+YZNGx$-rdM@|GAUp{^SQN_vbTM?ynB9++WwT+|G?G_qQup z?$f8U+&|pUa`&OU*QT-DH;=O1BfnyKfnTt^qWf81Nh8ZU?P`{H_D@;fC;o}$efkBK zS6RvOru=~Ag+I*l>~FHXnO|Xfb8cgK^N@d03Cmk{Cd+GD#q!o%!SdRUvb;M0|4sqR z`##F~>FF%*mndfw%6;?#miIW)fBP`Y>t4$8o?F54UWETD%0KW)miL#hv%Gg!vHaYJ zS^mfpmjB^zu>3PGXZd4aV)6YMEPu)YmLIx;<=a=W{L6pE^5^`5<-H!kAkINVFjQ=!B=Onf|jRQ!TNeu@Q)K%!FRvG3jSpuEBM!Gtl<71u!8@0 zCM$UGJFH;y2v+det*l@t%HQ=#R`3k)|K|WJcx44E=xbyJZ(Pj^22lUtG*+0ukrj?Q zlNEk=6)POQn-z|kzzWa(F)RE`2`jAp3M-s)D=Q4W!3r-uzzRQK&kC>F$_lSv!3rBM zW`#?yW`(POcPrwzpUw*JL^=O_IV=1z@PBrQ75>M5R`_2}v%+nNcO(4|C~qIiIgrB& z|AO-0euEX|Ze>Ly|A`fyaw{u3<2hDzPBkkU_YGEr`B7AH1uHrq=@(zXifVqrie?;P zMPHcCioWa_#Eaiupt4F||#Wf%Mcu&~}+VsWPc}B}HpoQp%7;>P=EG zhigscdDV4FdloEfS_&%9U$}VbqN^KLEL*9L)BJ@ClWPJ%!(Z7{pPU5%EzA7n%U3L0 zeMQ59#mnbb+*q+vsXaNV+>kV>a&AR>q$|I?A~r;sBH2_fC2M7`n7?>s!}KNd7pYBY ztf-zHnYHYaWjEclZ0Y6mFIU>KK*DA%n@+iuBy@WD{6+I)4ZzUT8Yfj|QX=Itm8hjP zR##Z9Zg zYMaipnYyMYuE4BcIBVJLNYbetTg|7%z;Wl3}+sTC~oK zH&QobUW!msbycEt5$2_fFfZK=d!?&UwFq9iz~iMWO_xEGErTdp1Vzb7u{xQ^TP<jqyS-!?}++&3(*b>4!zq z!o{mNXhp+KZdQnY9%%S7_m(uco&?TaDJ7stp8Msd#SL!il9&?FWF@+optKBAU)?aL zvncTUSN(bNrdN{e6us!=+D zrcl+xPlX{VG0)w6oYEpl)7uS7N~{4I#YGsj7a@>e zhLlug5M*kDAia!B_9EhGN25*~4iWeI%HxRvaihtp>4wBBMyIkYFFibURCxZxu((lg zT-<1Kb6oE3_PI{w@Dh|5oI3tgNO)p+>i8oe;fVo4{=^8?(c>ZWcw`geE-^9#Eyc1ag)nYNKaC z!rkt9Q7{EJtUL!iD`!1~@5)mIIP)P00-XC$*cGV=aQ?&dyFwKp;y?r;7Q}t@{IWEsn#6(AUnk2OwQB#uVyHc1=Ls?Gp$jAcIKqbL>7D;g)5i^Q+ z-c9vdq*1-j<@mf)lJ0dL;dw|>-ks)d2PEyq6nBAw`ZQ-n%_IYO(J2FbAPMIRMHRg?2IXAK1Cf4yLESs1FmP>eP;e2_{oKi~*ccx@?bcm!RRAudK zQl&&vfYnuLfu=H)nw3HTH6hSynOj5ZTATr1QEf<&9Y`rjb^;G?b=9<6_}Xg2!bz30 zmU-<(62h~VCEAm;I(OMhw@w8J##NC5q(!y46=`x)f`{QP4JQ`d+>-DdC9U?zj*6u> zvCQT|Q&!kS5!&KfY7vwnO%Vw&_~J0FpbTk>kl=>2%V;iwn>KX$m@ItpEVT+X#eG_n zS)_|WDMQyVo##j`UxjO{5wxJ?B5=m#EmyfPZ7F2BoTSNx@HME^Lgd8N3sK=$dP{43 z*(kLTImz`xRJd1&OUHCQa#PZFN=<@@q(wLt1g5Qnl6w!Dr>l`@p0++O!Fyg-#;~GH zdATTqLEpe{%!VYrV~O%; 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