From 4237bb7abd03b3fa654169f38cd72ae7aec1c35f Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 28 May 2022 09:41:48 +0000 Subject: [PATCH] Added comments to some files, added a+b = 0 detector to comparator.sv --- .gitignore | 2 ++ pipelined/src/fpu/fpu.sv | 1 + pipelined/src/hazard/hazard.sv | 2 +- pipelined/src/ieu/comparator.sv | 9 +++++++++ pipelined/srt/Makefile | 7 +++++-- pipelined/srt/testgen | Bin 13088 -> 0 bytes 6 files changed, 18 insertions(+), 3 deletions(-) delete mode 100755 pipelined/srt/testgen diff --git a/.gitignore b/.gitignore index 1e986c3bd..6e4868820 100644 --- a/.gitignore +++ b/.gitignore @@ -104,3 +104,5 @@ pipelined/config/rv64ic_noPriv pipelined/config/rv64ic_orig synthDC/Summary.csv pipelined/srt/exptestgen +pipelined/srt/testgen +pipelined/srt/qst2 diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index b4b5a2e98..581d72408 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -237,6 +237,7 @@ module fpu ( // select the result that may be written to the integer register - to IEU mux4 #(`XLEN) IntResMux(CmpResE[`XLEN-1:0], FSrcXE[`XLEN-1:0], ClassResE[`XLEN-1:0], CvtResE[`XLEN-1:0], FIntResSelE, FIntResE); + // *** DH 5/25/22: CvtRes will move to mem stage. Premux in execute to save area, then make sure stalls are ok // E/M pipe registers diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv index 159ee10ec..cf4cdaa8b 100644 --- a/pipelined/src/hazard/hazard.sv +++ b/pipelined/src/hazard/hazard.sv @@ -65,7 +65,7 @@ module hazard( assign StallFCause = CSRWritePendingDEM & ~(TrapM | RetM | BPPredWrongE); // stall in decode if instruction is a load/mul/csr dependent on previous assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FPUStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE); - assign StallECause = (DivBusyE | FDivBusyE) & ~(TrapM); + assign StallECause = (DivBusyE | FDivBusyE) & ~(TrapM); // *** can we move to decode stage (KP?) // WFI terminates if any enabled interrupt is pending, even if global interrupts are disabled. It could also terminate with TW trap assign StallMCause = wfiM & (~TrapM & ~IntPendingM); assign StallWCause = LSUStallM | IFUStallF; diff --git a/pipelined/src/ieu/comparator.sv b/pipelined/src/ieu/comparator.sv index cc2eb1723..61a17ad9f 100644 --- a/pipelined/src/ieu/comparator.sv +++ b/pipelined/src/ieu/comparator.sv @@ -30,6 +30,15 @@ `include "wally-config.vh" +module donedet #(parameter WIDTH=64) ( + input logic [WIDTH-1:0] a, b, + output logic eq); + + //assign eq = (a+b == 0); // gives good speed but 3x necessary area + // See CMOS VLSI Design 4th Ed. p. 463 K = A+B for K = 0 + assign eq = ((a ^ b) == {a[WIDTH-2:0], 1'b0} | {b[WIDTH-2:0], 1'b0}); + endmodule + module comparator_sub #(parameter WIDTH=64) ( input logic [WIDTH-1:0] a, b, output logic [2:0] flags); diff --git a/pipelined/srt/Makefile b/pipelined/srt/Makefile index 73a0b75fa..67fbd892c 100644 --- a/pipelined/srt/Makefile +++ b/pipelined/srt/Makefile @@ -1,7 +1,10 @@ -all: sqrttestgen testgen +all: sqrttestgen testgen qst2 sqrttestgen: sqrttestgen.c gcc sqrttestgen.c -lm -o sqrttestgen - + testgen: testgen.c gcc testgen.c -lm -o testgen + +qst2: qst2.c + gcc qst2.c -lm -o qst2 diff --git a/pipelined/srt/testgen b/pipelined/srt/testgen deleted file mode 100755 index bb01f81bc94bff6c806ca199a9d5f0f60e259183..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 13088 zcmeHNeQaCR6~DHVH2t#OQrfgY^Tt|8yTwhvvXrXJa}u{NC@G~)_!v!J+}KVGiCygH zHU$-eLMp7#l4)ZqLrB#|H%*%allY@UtZ@iy=zlE|TLqKm0iB$Fh_r>`u~6@v`|fd` zUu;0yChd=$kxm}l8(KPW=p=SeL1V@ck2WqS`FA%?7hZ%A55IOcYMY1UBe1lyV zi8Cf~0PWCMa9OA2?K#{h{OA>&>`+9zGGSLH?1(3YW5j8EI5s?5M0+h(86=ctWUPUo zr#R{&?YN-%usk%6i@;@GAl{_Ij5yid4|aTfqW+thQz+~d{S}G}qj(4|hRfD;2lrNQ zSkvvR><)%vy_LN+)s@v7T+y&=9UnKgkGk8oxALASjuJ@d^CCEK4PgBbK6!A*=_6yq zt(z0KzP9k#J@Vr3+=2RY;mFRL-ZA$A@lDqTX=#8ooi+osa5~I37QovI;OKq6cF+e2 z4l}I*AfNuS0{H3z`1S<>*R>;0xF?)+Mz=i7{G-4Cbi^r=^;yYG+S4q((JwL{n83 z=njV?Slyvl`+I{L3xxOiLoBc_rggADM|U{tXAy76$D*3gABnKQfk;sELwzI|(gM&T znu`{DyulFL*3?*6udZ{gb77!i@#ue8vKb_tSNvlP*NFs2Y*}zNu81&{k+4<*PU}>! zw`S|p!DxU~%O#i75jKtvK~ts8ssjDIL|7G8^xN zs?5q2aCVf-P(ry2E60-=pq0x|#*mDkt(1mk^NzKAjoeS9C6KSCLYJl@Xb2*`mUkU6cr(ilItM~Q!=^nWt3qor{y z(LPsZ%Gk)n9AsmMX2~q|AQ*lYaFjPNb}|fsX;mt5-j)8eU5Q^fU~L;ciH%`EK5HAs zs!Y;R-iO#plt_OhZ3BHJ{V-zh@FklTOFcAXt-&&w)1N!Tn|0*v(#CyW_F#a$#PEY#GXu#zte-ZPaxLX_J@4H)?j;u^ClweCZQi*(5)2a(=KU7A(vf<8}dgV))r-3Wl za%!O|ez7TjqXF8;Ec&a`KWb4nU5Z`A4fl~Y_ilHadyiWk9h&O#`Y6mi?$J|QGWUc| z7Wh^CIy%5Ke^lG=@6f`LC@9v4W8J>c-I~OIi6uj&6bN?vjXw>BW+!TOAuaf4f?pH- zs^F7?->f~l`9%NcnN01^UqZTCyPnha+Eu$>c>D8;iP}fs(tc7_G*SEb?*>2YViUDX z+O%_?C0A-&Ib9HT@@d9zA~ zEVG=5;|=5x^syQh1m)LfYz5S#{_E*X<~Zuwom=f?_d4btDD7jl%QmlGzv51WQ3rmO z*h=vA59ov2?mTR*pI>5o!vbCNdLO{2U>&~%58CLUpT&tU4jDOClKbNh474T1? z9`}l@eJ`)(eZK>68N|kq^>udV3s#T4?5NFSmyQ&9>=n-!EB30xC5pYKe^#?y?zY#s z?Nx4jMV(!$vzLK>oxPODZ65e9Lpxu;La~z>nu)+n1ZE;I6M>ls%tT-&0y7bqiNH(* zW+E^Xftd)*MBx890z2S+I#QM3T!52!eKL(pLSdfZiDH?T<_p;eub+{Y@-v*^%{S6* z{5<`s!8RUU|cYRot_}CmXEZ8ml}_0l!4HblAHIaqcVnZCjloqa_JLe{DQnM*Pkm?4)u&x<3dMc2h+WN0 zA$ke-PYavwKkl1Wh=0N~FW55T6DHgxaP$7%z}sKO_6h%KKi|di>G6C*v_roKAaXhk zXA7G?FDC%cH?BhCeT}!XkX6}bC{58Hp_nfYsFAPzGu-r+Y3tzw-p=%S|5)go*VPS< zPhX$2VE~pq>!BR*g%JOCvCe7V9spc|UpwLGhOc^h(iyw4-^T5vw&mV z@bf(q|0V(aeK?$uuhMIZLtN-n{u$aJB>_i$bKEWqeas6$;@@0=UlsT{5r6(I1@JEg z{%hgS7Bm8y1rwS#Z>IoWSpcssfbRl)fpuv%KS%GCu@AUE)Awz)Ks%3PJNfc_IwD$B ziv^lT_fkuq!KWMIK8M8j$q5sHYspQG>iU8WnBxOe>y( z)#dNy`B~u}hz$;i=Wpe9%JaN(Ax!nkMfAk3TufD4n(M_3VG>wwt)3B8AS9)h(#}Xa}f4H{PCL2lx=yuz5gm6}e!BmHb&~4Xz+X!Oiv!fZu>;8|t6# zqmP;Fi-kQsM^Uqw2Z_&eWS_9gAThY_=8Q>Vz$GAJk?i4)j?)8hw!uO6Nt?{^B!WOs z>MVOU$8QhR;IkUp)BXEyF;MD<{3ku)kAXct`;kod`Mttk7Coc?s6+k>nBjdHs**iD z51bVC^t?&^lRf$Mtgx>W4bt;#O4y$lINGC)+5RYC7!&jlDIuOC5~4$Tj@N5-U#W~d z4u{b`DeRNN{x~Wbi1Iy&{}k$s_I)KX*X|Pzk-yZ0S$@T2Pxlo=!u~xG2ePMrN&cnD zo}PbvxF~^U>nwXVHOGDfHRwOhAKf4I341428b~sfvG{v9jP{fVPWj||_1NL?}#N{&ed?xbY&H5x0$NM~o!JgjtlzvP5zk@BhNd43Ep7R^* z!GzO4;EYpE_Vipx`TR*Sez6>~>z~%aF|alEPtT9(a^8GaUzet?9~%FsCj0Djrlec6 z>nwXFJK|}mG4@aQ@9mOqVxDg?oNRkHp@ePG_%Zzz$tQ6J_td#W{Ss<}2C>a50t6@f zADM9K-^gk08&wmME|ubs3(y^Ktbv32$Gr#%uP^eQ1LE}V-Fjib)HwA^x|m9v&%RkC MePNE1kxU}{H*I5|R{#J2