diff --git a/.gitignore b/.gitignore index 1e651e68e..2d1454e3c 100644 --- a/.gitignore +++ b/.gitignore @@ -15,7 +15,7 @@ benchmarks/embench/wally*.json #vsim work files to ignore transcript vsim.wlf -pipelined/wlft* +wlft* wlft* /imperas-riscv-tests/FunctionRadix_32.addr /imperas-riscv-tests/FunctionRadix_64.addr @@ -42,8 +42,8 @@ tests/linux-testgen/buildroot-image-output tests/linux-testgen/buildroot-config-src/main.config.old tests/linux-testgen/buildroot-config-src/linux.config.old tests/linux-testgen/buildroot-config-src/busybox.config.old -pipelined/regression/slack-notifier/slack-webhook-url.txt -pipelined/regression/logs +sim/slack-notifier/slack-webhook-url.txt +sim/logs fpga/generator/IP fpga/generator/vivado.* fpga/generator/.Xil/* @@ -59,7 +59,7 @@ examples/C/sum/sum examples/C/fir/fir examples/fp/softfloat_demo/softfloat_demo examples/fp/fpcalc/fpcalc -pipelined/src/fma/fma16_testgen +src/fma/fma16_testgen linux/devicetree/debug/* !linux/devicetree/debug/dump-dts.sh linux/testvector-generation/genCheckpoint.gdb @@ -79,29 +79,25 @@ synthDC/ppa/plots synthDC/wallyplots/ synthDC/runArchive synthDC/hdl -/pipelined/regression/power.saif +sim/power.saif tests/fp/vectors/*.tv synthDC/Summary.csv -pipelined/srt/exptestgen -pipelined/srt/testgen -pipelined/srt/qslc_r4a2 -pipelined/srt/qslc_r4a2.sv -pipelined/srt/testvectors -pipelined/regression/wkdir +sim/wkdir tests/custom/work tests/custom/*/*/*.list tests/custom/*/*/*.elf tests/custom/*/*/*.map tests/custom/*/*/*.memfile tests/custom/crt0/*.a -/pipelined/regression/sd_model.log +tests/custom/*/*.elf* +sim/sd_model.log fpga/src/sdc/* fpga/src/sdc.tar.gz fpga/src/CopiedFiles_do_not_add_to_repo/* -/pipelined/regression/branch.log +sim/branch.log /fpga/generator/sim/imp-funcsim.v /fpga/generator/sim/imp-timesim.sdf /fpga/generator/sim/imp-timesim.v /fpga/generator/sim/syn-funcsim.v external -pipelined/regression/results +sim/results diff --git a/Install b/Install index 7e509197d..47a91dddd 100644 --- a/Install +++ b/Install @@ -328,6 +328,6 @@ source ./setup.sh # may require some modification for your system. Always cd make - cd pipelined/regression + cd sim ./regression-wally #(depends on having Questa installed) diff --git a/Makefile b/Makefile index b3a054e49..518bcd2dd 100644 --- a/Makefile +++ b/Makefile @@ -1,3 +1,7 @@ +# David_Harris@hmc.edu 2023 +# Top-level Makefile for CORE-V-Wally +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + all: make install make regression @@ -15,8 +19,8 @@ install: ##ln -s ${RISCV}/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe regression: - make -C pipelined/regression + make -C sim clean: - make clean -C pipelined/regression + make clean -C sim diff --git a/README.md b/README.md index 1fec92868..d8c2432d4 100644 --- a/README.md +++ b/README.md @@ -53,7 +53,7 @@ Edit setup.sh and change the following lines to point to the path and license se Run a regression simulation with Questa to prove everything is installed. - $ cd pipelined/regression + $ cd sim $ ./regression-wally (depends on having Questa installed) # Toolchain Installation (Sys Admin) @@ -110,12 +110,12 @@ Ubuntu users may need to install and update various tools. Beware when cutting ### Install RISC-V GCC Cross-Compiler -To install GCC from source can take hours to compile. This configuration enables multilib to target many flavors of RISC-V. This book is tested with GCC 12.2 (tagged 2022.09.21), but will likely work with newer versions as well. +To install GCC from source can take hours to compile. This configuration enables multilib to target many flavors of RISC-V. This book is tested with GCC 12.2 (tagged 2023.01.31), but will likely work with newer versions as well. $ git clone https://github.com/riscv/riscv-gnu-toolchain $ cd riscv-gnu-toolchain - $ git checkout 2022.09.21 - $ ./configure --prefix=$RISCV --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" + $ git checkout 2023.01.31 + $ ./configure --prefix=$RISCV --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" $ make --jobs Note: make --jobs will reduce compile time by compiling in parallel. However, adding this option could dramatically increase the memory utilization of your local machine. @@ -125,7 +125,7 @@ Note: make --jobs will reduce compile time by compiling in parallel. However, a We also need the elf2hex utility to convert executable files into hexadecimal files for Verilog simulation. Install with: $ cd $RISCV - $ export PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH + $ export PATH=$RISCV/bin:$PATH $ git clone https://github.com/sifive/elf2hex.git $ cd elf2hex $ autoreconf -i @@ -143,7 +143,7 @@ Spike also takes a while to install and compile, but this can be done concurrent $ git clone https://github.com/riscv-software-src/riscv-isa-sim $ mkdir riscv-isa-sim/build $ cd riscv-isa-sim/build - $ ../configure --prefix=$RISCV --enable-commitlog + $ ../configure --prefix=$RISCV $ make --jobs $ make install $ cd ../arch_test_target/spike/device diff --git a/benchmarks/coremark/Makefile b/benchmarks/coremark/Makefile index 8c467d581..b412c36ef 100644 --- a/benchmarks/coremark/Makefile +++ b/benchmarks/coremark/Makefile @@ -1,5 +1,6 @@ # Wally Coremark Makefile # Daniel Torres & David Harris 28 July 2022 +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 PORT_DIR = $(CURDIR)/riscv64-baremetal cmbase=../../addins/coremark @@ -21,8 +22,8 @@ PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \ all: $(work_dir)/coremark.bare.riscv.elf.memfile run: - (cd ../../pipelined/regression && (time vsim -c -do "do wally-pipelined-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log)) - cd ../../benchmarks/coremark/ + (cd ../../sim && (time vsim -c -do "do wally-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log)) + cd ../benchmarks/coremark/ # KMG: added post processing script to give out branch miss proportion along with other stats to the coremark test python3 coremark-postprocess.py diff --git a/benchmarks/coremark/coremark-postprocess.py b/benchmarks/coremark/coremark-postprocess.py index d069e8744..f77f2ef8b 100644 --- a/benchmarks/coremark/coremark-postprocess.py +++ b/benchmarks/coremark/coremark-postprocess.py @@ -9,17 +9,7 @@ # # Copyright (C) 2021 Harvey Mudd College & Oklahoma State University # -# Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -# files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -# modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -# is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -# OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -# OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 ################################################## logFile = "../../benchmarks/coremark/work/coremark.sim.log" diff --git a/benchmarks/embench/Makefile b/benchmarks/embench/Makefile index 21c30cf6e..538fb64f9 100644 --- a/benchmarks/embench/Makefile +++ b/benchmarks/embench/Makefile @@ -34,7 +34,7 @@ sim: modelsim_build_memfile modelsim_run speed # launches modelsim to simulate tests on wally modelsim_run: - (cd ../../pipelined/regression/ && vsim -c -do "do wally-pipelined-batch.do rv32gc embench") + (cd ../../sim/ && vsim -c -do "do wally-batch.do rv32gc embench") cd ../../benchmarks/embench/ # builds the objdump based on the compiled c elf files diff --git a/benchmarks/graphGen.py b/benchmarks/graphGen.py index de8b70ce9..dd7b3a204 100755 --- a/benchmarks/graphGen.py +++ b/benchmarks/graphGen.py @@ -1,4 +1,7 @@ #!/usr/bin/env python +# Daniel Torres 2022 +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + import subprocess import sys import json diff --git a/bin/imperas-one-time.sh b/bin/imperas-one-time.sh index 474bccea3..404636d7c 100755 --- a/bin/imperas-one-time.sh +++ b/bin/imperas-one-time.sh @@ -27,7 +27,7 @@ ################################################################################################ -IMP_HASH=56b1479 +IMP_HASH=355a055ff7e36bc897e942e41f06e1baf96e34d5 # clone the Imperas repo cd $WALY diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py index 35bb9c82e..5b5ce522d 100755 --- a/bin/parseHPMC.py +++ b/bin/parseHPMC.py @@ -28,6 +28,7 @@ import os import sys import matplotlib.pyplot as plt +import re def ComputeCPI(benchmark): 'Computes and inserts CPI into benchmark stats.' @@ -145,6 +146,11 @@ def FormatToPlot(currBenchmark): if(sys.argv[1] == '-b'): configList = [] + summery = 0 + if(sys.argv[2] == '-s'): + summery = 1 + sys.argv = sys.argv[1::] + print('summery = %d' % summery) for config in sys.argv[2::]: benchmarks = ProcessFile(config) ComputeAverage(benchmarks) @@ -171,18 +177,50 @@ if(sys.argv[1] == '-b'): size = len(benchmarkDict) index = 1 - print('Number of plots', size) - for benchmarkName in benchmarkDict: - currBenchmark = benchmarkDict[benchmarkName] - (names, values) = FormatToPlot(currBenchmark) - print(names, values) - plt.subplot(6, 7, index) - plt.bar(names, values) - plt.title(benchmarkName) - plt.ylabel('BR Dir Miss Rate (%)') - #plt.xlabel('Predictor') - index += 1 - #plt.tight_layout() + print('summery = %d' % summery) + if(summery == 0): + print('Number of plots', size) + for benchmarkName in benchmarkDict: + currBenchmark = benchmarkDict[benchmarkName] + (names, values) = FormatToPlot(currBenchmark) + print(names, values) + plt.subplot(6, 7, index) + plt.bar(names, values) + plt.title(benchmarkName) + plt.ylabel('BR Dir Miss Rate (%)') + #plt.xlabel('Predictor') + index += 1 + else: + combined = benchmarkDict['All_'] + (name, value) = FormatToPlot(combined) + lst = [] + dct = {} + category = [] + length = [] + accuracy = [] + for index in range(0, len(name)): + match = re.match(r"([a-z]+)([0-9]+)", name[index], re.I) + percent = 100 -value[index] + if match: + (PredType, size) = match.groups() + category.append(PredType) + length.append(size) + accuracy.append(percent) + if(PredType not in dct): + dct[PredType] = ([size], [percent]) + else: + (currSize, currPercent) = dct[PredType] + currSize.append(size) + currPercent.append(percent) + dct[PredType] = (currSize, currPercent) + print(dct) + for cat in dct: + (x, y) = dct[cat] + plt.scatter(x, y, label=cat) + plt.plot(x, y) + plt.ylabel('Prediction Accuracy') + plt.xlabel('Size (b or k)') + plt.legend(loc='upper left') plt.show() diff --git a/bin/radixcopiesmultiregression.sh b/bin/radixcopiesmultiregression.sh index 1953b1da4..5d4f3f653 100755 --- a/bin/radixcopiesmultiregression.sh +++ b/bin/radixcopiesmultiregression.sh @@ -1,4 +1,6 @@ #!/bin/bash +# Alessandro Maiuolo 2022 +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 configFile=config/shared/wally-shared.vh @@ -10,39 +12,39 @@ currCopies="define DIVCOPIES 32'h1" sed -i "s/$searchRadix/$currRadix/" $configFile sed -i "s/$searchCopies/$currCopies/" $configFile echo regression on Radix :$currRadix: and Copies :$currCopies: -./regression/regression-wally +./sim/regression-wally currRadix="define RADIX 32'h2" currCopies="define DIVCOPIES 32'h2" sed -i "s/$searchRadix/$currRadix/" $configFile sed -i "s/$searchCopies/$currCopies/" $configFile echo regression on Radix :$currRadix: and Copies :$currCopies: -./regression/regression-wally +./sim/regression-wally currRadix="define RADIX 32'h2" currCopies="define DIVCOPIES 32'h4" sed -i "s/$searchRadix/$currRadix/" $configFile sed -i "s/$searchCopies/$currCopies/" $configFile echo regression on Radix :$currRadix: and Copies :$currCopies: -./regression/regression-wally +./sim/regression-wally currRadix="define RADIX 32'h4" currCopies="define DIVCOPIES 32'h1" sed -i "s/$searchRadix/$currRadix/" $configFile sed -i "s/$searchCopies/$currCopies/" $configFile echo regression on Radix :$currRadix: and Copies :$currCopies: -./regression/regression-wally +./sim/regression-wally currRadix="define RADIX 32'h4" currCopies="define DIVCOPIES 32'h2" sed -i "s/$searchRadix/$currRadix/" $configFile sed -i "s/$searchCopies/$currCopies/" $configFile echo regression on Radix :$currRadix: and Copies :$currCopies: -./regression/regression-wally +./sim/regression-wally currRadix="define RADIX 32'h4" currCopies="define DIVCOPIES 32'h4" sed -i "s/$searchRadix/$currRadix/" $configFile sed -i "s/$searchCopies/$currCopies/" $configFile echo regression on Radix :$currRadix: and Copies :$currCopies: -./regression/regression-wally \ No newline at end of file +./sim/regression-wally \ No newline at end of file diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 08d63554f..bd0684bdf 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -54,13 +54,15 @@ fi cd $RISCV git clone https://github.com/riscv/riscv-gnu-toolchain cd riscv-gnu-toolchain -./configure --prefix=${RISCV} --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" +git checkout 2023.01.31 +./configure --prefix=${RISCV} --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" make -j ${NUM_THREADS} make install # elf2hex cd $RISCV -export PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH +#export PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH +gexport PATH=$RISCV/bin:$PATH git clone https://github.com/sifive/elf2hex.git cd elf2hex autoreconf -i @@ -87,7 +89,7 @@ cd $RISCV git clone https://github.com/riscv-software-src/riscv-isa-sim mkdir -p riscv-isa-sim/build cd riscv-isa-sim/build -../configure --prefix=$RISCV --enable-commitlog +../configure --prefix=$RISCV make -j ${NUM_THREADS} make install cd ../arch_test_target/spike/device diff --git a/pipelined/config/buildroot/wally-config.vh b/config/buildroot/wally-config.vh similarity index 100% rename from pipelined/config/buildroot/wally-config.vh rename to config/buildroot/wally-config.vh diff --git a/pipelined/config/fpga/wally-config.vh b/config/fpga/wally-config.vh similarity index 100% rename from pipelined/config/fpga/wally-config.vh rename to config/fpga/wally-config.vh diff --git a/pipelined/config/rv32e/wally-config.vh b/config/rv32e/wally-config.vh similarity index 100% rename from pipelined/config/rv32e/wally-config.vh rename to config/rv32e/wally-config.vh diff --git a/pipelined/config/rv32gc/wally-config.vh b/config/rv32gc/wally-config.vh similarity index 100% rename from pipelined/config/rv32gc/wally-config.vh rename to config/rv32gc/wally-config.vh diff --git a/pipelined/config/rv32i/wally-config.vh b/config/rv32i/wally-config.vh similarity index 100% rename from pipelined/config/rv32i/wally-config.vh rename to config/rv32i/wally-config.vh diff --git a/pipelined/config/rv32imc/wally-config.vh b/config/rv32imc/wally-config.vh similarity index 100% rename from pipelined/config/rv32imc/wally-config.vh rename to config/rv32imc/wally-config.vh diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/config/rv64fpquad/wally-config.vh similarity index 100% rename from pipelined/config/rv64fpquad/wally-config.vh rename to config/rv64fpquad/wally-config.vh diff --git a/pipelined/config/rv64gc/wally-config.vh b/config/rv64gc/wally-config.vh similarity index 100% rename from pipelined/config/rv64gc/wally-config.vh rename to config/rv64gc/wally-config.vh diff --git a/pipelined/config/rv64i/wally-config.vh b/config/rv64i/wally-config.vh similarity index 100% rename from pipelined/config/rv64i/wally-config.vh rename to config/rv64i/wally-config.vh diff --git a/pipelined/config/shared/README b/config/shared/README similarity index 100% rename from pipelined/config/shared/README rename to config/shared/README diff --git a/pipelined/config/shared/wally-shared.vh b/config/shared/wally-shared.vh similarity index 99% rename from pipelined/config/shared/wally-shared.vh rename to config/shared/wally-shared.vh index 5d60fdce3..507388f7f 100644 --- a/pipelined/config/shared/wally-shared.vh +++ b/config/shared/wally-shared.vh @@ -135,9 +135,6 @@ `define DIVBLEN ($clog2(`DIVb+1)-1) `define DIVa (`DIVb+1-`XLEN) // used for idiv on fpu -// Memory synthesis configuration -`define USE_SRAM 0 - // Disable spurious Verilator warnings /* verilator lint_off STMTDLY */ diff --git a/examples/C/fir/Makefile b/examples/C/fir/Makefile index c27e423a5..4e3991e46 100644 --- a/examples/C/fir/Makefile +++ b/examples/C/fir/Makefile @@ -5,7 +5,7 @@ $(TARGET).objdump: $(TARGET) spike $(TARGET) $(TARGET): $(TARGET).c Makefile - riscv64-unknown-elf-gcc -o $(TARGET) -g -O2\ + riscv64-unknown-elf-gcc -o $(TARGET) -g\ -march=rv64gc -mabi=lp64d -mcmodel=medany \ -nostdlib -static -lm -fno-tree-loop-distribute-patterns \ -T../common/test.ld -I../common \ diff --git a/examples/C/lab1matrix/Makefile b/examples/C/lab1matrix/Makefile deleted file mode 100644 index 18c011f4f..000000000 --- a/examples/C/lab1matrix/Makefile +++ /dev/null @@ -1,33 +0,0 @@ -TARGET = matMult - -$(TARGET).objdump: $(TARGET) - riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump - spike $(TARGET) - -$(TARGET): $(TARGET).c Makefile - riscv64-unknown-elf-gcc -o $(TARGET) -g -O\ - -march=rv64gc -mabi=lp64d -mcmodel=medany \ - -nostdlib -static -lm -fno-tree-loop-distribute-patterns \ - -T../common/test.ld -I../common \ - $(TARGET).c ../common/crt.S ../common/syscalls.c -# Compiler flags: -# -o $(TARGET) defines the name of the output file -# -g generates debugging symbols for gdb -# -O turns on basic optimization; -O3 turns on heavy optimization; omit for no optimization -# -march=rv64gc -mabi=lp64d =mcmodel=medany generates code for RV64GC with doubles and long/ptrs = 64 bits -# -static forces static linking (no dynamic shared libraries on bare metal) -# -lm links the math library if necessary (when #include math.h) -# -nostdlib avoids inserting standard startup files and default libraries -# because we are using crt.s on bare metal -# -fno-tree-loop-distribute-patterns turns replacing loops with memcpy/memset in the std library -# -T specifies the linker file -# -I specifies the include path (e.g. for util.h) -# The last line defines the C files to compile. -# crt.S is needed as our startup file to initialize the processor -# syscalls.c implements printf through the HTIF for Spike -# other flags from riscv-tests makefiles that don't seem to be important -# -ffast-math -DPREALLOCATE=1 -std=gnu99 \ -# -fno-common -fno-builtin-printf -nostartfiles -lgcc \ - -clean: - rm -f $(TARGET) $(TARGET).objdump diff --git a/examples/C/lab1matrix/matMult b/examples/C/lab1matrix/matMult deleted file mode 100755 index e3d3b25dd..000000000 Binary files a/examples/C/lab1matrix/matMult and /dev/null differ diff --git a/examples/C/lab1matrix/matMult.c b/examples/C/lab1matrix/matMult.c deleted file mode 100644 index b794819f9..000000000 --- a/examples/C/lab1matrix/matMult.c +++ /dev/null @@ -1,87 +0,0 @@ -// matMult.c -// mmasserfrye@hmc.edu 30 January 2022 - -#include // supports printf -#include // supports fabs -#include "util.h" // supports verify - -// puts the indicated row of length n from matrix mat into array arr -void getRow(int n, int row, double *mat, double *arr){ - int ind; - for (int i=0; i. diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile index b200a22de..562dcfbc9 100644 --- a/fpga/generator/Makefile +++ b/fpga/generator/Makefile @@ -31,7 +31,7 @@ SDC: PreProcessFiles: rm -rf ../src/CopiedFiles_do_not_add_to_repo/ - cp -r ../../pipelined/src/ ../src/CopiedFiles_do_not_add_to_repo/ + cp -r ../../src/ ../src/CopiedFiles_do_not_add_to_repo/ ./insert_debug_comment.sh $(dst)/%.log: %.tcl diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index 55f65b31b..d58199e19 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -26,7 +26,7 @@ read_verilog [glob -type f ../../pipelined/src/uncore/newsdc/*.v] read_verilog {../src/fpgaTop.v} read_verilog -sv [glob -type f ../src/sdc/*.sv] -set_property include_dirs {../../pipelined/config/fpga ../../pipelined/config/shared} [current_fileset] +set_property include_dirs {../../config/fpga ../../config/shared} [current_fileset] add_files -fileset constrs_1 -norecurse ../constraints/constraints-$boardSubName.xdc diff --git a/pipelined/regression/sim-wally b/pipelined/regression/sim-wally deleted file mode 100755 index 51c8b3edc..000000000 --- a/pipelined/regression/sim-wally +++ /dev/null @@ -1,2 +0,0 @@ -vsim -do "do wally-pipelined.do rv64gc arch64d" - diff --git a/pipelined/regression/sim-wally-batch b/pipelined/regression/sim-wally-batch deleted file mode 100755 index e9a387d0a..000000000 --- a/pipelined/regression/sim-wally-batch +++ /dev/null @@ -1 +0,0 @@ -vsim -c -do "do wally-pipelined-batch.do rv32gc wally32priv" diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do deleted file mode 100644 index b62c31227..000000000 --- a/pipelined/regression/wave.do +++ /dev/null @@ -1,679 +0,0 @@ -onerror {resume} -quietly virtual signal -install /testbench/dut/core/ifu/bpred/bpred { /testbench/dut/core/ifu/bpred/bpred/PostSpillInstrRawF[11:7]} rd -quietly WaveActivateNextPane {} 0 -add wave -noupdate /testbench/clk -add wave -noupdate /testbench/reset -add wave -noupdate /testbench/reset_ext -add wave -noupdate /testbench/memfilename -add wave -noupdate /testbench/dut/core/SATP_REGW -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM -add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/MDUStallD -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallF -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallD -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW -add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName -add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF -add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrD -add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrE -add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrM -add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCNextF -add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCF -add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCD -add wave -noupdate -expand -group PCS /testbench/dut/core/PCE -add wave -noupdate -expand -group PCS /testbench/dut/core/PCM -add wave -noupdate -expand -group PCS /testbench/PCW -add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD -add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD -add wave -noupdate -group {Decode Stage} /testbench/InstrDName -add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/InstrValidD -add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD -add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD -add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D -add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D -add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE -add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE -add wave -noupdate -group {Execution Stage} /testbench/InstrEName -add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE -add wave -noupdate -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM -add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -group {WriteBack stage} /testbench/PCW -add wave -noupdate -group {WriteBack stage} /testbench/InstrW -add wave -noupdate -group {WriteBack stage} /testbench/InstrWName -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MCAUSE_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEPC_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIDELEG_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIE_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW -add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check} -add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF -add wave -noupdate -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE -add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE -add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE -add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE -add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE -add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE -add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE -add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE -add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/PCNext0F -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext1F -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredWrongE -add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf -add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1 -add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2 -add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a3 -add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd1 -add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd2 -add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/we3 -add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/wd3 -add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ReadDataW -add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/CSRReadValW -add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultSrcW -add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultW -add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/A -add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/B -add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/Result -add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/ALUControl -add wave -noupdate -group alu -divider internals -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1D -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2D -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1E -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2E -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdE -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdM -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdW -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/MemReadE -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteM -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteW -add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardAE -add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardBE -add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/LoadStallD -add wave -noupdate -group Forward /testbench/dut/core/ieu/dp/IFResultM -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/ForwardAE -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1E -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdM -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdW -add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE -add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE -add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE -add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUReq -add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUReq -add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSave -add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFURestore -add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUDisable -add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUDisable -add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSelect -add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUSelect -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST -add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHTRANS -add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHADDR -add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHBURST -add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHREADY -add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/HRDATA -add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUReq -add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHTRANS -add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHSIZE -add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHBURST -add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHADDR -add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/HRDATA -add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWRITE -add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWSTRB -add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWDATA -add wave -noupdate -group AHB -expand -group LSU -color Pink /testbench/dut/core/lsu/LSUHREADY -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HCLK -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESETn -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HREADY -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESP -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HADDR -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWDATA -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWRITE -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HSIZE -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM -add wave -noupdate -expand -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/FWriteDataM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK -add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW -add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW -add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr -add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} -add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM[62]} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData -add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit -add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck -add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr -add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal -add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWalk -add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/WalkerState -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWAdr -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PTE -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCFSpill -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/NextPageType -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PageType -add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ValidNonLeafPTE -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ITLBWriteF -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWriteM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSULoadAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSUStoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWInstrAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LoadAccessFaultM -add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/StoreAmoAccessFaultM -add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr -add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr -add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/MExtInt -add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/SExtInt -add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/Dout -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intClaim -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intEn -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intInProgress -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intPending -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intPriority -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intThreshold -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/nextIntPending -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/requests -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/irqMatrix -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/priorities_with_irqs -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/max_priority_with_irqs -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/irqs_at_max_priority -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/threshMask -add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsIn -add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsOut -add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsEn -add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIntr -add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSEL -add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PADDR -add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWRITE -add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PRDATA -add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PREADY -add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWDATA -add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSTRB -add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PENABLE -add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIME -add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIMECMP -add wave -noupdate -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PSEL -add wave -noupdate -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PADDR -add wave -noupdate -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PWDATA -add wave -noupdate -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PSTRB -add wave -noupdate -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PWRITE -add wave -noupdate -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PENABLE -add wave -noupdate -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PRDATA -add wave -noupdate -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PREADY -add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/LSR -add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/MCR -add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/MSR -add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/RBR -add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/TXHR -add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/LCR -add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/intrID -add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/INTR -add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxstate -add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/txstate -add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/txbitssent -add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/txbitsexpected -add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxbitsreceived -add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxbitsexpected -add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxdata -add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxoverrunerr -add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxdataready -add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxdataavailintr -add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/RXBR -add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/squashRXerrIP -add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxshiftreg -add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/SOUTbit -add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/SINsync -add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/txsr -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/SIN -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/SOUT -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/RTSb -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DTRb -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/OUT1b -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/OUT2b -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DSRb -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DCDb -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/CTSb -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/TXRDYb -add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/RXRDYb -add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/core/FlushW -add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/PCM -add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM -add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW -add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F -add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/InstrRawF -add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF -add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUStallF -add wave -noupdate -expand -group ifu -group Spill /testbench/dut/core/ifu/Spill/spill/CurrState -add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/SpillF -add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallD -add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissF -add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/InstrDAPageFaultF -add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF -add wave -noupdate -expand -group ifu -group Spill /testbench/dut/core/ifu/SelNextSpillF -add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE -add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST -add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS -add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE -add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR -add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush -add wave -noupdate -expand -group ifu -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState -add wave -noupdate -expand -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss -add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay -add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF -add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr -add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/bwe} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/dout} -add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/RAM} -add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite -add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/ITLBMissF -add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/VAdr -add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress -add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/Matches -add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/InstrPageFaultF -add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/TLBFlush -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Valid} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/PageType} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key0} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key1} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/match/Key2} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/match/Key3} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query0} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query1} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/match/Query2} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/match/Query3} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Valid} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageTypeWriteVal} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageType} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key0} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/match/Key2} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/match/Key3} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/match/Query2} -add wave -noupdate -expand -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/match/Query3} -add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]} -add wave -noupdate -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]} -add wave -noupdate -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]} -add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP DIRECTION WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]} -add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]} -add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BTA/JTA WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]} -add wave -noupdate -group {Performance Counters} -expand -group BRP -label {JAL(R) INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]} -add wave -noupdate -group {Performance Counters} -expand -group BRP -label {RAS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]} -add wave -noupdate -group {Performance Counters} -expand -group BRP -label {RETURN INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]} -add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]} -add wave -noupdate -group {Performance Counters} -expand -group BRP -label {Branch Predictor Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]} -add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]} -add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]} -add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]} -add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]} -add wave -noupdate -group {ifu } -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState -add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/HREADY -add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/FetchBuffer -add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/CaptureEn -add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR -add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE -add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS -add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CacheBusAck -add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/VPN -add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/TLBWrite -add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/PTE -add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/VAdr -add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/FRD1E -add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/FRD2E -add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/FRD3E -add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcAE -add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcBE -add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/Funct3E -add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/W64E -add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/X -add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/Y -add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/Z -add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/fregfile/rf -add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HADDR -add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HTRANS -add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HREADY -add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELRegions -add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELNoneD -add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELPLICD -add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HRDATA -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PopF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PushE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/RASPCF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/RepairD -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/rd -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PostSpillInstrRawF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BTBPredPCWrongM -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetWrongE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassD -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassD -add wave -noupdate -color Firebrick /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredWrongM -add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF -add wave -noupdate -expand -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE -add wave -noupdate -expand -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE -add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/TableDirPredictionF -add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF -add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionWrongE -add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM -add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushE -add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF -add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD -add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE -add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD -add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF -add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextD -add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextE -add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionE -add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE -add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM -add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/PCNextF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TableBTBPredictionF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredPCF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/SelBPPredF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredValidF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD -add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW -add wave -noupdate /testbench/dut/core/ifu/CSRWriteFenceM -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {1151457 ns} 0} {{Cursor 4} {1156601 ns} 1} {{Cursor 5} {1156601 ns} 1} -quietly wave cursor active 3 -configure wave -namecolwidth 250 -configure wave -valuecolwidth 194 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {1151311 ns} {1151571 ns} diff --git a/pipelined/src/ifu/bpred/speculativeglobalhistory.sv b/pipelined/src/ifu/bpred/speculativeglobalhistory.sv deleted file mode 100644 index 3ed9ba3e5..000000000 --- a/pipelined/src/ifu/bpred/speculativeglobalhistory.sv +++ /dev/null @@ -1,142 +0,0 @@ -/////////////////////////////////////////// -// speculativeglobalhistory.sv -// -// Written: Shreya Sanghai -// Email: ssanghai@hmc.edu -// Created: March 16, 2021 -// Modified: -// -// Purpose: Global History Branch predictor with parameterized global history register -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module speculativeglobalhistory #(parameter int k = 10 ) ( - input logic clk, - input logic reset, - input logic StallF, StallD, StallE, StallM, StallW, - input logic FlushD, FlushE, FlushM, FlushW, - output logic [1:0] DirPredictionF, - output logic DirPredictionWrongE, - // update - input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, - input logic [3:0] WrongPredInstrClassD, - input logic PCSrcE -); - - logic MatchF, MatchD, MatchE; - logic MatchNextX, MatchXF; - - logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE; - logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE; - - logic [k-1:0] GHRF; - logic GHRExtraF; - logic [k-1:0] GHRD, GHRE, GHRM, GHRW; - logic [k-1:0] GHRNextF; - logic [k-1:0] GHRNextD; - logic [k-1:0] GHRNextE, GHRNextM, GHRNextW; - logic [k-1:0] IndexNextF, IndexF; - logic [k-1:0] IndexD, IndexE; - - - logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF; - - assign IndexNextF = GHRNextF; - assign IndexF = GHRF; - assign IndexD = GHRD[k-1:0]; - assign IndexE = GHRE[k-1:0]; - - ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), - .ce1(~StallF | reset), .ce2(~StallM & ~FlushM), - .ra1(IndexNextF), - .rd1(TableDirPredictionF), - .wa2(IndexE), - .wd2(NewDirPredictionE), - .we2(BranchInstrE & ~StallM & ~FlushM), - .bwe2(1'b1)); - - // if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage - // and then register for use in the Fetch stage. - assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF); - assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD); - assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE); - assign MatchNextX = MatchF | MatchD | MatchE; - - flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); - - assign ForwardNewDirPrediction = MatchF ? NewDirPredictionF : - MatchD ? NewDirPredictionD : - NewDirPredictionE ; - - flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF); - - assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF; - - // DirPrediction pipeline - flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD); - flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE); - - // New prediction pipeline - assign NewDirPredictionF = {DirPredictionF[1], DirPredictionF[1]}; - - flopenr #(2) NewPredDReg(clk, reset, ~StallD, NewDirPredictionF, NewDirPredictionD); - satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE)); - - // GHR pipeline - // this version fails the regression test do to pessimistic x propagation. - // assign GHRNextF = FlushD | DirPredictionWrongE ? GHRNextD[k-1:0] : - // BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : - // GHRF; - - always_comb begin - if(FlushD | DirPredictionWrongE) begin - GHRNextF = GHRNextD[k-1:0]; - end else if(BranchInstrF) GHRNextF = {DirPredictionF[1], GHRF[k-1:1]}; - else GHRNextF = GHRF; - end - - flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF); - flopenr #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRF[0], GHRExtraF); - - // use with out instruction class prediction - //assign GHRNextD = FlushD ? GHRNextE[k-1:0] : GHRF[k-1:0]; - // with instruction class prediction - assign GHRNextD = (FlushD | DirPredictionWrongE) ? GHRNextE[k-1:0] : - WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], GHRF[k-1:1]} : // shift right - WrongPredInstrClassD[0] & ~BranchInstrD ? {GHRF[k-2:0], GHRExtraF}: // shift left - GHRF[k-1:0]; - - flopenr #(k) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD); - - assign GHRNextE = BranchInstrE & ~FlushM ? {PCSrcE, GHRD[k-2:0]} : // if the branch is not flushed - FlushE ? GHRNextM : // branch is flushed - GHRD; - flopenr #(k) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, GHRE); - - assign GHRNextM = FlushM ? GHRNextW : GHRE; - flopenr #(k) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM); - - assign GHRNextW = FlushW ? GHRW : GHRM; - flopenr #(k) GHRWReg(clk, reset, (BranchInstrW & ~StallW) | FlushW, GHRNextW, GHRW); - - assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE; - -endmodule diff --git a/setup.imperas.sh b/setup.imperas.sh index e3ac447bf..71d5dcfd5 100644 --- a/setup.imperas.sh +++ b/setup.imperas.sh @@ -31,12 +31,12 @@ export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC # setup QUESTA (Imperas only command, YMMV) svsetup -questa -pushd pipelined/regression +pushd sim # With IDV IMPERAS_TOOLS=$(pwd)/imperas.ic \ OTHERFLAGS="+TRACE2LOG_ENABLE=1 VERBOSE=1" \ TESTDIR=${WALLY}/external/ImperasDV-HMC/tests/riscof/work/riscv-arch-test/rv64i_m/F/src/fadd_b1-01.S \ - vsim -c -do "do wally-pipelined-imperas.do rv64gc" + vsim -c -do "do wally-imperas.do rv64gc" popd # notes @@ -50,7 +50,7 @@ popd IMPERAS_TOOLS=$(pwd)/imperas.ic \ OTHERFLAGS="+TRACE2LOG_ENABLE=1 VERBOSE=1" \ TESTDIR=../../tests/riscof_lee/work/riscv-arch-test/rv64i_m/F/src/fadd_b1-01.S \ -vsim -c -do "do wally-pipelined-imperas.do rv64gc" +vsim -c -do "do wally-imperas.do rv64gc" # getting library issue. diff --git a/setup.sh b/setup.sh index d54ae7bd4..af4bac3b5 100755 --- a/setup.sh +++ b/setup.sh @@ -3,6 +3,7 @@ # setup.sh # David_Harris@hmc.edu and kekim@hmc.edu 1 December 2021 # Set up tools for rvw +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 echo "Executing Wally setup.sh" diff --git a/pipelined/regression/Makefile b/sim/Makefile similarity index 62% rename from pipelined/regression/Makefile rename to sim/Makefile index adc7bc718..6a917bcda 100644 --- a/pipelined/regression/Makefile +++ b/sim/Makefile @@ -2,27 +2,27 @@ all: riscoftests memfiles # *** Build old tests/imperas-riscv-tests for now; # Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test # DH: 2/27/22 temporarily commented out imperas-riscv-tests because license expired - #make -C ../../tests/imperas-riscv-tests --jobs - #make -C ../../tests/imperas-riscv-tests XLEN=64 --jobs + #make -C ../tests/imperas-riscv-tests --jobs + #make -C ../tests/imperas-riscv-tests XLEN=64 --jobs # Only compile Imperas tests if they are installed locally. # They are usually a symlink to $RISCV/imperas-riscv-tests and only # get compiled there manually during installation - #make -C ../../addins/imperas-riscv-tests - #make -C ../../addins/imperas-riscv-tests XLEN=64 - #cd ../../addins/imperas-riscv-tests; elf2hex.sh - #cd ../../addins/imperas-riscv-tests; extractFunctionRadix.sh work/*/*/*.elf.objdump + #make -C ../addins/imperas-riscv-tests + #make -C ../addins/imperas-riscv-tests XLEN=64 + #cd ../addins/imperas-riscv-tests; elf2hex.sh + #cd ../addins/imperas-riscv-tests; extractFunctionRadix.sh work/*/*/*.elf.objdump # Link Linux test vectors - #cd ../../tests/linux-testgen/linux-testvectors/;./tvLinker.sh + #cd ../tests/linux-testgen/linux-testvectors/;./tvLinker.sh allclean: clean all clean: - make clean -C ../../tests/riscof + make clean -C ../tests/riscof # make clean -C ../../tests/wally-riscv-arch-test # make allclean -C ../../tests/imperas-riscv-tests riscoftests: # Builds riscv-arch-test 64 and 32-bit versions and builds wally-riscv-arch-test 64 and 32-bit versions - make -C ../../tests/riscof/ + make -C ../tests/riscof/ memfiles: make -f makefile-memfile wally-sim-files --jobs diff --git a/pipelined/regression/buildrootBugFinder.py b/sim/buildrootBugFinder.py similarity index 90% rename from pipelined/regression/buildrootBugFinder.py rename to sim/buildrootBugFinder.py index 89a838d2f..af6324596 100755 --- a/pipelined/regression/buildrootBugFinder.py +++ b/sim/buildrootBugFinder.py @@ -22,7 +22,7 @@ def main(): break checkpoint = checkpointList[0] logFile = logDir+"checkpoint"+str(checkpoint)+".log" - runCommand="{\nvsim -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < ${OUTDIR} :: ${OUTLOG}" mkdir -p ${OUTDIR} - vsim -c -do "do wally-pipelined-imperas.do rv64gc" + vsim -c -do "do wally-imperas.do rv64gc" mv transcript ${OUTLOG} done diff --git a/pipelined/regression/sim-buildroot b/sim/sim-buildroot similarity index 84% rename from pipelined/regression/sim-buildroot rename to sim/sim-buildroot index 938bff866..530e33386 100755 --- a/pipelined/regression/sim-buildroot +++ b/sim/sim-buildroot @@ -30,4 +30,4 @@ echo "INSTR_LIMIT = ${INSTR_LIMIT}" echo "INSTR_WAVEON = ${INSTR_WAVEON}" echo "CHECKPOINT = ${CHECKPOINT}" -vsim -do "do ./wally-pipelined.do buildroot buildroot $RISCV $INSTR_LIMIT $INSTR_WAVEON $CHECKPOINT" +vsim -do "do ./wally.do buildroot buildroot $RISCV $INSTR_LIMIT $INSTR_WAVEON $CHECKPOINT" diff --git a/pipelined/regression/sim-buildroot-batch b/sim/sim-buildroot-batch similarity index 85% rename from pipelined/regression/sim-buildroot-batch rename to sim/sim-buildroot-batch index a8d4038ef..81a6fac1e 100755 --- a/pipelined/regression/sim-buildroot-batch +++ b/sim/sim-buildroot-batch @@ -32,5 +32,5 @@ echo "CHECKPOINT = ${CHECKPOINT}" # *** change config from buildroot to rv64gc vsim -c <" prompt: -# do wally-pipelined.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do wally-pipelined.do -c -# (omit the "-c" to see the GUI while running from the shell) +# run with vsim -do "do wally.do rv64ic riscvarchtest-64m" onbreak {resume} diff --git a/pipelined/regression/wally-pipelined-batch.do b/sim/wally-batch.do similarity index 89% rename from pipelined/regression/wally-pipelined-batch.do rename to sim/wally-batch.do index 4bd153ce7..064f503b2 100644 --- a/pipelined/regression/wally-pipelined-batch.do +++ b/sim/wally-batch.do @@ -1,4 +1,5 @@ -# wally-pipelined-batch.do +# wally-batch.do +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 # # Modification by Oklahoma State University & Harvey Mudd College # Use with Testbench @@ -7,14 +8,14 @@ # # Takes 1:10 to run RV64IC tests using gui -# Usage: do wally-pipelined-batch.do -# Example: do wally-pipelined-batch.do rv32imc imperas-32i +# Usage: do wally-batch.do +# Example: do wally-batch.do rv32imc imperas-32i -# Use this wally-pipelined-batch.do file to run this example. +# Use this wally-batch.do file to run this example. # Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do wally-pipelined-batch.do +# do wally-batch.do # or, to run from a shell, type the following at the shell prompt: -# vsim -do wally-pipelined-batch.do -c +# vsim -do wally-batch.do -c # (omit the "-c" to see the GUI while running from the shell) onbreak {resume} @@ -91,9 +92,9 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { # power off -r /dut/core/* } -#coverage report -file wally-pipelined-coverage.txt +#coverage report -file wally-coverage.txt # These aren't doing anything helpful #coverage report -memory -#profile report -calltree -file wally-pipelined-calltree.rpt -cutoff 2 +#profile report -calltree -file wally-calltree.rpt -cutoff 2 #power report -all -bsaif power.saif quit diff --git a/sim/wally-imperas-cov.do b/sim/wally-imperas-cov.do new file mode 100644 index 000000000..9ac7a39e4 --- /dev/null +++ b/sim/wally-imperas-cov.do @@ -0,0 +1,68 @@ +# wally.do +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Modification by Oklahoma State University & Harvey Mudd College +# Use with Testbench +# James Stine, 2008; David Harris 2021 +# Go Cowboys!!!!!! +# +# Takes 1:10 to run RV64IC tests using gui + +onbreak {resume} + +# create library +if [file exists work] { + vdel -all +} +vlib work + +# compile source files +# suppress spurious warnngs about +# "Extra checking for conflicts with always_comb done at vopt time" +# because vsim will run vopt + +# start and run simulation +# remove +acc flag for faster sim during regressions if there is no need to access internal signals + # *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings. +vlog +incdir+../config/$1 \ + +incdir+../config/shared \ + +define+USE_IMPERAS_DV \ + +incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \ + +incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \ + $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-api-pkg.sv \ + $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-trace.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/rvvi-pkg.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2api.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2log.sv \ + \ + +define+INCLUDE_TRACE2COV +define+COVER_BASE_RV64I +define+COVER_LEVEL_DV_PR_EXT \ + +define+COVER_RV64I \ + +define+COVER_RV64C \ + +define+COVER_RV64M \ + +incdir+$env(IMPERAS_HOME)/ImpProprietary/source/host/riscvISACOV/source \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2cov.sv \ + \ + ../testbench/testbench_imperas.sv \ + ../testbench/common/*.sv \ + ../src/*/*.sv \ + ../src/*/*/*.sv \ + -suppress 2583 \ + -suppress 7063 \ + +acc +vopt +acc work.testbench -G DEBUG=1 -o workopt +vsim workopt +nowarn3829 -fatal 7 \ + -sv_lib $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model \ + +testDir=$env(TESTDIR) $env(OTHERFLAGS) +TRACE2COV_ENABLE=1 \ + -do "coverage save -onexit ./riscv.ucdb" + +view wave +#-- display input and output signals as hexidecimal values +# add log -recursive /* +# do wave.do + +run -all + +noview ../testbench/testbench_imperas.sv +view wave + +quit -f diff --git a/pipelined/regression/wally-pipelined-imperas-no-idv.do b/sim/wally-imperas-no-idv.do similarity index 73% rename from pipelined/regression/wally-pipelined-imperas-no-idv.do rename to sim/wally-imperas-no-idv.do index 646c41c72..5f300250c 100644 --- a/pipelined/regression/wally-pipelined-imperas-no-idv.do +++ b/sim/wally-imperas-no-idv.do @@ -1,4 +1,5 @@ -# wally-pipelined.do +# wally.do +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 # # Modification by Oklahoma State University & Harvey Mudd College # Use with Testbench @@ -7,15 +8,6 @@ # # Takes 1:10 to run RV64IC tests using gui -# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m" - -# Use this wally-pipelined.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do wally-pipelined.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do wally-pipelined.do -c -# (omit the "-c" to see the GUI while running from the shell) - onbreak {resume} # create library diff --git a/pipelined/regression/wally-pipelined-imperas.do b/sim/wally-imperas.do similarity index 77% rename from pipelined/regression/wally-pipelined-imperas.do rename to sim/wally-imperas.do index 21ed71420..d10c57d57 100644 --- a/pipelined/regression/wally-pipelined-imperas.do +++ b/sim/wally-imperas.do @@ -1,4 +1,5 @@ -# wally-pipelined.do +# wally.do +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 # # Modification by Oklahoma State University & Harvey Mudd College # Use with Testbench @@ -7,15 +8,6 @@ # # Takes 1:10 to run RV64IC tests using gui -# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m" - -# Use this wally-pipelined.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do wally-pipelined.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do wally-pipelined.do -c -# (omit the "-c" to see the GUI while running from the shell) - onbreak {resume} # create library @@ -42,6 +34,7 @@ vlog +incdir+../config/$1 \ $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/rvvi-pkg.sv \ $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2api.sv \ $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2log.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2cov.sv \ ../testbench/testbench_imperas.sv \ ../testbench/common/*.sv \ ../src/*/*.sv \ @@ -54,10 +47,12 @@ vsim workopt +nowarn3829 -fatal 7 \ +testDir=$env(TESTDIR) $env(OTHERFLAGS) view wave #-- display input and output signals as hexidecimal values -add log -recursive /* -do wave.do +# add log -recursive /* +# do wave.do run -all noview ../testbench/testbench_imperas.sv view wave + +quit -f diff --git a/pipelined/regression/wally-pipelined.do b/sim/wally.do similarity index 95% rename from pipelined/regression/wally-pipelined.do rename to sim/wally.do index 9d61511b7..895b10b95 100644 --- a/pipelined/regression/wally-pipelined.do +++ b/sim/wally.do @@ -1,4 +1,5 @@ -# wally-pipelined.do +# wally.do +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 # # Modification by Oklahoma State University & Harvey Mudd College # Use with Testbench @@ -11,9 +12,9 @@ # Use this wally-pipelined.do file to run this example. # Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do wally-pipelined.do +# do wally.do # or, to run from a shell, type the following at the shell prompt: -# vsim -do wally-pipelined.do -c +# vsim -do wally.do -c # (omit the "-c" to see the GUI while running from the shell) onbreak {resume} diff --git a/pipelined/regression/wave-all.do b/sim/wave-all.do similarity index 100% rename from pipelined/regression/wave-all.do rename to sim/wave-all.do diff --git a/pipelined/regression/wave-dos/ahb-muldiv.do b/sim/wave-dos/ahb-muldiv.do similarity index 100% rename from pipelined/regression/wave-dos/ahb-muldiv.do rename to sim/wave-dos/ahb-muldiv.do diff --git a/pipelined/regression/wave-dos/ahb-waves.do b/sim/wave-dos/ahb-waves.do similarity index 100% rename from pipelined/regression/wave-dos/ahb-waves.do rename to sim/wave-dos/ahb-waves.do diff --git a/pipelined/regression/wave-dos/cache-waves.do b/sim/wave-dos/cache-waves.do similarity index 100% rename from pipelined/regression/wave-dos/cache-waves.do rename to sim/wave-dos/cache-waves.do diff --git a/pipelined/regression/wave-dos/default-waves.do b/sim/wave-dos/default-waves.do similarity index 100% rename from pipelined/regression/wave-dos/default-waves.do rename to sim/wave-dos/default-waves.do diff --git a/pipelined/regression/wave-dos/generic.do b/sim/wave-dos/generic.do similarity index 100% rename from pipelined/regression/wave-dos/generic.do rename to sim/wave-dos/generic.do diff --git a/pipelined/regression/wave-dos/linux-waves.do b/sim/wave-dos/linux-waves.do similarity index 100% rename from pipelined/regression/wave-dos/linux-waves.do rename to sim/wave-dos/linux-waves.do diff --git a/pipelined/regression/wave-dos/peripheral-waves.do b/sim/wave-dos/peripheral-waves.do similarity index 100% rename from pipelined/regression/wave-dos/peripheral-waves.do rename to sim/wave-dos/peripheral-waves.do diff --git a/pipelined/regression/wave-fpu.do b/sim/wave-fpu.do similarity index 100% rename from pipelined/regression/wave-fpu.do rename to sim/wave-fpu.do diff --git a/sim/wave.do b/sim/wave.do new file mode 100644 index 000000000..5faf74f35 --- /dev/null +++ b/sim/wave.do @@ -0,0 +1,682 @@ +onerror {resume} +quietly virtual signal -install /testbench/dut/core/ifu/bpred/bpred { /testbench/dut/core/ifu/bpred/bpred/PostSpillInstrRawF[11:7]} rd +quietly WaveActivateNextPane {} 0 +add wave -noupdate /testbench/clk +add wave -noupdate /testbench/reset +add wave -noupdate /testbench/reset_ext +add wave -noupdate /testbench/memfilename +add wave -noupdate /testbench/dut/core/SATP_REGW +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM +add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/MDUStallD +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM +add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallF +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallD +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW +add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrD +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrE +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrM +add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCNextF +add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCF +add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCD +add wave -noupdate -expand -group PCS /testbench/dut/core/PCE +add wave -noupdate -expand -group PCS /testbench/dut/core/PCM +add wave -noupdate -expand -group PCS /testbench/PCW +add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD +add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD +add wave -noupdate -group {Decode Stage} /testbench/InstrDName +add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/InstrValidD +add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD +add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD +add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D +add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D +add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE +add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE +add wave -noupdate -group {Execution Stage} /testbench/InstrEName +add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE +add wave -noupdate -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM +add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM +add wave -noupdate -group {WriteBack stage} /testbench/PCW +add wave -noupdate -group {WriteBack stage} /testbench/InstrW +add wave -noupdate -group {WriteBack stage} /testbench/InstrWName +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MCAUSE_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEPC_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIDELEG_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIE_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW +add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW +add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW +add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW +add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS +add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check} +add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF +add wave -noupdate -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE +add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE +add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE +add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE +add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE +add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE +add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE +add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE +add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE +add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF +add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE +add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF +add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F +add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/PCNext0F +add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext1F +add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredWrongE +add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf +add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1 +add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2 +add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a3 +add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd1 +add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd2 +add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/we3 +add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/wd3 +add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ReadDataW +add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/CSRReadValW +add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultSrcW +add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultW +add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/A +add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/B +add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/Result +add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/ALUControl +add wave -noupdate -group alu -divider internals +add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1D +add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2D +add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1E +add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2E +add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdE +add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdM +add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdW +add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/MemReadE +add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteM +add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteW +add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardAE +add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardBE +add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/LoadStallD +add wave -noupdate -group Forward /testbench/dut/core/ieu/dp/IFResultM +add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/ForwardAE +add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1E +add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdM +add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdW +add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE +add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE +add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE +add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUReq +add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUReq +add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSave +add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFURestore +add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUDisable +add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUDisable +add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSelect +add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUSelect +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST +add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHTRANS +add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHADDR +add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHBURST +add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHREADY +add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/HRDATA +add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUReq +add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHTRANS +add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHSIZE +add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHBURST +add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHADDR +add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/HRDATA +add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWRITE +add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWSTRB +add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWDATA +add wave -noupdate -group AHB -expand -group LSU -color Pink /testbench/dut/core/lsu/LSUHREADY +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HCLK +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESETn +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HREADY +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESP +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HADDR +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWDATA +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWRITE +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HSIZE +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS +add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM +add wave -noupdate -expand -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/FWriteDataM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK +add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW +add wave -noupdate -expand -group lsu -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrE +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrM +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr +add wave -noupdate -expand -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} +add wave -noupdate -expand -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay +add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn +add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CAdr +add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} +add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU +add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU +add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay +add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate +add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate +add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded +add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty +add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr +add wave -noupdate -expand -group lsu -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr +add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag +add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn +add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn +add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag +add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush +add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay +add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr +add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr +add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CAdr +add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU +add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU +add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn +add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine +add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr +add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay +add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay +add wave -noupdate -expand -group lsu -group dcache -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} +add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM[62]} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/we} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} +add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr +add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr +add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache +add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall +add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM +add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData +add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -expand -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit +add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr +add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck +add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord +add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWalk +add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/WalkerState +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWAdr +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PTE +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCFSpill +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/NextPageType +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PageType +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ValidNonLeafPTE +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCFSpill +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ITLBWriteF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWriteM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSULoadAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSUStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWInstrAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LoadAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/StoreAmoAccessFaultM +add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr +add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr +add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/MExtInt +add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/SExtInt +add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/Dout +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intClaim +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intEn +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intInProgress +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intPending +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intPriority +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intThreshold +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/nextIntPending +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/requests +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/irqMatrix +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/priorities_with_irqs +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/max_priority_with_irqs +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/irqs_at_max_priority +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/threshMask +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsIn +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsOut +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsEn +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIntr +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSEL +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PADDR +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWRITE +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PRDATA +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PREADY +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWDATA +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSTRB +add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PENABLE +add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIME +add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIMECMP +add wave -noupdate -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PSEL +add wave -noupdate -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PADDR +add wave -noupdate -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PWDATA +add wave -noupdate -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PSTRB +add wave -noupdate -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PWRITE +add wave -noupdate -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PENABLE +add wave -noupdate -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PRDATA +add wave -noupdate -group CLINT -expand -group {clint bus} /testbench/dut/uncore/uncore/clint/clint/PREADY +add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/LSR +add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/MCR +add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/MSR +add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/RBR +add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/TXHR +add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uncore/uart/uart/u/LCR +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/intrID +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/INTR +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxstate +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/txstate +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/txbitssent +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/txbitsexpected +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxbitsreceived +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxbitsexpected +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxdata +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxoverrunerr +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxdataready +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxdataavailintr +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/RXBR +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/squashRXerrIP +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/rxshiftreg +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/SOUTbit +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/SINsync +add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/u/txsr +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/SIN +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/SOUT +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/RTSb +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DTRb +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/OUT1b +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/OUT2b +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DSRb +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/DCDb +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/CTSb +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/TXRDYb +add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uncore/uart/uart/RXRDYb +add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/core/FlushW +add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/PCM +add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM +add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW +add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F +add wave -noupdate -group ifu /testbench/dut/core/ifu/InstrRawF +add wave -noupdate -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF +add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUStallF +add wave -noupdate -group ifu -group Spill /testbench/dut/core/ifu/Spill/spill/CurrState +add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/SpillF +add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallD +add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissF +add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/InstrDAPageFaultF +add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF +add wave -noupdate -group ifu -group Spill /testbench/dut/core/ifu/SelNextSpillF +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR +add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush +add wave -noupdate -group ifu -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState +add wave -noupdate -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss +add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay +add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF +add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr +add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/RAM} +add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/bwe} +add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/dout} +add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/RAM} +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/VAdr +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/Matches +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/InstrPageFaultF +add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/TLBFlush +add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Valid} +add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/PageType} +add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key} +add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key0} +add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key1} +add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query0} +add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query1} +add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Valid} +add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageTypeWriteVal} +add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageType} +add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key} +add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key0} +add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1} +add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0} +add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1} +add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]} +add wave -noupdate -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]} +add wave -noupdate -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]} +add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP DIRECTION WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]} +add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]} +add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BTA/JTA WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]} +add wave -noupdate -group {Performance Counters} -expand -group BRP -label {JAL(R) INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]} +add wave -noupdate -group {Performance Counters} -expand -group BRP -label {RAS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]} +add wave -noupdate -group {Performance Counters} -expand -group BRP -label {RETURN INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]} +add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]} +add wave -noupdate -group {Performance Counters} -expand -group BRP -label {Branch Predictor Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]} +add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]} +add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]} +add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]} +add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]} +add wave -noupdate -group {ifu } -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState +add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/HREADY +add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/FetchBuffer +add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/CaptureEn +add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR +add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE +add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS +add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CacheBusAck +add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/VPN +add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/TLBWrite +add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/PTE +add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/VAdr +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/FRD1E +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/FRD2E +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/FRD3E +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcAE +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcBE +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/Funct3E +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/W64E +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/X +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/Y +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/Z +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/fregfile/rf +add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HADDR +add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HTRANS +add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HREADY +add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELRegions +add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELNoneD +add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELPLICD +add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HRDATA +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PopF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PushE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/RASPCF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/RepairD +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/rd +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PostSpillInstrRawF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BTBPredPCWrongM +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetWrongE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassD +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassD +add wave -noupdate -color Firebrick /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredWrongM +add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF +add wave -noupdate -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE +add wave -noupdate -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE +add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/TableDirPredictionF +add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF +add wave -noupdate -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionWrongE +add wave -noupdate -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM +add wave -noupdate -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushE +add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF +add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD +add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE +add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD +add wave -noupdate -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF +add wave -noupdate -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextD +add wave -noupdate -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextE +add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionE +add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE +add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM +add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/PCNextF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TableBTBPredictionF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredPCF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/SelBPPredF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredValidF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD +add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW +add wave -noupdate /testbench/dut/core/ifu/CSRWriteFenceM +add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/NextFFLAGSM +add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/WriteFFLAGSM +add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/InstrValidNotFlushedM +add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/CSRUWriteM +add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS +add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/CSRAdrM +add wave -noupdate /testbench/dut/core/ifu/PCLinkE +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {391801 ns} 1} {{Cursor 4} {1156601 ns} 1} {{Cursor 5} {497341 ns} 0} +quietly wave cursor active 5 +configure wave -namecolwidth 250 +configure wave -valuecolwidth 194 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {497212 ns} {497470 ns} diff --git a/pipelined/src/cache/cache.sv b/src/cache/cache.sv similarity index 100% rename from pipelined/src/cache/cache.sv rename to src/cache/cache.sv diff --git a/pipelined/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv similarity index 100% rename from pipelined/src/cache/cacheLRU.sv rename to src/cache/cacheLRU.sv diff --git a/pipelined/src/cache/cachefsm.sv b/src/cache/cachefsm.sv similarity index 100% rename from pipelined/src/cache/cachefsm.sv rename to src/cache/cachefsm.sv diff --git a/pipelined/src/cache/cacheway.sv b/src/cache/cacheway.sv similarity index 100% rename from pipelined/src/cache/cacheway.sv rename to src/cache/cacheway.sv diff --git a/pipelined/src/cache/subcachelineread.sv b/src/cache/subcachelineread.sv similarity index 100% rename from pipelined/src/cache/subcachelineread.sv rename to src/cache/subcachelineread.sv diff --git a/pipelined/src/ebu/ahbcacheinterface.sv b/src/ebu/ahbcacheinterface.sv similarity index 100% rename from pipelined/src/ebu/ahbcacheinterface.sv rename to src/ebu/ahbcacheinterface.sv diff --git a/pipelined/src/ebu/ahbinterface.sv b/src/ebu/ahbinterface.sv similarity index 100% rename from pipelined/src/ebu/ahbinterface.sv rename to src/ebu/ahbinterface.sv diff --git a/pipelined/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv similarity index 97% rename from pipelined/src/ebu/buscachefsm.sv rename to src/ebu/buscachefsm.sv index 8467f3029..2f3e99228 100644 --- a/pipelined/src/ebu/buscachefsm.sv +++ b/src/ebu/buscachefsm.sv @@ -116,7 +116,7 @@ module buscachefsm #( assign CaptureEn = (CurrState == DATA_PHASE & BusRW[1]) | (CurrState == CACHE_FETCH & HREADY); assign CacheAccess = CurrState == CACHE_FETCH | CurrState == CACHE_WRITEBACK; - assign BusStall = (CurrState == ADR_PHASE & (|BusRW | |CacheBusRW)) | + assign BusStall = (CurrState == ADR_PHASE & ((|BusRW) | (|CacheBusRW))) | //(CurrState == DATA_PHASE & ~BusRW[0]) | // *** replace the next line with this. Fails uart test but i think it's a test problem not a hardware problem. (CurrState == DATA_PHASE) | (CurrState == CACHE_FETCH & ~HREADY) | @@ -124,7 +124,7 @@ module buscachefsm #( assign BusCommitted = CurrState != ADR_PHASE; // AHB bus interface - assign HTRANS = (CurrState == ADR_PHASE & HREADY & (|BusRW | |CacheBusRW) & ~Flush) | + assign HTRANS = (CurrState == ADR_PHASE & HREADY & ((|BusRW) | (|CacheBusRW)) & ~Flush) | (CacheAccess & FinalBeatCount & |CacheBusRW & HREADY) ? AHB_NONSEQ : // if we have a pipelined request (CacheAccess & |BeatCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE; diff --git a/pipelined/src/ebu/busfsm.sv b/src/ebu/busfsm.sv similarity index 100% rename from pipelined/src/ebu/busfsm.sv rename to src/ebu/busfsm.sv diff --git a/pipelined/src/ebu/controllerinputstage.sv b/src/ebu/controllerinputstage.sv similarity index 100% rename from pipelined/src/ebu/controllerinputstage.sv rename to src/ebu/controllerinputstage.sv diff --git a/pipelined/src/ebu/ebu.sv b/src/ebu/ebu.sv similarity index 100% rename from pipelined/src/ebu/ebu.sv rename to src/ebu/ebu.sv diff --git a/pipelined/src/ebu/ebuarbfsm.sv b/src/ebu/ebuarbfsm.sv similarity index 100% rename from pipelined/src/ebu/ebuarbfsm.sv rename to src/ebu/ebuarbfsm.sv diff --git a/pipelined/src/fpu/fclassify.sv b/src/fpu/fclassify.sv similarity index 100% rename from pipelined/src/fpu/fclassify.sv rename to src/fpu/fclassify.sv diff --git a/pipelined/src/fpu/fcmp.sv b/src/fpu/fcmp.sv similarity index 100% rename from pipelined/src/fpu/fcmp.sv rename to src/fpu/fcmp.sv diff --git a/pipelined/src/fpu/fctrl.sv b/src/fpu/fctrl.sv similarity index 100% rename from pipelined/src/fpu/fctrl.sv rename to src/fpu/fctrl.sv diff --git a/pipelined/src/fpu/fcvt.sv b/src/fpu/fcvt.sv similarity index 100% rename from pipelined/src/fpu/fcvt.sv rename to src/fpu/fcvt.sv diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/src/fpu/fdivsqrt/fdivsqrt.sv similarity index 100% rename from pipelined/src/fpu/fdivsqrt/fdivsqrt.sv rename to src/fpu/fdivsqrt/fdivsqrt.sv diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv similarity index 100% rename from pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv rename to src/fpu/fdivsqrt/fdivsqrtexpcalc.sv diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv similarity index 100% rename from pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv rename to src/fpu/fdivsqrt/fdivsqrtfgen2.sv diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv similarity index 100% rename from pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv rename to src/fpu/fdivsqrt/fdivsqrtfgen4.sv diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/src/fpu/fdivsqrt/fdivsqrtfsm.sv similarity index 100% rename from pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv rename to src/fpu/fdivsqrt/fdivsqrtfsm.sv diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv b/src/fpu/fdivsqrt/fdivsqrtiter.sv similarity index 100% rename from pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv rename to src/fpu/fdivsqrt/fdivsqrtiter.sv diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv similarity index 100% rename from pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv rename to src/fpu/fdivsqrt/fdivsqrtpostproc.sv diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv similarity index 100% rename from pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv rename to src/fpu/fdivsqrt/fdivsqrtpreproc.sv diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv b/src/fpu/fdivsqrt/fdivsqrtqsel2.sv similarity index 100% rename from pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv rename to src/fpu/fdivsqrt/fdivsqrtqsel2.sv diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv b/src/fpu/fdivsqrt/fdivsqrtqsel4.sv similarity index 100% rename from pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv rename to src/fpu/fdivsqrt/fdivsqrtqsel4.sv diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv b/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv similarity index 100% rename from pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv rename to src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv b/src/fpu/fdivsqrt/fdivsqrtstage2.sv similarity index 100% rename from pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv rename to src/fpu/fdivsqrt/fdivsqrtstage2.sv diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/src/fpu/fdivsqrt/fdivsqrtstage4.sv similarity index 100% rename from pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv rename to src/fpu/fdivsqrt/fdivsqrtstage4.sv diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv similarity index 100% rename from pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv rename to src/fpu/fdivsqrt/fdivsqrtuotfc2.sv diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv similarity index 100% rename from pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv rename to src/fpu/fdivsqrt/fdivsqrtuotfc4.sv diff --git a/pipelined/src/fpu/fhazard.sv b/src/fpu/fhazard.sv similarity index 100% rename from pipelined/src/fpu/fhazard.sv rename to src/fpu/fhazard.sv diff --git a/pipelined/src/fpu/fma/fma.sv b/src/fpu/fma/fma.sv similarity index 100% rename from pipelined/src/fpu/fma/fma.sv rename to src/fpu/fma/fma.sv diff --git a/pipelined/src/fpu/fma/fmaadd.sv b/src/fpu/fma/fmaadd.sv similarity index 100% rename from pipelined/src/fpu/fma/fmaadd.sv rename to src/fpu/fma/fmaadd.sv diff --git a/pipelined/src/fpu/fma/fmaalign.sv b/src/fpu/fma/fmaalign.sv similarity index 100% rename from pipelined/src/fpu/fma/fmaalign.sv rename to src/fpu/fma/fmaalign.sv diff --git a/pipelined/src/fpu/fma/fmaexpadd.sv b/src/fpu/fma/fmaexpadd.sv similarity index 100% rename from pipelined/src/fpu/fma/fmaexpadd.sv rename to src/fpu/fma/fmaexpadd.sv diff --git a/pipelined/src/fpu/fma/fmalza.sv b/src/fpu/fma/fmalza.sv similarity index 100% rename from pipelined/src/fpu/fma/fmalza.sv rename to src/fpu/fma/fmalza.sv diff --git a/pipelined/src/fpu/fma/fmamult.sv b/src/fpu/fma/fmamult.sv similarity index 100% rename from pipelined/src/fpu/fma/fmamult.sv rename to src/fpu/fma/fmamult.sv diff --git a/pipelined/src/fpu/fma/fmasign.sv b/src/fpu/fma/fmasign.sv similarity index 100% rename from pipelined/src/fpu/fma/fmasign.sv rename to src/fpu/fma/fmasign.sv diff --git a/pipelined/src/fpu/fpu.sv b/src/fpu/fpu.sv similarity index 100% rename from pipelined/src/fpu/fpu.sv rename to src/fpu/fpu.sv diff --git a/pipelined/src/fpu/fregfile.sv b/src/fpu/fregfile.sv similarity index 100% rename from pipelined/src/fpu/fregfile.sv rename to src/fpu/fregfile.sv diff --git a/pipelined/src/fpu/fsgninj.sv b/src/fpu/fsgninj.sv similarity index 85% rename from pipelined/src/fpu/fsgninj.sv rename to src/fpu/fsgninj.sv index d5568cabe..0db7dc2f3 100755 --- a/pipelined/src/fpu/fsgninj.sv +++ b/src/fpu/fsgninj.sv @@ -29,11 +29,11 @@ `include "wally-config.vh" module fsgninj ( - input logic Xs, Ys, // X and Y sign bits - input logic [`FLEN-1:0] X, // X - input logic [`FMTBITS-1:0] Fmt, // format - input logic [1:0] OpCtrl, // operation control - output logic [`FLEN-1:0] SgnRes // result + input logic Xs, Ys, // X and Y sign bits + input logic [`FLEN-1:0] X, // X + input logic [`FMTBITS-1:0] Fmt, // format + input logic [1:0] OpCtrl, // operation control + output logic [`FLEN-1:0] SgnRes // result ); logic ResSgn; // result sign @@ -54,13 +54,13 @@ module fsgninj ( assign SgnRes = {ResSgn, X[`FLEN-2:0]}; else if (`FPSIZES == 2) assign SgnRes = {~Fmt|ResSgn, X[`FLEN-2:`LEN1], Fmt ? X[`LEN1-1] : ResSgn, X[`LEN1-2:0]}; - else if (`FPSIZES == 3) begin + else if (`FPSIZES == 3) begin logic [2:0] SgnBits; always_comb case (Fmt) - `FMT: SgnBits = {ResSgn, X[`LEN1-1], X[`LEN2-1]}; - `FMT1: SgnBits = {1'b1, ResSgn, X[`LEN2-1]}; - `FMT2: SgnBits = {2'b11, ResSgn}; + `FMT: SgnBits = {ResSgn, X[`LEN1-1], X[`LEN2-1]}; + `FMT1: SgnBits = {1'b1, ResSgn, X[`LEN2-1]}; + `FMT2: SgnBits = {2'b11, ResSgn}; default: SgnBits = {3{1'bx}}; endcase assign SgnRes = {SgnBits[2], X[`FLEN-2:`LEN1], SgnBits[1], X[`LEN1-2:`LEN2], SgnBits[0], X[`LEN2-2:0]}; diff --git a/pipelined/src/fpu/postproc/cvtshiftcalc.sv b/src/fpu/postproc/cvtshiftcalc.sv similarity index 100% rename from pipelined/src/fpu/postproc/cvtshiftcalc.sv rename to src/fpu/postproc/cvtshiftcalc.sv diff --git a/pipelined/src/fpu/postproc/divshiftcalc.sv b/src/fpu/postproc/divshiftcalc.sv similarity index 100% rename from pipelined/src/fpu/postproc/divshiftcalc.sv rename to src/fpu/postproc/divshiftcalc.sv diff --git a/pipelined/src/fpu/postproc/flags.sv b/src/fpu/postproc/flags.sv similarity index 100% rename from pipelined/src/fpu/postproc/flags.sv rename to src/fpu/postproc/flags.sv diff --git a/pipelined/src/fpu/postproc/fmashiftcalc.sv b/src/fpu/postproc/fmashiftcalc.sv similarity index 100% rename from pipelined/src/fpu/postproc/fmashiftcalc.sv rename to src/fpu/postproc/fmashiftcalc.sv diff --git a/pipelined/src/fpu/postproc/negateintres.sv b/src/fpu/postproc/negateintres.sv similarity index 100% rename from pipelined/src/fpu/postproc/negateintres.sv rename to src/fpu/postproc/negateintres.sv diff --git a/pipelined/src/fpu/postproc/normshift.sv b/src/fpu/postproc/normshift.sv similarity index 100% rename from pipelined/src/fpu/postproc/normshift.sv rename to src/fpu/postproc/normshift.sv diff --git a/pipelined/src/fpu/postproc/postprocess.sv b/src/fpu/postproc/postprocess.sv similarity index 100% rename from pipelined/src/fpu/postproc/postprocess.sv rename to src/fpu/postproc/postprocess.sv diff --git a/pipelined/src/fpu/postproc/resultsign.sv b/src/fpu/postproc/resultsign.sv similarity index 100% rename from pipelined/src/fpu/postproc/resultsign.sv rename to src/fpu/postproc/resultsign.sv diff --git a/pipelined/src/fpu/postproc/round.sv b/src/fpu/postproc/round.sv similarity index 100% rename from pipelined/src/fpu/postproc/round.sv rename to src/fpu/postproc/round.sv diff --git a/pipelined/src/fpu/postproc/roundsign.sv b/src/fpu/postproc/roundsign.sv similarity index 100% rename from pipelined/src/fpu/postproc/roundsign.sv rename to src/fpu/postproc/roundsign.sv diff --git a/pipelined/src/fpu/postproc/shiftcorrection.sv b/src/fpu/postproc/shiftcorrection.sv similarity index 100% rename from pipelined/src/fpu/postproc/shiftcorrection.sv rename to src/fpu/postproc/shiftcorrection.sv diff --git a/pipelined/src/fpu/postproc/specialcase.sv b/src/fpu/postproc/specialcase.sv similarity index 100% rename from pipelined/src/fpu/postproc/specialcase.sv rename to src/fpu/postproc/specialcase.sv diff --git a/pipelined/src/fpu/unpack.sv b/src/fpu/unpack.sv similarity index 94% rename from pipelined/src/fpu/unpack.sv rename to src/fpu/unpack.sv index 13addc2e3..356d7e897 100644 --- a/pipelined/src/fpu/unpack.sv +++ b/src/fpu/unpack.sv @@ -48,15 +48,14 @@ module unpack ( unpackinput unpackinputX (.In(X), .Fmt, .Sgn(Xs), .Exp(Xe), .Man(Xm), .En(XEn), .NaN(XNaN), .SNaN(XSNaN), .ExpNonZero(XExpNonZero), - .Zero(XZero), .Inf(XInf), .ExpMax(XExpMax), .FracZero(XFracZero)); + .Zero(XZero), .Inf(XInf), .ExpMax(XExpMax), .FracZero(XFracZero), .Subnorm(XSubnorm)); unpackinput unpackinputY (.In(Y), .Fmt, .Sgn(Ys), .Exp(Ye), .Man(Ym), .En(YEn), .NaN(YNaN), .SNaN(YSNaN), .ExpNonZero(YExpNonZero), - .Zero(YZero), .Inf(YInf), .ExpMax(YExpMax), .FracZero(YFracZero)); + .Zero(YZero), .Inf(YInf), .ExpMax(YExpMax), .FracZero(YFracZero), .Subnorm()); unpackinput unpackinputZ (.In(Z), .Fmt, .Sgn(Zs), .Exp(Ze), .Man(Zm), .En(ZEn), .NaN(ZNaN), .SNaN(ZSNaN), .ExpNonZero(ZExpNonZero), - .Zero(ZZero), .Inf(ZInf), .ExpMax(ZExpMax), .FracZero(ZFracZero)); - // is the input subnormal - assign XSubnorm = ~XExpNonZero & ~XFracZero; -endmodule \ No newline at end of file + .Zero(ZZero), .Inf(ZInf), .ExpMax(ZExpMax), .FracZero(ZFracZero), .Subnorm()); + + endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/unpackinput.sv b/src/fpu/unpackinput.sv similarity index 90% rename from pipelined/src/fpu/unpackinput.sv rename to src/fpu/unpackinput.sv index 34663bd8c..68f98e900 100644 --- a/pipelined/src/fpu/unpackinput.sv +++ b/src/fpu/unpackinput.sv @@ -31,16 +31,17 @@ module unpackinput ( input logic [`FLEN-1:0] In, // inputs from register file input logic En, // enable the input input logic [`FMTBITS-1:0] Fmt, // format signal 00 - single 01 - double 11 - quad 10 - half - output logic Sgn, // sign bits of XYZ - output logic [`NE-1:0] Exp, // exponents of XYZ (converted to largest supported precision) - output logic [`NF:0] Man, // mantissas of XYZ (converted to largest supported precision) - output logic NaN, // is XYZ a NaN - output logic SNaN, // is XYZ a signaling NaN - output logic Zero, // is XYZ zero - output logic Inf, // is XYZ infinity + output logic Sgn, // sign bits of the number + output logic [`NE-1:0] Exp, // exponent of the number (converted to largest supported precision) + output logic [`NF:0] Man, // mantissa of the number (converted to largest supported precision) + output logic NaN, // is the number a NaN + output logic SNaN, // is the number a signaling NaN + output logic Zero, // is the number zero + output logic Inf, // is the number infinity output logic ExpNonZero, // is the exponent not zero output logic FracZero, // is the fraction zero - output logic ExpMax // does In have the maximum exponent (NaN or Inf) + output logic ExpMax, // does In have the maximum exponent (NaN or Inf) + output logic Subnorm // is the number subnormal ); logic [`NF-1:0] Frac; // Fraction of XYZ @@ -55,7 +56,6 @@ module unpackinput ( assign ExpMax = &In[`FLEN-2:`NF]; // is the exponent all 1's end else if (`FPSIZES == 2) begin // if there are 2 floating point formats supported - //***need better names for these constants // largest format | smaller format //---------------------------------- // `FLEN | `LEN1 length of floating point number @@ -103,7 +103,6 @@ module unpackinput ( end else if (`FPSIZES == 3) begin // three floating point precsions supported - //***need better names for these constants // largest format | larger format | smallest format //--------------------------------------------------- // `FLEN | `LEN1 | `LEN2 length of floating point number @@ -195,7 +194,7 @@ module unpackinput ( // Check NaN boxing always_comb case (Fmt) - 2'b11: BadNaNBox = 0; + 2'b11: BadNaNBox = 0; 2'b01: BadNaNBox = ~&In[`Q_LEN-1:`D_LEN]; 2'b00: BadNaNBox = ~&In[`Q_LEN-1:`S_LEN]; 2'b10: BadNaNBox = ~&In[`Q_LEN-1:`H_LEN]; @@ -261,10 +260,12 @@ module unpackinput ( end // Output logic - assign FracZero = ~|Frac; // is the fraction zero? + assign FracZero = ~|Frac & ~BadNaNBox; // is the fraction zero? assign Man = {ExpNonZero, Frac}; // add the assumed one (or zero if Subnormal or zero) to create the significand assign NaN = ((ExpMax & ~FracZero)|BadNaNBox)&En; // is the input a NaN? assign SNaN = NaN&~Frac[`NF-1]&~BadNaNBox; // is the input a singnaling NaN? - assign Inf = ExpMax & FracZero &En; // is the input infinity? - assign Zero = ~ExpNonZero & FracZero; // is the input zero? + assign Inf = ExpMax & FracZero &En & ~BadNaNBox; // is the input infinity? + assign Zero = ~ExpNonZero & FracZero & ~BadNaNBox; // is the input zero? + assign Subnorm = ~ExpNonZero & ~FracZero & ~BadNaNBox; // is the input subnormal + endmodule \ No newline at end of file diff --git a/pipelined/src/generic/adder.sv b/src/generic/adder.sv similarity index 100% rename from pipelined/src/generic/adder.sv rename to src/generic/adder.sv diff --git a/pipelined/src/generic/aplusbeq0.sv b/src/generic/aplusbeq0.sv similarity index 100% rename from pipelined/src/generic/aplusbeq0.sv rename to src/generic/aplusbeq0.sv diff --git a/pipelined/src/generic/arrs.sv b/src/generic/arrs.sv similarity index 100% rename from pipelined/src/generic/arrs.sv rename to src/generic/arrs.sv diff --git a/pipelined/src/generic/binencoder.sv b/src/generic/binencoder.sv similarity index 100% rename from pipelined/src/generic/binencoder.sv rename to src/generic/binencoder.sv diff --git a/pipelined/src/generic/clockgater.sv b/src/generic/clockgater.sv similarity index 100% rename from pipelined/src/generic/clockgater.sv rename to src/generic/clockgater.sv diff --git a/pipelined/src/generic/counter.sv b/src/generic/counter.sv similarity index 100% rename from pipelined/src/generic/counter.sv rename to src/generic/counter.sv diff --git a/pipelined/src/generic/csa.sv b/src/generic/csa.sv similarity index 100% rename from pipelined/src/generic/csa.sv rename to src/generic/csa.sv diff --git a/pipelined/src/generic/decoder.sv b/src/generic/decoder.sv similarity index 100% rename from pipelined/src/generic/decoder.sv rename to src/generic/decoder.sv diff --git a/pipelined/src/generic/flop/flop.sv b/src/generic/flop/flop.sv similarity index 100% rename from pipelined/src/generic/flop/flop.sv rename to src/generic/flop/flop.sv diff --git a/pipelined/src/generic/flop/flopen.sv b/src/generic/flop/flopen.sv similarity index 100% rename from pipelined/src/generic/flop/flopen.sv rename to src/generic/flop/flopen.sv diff --git a/pipelined/src/generic/flop/flopenl.sv b/src/generic/flop/flopenl.sv similarity index 100% rename from pipelined/src/generic/flop/flopenl.sv rename to src/generic/flop/flopenl.sv diff --git a/pipelined/src/generic/flop/flopenr.sv b/src/generic/flop/flopenr.sv similarity index 100% rename from pipelined/src/generic/flop/flopenr.sv rename to src/generic/flop/flopenr.sv diff --git a/pipelined/src/generic/flop/flopenrc.sv b/src/generic/flop/flopenrc.sv similarity index 100% rename from pipelined/src/generic/flop/flopenrc.sv rename to src/generic/flop/flopenrc.sv diff --git a/pipelined/src/generic/flop/flopens.sv b/src/generic/flop/flopens.sv similarity index 100% rename from pipelined/src/generic/flop/flopens.sv rename to src/generic/flop/flopens.sv diff --git a/pipelined/src/generic/flop/flopr.sv b/src/generic/flop/flopr.sv similarity index 100% rename from pipelined/src/generic/flop/flopr.sv rename to src/generic/flop/flopr.sv diff --git a/pipelined/src/generic/flop/floprc.sv b/src/generic/flop/floprc.sv similarity index 100% rename from pipelined/src/generic/flop/floprc.sv rename to src/generic/flop/floprc.sv diff --git a/pipelined/src/generic/flop/synchronizer.sv b/src/generic/flop/synchronizer.sv similarity index 100% rename from pipelined/src/generic/flop/synchronizer.sv rename to src/generic/flop/synchronizer.sv diff --git a/pipelined/src/generic/lzc.sv b/src/generic/lzc.sv similarity index 97% rename from pipelined/src/generic/lzc.sv rename to src/generic/lzc.sv index 60719c494..ecfd6796a 100644 --- a/pipelined/src/generic/lzc.sv +++ b/src/generic/lzc.sv @@ -33,6 +33,6 @@ module lzc #(parameter WIDTH = 1) ( always_comb begin i = 0; while (~num[WIDTH-1-i] & (i < WIDTH)) i = i+1; // search for leading one - ZeroCnt = i[$clog2(WIDTH)-1:0]; + ZeroCnt = i[$clog2(WIDTH+1)-1:0]; end endmodule diff --git a/pipelined/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv similarity index 92% rename from pipelined/src/generic/mem/ram1p1rwbe.sv rename to src/generic/mem/ram1p1rwbe.sv index e33e708a3..f1e784c13 100644 --- a/pipelined/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -55,10 +55,10 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) ( logic [WIDTH-1:0] BitWriteMask; for (index=0; index < WIDTH; index++) assign BitWriteMask[index] = bwe[index/8]; - TS1N28HPCPSVTB64X128M4SW sram1A (.CLK(clk), .CEB(~ce), .WEB(~we), + ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we), .A(addr), .D(din), .BWEB(~BitWriteMask), .Q(dout)); - + end else if (`USE_SRAM == 1 && WIDTH == 44 && DEPTH == 64) begin genvar index; // 64 x 44-bit SRAM @@ -69,15 +69,15 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) ( .A(addr), .D(din), .BWEB(~BitWriteMask), .Q(dout)); - end if (`USE_SRAM == 1 && WIDTH == 128 && DEPTH == 32) begin + end else if (`USE_SRAM == 1 && WIDTH == 128 && DEPTH == 32) begin genvar index; // 64 x 128-bit SRAM logic [WIDTH-1:0] BitWriteMask; for (index=0; index < WIDTH; index++) assign BitWriteMask[index] = bwe[index/8]; - TS1N28HPCPSVTB64X128M4SW sram1A (.CLK(clk), .CEB(~ce), .WEB(~we), - .A(addr), .D(din), - .BWEB(~BitWriteMask), .Q(dout)); + ram1p1rwbe_128x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we), + .A(addr), .D(din), + .BWEB(~BitWriteMask), .Q(dout)); end else if (`USE_SRAM == 1 && WIDTH == 22 && DEPTH == 32) begin genvar index; @@ -85,7 +85,7 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) ( logic [WIDTH-1:0] BitWriteMask; for (index=0; index < WIDTH; index++) assign BitWriteMask[index] = bwe[index/8]; - ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we), + ram1p1rwbe_64x22 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we), .A(addr), .D(din), .BWEB(~BitWriteMask), .Q(dout)); diff --git a/pipelined/src/generic/mem/ram1p1rwbe_64x128.sv b/src/generic/mem/ram1p1rwbe_64x128.sv similarity index 100% rename from pipelined/src/generic/mem/ram1p1rwbe_64x128.sv rename to src/generic/mem/ram1p1rwbe_64x128.sv diff --git a/pipelined/src/generic/mem/ram1p1rwbe_64x22.sv b/src/generic/mem/ram1p1rwbe_64x22.sv similarity index 100% rename from pipelined/src/generic/mem/ram1p1rwbe_64x22.sv rename to src/generic/mem/ram1p1rwbe_64x22.sv diff --git a/pipelined/src/generic/mem/ram1p1rwbe_64x44.sv b/src/generic/mem/ram1p1rwbe_64x44.sv similarity index 100% rename from pipelined/src/generic/mem/ram1p1rwbe_64x44.sv rename to src/generic/mem/ram1p1rwbe_64x44.sv diff --git a/pipelined/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv similarity index 98% rename from pipelined/src/generic/mem/ram2p1r1wbe.sv rename to src/generic/mem/ram2p1r1wbe.sv index 08c232bba..da099cdc7 100644 --- a/pipelined/src/generic/mem/ram2p1r1wbe.sv +++ b/src/generic/mem/ram2p1r1wbe.sv @@ -64,7 +64,7 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) ( .QA(rd1), .QB()); - end if (`USE_SRAM == 1 && WIDTH == 36 && DEPTH == 1024) begin + end else if (`USE_SRAM == 1 && WIDTH == 36 && DEPTH == 1024) begin ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk), .CEBA(~ce1), .CEBB(~ce2), diff --git a/pipelined/src/generic/mem/ram2p1r1wbe_1024x36.sv b/src/generic/mem/ram2p1r1wbe_1024x36.sv similarity index 100% rename from pipelined/src/generic/mem/ram2p1r1wbe_1024x36.sv rename to src/generic/mem/ram2p1r1wbe_1024x36.sv diff --git a/pipelined/src/generic/mem/ram2p1r1wbe_1024x68.sv b/src/generic/mem/ram2p1r1wbe_1024x68.sv similarity index 100% rename from pipelined/src/generic/mem/ram2p1r1wbe_1024x68.sv rename to src/generic/mem/ram2p1r1wbe_1024x68.sv diff --git a/pipelined/src/generic/mem/ram2p1r1wbe_64x32.sv b/src/generic/mem/ram2p1r1wbe_64x32.sv similarity index 100% rename from pipelined/src/generic/mem/ram2p1r1wbe_64x32.sv rename to src/generic/mem/ram2p1r1wbe_64x32.sv diff --git a/pipelined/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv similarity index 100% rename from pipelined/src/generic/mem/rom1p1r.sv rename to src/generic/mem/rom1p1r.sv diff --git a/pipelined/src/generic/mem/rom1p1r_128x32.sv b/src/generic/mem/rom1p1r_128x32.sv similarity index 100% rename from pipelined/src/generic/mem/rom1p1r_128x32.sv rename to src/generic/mem/rom1p1r_128x32.sv diff --git a/pipelined/src/generic/mem/rom1p1r_128x64.sv b/src/generic/mem/rom1p1r_128x64.sv similarity index 100% rename from pipelined/src/generic/mem/rom1p1r_128x64.sv rename to src/generic/mem/rom1p1r_128x64.sv diff --git a/pipelined/src/generic/mux.sv b/src/generic/mux.sv similarity index 100% rename from pipelined/src/generic/mux.sv rename to src/generic/mux.sv diff --git a/pipelined/src/generic/neg.sv b/src/generic/neg.sv similarity index 100% rename from pipelined/src/generic/neg.sv rename to src/generic/neg.sv diff --git a/pipelined/src/generic/onehotdecoder.sv b/src/generic/onehotdecoder.sv similarity index 100% rename from pipelined/src/generic/onehotdecoder.sv rename to src/generic/onehotdecoder.sv diff --git a/pipelined/src/generic/or_rows.sv b/src/generic/or_rows.sv similarity index 100% rename from pipelined/src/generic/or_rows.sv rename to src/generic/or_rows.sv diff --git a/pipelined/src/generic/priorityonehot.sv b/src/generic/priorityonehot.sv similarity index 100% rename from pipelined/src/generic/priorityonehot.sv rename to src/generic/priorityonehot.sv diff --git a/pipelined/src/generic/prioritythermometer.sv b/src/generic/prioritythermometer.sv similarity index 100% rename from pipelined/src/generic/prioritythermometer.sv rename to src/generic/prioritythermometer.sv diff --git a/pipelined/src/hazard/hazard.sv b/src/hazard/hazard.sv similarity index 100% rename from pipelined/src/hazard/hazard.sv rename to src/hazard/hazard.sv diff --git a/pipelined/src/ieu/alu.sv b/src/ieu/alu.sv similarity index 100% rename from pipelined/src/ieu/alu.sv rename to src/ieu/alu.sv diff --git a/pipelined/src/ieu/comparator.sv b/src/ieu/comparator.sv similarity index 100% rename from pipelined/src/ieu/comparator.sv rename to src/ieu/comparator.sv diff --git a/pipelined/src/ieu/controller.sv b/src/ieu/controller.sv similarity index 98% rename from pipelined/src/ieu/controller.sv rename to src/ieu/controller.sv index 1819de17c..d66425343 100644 --- a/pipelined/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -62,7 +62,10 @@ module controller( output logic [2:0] Funct3M, // Instruction's funct3 field output logic RegWriteM, // Instruction writes a register (needed for Hazard unit) output logic InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$ - output logic InstrValidM, // Instruction is valid + output logic InstrValidD, InstrValidE, InstrValidM, // Instruction is valid + output logic BranchD, BranchE, + output logic JumpD, + output logic FWriteIntM, // FPU controller writes integer register file // Writeback stage control signals input logic StallW, FlushW, // Stall, flush Writeback stage @@ -84,8 +87,6 @@ module controller( logic RegWriteD, RegWriteE; // RegWrite (register will be written) logic [2:0] ResultSrcD, ResultSrcE, ResultSrcM; // Select which result to write back to register file logic [1:0] MemRWD, MemRWE; // Store (write to memory) - logic JumpD; // Jump instruction - logic BranchD, BranchE; // Branch instruction logic ALUOpD; // 0 for address generation, 1 for all other operations (must use Funct3) logic [2:0] ALUControlD; // Determines ALU operation logic ALUSrcAD, ALUSrcBD; // ALU inputs @@ -96,7 +97,6 @@ module controller( logic FenceXD; // Fence instruction logic InvalidateICacheD, FlushDCacheD;// Invalidate I$, flush D$ logic CSRWriteD, CSRWriteE; // CSR write - logic InstrValidD, InstrValidE; // Instruction is valid logic PrivilegedD, PrivilegedE; // Privileged instruction logic InvalidateICacheE, FlushDCacheE;// Invalidate I$, flush D$ logic [`CTRLW-1:0] ControlsD; // Main Instruction Decoder control signals diff --git a/pipelined/src/ieu/datapath.sv b/src/ieu/datapath.sv similarity index 100% rename from pipelined/src/ieu/datapath.sv rename to src/ieu/datapath.sv diff --git a/pipelined/src/ieu/extend.sv b/src/ieu/extend.sv similarity index 100% rename from pipelined/src/ieu/extend.sv rename to src/ieu/extend.sv diff --git a/pipelined/src/ieu/forward.sv b/src/ieu/forward.sv similarity index 100% rename from pipelined/src/ieu/forward.sv rename to src/ieu/forward.sv diff --git a/pipelined/src/ieu/ieu.sv b/src/ieu/ieu.sv similarity index 95% rename from pipelined/src/ieu/ieu.sv rename to src/ieu/ieu.sv index 681bd9826..9d3a833e9 100644 --- a/pipelined/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -54,7 +54,9 @@ module ieu ( output logic [4:0] RdM, // Destination register input logic [`XLEN-1:0] FIntResM, // Integer result from FPU (fmv, fclass, fcmp) output logic InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$ - output logic InstrValidM, // Instruction is valid + output logic InstrValidD, InstrValidE, InstrValidM,// Instruction is valid + output logic BranchD, BranchE, + output logic JumpD, JumpE, // Writeback stage signals input logic [`XLEN-1:0] FIntDivResultW, // Integer divide result from FPU fdivsqrt) input logic [`XLEN-1:0] CSRReadValW, // CSR read value, @@ -87,7 +89,6 @@ module ieu ( logic [1:0] ForwardAE, ForwardBE; // Select signals for forwarding multiplexers logic RegWriteM, RegWriteW; // Register will be written in Memory, Writeback stages logic MemReadE, CSRReadE; // Load, CSRRead instruction - logic JumpE; // Jump instruction logic BranchSignedE; // Branch does signed comparison on operands logic MDUE; // Multiply/divide instruction @@ -95,9 +96,9 @@ module ieu ( .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, .StallE, .FlushE, .FlagsE, .FWriteIntE, .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .MemReadE, .CSRReadE, - .Funct3E, .IntDivE, .MDUE, .W64E, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM, + .Funct3E, .IntDivE, .MDUE, .W64E, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, - .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .FWriteIntM, + .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM, .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .StoreStallD); datapath dp( diff --git a/pipelined/src/ieu/regfile.sv b/src/ieu/regfile.sv similarity index 100% rename from pipelined/src/ieu/regfile.sv rename to src/ieu/regfile.sv diff --git a/pipelined/src/ieu/shifter.sv b/src/ieu/shifter.sv similarity index 100% rename from pipelined/src/ieu/shifter.sv rename to src/ieu/shifter.sv diff --git a/pipelined/src/ifu/CodeAligner.py b/src/ifu/CodeAligner.py similarity index 100% rename from pipelined/src/ifu/CodeAligner.py rename to src/ifu/CodeAligner.py diff --git a/pipelined/src/ifu/bpred/RASPredictor.sv b/src/ifu/bpred/RASPredictor.sv similarity index 86% rename from pipelined/src/ifu/bpred/RASPredictor.sv rename to src/ifu/bpred/RASPredictor.sv index f71cb48f4..330607af4 100644 --- a/pipelined/src/ifu/bpred/RASPredictor.sv +++ b/src/ifu/bpred/RASPredictor.sv @@ -34,7 +34,9 @@ module RASPredictor #(parameter int StackSize = 16 )( input logic reset, input logic StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM, input logic [3:0] WrongPredInstrClassD, // Prediction class is wrong - input logic [3:0] InstrClassD, InstrClassE, PredInstrClassF, // Instr class + input logic [3:0] InstrClassD, + input logic [3:0] InstrClassE, // Instr class + input logic [3:0] PredInstrClassF, input logic [`XLEN-1:0] PCLinkE, // PC of instruction after a jal output logic [`XLEN-1:0] RASPCF // Top of the stack ); @@ -42,7 +44,7 @@ module RASPredictor #(parameter int StackSize = 16 )( logic CounterEn; localparam Depth = $clog2(StackSize); - logic [Depth-1:0] NextPtr, CurrPtr, PtrP1, PtrM1; + logic [Depth-1:0] NextPtr, Ptr, P1, M1, IncDecPtr; logic [StackSize-1:0] [`XLEN-1:0] memory; integer index; @@ -71,12 +73,13 @@ module RASPredictor #(parameter int StackSize = 16 )( assign CounterEn = PopF | PushE | RepairD; assign DecrementPtr = (PopF | DecRepairD) & ~IncrRepairD; - mux2 #(Depth) PtrMux(PtrP1, PtrM1, DecrementPtr, NextPtr); - assign PtrM1 = CurrPtr - 1'b1; - assign PtrP1 = CurrPtr + 1'b1; + assign P1 = 1; + assign M1 = '1; // -1 + mux2 #(Depth) PtrMux(P1, M1, DecrementPtr, IncDecPtr); + assign NextPtr = Ptr + IncDecPtr; - flopenr #(Depth) PTR(clk, reset, CounterEn, NextPtr, CurrPtr); + flopenr #(Depth) PTR(clk, reset, CounterEn, NextPtr, Ptr); // RAS must be reset. always_ff @ (posedge clk) begin @@ -84,14 +87,11 @@ module RASPredictor #(parameter int StackSize = 16 )( for(index=0; index $(TARGET).elf.objdump + +$(TARGET).elf: $(TARGET).S Makefile + riscv64-unknown-elf-gcc -g -o $(TARGET).elf -march=rv64gc -mabi=lp64 -mcmodel=medany \ + -nostartfiles -T$(WALLY)/examples/link/link.ld $(TARGET).S + + +clean: + rm -f $(TARGET).elf $(TARGET).elf.* *.signature.output + + + diff --git a/tests/custom/debug/debug.S b/tests/custom/debug/debug.S new file mode 100644 index 000000000..5be3c2012 --- /dev/null +++ b/tests/custom/debug/debug.S @@ -0,0 +1,59 @@ +// debug.S +// David_Harris@hmc.edu 4 February 2023 +// Small code snippets for the purpose of debugging issues +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +.global rvtest_entry_point +rvtest_entry_point: + lui t0, 0x1e # turn on Floating point and XS + csrs mstatus, t0 + + # openhwgroup/cvw Issue #55 + la a6, begin_signature + la a7, rvtest_data + fadd.d ft0, ft1, ft2 + fld f4, 0(a7) + fld f9, 8(a7) +# li x1, 0x7ff0000000000001 +# sd x1, 0(a6) +# fmv.w.x f4, x1 +# li x1, 0x7ff8000000000000 + # fmv.w.x f9, x1 + fsgnjx.s f12,f9,f4 # expected f 0xffffffff7fc00000 + fsd f12, 0(a6) + +######################### +# HTIF and signature +######################### + +write_tohost: + la t1, tohost + li t0, 1 # 1 for success, 3 for failure + sd t0, 0(t1) # send success code + +self_loop: + j self_loop # wait + +.align 6 +.section .tohost +tohost: # write to HTIF + .dword 0 +fromhost: + .dword 0 + +.align 6 +.data + +rvtest_data: +.dword 0x7ff0000000000001 +.dword 0x7ff8000000000000 + +.EQU XLEN,64 +begin_signature: + .fill 2*(XLEN/32),4,0xdeadbeef # +end_signature: + +# Initialize stack with room for 512 bytes +.bss + .space 512 +topofstack: \ No newline at end of file diff --git a/tests/testgen/privileged/run.sh b/tests/testgen/privileged/run.sh index 1fa3a9d01..d1afb4e89 100755 --- a/tests/testgen/privileged/run.sh +++ b/tests/testgen/privileged/run.sh @@ -11,7 +11,7 @@ printf "\n\n#####\nStarting tests for $1\n#####\n\n" if [[ "$2" != "-simonly" ]] then - cd $WALLY/pipelined/testgen/privileged + cd $WALLY/testgen/privileged python3 "testgen-$1.py" printf "\n\n#####\nRan testgen-$1.py Making...\n#####\n\n\n" @@ -48,7 +48,7 @@ fi if [[ "$2" == "-sim" || "$2" == "-simonly" ]] then printf "\n\n\n#####\nSimulating!\n#####\n\n" - cd $WALLY/pipelined/regression + cd $WALLY/sim vsim -do wally-privileged.do -c fi diff --git a/tests/testgen/testgen_header.S b/tests/testgen/testgen_header.S index 4129782f6..a93e5af10 100644 --- a/tests/testgen/testgen_header.S +++ b/tests/testgen/testgen_header.S @@ -1,21 +1,12 @@ // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 /////////////////////////////////////////// #include "model_test.h" #include "arch_test.h" +RVTEST_ISA("RV64I") .section .text.init .globl rvtest_entry_point @@ -23,4 +14,7 @@ rvtest_entry_point: RVMODEL_BOOT RVTEST_CODE_BEGIN +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",temp) + + RVTEST_SIGBASE( x6, wally_signature) diff --git a/wallypipelinedcore.sv b/wallypipelinedcore.sv deleted file mode 100644 index 7013d0309..000000000 --- a/wallypipelinedcore.sv +++ /dev/null @@ -1,360 +0,0 @@ -/////////////////////////////////////////// -// wallypipelinedcore.sv -// -// Written: David_Harris@hmc.edu 9 January 2021 -// Modified: -// -// Purpose: Pipelined RISC-V Processor -// -// Documentation: RISC-V System on Chip Design (Figure 4.1) -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -import cvw::*; // global CORE-V-Wally parameters - -module wallypipelinedcore ( - input logic clk, reset, - // Privileged - input logic MTimerInt, MExtInt, SExtInt, MSwInt, - input logic [63:0] MTIME_CLINT, - // Bus Interface - input logic [AHBW-1:0] HRDATA, - input logic HREADY, HRESP, - output logic HCLK, HRESETn, - output logic [PA_BITS-1:0] HADDR, - output logic [AHBW-1:0] HWDATA, - output logic [XLEN/8-1:0] HWSTRB, - output logic HWRITE, - output logic [2:0] HSIZE, - output logic [2:0] HBURST, - output logic [3:0] HPROT, - output logic [1:0] HTRANS, - output logic HMASTLOCK -); - - logic StallF, StallD, StallE, StallM, StallW; - logic FlushD, FlushE, FlushM, FlushW; - logic RetM; - logic TrapM; - - // signals that must connect through DP - logic IntDivE, W64E; - logic CSRReadM, CSRWriteM, PrivilegedM; - logic [1:0] AtomicM; - logic [XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE; - logic [XLEN-1:0] SrcAM; - logic [2:0] Funct3E; - logic [31:0] InstrD; - logic [31:0] InstrM; - logic [XLEN-1:0] PCFSpill, PCE, PCLinkE; - logic [XLEN-1:0] PCM; - logic [XLEN-1:0] CSRReadValW, MDUResultW; - logic [XLEN-1:0] UnalignedPCNextF, PCNext2F; - logic [1:0] MemRWM; - logic InstrValidM; - logic InstrMisalignedFaultM; - logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD; - logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM; - logic LoadMisalignedFaultM, LoadAccessFaultM; - logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM; - logic InvalidateICacheM, FlushDCacheM; - logic PCSrcE; - logic CSRWriteFenceM; - logic DivBusyE; - logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD; - logic SquashSCW; - - // floating point unit signals - logic [2:0] FRM_REGW; - logic [4:0] RdE, RdM, RdW; - logic FPUStallD; - logic FWriteIntE; - logic [FLEN-1:0] FWriteDataM; - logic [XLEN-1:0] FIntResM; - logic [XLEN-1:0] FCvtIntResW; - logic FCvtIntW; - logic FDivBusyE; - logic IllegalFPUInstrM; - logic FRegWriteM; - logic FCvtIntStallD; - logic FpLoadStoreM; - logic [4:0] SetFflagsM; - logic [XLEN-1:0] FIntDivResultW; - - // memory management unit signals - logic ITLBWriteF; - logic ITLBMissF; - logic [XLEN-1:0] SATP_REGW; - logic STATUS_MXR, STATUS_SUM, STATUS_MPRV; - logic [1:0] STATUS_MPP, STATUS_FS; - logic [1:0] PrivilegeModeW; - logic [XLEN-1:0] PTE; - logic [1:0] PageType; - logic sfencevmaM, WFIStallM; - logic SelHPTW; - - // PMA checker signals - var logic [XLEN-1:0] PMPADDR_ARRAY_REGW[PMP_ENTRIES-1:0]; - var logic [7:0] PMPCFG_ARRAY_REGW[PMP_ENTRIES-1:0]; - - // IMem stalls - logic IFUStallF; - logic LSUStallM; - - // cpu lsu interface - logic [2:0] Funct3M; - logic [XLEN-1:0] IEUAdrE; - logic [XLEN-1:0] WriteDataM; - logic [XLEN-1:0] IEUAdrM; - logic [LLEN-1:0] ReadDataW; - logic CommittedM; - - // AHB ifu interface - logic [PA_BITS-1:0] IFUHADDR; - logic [2:0] IFUHBURST; - logic [1:0] IFUHTRANS; - logic [2:0] IFUHSIZE; - logic IFUHWRITE; - logic IFUHREADY; - - // AHB LSU interface - logic [PA_BITS-1:0] LSUHADDR; - logic [XLEN-1:0] LSUHWDATA; - logic [XLEN/8-1:0] LSUHWSTRB; - logic LSUHWRITE; - logic LSUHREADY; - - logic BPPredWrongE, BPPredWrongM; - logic DirPredictionWrongM; - logic BTBPredPCWrongM; - logic RASPredPCWrongM; - logic PredictionInstrClassWrongM; - logic [3:0] InstrClassM; - logic InstrAccessFaultF, HPTWInstrAccessFaultM; - logic [2:0] LSUHSIZE; - logic [2:0] LSUHBURST; - logic [1:0] LSUHTRANS; - - logic DCacheMiss; - logic DCacheAccess; - logic ICacheMiss; - logic ICacheAccess; - logic BreakpointFaultM, EcallFaultM; - logic InstrDAPageFaultF; - logic BigEndianM; - logic FCvtIntE; - logic CommittedF; - logic JumpOrTakenBranchM; - - // instruction fetch unit: PC, branch prediction, instruction cache - ifu ifu(.clk, .reset, - .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - // Fetch - .HRDATA, .PCFSpill, .IFUHADDR, .PCNext2F, - .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE, - .ICacheAccess, .ICacheMiss, - // Execute - .PCLinkE, .PCSrcE, .IEUAdrE, .PCE, .BPPredWrongE, .BPPredWrongM, - // Mem - .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM, - .InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM, .JumpOrTakenBranchM, - .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM, - // Faults out - .IllegalBaseInstrFaultD, .InstrPageFaultF, .IllegalIEUInstrFaultD, .InstrMisalignedFaultM, - // mmu management - .PrivilegeModeW, .PTE, .PageType, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, - .STATUS_MPP, .ITLBWriteF, .sfencevmaM, .ITLBMissF, - // pmp/pma (inside mmu) signals. - .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .InstrAccessFaultF, .InstrDAPageFaultF); - - // integer execution unit: integer register file, datapath and controller - ieu ieu(.clk, .reset, - // Decode Stage interface - .InstrD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, - // Execute Stage interface - .PCE, .PCLinkE, .FWriteIntE, .FCvtIntE, .IEUAdrE, .IntDivE, .W64E, - .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, - // Memory stage interface - .SquashSCW, // from LSU - .MemRWM, // read/write control goes to LSU - .AtomicM, // atomic control goes to LSU - .WriteDataM, // Write data to LSU - .Funct3M, // size and signedness to LSU - .SrcAM, // to privilege and fpu - .RdE, .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM, - // Writeback stage - .CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[XLEN-1:0]), - .InstrValidM, .FCvtIntResW, .FCvtIntW, - // hazards - .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD, .PCSrcE, - .CSRReadM, .CSRWriteM, .PrivilegedM, .CSRWriteFenceM, .StoreStallD); - - lsu lsu( - .clk, .reset, .StallM, .FlushM, .StallW, .FlushW, - // CPU interface - .MemRWM, .Funct3M, .Funct7M(InstrM[31:25]), .AtomicM, - .CommittedM, .DCacheMiss, .DCacheAccess, .SquashSCW, - .FpLoadStoreM, .FWriteDataM, .IEUAdrE, .IEUAdrM, .WriteDataM, - .ReadDataW, .FlushDCacheM, - // connected to ahb (all stay the same) - .LSUHADDR, .HRDATA, .LSUHWDATA, .LSUHWSTRB, .LSUHSIZE, - .LSUHBURST, .LSUHTRANS, .LSUHWRITE, .LSUHREADY, - // connect to csr or privilege and stay the same. - .PrivilegeModeW, .BigEndianM, // connects to csr - .PMPCFG_ARRAY_REGW, // connects to csr - .PMPADDR_ARRAY_REGW, // connects to csr - // hptw keep i/o - .SATP_REGW, // from csr - .STATUS_MXR, // from csr - .STATUS_SUM, // from csr - .STATUS_MPRV, // from csr - .STATUS_MPP, // from csr - .sfencevmaM, // connects to privilege - .LoadPageFaultM, // connects to privilege - .StoreAmoPageFaultM, // connects to privilege - .LoadMisalignedFaultM, // connects to privilege - .LoadAccessFaultM, // connects to privilege - .HPTWInstrAccessFaultM, // connects to privilege - .StoreAmoMisalignedFaultM, // connects to privilege - .StoreAmoAccessFaultM, // connects to privilege - .InstrDAPageFaultF, - .PCFSpill, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW, - .LSUStallM); - - if(BUS_SUPPORTED) begin : ebu - ebu ebu(// IFU connections - .clk, .reset, - // IFU interface - .IFUHADDR, - .IFUHBURST, - .IFUHTRANS, - .IFUHREADY, - .IFUHSIZE, - // LSU interface - .LSUHADDR, - .LSUHWDATA, - .LSUHWSTRB, - .LSUHSIZE, - .LSUHBURST, - .LSUHTRANS, - .LSUHWRITE, - .LSUHREADY, - // BUS interface - .HREADY, .HRESP, .HCLK, .HRESETn, - .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, - .HPROT, .HTRANS, .HMASTLOCK); - end - - // global stall and flush control - hazard hzu( - .BPPredWrongE, .CSRWriteFenceM, .RetM, .TrapM, - .LoadStallD, .StoreStallD, .MDUStallD, .CSRRdStallD, - .LSUStallM, .IFUStallF, - .FCvtIntStallD, .FPUStallD, - .DivBusyE, .FDivBusyE, - .EcallFaultM, .BreakpointFaultM, - .WFIStallM, - // Stall & flush outputs - .StallF, .StallD, .StallE, .StallM, .StallW, - .FlushD, .FlushE, .FlushM, .FlushW); - - // privileged unit - if (ZICSR_SUPPORTED) begin:priv - privileged priv( - .clk, .reset, - .FlushD, .FlushE, .FlushM, .FlushW, .StallD, .StallE, .StallM, .StallW, - .CSRReadM, .CSRWriteM, .SrcAM, .PCM, .PCNext2F, - .InstrM, .CSRReadValW, .UnalignedPCNextF, - .RetM, .TrapM, .sfencevmaM, - .InstrValidM, .CommittedM, .CommittedF, - .FRegWriteM, .LoadStallD, - .DirPredictionWrongM, .BTBPredPCWrongM, .BPPredWrongM, - .RASPredPCWrongM, .PredictionInstrClassWrongM, - .InstrClassM, .JumpOrTakenBranchM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM, - .InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM, - .InstrMisalignedFaultM, .IllegalIEUInstrFaultD, - .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, - .MTimerInt, .MExtInt, .SExtInt, .MSwInt, - .MTIME_CLINT, .IEUAdrM, .SetFflagsM, - .InstrAccessFaultF, .HPTWInstrAccessFaultM, .LoadAccessFaultM, .StoreAmoAccessFaultM, .SelHPTW, - .IllegalFPUInstrM, .PrivilegeModeW, .SATP_REGW, - .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS, - .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, - .FRM_REGW,.BreakpointFaultM, .EcallFaultM, .WFIStallM, .BigEndianM); - end else begin - assign CSRReadValW = 0; - assign UnalignedPCNextF = PCNext2F; - assign RetM = 0; - assign TrapM = 0; - assign WFIStallM = 0; - assign sfencevmaM = 0; - assign BigEndianM = 0; - end - - // multiply/divide unit - if (M_SUPPORTED) begin:mdu - mdu mdu(.clk, .reset, .StallM, .StallW, .FlushE, .FlushM, .FlushW, - .ForwardedSrcAE, .ForwardedSrcBE, - .Funct3E, .Funct3M, .IntDivE, .W64E, - .MDUResultW, .DivBusyE); - end else begin // no M instructions supported - assign MDUResultW = 0; - assign DivBusyE = 0; - end - - // floating point unit - if (F_SUPPORTED) begin:fpu - fpu fpu( - .clk, .reset, - .FRM_REGW, // Rounding mode from CSR - .InstrD, // instruction from IFU - .ReadDataW(ReadDataW[FLEN-1:0]),// Read data from memory - .ForwardedSrcAE, // Integer input being processed (from IEU) - .StallE, .StallM, .StallW, // stall signals from HZU - .FlushE, .FlushM, .FlushW, // flush signals from HZU - .RdE, .RdM, .RdW, // which FP register to write to (from IEU) - .STATUS_FS, // is floating-point enabled? - .FRegWriteM, // FP register write enable - .FpLoadStoreM, - .ForwardedSrcBE, // Integer input for intdiv - .Funct3E, .Funct3M, .IntDivE, .W64E, // Integer flags and functions - .FPUStallD, // Stall the decode stage - .FWriteIntE, .FCvtIntE, // integer register write enable, conversion operation - .FWriteDataM, // Data to be written to memory - .FIntResM, // data to be written to integer register - .FCvtIntResW, // fp -> int conversion result to be stored in int register - .FCvtIntW, // fpu result selection - .FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage) - .IllegalFPUInstrM, // Is the instruction an illegal fpu instruction - .SetFflagsM, // FPU flags (to privileged unit) - .FIntDivResultW); - end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low - assign FPUStallD = 0; - assign FWriteIntE = 0; - assign FCvtIntE = 0; - assign FIntResM = 0; - assign FCvtIntW = 0; - assign FDivBusyE = 0; - assign IllegalFPUInstrM = 1; - assign SetFflagsM = 0; - assign FpLoadStoreM = 0; - end - -endmodule diff --git a/wallypipelinedsoc.sv b/wallypipelinedsoc.sv deleted file mode 100644 index e792f6f89..000000000 --- a/wallypipelinedsoc.sv +++ /dev/null @@ -1,92 +0,0 @@ -/////////////////////////////////////////// -// wally-pipelinedsoc.sv -// -// Written: David_Harris@hmc.edu 6 November 2020 -// Modified: -// -// Purpose: System on chip including pipelined processor and uncore memories/peripherals -// -// Documentation: RISC-V System on Chip Design (Figure 6.20) -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -import cvw::*; // global CORE-V-Wally parameters - -module wallypipelinedsoc ( - input logic clk, - input logic reset_ext, // external asynchronous reset pin - output logic reset, // reset synchronized to clk to prevent races on release - // AHB Interface - input logic [AHBW-1:0] HRDATAEXT, - input logic HREADYEXT, HRESPEXT, - output logic HSELEXT, - // outputs to external memory, shared with uncore memory - output logic HCLK, HRESETn, - output logic [PA_BITS-1:0] HADDR, - output logic [AHBW-1:0] HWDATA, - output logic [XLEN/8-1:0] HWSTRB, - output logic HWRITE, - output logic [2:0] HSIZE, - output logic [2:0] HBURST, - output logic [3:0] HPROT, - output logic [1:0] HTRANS, - output logic HMASTLOCK, - output logic HREADY, - // I/O Interface - input logic TIMECLK, // optional for CLINT MTIME counter - input logic [31:0] GPIOPinsIn, // inputs from GPIO - output logic [31:0] GPIOPinsOut, // output values for GPIO - output logic [31:0] GPIOPinsEn, // output enables for GPIO - input logic UARTSin, // UART serial data input - output logic UARTSout, // UART serial data output - input logic SDCCmdIn, // SDC Command input - output logic SDCCmdOut, // SDC Command output - output logic SDCCmdOE, // SDC Command output enable - input logic [3:0] SDCDatIn, // SDC data input - output logic SDCCLK // SDC clock -); - - // Uncore signals - logic [AHBW-1:0] HRDATA; // from AHB mux in uncore - logic HRESP; // response from AHB - logic MTimerInt, MSwInt; // timer and software interrupts from CLINT - logic [63:0] MTIME_CLINT; // from CLINT to CSRs - logic MExtInt,SExtInt; // from PLIC - - // synchronize reset to SOC clock domain - synchronizer resetsync(.clk, .d(reset_ext), .q(reset)); - - // instantiate processor and internal memories - wallypipelinedcore core(.clk, .reset, - .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT, - .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, - .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK - ); - - // instantiate uncore if a bus interface exists - if (BUS_SUPPORTED) begin : uncore - uncore uncore(.HCLK, .HRESETn, .TIMECLK, - .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, - .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, - .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, - .UARTSout, .MTIME_CLINT, - .SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK); - end - -endmodule