From e820d1938ac7d21c8cbb7eddfc7e7c75c40c5fac Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Wed, 1 Feb 2023 05:06:56 -0800
Subject: [PATCH 01/71] Only add memory libraries when targeting 28nm

---
 synthDC/.synopsys_dc.setup | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup
index 8b0ba0309..492256568 100755
--- a/synthDC/.synopsys_dc.setup
+++ b/synthDC/.synopsys_dc.setup
@@ -48,10 +48,12 @@ set cache_read   $cache_write
 lappend search_path ./scripts
 lappend search_path ./hdl
 lappend search_path ./mapped
-set memory /home/jstine/WallyMem/rv64gc/
-lappend target_library $memory/ts3n28hpcpa128x64m8m_130a/NLDM/ts3n28hpcpa128x64m8m_tt0p9v25c.db
-lappend target_library $memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db
-lappend target_library $memory/ts1n28hpcpsvtb64x44m4sw_180a/NLDM/ts1n28hpcpsvtb64x44m4sw_tt0p9v25c.db
+if {$tech="tsmc28"} {}
+    set memory /home/jstine/WallyMem/rv64gc/
+    lappend target_library $memory/ts3n28hpcpa128x64m8m_130a/NLDM/ts3n28hpcpa128x64m8m_tt0p9v25c.db
+    lappend target_library $memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db
+    lappend target_library $memory/ts1n28hpcpsvtb64x44m4sw_180a/NLDM/ts1n28hpcpsvtb64x44m4sw_tt0p9v25c.db
+}
 
 # Set up User Information
 set company "Oklahoma State University"

From 8601f0439766508dda9a2d137fd4bf599ef64e4a Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Wed, 1 Feb 2023 05:49:30 -0800
Subject: [PATCH 02/71] Fixed typo in DC setup for memories

---
 synthDC/.synopsys_dc.setup | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup
index 492256568..2fdc11c27 100755
--- a/synthDC/.synopsys_dc.setup
+++ b/synthDC/.synopsys_dc.setup
@@ -48,7 +48,7 @@ set cache_read   $cache_write
 lappend search_path ./scripts
 lappend search_path ./hdl
 lappend search_path ./mapped
-if {$tech="tsmc28"} {}
+if {$tech == "tsmc28"} {
     set memory /home/jstine/WallyMem/rv64gc/
     lappend target_library $memory/ts3n28hpcpa128x64m8m_130a/NLDM/ts3n28hpcpa128x64m8m_tt0p9v25c.db
     lappend target_library $memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db

From 0a540495f62ae178ff10ff199f0bad8c94090ac0 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Wed, 1 Feb 2023 15:43:52 -0800
Subject: [PATCH 03/71] Removed O2 from fir Makefile to be consistent with lab.

---
 examples/C/fir/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/examples/C/fir/Makefile b/examples/C/fir/Makefile
index c27e423a5..4e3991e46 100644
--- a/examples/C/fir/Makefile
+++ b/examples/C/fir/Makefile
@@ -5,7 +5,7 @@ $(TARGET).objdump: $(TARGET)
 	spike $(TARGET)
     
 $(TARGET): $(TARGET).c Makefile
-	riscv64-unknown-elf-gcc -o $(TARGET) -g -O2\
+	riscv64-unknown-elf-gcc -o $(TARGET) -g\
 	  -march=rv64gc -mabi=lp64d -mcmodel=medany \
 	  -nostdlib -static -lm -fno-tree-loop-distribute-patterns \
 	  -T../common/test.ld -I../common \

From 78eb90715c7819bd8b524c2197f67f5e3ccbe549 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 2 Feb 2023 14:14:11 -0800
Subject: [PATCH 04/71] Removed pipelined level of hierarchy

---
 .gitignore                                    | 23 ++++++++-----------
 Install                                       |  2 +-
 Makefile                                      |  4 ++--
 README.md                                     |  2 +-
 benchmarks/coremark/Makefile                  |  2 +-
 benchmarks/embench/Makefile                   |  2 +-
 .../buildroot/wally-config.vh                 |  0
 .../config => config}/fpga/wally-config.vh    |  0
 .../config => config}/rv32e/wally-config.vh   |  0
 .../config => config}/rv32gc/wally-config.vh  |  0
 .../config => config}/rv32i/wally-config.vh   |  0
 .../config => config}/rv32imc/wally-config.vh |  0
 .../rv64fpquad/wally-config.vh                |  0
 .../config => config}/rv64gc/wally-config.vh  |  0
 .../config => config}/rv64i/wally-config.vh   |  0
 {pipelined/config => config}/shared/README    |  0
 .../config => config}/shared/wally-shared.vh  |  0
 fpga/README.md                                |  2 +-
 fpga/generator/Makefile                       |  2 +-
 fpga/generator/wally.tcl                      |  2 +-
 {pipelined/regression => regression}/Makefile |  0
 .../buildrootBugFinder.py                     |  0
 .../regression => regression}/fpga-wave.do    |  0
 .../regression => regression}/imperas.ic      |  0
 .../regression => regression}/lint-wally      |  0
 .../regression => regression}/linux-wave.do   |  0
 .../regression => regression}/make-tests.sh   |  2 +-
 .../makefile-memfile                          |  0
 .../regression-wally                          |  0
 .../run-imperasdv-tests.bash                  |  0
 .../regression => regression}/sim-buildroot   |  0
 .../sim-buildroot-batch                       |  0
 .../regression => regression}/sim-imperas     |  0
 .../regression => regression}/sim-testfloat   |  0
 .../sim-testfloat-batch                       |  0
 .../regression => regression}/sim-wally       |  0
 .../regression => regression}/sim-wally-batch |  0
 .../slack-notifier/slack-notifier.py          |  0
 {pipelined/regression => regression}/test     |  0
 .../regression => regression}/testfloat.do    |  0
 .../wally-pipelined-batch.do                  |  0
 .../wally-pipelined-imperas-no-idv.do         |  0
 .../wally-pipelined-imperas.do                |  0
 .../wally-pipelined.do                        |  0
 .../regression => regression}/wave-all.do     |  0
 .../wave-dos/ahb-muldiv.do                    |  0
 .../wave-dos/ahb-waves.do                     |  0
 .../wave-dos/cache-waves.do                   |  0
 .../wave-dos/default-waves.do                 |  0
 .../wave-dos/generic.do                       |  0
 .../wave-dos/linux-waves.do                   |  0
 .../wave-dos/peripheral-waves.do              |  0
 .../regression => regression}/wave-fpu.do     |  0
 {pipelined/regression => regression}/wave.do  |  0
 setup.imperas.sh                              |  2 +-
 {pipelined/src => src}/cache/cache.sv         |  0
 {pipelined/src => src}/cache/cacheLRU.sv      |  0
 {pipelined/src => src}/cache/cachefsm.sv      |  0
 {pipelined/src => src}/cache/cacheway.sv      |  0
 .../src => src}/cache/subcachelineread.sv     |  0
 .../src => src}/ebu/ahbcacheinterface.sv      |  0
 {pipelined/src => src}/ebu/ahbinterface.sv    |  0
 {pipelined/src => src}/ebu/buscachefsm.sv     |  0
 {pipelined/src => src}/ebu/busfsm.sv          |  0
 .../src => src}/ebu/controllerinputstage.sv   |  0
 {pipelined/src => src}/ebu/ebu.sv             |  0
 {pipelined/src => src}/ebu/ebuarbfsm.sv       |  0
 {pipelined/src => src}/fpu/fclassify.sv       |  0
 {pipelined/src => src}/fpu/fcmp.sv            |  0
 {pipelined/src => src}/fpu/fctrl.sv           |  0
 {pipelined/src => src}/fpu/fcvt.sv            |  0
 .../src => src}/fpu/fdivsqrt/fdivsqrt.sv      |  0
 .../fpu/fdivsqrt/fdivsqrtexpcalc.sv           |  0
 .../src => src}/fpu/fdivsqrt/fdivsqrtfgen2.sv |  0
 .../src => src}/fpu/fdivsqrt/fdivsqrtfgen4.sv |  0
 .../src => src}/fpu/fdivsqrt/fdivsqrtfsm.sv   |  0
 .../src => src}/fpu/fdivsqrt/fdivsqrtiter.sv  |  0
 .../fpu/fdivsqrt/fdivsqrtpostproc.sv          |  0
 .../fpu/fdivsqrt/fdivsqrtpreproc.sv           |  0
 .../src => src}/fpu/fdivsqrt/fdivsqrtqsel2.sv |  0
 .../src => src}/fpu/fdivsqrt/fdivsqrtqsel4.sv |  0
 .../fpu/fdivsqrt/fdivsqrtqsel4cmp.sv          |  0
 .../fpu/fdivsqrt/fdivsqrtstage2.sv            |  0
 .../fpu/fdivsqrt/fdivsqrtstage4.sv            |  0
 .../fpu/fdivsqrt/fdivsqrtuotfc2.sv            |  0
 .../fpu/fdivsqrt/fdivsqrtuotfc4.sv            |  0
 {pipelined/src => src}/fpu/fhazard.sv         |  0
 {pipelined/src => src}/fpu/fma/fma.sv         |  0
 {pipelined/src => src}/fpu/fma/fmaadd.sv      |  0
 {pipelined/src => src}/fpu/fma/fmaalign.sv    |  0
 {pipelined/src => src}/fpu/fma/fmaexpadd.sv   |  0
 {pipelined/src => src}/fpu/fma/fmalza.sv      |  0
 {pipelined/src => src}/fpu/fma/fmamult.sv     |  0
 {pipelined/src => src}/fpu/fma/fmasign.sv     |  0
 {pipelined/src => src}/fpu/fpu.sv             |  0
 {pipelined/src => src}/fpu/fregfile.sv        |  0
 {pipelined/src => src}/fpu/fsgninj.sv         |  0
 .../src => src}/fpu/postproc/cvtshiftcalc.sv  |  0
 .../src => src}/fpu/postproc/divshiftcalc.sv  |  0
 {pipelined/src => src}/fpu/postproc/flags.sv  |  0
 .../src => src}/fpu/postproc/fmashiftcalc.sv  |  0
 .../src => src}/fpu/postproc/negateintres.sv  |  0
 .../src => src}/fpu/postproc/normshift.sv     |  0
 .../src => src}/fpu/postproc/postprocess.sv   |  0
 .../src => src}/fpu/postproc/resultsign.sv    |  0
 {pipelined/src => src}/fpu/postproc/round.sv  |  0
 .../src => src}/fpu/postproc/roundsign.sv     |  0
 .../fpu/postproc/shiftcorrection.sv           |  0
 .../src => src}/fpu/postproc/specialcase.sv   |  0
 {pipelined/src => src}/fpu/unpack.sv          |  0
 {pipelined/src => src}/fpu/unpackinput.sv     |  0
 {pipelined/src => src}/generic/adder.sv       |  0
 {pipelined/src => src}/generic/aplusbeq0.sv   |  0
 {pipelined/src => src}/generic/arrs.sv        |  0
 {pipelined/src => src}/generic/binencoder.sv  |  0
 {pipelined/src => src}/generic/clockgater.sv  |  0
 {pipelined/src => src}/generic/counter.sv     |  0
 {pipelined/src => src}/generic/csa.sv         |  0
 {pipelined/src => src}/generic/decoder.sv     |  0
 {pipelined/src => src}/generic/flop/flop.sv   |  0
 {pipelined/src => src}/generic/flop/flopen.sv |  0
 .../src => src}/generic/flop/flopenl.sv       |  0
 .../src => src}/generic/flop/flopenr.sv       |  0
 .../src => src}/generic/flop/flopenrc.sv      |  0
 .../src => src}/generic/flop/flopens.sv       |  0
 {pipelined/src => src}/generic/flop/flopr.sv  |  0
 {pipelined/src => src}/generic/flop/floprc.sv |  0
 .../src => src}/generic/flop/synchronizer.sv  |  0
 {pipelined/src => src}/generic/lzc.sv         |  0
 .../src => src}/generic/mem/ram1p1rwbe.sv     |  0
 .../generic/mem/ram1p1rwbe_64x128.sv          |  0
 .../generic/mem/ram1p1rwbe_64x44.sv           |  0
 .../src => src}/generic/mem/ram2p1r1wbe.sv    |  0
 .../generic/mem/ram2p1r1wbe_1024x68.sv        |  0
 .../generic/mem/ram2p1r1wbe_64x32.sv          |  0
 {pipelined/src => src}/generic/mem/rom1p1r.sv |  0
 .../src => src}/generic/mem/rom1p1r_128x32.sv |  0
 .../src => src}/generic/mem/rom1p1r_128x64.sv |  0
 {pipelined/src => src}/generic/mux.sv         |  0
 {pipelined/src => src}/generic/neg.sv         |  0
 .../src => src}/generic/onehotdecoder.sv      |  0
 {pipelined/src => src}/generic/or_rows.sv     |  0
 .../src => src}/generic/priorityonehot.sv     |  0
 .../generic/prioritythermometer.sv            |  0
 {pipelined/src => src}/hazard/hazard.sv       |  0
 {pipelined/src => src}/ieu/alu.sv             |  0
 {pipelined/src => src}/ieu/comparator.sv      |  0
 {pipelined/src => src}/ieu/controller.sv      |  0
 {pipelined/src => src}/ieu/datapath.sv        |  0
 {pipelined/src => src}/ieu/extend.sv          |  0
 {pipelined/src => src}/ieu/forward.sv         |  0
 {pipelined/src => src}/ieu/ieu.sv             |  0
 {pipelined/src => src}/ieu/regfile.sv         |  0
 {pipelined/src => src}/ieu/shifter.sv         |  0
 {pipelined/src => src}/ifu/CodeAligner.py     |  0
 .../src => src}/ifu/bpred/RASPredictor.sv     |  0
 {pipelined/src => src}/ifu/bpred/bpred.sv     |  0
 {pipelined/src => src}/ifu/bpred/btb.sv       |  0
 .../src => src}/ifu/bpred/foldedgshare.sv     |  0
 .../src => src}/ifu/bpred/globalhistory.sv    |  0
 {pipelined/src => src}/ifu/bpred/gshare.sv    |  0
 .../ifu/bpred/localHistoryPredictor.sv        |  0
 {pipelined/src => src}/ifu/bpred/optgshare.sv |  0
 .../src => src}/ifu/bpred/satCounter2.sv      |  0
 .../ifu/bpred/speculativeglobalhistory.sv     |  0
 .../ifu/bpred/speculativegshare.sv            |  0
 .../src => src}/ifu/bpred/twoBitPredictor.sv  |  0
 {pipelined/src => src}/ifu/decompress.sv      |  0
 {pipelined/src => src}/ifu/ifu.sv             |  0
 {pipelined/src => src}/ifu/irom.sv            |  0
 {pipelined/src => src}/ifu/spill.sv           |  0
 {pipelined/src => src}/lsu/amoalu.sv          |  0
 {pipelined/src => src}/lsu/atomic.sv          |  0
 {pipelined/src => src}/lsu/dtim.sv            |  0
 {pipelined/src => src}/lsu/endianswap.sv      |  0
 {pipelined/src => src}/lsu/lrsc.sv            |  0
 {pipelined/src => src}/lsu/lsu.sv             |  0
 {pipelined/src => src}/lsu/subwordread.sv     |  0
 {pipelined/src => src}/lsu/subwordwrite.sv    |  0
 {pipelined/src => src}/lsu/swbytemask.sv      |  0
 {pipelined/src => src}/mdu/intdivrestoring.sv |  0
 .../src => src}/mdu/intdivrestoringstep.sv    |  0
 {pipelined/src => src}/mdu/mdu.sv             |  0
 {pipelined/src => src}/mdu/mul.sv             |  0
 {pipelined/src => src}/mmu/adrdec.sv          |  0
 {pipelined/src => src}/mmu/adrdecs.sv         |  0
 {pipelined/src => src}/mmu/hptw.sv            |  0
 {pipelined/src => src}/mmu/mmu.sv             |  0
 {pipelined/src => src}/mmu/pmachecker.sv      |  0
 {pipelined/src => src}/mmu/pmpadrdec.sv       |  0
 {pipelined/src => src}/mmu/pmpchecker.sv      |  0
 {pipelined/src => src}/mmu/tlb.sv             |  0
 {pipelined/src => src}/mmu/tlbcam.sv          |  0
 {pipelined/src => src}/mmu/tlbcamline.sv      |  0
 {pipelined/src => src}/mmu/tlbcontrol.sv      |  0
 {pipelined/src => src}/mmu/tlblru.sv          |  0
 {pipelined/src => src}/mmu/tlbmixer.sv        |  0
 {pipelined/src => src}/mmu/tlbram.sv          |  0
 {pipelined/src => src}/mmu/tlbramline.sv      |  0
 {pipelined/src => src}/mmu/vm64check.sv       |  0
 {pipelined/src => src}/privileged/csr.sv      |  0
 {pipelined/src => src}/privileged/csrc.sv     |  0
 {pipelined/src => src}/privileged/csri.sv     |  0
 {pipelined/src => src}/privileged/csrm.sv     |  0
 {pipelined/src => src}/privileged/csrs.sv     |  0
 {pipelined/src => src}/privileged/csrsr.sv    |  0
 {pipelined/src => src}/privileged/csru.sv     |  0
 {pipelined/src => src}/privileged/privdec.sv  |  0
 .../src => src}/privileged/privileged.sv      |  0
 {pipelined/src => src}/privileged/privmode.sv |  0
 .../src => src}/privileged/privpiperegs.sv    |  0
 {pipelined/src => src}/privileged/trap.sv     |  0
 {pipelined/src => src}/uncore/ahbapbbridge.sv |  0
 {pipelined/src => src}/uncore/clint_apb.sv    |  0
 {pipelined/src => src}/uncore/gpio_apb.sv     |  0
 {pipelined/src => src}/uncore/plic_apb.sv     |  0
 {pipelined/src => src}/uncore/ram_ahb.sv      |  0
 {pipelined/src => src}/uncore/rom_ahb.sv      |  0
 {pipelined/src => src}/uncore/uartPC16550D.sv |  0
 {pipelined/src => src}/uncore/uart_apb.sv     |  0
 {pipelined/src => src}/uncore/uncore.sv       |  0
 {pipelined/src => src}/wally/cvw.sv           |  0
 .../src => src}/wally/wallypipelinedcore.sv   |  0
 .../src => src}/wally/wallypipelinedsoc.sv    |  0
 synthDC/Makefile                              |  6 ++---
 synthDC/scripts/synth.tcl                     |  2 +-
 .../common/functionName.sv                    |  0
 .../common/instrNameDecTB.sv                  |  0
 .../common/instrTrackerTB.sv                  |  0
 .../common/wallyTracer.sv                     |  0
 {pipelined/testbench => testbench}/fp/case.sh |  0
 .../testbench => testbench}/sdc/ram2sdLoad.py |  0
 .../testbench => testbench}/sdc/ramdisk2.hex  |  0
 .../testbench => testbench}/sdc/run_tb.do     |  0
 .../testbench => testbench}/sdc/sdModel.sv    |  0
 .../testbench => testbench}/sdc/sd_crc_16.sv  |  0
 .../testbench => testbench}/sdc/sd_crc_7.sv   |  0
 .../testbench => testbench}/sdc/sd_defines.h  |  0
 .../testbench => testbench}/sdc/sd_top_tb.sv  |  0
 .../testbench => testbench}/sdc/wave.do       |  0
 .../testbench => testbench}/testbench-fp.sv   |  2 +-
 .../testbench-linux.sv                        |  0
 .../testbench => testbench}/testbench.sv      |  2 +-
 .../testbench_imperas.sv                      |  0
 .../testbench => testbench}/tests-fp.vh       |  0
 {pipelined/testbench => testbench}/tests.vh   | 14 +++++------
 tests/testgen/privileged/run.sh               |  4 ++--
 247 files changed, 35 insertions(+), 40 deletions(-)
 rename {pipelined/config => config}/buildroot/wally-config.vh (100%)
 rename {pipelined/config => config}/fpga/wally-config.vh (100%)
 rename {pipelined/config => config}/rv32e/wally-config.vh (100%)
 rename {pipelined/config => config}/rv32gc/wally-config.vh (100%)
 rename {pipelined/config => config}/rv32i/wally-config.vh (100%)
 rename {pipelined/config => config}/rv32imc/wally-config.vh (100%)
 rename {pipelined/config => config}/rv64fpquad/wally-config.vh (100%)
 rename {pipelined/config => config}/rv64gc/wally-config.vh (100%)
 rename {pipelined/config => config}/rv64i/wally-config.vh (100%)
 rename {pipelined/config => config}/shared/README (100%)
 rename {pipelined/config => config}/shared/wally-shared.vh (100%)
 rename {pipelined/regression => regression}/Makefile (100%)
 rename {pipelined/regression => regression}/buildrootBugFinder.py (100%)
 rename {pipelined/regression => regression}/fpga-wave.do (100%)
 rename {pipelined/regression => regression}/imperas.ic (100%)
 rename {pipelined/regression => regression}/lint-wally (100%)
 rename {pipelined/regression => regression}/linux-wave.do (100%)
 rename {pipelined/regression => regression}/make-tests.sh (88%)
 rename {pipelined/regression => regression}/makefile-memfile (100%)
 rename {pipelined/regression => regression}/regression-wally (100%)
 rename {pipelined/regression => regression}/run-imperasdv-tests.bash (100%)
 rename {pipelined/regression => regression}/sim-buildroot (100%)
 rename {pipelined/regression => regression}/sim-buildroot-batch (100%)
 rename {pipelined/regression => regression}/sim-imperas (100%)
 rename {pipelined/regression => regression}/sim-testfloat (100%)
 rename {pipelined/regression => regression}/sim-testfloat-batch (100%)
 rename {pipelined/regression => regression}/sim-wally (100%)
 rename {pipelined/regression => regression}/sim-wally-batch (100%)
 rename {pipelined/regression => regression}/slack-notifier/slack-notifier.py (100%)
 rename {pipelined/regression => regression}/test (100%)
 rename {pipelined/regression => regression}/testfloat.do (100%)
 rename {pipelined/regression => regression}/wally-pipelined-batch.do (100%)
 rename {pipelined/regression => regression}/wally-pipelined-imperas-no-idv.do (100%)
 rename {pipelined/regression => regression}/wally-pipelined-imperas.do (100%)
 rename {pipelined/regression => regression}/wally-pipelined.do (100%)
 rename {pipelined/regression => regression}/wave-all.do (100%)
 rename {pipelined/regression => regression}/wave-dos/ahb-muldiv.do (100%)
 rename {pipelined/regression => regression}/wave-dos/ahb-waves.do (100%)
 rename {pipelined/regression => regression}/wave-dos/cache-waves.do (100%)
 rename {pipelined/regression => regression}/wave-dos/default-waves.do (100%)
 rename {pipelined/regression => regression}/wave-dos/generic.do (100%)
 rename {pipelined/regression => regression}/wave-dos/linux-waves.do (100%)
 rename {pipelined/regression => regression}/wave-dos/peripheral-waves.do (100%)
 rename {pipelined/regression => regression}/wave-fpu.do (100%)
 rename {pipelined/regression => regression}/wave.do (100%)
 rename {pipelined/src => src}/cache/cache.sv (100%)
 rename {pipelined/src => src}/cache/cacheLRU.sv (100%)
 rename {pipelined/src => src}/cache/cachefsm.sv (100%)
 rename {pipelined/src => src}/cache/cacheway.sv (100%)
 rename {pipelined/src => src}/cache/subcachelineread.sv (100%)
 rename {pipelined/src => src}/ebu/ahbcacheinterface.sv (100%)
 rename {pipelined/src => src}/ebu/ahbinterface.sv (100%)
 rename {pipelined/src => src}/ebu/buscachefsm.sv (100%)
 rename {pipelined/src => src}/ebu/busfsm.sv (100%)
 rename {pipelined/src => src}/ebu/controllerinputstage.sv (100%)
 rename {pipelined/src => src}/ebu/ebu.sv (100%)
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diff --git a/.gitignore b/.gitignore
index 1e651e68e..b389dd1dd 100644
--- a/.gitignore
+++ b/.gitignore
@@ -15,7 +15,7 @@ benchmarks/embench/wally*.json
 #vsim work files to ignore
 transcript
 vsim.wlf
-pipelined/wlft*
+wlft*
 wlft*
 /imperas-riscv-tests/FunctionRadix_32.addr
 /imperas-riscv-tests/FunctionRadix_64.addr
@@ -42,8 +42,8 @@ tests/linux-testgen/buildroot-image-output
 tests/linux-testgen/buildroot-config-src/main.config.old
 tests/linux-testgen/buildroot-config-src/linux.config.old
 tests/linux-testgen/buildroot-config-src/busybox.config.old
-pipelined/regression/slack-notifier/slack-webhook-url.txt
-pipelined/regression/logs
+regression/slack-notifier/slack-webhook-url.txt
+regression/logs
 fpga/generator/IP
 fpga/generator/vivado.*
 fpga/generator/.Xil/*
@@ -59,7 +59,7 @@ examples/C/sum/sum
 examples/C/fir/fir
 examples/fp/softfloat_demo/softfloat_demo
 examples/fp/fpcalc/fpcalc
-pipelined/src/fma/fma16_testgen
+src/fma/fma16_testgen
 linux/devicetree/debug/*
 !linux/devicetree/debug/dump-dts.sh
 linux/testvector-generation/genCheckpoint.gdb
@@ -79,29 +79,24 @@ synthDC/ppa/plots
 synthDC/wallyplots/
 synthDC/runArchive
 synthDC/hdl
-/pipelined/regression/power.saif
+regression/power.saif
 tests/fp/vectors/*.tv
 synthDC/Summary.csv
-pipelined/srt/exptestgen
-pipelined/srt/testgen
-pipelined/srt/qslc_r4a2
-pipelined/srt/qslc_r4a2.sv
-pipelined/srt/testvectors
-pipelined/regression/wkdir
+regression/wkdir
 tests/custom/work
 tests/custom/*/*/*.list
 tests/custom/*/*/*.elf
 tests/custom/*/*/*.map
 tests/custom/*/*/*.memfile
 tests/custom/crt0/*.a
-/pipelined/regression/sd_model.log
+regression/sd_model.log
 fpga/src/sdc/*
 fpga/src/sdc.tar.gz
 fpga/src/CopiedFiles_do_not_add_to_repo/*
-/pipelined/regression/branch.log
+regression/branch.log
 /fpga/generator/sim/imp-funcsim.v
 /fpga/generator/sim/imp-timesim.sdf
 /fpga/generator/sim/imp-timesim.v
 /fpga/generator/sim/syn-funcsim.v
 external
-pipelined/regression/results
+regression/results
diff --git a/Install b/Install
index 7e509197d..46f4d78ec 100644
--- a/Install
+++ b/Install
@@ -328,6 +328,6 @@ source ./setup.sh        # may require some modification for your system. Always
 
   cd <to location of repo clone>
   make
-  cd pipelined/regression
+  cd regression
   ./regression-wally       #(depends on having Questa installed)
 
diff --git a/Makefile b/Makefile
index b3a054e49..24ba57e57 100644
--- a/Makefile
+++ b/Makefile
@@ -15,8 +15,8 @@ install:
 	##ln -s ${RISCV}/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
 
 regression:
-	make -C pipelined/regression
+	make -C regression
 
 clean:
-	make clean -C pipelined/regression
+	make clean -C regression
 
diff --git a/README.md b/README.md
index 12d7fe1f6..824c7c176 100644
--- a/README.md
+++ b/README.md
@@ -53,7 +53,7 @@ Edit setup.sh and change the following lines to point to the path and license se
 
 Run a regression simulation with Questa to prove everything is installed.
 
-	$ cd pipelined/regression
+	$ cd regression
 	$ ./regression-wally       (depends on having Questa installed)
 
 # Toolchain Installation (Sys Admin)
diff --git a/benchmarks/coremark/Makefile b/benchmarks/coremark/Makefile
index 8c467d581..b8235ea94 100644
--- a/benchmarks/coremark/Makefile
+++ b/benchmarks/coremark/Makefile
@@ -21,7 +21,7 @@ PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \
 all: $(work_dir)/coremark.bare.riscv.elf.memfile
 
 run:
-	(cd ../../pipelined/regression && (time vsim -c -do "do wally-pipelined-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
+	(cd ../../regression && (time vsim -c -do "do wally-pipelined-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
 	cd ../../benchmarks/coremark/
 #	KMG: added post processing script to give out branch miss proportion along with other stats to the coremark test
 	python3 coremark-postprocess.py
diff --git a/benchmarks/embench/Makefile b/benchmarks/embench/Makefile
index 21c30cf6e..b5030d119 100644
--- a/benchmarks/embench/Makefile
+++ b/benchmarks/embench/Makefile
@@ -34,7 +34,7 @@ sim: modelsim_build_memfile modelsim_run speed
 
 # launches modelsim to simulate tests on wally
 modelsim_run:
-	(cd ../../pipelined/regression/ && vsim -c -do "do wally-pipelined-batch.do rv32gc embench")
+	(cd ../../regression/ && vsim -c -do "do wally-pipelined-batch.do rv32gc embench")
 	cd ../../benchmarks/embench/
 
 # builds the objdump based on the compiled c elf files
diff --git a/pipelined/config/buildroot/wally-config.vh b/config/buildroot/wally-config.vh
similarity index 100%
rename from pipelined/config/buildroot/wally-config.vh
rename to config/buildroot/wally-config.vh
diff --git a/pipelined/config/fpga/wally-config.vh b/config/fpga/wally-config.vh
similarity index 100%
rename from pipelined/config/fpga/wally-config.vh
rename to config/fpga/wally-config.vh
diff --git a/pipelined/config/rv32e/wally-config.vh b/config/rv32e/wally-config.vh
similarity index 100%
rename from pipelined/config/rv32e/wally-config.vh
rename to config/rv32e/wally-config.vh
diff --git a/pipelined/config/rv32gc/wally-config.vh b/config/rv32gc/wally-config.vh
similarity index 100%
rename from pipelined/config/rv32gc/wally-config.vh
rename to config/rv32gc/wally-config.vh
diff --git a/pipelined/config/rv32i/wally-config.vh b/config/rv32i/wally-config.vh
similarity index 100%
rename from pipelined/config/rv32i/wally-config.vh
rename to config/rv32i/wally-config.vh
diff --git a/pipelined/config/rv32imc/wally-config.vh b/config/rv32imc/wally-config.vh
similarity index 100%
rename from pipelined/config/rv32imc/wally-config.vh
rename to config/rv32imc/wally-config.vh
diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/config/rv64fpquad/wally-config.vh
similarity index 100%
rename from pipelined/config/rv64fpquad/wally-config.vh
rename to config/rv64fpquad/wally-config.vh
diff --git a/pipelined/config/rv64gc/wally-config.vh b/config/rv64gc/wally-config.vh
similarity index 100%
rename from pipelined/config/rv64gc/wally-config.vh
rename to config/rv64gc/wally-config.vh
diff --git a/pipelined/config/rv64i/wally-config.vh b/config/rv64i/wally-config.vh
similarity index 100%
rename from pipelined/config/rv64i/wally-config.vh
rename to config/rv64i/wally-config.vh
diff --git a/pipelined/config/shared/README b/config/shared/README
similarity index 100%
rename from pipelined/config/shared/README
rename to config/shared/README
diff --git a/pipelined/config/shared/wally-shared.vh b/config/shared/wally-shared.vh
similarity index 100%
rename from pipelined/config/shared/wally-shared.vh
rename to config/shared/wally-shared.vh
diff --git a/fpga/README.md b/fpga/README.md
index 3f9853c72..dfa27479e 100644
--- a/fpga/README.md
+++ b/fpga/README.md
@@ -16,7 +16,7 @@ a large number of debuging signals.
 
 * Programming the flash card
 You'll need to write the linux image to the flash card.  Use the convert2bin.py 
-script in pipelined/linux-testgen/linux-testvectors/ to convert the ram.txt
+script in linux-testgen/linux-testvectors/ [*** moved?] to convert the ram.txt 
 file from QEMU's preload to generate the binary.  Then to copy
  sudo dd if=ram.bin of=<path to flash card>.
 
diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile
index 3ab35b34b..1d07305fb 100644
--- a/fpga/generator/Makefile
+++ b/fpga/generator/Makefile
@@ -27,7 +27,7 @@ SDC:
 
 PreProcessFiles:
 	rm -rf ../src/CopiedFiles_do_not_add_to_repo/
-	cp -r ../../pipelined/src/ ../src/CopiedFiles_do_not_add_to_repo/
+	cp -r ../../src/ ../src/CopiedFiles_do_not_add_to_repo/
 	./insert_debug_comment.sh
 
 $(dst)/%.log: %.tcl
diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl
index 45444d577..c93abed78 100644
--- a/fpga/generator/wally.tcl
+++ b/fpga/generator/wally.tcl
@@ -19,7 +19,7 @@ read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../s
 read_verilog  {../src/fpgaTop.v}
 read_verilog -sv  [glob -type f ../src/sdc/*.sv]
 
-set_property include_dirs {../../pipelined/config/fpga ../../pipelined/config/shared} [current_fileset]
+set_property include_dirs {../../config/fpga ../../config/shared} [current_fileset]
 
 
 add_files -fileset constrs_1 -norecurse ../constraints/constraints-$boardSubName.xdc
diff --git a/pipelined/regression/Makefile b/regression/Makefile
similarity index 100%
rename from pipelined/regression/Makefile
rename to regression/Makefile
diff --git a/pipelined/regression/buildrootBugFinder.py b/regression/buildrootBugFinder.py
similarity index 100%
rename from pipelined/regression/buildrootBugFinder.py
rename to regression/buildrootBugFinder.py
diff --git a/pipelined/regression/fpga-wave.do b/regression/fpga-wave.do
similarity index 100%
rename from pipelined/regression/fpga-wave.do
rename to regression/fpga-wave.do
diff --git a/pipelined/regression/imperas.ic b/regression/imperas.ic
similarity index 100%
rename from pipelined/regression/imperas.ic
rename to regression/imperas.ic
diff --git a/pipelined/regression/lint-wally b/regression/lint-wally
similarity index 100%
rename from pipelined/regression/lint-wally
rename to regression/lint-wally
diff --git a/pipelined/regression/linux-wave.do b/regression/linux-wave.do
similarity index 100%
rename from pipelined/regression/linux-wave.do
rename to regression/linux-wave.do
diff --git a/pipelined/regression/make-tests.sh b/regression/make-tests.sh
similarity index 88%
rename from pipelined/regression/make-tests.sh
rename to regression/make-tests.sh
index fe4555ff2..de7765086 100755
--- a/pipelined/regression/make-tests.sh
+++ b/regression/make-tests.sh
@@ -13,4 +13,4 @@ make
 # exe2memfile.pl work/*/*/*.elf
 # cd ../linux-testgen/linux-testvectors
 # ./tvLinker.sh
-# cd ../../../pipelined/regression
+# cd ../../../regression
diff --git a/pipelined/regression/makefile-memfile b/regression/makefile-memfile
similarity index 100%
rename from pipelined/regression/makefile-memfile
rename to regression/makefile-memfile
diff --git a/pipelined/regression/regression-wally b/regression/regression-wally
similarity index 100%
rename from pipelined/regression/regression-wally
rename to regression/regression-wally
diff --git a/pipelined/regression/run-imperasdv-tests.bash b/regression/run-imperasdv-tests.bash
similarity index 100%
rename from pipelined/regression/run-imperasdv-tests.bash
rename to regression/run-imperasdv-tests.bash
diff --git a/pipelined/regression/sim-buildroot b/regression/sim-buildroot
similarity index 100%
rename from pipelined/regression/sim-buildroot
rename to regression/sim-buildroot
diff --git a/pipelined/regression/sim-buildroot-batch b/regression/sim-buildroot-batch
similarity index 100%
rename from pipelined/regression/sim-buildroot-batch
rename to regression/sim-buildroot-batch
diff --git a/pipelined/regression/sim-imperas b/regression/sim-imperas
similarity index 100%
rename from pipelined/regression/sim-imperas
rename to regression/sim-imperas
diff --git a/pipelined/regression/sim-testfloat b/regression/sim-testfloat
similarity index 100%
rename from pipelined/regression/sim-testfloat
rename to regression/sim-testfloat
diff --git a/pipelined/regression/sim-testfloat-batch b/regression/sim-testfloat-batch
similarity index 100%
rename from pipelined/regression/sim-testfloat-batch
rename to regression/sim-testfloat-batch
diff --git a/pipelined/regression/sim-wally b/regression/sim-wally
similarity index 100%
rename from pipelined/regression/sim-wally
rename to regression/sim-wally
diff --git a/pipelined/regression/sim-wally-batch b/regression/sim-wally-batch
similarity index 100%
rename from pipelined/regression/sim-wally-batch
rename to regression/sim-wally-batch
diff --git a/pipelined/regression/slack-notifier/slack-notifier.py b/regression/slack-notifier/slack-notifier.py
similarity index 100%
rename from pipelined/regression/slack-notifier/slack-notifier.py
rename to regression/slack-notifier/slack-notifier.py
diff --git a/pipelined/regression/test b/regression/test
similarity index 100%
rename from pipelined/regression/test
rename to regression/test
diff --git a/pipelined/regression/testfloat.do b/regression/testfloat.do
similarity index 100%
rename from pipelined/regression/testfloat.do
rename to regression/testfloat.do
diff --git a/pipelined/regression/wally-pipelined-batch.do b/regression/wally-pipelined-batch.do
similarity index 100%
rename from pipelined/regression/wally-pipelined-batch.do
rename to regression/wally-pipelined-batch.do
diff --git a/pipelined/regression/wally-pipelined-imperas-no-idv.do b/regression/wally-pipelined-imperas-no-idv.do
similarity index 100%
rename from pipelined/regression/wally-pipelined-imperas-no-idv.do
rename to regression/wally-pipelined-imperas-no-idv.do
diff --git a/pipelined/regression/wally-pipelined-imperas.do b/regression/wally-pipelined-imperas.do
similarity index 100%
rename from pipelined/regression/wally-pipelined-imperas.do
rename to regression/wally-pipelined-imperas.do
diff --git a/pipelined/regression/wally-pipelined.do b/regression/wally-pipelined.do
similarity index 100%
rename from pipelined/regression/wally-pipelined.do
rename to regression/wally-pipelined.do
diff --git a/pipelined/regression/wave-all.do b/regression/wave-all.do
similarity index 100%
rename from pipelined/regression/wave-all.do
rename to regression/wave-all.do
diff --git a/pipelined/regression/wave-dos/ahb-muldiv.do b/regression/wave-dos/ahb-muldiv.do
similarity index 100%
rename from pipelined/regression/wave-dos/ahb-muldiv.do
rename to regression/wave-dos/ahb-muldiv.do
diff --git a/pipelined/regression/wave-dos/ahb-waves.do b/regression/wave-dos/ahb-waves.do
similarity index 100%
rename from pipelined/regression/wave-dos/ahb-waves.do
rename to regression/wave-dos/ahb-waves.do
diff --git a/pipelined/regression/wave-dos/cache-waves.do b/regression/wave-dos/cache-waves.do
similarity index 100%
rename from pipelined/regression/wave-dos/cache-waves.do
rename to regression/wave-dos/cache-waves.do
diff --git a/pipelined/regression/wave-dos/default-waves.do b/regression/wave-dos/default-waves.do
similarity index 100%
rename from pipelined/regression/wave-dos/default-waves.do
rename to regression/wave-dos/default-waves.do
diff --git a/pipelined/regression/wave-dos/generic.do b/regression/wave-dos/generic.do
similarity index 100%
rename from pipelined/regression/wave-dos/generic.do
rename to regression/wave-dos/generic.do
diff --git a/pipelined/regression/wave-dos/linux-waves.do b/regression/wave-dos/linux-waves.do
similarity index 100%
rename from pipelined/regression/wave-dos/linux-waves.do
rename to regression/wave-dos/linux-waves.do
diff --git a/pipelined/regression/wave-dos/peripheral-waves.do b/regression/wave-dos/peripheral-waves.do
similarity index 100%
rename from pipelined/regression/wave-dos/peripheral-waves.do
rename to regression/wave-dos/peripheral-waves.do
diff --git a/pipelined/regression/wave-fpu.do b/regression/wave-fpu.do
similarity index 100%
rename from pipelined/regression/wave-fpu.do
rename to regression/wave-fpu.do
diff --git a/pipelined/regression/wave.do b/regression/wave.do
similarity index 100%
rename from pipelined/regression/wave.do
rename to regression/wave.do
diff --git a/setup.imperas.sh b/setup.imperas.sh
index e3ac447bf..4e30fb07f 100644
--- a/setup.imperas.sh
+++ b/setup.imperas.sh
@@ -31,7 +31,7 @@ export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC
 # setup QUESTA (Imperas only command, YMMV)
 svsetup -questa
 
-pushd pipelined/regression
+pushd regression
     # With IDV
     IMPERAS_TOOLS=$(pwd)/imperas.ic \
         OTHERFLAGS="+TRACE2LOG_ENABLE=1 VERBOSE=1" \
diff --git a/pipelined/src/cache/cache.sv b/src/cache/cache.sv
similarity index 100%
rename from pipelined/src/cache/cache.sv
rename to src/cache/cache.sv
diff --git a/pipelined/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv
similarity index 100%
rename from pipelined/src/cache/cacheLRU.sv
rename to src/cache/cacheLRU.sv
diff --git a/pipelined/src/cache/cachefsm.sv b/src/cache/cachefsm.sv
similarity index 100%
rename from pipelined/src/cache/cachefsm.sv
rename to src/cache/cachefsm.sv
diff --git a/pipelined/src/cache/cacheway.sv b/src/cache/cacheway.sv
similarity index 100%
rename from pipelined/src/cache/cacheway.sv
rename to src/cache/cacheway.sv
diff --git a/pipelined/src/cache/subcachelineread.sv b/src/cache/subcachelineread.sv
similarity index 100%
rename from pipelined/src/cache/subcachelineread.sv
rename to src/cache/subcachelineread.sv
diff --git a/pipelined/src/ebu/ahbcacheinterface.sv b/src/ebu/ahbcacheinterface.sv
similarity index 100%
rename from pipelined/src/ebu/ahbcacheinterface.sv
rename to src/ebu/ahbcacheinterface.sv
diff --git a/pipelined/src/ebu/ahbinterface.sv b/src/ebu/ahbinterface.sv
similarity index 100%
rename from pipelined/src/ebu/ahbinterface.sv
rename to src/ebu/ahbinterface.sv
diff --git a/pipelined/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv
similarity index 100%
rename from pipelined/src/ebu/buscachefsm.sv
rename to src/ebu/buscachefsm.sv
diff --git a/pipelined/src/ebu/busfsm.sv b/src/ebu/busfsm.sv
similarity index 100%
rename from pipelined/src/ebu/busfsm.sv
rename to src/ebu/busfsm.sv
diff --git a/pipelined/src/ebu/controllerinputstage.sv b/src/ebu/controllerinputstage.sv
similarity index 100%
rename from pipelined/src/ebu/controllerinputstage.sv
rename to src/ebu/controllerinputstage.sv
diff --git a/pipelined/src/ebu/ebu.sv b/src/ebu/ebu.sv
similarity index 100%
rename from pipelined/src/ebu/ebu.sv
rename to src/ebu/ebu.sv
diff --git a/pipelined/src/ebu/ebuarbfsm.sv b/src/ebu/ebuarbfsm.sv
similarity index 100%
rename from pipelined/src/ebu/ebuarbfsm.sv
rename to src/ebu/ebuarbfsm.sv
diff --git a/pipelined/src/fpu/fclassify.sv b/src/fpu/fclassify.sv
similarity index 100%
rename from pipelined/src/fpu/fclassify.sv
rename to src/fpu/fclassify.sv
diff --git a/pipelined/src/fpu/fcmp.sv b/src/fpu/fcmp.sv
similarity index 100%
rename from pipelined/src/fpu/fcmp.sv
rename to src/fpu/fcmp.sv
diff --git a/pipelined/src/fpu/fctrl.sv b/src/fpu/fctrl.sv
similarity index 100%
rename from pipelined/src/fpu/fctrl.sv
rename to src/fpu/fctrl.sv
diff --git a/pipelined/src/fpu/fcvt.sv b/src/fpu/fcvt.sv
similarity index 100%
rename from pipelined/src/fpu/fcvt.sv
rename to src/fpu/fcvt.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/src/fpu/fdivsqrt/fdivsqrt.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
rename to src/fpu/fdivsqrt/fdivsqrt.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv
rename to src/fpu/fdivsqrt/fdivsqrtexpcalc.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv
rename to src/fpu/fdivsqrt/fdivsqrtfgen2.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv
rename to src/fpu/fdivsqrt/fdivsqrtfgen4.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/src/fpu/fdivsqrt/fdivsqrtfsm.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv
rename to src/fpu/fdivsqrt/fdivsqrtfsm.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv b/src/fpu/fdivsqrt/fdivsqrtiter.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv
rename to src/fpu/fdivsqrt/fdivsqrtiter.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
rename to src/fpu/fdivsqrt/fdivsqrtpostproc.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
rename to src/fpu/fdivsqrt/fdivsqrtpreproc.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv b/src/fpu/fdivsqrt/fdivsqrtqsel2.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv
rename to src/fpu/fdivsqrt/fdivsqrtqsel2.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv b/src/fpu/fdivsqrt/fdivsqrtqsel4.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv
rename to src/fpu/fdivsqrt/fdivsqrtqsel4.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv b/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv
rename to src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv b/src/fpu/fdivsqrt/fdivsqrtstage2.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv
rename to src/fpu/fdivsqrt/fdivsqrtstage2.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/src/fpu/fdivsqrt/fdivsqrtstage4.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv
rename to src/fpu/fdivsqrt/fdivsqrtstage4.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
rename to src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
rename to src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
diff --git a/pipelined/src/fpu/fhazard.sv b/src/fpu/fhazard.sv
similarity index 100%
rename from pipelined/src/fpu/fhazard.sv
rename to src/fpu/fhazard.sv
diff --git a/pipelined/src/fpu/fma/fma.sv b/src/fpu/fma/fma.sv
similarity index 100%
rename from pipelined/src/fpu/fma/fma.sv
rename to src/fpu/fma/fma.sv
diff --git a/pipelined/src/fpu/fma/fmaadd.sv b/src/fpu/fma/fmaadd.sv
similarity index 100%
rename from pipelined/src/fpu/fma/fmaadd.sv
rename to src/fpu/fma/fmaadd.sv
diff --git a/pipelined/src/fpu/fma/fmaalign.sv b/src/fpu/fma/fmaalign.sv
similarity index 100%
rename from pipelined/src/fpu/fma/fmaalign.sv
rename to src/fpu/fma/fmaalign.sv
diff --git a/pipelined/src/fpu/fma/fmaexpadd.sv b/src/fpu/fma/fmaexpadd.sv
similarity index 100%
rename from pipelined/src/fpu/fma/fmaexpadd.sv
rename to src/fpu/fma/fmaexpadd.sv
diff --git a/pipelined/src/fpu/fma/fmalza.sv b/src/fpu/fma/fmalza.sv
similarity index 100%
rename from pipelined/src/fpu/fma/fmalza.sv
rename to src/fpu/fma/fmalza.sv
diff --git a/pipelined/src/fpu/fma/fmamult.sv b/src/fpu/fma/fmamult.sv
similarity index 100%
rename from pipelined/src/fpu/fma/fmamult.sv
rename to src/fpu/fma/fmamult.sv
diff --git a/pipelined/src/fpu/fma/fmasign.sv b/src/fpu/fma/fmasign.sv
similarity index 100%
rename from pipelined/src/fpu/fma/fmasign.sv
rename to src/fpu/fma/fmasign.sv
diff --git a/pipelined/src/fpu/fpu.sv b/src/fpu/fpu.sv
similarity index 100%
rename from pipelined/src/fpu/fpu.sv
rename to src/fpu/fpu.sv
diff --git a/pipelined/src/fpu/fregfile.sv b/src/fpu/fregfile.sv
similarity index 100%
rename from pipelined/src/fpu/fregfile.sv
rename to src/fpu/fregfile.sv
diff --git a/pipelined/src/fpu/fsgninj.sv b/src/fpu/fsgninj.sv
similarity index 100%
rename from pipelined/src/fpu/fsgninj.sv
rename to src/fpu/fsgninj.sv
diff --git a/pipelined/src/fpu/postproc/cvtshiftcalc.sv b/src/fpu/postproc/cvtshiftcalc.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/cvtshiftcalc.sv
rename to src/fpu/postproc/cvtshiftcalc.sv
diff --git a/pipelined/src/fpu/postproc/divshiftcalc.sv b/src/fpu/postproc/divshiftcalc.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/divshiftcalc.sv
rename to src/fpu/postproc/divshiftcalc.sv
diff --git a/pipelined/src/fpu/postproc/flags.sv b/src/fpu/postproc/flags.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/flags.sv
rename to src/fpu/postproc/flags.sv
diff --git a/pipelined/src/fpu/postproc/fmashiftcalc.sv b/src/fpu/postproc/fmashiftcalc.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/fmashiftcalc.sv
rename to src/fpu/postproc/fmashiftcalc.sv
diff --git a/pipelined/src/fpu/postproc/negateintres.sv b/src/fpu/postproc/negateintres.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/negateintres.sv
rename to src/fpu/postproc/negateintres.sv
diff --git a/pipelined/src/fpu/postproc/normshift.sv b/src/fpu/postproc/normshift.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/normshift.sv
rename to src/fpu/postproc/normshift.sv
diff --git a/pipelined/src/fpu/postproc/postprocess.sv b/src/fpu/postproc/postprocess.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/postprocess.sv
rename to src/fpu/postproc/postprocess.sv
diff --git a/pipelined/src/fpu/postproc/resultsign.sv b/src/fpu/postproc/resultsign.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/resultsign.sv
rename to src/fpu/postproc/resultsign.sv
diff --git a/pipelined/src/fpu/postproc/round.sv b/src/fpu/postproc/round.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/round.sv
rename to src/fpu/postproc/round.sv
diff --git a/pipelined/src/fpu/postproc/roundsign.sv b/src/fpu/postproc/roundsign.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/roundsign.sv
rename to src/fpu/postproc/roundsign.sv
diff --git a/pipelined/src/fpu/postproc/shiftcorrection.sv b/src/fpu/postproc/shiftcorrection.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/shiftcorrection.sv
rename to src/fpu/postproc/shiftcorrection.sv
diff --git a/pipelined/src/fpu/postproc/specialcase.sv b/src/fpu/postproc/specialcase.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/specialcase.sv
rename to src/fpu/postproc/specialcase.sv
diff --git a/pipelined/src/fpu/unpack.sv b/src/fpu/unpack.sv
similarity index 100%
rename from pipelined/src/fpu/unpack.sv
rename to src/fpu/unpack.sv
diff --git a/pipelined/src/fpu/unpackinput.sv b/src/fpu/unpackinput.sv
similarity index 100%
rename from pipelined/src/fpu/unpackinput.sv
rename to src/fpu/unpackinput.sv
diff --git a/pipelined/src/generic/adder.sv b/src/generic/adder.sv
similarity index 100%
rename from pipelined/src/generic/adder.sv
rename to src/generic/adder.sv
diff --git a/pipelined/src/generic/aplusbeq0.sv b/src/generic/aplusbeq0.sv
similarity index 100%
rename from pipelined/src/generic/aplusbeq0.sv
rename to src/generic/aplusbeq0.sv
diff --git a/pipelined/src/generic/arrs.sv b/src/generic/arrs.sv
similarity index 100%
rename from pipelined/src/generic/arrs.sv
rename to src/generic/arrs.sv
diff --git a/pipelined/src/generic/binencoder.sv b/src/generic/binencoder.sv
similarity index 100%
rename from pipelined/src/generic/binencoder.sv
rename to src/generic/binencoder.sv
diff --git a/pipelined/src/generic/clockgater.sv b/src/generic/clockgater.sv
similarity index 100%
rename from pipelined/src/generic/clockgater.sv
rename to src/generic/clockgater.sv
diff --git a/pipelined/src/generic/counter.sv b/src/generic/counter.sv
similarity index 100%
rename from pipelined/src/generic/counter.sv
rename to src/generic/counter.sv
diff --git a/pipelined/src/generic/csa.sv b/src/generic/csa.sv
similarity index 100%
rename from pipelined/src/generic/csa.sv
rename to src/generic/csa.sv
diff --git a/pipelined/src/generic/decoder.sv b/src/generic/decoder.sv
similarity index 100%
rename from pipelined/src/generic/decoder.sv
rename to src/generic/decoder.sv
diff --git a/pipelined/src/generic/flop/flop.sv b/src/generic/flop/flop.sv
similarity index 100%
rename from pipelined/src/generic/flop/flop.sv
rename to src/generic/flop/flop.sv
diff --git a/pipelined/src/generic/flop/flopen.sv b/src/generic/flop/flopen.sv
similarity index 100%
rename from pipelined/src/generic/flop/flopen.sv
rename to src/generic/flop/flopen.sv
diff --git a/pipelined/src/generic/flop/flopenl.sv b/src/generic/flop/flopenl.sv
similarity index 100%
rename from pipelined/src/generic/flop/flopenl.sv
rename to src/generic/flop/flopenl.sv
diff --git a/pipelined/src/generic/flop/flopenr.sv b/src/generic/flop/flopenr.sv
similarity index 100%
rename from pipelined/src/generic/flop/flopenr.sv
rename to src/generic/flop/flopenr.sv
diff --git a/pipelined/src/generic/flop/flopenrc.sv b/src/generic/flop/flopenrc.sv
similarity index 100%
rename from pipelined/src/generic/flop/flopenrc.sv
rename to src/generic/flop/flopenrc.sv
diff --git a/pipelined/src/generic/flop/flopens.sv b/src/generic/flop/flopens.sv
similarity index 100%
rename from pipelined/src/generic/flop/flopens.sv
rename to src/generic/flop/flopens.sv
diff --git a/pipelined/src/generic/flop/flopr.sv b/src/generic/flop/flopr.sv
similarity index 100%
rename from pipelined/src/generic/flop/flopr.sv
rename to src/generic/flop/flopr.sv
diff --git a/pipelined/src/generic/flop/floprc.sv b/src/generic/flop/floprc.sv
similarity index 100%
rename from pipelined/src/generic/flop/floprc.sv
rename to src/generic/flop/floprc.sv
diff --git a/pipelined/src/generic/flop/synchronizer.sv b/src/generic/flop/synchronizer.sv
similarity index 100%
rename from pipelined/src/generic/flop/synchronizer.sv
rename to src/generic/flop/synchronizer.sv
diff --git a/pipelined/src/generic/lzc.sv b/src/generic/lzc.sv
similarity index 100%
rename from pipelined/src/generic/lzc.sv
rename to src/generic/lzc.sv
diff --git a/pipelined/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv
similarity index 100%
rename from pipelined/src/generic/mem/ram1p1rwbe.sv
rename to src/generic/mem/ram1p1rwbe.sv
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similarity index 100%
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rename to src/generic/mem/ram1p1rwbe_64x128.sv
diff --git a/pipelined/src/generic/mem/ram1p1rwbe_64x44.sv b/src/generic/mem/ram1p1rwbe_64x44.sv
similarity index 100%
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rename to src/generic/mem/ram1p1rwbe_64x44.sv
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similarity index 100%
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rename to src/generic/mem/ram2p1r1wbe.sv
diff --git a/pipelined/src/generic/mem/ram2p1r1wbe_1024x68.sv b/src/generic/mem/ram2p1r1wbe_1024x68.sv
similarity index 100%
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rename to src/generic/mem/ram2p1r1wbe_1024x68.sv
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similarity index 100%
rename from pipelined/src/generic/mem/ram2p1r1wbe_64x32.sv
rename to src/generic/mem/ram2p1r1wbe_64x32.sv
diff --git a/pipelined/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv
similarity index 100%
rename from pipelined/src/generic/mem/rom1p1r.sv
rename to src/generic/mem/rom1p1r.sv
diff --git a/pipelined/src/generic/mem/rom1p1r_128x32.sv b/src/generic/mem/rom1p1r_128x32.sv
similarity index 100%
rename from pipelined/src/generic/mem/rom1p1r_128x32.sv
rename to src/generic/mem/rom1p1r_128x32.sv
diff --git a/pipelined/src/generic/mem/rom1p1r_128x64.sv b/src/generic/mem/rom1p1r_128x64.sv
similarity index 100%
rename from pipelined/src/generic/mem/rom1p1r_128x64.sv
rename to src/generic/mem/rom1p1r_128x64.sv
diff --git a/pipelined/src/generic/mux.sv b/src/generic/mux.sv
similarity index 100%
rename from pipelined/src/generic/mux.sv
rename to src/generic/mux.sv
diff --git a/pipelined/src/generic/neg.sv b/src/generic/neg.sv
similarity index 100%
rename from pipelined/src/generic/neg.sv
rename to src/generic/neg.sv
diff --git a/pipelined/src/generic/onehotdecoder.sv b/src/generic/onehotdecoder.sv
similarity index 100%
rename from pipelined/src/generic/onehotdecoder.sv
rename to src/generic/onehotdecoder.sv
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similarity index 100%
rename from pipelined/src/generic/or_rows.sv
rename to src/generic/or_rows.sv
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similarity index 100%
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rename to src/generic/priorityonehot.sv
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similarity index 100%
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rename to src/generic/prioritythermometer.sv
diff --git a/pipelined/src/hazard/hazard.sv b/src/hazard/hazard.sv
similarity index 100%
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rename to src/hazard/hazard.sv
diff --git a/pipelined/src/ieu/alu.sv b/src/ieu/alu.sv
similarity index 100%
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rename to src/ieu/alu.sv
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similarity index 100%
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rename to src/ieu/comparator.sv
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similarity index 100%
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rename to src/ieu/controller.sv
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similarity index 100%
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rename to src/ieu/datapath.sv
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similarity index 100%
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rename to src/ieu/extend.sv
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similarity index 100%
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rename to src/ieu/forward.sv
diff --git a/pipelined/src/ieu/ieu.sv b/src/ieu/ieu.sv
similarity index 100%
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rename to src/ieu/ieu.sv
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similarity index 100%
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rename to src/ieu/regfile.sv
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similarity index 100%
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rename to src/ieu/shifter.sv
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similarity index 100%
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rename to src/ifu/CodeAligner.py
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similarity index 100%
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rename to src/ifu/bpred/bpred.sv
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similarity index 100%
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similarity index 100%
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rename to src/ifu/bpred/foldedgshare.sv
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similarity index 100%
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rename to src/ifu/bpred/globalhistory.sv
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similarity index 100%
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rename to src/ifu/bpred/localHistoryPredictor.sv
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similarity index 100%
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similarity index 100%
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rename to src/lsu/atomic.sv
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similarity index 100%
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similarity index 100%
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similarity index 100%
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similarity index 100%
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similarity index 100%
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rename to src/mdu/intdivrestoringstep.sv
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similarity index 100%
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rename to src/mdu/mul.sv
diff --git a/pipelined/src/mmu/adrdec.sv b/src/mmu/adrdec.sv
similarity index 100%
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rename to src/mmu/adrdec.sv
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diff --git a/pipelined/src/mmu/hptw.sv b/src/mmu/hptw.sv
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similarity index 100%
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diff --git a/pipelined/src/mmu/pmachecker.sv b/src/mmu/pmachecker.sv
similarity index 100%
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diff --git a/pipelined/src/mmu/pmpadrdec.sv b/src/mmu/pmpadrdec.sv
similarity index 100%
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diff --git a/pipelined/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv
similarity index 100%
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diff --git a/pipelined/src/mmu/tlb.sv b/src/mmu/tlb.sv
similarity index 100%
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rename to src/mmu/tlb.sv
diff --git a/pipelined/src/mmu/tlbcam.sv b/src/mmu/tlbcam.sv
similarity index 100%
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rename to src/mmu/tlbcam.sv
diff --git a/pipelined/src/mmu/tlbcamline.sv b/src/mmu/tlbcamline.sv
similarity index 100%
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diff --git a/pipelined/src/mmu/tlbcontrol.sv b/src/mmu/tlbcontrol.sv
similarity index 100%
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diff --git a/pipelined/src/mmu/tlblru.sv b/src/mmu/tlblru.sv
similarity index 100%
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diff --git a/pipelined/src/mmu/tlbmixer.sv b/src/mmu/tlbmixer.sv
similarity index 100%
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similarity index 100%
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diff --git a/pipelined/src/mmu/tlbramline.sv b/src/mmu/tlbramline.sv
similarity index 100%
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diff --git a/pipelined/src/mmu/vm64check.sv b/src/mmu/vm64check.sv
similarity index 100%
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diff --git a/pipelined/src/privileged/csr.sv b/src/privileged/csr.sv
similarity index 100%
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diff --git a/pipelined/src/privileged/csrc.sv b/src/privileged/csrc.sv
similarity index 100%
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diff --git a/pipelined/src/privileged/csri.sv b/src/privileged/csri.sv
similarity index 100%
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diff --git a/pipelined/src/privileged/csrm.sv b/src/privileged/csrm.sv
similarity index 100%
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diff --git a/pipelined/src/privileged/csrs.sv b/src/privileged/csrs.sv
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diff --git a/pipelined/src/privileged/csrsr.sv b/src/privileged/csrsr.sv
similarity index 100%
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diff --git a/pipelined/src/privileged/csru.sv b/src/privileged/csru.sv
similarity index 100%
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similarity index 100%
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similarity index 100%
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diff --git a/pipelined/src/privileged/privmode.sv b/src/privileged/privmode.sv
similarity index 100%
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diff --git a/pipelined/src/privileged/privpiperegs.sv b/src/privileged/privpiperegs.sv
similarity index 100%
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diff --git a/pipelined/src/privileged/trap.sv b/src/privileged/trap.sv
similarity index 100%
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diff --git a/pipelined/src/uncore/ahbapbbridge.sv b/src/uncore/ahbapbbridge.sv
similarity index 100%
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rename to src/uncore/ahbapbbridge.sv
diff --git a/pipelined/src/uncore/clint_apb.sv b/src/uncore/clint_apb.sv
similarity index 100%
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rename to src/uncore/clint_apb.sv
diff --git a/pipelined/src/uncore/gpio_apb.sv b/src/uncore/gpio_apb.sv
similarity index 100%
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rename to src/uncore/gpio_apb.sv
diff --git a/pipelined/src/uncore/plic_apb.sv b/src/uncore/plic_apb.sv
similarity index 100%
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diff --git a/pipelined/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv
similarity index 100%
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diff --git a/pipelined/src/uncore/rom_ahb.sv b/src/uncore/rom_ahb.sv
similarity index 100%
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rename to src/uncore/rom_ahb.sv
diff --git a/pipelined/src/uncore/uartPC16550D.sv b/src/uncore/uartPC16550D.sv
similarity index 100%
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rename to src/uncore/uartPC16550D.sv
diff --git a/pipelined/src/uncore/uart_apb.sv b/src/uncore/uart_apb.sv
similarity index 100%
rename from pipelined/src/uncore/uart_apb.sv
rename to src/uncore/uart_apb.sv
diff --git a/pipelined/src/uncore/uncore.sv b/src/uncore/uncore.sv
similarity index 100%
rename from pipelined/src/uncore/uncore.sv
rename to src/uncore/uncore.sv
diff --git a/pipelined/src/wally/cvw.sv b/src/wally/cvw.sv
similarity index 100%
rename from pipelined/src/wally/cvw.sv
rename to src/wally/cvw.sv
diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv
similarity index 100%
rename from pipelined/src/wally/wallypipelinedcore.sv
rename to src/wally/wallypipelinedcore.sv
diff --git a/pipelined/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv
similarity index 100%
rename from pipelined/src/wally/wallypipelinedsoc.sv
rename to src/wally/wallypipelinedsoc.sv
diff --git a/synthDC/Makefile b/synthDC/Makefile
index 81d37e9d2..7ef295434 100755
--- a/synthDC/Makefile
+++ b/synthDC/Makefile
@@ -27,7 +27,7 @@ export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time
 export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash)
 export SAIFPOWER ?= 0
 
-OLDCONFIGDIR ?= ${WALLY}/pipelined/config
+OLDCONFIGDIR ?= ${WALLY}/config
 export CONFIGDIR ?= $(OUTPUTDIR)/hdl/config
 CONFIGFILES	?= $(shell find $(CONFIGDIR) -name rv*_*)
 CONFIGFILESTRIM = $(notdir $(CONFIGFILES))
@@ -102,11 +102,11 @@ endif
 	sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/$@_noPriv/wally-config.vh
 
 ifeq ($(SAIFPOWER), 1)
-	cp -f ../pipelined/regression/power.saif .
+	cp -f ../regression/power.saif .
 endif
 
 ifeq ($(SAIFPOWER), 1)
-	cp -f ../pipelined/regression/power.saif .
+	cp -f ../regression/power.saif .
 endif
 
 freqs: 
diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl
index 9fd86eccc..29a0d3a35 100755
--- a/synthDC/scripts/synth.tcl
+++ b/synthDC/scripts/synth.tcl
@@ -19,7 +19,7 @@ set_host_options -max_cores $::env(MAXCORES)
 # get outputDir and configDir from environment (Makefile)
 set outputDir $::env(OUTPUTDIR)
 set cfg $::env(CONFIGDIR)/$::env(CONFIG)_$::env(MOD)/wally-config.vh
-set hdl_src "../pipelined/src"
+set hdl_src "../src"
 set saifpower $::env(SAIFPOWER)
 set maxopt $::env(MAXOPT)
 set drive $::env(DRIVE)
diff --git a/pipelined/testbench/common/functionName.sv b/testbench/common/functionName.sv
similarity index 100%
rename from pipelined/testbench/common/functionName.sv
rename to testbench/common/functionName.sv
diff --git a/pipelined/testbench/common/instrNameDecTB.sv b/testbench/common/instrNameDecTB.sv
similarity index 100%
rename from pipelined/testbench/common/instrNameDecTB.sv
rename to testbench/common/instrNameDecTB.sv
diff --git a/pipelined/testbench/common/instrTrackerTB.sv b/testbench/common/instrTrackerTB.sv
similarity index 100%
rename from pipelined/testbench/common/instrTrackerTB.sv
rename to testbench/common/instrTrackerTB.sv
diff --git a/pipelined/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv
similarity index 100%
rename from pipelined/testbench/common/wallyTracer.sv
rename to testbench/common/wallyTracer.sv
diff --git a/pipelined/testbench/fp/case.sh b/testbench/fp/case.sh
similarity index 100%
rename from pipelined/testbench/fp/case.sh
rename to testbench/fp/case.sh
diff --git a/pipelined/testbench/sdc/ram2sdLoad.py b/testbench/sdc/ram2sdLoad.py
similarity index 100%
rename from pipelined/testbench/sdc/ram2sdLoad.py
rename to testbench/sdc/ram2sdLoad.py
diff --git a/pipelined/testbench/sdc/ramdisk2.hex b/testbench/sdc/ramdisk2.hex
similarity index 100%
rename from pipelined/testbench/sdc/ramdisk2.hex
rename to testbench/sdc/ramdisk2.hex
diff --git a/pipelined/testbench/sdc/run_tb.do b/testbench/sdc/run_tb.do
similarity index 100%
rename from pipelined/testbench/sdc/run_tb.do
rename to testbench/sdc/run_tb.do
diff --git a/pipelined/testbench/sdc/sdModel.sv b/testbench/sdc/sdModel.sv
similarity index 100%
rename from pipelined/testbench/sdc/sdModel.sv
rename to testbench/sdc/sdModel.sv
diff --git a/pipelined/testbench/sdc/sd_crc_16.sv b/testbench/sdc/sd_crc_16.sv
similarity index 100%
rename from pipelined/testbench/sdc/sd_crc_16.sv
rename to testbench/sdc/sd_crc_16.sv
diff --git a/pipelined/testbench/sdc/sd_crc_7.sv b/testbench/sdc/sd_crc_7.sv
similarity index 100%
rename from pipelined/testbench/sdc/sd_crc_7.sv
rename to testbench/sdc/sd_crc_7.sv
diff --git a/pipelined/testbench/sdc/sd_defines.h b/testbench/sdc/sd_defines.h
similarity index 100%
rename from pipelined/testbench/sdc/sd_defines.h
rename to testbench/sdc/sd_defines.h
diff --git a/pipelined/testbench/sdc/sd_top_tb.sv b/testbench/sdc/sd_top_tb.sv
similarity index 100%
rename from pipelined/testbench/sdc/sd_top_tb.sv
rename to testbench/sdc/sd_top_tb.sv
diff --git a/pipelined/testbench/sdc/wave.do b/testbench/sdc/wave.do
similarity index 100%
rename from pipelined/testbench/sdc/wave.do
rename to testbench/sdc/wave.do
diff --git a/pipelined/testbench/testbench-fp.sv b/testbench/testbench-fp.sv
similarity index 99%
rename from pipelined/testbench/testbench-fp.sv
rename to testbench/testbench-fp.sv
index 62a739c40..8d6826b70 100644
--- a/pipelined/testbench/testbench-fp.sv
+++ b/testbench/testbench-fp.sv
@@ -31,7 +31,7 @@
 
 // steps to run FMA Tests
 //    1) create test vectors in riscv-wally/Tests/fp with: ./run-all.sh
-//    2) go to riscv-wally/pipelined/testbench/fp/Tests
+//    2) go to cvw/testbench/fp/Tests
 //    3) run ./sim-fma-batch
 module testbenchfp;
   parameter TEST="none";
diff --git a/pipelined/testbench/testbench-linux.sv b/testbench/testbench-linux.sv
similarity index 100%
rename from pipelined/testbench/testbench-linux.sv
rename to testbench/testbench-linux.sv
diff --git a/pipelined/testbench/testbench.sv b/testbench/testbench.sv
similarity index 99%
rename from pipelined/testbench/testbench.sv
rename to testbench/testbench.sv
index 853a6e001..a3fa2c093 100644
--- a/pipelined/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -238,7 +238,7 @@ logic [3:0] dummy;
       else memfilename = {pathname, tests[test], ".elf.memfile"};
       if (`FPGA) begin
         string romfilename, sdcfilename;
-        romfilename = {"../../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
+        romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
         sdcfilename = {"../testbench/sdc/ramdisk2.hex"};   
         $readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
         $readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
diff --git a/pipelined/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv
similarity index 100%
rename from pipelined/testbench/testbench_imperas.sv
rename to testbench/testbench_imperas.sv
diff --git a/pipelined/testbench/tests-fp.vh b/testbench/tests-fp.vh
similarity index 100%
rename from pipelined/testbench/tests-fp.vh
rename to testbench/tests-fp.vh
diff --git a/pipelined/testbench/tests.vh b/testbench/tests.vh
similarity index 99%
rename from pipelined/testbench/tests.vh
rename to testbench/tests.vh
index 1d094254e..f119b0a4e 100644
--- a/pipelined/testbench/tests.vh
+++ b/testbench/tests.vh
@@ -33,13 +33,13 @@
 // *** remove MYIMPERASTEST cases when ported 
 
 string tvpaths[] = '{
-    "../../addins/imperas-riscv-tests/work/",
-    "../../tests/riscof/work/riscv-arch-test/",
-    "../../tests/riscof/work/wally-riscv-arch-test/",
-    "../../tests/imperas-riscv-tests/work/",
-    "../../benchmarks/coremark/work/",
-    "../../addins/embench-iot/",
-    "../../tests/custom/work/"
+    "../addins/imperas-riscv-tests/work/",
+    "../tests/riscof/work/riscv-arch-test/",
+    "../tests/riscof/work/wally-riscv-arch-test/",
+    "../tests/imperas-riscv-tests/work/",
+    "../benchmarks/coremark/work/",
+    "../addins/embench-iot/",
+    "../tests/custom/work/"
     };
 
   string coremark[] = '{
diff --git a/tests/testgen/privileged/run.sh b/tests/testgen/privileged/run.sh
index 1fa3a9d01..414f4f2d5 100755
--- a/tests/testgen/privileged/run.sh
+++ b/tests/testgen/privileged/run.sh
@@ -11,7 +11,7 @@ printf "\n\n#####\nStarting tests for $1\n#####\n\n"
 
 if [[ "$2" != "-simonly" ]]
 then
-	cd $WALLY/pipelined/testgen/privileged
+	cd $WALLY/testgen/privileged
 	python3 "testgen-$1.py"
 	printf "\n\n#####\nRan testgen-$1.py Making...\n#####\n\n\n"
 
@@ -48,7 +48,7 @@ fi
 if [[ "$2" == "-sim" || "$2" == "-simonly" ]]
 then
 	printf "\n\n\n#####\nSimulating!\n#####\n\n"
-	cd $WALLY/pipelined/regression
+	cd $WALLY/regression
 	vsim -do wally-privileged.do -c
 fi
 

From 80f42a8638a104955c0fe826ab16b0a3ea4616c2 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 2 Feb 2023 14:48:23 -0800
Subject: [PATCH 05/71] Renamed regression to sim

---
 .gitignore                                     | 14 +++++++-------
 Install                                        |  2 +-
 Makefile                                       |  4 ++--
 README.md                                      |  2 +-
 benchmarks/coremark/Makefile                   |  4 ++--
 benchmarks/embench/Makefile                    |  2 +-
 setup.imperas.sh                               |  2 +-
 {regression => sim}/Makefile                   | 18 +++++++++---------
 {regression => sim}/buildrootBugFinder.py      |  0
 {regression => sim}/fpga-wave.do               |  0
 {regression => sim}/imperas.ic                 |  0
 {regression => sim}/lint-wally                 |  0
 {regression => sim}/linux-wave.do              |  0
 {regression => sim}/make-tests.sh              |  0
 {regression => sim}/makefile-memfile           |  2 +-
 {regression => sim}/regression-wally           |  0
 {regression => sim}/run-imperasdv-tests.bash   |  0
 {regression => sim}/sim-buildroot              |  0
 {regression => sim}/sim-buildroot-batch        |  0
 {regression => sim}/sim-imperas                |  0
 {regression => sim}/sim-testfloat              |  0
 {regression => sim}/sim-testfloat-batch        |  0
 {regression => sim}/sim-wally                  |  0
 {regression => sim}/sim-wally-batch            |  0
 .../slack-notifier/slack-notifier.py           |  0
 {regression => sim}/test                       |  0
 {regression => sim}/testfloat.do               |  0
 {regression => sim}/wally-pipelined-batch.do   |  0
 .../wally-pipelined-imperas-no-idv.do          |  0
 {regression => sim}/wally-pipelined-imperas.do |  0
 {regression => sim}/wally-pipelined.do         |  0
 {regression => sim}/wave-all.do                |  0
 {regression => sim}/wave-dos/ahb-muldiv.do     |  0
 {regression => sim}/wave-dos/ahb-waves.do      |  0
 {regression => sim}/wave-dos/cache-waves.do    |  0
 {regression => sim}/wave-dos/default-waves.do  |  0
 {regression => sim}/wave-dos/generic.do        |  0
 {regression => sim}/wave-dos/linux-waves.do    |  0
 .../wave-dos/peripheral-waves.do               |  0
 {regression => sim}/wave-fpu.do                |  0
 {regression => sim}/wave.do                    |  0
 synthDC/Makefile                               |  4 ++--
 tests/testgen/privileged/run.sh                |  2 +-
 43 files changed, 28 insertions(+), 28 deletions(-)
 rename {regression => sim}/Makefile (62%)
 rename {regression => sim}/buildrootBugFinder.py (100%)
 rename {regression => sim}/fpga-wave.do (100%)
 rename {regression => sim}/imperas.ic (100%)
 rename {regression => sim}/lint-wally (100%)
 rename {regression => sim}/linux-wave.do (100%)
 rename {regression => sim}/make-tests.sh (100%)
 rename {regression => sim}/makefile-memfile (99%)
 rename {regression => sim}/regression-wally (100%)
 rename {regression => sim}/run-imperasdv-tests.bash (100%)
 rename {regression => sim}/sim-buildroot (100%)
 rename {regression => sim}/sim-buildroot-batch (100%)
 rename {regression => sim}/sim-imperas (100%)
 rename {regression => sim}/sim-testfloat (100%)
 rename {regression => sim}/sim-testfloat-batch (100%)
 rename {regression => sim}/sim-wally (100%)
 rename {regression => sim}/sim-wally-batch (100%)
 rename {regression => sim}/slack-notifier/slack-notifier.py (100%)
 rename {regression => sim}/test (100%)
 rename {regression => sim}/testfloat.do (100%)
 rename {regression => sim}/wally-pipelined-batch.do (100%)
 rename {regression => sim}/wally-pipelined-imperas-no-idv.do (100%)
 rename {regression => sim}/wally-pipelined-imperas.do (100%)
 rename {regression => sim}/wally-pipelined.do (100%)
 rename {regression => sim}/wave-all.do (100%)
 rename {regression => sim}/wave-dos/ahb-muldiv.do (100%)
 rename {regression => sim}/wave-dos/ahb-waves.do (100%)
 rename {regression => sim}/wave-dos/cache-waves.do (100%)
 rename {regression => sim}/wave-dos/default-waves.do (100%)
 rename {regression => sim}/wave-dos/generic.do (100%)
 rename {regression => sim}/wave-dos/linux-waves.do (100%)
 rename {regression => sim}/wave-dos/peripheral-waves.do (100%)
 rename {regression => sim}/wave-fpu.do (100%)
 rename {regression => sim}/wave.do (100%)

diff --git a/.gitignore b/.gitignore
index b389dd1dd..5619adbff 100644
--- a/.gitignore
+++ b/.gitignore
@@ -42,8 +42,8 @@ tests/linux-testgen/buildroot-image-output
 tests/linux-testgen/buildroot-config-src/main.config.old
 tests/linux-testgen/buildroot-config-src/linux.config.old
 tests/linux-testgen/buildroot-config-src/busybox.config.old
-regression/slack-notifier/slack-webhook-url.txt
-regression/logs
+sim/slack-notifier/slack-webhook-url.txt
+sim/logs
 fpga/generator/IP
 fpga/generator/vivado.*
 fpga/generator/.Xil/*
@@ -79,24 +79,24 @@ synthDC/ppa/plots
 synthDC/wallyplots/
 synthDC/runArchive
 synthDC/hdl
-regression/power.saif
+sim/power.saif
 tests/fp/vectors/*.tv
 synthDC/Summary.csv
-regression/wkdir
+sim/wkdir
 tests/custom/work
 tests/custom/*/*/*.list
 tests/custom/*/*/*.elf
 tests/custom/*/*/*.map
 tests/custom/*/*/*.memfile
 tests/custom/crt0/*.a
-regression/sd_model.log
+sim/sd_model.log
 fpga/src/sdc/*
 fpga/src/sdc.tar.gz
 fpga/src/CopiedFiles_do_not_add_to_repo/*
-regression/branch.log
+sim/branch.log
 /fpga/generator/sim/imp-funcsim.v
 /fpga/generator/sim/imp-timesim.sdf
 /fpga/generator/sim/imp-timesim.v
 /fpga/generator/sim/syn-funcsim.v
 external
-regression/results
+sim/results
diff --git a/Install b/Install
index 46f4d78ec..47a91dddd 100644
--- a/Install
+++ b/Install
@@ -328,6 +328,6 @@ source ./setup.sh        # may require some modification for your system. Always
 
   cd <to location of repo clone>
   make
-  cd regression
+  cd sim
   ./regression-wally       #(depends on having Questa installed)
 
diff --git a/Makefile b/Makefile
index 24ba57e57..1f540b56c 100644
--- a/Makefile
+++ b/Makefile
@@ -15,8 +15,8 @@ install:
 	##ln -s ${RISCV}/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
 
 regression:
-	make -C regression
+	make -C sim
 
 clean:
-	make clean -C regression
+	make clean -C sim
 
diff --git a/README.md b/README.md
index 824c7c176..ce92151ed 100644
--- a/README.md
+++ b/README.md
@@ -53,7 +53,7 @@ Edit setup.sh and change the following lines to point to the path and license se
 
 Run a regression simulation with Questa to prove everything is installed.
 
-	$ cd regression
+	$ cd sim
 	$ ./regression-wally       (depends on having Questa installed)
 
 # Toolchain Installation (Sys Admin)
diff --git a/benchmarks/coremark/Makefile b/benchmarks/coremark/Makefile
index b8235ea94..e0aa6661d 100644
--- a/benchmarks/coremark/Makefile
+++ b/benchmarks/coremark/Makefile
@@ -21,8 +21,8 @@ PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \
 all: $(work_dir)/coremark.bare.riscv.elf.memfile
 
 run:
-	(cd ../../regression && (time vsim -c -do "do wally-pipelined-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
-	cd ../../benchmarks/coremark/
+	(cd ../../sim && (time vsim -c -do "do wally-pipelined-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
+	cd ../benchmarks/coremark/
 #	KMG: added post processing script to give out branch miss proportion along with other stats to the coremark test
 	python3 coremark-postprocess.py
 
diff --git a/benchmarks/embench/Makefile b/benchmarks/embench/Makefile
index b5030d119..0d619c90b 100644
--- a/benchmarks/embench/Makefile
+++ b/benchmarks/embench/Makefile
@@ -34,7 +34,7 @@ sim: modelsim_build_memfile modelsim_run speed
 
 # launches modelsim to simulate tests on wally
 modelsim_run:
-	(cd ../../regression/ && vsim -c -do "do wally-pipelined-batch.do rv32gc embench")
+	(cd ../../sim/ && vsim -c -do "do wally-pipelined-batch.do rv32gc embench")
 	cd ../../benchmarks/embench/
 
 # builds the objdump based on the compiled c elf files
diff --git a/setup.imperas.sh b/setup.imperas.sh
index 4e30fb07f..755a298b5 100644
--- a/setup.imperas.sh
+++ b/setup.imperas.sh
@@ -31,7 +31,7 @@ export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC
 # setup QUESTA (Imperas only command, YMMV)
 svsetup -questa
 
-pushd regression
+pushd sim
     # With IDV
     IMPERAS_TOOLS=$(pwd)/imperas.ic \
         OTHERFLAGS="+TRACE2LOG_ENABLE=1 VERBOSE=1" \
diff --git a/regression/Makefile b/sim/Makefile
similarity index 62%
rename from regression/Makefile
rename to sim/Makefile
index adc7bc718..6a917bcda 100644
--- a/regression/Makefile
+++ b/sim/Makefile
@@ -2,27 +2,27 @@ all: riscoftests memfiles
 	# *** Build old tests/imperas-riscv-tests for now;
 	# Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test
 	# DH: 2/27/22 temporarily commented out imperas-riscv-tests because license expired
-	#make -C ../../tests/imperas-riscv-tests --jobs
-	#make -C ../../tests/imperas-riscv-tests XLEN=64 --jobs
+	#make -C ../tests/imperas-riscv-tests --jobs
+	#make -C ../tests/imperas-riscv-tests XLEN=64 --jobs
 	# Only compile Imperas tests if they are installed locally.  
 	# They are usually a symlink to $RISCV/imperas-riscv-tests and only 
 	# get compiled there manually during installation
-	#make -C ../../addins/imperas-riscv-tests
-	#make -C ../../addins/imperas-riscv-tests XLEN=64
-	#cd ../../addins/imperas-riscv-tests; elf2hex.sh
-	#cd ../../addins/imperas-riscv-tests; extractFunctionRadix.sh work/*/*/*.elf.objdump
+	#make -C ../addins/imperas-riscv-tests
+	#make -C ../addins/imperas-riscv-tests XLEN=64
+	#cd ../addins/imperas-riscv-tests; elf2hex.sh
+	#cd ../addins/imperas-riscv-tests; extractFunctionRadix.sh work/*/*/*.elf.objdump
 	# Link Linux test vectors 
-	#cd ../../tests/linux-testgen/linux-testvectors/;./tvLinker.sh
+	#cd ../tests/linux-testgen/linux-testvectors/;./tvLinker.sh
 
 allclean: clean all
 
 clean:
-	make clean -C ../../tests/riscof
+	make clean -C ../tests/riscof
 #   make clean -C ../../tests/wally-riscv-arch-test
 #	make allclean -C ../../tests/imperas-riscv-tests
 
 riscoftests: 
 # 	Builds riscv-arch-test 64 and 32-bit versions and builds wally-riscv-arch-test 64 and 32-bit versions
-	make -C ../../tests/riscof/ 
+	make -C ../tests/riscof/ 
 memfiles:
 	make -f makefile-memfile wally-sim-files --jobs
diff --git a/regression/buildrootBugFinder.py b/sim/buildrootBugFinder.py
similarity index 100%
rename from regression/buildrootBugFinder.py
rename to sim/buildrootBugFinder.py
diff --git a/regression/fpga-wave.do b/sim/fpga-wave.do
similarity index 100%
rename from regression/fpga-wave.do
rename to sim/fpga-wave.do
diff --git a/regression/imperas.ic b/sim/imperas.ic
similarity index 100%
rename from regression/imperas.ic
rename to sim/imperas.ic
diff --git a/regression/lint-wally b/sim/lint-wally
similarity index 100%
rename from regression/lint-wally
rename to sim/lint-wally
diff --git a/regression/linux-wave.do b/sim/linux-wave.do
similarity index 100%
rename from regression/linux-wave.do
rename to sim/linux-wave.do
diff --git a/regression/make-tests.sh b/sim/make-tests.sh
similarity index 100%
rename from regression/make-tests.sh
rename to sim/make-tests.sh
diff --git a/regression/makefile-memfile b/sim/makefile-memfile
similarity index 99%
rename from regression/makefile-memfile
rename to sim/makefile-memfile
index 646da5ac3..6c2da42fa 100644
--- a/regression/makefile-memfile
+++ b/sim/makefile-memfile
@@ -1,4 +1,4 @@
-ROOT	:= ../..
+ROOT	:= ..
 SUFFIX	:= work
 ARCHDIR	:= $(ROOT)/tests/riscof
 WALLYDIR:= $(ROOT)/tests/wally-riscv-arch-test
diff --git a/regression/regression-wally b/sim/regression-wally
similarity index 100%
rename from regression/regression-wally
rename to sim/regression-wally
diff --git a/regression/run-imperasdv-tests.bash b/sim/run-imperasdv-tests.bash
similarity index 100%
rename from regression/run-imperasdv-tests.bash
rename to sim/run-imperasdv-tests.bash
diff --git a/regression/sim-buildroot b/sim/sim-buildroot
similarity index 100%
rename from regression/sim-buildroot
rename to sim/sim-buildroot
diff --git a/regression/sim-buildroot-batch b/sim/sim-buildroot-batch
similarity index 100%
rename from regression/sim-buildroot-batch
rename to sim/sim-buildroot-batch
diff --git a/regression/sim-imperas b/sim/sim-imperas
similarity index 100%
rename from regression/sim-imperas
rename to sim/sim-imperas
diff --git a/regression/sim-testfloat b/sim/sim-testfloat
similarity index 100%
rename from regression/sim-testfloat
rename to sim/sim-testfloat
diff --git a/regression/sim-testfloat-batch b/sim/sim-testfloat-batch
similarity index 100%
rename from regression/sim-testfloat-batch
rename to sim/sim-testfloat-batch
diff --git a/regression/sim-wally b/sim/sim-wally
similarity index 100%
rename from regression/sim-wally
rename to sim/sim-wally
diff --git a/regression/sim-wally-batch b/sim/sim-wally-batch
similarity index 100%
rename from regression/sim-wally-batch
rename to sim/sim-wally-batch
diff --git a/regression/slack-notifier/slack-notifier.py b/sim/slack-notifier/slack-notifier.py
similarity index 100%
rename from regression/slack-notifier/slack-notifier.py
rename to sim/slack-notifier/slack-notifier.py
diff --git a/regression/test b/sim/test
similarity index 100%
rename from regression/test
rename to sim/test
diff --git a/regression/testfloat.do b/sim/testfloat.do
similarity index 100%
rename from regression/testfloat.do
rename to sim/testfloat.do
diff --git a/regression/wally-pipelined-batch.do b/sim/wally-pipelined-batch.do
similarity index 100%
rename from regression/wally-pipelined-batch.do
rename to sim/wally-pipelined-batch.do
diff --git a/regression/wally-pipelined-imperas-no-idv.do b/sim/wally-pipelined-imperas-no-idv.do
similarity index 100%
rename from regression/wally-pipelined-imperas-no-idv.do
rename to sim/wally-pipelined-imperas-no-idv.do
diff --git a/regression/wally-pipelined-imperas.do b/sim/wally-pipelined-imperas.do
similarity index 100%
rename from regression/wally-pipelined-imperas.do
rename to sim/wally-pipelined-imperas.do
diff --git a/regression/wally-pipelined.do b/sim/wally-pipelined.do
similarity index 100%
rename from regression/wally-pipelined.do
rename to sim/wally-pipelined.do
diff --git a/regression/wave-all.do b/sim/wave-all.do
similarity index 100%
rename from regression/wave-all.do
rename to sim/wave-all.do
diff --git a/regression/wave-dos/ahb-muldiv.do b/sim/wave-dos/ahb-muldiv.do
similarity index 100%
rename from regression/wave-dos/ahb-muldiv.do
rename to sim/wave-dos/ahb-muldiv.do
diff --git a/regression/wave-dos/ahb-waves.do b/sim/wave-dos/ahb-waves.do
similarity index 100%
rename from regression/wave-dos/ahb-waves.do
rename to sim/wave-dos/ahb-waves.do
diff --git a/regression/wave-dos/cache-waves.do b/sim/wave-dos/cache-waves.do
similarity index 100%
rename from regression/wave-dos/cache-waves.do
rename to sim/wave-dos/cache-waves.do
diff --git a/regression/wave-dos/default-waves.do b/sim/wave-dos/default-waves.do
similarity index 100%
rename from regression/wave-dos/default-waves.do
rename to sim/wave-dos/default-waves.do
diff --git a/regression/wave-dos/generic.do b/sim/wave-dos/generic.do
similarity index 100%
rename from regression/wave-dos/generic.do
rename to sim/wave-dos/generic.do
diff --git a/regression/wave-dos/linux-waves.do b/sim/wave-dos/linux-waves.do
similarity index 100%
rename from regression/wave-dos/linux-waves.do
rename to sim/wave-dos/linux-waves.do
diff --git a/regression/wave-dos/peripheral-waves.do b/sim/wave-dos/peripheral-waves.do
similarity index 100%
rename from regression/wave-dos/peripheral-waves.do
rename to sim/wave-dos/peripheral-waves.do
diff --git a/regression/wave-fpu.do b/sim/wave-fpu.do
similarity index 100%
rename from regression/wave-fpu.do
rename to sim/wave-fpu.do
diff --git a/regression/wave.do b/sim/wave.do
similarity index 100%
rename from regression/wave.do
rename to sim/wave.do
diff --git a/synthDC/Makefile b/synthDC/Makefile
index 7ef295434..f13b38ab6 100755
--- a/synthDC/Makefile
+++ b/synthDC/Makefile
@@ -102,11 +102,11 @@ endif
 	sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/$@_noPriv/wally-config.vh
 
 ifeq ($(SAIFPOWER), 1)
-	cp -f ../regression/power.saif .
+	cp -f ../sim/power.saif .
 endif
 
 ifeq ($(SAIFPOWER), 1)
-	cp -f ../regression/power.saif .
+	cp -f ../sim/power.saif .
 endif
 
 freqs: 
diff --git a/tests/testgen/privileged/run.sh b/tests/testgen/privileged/run.sh
index 414f4f2d5..d1afb4e89 100755
--- a/tests/testgen/privileged/run.sh
+++ b/tests/testgen/privileged/run.sh
@@ -48,7 +48,7 @@ fi
 if [[ "$2" == "-sim" || "$2" == "-simonly" ]]
 then
 	printf "\n\n\n#####\nSimulating!\n#####\n\n"
-	cd $WALLY/regression
+	cd $WALLY/sim
 	vsim -do wally-privileged.do -c
 fi
 

From 644dfe7463fb617c34e97399e5076410970b0a0e Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 2 Feb 2023 19:40:41 -0800
Subject: [PATCH 06/71] Removed lab1matrix solutions

---
 examples/C/lab1matrix/Makefile  |  33 ------------
 examples/C/lab1matrix/matMult   | Bin 43352 -> 0 bytes
 examples/C/lab1matrix/matMult.c |  87 --------------------------------
 3 files changed, 120 deletions(-)
 delete mode 100644 examples/C/lab1matrix/Makefile
 delete mode 100755 examples/C/lab1matrix/matMult
 delete mode 100644 examples/C/lab1matrix/matMult.c

diff --git a/examples/C/lab1matrix/Makefile b/examples/C/lab1matrix/Makefile
deleted file mode 100644
index 18c011f4f..000000000
--- a/examples/C/lab1matrix/Makefile
+++ /dev/null
@@ -1,33 +0,0 @@
-TARGET = matMult
-
-$(TARGET).objdump: $(TARGET)
-	riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump
-	spike $(TARGET)
-    
-$(TARGET): $(TARGET).c Makefile
-	riscv64-unknown-elf-gcc -o $(TARGET) -g -O\
-	  -march=rv64gc -mabi=lp64d -mcmodel=medany \
-	  -nostdlib -static -lm -fno-tree-loop-distribute-patterns \
-	  -T../common/test.ld -I../common \
-	  $(TARGET).c ../common/crt.S ../common/syscalls.c
-# Compiler flags:
-#  -o $(TARGET) defines the name of the output file
-#  -g generates debugging symbols for gdb
-#  -O turns on basic optimization; -O3 turns on heavy optimization; omit for no optimization
-#  -march=rv64gc -mabi=lp64d =mcmodel=medany generates code for RV64GC with doubles and long/ptrs = 64 bits
-#  -static forces static linking (no dynamic shared libraries on bare metal)
-#  -lm links the math library if necessary (when #include math.h)
-#  -nostdlib avoids inserting standard startup files and default libraries 
-#     because we are using crt.s on bare metal
-#  -fno-tree-loop-distribute-patterns turns replacing loops with memcpy/memset in the std library 
-#  -T specifies the linker file
-#  -I specifies the include path (e.g. for util.h)
-#  The last line defines the C files to compile.  
-#    crt.S is needed as our startup file to initialize the processor
-#    syscalls.c implements printf through the HTIF for Spike
-# other flags from riscv-tests makefiles that don't seem to be important
-#	  -ffast-math -DPREALLOCATE=1 -std=gnu99  \
-#     -fno-common -fno-builtin-printf -nostartfiles -lgcc \
-
-clean:
-	rm -f $(TARGET) $(TARGET).objdump
diff --git a/examples/C/lab1matrix/matMult b/examples/C/lab1matrix/matMult
deleted file mode 100755
index e3d3b25dd44f3d863bf10fb093a7f51972edf99a..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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zqtlwmD=jNoR)MjX*DzdMQc_p8oNJXe0XpP5l*M($)fG5c8pgWnim2vFI@g#s^vWQi
zVM)~Ke1*V(E_A;j5BDAPEeJ<qc^wX}k@5ULg?ob$p^BO5Tn!2`3HuN=MqKU)n81Pf
zBNEJbeepcY)>Yo$nO0|A;d&l`sQyjf5F<6kdof!9%;czRENa9*+F*HKa_j<)m}Kx=
zusGtOYcl=_X1Tn78FnGH;=eI4p{_dXp{a_?0gy}{Kd*zEF47d)x^O<Ze@0vdK=B*H
zavo&<DNJa}i7|D0WiCcVMZx@U&_*%hilr?<TP%*q7tz9w3wNfYu2|Yyw8r9yq3jyX
zc3odx@@Fh<0~%s+MEf!={J3t@h4Y!}KpMCe#o725Ez|9n#x%xM#m?{G-)Rnl|4I`i
z;)><}7qk&>WCRU?GjG?3r#Uc8JM(jS0Qj@<C*GkM9%sVu;D6>j_@8al46!>)7RTl9
zKn4}bjZxR14ZoQNP8;(v;vE37IBM(h6HW1Q%=lyDpLluhX%78)j5c7nc6oG3VT@n;
sR&#|gJ?H}$od{yOQ25RFs6rIQC>K*zJMy#fAKk6_KhcHr8O#6w07E3%>;M1&

diff --git a/examples/C/lab1matrix/matMult.c b/examples/C/lab1matrix/matMult.c
deleted file mode 100644
index b794819f9..000000000
--- a/examples/C/lab1matrix/matMult.c
+++ /dev/null
@@ -1,87 +0,0 @@
-// matMult.c
-// mmasserfrye@hmc.edu 30 January 2022
-
-#include <stdio.h>  // supports printf
-#include <math.h>   // supports fabs
-#include "util.h"   // supports verify
-
-// puts the indicated row of length n from matrix mat into array arr
-void getRow(int n, int row, double *mat, double *arr){
-    int ind;
-    for (int i=0; i<n; i++){
-        ind = i+row*n;
-        arr[i] = mat[ind];
-    }
-}
-
-// computes the dot product of arrays a and b of length n
-double dotproduct(int n, double a[], double b[]) {
-
-    volatile int i;
-    double sum;
-    sum = 0;
-
-    for (i=0; i<n; i++) {
-        if (i==0) sum=0;
-        sum += a[i]*b[i];
-    }
-    return sum;
-}
-
-// multiplies matrices A (m1 x n1m2) and B (n1m2 x n2) and puts the result in Y
-void mult(int m1, int n1m2, int n2, double *A, double *B, double *Y) {
-
-    // transpose B into Bt so we can dot product matching rows
-    double Bt[n2*n1m2];
-    int ind;
-    int indt;
-    for (int i=0; i<n1m2; i++){
-        for (int j=0; j<n2; j++){
-            ind = i*n2+j;
-            indt = j*n1m2+i;
-            Bt[indt] = B[ind];
-        }
-    }
-
-    int indY;
-    double Arow[n1m2];
-    double Bcol[n1m2];
-
-    for (int i=0; i<m1; i++){
-        for (int j=0; j<n2; j++){
-            indY = i*n2+j;
-            getRow(n1m2, i, A, Arow);
-            getRow(n1m2, j, Bt, Bcol);
-            Y[indY] = dotproduct(n1m2, Arow, Bcol);
-        }
-    }
-}
-
-int main(void) {
-
-    // change these bits to test stuff
-    int m = 20;
-    int n = 1;
-    double X[20]; // change to m*n
-    double Y[400]; // change to m^2
-
-    // fill in some numbers so the test feels legit
-    for (int i=0; i<n; i++){
-        X[i] = i;
-    }
- 
-    setStats(1);
-    mult(m, n, m, X, X, Y);
-    setStats(0);
-
-    /*
-    // use this code from Harris's fir.c to print matrix one element at a time
-    // library linked doesn't support printing doubles, so convert to integers to print
-    for (int i=0; i<m*m; i++)  {
-        int tmp = Y[i];
-        printf("Y[%d] = %d\n", i, tmp);
-    }
-    */
-    return 0;
-    
-}
\ No newline at end of file

From 4dca69f20537049a8a52f0c191744866b1692dee Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Fri, 3 Feb 2023 08:36:03 -0800
Subject: [PATCH 07/71] Updated division radix test script with paths, but
 script is out of date for files it manipulates

---
 bin/radixcopiesmultiregression.sh | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/bin/radixcopiesmultiregression.sh b/bin/radixcopiesmultiregression.sh
index 1953b1da4..f701dada2 100755
--- a/bin/radixcopiesmultiregression.sh
+++ b/bin/radixcopiesmultiregression.sh
@@ -10,39 +10,39 @@ currCopies="define DIVCOPIES 32'h1"
 sed -i "s/$searchRadix/$currRadix/" $configFile
 sed -i "s/$searchCopies/$currCopies/" $configFile
 echo regression on Radix :$currRadix: and Copies :$currCopies:
-./regression/regression-wally
+./sim/regression-wally
 
 currRadix="define RADIX 32'h2"
 currCopies="define DIVCOPIES 32'h2"
 sed -i "s/$searchRadix/$currRadix/" $configFile
 sed -i "s/$searchCopies/$currCopies/" $configFile
 echo regression on Radix :$currRadix: and Copies :$currCopies:
-./regression/regression-wally
+./sim/regression-wally
 
 currRadix="define RADIX 32'h2"
 currCopies="define DIVCOPIES 32'h4"
 sed -i "s/$searchRadix/$currRadix/" $configFile
 sed -i "s/$searchCopies/$currCopies/" $configFile
 echo regression on Radix :$currRadix: and Copies :$currCopies:
-./regression/regression-wally
+./sim/regression-wally
 
 currRadix="define RADIX 32'h4"
 currCopies="define DIVCOPIES 32'h1"
 sed -i "s/$searchRadix/$currRadix/" $configFile
 sed -i "s/$searchCopies/$currCopies/" $configFile
 echo regression on Radix :$currRadix: and Copies :$currCopies:
-./regression/regression-wally
+./sim/regression-wally
 
 currRadix="define RADIX 32'h4"
 currCopies="define DIVCOPIES 32'h2"
 sed -i "s/$searchRadix/$currRadix/" $configFile
 sed -i "s/$searchCopies/$currCopies/" $configFile
 echo regression on Radix :$currRadix: and Copies :$currCopies:
-./regression/regression-wally
+./sim/regression-wally
 
 currRadix="define RADIX 32'h4"
 currCopies="define DIVCOPIES 32'h4"
 sed -i "s/$searchRadix/$currRadix/" $configFile
 sed -i "s/$searchCopies/$currCopies/" $configFile
 echo regression on Radix :$currRadix: and Copies :$currCopies:
-./regression/regression-wally
\ No newline at end of file
+./sim/regression-wally
\ No newline at end of file

From 34fbfeb5cdaea5a514f577177452866696a649f0 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Fri, 3 Feb 2023 08:36:51 -0800
Subject: [PATCH 08/71] Removed redundant line from synthesis makefile

---
 synthDC/Makefile | 1 -
 1 file changed, 1 deletion(-)

diff --git a/synthDC/Makefile b/synthDC/Makefile
index f13b38ab6..c715a88b4 100755
--- a/synthDC/Makefile
+++ b/synthDC/Makefile
@@ -24,7 +24,6 @@ export DRIVE ?= FLOP
 time := $(shell date +%F-%H-%M)
 hash := $(shell git rev-parse --short HEAD)
 export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash)
-export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash)
 export SAIFPOWER ?= 0
 
 OLDCONFIGDIR ?= ${WALLY}/config

From 583d87afc7c07b9137b3d412cb67c328c6513a73 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Fri, 3 Feb 2023 17:40:20 -0600
Subject: [PATCH 09/71] Change CurrPtr to Ptr in RAS.

---
 pipelined/src/ifu/bpred/RASPredictor.sv | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/pipelined/src/ifu/bpred/RASPredictor.sv b/pipelined/src/ifu/bpred/RASPredictor.sv
index f71cb48f4..624d8e641 100644
--- a/pipelined/src/ifu/bpred/RASPredictor.sv
+++ b/pipelined/src/ifu/bpred/RASPredictor.sv
@@ -42,7 +42,7 @@ module RASPredictor #(parameter int StackSize = 16 )(
   logic                     CounterEn;
   localparam Depth = $clog2(StackSize);
 
-  logic [Depth-1:0]         NextPtr, CurrPtr, PtrP1, PtrM1;
+  logic [Depth-1:0]         NextPtr, Ptr, PtrP1, PtrM1;
   logic [StackSize-1:0]     [`XLEN-1:0] memory;
   integer        index;
 
@@ -73,10 +73,10 @@ module RASPredictor #(parameter int StackSize = 16 )(
   assign DecrementPtr = (PopF | DecRepairD) & ~IncrRepairD;
   mux2 #(Depth) PtrMux(PtrP1, PtrM1, DecrementPtr, NextPtr);
 
-  assign PtrM1 = CurrPtr - 1'b1;
-  assign PtrP1 = CurrPtr + 1'b1;
+  assign PtrM1 = Ptr - 1'b1;
+  assign PtrP1 = Ptr + 1'b1;
 
-  flopenr #(Depth) PTR(clk, reset, CounterEn, NextPtr, CurrPtr);
+  flopenr #(Depth) PTR(clk, reset, CounterEn, NextPtr, Ptr);
 
   // RAS must be reset. 
   always_ff @ (posedge clk) begin
@@ -88,7 +88,7 @@ module RASPredictor #(parameter int StackSize = 16 )(
     end
   end
 
-  assign RASPCF = memory[CurrPtr];
+  assign RASPCF = memory[Ptr];
   
   
 endmodule

From f5468ebd7ac8a689db528af2225764fe4ef61e34 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Fri, 3 Feb 2023 18:19:47 -0600
Subject: [PATCH 10/71] Replaced PCLinkX registers with a +2/4 adder in the
 execution stage. David and I estimate this is lower hardware cost.

---
 pipelined/src/ifu/ifu.sv   | 20 ++++++++++----------
 pipelined/src/ifu/spill.sv |  5 ++++-
 2 files changed, 14 insertions(+), 11 deletions(-)

diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index c64049909..956144de2 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -109,6 +109,8 @@ module ifu (
   logic [31:0] 				   ICacheInstrF;                          // Instruction from the I$
   logic [31:0] 				   InstrRawF;                             // Instruction from the IROM, I$, or bus
   logic                        CompressedF;                           // The fetched instruction is compressed
+  logic                        CompressedD;                           // The decoded instruction is compressed
+  logic                        CompressedE;                           // The execution instruction is compressed
   logic [31:0] 				   PostSpillInstrRawF;                    // Fetch instruction after merge two halves of spill
   logic [31:0] 				   InstrRawD;                             // Non-decompressed instruction in the Decode stage
   
@@ -297,18 +299,11 @@ module ifu (
 
   // pcadder
   // add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32
+  // *** consider using PCPlus2or4F = PCF + CompressedF ? 2 : 4;
   assign PCPlus4F = PCF[`XLEN-1:2] + 1; // add 4 to PC
   // choose PC+2 or PC+4 based on CompressedF, which arrives later. 
   // Speeds up critical path as compared to selecting adder input based on CompressedF
   // *** consider gating PCPlus4F to provide the reset.
-/* -----\/----- EXCLUDED -----\/-----
-  assign PCPlus2or4F[0] = '0;
-  assign PCPlus2or4F[1] = ~reset & (CompressedF ^ PCF[1]);
-  assign PCPlus2or4F[`XLEN-1:2] = reset ? '0 : CompressedF & ~PCF[1] ? PCF[`XLEN-1:2] : PCPlus4F;
- -----/\----- EXCLUDED -----/\----- */
-/* -----\/----- EXCLUDED -----\/-----
-  assign PCPlus2or4F[1:0] = reset ? 2'b00 : CompressedF ? PCF[1] ? 2'b00 : 2'b10 : PCF[1:0];
- -----/\----- EXCLUDED -----/\----- */
 
   // *** There is actually a bug in the regression test.  We fetched an address which returns data with
   // an X.  This version of the code does not die because if CompressedF is an X it just defaults to the last
@@ -377,6 +372,11 @@ module ifu (
   flopenr #(32)    InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM);
   flopenr #(`XLEN) PCEReg(clk, reset, ~StallE, PCD, PCE);
   flopenr #(`XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM);
-  flopenr #(`XLEN) PCPDReg(clk, reset, ~StallD, PCPlus2or4F, PCLinkD);
-  flopenr #(`XLEN) PCPEReg(clk, reset, ~StallE, PCLinkD, PCLinkE);
+  //flopenr #(`XLEN) PCPDReg(clk, reset, ~StallD, PCPlus2or4F, PCLinkD);
+  //flopenr #(`XLEN) PCPEReg(clk, reset, ~StallE, PCLinkD, PCLinkE);
+
+  flopenrc #(1) CompressedDReg(clk, reset, FlushD, ~StallD, CompressedF, CompressedD);
+  flopenrc #(1) CompressedEReg(clk, reset, FlushE, ~StallE, CompressedD, CompressedE);
+  assign PCLinkE = PCE + (CompressedE ? 2 : 4);
+  
 endmodule
diff --git a/pipelined/src/ifu/spill.sv b/pipelined/src/ifu/spill.sv
index aa93c4397..4bb677cab 100644
--- a/pipelined/src/ifu/spill.sv
+++ b/pipelined/src/ifu/spill.sv
@@ -107,6 +107,9 @@ module spill #(
   // merge together
   mux2 #(32) postspillmux(InstrRawF, {InstrRawF[15:0], InstrFirstHalf}, SpillF, PostSpillInstrRawF);
 
-  assign CompressedF = PostSpillInstrRawF[1:0] != 2'b11;
+  // Need to use always comb to avoid pessimistic x propagation if PostSpillInstrRawF is x
+  always_comb
+	if (PostSpillInstrRawF[1:0] != 2'b11) CompressedF = 1'b1;
+	else CompressedF = 1'b0;
 
 endmodule

From b78ce62748f80a870bf11ec079c9d6037e3923a5 Mon Sep 17 00:00:00 2001
From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com>
Date: Sat, 4 Feb 2023 09:50:36 +0000
Subject: [PATCH 11/71] added use sram parameter, cleaned up config writing,
 added single synth functionality to wallySynth

---
 synthDC/Makefile          | 79 +++++++++++++++++----------------------
 synthDC/scripts/synth.tcl |  3 +-
 synthDC/wallySynth.py     | 17 ++++++---
 3 files changed, 47 insertions(+), 52 deletions(-)

diff --git a/synthDC/Makefile b/synthDC/Makefile
index 81d37e9d2..fdfc9e488 100755
--- a/synthDC/Makefile
+++ b/synthDC/Makefile
@@ -12,7 +12,7 @@ export MOD ?= orig
 # title to add a note in the synth's directory name
 TITLE = 
 # tsmc28, sky130, and sky90 presently supported
-export TECH ?= sky90
+export TECH ?= tsmc28
 # MAXCORES allows parallel compilation, which is faster but less CPU-efficient
 # Avoid when doing sweeps of many optimization points in parallel
 export MAXCORES ?= 1
@@ -20,6 +20,7 @@ export MAXCORES ?= 1
 # The output netlist is hard to interpret, but significantly better PPA
 export MAXOPT ?= 0
 export DRIVE ?= FLOP
+export USESRAM ?= 0
 
 time := $(shell date +%F-%H-%M)
 hash := $(shell git rev-parse --short HEAD)
@@ -29,13 +30,7 @@ export SAIFPOWER ?= 0
 
 OLDCONFIGDIR ?= ${WALLY}/pipelined/config
 export CONFIGDIR ?= $(OUTPUTDIR)/hdl/config
-CONFIGFILES	?= $(shell find $(CONFIGDIR) -name rv*_*)
-CONFIGFILESTRIM = $(notdir $(CONFIGFILES))
 
-print:
-	@echo $(FREQS)
-	@echo $(CONFIG)
-	@echo $(CONFIGFILESTRIM)
 
 
 default:
@@ -46,8 +41,6 @@ default:
 
 DIRS32 = rv32e rv32gc rv32imc rv32i
 DIRS64 = rv64i rv64gc
-DIRS32 = rv32e rv32gc rv32ic rv32i
-DIRS64 = rv64i rv64gc
 DIRS = $(DIRS32) $(DIRS64)
 
 # k = 3 6 
@@ -60,57 +53,55 @@ DIRS = $(DIRS32) $(DIRS64)
 configs: $(CONFIG)
 $(CONFIG):
 	@echo $(CONFIG)
-	cp -r $(OLDCONFIGDIR)/$(CONFIG) $(CONFIGDIR)/$(CONFIG)_orig
-	sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
-	sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
-	sed -i 's/BPRED_SIZE.*/BPRED_SIZE 5/g' $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
+	cp -r $(OLDCONFIGDIR)/shared/*.vh $(CONFIGDIR)
+	cp -r $(OLDCONFIGDIR)/$(CONFIG)/* $(CONFIGDIR)
 
-ifneq ($(filter $ $(CONFIG), $(DIRS32)),)
-	sed -i "s/DTIM_RANGE.*/DTIM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
-	sed -i "s/IROM_RANGE.*/IROM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
-	sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
-	sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
-else ifneq ($(filter $ $(CONFIG), $(DIRS64)),)
-	sed -i "s/DTIM_RANGE.*/DTIM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
-	sed -i "s/IROM_RANGE.*/IROM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
-	sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
-	sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/$(CONFIG)_orig/wally-config.vh
+ifeq ($(USESRAM), 1)
+	sed -i 's/USE_SRAM.*/USE_SRAM 1/g' $(CONFIGDIR)/wally-shared.vh
+
+else
+	sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/wally-config.vh
+	sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/wally-config.vh
+	sed -i 's/BPRED_SIZE.*/BPRED_SIZE 5/g' $(CONFIGDIR)/wally-config.vh
+
+ifneq ($(filter $(CONFIG), $(DIRS32)),)
+	sed -i "s/DTIM_RANGE.*/DTIM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh
+	sed -i "s/IROM_RANGE.*/IROM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh
+	sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh
+	sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh
+else ifneq ($(filter $(CONFIG), $(DIRS64)),)
+	sed -i "s/DTIM_RANGE.*/DTIM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh
+	sed -i "s/IROM_RANGE.*/IROM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh
+	sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh
+	sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh
 else 
 	$(info $(CONFIG) does not exist in $(DIRS32) or $(DIRS64))
 	@echo "Config not in list, RAM_RANGE will be unmodified"
 endif
+endif
 	
+ifeq ($(MOD), FPUoff)
 	# turn off FPU 
-	cp -r $(CONFIGDIR)/$@_orig $(CONFIGDIR)/$@_FPUoff
-	sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_FPUoff/wally-config.vh
-	sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_FPUoff/wally-config.vh
-
+	sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/wally-config.vh
+	sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/wally-config.vh
+else ifeq ($(MOD), PMP16)
 	# PMP 16 
-	cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP16
-	sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 16/' $(CONFIGDIR)/$@_PMP16/wally-config.vh
-	
+	sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 16/' $(CONFIGDIR)/wally-config.vh
+else ifeq ($(MOD), PMP0)
 	# PMP 0
-	cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP0
-	sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$@_PMP0/wally-config.vh
-	
+	sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/wally-config.vh
+else ifeq ($(MOD), noMulDiv)
 	# no muldiv
-	cp -r $(CONFIGDIR)/$@_PMP0 $(CONFIGDIR)/$@_noMulDiv
-	sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh
-
+	sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/wally-config.vh
+else ifeq ($(MOD), noPriv)
 	# no priv
-	cp -r $(CONFIGDIR)/$@_noMulDiv $(CONFIGDIR)/$@_noPriv
-	sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/$@_noPriv/wally-config.vh
-
-ifeq ($(SAIFPOWER), 1)
-	cp -f ../pipelined/regression/power.saif .
+	sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/wally-config.vh
 endif
 
 ifeq ($(SAIFPOWER), 1)
 	cp -f ../pipelined/regression/power.saif .
 endif
 
-freqs: 
-	@$(foreach freq, $(FREQS), make synth DESIGN=wallypipelinedcore CONFIG=rv32e FREQ=$(freq) MAXCORES=1;)
 
 mkdirecs:
 	@echo "DC Synthesis"
@@ -129,7 +120,7 @@ rundc:
 	
 	
 clean:
-	rm -rf $(OUTPUTDIR)/hdl
+	rm -rf $(OUTPUTDIR)/hdl/*.sv
 	rm -rf $(OUTPUTDIR)/WORK
 	rm -rf $(OUTPUTDIR)/alib-52
 	rm -f default.svf
diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl
index 9fd86eccc..d7e792569 100755
--- a/synthDC/scripts/synth.tcl
+++ b/synthDC/scripts/synth.tcl
@@ -18,7 +18,7 @@ set_host_options -max_cores $::env(MAXCORES)
 
 # get outputDir and configDir from environment (Makefile)
 set outputDir $::env(OUTPUTDIR)
-set cfg $::env(CONFIGDIR)/$::env(CONFIG)_$::env(MOD)/wally-config.vh
+set cfg $::env(CONFIGDIR)/wally-config.vh
 set hdl_src "../pipelined/src"
 set saifpower $::env(SAIFPOWER)
 set maxopt $::env(MAXOPT)
@@ -26,7 +26,6 @@ set drive $::env(DRIVE)
 
 eval file copy -force $cfg {$outputDir/hdl/}
 eval file copy -force $cfg {$outputDir/}
-eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {$outputDir/hdl/}
 eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/}
 eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/}
 
diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py
index 9ac3a995d..5015b8ca7 100755
--- a/synthDC/wallySynth.py
+++ b/synthDC/wallySynth.py
@@ -5,9 +5,9 @@ import subprocess
 from multiprocessing import Pool
 import argparse
 
-def runSynth(config, mod, tech, freq, maxopt):
+def runSynth(config, mod, tech, freq, maxopt, usesram):
     global pool
-    command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} MAXCORES=1".format(config, mod, tech, freq, maxopt)
+    command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} USESRAM={} MAXCORES=1".format(config, mod, tech, freq, maxopt, usesram)
     pool.map(mask, [command])
 
 def mask(command):
@@ -32,6 +32,7 @@ if __name__ == '__main__':
     parser.add_argument("-t", "--targetfreq", type=int, help = "Target frequncy")
     parser.add_argument("-e", "--tech", choices=techs, help = "Technology")
     parser.add_argument("-o", "--maxopt", action='store_true', help = "Turn on MAXOPT")
+    parser.add_argument("-r", "--usesram", action='store_true', help = "Use SRAM (not flops)")
 
     args = parser.parse_args()
 
@@ -39,17 +40,21 @@ if __name__ == '__main__':
     defaultfreq = 3000 if tech == 'sky90' else 10000
     freq = args.targetfreq if args.targetfreq else defaultfreq
     maxopt = int(args.maxopt)
-    mod = 'orig' # until memory integrated
+    usesram = int(args.usesram)
+    mod = 'orig'
 
     if args.freqsweep:
         sc = args.freqsweep
         config = args.version if args.version else 'rv32e'
         for freq in [round(sc+sc*x/100) for x in freqVaryPct]: # rv32e freq sweep
-            runSynth(config, mod, tech, freq, maxopt)
+            runSynth(config, mod, tech, freq, maxopt, usesram)
     if args.configsweep:
         for config in ['rv32i', 'rv64gc', 'rv64i', 'rv32gc', 'rv32imc', 'rv32e']: #configs
-            runSynth(config, mod, tech, freq, maxopt)
+            runSynth(config, mod, tech, freq, maxopt, usesram)
     if args.featuresweep:
         config = args.version if args.version else 'rv64gc'
         for mod in ['FPUoff', 'noMulDiv', 'noPriv', 'PMP0', 'PMP16']: # rv64gc path variations 'orig', 
-            runSynth(config, mod, tech, freq, maxopt)
+            runSynth(config, mod, tech, freq, maxopt, usesram)
+    else:
+        config = args.version if args.version else 'rv64gc'
+        runSynth(config, mod, tech, freq, maxopt, usesram)
\ No newline at end of file

From 4be41ae25c0ba64901c8cbd4c2f89e78407c3f2f Mon Sep 17 00:00:00 2001
From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com>
Date: Sat, 4 Feb 2023 10:24:01 +0000
Subject: [PATCH 12/71] finishing the job of the last commit

---
 synthDC/Makefile          | 8 ++++----
 synthDC/scripts/synth.tcl | 5 ++---
 synthDC/wallySynth.py     | 4 ++--
 3 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/synthDC/Makefile b/synthDC/Makefile
index fdfc9e488..fd9667942 100755
--- a/synthDC/Makefile
+++ b/synthDC/Makefile
@@ -29,7 +29,7 @@ export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time
 export SAIFPOWER ?= 0
 
 OLDCONFIGDIR ?= ${WALLY}/pipelined/config
-export CONFIGDIR ?= $(OUTPUTDIR)/hdl/config
+export CONFIGDIR ?= $(OUTPUTDIR)/config
 
 
 
@@ -106,8 +106,8 @@ endif
 mkdirecs:
 	@echo "DC Synthesis"
 	@mkdir -p $(OUTPUTDIR)
-	@mkdir -p $(OUTPUTDIR)/hdl/config
-	@mkdir -p $(OUTPUTDIR)/hdl/config
+	@mkdir -p $(OUTPUTDIR)/hdl
+	@mkdir -p $(OUTPUTDIR)/config
 	@mkdir -p $(OUTPUTDIR)/reports
 	@mkdir -p $(OUTPUTDIR)/mapped
 	@mkdir -p $(OUTPUTDIR)/unmapped
@@ -120,7 +120,7 @@ rundc:
 	
 	
 clean:
-	rm -rf $(OUTPUTDIR)/hdl/*.sv
+	rm -rf $(OUTPUTDIR)/hdl
 	rm -rf $(OUTPUTDIR)/WORK
 	rm -rf $(OUTPUTDIR)/alib-52
 	rm -f default.svf
diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl
index d7e792569..ba6e4bb96 100755
--- a/synthDC/scripts/synth.tcl
+++ b/synthDC/scripts/synth.tcl
@@ -18,14 +18,13 @@ set_host_options -max_cores $::env(MAXCORES)
 
 # get outputDir and configDir from environment (Makefile)
 set outputDir $::env(OUTPUTDIR)
-set cfg $::env(CONFIGDIR)/wally-config.vh
+set cfg $::env(CONFIGDIR)
 set hdl_src "../pipelined/src"
 set saifpower $::env(SAIFPOWER)
 set maxopt $::env(MAXOPT)
 set drive $::env(DRIVE)
 
-eval file copy -force $cfg {$outputDir/hdl/}
-eval file copy -force $cfg {$outputDir/}
+eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/}
 eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/}
 eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/}
 
diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py
index 5015b8ca7..3c96c38ee 100755
--- a/synthDC/wallySynth.py
+++ b/synthDC/wallySynth.py
@@ -1,5 +1,5 @@
 #!/usr/bin/python3
-# Madeleine Masser-Frye mmasserfrye@hmc.edu 6/22
+# Madeleine Masser-Frye mmasserfrye@hmc.edu 1/2023
 
 import subprocess
 from multiprocessing import Pool
@@ -32,7 +32,7 @@ if __name__ == '__main__':
     parser.add_argument("-t", "--targetfreq", type=int, help = "Target frequncy")
     parser.add_argument("-e", "--tech", choices=techs, help = "Technology")
     parser.add_argument("-o", "--maxopt", action='store_true', help = "Turn on MAXOPT")
-    parser.add_argument("-r", "--usesram", action='store_true', help = "Use SRAM (not flops)")
+    parser.add_argument("-r", "--usesram", action='store_true', help = "Use SRAM modules")
 
     args = parser.parse_args()
 

From e831baf335ee375386685a297623fb731d06a395 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 4 Feb 2023 03:42:20 -0800
Subject: [PATCH 13/71] Improved illegal NaN-box detection and formatted
 fsgninj

---
 src/fpu/fsgninj.sv     | 18 +++++++++---------
 src/fpu/unpack.sv      | 11 +++++------
 src/fpu/unpackinput.sv | 25 ++++++++++++++-----------
 3 files changed, 28 insertions(+), 26 deletions(-)

diff --git a/src/fpu/fsgninj.sv b/src/fpu/fsgninj.sv
index d5568cabe..0db7dc2f3 100755
--- a/src/fpu/fsgninj.sv
+++ b/src/fpu/fsgninj.sv
@@ -29,11 +29,11 @@
 `include "wally-config.vh"
 
 module fsgninj (  
-	input  logic        		Xs, Ys,	// X and Y sign bits
-	input  logic [`FLEN-1:0] 	X,		// X
-	input  logic [`FMTBITS-1:0]	Fmt,	// format
-	input  logic [1:0]  		OpCtrl,	// operation control
-	output logic [`FLEN-1:0] 	SgnRes	// result
+	input  logic        		    Xs, Ys,	// X and Y sign bits
+	input  logic [`FLEN-1:0] 	  X,		  // X
+	input  logic [`FMTBITS-1:0]	Fmt,	  // format
+	input  logic [1:0]  		    OpCtrl,	// operation control
+	output logic [`FLEN-1:0] 	  SgnRes	// result
 );
 
 	logic ResSgn;	// result sign
@@ -54,13 +54,13 @@ module fsgninj (
 		assign SgnRes = {ResSgn, X[`FLEN-2:0]};
   else if (`FPSIZES == 2)
 		assign SgnRes = {~Fmt|ResSgn, X[`FLEN-2:`LEN1], Fmt ? X[`LEN1-1] : ResSgn, X[`LEN1-2:0]};
-  else if (`FPSIZES == 3) begin
+  else if (`FPSIZES ==  3) begin
 		logic [2:0] SgnBits;
     always_comb
       case (Fmt)
-        `FMT: SgnBits = {ResSgn, X[`LEN1-1], X[`LEN2-1]};
-        `FMT1: SgnBits = {1'b1, ResSgn, X[`LEN2-1]};
-        `FMT2: SgnBits = {2'b11, ResSgn};
+        `FMT:    SgnBits = {ResSgn, X[`LEN1-1], X[`LEN2-1]};
+  	    `FMT1:   SgnBits = {1'b1, ResSgn, X[`LEN2-1]};
+        `FMT2:   SgnBits = {2'b11, ResSgn};
         default: SgnBits = {3{1'bx}};
       endcase
 		assign SgnRes = {SgnBits[2], X[`FLEN-2:`LEN1], SgnBits[1], X[`LEN1-2:`LEN2], SgnBits[0], X[`LEN2-2:0]};
diff --git a/src/fpu/unpack.sv b/src/fpu/unpack.sv
index 13addc2e3..356d7e897 100644
--- a/src/fpu/unpack.sv
+++ b/src/fpu/unpack.sv
@@ -48,15 +48,14 @@ module unpack (
   
   unpackinput unpackinputX (.In(X), .Fmt, .Sgn(Xs), .Exp(Xe), .Man(Xm), .En(XEn),
                           .NaN(XNaN), .SNaN(XSNaN), .ExpNonZero(XExpNonZero),
-                          .Zero(XZero), .Inf(XInf), .ExpMax(XExpMax), .FracZero(XFracZero));
+                          .Zero(XZero), .Inf(XInf), .ExpMax(XExpMax), .FracZero(XFracZero), .Subnorm(XSubnorm));
 
   unpackinput unpackinputY (.In(Y), .Fmt, .Sgn(Ys), .Exp(Ye), .Man(Ym), .En(YEn),
                           .NaN(YNaN), .SNaN(YSNaN), .ExpNonZero(YExpNonZero),
-                          .Zero(YZero), .Inf(YInf), .ExpMax(YExpMax), .FracZero(YFracZero));
+                          .Zero(YZero), .Inf(YInf), .ExpMax(YExpMax), .FracZero(YFracZero), .Subnorm());
 
   unpackinput unpackinputZ (.In(Z), .Fmt, .Sgn(Zs), .Exp(Ze), .Man(Zm), .En(ZEn),
                           .NaN(ZNaN), .SNaN(ZSNaN), .ExpNonZero(ZExpNonZero),
-                          .Zero(ZZero), .Inf(ZInf), .ExpMax(ZExpMax), .FracZero(ZFracZero));
-  // is the input subnormal
-  assign XSubnorm = ~XExpNonZero & ~XFracZero;
-endmodule
\ No newline at end of file
+                          .Zero(ZZero), .Inf(ZInf), .ExpMax(ZExpMax), .FracZero(ZFracZero), .Subnorm());
+ 
+ endmodule
\ No newline at end of file
diff --git a/src/fpu/unpackinput.sv b/src/fpu/unpackinput.sv
index 34663bd8c..b85077d20 100644
--- a/src/fpu/unpackinput.sv
+++ b/src/fpu/unpackinput.sv
@@ -31,16 +31,17 @@ module unpackinput (
   input  logic [`FLEN-1:0]        In,         // inputs from register file
   input  logic                    En,         // enable the input
   input  logic [`FMTBITS-1:0]     Fmt,        // format signal 00 - single 01 - double 11 - quad 10 - half
-  output logic                    Sgn,        // sign bits of XYZ
-  output logic [`NE-1:0]          Exp,        // exponents of XYZ (converted to largest supported precision)
-  output logic [`NF:0]            Man,        // mantissas of XYZ (converted to largest supported precision)
-  output logic                    NaN,        // is XYZ a NaN
-  output logic                    SNaN,       // is XYZ a signaling NaN
-  output logic                    Zero,       // is XYZ zero
-  output logic                    Inf,        // is XYZ infinity
+  output logic                    Sgn,        // sign bits of the number 
+  output logic [`NE-1:0]          Exp,        // exponent of the number  (converted to largest supported precision)
+  output logic [`NF:0]            Man,        // mantissa of the number  (converted to largest supported precision)
+  output logic                    NaN,        // is the number a NaN
+  output logic                    SNaN,       // is the number a signaling NaN
+  output logic                    Zero,       // is the number zero
+  output logic                    Inf,        // is the number infinity
   output logic                    ExpNonZero, // is the exponent not zero
   output logic                    FracZero,   // is the fraction zero
-  output logic                    ExpMax      // does In have the maximum exponent (NaN or Inf)
+  output logic                    ExpMax,      // does In have the maximum exponent (NaN or Inf)
+  output logic                    Subnorm     // is the number subnormal
 );
 
   logic [`NF-1:0] Frac;       // Fraction of XYZ
@@ -261,10 +262,12 @@ module unpackinput (
   end
 
   // Output logic
-  assign FracZero = ~|Frac; // is the fraction zero?
+  assign FracZero = ~|Frac & ~BadNaNBox; // is the fraction zero?
   assign Man = {ExpNonZero, Frac}; // add the assumed one (or zero if Subnormal or zero) to create the significand
   assign NaN = ((ExpMax & ~FracZero)|BadNaNBox)&En; // is the input a NaN?
   assign SNaN = NaN&~Frac[`NF-1]&~BadNaNBox; // is the input a singnaling NaN?
-  assign Inf = ExpMax & FracZero &En; // is the input infinity?
-  assign Zero = ~ExpNonZero & FracZero; // is the input zero?
+  assign Inf = ExpMax & FracZero &En & ~BadNaNBox; // is the input infinity?
+  assign Zero = ~ExpNonZero & FracZero & ~BadNaNBox; // is the input zero?
+  assign Subnorm = ~ExpNonZero & ~FracZero & ~BadNaNBox; // is the input subnormal
+
 endmodule
\ No newline at end of file

From f89e64231215292296e3cf449db931eb34c4d03e Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 4 Feb 2023 04:19:09 -0800
Subject: [PATCH 14/71] ../synthDC/Makefile

---
 synthDC/Makefile | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/synthDC/Makefile b/synthDC/Makefile
index 4d39e7c87..613ca49af 100755
--- a/synthDC/Makefile
+++ b/synthDC/Makefile
@@ -57,27 +57,17 @@ $(CONFIG):
 
 ifeq ($(USESRAM), 1)
 	sed -i 's/USE_SRAM.*/USE_SRAM 1/g' $(CONFIGDIR)/wally-shared.vh
-
 else
 	sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/wally-config.vh
 	sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/wally-config.vh
 	sed -i 's/BPRED_SIZE.*/BPRED_SIZE 5/g' $(CONFIGDIR)/wally-config.vh
 
-  @echo "match32"
-  @echo $(filter $(CONFIG), $(DIRS32))
-  @echo "match64"
-  @echo $(filter $(CONFIG), $(DIRS64))
-
   ifneq ($(filter $(CONFIG), $(DIRS32)),)
     sed -i "s/DTIM_RANGE.*/DTIM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh
     sed -i "s/IROM_RANGE.*/IROM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh
-    sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh
-    sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh
   else ifneq ($(filter $(CONFIG), $(DIRS64)),)
     sed -i "s/DTIM_RANGE.*/DTIM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh
     sed -i "s/IROM_RANGE.*/IROM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh
-    sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh
-    sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh
   else 
     $(info $(CONFIG) does not exist in $(DIRS32) or $(DIRS64))
     @echo "Config not in list, RAM_RANGE will be unmodified"

From be08523ba0f60087e65c43160c4f5a26608fd873 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 4 Feb 2023 04:29:27 -0800
Subject: [PATCH 15/71] Added license headers

---
 Makefile                                    |   4 +
 benchmarks/coremark/Makefile                |   1 +
 benchmarks/coremark/coremark-postprocess.py |  12 +-
 benchmarks/graphGen.py                      |   3 +
 bin/radixcopiesmultiregression.sh           |   2 +
 setup.sh                                    |   1 +
 wallypipelinedcore.sv                       | 360 --------------------
 wallypipelinedsoc.sv                        |  92 -----
 8 files changed, 12 insertions(+), 463 deletions(-)
 delete mode 100644 wallypipelinedcore.sv
 delete mode 100644 wallypipelinedsoc.sv

diff --git a/Makefile b/Makefile
index 1f540b56c..518bcd2dd 100644
--- a/Makefile
+++ b/Makefile
@@ -1,3 +1,7 @@
+# David_Harris@hmc.edu 2023
+# Top-level Makefile for CORE-V-Wally
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
 all:
 	make install
 	make regression
diff --git a/benchmarks/coremark/Makefile b/benchmarks/coremark/Makefile
index e0aa6661d..bb0f20f5a 100644
--- a/benchmarks/coremark/Makefile
+++ b/benchmarks/coremark/Makefile
@@ -1,5 +1,6 @@
 # Wally Coremark Makefile
 # Daniel Torres & David Harris 28 July 2022
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 
 PORT_DIR = $(CURDIR)/riscv64-baremetal
 cmbase=../../addins/coremark
diff --git a/benchmarks/coremark/coremark-postprocess.py b/benchmarks/coremark/coremark-postprocess.py
index d069e8744..f77f2ef8b 100644
--- a/benchmarks/coremark/coremark-postprocess.py
+++ b/benchmarks/coremark/coremark-postprocess.py
@@ -9,17 +9,7 @@
 #
 # Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 #
-# Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-# files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
-# modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
-# is furnished to do so, subject to the following conditions:
-#
-# The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-#
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-# OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
-# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-# OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 ##################################################
 
 logFile = "../../benchmarks/coremark/work/coremark.sim.log"
diff --git a/benchmarks/graphGen.py b/benchmarks/graphGen.py
index de8b70ce9..dd7b3a204 100755
--- a/benchmarks/graphGen.py
+++ b/benchmarks/graphGen.py
@@ -1,4 +1,7 @@
 #!/usr/bin/env python
+# Daniel Torres 2022
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
 import subprocess
 import sys
 import json
diff --git a/bin/radixcopiesmultiregression.sh b/bin/radixcopiesmultiregression.sh
index f701dada2..5d4f3f653 100755
--- a/bin/radixcopiesmultiregression.sh
+++ b/bin/radixcopiesmultiregression.sh
@@ -1,4 +1,6 @@
 #!/bin/bash
+# Alessandro Maiuolo 2022
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 
 configFile=config/shared/wally-shared.vh
 
diff --git a/setup.sh b/setup.sh
index d54ae7bd4..af4bac3b5 100755
--- a/setup.sh
+++ b/setup.sh
@@ -3,6 +3,7 @@
 # setup.sh
 # David_Harris@hmc.edu and kekim@hmc.edu 1 December 2021
 # Set up tools for rvw
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 
 echo "Executing Wally setup.sh"
 
diff --git a/wallypipelinedcore.sv b/wallypipelinedcore.sv
deleted file mode 100644
index 7013d0309..000000000
--- a/wallypipelinedcore.sv
+++ /dev/null
@@ -1,360 +0,0 @@
-///////////////////////////////////////////
-// wallypipelinedcore.sv
-//
-// Written: David_Harris@hmc.edu 9 January 2021
-// Modified: 
-//
-// Purpose: Pipelined RISC-V Processor
-// 
-// Documentation: RISC-V System on Chip Design (Figure 4.1)
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-import cvw::*;  // global CORE-V-Wally parameters
-
-module wallypipelinedcore (
-   input  logic                  clk, reset,
-   // Privileged
-   input  logic                  MTimerInt, MExtInt, SExtInt, MSwInt,
-   input  logic [63:0]           MTIME_CLINT, 
-   // Bus Interface
-   input  logic [AHBW-1:0]       HRDATA,
-   input  logic                  HREADY, HRESP,
-   output logic                  HCLK, HRESETn,
-   output logic [PA_BITS-1:0]    HADDR,
-   output logic [AHBW-1:0]       HWDATA,
-   output logic [XLEN/8-1:0]     HWSTRB,
-   output logic                  HWRITE,
-   output logic [2:0]            HSIZE,
-   output logic [2:0]            HBURST,
-   output logic [3:0]            HPROT,
-   output logic [1:0]            HTRANS,
-   output logic                  HMASTLOCK
-);
-
-  logic                          StallF, StallD, StallE, StallM, StallW;
-  logic                          FlushD, FlushE, FlushM, FlushW;
-  logic                          RetM;
-  logic TrapM;
-
-  //  signals that must connect through DP
-  logic                          IntDivE, W64E;
-  logic                          CSRReadM, CSRWriteM, PrivilegedM;
-  logic [1:0]                    AtomicM;
-  logic [XLEN-1:0]               ForwardedSrcAE, ForwardedSrcBE;
-  logic [XLEN-1:0] 			  SrcAM;
-  logic [2:0]                    Funct3E;
-  logic [31:0]                   InstrD;
-  logic [31:0] 					 InstrM;
-  logic [XLEN-1:0]               PCFSpill, PCE, PCLinkE;
-  logic [XLEN-1:0] 			  PCM;
-  logic [XLEN-1:0]               CSRReadValW, MDUResultW;
-  logic [XLEN-1:0]               UnalignedPCNextF, PCNext2F;
-  logic [1:0] 					 MemRWM;
-  logic 						 InstrValidM;
-  logic                          InstrMisalignedFaultM;
-  logic                          IllegalBaseInstrFaultD, IllegalIEUInstrFaultD;
-  logic                          InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM;
-  logic                          LoadMisalignedFaultM, LoadAccessFaultM;
-  logic                          StoreAmoMisalignedFaultM, StoreAmoAccessFaultM;
-  logic                          InvalidateICacheM, FlushDCacheM;
-  logic                          PCSrcE;
-  logic                          CSRWriteFenceM;
-  logic                          DivBusyE;
-  logic                          LoadStallD, StoreStallD, MDUStallD, CSRRdStallD;
-  logic                          SquashSCW;
-
-  // floating point unit signals
-  logic [2:0]                    FRM_REGW;
-  logic [4:0]                    RdE, RdM, RdW;
-  logic                          FPUStallD;
-  logic                          FWriteIntE;
-  logic [FLEN-1:0]               FWriteDataM;
-  logic [XLEN-1:0]               FIntResM;  
-  logic [XLEN-1:0]              FCvtIntResW; 
-  logic                          FCvtIntW; 
-  logic                          FDivBusyE;
-  logic                          IllegalFPUInstrM;
-  logic                          FRegWriteM;
-  logic                          FCvtIntStallD;
-  logic                          FpLoadStoreM;
-  logic [4:0]                    SetFflagsM;
-  logic [XLEN-1:0]               FIntDivResultW;
-
-  // memory management unit signals
-  logic                          ITLBWriteF;
-  logic                          ITLBMissF;
-  logic [XLEN-1:0]               SATP_REGW;
-  logic                          STATUS_MXR, STATUS_SUM, STATUS_MPRV;
-  logic  [1:0]                   STATUS_MPP, STATUS_FS;
-  logic [1:0]                    PrivilegeModeW;
-  logic [XLEN-1:0]               PTE;
-  logic [1:0]                    PageType;
-  logic                          sfencevmaM, WFIStallM;
-  logic                          SelHPTW;
-
-  // PMA checker signals
-  var logic [XLEN-1:0]           PMPADDR_ARRAY_REGW[PMP_ENTRIES-1:0];
-  var logic [7:0]                PMPCFG_ARRAY_REGW[PMP_ENTRIES-1:0];
-
-  // IMem stalls
-  logic                          IFUStallF;
-  logic                          LSUStallM;
-
-  // cpu lsu interface
-  logic [2:0]                    Funct3M;
-  logic [XLEN-1:0]               IEUAdrE;
-  logic [XLEN-1:0]  WriteDataM;
-  logic [XLEN-1:0]  IEUAdrM;  
-  logic [LLEN-1:0]               ReadDataW;  
-  logic                          CommittedM;
-
-  // AHB ifu interface
-  logic [PA_BITS-1:0]            IFUHADDR;
-  logic [2:0]                    IFUHBURST;
-  logic [1:0]                    IFUHTRANS;
-  logic [2:0]                    IFUHSIZE;
-  logic                          IFUHWRITE;
-  logic                          IFUHREADY;
-  
-  // AHB LSU interface
-  logic [PA_BITS-1:0]            LSUHADDR;
-  logic [XLEN-1:0]               LSUHWDATA;
-  logic [XLEN/8-1:0]             LSUHWSTRB;
-  logic                          LSUHWRITE;
-  logic                          LSUHREADY;
-  
-  logic                          BPPredWrongE, BPPredWrongM;
-  logic                          DirPredictionWrongM;
-  logic                          BTBPredPCWrongM;
-  logic                          RASPredPCWrongM;
-  logic                          PredictionInstrClassWrongM;
-  logic [3:0]                    InstrClassM;
-  logic                          InstrAccessFaultF, HPTWInstrAccessFaultM;
-  logic [2:0]                    LSUHSIZE;
-  logic [2:0]                    LSUHBURST;
-  logic [1:0]                    LSUHTRANS;
-  
-  logic                          DCacheMiss;
-  logic                          DCacheAccess;
-  logic                          ICacheMiss;
-  logic                          ICacheAccess;
-  logic                          BreakpointFaultM, EcallFaultM;
-  logic                          InstrDAPageFaultF;
-  logic                          BigEndianM;
-  logic                          FCvtIntE;
-  logic                          CommittedF;
-  logic 						 JumpOrTakenBranchM;
-  
-  // instruction fetch unit: PC, branch prediction, instruction cache
-  ifu ifu(.clk, .reset,
-    .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-    // Fetch
-    .HRDATA, .PCFSpill, .IFUHADDR, .PCNext2F,
-    .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE,
-    .ICacheAccess, .ICacheMiss,
-    // Execute
-    .PCLinkE, .PCSrcE, .IEUAdrE, .PCE, .BPPredWrongE,  .BPPredWrongM, 
-    // Mem
-    .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM,
-    .InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM, .JumpOrTakenBranchM,
-    .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM,
-    // Faults out
-    .IllegalBaseInstrFaultD, .InstrPageFaultF, .IllegalIEUInstrFaultD, .InstrMisalignedFaultM,
-    // mmu management
-    .PrivilegeModeW, .PTE, .PageType, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV,
-    .STATUS_MPP, .ITLBWriteF, .sfencevmaM, .ITLBMissF,
-    // pmp/pma (inside mmu) signals. 
-    .PMPCFG_ARRAY_REGW,  .PMPADDR_ARRAY_REGW, .InstrAccessFaultF, .InstrDAPageFaultF); 
-    
-  // integer execution unit: integer register file, datapath and controller
-  ieu ieu(.clk, .reset,
-     // Decode Stage interface
-     .InstrD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD,
-     // Execute Stage interface
-     .PCE, .PCLinkE, .FWriteIntE, .FCvtIntE, .IEUAdrE, .IntDivE, .W64E,
-     .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, 
-     // Memory stage interface
-     .SquashSCW, // from LSU
-     .MemRWM, // read/write control goes to LSU
-     .AtomicM, // atomic control goes to LSU
-     .WriteDataM, // Write data to LSU
-     .Funct3M, // size and signedness to LSU
-     .SrcAM, // to privilege and fpu
-     .RdE, .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM,
-     // Writeback stage
-     .CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[XLEN-1:0]),
-     .InstrValidM, .FCvtIntResW, .FCvtIntW,
-     // hazards
-     .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-     .FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD, .PCSrcE,
-     .CSRReadM, .CSRWriteM, .PrivilegedM, .CSRWriteFenceM, .StoreStallD); 
-
-  lsu lsu(
-    .clk, .reset, .StallM, .FlushM, .StallW, .FlushW,
-    // CPU interface
-    .MemRWM, .Funct3M, .Funct7M(InstrM[31:25]), .AtomicM,
-    .CommittedM, .DCacheMiss, .DCacheAccess, .SquashSCW,            
-    .FpLoadStoreM, .FWriteDataM, .IEUAdrE, .IEUAdrM, .WriteDataM,
-    .ReadDataW, .FlushDCacheM,
-    // connected to ahb (all stay the same)
-    .LSUHADDR,  .HRDATA, .LSUHWDATA, .LSUHWSTRB, .LSUHSIZE, 
-    .LSUHBURST, .LSUHTRANS, .LSUHWRITE, .LSUHREADY,
-    // connect to csr or privilege and stay the same.
-    .PrivilegeModeW, .BigEndianM,          // connects to csr
-    .PMPCFG_ARRAY_REGW,     // connects to csr
-    .PMPADDR_ARRAY_REGW,    // connects to csr
-    // hptw keep i/o
-    .SATP_REGW, // from csr
-    .STATUS_MXR, // from csr
-    .STATUS_SUM,  // from csr
-    .STATUS_MPRV,  // from csr            
-    .STATUS_MPP,  // from csr      
-    .sfencevmaM,                   // connects to privilege
-    .LoadPageFaultM,   // connects to privilege
-    .StoreAmoPageFaultM, // connects to privilege
-    .LoadMisalignedFaultM, // connects to privilege
-    .LoadAccessFaultM,         // connects to privilege
-    .HPTWInstrAccessFaultM,         // connects to privilege
-    .StoreAmoMisalignedFaultM, // connects to privilege
-    .StoreAmoAccessFaultM,     // connects to privilege
-    .InstrDAPageFaultF,
-    .PCFSpill, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW,
-    .LSUStallM);                    
-
-  if(BUS_SUPPORTED) begin : ebu
-    ebu ebu(// IFU connections
-      .clk, .reset,
-      // IFU interface
-      .IFUHADDR,
-      .IFUHBURST, 
-      .IFUHTRANS, 
-      .IFUHREADY,
-      .IFUHSIZE,
-      // LSU interface
-      .LSUHADDR,
-      .LSUHWDATA,
-      .LSUHWSTRB,
-      .LSUHSIZE,
-      .LSUHBURST,
-      .LSUHTRANS,
-      .LSUHWRITE,
-      .LSUHREADY,
-      // BUS interface
-      .HREADY, .HRESP, .HCLK, .HRESETn,
-      .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,
-      .HPROT, .HTRANS, .HMASTLOCK);
-  end
-
-  // global stall and flush control  
-  hazard  hzu(
-    .BPPredWrongE, .CSRWriteFenceM, .RetM, .TrapM,
-    .LoadStallD, .StoreStallD, .MDUStallD, .CSRRdStallD,
-    .LSUStallM, .IFUStallF,
-    .FCvtIntStallD, .FPUStallD,
-    .DivBusyE, .FDivBusyE,
-    .EcallFaultM, .BreakpointFaultM,
-    .WFIStallM,
-    // Stall & flush outputs
-    .StallF, .StallD, .StallE, .StallM, .StallW,
-    .FlushD, .FlushE, .FlushM, .FlushW);    
-
-  // privileged unit
-  if (ZICSR_SUPPORTED) begin:priv
-    privileged priv(
-      .clk, .reset,
-      .FlushD, .FlushE, .FlushM, .FlushW, .StallD, .StallE, .StallM, .StallW,
-      .CSRReadM, .CSRWriteM, .SrcAM, .PCM, .PCNext2F,
-      .InstrM, .CSRReadValW, .UnalignedPCNextF,
-      .RetM, .TrapM, .sfencevmaM,
-      .InstrValidM, .CommittedM, .CommittedF,
-      .FRegWriteM, .LoadStallD,
-      .DirPredictionWrongM, .BTBPredPCWrongM, .BPPredWrongM,
-      .RASPredPCWrongM, .PredictionInstrClassWrongM,
-      .InstrClassM, .JumpOrTakenBranchM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
-      .InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM,
-      .InstrMisalignedFaultM, .IllegalIEUInstrFaultD, 
-      .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
-      .MTimerInt, .MExtInt, .SExtInt, .MSwInt,
-      .MTIME_CLINT, .IEUAdrM, .SetFflagsM,
-      .InstrAccessFaultF, .HPTWInstrAccessFaultM, .LoadAccessFaultM, .StoreAmoAccessFaultM, .SelHPTW,
-      .IllegalFPUInstrM, .PrivilegeModeW, .SATP_REGW,
-      .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS,
-      .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, 
-      .FRM_REGW,.BreakpointFaultM, .EcallFaultM, .WFIStallM, .BigEndianM);
-  end else begin
-    assign CSRReadValW = 0;
-    assign UnalignedPCNextF = PCNext2F;
-    assign RetM = 0;
-    assign TrapM = 0;
-    assign WFIStallM = 0;
-    assign sfencevmaM = 0;
-    assign BigEndianM = 0;
-  end
-
-  // multiply/divide unit
-  if (M_SUPPORTED) begin:mdu
-    mdu mdu(.clk, .reset, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
-      .ForwardedSrcAE, .ForwardedSrcBE, 
-      .Funct3E, .Funct3M, .IntDivE, .W64E,
-      .MDUResultW, .DivBusyE); 
-  end else begin // no M instructions supported
-    assign MDUResultW = 0; 
-    assign DivBusyE = 0;
-  end
-
-  // floating point unit
-  if (F_SUPPORTED) begin:fpu
-    fpu fpu(
-      .clk, .reset,
-      .FRM_REGW, // Rounding mode from CSR
-      .InstrD, // instruction from IFU
-      .ReadDataW(ReadDataW[FLEN-1:0]),// Read data from memory
-      .ForwardedSrcAE, // Integer input being processed (from IEU)
-      .StallE, .StallM, .StallW, // stall signals from HZU
-      .FlushE, .FlushM, .FlushW, // flush signals from HZU
-      .RdE, .RdM, .RdW, // which FP register to write to (from IEU)
-      .STATUS_FS, // is floating-point enabled?
-      .FRegWriteM, // FP register write enable
-      .FpLoadStoreM,
-      .ForwardedSrcBE, // Integer input for intdiv
-      .Funct3E, .Funct3M, .IntDivE, .W64E, // Integer flags and functions
-      .FPUStallD, // Stall the decode stage
-      .FWriteIntE, .FCvtIntE, // integer register write enable, conversion operation
-      .FWriteDataM, // Data to be written to memory
-      .FIntResM, // data to be written to integer register
-      .FCvtIntResW, // fp -> int conversion result to be stored in int register
-      .FCvtIntW,   // fpu result selection
-      .FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage)
-      .IllegalFPUInstrM, // Is the instruction an illegal fpu instruction
-      .SetFflagsM,        // FPU flags (to privileged unit)
-      .FIntDivResultW); 
-  end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low
-    assign FPUStallD = 0;
-    assign FWriteIntE = 0; 
-    assign FCvtIntE = 0;
-    assign FIntResM = 0;
-    assign FCvtIntW = 0;
-    assign FDivBusyE = 0;
-    assign IllegalFPUInstrM = 1;
-    assign SetFflagsM = 0;
-    assign FpLoadStoreM = 0;
-  end
-  
-endmodule
diff --git a/wallypipelinedsoc.sv b/wallypipelinedsoc.sv
deleted file mode 100644
index e792f6f89..000000000
--- a/wallypipelinedsoc.sv
+++ /dev/null
@@ -1,92 +0,0 @@
-///////////////////////////////////////////
-// wally-pipelinedsoc.sv
-//
-// Written: David_Harris@hmc.edu 6 November 2020
-// Modified: 
-//
-// Purpose: System on chip including pipelined processor and uncore memories/peripherals
-//
-// Documentation: RISC-V System on Chip Design (Figure 6.20)
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-import cvw::*;  // global CORE-V-Wally parameters
-
-module wallypipelinedsoc (
-  input  logic 		            clk, 
-  input  logic                reset_ext,        // external asynchronous reset pin
-  output logic                reset,            // reset synchronized to clk to prevent races on release
-  // AHB Interface
-  input  logic [AHBW-1:0]     HRDATAEXT,
-  input  logic 		            HREADYEXT, HRESPEXT,
-  output logic 		            HSELEXT,
-  // outputs to external memory, shared with uncore memory
-  output logic 		            HCLK, HRESETn,
-  output logic [PA_BITS-1:0]  HADDR,
-  output logic [AHBW-1:0]     HWDATA,
-  output logic [XLEN/8-1:0]   HWSTRB,
-  output logic 		            HWRITE,
-  output logic [2:0] 	        HSIZE,
-  output logic [2:0] 	        HBURST,
-  output logic [3:0] 	        HPROT,
-  output logic [1:0] 	        HTRANS,
-  output logic 		            HMASTLOCK,
-  output logic 		            HREADY,
-  // I/O Interface
-  input  logic                TIMECLK,          // optional for CLINT MTIME counter
-  input  logic [31:0] 	      GPIOPinsIn,       // inputs from GPIO
-  output logic [31:0] 	      GPIOPinsOut,      // output values for GPIO
-  output logic [31:0]         GPIOPinsEn,       // output enables for GPIO
-  input  logic 		            UARTSin,          // UART serial data input
-  output logic 		            UARTSout,         // UART serial data output
-  input  logic 		            SDCCmdIn,         // SDC Command input
-  output logic 		            SDCCmdOut,        // SDC Command output
-  output logic 		            SDCCmdOE,			    // SDC Command output enable
-  input  logic [3:0] 	        SDCDatIn,         // SDC data input
-  output logic 		            SDCCLK			      // SDC clock
-);
-
-  // Uncore signals
-  logic [AHBW-1:0]            HRDATA;           // from AHB mux in uncore
-  logic                       HRESP;            // response from AHB
-  logic                       MTimerInt, MSwInt; // timer and software interrupts from CLINT
-  logic [63:0]                MTIME_CLINT;      // from CLINT to CSRs
-  logic                       MExtInt,SExtInt;  // from PLIC
-
-  // synchronize reset to SOC clock domain
-  synchronizer resetsync(.clk, .d(reset_ext), .q(reset)); 
-   
-  // instantiate processor and internal memories
-  wallypipelinedcore core(.clk, .reset,
-    .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT,
-    .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB,
-    .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK
-   );
-
-  // instantiate uncore if a bus interface exists
-  if (BUS_SUPPORTED) begin : uncore
-    uncore uncore(.HCLK, .HRESETn, .TIMECLK,
-      .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
-      .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT,
-      .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, 
-	    .UARTSout, .MTIME_CLINT, 
-	    .SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK);
-  end
-
-endmodule

From ae548608050285651dbc4138c3675f06cc6fed59 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 4 Feb 2023 04:38:41 -0800
Subject: [PATCH 16/71] Renamed wally-piplined.do to wally.do

---
 benchmarks/coremark/Makefile                  |  2 +-
 benchmarks/embench/Makefile                   |  2 +-
 setup.imperas.sh                              |  4 ++--
 sim/buildrootBugFinder.py                     |  2 +-
 sim/regression-wally                          | 20 +++++++++----------
 sim/run-imperasdv-tests.bash                  |  2 +-
 sim/sim-buildroot                             |  2 +-
 sim/sim-buildroot-batch                       |  2 +-
 sim/sim-imperas                               |  2 +-
 sim/sim-wally                                 |  2 +-
 sim/sim-wally-batch                           |  2 +-
 sim/testfloat.do                              | 11 ++--------
 ...ally-pipelined-batch.do => wally-batch.do} | 17 ++++++++--------
 ...eras-no-idv.do => wally-imperas-no-idv.do} | 12 ++---------
 ...-pipelined-imperas.do => wally-imperas.do} | 12 ++---------
 sim/{wally-pipelined.do => wally.do}          |  7 ++++---
 16 files changed, 40 insertions(+), 61 deletions(-)
 rename sim/{wally-pipelined-batch.do => wally-batch.do} (89%)
 rename sim/{wally-pipelined-imperas-no-idv.do => wally-imperas-no-idv.do} (73%)
 rename sim/{wally-pipelined-imperas.do => wally-imperas.do} (79%)
 rename sim/{wally-pipelined.do => wally.do} (95%)

diff --git a/benchmarks/coremark/Makefile b/benchmarks/coremark/Makefile
index bb0f20f5a..b412c36ef 100644
--- a/benchmarks/coremark/Makefile
+++ b/benchmarks/coremark/Makefile
@@ -22,7 +22,7 @@ PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \
 all: $(work_dir)/coremark.bare.riscv.elf.memfile
 
 run:
-	(cd ../../sim && (time vsim -c -do "do wally-pipelined-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
+	(cd ../../sim && (time vsim -c -do "do wally-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
 	cd ../benchmarks/coremark/
 #	KMG: added post processing script to give out branch miss proportion along with other stats to the coremark test
 	python3 coremark-postprocess.py
diff --git a/benchmarks/embench/Makefile b/benchmarks/embench/Makefile
index 0d619c90b..538fb64f9 100644
--- a/benchmarks/embench/Makefile
+++ b/benchmarks/embench/Makefile
@@ -34,7 +34,7 @@ sim: modelsim_build_memfile modelsim_run speed
 
 # launches modelsim to simulate tests on wally
 modelsim_run:
-	(cd ../../sim/ && vsim -c -do "do wally-pipelined-batch.do rv32gc embench")
+	(cd ../../sim/ && vsim -c -do "do wally-batch.do rv32gc embench")
 	cd ../../benchmarks/embench/
 
 # builds the objdump based on the compiled c elf files
diff --git a/setup.imperas.sh b/setup.imperas.sh
index 755a298b5..71d5dcfd5 100644
--- a/setup.imperas.sh
+++ b/setup.imperas.sh
@@ -36,7 +36,7 @@ pushd sim
     IMPERAS_TOOLS=$(pwd)/imperas.ic \
         OTHERFLAGS="+TRACE2LOG_ENABLE=1 VERBOSE=1" \
         TESTDIR=${WALLY}/external/ImperasDV-HMC/tests/riscof/work/riscv-arch-test/rv64i_m/F/src/fadd_b1-01.S  \
-        vsim -c -do "do wally-pipelined-imperas.do rv64gc"
+        vsim -c -do "do wally-imperas.do rv64gc"
 popd
 
 # notes
@@ -50,7 +50,7 @@ popd
 IMPERAS_TOOLS=$(pwd)/imperas.ic \
 OTHERFLAGS="+TRACE2LOG_ENABLE=1 VERBOSE=1" \
 TESTDIR=../../tests/riscof_lee/work/riscv-arch-test/rv64i_m/F/src/fadd_b1-01.S  \
-vsim -c -do "do wally-pipelined-imperas.do rv64gc"
+vsim -c -do "do wally-imperas.do rv64gc"
 
 
 # getting library issue.
diff --git a/sim/buildrootBugFinder.py b/sim/buildrootBugFinder.py
index 89a838d2f..af6324596 100755
--- a/sim/buildrootBugFinder.py
+++ b/sim/buildrootBugFinder.py
@@ -22,7 +22,7 @@ def main():
             break
         checkpoint = checkpointList[0]
         logFile = logDir+"checkpoint"+str(checkpoint)+".log"
-        runCommand="{\nvsim -c <<!\ndo wally-pipelined-batch.do buildroot buildroot /opt/riscv 0 "+str(checkpoint+1)+" "+str(checkpoint)+"\n!\n} | tee "+logFile 
+        runCommand="{\nvsim -c <<!\ndo wally-batch.do buildroot buildroot /opt/riscv 0 "+str(checkpoint+1)+" "+str(checkpoint)+"\n!\n} | tee "+logFile 
         print(runCommand)
         os.system(runCommand)
         try:
diff --git a/sim/regression-wally b/sim/regression-wally
index f99906284..07603120b 100755
--- a/sim/regression-wally
+++ b/sim/regression-wally
@@ -50,18 +50,18 @@ def getBuildrootTC(boot):
     MAX_EXPECTED = 246000000 # *** TODO: replace this with a search for the login prompt.
     if boot:
         name="buildrootboot"
-        BRcmd="vsim > {} -c <<!\ndo wally-pipelined.do buildroot buildroot-no-trace $RISCV 0 1 0\n!"
+        BRcmd="vsim > {} -c <<!\ndo wally.do buildroot buildroot-no-trace $RISCV 0 1 0\n!"
         BRgrepstr="WallyHostname login:"
     else:
         name="buildroot"
-        BRcmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do buildroot buildroot $RISCV "+str(INSTR_LIMIT)+" 1 0\n!"
+        BRcmd="vsim > {} -c <<!\ndo wally-batch.do buildroot buildroot $RISCV "+str(INSTR_LIMIT)+" 1 0\n!"
         BRgrepstr=str(INSTR_LIMIT)+" instructions"
     return  TestCase(name,variant="rv64gc",cmd=BRcmd,grepstr=BRgrepstr)
 
 tc = TestCase(
       name="buildroot-checkpoint",
       variant="rv64gc",
-      cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do buildroot buildroot-checkpoint $RISCV 400100000 400000001 400000000\n!", # *** will this work with rv64gc rather than buildroot config?
+      cmd="vsim > {} -c <<!\ndo wally-batch.do buildroot buildroot-checkpoint $RISCV 400100000 400000001 400000000\n!", # *** will this work with rv64gc rather than buildroot config?
       grepstr="400100000 instructions")
 configs.append(tc)
 
@@ -71,7 +71,7 @@ for test in tests64gc:
   tc = TestCase(
         name=test,
         variant="rv64gc",
-        cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv64gc "+test+"\n!",
+        cmd="vsim > {} -c <<!\ndo wally-batch.do rv64gc "+test+"\n!",
         grepstr="All tests ran without failures")
   configs.append(tc)
 
@@ -80,7 +80,7 @@ for test in tests64i:
   tc = TestCase(
         name=test,
         variant="rv64i",
-        cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv64i "+test+"\n!",
+        cmd="vsim > {} -c <<!\ndo wally-batch.do rv64i "+test+"\n!",
         grepstr="All tests ran without failures")
   configs.append(tc)
 
@@ -90,7 +90,7 @@ for test in tests32gc:
   tc = TestCase(
         name=test,
         variant="rv32gc",
-        cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv32gc "+test+"\n!",
+        cmd="vsim > {} -c <<!\ndo wally-batch.do rv32gc "+test+"\n!",
         grepstr="All tests ran without failures")
   configs.append(tc)
 
@@ -100,7 +100,7 @@ for test in tests32imc:
   tc = TestCase(
         name=test,
         variant="rv32imc",
-        cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv32imc "+test+"\n!",
+        cmd="vsim > {} -c <<!\ndo wally-batch.do rv32imc "+test+"\n!",
         grepstr="All tests ran without failures")
   configs.append(tc)
 
@@ -109,7 +109,7 @@ for test in tests32i:
   tc = TestCase(
         name=test,
         variant="rv32i",
-        cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv32i "+test+"\n!",
+        cmd="vsim > {} -c <<!\ndo wally-batch.do rv32i "+test+"\n!",
         grepstr="All tests ran without failures")
   configs.append(tc)
 
@@ -119,7 +119,7 @@ for test in tests32e:
   tc = TestCase(
         name=test,
         variant="rv32e",
-        cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv32e "+test+"\n!",
+        cmd="vsim > {} -c <<!\ndo wally-batch.do rv32e "+test+"\n!",
         grepstr="All tests ran without failures")
   configs.append(tc)
 
@@ -128,7 +128,7 @@ for test in ahbTests:
   tc = TestCase(
         name="ram_latency_" + test[0] + "_burst_en_" + test[1],
         variant="ahb",
-        cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv64gc ahb "+test[0]+" "+test[1]+"\n!",
+        cmd="vsim > {} -c <<!\ndo wally-batch.do rv64gc ahb "+test[0]+" "+test[1]+"\n!",
         grepstr="All tests ran without failures")
   configs.append(tc)
   
diff --git a/sim/run-imperasdv-tests.bash b/sim/run-imperasdv-tests.bash
index c037c369d..a9facd0e4 100755
--- a/sim/run-imperasdv-tests.bash
+++ b/sim/run-imperasdv-tests.bash
@@ -17,6 +17,6 @@ for t in $ALL; do
     echo "Running test ${TESTDIR} -> ${OUTDIR} :: ${OUTLOG}"
 
     mkdir -p ${OUTDIR}
-    vsim -c -do "do wally-pipelined-imperas.do rv64gc"
+    vsim -c -do "do wally-imperas.do rv64gc"
     mv transcript ${OUTLOG}
 done
diff --git a/sim/sim-buildroot b/sim/sim-buildroot
index 938bff866..530e33386 100755
--- a/sim/sim-buildroot
+++ b/sim/sim-buildroot
@@ -30,4 +30,4 @@ echo "INSTR_LIMIT  = ${INSTR_LIMIT}"
 echo "INSTR_WAVEON = ${INSTR_WAVEON}"
 echo "CHECKPOINT   = ${CHECKPOINT}"
 
-vsim -do "do ./wally-pipelined.do buildroot buildroot $RISCV $INSTR_LIMIT $INSTR_WAVEON $CHECKPOINT"
+vsim -do "do ./wally.do buildroot buildroot $RISCV $INSTR_LIMIT $INSTR_WAVEON $CHECKPOINT"
diff --git a/sim/sim-buildroot-batch b/sim/sim-buildroot-batch
index a8d4038ef..81a6fac1e 100755
--- a/sim/sim-buildroot-batch
+++ b/sim/sim-buildroot-batch
@@ -32,5 +32,5 @@ echo "CHECKPOINT   = ${CHECKPOINT}"
 
 # *** change config from buildroot to rv64gc
 vsim -c <<!
-do wally-pipelined-batch.do buildroot buildroot-no-trace $RISCV $INSTR_LIMIT $INSTR_WAVEON $CHECKPOINT
+do wally-batch.do buildroot buildroot-no-trace $RISCV $INSTR_LIMIT $INSTR_WAVEON $CHECKPOINT
 !
diff --git a/sim/sim-imperas b/sim/sim-imperas
index d696f18e5..eb7633904 100755
--- a/sim/sim-imperas
+++ b/sim/sim-imperas
@@ -29,4 +29,4 @@
 IMPERAS_TOOLS=$(pwd)/imperas.ic \
 OTHERFLAGS="+TRACE2LOG_ENABLE=1 VERBOSE=1" \
 TESTDIR=${WALLY}/external/ImperasDV-HMC/tests/riscof/work/riscv-arch-test/rv64i_m/F/src/fadd_b1-01.S  \
-vsim -c -do "do wally-pipelined-imperas.do rv64gc"
+vsim -c -do "do wally-imperas.do rv64gc"
diff --git a/sim/sim-wally b/sim/sim-wally
index 51c8b3edc..410cc5406 100755
--- a/sim/sim-wally
+++ b/sim/sim-wally
@@ -1,2 +1,2 @@
-vsim -do "do wally-pipelined.do rv64gc arch64d"
+vsim -do "do wally.do rv64gc arch64d"
 
diff --git a/sim/sim-wally-batch b/sim/sim-wally-batch
index e9a387d0a..46c35c75c 100755
--- a/sim/sim-wally-batch
+++ b/sim/sim-wally-batch
@@ -1 +1 @@
-vsim -c -do "do wally-pipelined-batch.do rv32gc wally32priv"
+vsim -c -do "do wally-batch.do rv32gc wally32priv"
diff --git a/sim/testfloat.do b/sim/testfloat.do
index 9b2c2b16d..49f816ce8 100644
--- a/sim/testfloat.do
+++ b/sim/testfloat.do
@@ -1,4 +1,4 @@
-# wally-pipelined.do 
+# testfloat.do 
 #
 # Modification by Oklahoma State University & Harvey Mudd College
 # Use with Testbench 
@@ -7,14 +7,7 @@
 #
 # Takes 1:10 to run RV64IC tests using gui
 
-# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m"
-
-# Use this wally-pipelined.do file to run this example.
-# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
-#     do wally-pipelined.do
-# or, to run from a shell, type the following at the shell prompt:
-#     vsim -do wally-pipelined.do -c
-# (omit the "-c" to see the GUI while running from the shell)
+# run with vsim -do "do wally.do rv64ic riscvarchtest-64m"
 
 onbreak {resume}
 
diff --git a/sim/wally-pipelined-batch.do b/sim/wally-batch.do
similarity index 89%
rename from sim/wally-pipelined-batch.do
rename to sim/wally-batch.do
index 4bd153ce7..064f503b2 100644
--- a/sim/wally-pipelined-batch.do
+++ b/sim/wally-batch.do
@@ -1,4 +1,5 @@
-# wally-pipelined-batch.do 
+# wally-batch.do 
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 #
 # Modification by Oklahoma State University & Harvey Mudd College
 # Use with Testbench 
@@ -7,14 +8,14 @@
 #
 # Takes 1:10 to run RV64IC tests using gui
 
-# Usage: do wally-pipelined-batch.do <config> <testcases>
-# Example: do wally-pipelined-batch.do rv32imc imperas-32i
+# Usage: do wally-batch.do <config> <testcases>
+# Example: do wally-batch.do rv32imc imperas-32i
 
-# Use this wally-pipelined-batch.do file to run this example.
+# Use this wally-batch.do file to run this example.
 # Either bring up ModelSim and type the following at the "ModelSim>" prompt:
-#     do wally-pipelined-batch.do
+#     do wally-batch.do
 # or, to run from a shell, type the following at the shell prompt:
-#     vsim -do wally-pipelined-batch.do -c
+#     vsim -do wally-batch.do -c
 # (omit the "-c" to see the GUI while running from the shell)
 
 onbreak {resume}
@@ -91,9 +92,9 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
     # power off -r /dut/core/*
 } 
 
-#coverage report -file wally-pipelined-coverage.txt
+#coverage report -file wally-coverage.txt
 # These aren't doing anything helpful
 #coverage report -memory 
-#profile report -calltree -file wally-pipelined-calltree.rpt -cutoff 2
+#profile report -calltree -file wally-calltree.rpt -cutoff 2
 #power report -all -bsaif power.saif
 quit
diff --git a/sim/wally-pipelined-imperas-no-idv.do b/sim/wally-imperas-no-idv.do
similarity index 73%
rename from sim/wally-pipelined-imperas-no-idv.do
rename to sim/wally-imperas-no-idv.do
index 646c41c72..5f300250c 100644
--- a/sim/wally-pipelined-imperas-no-idv.do
+++ b/sim/wally-imperas-no-idv.do
@@ -1,4 +1,5 @@
-# wally-pipelined.do 
+# wally.do 
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 #
 # Modification by Oklahoma State University & Harvey Mudd College
 # Use with Testbench 
@@ -7,15 +8,6 @@
 #
 # Takes 1:10 to run RV64IC tests using gui
 
-# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m"
-
-# Use this wally-pipelined.do file to run this example.
-# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
-#     do wally-pipelined.do
-# or, to run from a shell, type the following at the shell prompt:
-#     vsim -do wally-pipelined.do -c
-# (omit the "-c" to see the GUI while running from the shell)
-
 onbreak {resume}
 
 # create library
diff --git a/sim/wally-pipelined-imperas.do b/sim/wally-imperas.do
similarity index 79%
rename from sim/wally-pipelined-imperas.do
rename to sim/wally-imperas.do
index 21ed71420..d08361e8c 100644
--- a/sim/wally-pipelined-imperas.do
+++ b/sim/wally-imperas.do
@@ -1,4 +1,5 @@
-# wally-pipelined.do 
+# wally.do 
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 #
 # Modification by Oklahoma State University & Harvey Mudd College
 # Use with Testbench 
@@ -7,15 +8,6 @@
 #
 # Takes 1:10 to run RV64IC tests using gui
 
-# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m"
-
-# Use this wally-pipelined.do file to run this example.
-# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
-#     do wally-pipelined.do
-# or, to run from a shell, type the following at the shell prompt:
-#     vsim -do wally-pipelined.do -c
-# (omit the "-c" to see the GUI while running from the shell)
-
 onbreak {resume}
 
 # create library
diff --git a/sim/wally-pipelined.do b/sim/wally.do
similarity index 95%
rename from sim/wally-pipelined.do
rename to sim/wally.do
index 9d61511b7..895b10b95 100644
--- a/sim/wally-pipelined.do
+++ b/sim/wally.do
@@ -1,4 +1,5 @@
-# wally-pipelined.do 
+# wally.do 
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 #
 # Modification by Oklahoma State University & Harvey Mudd College
 # Use with Testbench 
@@ -11,9 +12,9 @@
 
 # Use this wally-pipelined.do file to run this example.
 # Either bring up ModelSim and type the following at the "ModelSim>" prompt:
-#     do wally-pipelined.do
+#     do wally.do
 # or, to run from a shell, type the following at the shell prompt:
-#     vsim -do wally-pipelined.do -c
+#     vsim -do wally.do -c
 # (omit the "-c" to see the GUI while running from the shell)
 
 onbreak {resume}

From 2c69adc5f7864a51a4e5532ab4340e0a68ac0c0c Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 4 Feb 2023 08:18:55 -0800
Subject: [PATCH 17/71] Started making debug testcase

---
 tests/custom/debug/Makefile | 27 ++++++++++++++++++++++++
 tests/custom/debug/debug.S  | 42 +++++++++++++++++++++++++++++++++++++
 2 files changed, 69 insertions(+)
 create mode 100644 tests/custom/debug/Makefile
 create mode 100644 tests/custom/debug/debug.S

diff --git a/tests/custom/debug/Makefile b/tests/custom/debug/Makefile
new file mode 100644
index 000000000..a63fb3b11
--- /dev/null
+++ b/tests/custom/debug/Makefile
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+TARGET = debug
+
+%.elf.memfile: %.elf %.elf.objdump.adr
+	riscv64-unknown-elf-elf2hex --bit-width $(if $(findstring rv64,$*),64,32) --input $< --output $@
+
+%.elf.objdump.addr: %.elf.objdump
+	extractFunctionRadix.sh $<
+
+$(TARGET).objdump: $(TARGET).elf
+	riscv64-unknown-elf-objdump -D $(TARGET).elf > $(TARGET).objdump
+    
+$(TARGET): $(TARGET).S Makefile
+	riscv64-unknown-elf-gcc -g -o $(TARGET).elf -march=rv64gc -mabi=lp64 -mcmodel=medany \
+	    -nostartfiles -T../../link/link.ld $(TARGET).S 
+
+sim:
+	spike +signature=$(TARGET).signature.output +signature-granularity=8 $(TARGET)
+	diff --ignore-case $(TARGET).signature.output $(TARGET).reference_output || exit
+	echo "Signature matches! Success!"
+
+clean:
+	rm -f $(TARGET).elf $(TARGET).objdump $(TARGET).objdump.adr %(TARGET).elf.memfile $(TARGET).signature.output
+
+
+
diff --git a/tests/custom/debug/debug.S b/tests/custom/debug/debug.S
new file mode 100644
index 000000000..aadbcac64
--- /dev/null
+++ b/tests/custom/debug/debug.S
@@ -0,0 +1,42 @@
+// debug.S
+// David_Harris@hmc.edu 4 February 2023
+// Small code snippets for the purpose of debugging issues
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+# openhwgroup/cvw Issue #55
+li x1, 0x7ff0000000000001
+fmv.w.x f4, x1
+li x1, 7ff8000000000000
+fmv.w.x f9, x1
+fsgnjx.s f12,f9,f4  # expected f 0xffffffff7fc00000
+
+
+#########################
+# HTIF and signature
+#########################
+
+write_tohost:
+    la t1, tohost
+    li t0, 1            # 1 for success, 3 for failure
+    sd t0, 0(t1)        # send success code
+
+self_loop:
+    j self_loop         # wait
+    
+.section .tohost 
+tohost:                 # write to HTIF
+    .dword 0
+fromhost:
+    .dword 0
+
+.data
+
+.EQU XLEN,64
+begin_signature:
+    .fill 2*(XLEN/32),4,0xdeadbeef    # 
+end_signature:
+
+# Initialize stack with room for 512 bytes
+.bss
+    .space 512
+topofstack:
\ No newline at end of file

From b09002c71d4b22bd66442370e524ada8a18ac07e Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 4 Feb 2023 08:19:20 -0800
Subject: [PATCH 18/71] Fixed license on testbench files

---
 testbench/testbench-fp.sv      | 24 ++++++++++--------------
 testbench/testbench-linux.sv   | 23 +++++++++++------------
 testbench/testbench.sv         | 24 ++++++++++--------------
 testbench/testbench_imperas.sv | 24 ++++++++++--------------
 testbench/tests-fp.vh          | 26 ++++++++++++++++++++++++++
 testbench/tests.vh             | 22 ++++++++++++----------
 6 files changed, 79 insertions(+), 64 deletions(-)

diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv
index 8d6826b70..3359090ac 100644
--- a/testbench/testbench-fp.sv
+++ b/testbench/testbench-fp.sv
@@ -9,22 +9,18 @@
 // 
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
-//   substantial portions of the Software.
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 `include "wally-config.vh"
 `include "tests-fp.vh"
diff --git a/testbench/testbench-linux.sv b/testbench/testbench-linux.sv
index da369250e..1705b36fd 100644
--- a/testbench/testbench-linux.sv
+++ b/testbench/testbench-linux.sv
@@ -10,20 +10,19 @@
 // 
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-// When letting Wally go for it, let wally make own interrupts
-///////////////////////////////////////////
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
 
diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index a3fa2c093..329d4c605 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -11,22 +11,18 @@
 // 
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
-//   substantial portions of the Software.
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
diff --git a/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv
index 65c92eb33..ce4b16de1 100644
--- a/testbench/testbench_imperas.sv
+++ b/testbench/testbench_imperas.sv
@@ -11,22 +11,18 @@
 // 
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
-//   substantial portions of the Software.
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
diff --git a/testbench/tests-fp.vh b/testbench/tests-fp.vh
index ff5cf2fb8..1d4cfdc60 100644
--- a/testbench/tests-fp.vh
+++ b/testbench/tests-fp.vh
@@ -1,3 +1,29 @@
+///////////////////////////////////////////
+// tests0fo.vh
+//
+// Written: Katherine Parry 2022
+// Modified: 
+//
+// Purpose: List of floating-point tests to apply
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021-3 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
 `define PATH "../../tests/fp/vectors/"
 `define ADD_OPCTRL 3'b110
 `define MUL_OPCTRL 3'b100
diff --git a/testbench/tests.vh b/testbench/tests.vh
index f119b0a4e..397c66a0d 100644
--- a/testbench/tests.vh
+++ b/testbench/tests.vh
@@ -10,18 +10,19 @@
 // 
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 //
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
 
 `define IMPERASTEST   "0"
 `define RISCVARCHTEST "1"
@@ -1883,6 +1884,7 @@ string imperas32f[] = '{
 
  string custom[] = '{
     `CUSTOM,
+    "debug",
     "simple",
     "cacheTest"
  };

From 43668a3fc573fb8b77a3cc6cf817f601faabe57c Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 4 Feb 2023 08:31:47 -0800
Subject: [PATCH 19/71] Developing debug test

---
 src/fpu/unpackinput.sv      | 4 +---
 tests/custom/debug/Makefile | 2 +-
 tests/custom/debug/debug.S  | 2 +-
 3 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/src/fpu/unpackinput.sv b/src/fpu/unpackinput.sv
index b85077d20..68f98e900 100644
--- a/src/fpu/unpackinput.sv
+++ b/src/fpu/unpackinput.sv
@@ -56,7 +56,6 @@ module unpackinput (
       assign ExpMax = &In[`FLEN-2:`NF];  // is the exponent all 1's
   
   end else if (`FPSIZES == 2) begin   // if there are 2 floating point formats supported
-      //***need better names for these constants
       // largest format | smaller format
       //----------------------------------
       //      `FLEN     |     `LEN1       length of floating point number
@@ -104,7 +103,6 @@ module unpackinput (
 
   end else if (`FPSIZES == 3) begin       // three floating point precsions supported
 
-      //***need better names for these constants
       // largest format | larger format  | smallest format
       //---------------------------------------------------
       //      `FLEN     |     `LEN1      |    `LEN2       length of floating point number
@@ -196,7 +194,7 @@ module unpackinput (
       // Check NaN boxing
       always_comb
           case (Fmt)
-              2'b11:  BadNaNBox = 0;
+              2'b11: BadNaNBox = 0;
               2'b01: BadNaNBox = ~&In[`Q_LEN-1:`D_LEN];
               2'b00: BadNaNBox = ~&In[`Q_LEN-1:`S_LEN];
               2'b10: BadNaNBox = ~&In[`Q_LEN-1:`H_LEN];
diff --git a/tests/custom/debug/Makefile b/tests/custom/debug/Makefile
index a63fb3b11..900f5b5e3 100644
--- a/tests/custom/debug/Makefile
+++ b/tests/custom/debug/Makefile
@@ -11,7 +11,7 @@ TARGET = debug
 $(TARGET).objdump: $(TARGET).elf
 	riscv64-unknown-elf-objdump -D $(TARGET).elf > $(TARGET).objdump
     
-$(TARGET): $(TARGET).S Makefile
+$(TARGET).elf: $(TARGET).S Makefile
 	riscv64-unknown-elf-gcc -g -o $(TARGET).elf -march=rv64gc -mabi=lp64 -mcmodel=medany \
 	    -nostartfiles -T../../link/link.ld $(TARGET).S 
 
diff --git a/tests/custom/debug/debug.S b/tests/custom/debug/debug.S
index aadbcac64..e493cab74 100644
--- a/tests/custom/debug/debug.S
+++ b/tests/custom/debug/debug.S
@@ -6,7 +6,7 @@
 # openhwgroup/cvw Issue #55
 li x1, 0x7ff0000000000001
 fmv.w.x f4, x1
-li x1, 7ff8000000000000
+li x1, 0x7ff8000000000000
 fmv.w.x f9, x1
 fsgnjx.s f12,f9,f4  # expected f 0xffffffff7fc00000
 

From d7a65b2576368dfc7116e3b863c9a6ad398c514a Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sat, 4 Feb 2023 11:28:23 -0600
Subject: [PATCH 20/71] Updates to imperas test bench.

---
 pipelined/regression/imperas.ic  |   1 +
 pipelined/regression/sim-imperas |   6 +-
 pipelined/regression/wave.do     | 762 ++++++++++++++++---------------
 3 files changed, 388 insertions(+), 381 deletions(-)

diff --git a/pipelined/regression/imperas.ic b/pipelined/regression/imperas.ic
index 164cec228..930b6d3e2 100644
--- a/pipelined/regression/imperas.ic
+++ b/pipelined/regression/imperas.ic
@@ -2,6 +2,7 @@
 --override cpu/show_c_prefix=T
 --override cpu/unaligned=F
 --override cpu/mstatus_FS=1
+--override cpu/ignore_non_leaf_DAU=1
 
 # Enable the Imperas instruction coverage
 -extlib    refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0
diff --git a/pipelined/regression/sim-imperas b/pipelined/regression/sim-imperas
index d696f18e5..da1d5a919 100755
--- a/pipelined/regression/sim-imperas
+++ b/pipelined/regression/sim-imperas
@@ -28,5 +28,7 @@
 ################################################################################################
 IMPERAS_TOOLS=$(pwd)/imperas.ic \
 OTHERFLAGS="+TRACE2LOG_ENABLE=1 VERBOSE=1" \
-TESTDIR=${WALLY}/external/ImperasDV-HMC/tests/riscof/work/riscv-arch-test/rv64i_m/F/src/fadd_b1-01.S  \
-vsim -c -do "do wally-pipelined-imperas.do rv64gc"
+TESTDIR=${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege/src/Lee.S/  \
+vsim  -do "do wally-pipelined-imperas.do rv64gc"
+
+#TESTDIR=${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege/src/FCVT-S-L-RTZ-01.S/  \
diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do
index b62c31227..7ccb27fb8 100644
--- a/pipelined/regression/wave.do
+++ b/pipelined/regression/wave.do
@@ -6,37 +6,37 @@ add wave -noupdate /testbench/reset
 add wave -noupdate /testbench/reset_ext
 add wave -noupdate /testbench/memfilename
 add wave -noupdate /testbench/dut/core/SATP_REGW
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
-add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/MDUStallD
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallF
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallD
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
+add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/MDUStallD
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM
+add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD
+add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE
+add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM
+add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW
+add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallF
+add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallD
+add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE
+add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM
+add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW
 add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName
 add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
 add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
@@ -68,23 +68,26 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
 add wave -noupdate -group {WriteBack stage} /testbench/PCW
 add wave -noupdate -group {WriteBack stage} /testbench/InstrW
 add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MCAUSE_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEPC_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIDELEG_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIE_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW
-add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MCAUSE_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MEPC_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIDELEG_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIE_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW
+add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
+add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW
+add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW
+add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS
 add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check}
 add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
 add wave -noupdate -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
@@ -178,209 +181,209 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM
-add wave -noupdate -expand -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/FWriteDataM
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB
-add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
-add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK
-add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState
-add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY
-add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall
-add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS
-add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer
-add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA
-add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA
-add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall
-add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW
-add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW
-add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
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-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM
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-add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
-add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
-add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
-add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
-add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate
-add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate
-add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded
-add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
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-add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag
-add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn
-add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn
-add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag
-add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM[62]}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/we}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
-add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
-add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
-add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData
-add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
-add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
-add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
-add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
-add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
-add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
-add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
-add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
-add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
-add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWalk
-add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/WalkerState
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWAdr
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PTE
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCFSpill
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/NextPageType
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PageType
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ValidNonLeafPTE
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ITLBWriteF
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWriteM
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSULoadAccessFaultM
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSUStoreAmoAccessFaultM
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWInstrAccessFaultM
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LoadAccessFaultM
-add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/StoreAmoAccessFaultM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
+add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM
+add wave -noupdate -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
+add wave -noupdate -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB
+add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
+add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK
+add wave -noupdate -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState
+add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY
+add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall
+add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS
+add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer
+add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA
+add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA
+add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall
+add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW
+add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW
+add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
+add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
+add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
+add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
+add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CAdr
+add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
+add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
+add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
+add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay
+add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate
+add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate
+add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded
+add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
+add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
+add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
+add wave -noupdate -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
+add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag
+add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn
+add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn
+add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag
+add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay
+add wave -noupdate -group lsu -expand -group dcache -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM[62]}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/we}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData
+add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
+add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
+add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
+add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
+add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
+add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
+add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
+add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
+add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
+add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
+add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWalk
+add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/WalkerState
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWAdr
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PTE
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCFSpill
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/NextPageType
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PageType
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ValidNonLeafPTE
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ITLBWriteF
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWriteM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSULoadAccessFaultM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSUStoreAmoAccessFaultM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWInstrAccessFaultM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LoadAccessFaultM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/StoreAmoAccessFaultM
 add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr
 add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr
 add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/MExtInt
@@ -461,112 +464,104 @@ add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/P
 add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM
 add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW
 add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F
-add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/InstrRawF
-add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF
-add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/IFUStallF
-add wave -noupdate -expand -group ifu -group Spill /testbench/dut/core/ifu/Spill/spill/CurrState
-add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/SpillF
-add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallD
-add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissF
-add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/InstrDAPageFaultF
-add wave -noupdate -expand -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF
-add wave -noupdate -expand -group ifu -group Spill /testbench/dut/core/ifu/SelNextSpillF
-add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE
-add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST
-add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS
-add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE
-add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR
-add wave -noupdate -expand -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush
-add wave -noupdate -expand -group ifu -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState
-add wave -noupdate -expand -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState
-add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF
-add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr
-add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF
-add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF
-add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss
-add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay
-add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF
-add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr
-add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
-add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay
-add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/bwe}
-add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/dout}
-add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/bwe}
-add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/dout}
-add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/bwe}
-add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/dout}
-add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/bwe}
-add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/dout}
-add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/bwe}
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+add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/bwe}
+add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/bwe}
+add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/bwe}
+add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/dout}
+add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
+add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/ITLBMissF
+add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/VAdr
+add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
+add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/Matches
+add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/InstrPageFaultF
+add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/TLBFlush
+add wave -noupdate -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Valid}
+add wave -noupdate -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/PageType}
+add wave -noupdate -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key}
+add wave -noupdate -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key0}
+add wave -noupdate -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key1}
+add wave -noupdate -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query0}
+add wave -noupdate -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query1}
+add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Valid}
+add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageTypeWriteVal}
+add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageType}
+add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key}
+add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key0}
+add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1}
+add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0}
+add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1}
 add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
 add wave -noupdate -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
 add wave -noupdate -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
@@ -631,25 +626,25 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassD
 add wave -noupdate -color Firebrick /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredWrongM
-add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF
-add wave -noupdate -expand -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE
-add wave -noupdate -expand -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE
-add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/TableDirPredictionF
-add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF
-add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionWrongE
-add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
-add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushE
-add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF
-add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD
-add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE
-add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD
-add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF
-add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextD
-add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextE
-add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionE
-add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE
-add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM
-add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
+add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF
+add wave -noupdate -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE
+add wave -noupdate -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE
+add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/TableDirPredictionF
+add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF
+add wave -noupdate -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionWrongE
+add wave -noupdate -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
+add wave -noupdate -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushE
+add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF
+add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD
+add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE
+add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD
+add wave -noupdate -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF
+add wave -noupdate -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextD
+add wave -noupdate -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextE
+add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionE
+add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE
+add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM
+add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/PCNextF
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TableBTBPredictionF
@@ -659,9 +654,18 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredValidF
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD
 add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW
 add wave -noupdate /testbench/dut/core/ifu/CSRWriteFenceM
+add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/NextFFLAGSM
+add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/WriteFFLAGSM
+add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/InstrValidNotFlushedM
+add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/CSRUWriteM
+add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS
+add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/CSRAdrM
+add wave -noupdate /testbench/dut/core/ifu/MatchCopy
+add wave -noupdate /testbench/dut/core/ifu/PCLinkECopy
+add wave -noupdate /testbench/dut/core/ifu/PCLinkE
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {1151457 ns} 0} {{Cursor 4} {1156601 ns} 1} {{Cursor 5} {1156601 ns} 1}
-quietly wave cursor active 3
+WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {391801 ns} 1} {{Cursor 4} {1156601 ns} 1} {{Cursor 5} {353781 ns} 0}
+quietly wave cursor active 5
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 194
 configure wave -justifyvalue left
@@ -676,4 +680,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {1151311 ns} {1151571 ns}
+WaveRestoreZoom {348453 ns} {359109 ns}

From 5256d3a625f42641f208eefecfaef221a10de6d2 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 4 Feb 2023 09:59:22 -0800
Subject: [PATCH 21/71] More progress on debug.S, but it crashes in Spike

---
 .gitignore                  |  1 +
 tests/custom/debug/Makefile | 14 +++++++-------
 tests/custom/debug/debug.S  | 27 +++++++++++++++++++++------
 3 files changed, 29 insertions(+), 13 deletions(-)

diff --git a/.gitignore b/.gitignore
index 5619adbff..2d1454e3c 100644
--- a/.gitignore
+++ b/.gitignore
@@ -89,6 +89,7 @@ tests/custom/*/*/*.elf
 tests/custom/*/*/*.map
 tests/custom/*/*/*.memfile
 tests/custom/crt0/*.a
+tests/custom/*/*.elf*
 sim/sd_model.log
 fpga/src/sdc/*
 fpga/src/sdc.tar.gz
diff --git a/tests/custom/debug/Makefile b/tests/custom/debug/Makefile
index 900f5b5e3..9ee0b2e7b 100644
--- a/tests/custom/debug/Makefile
+++ b/tests/custom/debug/Makefile
@@ -2,26 +2,26 @@
 
 TARGET = debug
 
-%.elf.memfile: %.elf %.elf.objdump.adr
+$(TARGET).elf.memfile:$(TARGET).elf $(TARGET).elf.objdump.addr
 	riscv64-unknown-elf-elf2hex --bit-width $(if $(findstring rv64,$*),64,32) --input $< --output $@
 
-%.elf.objdump.addr: %.elf.objdump
+$(TARGET).elf.objdump.addr: $(TARGET).elf.objdump
 	extractFunctionRadix.sh $<
 
-$(TARGET).objdump: $(TARGET).elf
-	riscv64-unknown-elf-objdump -D $(TARGET).elf > $(TARGET).objdump
+$(TARGET).elf.objdump: $(TARGET).elf
+	riscv64-unknown-elf-objdump -D $(TARGET).elf > $(TARGET).elf.objdump
     
 $(TARGET).elf: $(TARGET).S Makefile
 	riscv64-unknown-elf-gcc -g -o $(TARGET).elf -march=rv64gc -mabi=lp64 -mcmodel=medany \
-	    -nostartfiles -T../../link/link.ld $(TARGET).S 
+	    -nostartfiles -T$(WALLY)/examples/link/link.ld $(TARGET).S 
 
 sim:
-	spike +signature=$(TARGET).signature.output +signature-granularity=8 $(TARGET)
+	spike --isa=rv64gc +signature=$(TARGET).signature.output +signature-granularity=8 $(TARGET).elf
 	diff --ignore-case $(TARGET).signature.output $(TARGET).reference_output || exit
 	echo "Signature matches! Success!"
 
 clean:
-	rm -f $(TARGET).elf $(TARGET).objdump $(TARGET).objdump.adr %(TARGET).elf.memfile $(TARGET).signature.output
+	rm -f $(TARGET).elf $(TARGET).elf.*
 
 
 
diff --git a/tests/custom/debug/debug.S b/tests/custom/debug/debug.S
index e493cab74..431a261e5 100644
--- a/tests/custom/debug/debug.S
+++ b/tests/custom/debug/debug.S
@@ -3,13 +3,22 @@
 // Small code snippets for the purpose of debugging issues
 // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 
-# openhwgroup/cvw Issue #55
-li x1, 0x7ff0000000000001
-fmv.w.x f4, x1
-li x1, 0x7ff8000000000000
-fmv.w.x f9, x1
-fsgnjx.s f12,f9,f4  # expected f 0xffffffff7fc00000
+.global rvtest_entry_point
+rvtest_entry_point:
 
+    # openhwgroup/cvw Issue #55
+    la a6, begin_signature
+    la a7, rvtest_data
+    fadd.d ft0, ft1, ft2
+    fld f4, 0(a7)
+    fld f9, 8(a7)
+#    li x1, 0x7ff0000000000001
+#    sd x1, 0(a6)
+#    fmv.w.x f4, x1
+#    li x1, 0x7ff8000000000000
+ #   fmv.w.x f9, x1
+    fsgnjx.s f12,f9,f4  # expected f 0xffffffff7fc00000
+    fsd f12, 0(a6)
 
 #########################
 # HTIF and signature
@@ -23,14 +32,20 @@ write_tohost:
 self_loop:
     j self_loop         # wait
     
+.align 6
 .section .tohost 
 tohost:                 # write to HTIF
     .dword 0
 fromhost:
     .dword 0
 
+.align 6
 .data
 
+rvtest_data:
+.dword 0x7ff0000000000001
+.dword 0x7ff8000000000000
+
 .EQU XLEN,64
 begin_signature:
     .fill 2*(XLEN/32),4,0xdeadbeef    # 

From 9454eb921de5f2e8b6f805532c612e05d2be20ee Mon Sep 17 00:00:00 2001
From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com>
Date: Sun, 5 Feb 2023 00:02:50 +0000
Subject: [PATCH 22/71] Now modifying dtim and irom even when USESRAM=1

---
 synthDC/Makefile | 38 ++++++++++++++++++++++++--------------
 1 file changed, 24 insertions(+), 14 deletions(-)

diff --git a/synthDC/Makefile b/synthDC/Makefile
index 613ca49af..e9f4ac171 100755
--- a/synthDC/Makefile
+++ b/synthDC/Makefile
@@ -6,8 +6,8 @@ NAME := synth
 
 # defaults
 export DESIGN ?= wallypipelinedcore
-export FREQ ?= 3000
-export CONFIG ?= rv32e
+export FREQ ?= 10000
+export CONFIG ?= rv64gc
 export MOD ?= orig
 # title to add a note in the synth's directory name
 TITLE = 
@@ -20,7 +20,7 @@ export MAXCORES ?= 1
 # The output netlist is hard to interpret, but significantly better PPA
 export MAXOPT ?= 0
 export DRIVE ?= FLOP
-export USESRAM ?= 0
+export USESRAM ?= 1
 
 time := $(shell date +%F-%H-%M)
 hash := $(shell git rev-parse --short HEAD)
@@ -55,25 +55,35 @@ $(CONFIG):
 	cp -r $(OLDCONFIGDIR)/shared/*.vh $(CONFIGDIR)
 	cp -r $(OLDCONFIGDIR)/$(CONFIG)/* $(CONFIGDIR)
 
+# adjust DTIM and IROM to reasonable values depending on config	
+ifneq ($(filter $(CONFIG), $(DIRS32)),)
+	sed -i "s/DTIM_RANGE.*/DTIM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh
+	sed -i "s/IROM_RANGE.*/IROM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh
+else ifneq ($(filter $(CONFIG), $(DIRS64)),)
+	sed -i "s/DTIM_RANGE.*/DTIM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh
+	sed -i "s/IROM_RANGE.*/IROM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh
+else 
+    $(info $(CONFIG) does not exist in $(DIRS32) or $(DIRS64))
+    @echo "Config not in list, RAM_RANGE will be unmodified"
+endif
+
+# if USESRAM = 1, set that in the config file, otherwise reduce sizes
 ifeq ($(USESRAM), 1)
 	sed -i 's/USE_SRAM.*/USE_SRAM 1/g' $(CONFIGDIR)/wally-shared.vh
 else
 	sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/wally-config.vh
 	sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/wally-config.vh
 	sed -i 's/BPRED_SIZE.*/BPRED_SIZE 5/g' $(CONFIGDIR)/wally-config.vh
-
-  ifneq ($(filter $(CONFIG), $(DIRS32)),)
-    sed -i "s/DTIM_RANGE.*/DTIM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh
-    sed -i "s/IROM_RANGE.*/IROM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh
-  else ifneq ($(filter $(CONFIG), $(DIRS64)),)
-    sed -i "s/DTIM_RANGE.*/DTIM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh
-    sed -i "s/IROM_RANGE.*/IROM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh
-  else 
-    $(info $(CONFIG) does not exist in $(DIRS32) or $(DIRS64))
-    @echo "Config not in list, RAM_RANGE will be unmodified"
-  endif
+ifneq ($(filter $(CONFIG), $(DIRS32)),)
+	sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh
+	sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/wally-config.vh
+else ifneq ($(filter $(CONFIG), $(DIRS64)),)
+	sed -i "s/BOOTROM_RANGE.*/BOOTROM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh
+	sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE	 56\'h01FF/g" $(CONFIGDIR)/wally-config.vh
+endif
 endif
 	
+# adjust config if synthesizing with any modifications
 ifeq ($(MOD), FPUoff)
 	# turn off FPU 
 	sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/wally-config.vh

From 66fa1e67bb4e584a194a074dcf1d2e15f4d6769c Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 4 Feb 2023 18:49:25 -0800
Subject: [PATCH 23/71] Removed redundant USE_SRAM from wally-shared.vh
 (already in wally-config.vh)

---
 config/shared/wally-shared.vh | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/config/shared/wally-shared.vh b/config/shared/wally-shared.vh
index 5d60fdce3..507388f7f 100644
--- a/config/shared/wally-shared.vh
+++ b/config/shared/wally-shared.vh
@@ -135,9 +135,6 @@
 `define DIVBLEN     ($clog2(`DIVb+1)-1)
 `define DIVa        (`DIVb+1-`XLEN)             // used for idiv on fpu
 
-// Memory synthesis configuration
-`define USE_SRAM 0
-
 // Disable spurious Verilator warnings
 
 /* verilator lint_off STMTDLY */

From 7cf98811f39b80aad074b746cd306a6c6b66d661 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 4 Feb 2023 18:49:47 -0800
Subject: [PATCH 24/71] Parenthesized reduction operators to avoid DC lint

---
 src/ebu/buscachefsm.sv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv
index 8467f3029..2f3e99228 100644
--- a/src/ebu/buscachefsm.sv
+++ b/src/ebu/buscachefsm.sv
@@ -116,7 +116,7 @@ module buscachefsm #(
   assign CaptureEn = (CurrState == DATA_PHASE & BusRW[1]) | (CurrState == CACHE_FETCH & HREADY);
   assign CacheAccess = CurrState == CACHE_FETCH | CurrState == CACHE_WRITEBACK;
 
-  assign BusStall = (CurrState == ADR_PHASE & (|BusRW | |CacheBusRW)) |
+  assign BusStall = (CurrState == ADR_PHASE & ((|BusRW) | (|CacheBusRW))) |
 					//(CurrState == DATA_PHASE & ~BusRW[0]) |  // *** replace the next line with this.  Fails uart test but i think it's a test problem not a hardware problem.
 					(CurrState == DATA_PHASE) | 
           (CurrState == CACHE_FETCH & ~HREADY) |
@@ -124,7 +124,7 @@ module buscachefsm #(
   assign BusCommitted = CurrState != ADR_PHASE;
 
   // AHB bus interface
-  assign HTRANS = (CurrState == ADR_PHASE & HREADY & (|BusRW | |CacheBusRW) & ~Flush) |
+  assign HTRANS = (CurrState == ADR_PHASE & HREADY & ((|BusRW) | (|CacheBusRW)) & ~Flush) |
                   (CacheAccess & FinalBeatCount & |CacheBusRW & HREADY) ? AHB_NONSEQ : // if we have a pipelined request
                   (CacheAccess & |BeatCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE;
 

From 077edbf78dbef5b247aa935c418e008d33f5dd0e Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 4 Feb 2023 20:13:24 -0800
Subject: [PATCH 25/71] changed USE_SRAM to modify wally-config rather than
 wally-shared

---
 synthDC/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/synthDC/Makefile b/synthDC/Makefile
index e9f4ac171..974626706 100755
--- a/synthDC/Makefile
+++ b/synthDC/Makefile
@@ -69,7 +69,7 @@ endif
 
 # if USESRAM = 1, set that in the config file, otherwise reduce sizes
 ifeq ($(USESRAM), 1)
-	sed -i 's/USE_SRAM.*/USE_SRAM 1/g' $(CONFIGDIR)/wally-shared.vh
+	sed -i 's/USE_SRAM.*/USE_SRAM 1/g' $(CONFIGDIR)/wally-config.vh
 else
 	sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/wally-config.vh
 	sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/wally-config.vh

From 232bfbcfd02558c5bcec557f4a017daa8c615c1a Mon Sep 17 00:00:00 2001
From: eroom1966 <moore@imperas.com>
Date: Mon, 6 Feb 2023 13:43:12 +0000
Subject: [PATCH 26/71] remerge changes

---
 sim/imperas.ic                 | 18 ++++++++++++++----
 sim/wally-imperas.do           |  6 ++++--
 testbench/testbench_imperas.sv |  7 ++++---
 3 files changed, 22 insertions(+), 9 deletions(-)

diff --git a/sim/imperas.ic b/sim/imperas.ic
index 164cec228..2f400b24a 100644
--- a/sim/imperas.ic
+++ b/sim/imperas.ic
@@ -1,20 +1,23 @@
-#--showoverrides
 --override cpu/show_c_prefix=T
 --override cpu/unaligned=F
 --override cpu/mstatus_FS=1
 
 # Enable the Imperas instruction coverage
--extlib    refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0
--override  refRoot/cpu/cv/cover=basic
--override  refRoot/cpu/cv/extensions=RV32I
+#-extlib    refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0
+#-override  refRoot/cpu/cv/cover=basic
+#-override  refRoot/cpu/cv/extensions=RV32I
 
 # Add Imperas simulator application instruction tracing
 --trace
 --tracechange
 --traceshowicount
 --tracemode
+--tracemem ASX
 --monitornetschange
 
+# Exceptions and pagetables debug
+--override cpu/debugflags=6
+
 # Turn on verbose output for Imperas simulator
 --verbose
 
@@ -24,3 +27,10 @@
 # Store simulator output to logfile
 --output imperas.log
 
+--override cpu/PMP_registers=0
+#--showoverrides
+#--mpdconsole
+
+# ignore settings of bits DAU for non leaf page table walks
+--override cpu/ignore_non_leaf_DAU=1
+
diff --git a/sim/wally-imperas.do b/sim/wally-imperas.do
index d08361e8c..4164b7bdb 100644
--- a/sim/wally-imperas.do
+++ b/sim/wally-imperas.do
@@ -46,10 +46,12 @@ vsim workopt +nowarn3829  -fatal 7 \
      +testDir=$env(TESTDIR) $env(OTHERFLAGS)
 view wave
 #-- display input and output signals as hexidecimal values
-add log -recursive /*
-do wave.do
+# add log -recursive /*
+# do wave.do
 
 run -all
 
 noview ../testbench/testbench_imperas.sv
 view wave
+
+quit -f
diff --git a/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv
index ce4b16de1..759787299 100644
--- a/testbench/testbench_imperas.sv
+++ b/testbench/testbench_imperas.sv
@@ -142,9 +142,10 @@ module testbench;
       if (!rvviVersionCheck(RVVI_API_VERSION)) begin
         msgfatal($sformatf("%m @ t=%0t: Expecting RVVI API version %0d.", $time, RVVI_API_VERSION));
       end
-      void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VENDOR,  "riscv.ovpworld.org"));
-      void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_NAME,    "riscv"));
-      void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VARIANT, "RV64GC"));
+      void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VENDOR,         "riscv.ovpworld.org"));
+      void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_NAME,           "riscv"));
+      void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VARIANT,        "RV64GC"));
+      void'(rvviRefConfigSetInt(IDV_CONFIG_MODEL_ADDRESS_BUS_WIDTH, 39));
       if (!rvviRefInit(elffilename)) begin
         msgfatal($sformatf("%m @ t=%0t: rvviRefInit failed", $time));
       end

From d88b56eebc1b66be5d782d3cc89f30adf7349a3b Mon Sep 17 00:00:00 2001
From: eroom1966 <moore@imperas.com>
Date: Mon, 6 Feb 2023 14:01:05 +0000
Subject: [PATCH 27/71] remove leading space

---
 sim/imperas.ic | 1 -
 1 file changed, 1 deletion(-)

diff --git a/sim/imperas.ic b/sim/imperas.ic
index 2f400b24a..016fdf505 100644
--- a/sim/imperas.ic
+++ b/sim/imperas.ic
@@ -33,4 +33,3 @@
 
 # ignore settings of bits DAU for non leaf page table walks
 --override cpu/ignore_non_leaf_DAU=1
-

From ae3ac025563331431456581bfa5fd321c54394fc Mon Sep 17 00:00:00 2001
From: eroom1966 <moore@imperas.com>
Date: Mon, 6 Feb 2023 15:53:29 +0000
Subject: [PATCH 28/71] remove dead code for ignoring fflags/fcsr

---
 testbench/testbench_imperas.sv | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv
index 759787299..e52a79c2e 100644
--- a/testbench/testbench_imperas.sv
+++ b/testbench/testbench_imperas.sv
@@ -164,11 +164,6 @@ module testbench;
           void'(rvviRefCsrSetVolatile(0, 32'hB82));   // MINSTRETH
       end
 
-  //    // Temporary fix for inexact difference
-//      void'(rvviRefCsrSetVolatile(0, 32'h001));   // fflags
-//      void'(rvviRefCsrSetVolatile(0, 32'h003));   // fcsr
-      
-      
       // Enable the trace2log module
       if ($value$plusargs("TRACE2LOG_ENABLE=%d", TRACE2LOG_ENABLE)) begin
         msgnote($sformatf("%m @ t=%0t: TRACE2LOG_ENABLE is %0d", $time, TRACE2LOG_ENABLE));

From a07684914bec3b3cbac2b1f70c37b3f83a90e8b6 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 6 Feb 2023 16:35:03 -0600
Subject: [PATCH 29/71] Updated imperas git repo to use a different hash.

---
 bin/imperas-one-time.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/bin/imperas-one-time.sh b/bin/imperas-one-time.sh
index 474bccea3..404636d7c 100755
--- a/bin/imperas-one-time.sh
+++ b/bin/imperas-one-time.sh
@@ -27,7 +27,7 @@
 ################################################################################################
 
 
-IMP_HASH=56b1479
+IMP_HASH=355a055ff7e36bc897e942e41f06e1baf96e34d5
 
 # clone the Imperas repo
 cd $WALY

From 4e8ef4a0ac014bdbae067fe2c92ee6560d20221f Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 6 Feb 2023 16:42:07 -0600
Subject: [PATCH 30/71] Removed unreachable if branch in hptw next state logic.

---
 src/mmu/hptw.sv | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv
index 5cf58ffdf..78975e38e 100644
--- a/src/mmu/hptw.sv
+++ b/src/mmu/hptw.sv
@@ -255,7 +255,6 @@ module hptw (
 			L2_RD: if (DCacheStallM)                     								NextWalkerState = L2_RD;
 				else                                     									NextWalkerState = L1_ADR;
 			L1_ADR: if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // first access in SV32
-					else if (ValidNonLeafPTE)            										NextWalkerState = L1_RD;
 					else 				                														NextWalkerState = LEAF;	
 			L1_RD: if (DCacheStallM)                     								NextWalkerState = L1_RD;
 				else                                     									NextWalkerState = L0_ADR;

From c33230d1c1995c78fcda438ea71618b79c63e1e2 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 6 Feb 2023 17:32:28 -0600
Subject: [PATCH 31/71] Fixed Bug 66. If a load missed at the same time as a
 spilled instruction fetch with an ITLB miss in the second cache line, the
 HPTW did not wait for the load miss to finish.

---
 src/mmu/hptw.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv
index 78975e38e..c0b7ad933 100644
--- a/src/mmu/hptw.sv
+++ b/src/mmu/hptw.sv
@@ -245,7 +245,7 @@ module hptw (
 	flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset | FlushW, 1'b1, NextWalkerState, IDLE, WalkerState); 
 	always_comb 
 		case (WalkerState)
-			IDLE: if (TLBMiss)	 																				NextWalkerState = InitialWalkerState;
+			IDLE: if (TLBMiss & ~DCacheStallM)	    																		NextWalkerState = InitialWalkerState;
 				  	else 																									NextWalkerState = IDLE;
 			L3_ADR:                     																NextWalkerState = L3_RD; // first access in SV48
 			L3_RD: if (DCacheStallM)    																NextWalkerState = L3_RD;

From 4c219de13d4791788d834d5d8988b0fc569124ce Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Mon, 6 Feb 2023 15:38:57 -0800
Subject: [PATCH 32/71] Fixed floating point crash in debug.S

---
 tests/custom/debug/Makefile | 8 +++++---
 tests/custom/debug/debug.S  | 2 ++
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/tests/custom/debug/Makefile b/tests/custom/debug/Makefile
index 9ee0b2e7b..4616dde67 100644
--- a/tests/custom/debug/Makefile
+++ b/tests/custom/debug/Makefile
@@ -17,11 +17,13 @@ $(TARGET).elf: $(TARGET).S Makefile
 
 sim:
 	spike --isa=rv64gc +signature=$(TARGET).signature.output +signature-granularity=8 $(TARGET).elf
-	diff --ignore-case $(TARGET).signature.output $(TARGET).reference_output || exit
-	echo "Signature matches! Success!"
+#	diff --ignore-case $(TARGET).signature.output $(TARGET).reference_output || exit
+#	echo "Signature matches! Success!"
+	mkdir -p ../work 
+	cp -f * ../work
 
 clean:
-	rm -f $(TARGET).elf $(TARGET).elf.*
+	rm -f $(TARGET).elf $(TARGET).elf.* *.signature.output
 
 
 
diff --git a/tests/custom/debug/debug.S b/tests/custom/debug/debug.S
index 431a261e5..5be3c2012 100644
--- a/tests/custom/debug/debug.S
+++ b/tests/custom/debug/debug.S
@@ -5,6 +5,8 @@
 
 .global rvtest_entry_point
 rvtest_entry_point:
+    lui t0, 0x1e            # turn on Floating point and XS
+    csrs mstatus, t0                 
 
     # openhwgroup/cvw Issue #55
     la a6, begin_signature

From 44fef2f2a169be60b91736f4b5619114a2eaa1a4 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Mon, 6 Feb 2023 16:47:56 -0800
Subject: [PATCH 33/71] debug simulating, produing discrepancy

---
 tests/custom/debug/Makefile | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/tests/custom/debug/Makefile b/tests/custom/debug/Makefile
index 4616dde67..ddabe4e31 100644
--- a/tests/custom/debug/Makefile
+++ b/tests/custom/debug/Makefile
@@ -2,8 +2,15 @@
 
 TARGET = debug
 
+$(TARGET).signature.output: $(TARGET).elf.memfile $(TARGET).elf
+	spike --isa=rv64gc +signature=$(TARGET).signature.output +signature-granularity=4 $(TARGET).elf
+#	diff --ignore-case $(TARGET).signature.output $(TARGET).reference_output || exit
+#	echo "Signature matches! Success!"
+	mkdir -p ../work 
+	cp -f * ../work
+
 $(TARGET).elf.memfile:$(TARGET).elf $(TARGET).elf.objdump.addr
-	riscv64-unknown-elf-elf2hex --bit-width $(if $(findstring rv64,$*),64,32) --input $< --output $@
+	riscv64-unknown-elf-elf2hex --bit-width 64 --input $< --output $@
 
 $(TARGET).elf.objdump.addr: $(TARGET).elf.objdump
 	extractFunctionRadix.sh $<
@@ -15,12 +22,6 @@ $(TARGET).elf: $(TARGET).S Makefile
 	riscv64-unknown-elf-gcc -g -o $(TARGET).elf -march=rv64gc -mabi=lp64 -mcmodel=medany \
 	    -nostartfiles -T$(WALLY)/examples/link/link.ld $(TARGET).S 
 
-sim:
-	spike --isa=rv64gc +signature=$(TARGET).signature.output +signature-granularity=8 $(TARGET).elf
-#	diff --ignore-case $(TARGET).signature.output $(TARGET).reference_output || exit
-#	echo "Signature matches! Success!"
-	mkdir -p ../work 
-	cp -f * ../work
 
 clean:
 	rm -f $(TARGET).elf $(TARGET).elf.* *.signature.output

From e92605e2deaa57dd8eebb5c3094cf7a0b01f58c3 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 7 Feb 2023 06:31:14 -0800
Subject: [PATCH 34/71] Disabled STATUS_FS at reset, fixing issue #71

---
 src/privileged/csrsr.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv
index c5d5e7a1f..92f0f5045 100644
--- a/src/privileged/csrsr.sv
+++ b/src/privileged/csrsr.sv
@@ -145,7 +145,7 @@ module csrsr (
       STATUS_MXR_INT <= #1 0;
       STATUS_SUM_INT <= #1 0;
       STATUS_MPRV_INT <= #1 0; // Per Priv 3.3
-      STATUS_FS_INT <= #1 `F_SUPPORTED ? 2'b01 : 2'b00;
+      STATUS_FS_INT <= #1 `F_SUPPORTED ? 2'b00 : 2'b00; // leave floating-point off until activated, even if F_SUPPORTED
       STATUS_MPP <= #1 0; 
       STATUS_SPP <= #1 0; 
       STATUS_MPIE <= #1 0; 

From 755c795f919e3d4a55cd0d5b2998d5ce01d7a156 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 7 Feb 2023 06:55:42 -0800
Subject: [PATCH 35/71] Moved STATUS_FS_INT write to if statement to properly
 prioritize

---
 src/privileged/csrsr.sv | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv
index 92f0f5045..1fa1fe8e7 100644
--- a/src/privileged/csrsr.sv
+++ b/src/privileged/csrsr.sv
@@ -156,8 +156,6 @@ module csrsr (
       STATUS_SBE <= #1 0;
       STATUS_UBE <= #1 0;
     end else if (~StallW) begin
-      if (FRegWriteM | WriteFRMM | WriteFFLAGSM) STATUS_FS_INT <= #1 2'b11; // mark Float State dirty  *** this should happen in M stage, be part of if/else;
- 
       if (TrapM) begin
         // Update interrupt enables per Privileged Spec p. 21
         // y = PrivilegeModeW
@@ -211,6 +209,6 @@ module csrsr (
         STATUS_SPIE <= #1 `S_SUPPORTED & CSRWriteValM[5];
         STATUS_SIE <= #1 `S_SUPPORTED & CSRWriteValM[1];
         STATUS_UBE <= #1 CSRWriteValM[6] & `U_SUPPORTED & `BIGENDIAN_SUPPORTED;
-     end 
+      end else if (FRegWriteM | WriteFRMM | WriteFFLAGSM) STATUS_FS_INT <= #1 2'b11; 
     end
 endmodule

From 0678f3f2b71a735b842e0ca70e595a19be7edc4e Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Tue, 7 Feb 2023 14:01:59 -0600
Subject: [PATCH 36/71] Branch predictor cleanup.

---
 sim/wave.do            | 559 ++++++++++++++++++++---------------------
 src/ifu/bpred/bpred.sv |  56 ++---
 testbench/tests.vh     |   1 +
 3 files changed, 305 insertions(+), 311 deletions(-)

diff --git a/sim/wave.do b/sim/wave.do
index 7ccb27fb8..5faf74f35 100644
--- a/sim/wave.do
+++ b/sim/wave.do
@@ -6,37 +6,37 @@ add wave -noupdate /testbench/reset
 add wave -noupdate /testbench/reset_ext
 add wave -noupdate /testbench/memfilename
 add wave -noupdate /testbench/dut/core/SATP_REGW
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
-add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/MDUStallD
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM
-add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD
-add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE
-add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM
-add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW
-add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallF
-add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallD
-add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE
-add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM
-add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
+add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/MDUStallD
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallF
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallD
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW
 add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName
 add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
 add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
@@ -68,26 +68,26 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
 add wave -noupdate -group {WriteBack stage} /testbench/PCW
 add wave -noupdate -group {WriteBack stage} /testbench/InstrW
 add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
-add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MCAUSE_REGW
-add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW
-add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW
-add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW
-add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MEPC_REGW
-add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIDELEG_REGW
-add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIE_REGW
-add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW
-add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW
-add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW
-add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW
-add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW
-add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW
-add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW
-add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW
-add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW
-add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
-add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW
-add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW
-add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MCAUSE_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEPC_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIDELEG_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIE_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
+add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW
+add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW
+add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS
 add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check}
 add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
 add wave -noupdate -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
@@ -181,209 +181,210 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK
-add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
-add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM
-add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
-add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM
-add wave -noupdate -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM
-add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM
-add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
-add wave -noupdate -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB
-add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
-add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK
-add wave -noupdate -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState
-add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY
-add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall
-add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS
-add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer
-add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA
-add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA
-add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall
-add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW
-add wave -noupdate -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW
-add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
-add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
-add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
-add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
-add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
-add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CAdr
-add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
-add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
-add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
-add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay
-add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate
-add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate
-add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded
-add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
-add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
-add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
-add wave -noupdate -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
-add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag
-add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn
-add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn
-add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag
-add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay
-add wave -noupdate -group lsu -expand -group dcache -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM[62]}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/we}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
-add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr
-add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
-add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
-add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
-add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
-add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData
-add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
-add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
-add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
-add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
-add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
-add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
-add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
-add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
-add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
-add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
-add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
-add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
-add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
-add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
-add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
-add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
-add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
-add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
-add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
-add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
-add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
-add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
-add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
-add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
-add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
-add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
-add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
-add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
-add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
-add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
-add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress
-add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM
-add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM
-add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW
-add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
-add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
-add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
-add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
-add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWalk
-add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/WalkerState
-add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWAdr
-add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PTE
-add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCFSpill
-add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/NextPageType
-add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PageType
-add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ValidNonLeafPTE
-add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
-add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
-add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ITLBWriteF
-add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWriteM
-add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSULoadAccessFaultM
-add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSUStoreAmoAccessFaultM
-add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWInstrAccessFaultM
-add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LoadAccessFaultM
-add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/StoreAmoAccessFaultM
+add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
+add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM
+add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
+add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM
+add wave -noupdate -expand -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM
+add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/FWriteDataM
+add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
+add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IgnoreRequestTLB
+add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
+add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/ebu/ebu/HCLK
+add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState
+add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY
+add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall
+add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS
+add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer
+add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA
+add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/LSUHWDATA
+add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall
+add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW
+add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW
+add wave -noupdate -expand -group lsu -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrE
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrM
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
+add wave -noupdate -expand -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
+add wave -noupdate -expand -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
+add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
+add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
+add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CAdr
+add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
+add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
+add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
+add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay
+add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate
+add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate
+add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded
+add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
+add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
+add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
+add wave -noupdate -expand -group lsu -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
+add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag
+add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn
+add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn
+add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag
+add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush
+add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
+add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
+add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr
+add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
+add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
+add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
+add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
+add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine
+add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr
+add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
+add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay
+add wave -noupdate -expand -group lsu -group dcache -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
+add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM[62]}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/we}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
+add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr
+add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
+add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
+add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
+add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
+add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData
+add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
+add wave -noupdate -expand -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
+add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
+add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
+add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
+add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
+add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
+add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
+add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
+add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
+add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
+add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
+add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
+add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWalk
+add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/WalkerState
+add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWAdr
+add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PTE
+add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCFSpill
+add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/NextPageType
+add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PageType
+add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ValidNonLeafPTE
+add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCFSpill
+add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
+add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
+add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ITLBWriteF
+add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWriteM
+add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSULoadAccessFaultM
+add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSUStoreAmoAccessFaultM
+add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWInstrAccessFaultM
+add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LoadAccessFaultM
+add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/StoreAmoAccessFaultM
 add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr
 add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr
 add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/MExtInt
@@ -540,28 +541,28 @@ add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2
 add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/bwe}
 add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/dout}
 add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
-add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/ITLBMissF
-add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/VAdr
-add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
-add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/Matches
-add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/InstrPageFaultF
-add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/TLBFlush
-add wave -noupdate -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Valid}
-add wave -noupdate -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/PageType}
-add wave -noupdate -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key}
-add wave -noupdate -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key0}
-add wave -noupdate -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key1}
-add wave -noupdate -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query0}
-add wave -noupdate -group ifu -expand -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query1}
-add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Valid}
-add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageTypeWriteVal}
-add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageType}
-add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key}
-add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key0}
-add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1}
-add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0}
-add wave -noupdate -group ifu -expand -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1}
+add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
+add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF
+add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/VAdr
+add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
+add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/Matches
+add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/InstrPageFaultF
+add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/TLBFlush
+add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Valid}
+add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/PageType}
+add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key}
+add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key0}
+add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Key1}
+add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query0}
+add wave -noupdate -group ifu -group itlb -expand -group key21 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[21]/Query1}
+add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Valid}
+add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageTypeWriteVal}
+add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/PageType}
+add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key}
+add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key0}
+add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1}
+add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0}
+add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1}
 add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
 add wave -noupdate -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
 add wave -noupdate -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
@@ -660,11 +661,9 @@ add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/InstrValidNotFlus
 add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/CSRUWriteM
 add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS
 add wave -noupdate /testbench/dut/core/priv/priv/csr/csru/csru/CSRAdrM
-add wave -noupdate /testbench/dut/core/ifu/MatchCopy
-add wave -noupdate /testbench/dut/core/ifu/PCLinkECopy
 add wave -noupdate /testbench/dut/core/ifu/PCLinkE
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {391801 ns} 1} {{Cursor 4} {1156601 ns} 1} {{Cursor 5} {353781 ns} 0}
+WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {391801 ns} 1} {{Cursor 4} {1156601 ns} 1} {{Cursor 5} {497341 ns} 0}
 quietly wave cursor active 5
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 194
@@ -680,4 +679,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {348453 ns} {359109 ns}
+WaveRestoreZoom {497212 ns} {497470 ns}
diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index 664149652..700ec4092 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -71,8 +71,6 @@ module bpred (
 
   logic [3:0]               BTBPredInstrClassF, PredInstrClassF, PredInstrClassD, PredInstrClassE;
   logic [`XLEN-1:0]         PredPCF, RASPCF;
-  logic                     TargetWrongE;
-  logic                     FallThroughWrongE;
   logic                     PredictionPCWrongE;
   logic                     PredictionInstrClassWrongE;
   logic [3:0]               InstrClassF, InstrClassD, InstrClassE, InstrClassW;
@@ -219,27 +217,37 @@ module bpred (
   flopenrc #(4) PredInstrClassRegE(clk, reset, FlushE, ~StallE, PredInstrClassD, PredInstrClassE);
 
   // Check the prediction
-  // first check if the target or fallthrough address matches what was predicted.
-  assign TargetWrongE = IEUAdrE != PCD;
-  assign FallThroughWrongE = PCLinkE != PCD;
-  // If the target is taken check the target rather than fallthrough.  The instruction needs to be a branch if PCSrcE is selected
-  // Remember the bpred can incorrectly predict a non cfi instruction as a branch taken.  If the real instruction is non cfi
-  // it must have selected the fall through.
-  assign PredictionPCWrongE = (PCSrcE  & (|InstrClassE) ? TargetWrongE : FallThroughWrongE);
+  // if it is a CFI then check if the next instruction address (PCD) matches the branch's target or fallthrough address.
+  // if the class prediction is wrong a regular instruction may have been predicted as a taken branch
+  // this will result in PCD not being equal to the fall through address PCLinkE (PCE+4).
+  // The next instruction is always valid as no other flush would occur at the same time as the branch and not
+  // also flush the branch.  This will change in a superscaler cpu. 
+  assign PredictionPCWrongE = PCCorrectE != PCD;
+  assign BPPredWrongE = PredictionPCWrongE & (|InstrClassE | BPPredClassNonCFIWrongE);
 
-  // The branch direction also need to checked.
-  // However if the direction is wrong then the pc will be wrong.  This is only relavent to checking the
-  // accuracy of the direciton prediction.
-  //assign DirPredictionWrongE = (BPPredE[1] ^ PCSrcE) & InstrClassE[0];
+  // The branch direction is checked inside each branch predictor, but does not actually matter for
+  // branch miss prediction recovery.  If the class or direction is wrong, but the target is correct
+  // we an ignore the branch miss-prediction.
+
+  // Output the predicted PC or corrected PC on miss-predict.
+  // Selects the BP or PC+2/4.
+  mux2 #(`XLEN) pcmux0(PCPlus2or4F, BPPredPCF, SelBPPredF, PCNext0F);
+  // If the prediction is wrong select the correct address.
+  mux2 #(`XLEN) pcmux1(PCNext0F, PCCorrectE, BPPredWrongE, PCNext1F);  
+  // Correct branch/jump target.
+  mux2 #(`XLEN) pccorrectemux(PCLinkE, IEUAdrE, PCSrcE, PCCorrectE);
   
+  // If the fence/csrw was predicted as a taken branch then we select PCF, rather PCE.
+  // Effectively this is PCM+4 or the non-existant PCLinkM
+  if(`INSTR_CLASS_PRED) mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPPredWrongM, NextValidPCE);
+  else	assign NextValidPCE = PCE;
+
   // Finally we need to check if the class is wrong.  When the class is wrong the BTB needs to be updated.
   // Also we want to track this in a performance counter.
   assign PredictionInstrClassWrongE = InstrClassE != PredInstrClassE;
+  // The remaining checks are used for performance counters.
+
 
-  // We want to output to the instruction fetch if the PC fetched was wrong.  If by chance the predictor was wrong about
-  // the direction or class, but correct about the target we don't have the flush the pipeline.  However we still
-  // need this information to verify the accuracy of the predictors.
-  assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE) | BPPredClassNonCFIWrongE;
 
   // If we have a jump, jump register or jal or jalr and the PC is wrong we need to increment the performance counter.
   //assign BTBPredPCWrongE = (InstrClassE[3] | InstrClassE[1] | InstrClassE[0]) & PredictionPCWrongE;
@@ -255,20 +263,6 @@ module bpred (
   // branch class prediction wrong.
   assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD;
   
-  // Selects the BP or PC+2/4.
-  mux2 #(`XLEN) pcmux0(PCPlus2or4F, BPPredPCF, SelBPPredF, PCNext0F);
-  // If the prediction is wrong select the correct address.
-  mux2 #(`XLEN) pcmux1(PCNext0F, PCCorrectE, BPPredWrongE, PCNext1F);  
-  // Correct branch/jump target.
-  mux2 #(`XLEN) pccorrectemux(PCLinkE, IEUAdrE, PCSrcE, PCCorrectE);
-  
-  // If the fence/csrw was predicted as a taken branch then we select PCF, rather PCE.
-  // Effectively this is PCM+4 or the non-existant PCLinkM
-  //  if(`BPCLASS) begin
-  mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPPredWrongM, NextValidPCE);
-  //  end else begin
-  //	assign NextValidPCE = PCE;
-  //  end
 
   // performance counters
   // 1. class         (class wrong / minstret) (PredictionInstrClassWrongM / csr)                    // Correct now
diff --git a/testbench/tests.vh b/testbench/tests.vh
index 397c66a0d..1e1065cf1 100644
--- a/testbench/tests.vh
+++ b/testbench/tests.vh
@@ -1747,6 +1747,7 @@ string imperas32f[] = '{
  
  string wally64priv[] = '{
     `WALLYTEST,
+//    "rv64i_m/privilege/src/BUG66",
     "rv64i_m/privilege/src/WALLY-csr-permission-s-01.S",
     "rv64i_m/privilege/src/WALLY-csr-permission-u-01.S",
     "rv64i_m/privilege/src/WALLY-mie-01.S",

From b9f05c02e3189af222c1b7f02483378dc4b46077 Mon Sep 17 00:00:00 2001
From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com>
Date: Tue, 7 Feb 2023 20:07:43 +0000
Subject: [PATCH 37/71] for feature sweep now adding feature modifications on
 top of each other

---
 synthDC/Makefile | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/synthDC/Makefile b/synthDC/Makefile
index 974626706..76531d950 100755
--- a/synthDC/Makefile
+++ b/synthDC/Makefile
@@ -84,22 +84,22 @@ endif
 endif
 	
 # adjust config if synthesizing with any modifications
-ifeq ($(MOD), FPUoff)
+ifneq ($(MOD), orig)
+	# PMP 0
+	sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/wally-config.vh
+ifneq ($(MOD), PMP0)
+	# no priv
+	sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/wally-config.vh
+ifneq ($(MOD), noPriv)
 	# turn off FPU 
 	sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/wally-config.vh
 	sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/wally-config.vh
-else ifeq ($(MOD), PMP16)
-	# PMP 16 
-	sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 16/' $(CONFIGDIR)/wally-config.vh
-else ifeq ($(MOD), PMP0)
-	# PMP 0
-	sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/wally-config.vh
-else ifeq ($(MOD), noMulDiv)
+ifneq ($(MOD), noFPU)
 	# no muldiv
 	sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/wally-config.vh
-else ifeq ($(MOD), noPriv)
-	# no priv
-	sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/wally-config.vh
+endif
+endif
+endif
 endif
 
 ifeq ($(SAIFPOWER), 1)

From 0cbf50ed805077de75a128e2505b29e19f916a10 Mon Sep 17 00:00:00 2001
From: Madeleine Masser-Frye <51804758+mmasserfrye@users.noreply.github.com>
Date: Tue, 7 Feb 2023 21:18:39 +0000
Subject: [PATCH 38/71] changed default freqs for synth sweeps updated plotting
 to not overlap labels

---
 synthDC/extractSummary.py | 12 ++++++------
 synthDC/wallySynth.py     | 10 +++++++---
 2 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py
index 430f86178..3d939644a 100755
--- a/synthDC/extractSummary.py
+++ b/synthDC/extractSummary.py
@@ -8,6 +8,7 @@ from matplotlib.cbook import flatten
 import matplotlib.pyplot as plt
 import matplotlib.lines as lines
 import numpy as np
+from adjustText import adjust_text
 from ppa.ppaAnalyze import noOutliers
 from matplotlib import ticker
 import argparse
@@ -149,9 +150,8 @@ def areaDelay(tech, delays, areas, labels, fig, ax, norm=False):
     
     ax.yaxis.set_major_formatter(ticker.StrMethodFormatter('{x:,.0f}'))
 
-    for i in range(len(labels)):
-        plt.annotate(labels[i], (delays[i], areas[i]), textcoords="offset points", xytext=(0,10), ha='center')
-
+    texts = [plt.text(delays[i], areas[i], labels[i], ha='center', va='center') for i in range(len(labels))]
+    adjust_text(texts)
     return fig
 
 
@@ -169,7 +169,7 @@ def plotFeatures(tech, width, config):
 
     fig = areaDelay(tech, delays, areas, labels, fig, ax)
 
-    titlestr = tech+'_'+width+config
+    titlestr = tech+'_'+width+config+'_'+str(freq)+'MHz'
     plt.title(titlestr)
     plt.savefig(final_directory + '/features_'+titlestr+'.png')
 
@@ -240,8 +240,8 @@ def addFO4axis(fig, ax, tech):
 if __name__ == '__main__':
 
     parser = argparse.ArgumentParser()
-    parser.add_argument("-s", "--skyfreq", type=int, default=3000, help = "Target frequency used for sky90 syntheses")
-    parser.add_argument("-t", "--tsmcfreq", type=int, default=10000, help = "Target frequency used for tsmc28 syntheses")
+    parser.add_argument("-s", "--skyfreq", type=int, default=1500, help = "Target frequency used for sky90 syntheses")
+    parser.add_argument("-t", "--tsmcfreq", type=int, default=5000, help = "Target frequency used for tsmc28 syntheses")
     args = parser.parse_args()
 
     TechSpec = namedtuple("TechSpec", "color shape targfreq fo4 add32area add32lpower add32denergy")
diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py
index 3c96c38ee..3253607d5 100755
--- a/synthDC/wallySynth.py
+++ b/synthDC/wallySynth.py
@@ -37,8 +37,6 @@ if __name__ == '__main__':
     args = parser.parse_args()
 
     tech = args.tech if args.tech else 'sky90'
-    defaultfreq = 3000 if tech == 'sky90' else 10000
-    freq = args.targetfreq if args.targetfreq else defaultfreq
     maxopt = int(args.maxopt)
     usesram = int(args.usesram)
     mod = 'orig'
@@ -49,12 +47,18 @@ if __name__ == '__main__':
         for freq in [round(sc+sc*x/100) for x in freqVaryPct]: # rv32e freq sweep
             runSynth(config, mod, tech, freq, maxopt, usesram)
     if args.configsweep:
+        defaultfreq = 1500 if tech == 'sky90' else 5000
+        freq = args.targetfreq if args.targetfreq else defaultfreq
         for config in ['rv32i', 'rv64gc', 'rv64i', 'rv32gc', 'rv32imc', 'rv32e']: #configs
             runSynth(config, mod, tech, freq, maxopt, usesram)
     if args.featuresweep:
+        defaultfreq = 500 if tech == 'sky90' else 1500
+        freq = args.targetfreq if args.targetfreq else defaultfreq
         config = args.version if args.version else 'rv64gc'
-        for mod in ['FPUoff', 'noMulDiv', 'noPriv', 'PMP0', 'PMP16']: # rv64gc path variations 'orig', 
+        for mod in ['noFPU', 'noMulDiv', 'noPriv', 'PMP0', 'orig']: 
             runSynth(config, mod, tech, freq, maxopt, usesram)
     else:
+        defaultfreq = 500 if tech == 'sky90' else 1500
+        freq = args.targetfreq if args.targetfreq else defaultfreq
         config = args.version if args.version else 'rv64gc'
         runSynth(config, mod, tech, freq, maxopt, usesram)
\ No newline at end of file

From ff7dc4f34ae1cf53ae3ffbddd65d5b1046ad2a6d Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Tue, 7 Feb 2023 15:22:14 -0600
Subject: [PATCH 39/71] fpga constraints updates

---
 fpga/constraints/debug2.xdc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc
index 8b0b7c448..7ea5bf6bd 100644
--- a/fpga/constraints/debug2.xdc
+++ b/fpga/constraints/debug2.xdc
@@ -281,7 +281,7 @@ connect_debug_port u_ila_0/probe53 [get_nets [list wallypipelinedsoc/core/hzu/Re
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe54]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
-connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsoc/core/hzu/TrapM ]]
+connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsoc/core/TrapM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe55]

From f41a8f9e624c0bc22da8b856cc0a62f037032a02 Mon Sep 17 00:00:00 2001
From: David Harris <74973295+davidharrishmc@users.noreply.github.com>
Date: Tue, 7 Feb 2023 16:35:44 -0800
Subject: [PATCH 40/71] Update README.md

gcc seems to have changed its path to executables
---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 400df6b3b..32e363569 100644
--- a/README.md
+++ b/README.md
@@ -125,7 +125,7 @@ Note: make --jobs will reduce compile time by compiling in parallel.  However, a
 We also need the elf2hex utility to convert executable files into hexadecimal files for Verilog simulation. Install with:
 
 	$ cd $RISCV
-	$ export PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH
+	$ export PATH=$RISCV/bin:$PATH
 	$ git clone https://github.com/sifive/elf2hex.git
 	$ cd elf2hex
 	$ autoreconf -i

From 76332cac064176397d436225475cd1bec1af4f23 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 7 Feb 2023 16:49:50 -0800
Subject: [PATCH 41/71] Paths changed in latest GCC

---
 README.md                       | 6 +++---
 bin/wally-tool-chain-install.sh | 6 ++++--
 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/README.md b/README.md
index 400df6b3b..a7e2b99d0 100644
--- a/README.md
+++ b/README.md
@@ -110,11 +110,11 @@ Ubuntu users may need to install and update various tools.  Beware when cutting
 
 ### Install RISC-V GCC Cross-Compiler
 
-To install GCC from source can take hours to compile. This configuration enables multilib to target many flavors of RISC-V.   This book is tested with GCC 12.2 (tagged 2022.09.21), but will likely work with newer versions as well. 
+To install GCC from source can take hours to compile. This configuration enables multilib to target many flavors of RISC-V.   This book is tested with GCC 12.2 (tagged 2023.01.31), but will likely work with newer versions as well. 
 
 	$ git clone https://github.com/riscv/riscv-gnu-toolchain 
 	$ cd riscv-gnu-toolchain 
-	$ git checkout 2022.09.21 
+	$ git checkout 2023.01.31 
 	$ ./configure --prefix=$RISCV --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
 	$ make --jobs
 
@@ -143,7 +143,7 @@ Spike also takes a while to install and compile, but this can be done concurrent
 	$ git clone https://github.com/riscv-software-src/riscv-isa-sim
 	$ mkdir riscv-isa-sim/build
 	$ cd riscv-isa-sim/build
-	$ ../configure --prefix=$RISCV --enable-commitlog 
+	$ ../configure --prefix=$RISCV 
 	$ make --jobs
 	$ make install 
 	$ cd ../arch_test_target/spike/device
diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh
index 2b45d8e77..c4d9ed741 100755
--- a/bin/wally-tool-chain-install.sh
+++ b/bin/wally-tool-chain-install.sh
@@ -54,13 +54,15 @@ fi
 cd $RISCV
 git clone https://github.com/riscv/riscv-gnu-toolchain
 cd riscv-gnu-toolchain
+git checkout 2023.01.31 
 ./configure --prefix=${RISCV} --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
 make -j ${NUM_THREADS}
 make install
 
 # elf2hex
 cd $RISCV
-export PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH
+#export PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH
+gexport PATH=$RISCV/bin:$PATH
 git clone https://github.com/sifive/elf2hex.git
 cd elf2hex
 autoreconf -i
@@ -87,7 +89,7 @@ cd $RISCV
 git clone https://github.com/riscv-software-src/riscv-isa-sim
 mkdir -p riscv-isa-sim/build
 cd riscv-isa-sim/build
-../configure --prefix=$RISCV --enable-commitlog
+../configure --prefix=$RISCV 
 make -j ${NUM_THREADS}
 make install 
 cd ../arch_test_target/spike/device

From 7f062cff8b0ee5f4b4a9469d70f8a83d5a3dd4e9 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Wed, 8 Feb 2023 13:02:21 -0800
Subject: [PATCH 42/71] Removed unnecessary --enable-multilib from gcc build
 commands because --with-multilib-generator implies it

---
 README.md                       | 2 +-
 bin/wally-tool-chain-install.sh | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/README.md b/README.md
index efd7e26cf..d8c2432d4 100644
--- a/README.md
+++ b/README.md
@@ -115,7 +115,7 @@ To install GCC from source can take hours to compile. This configuration enables
 	$ git clone https://github.com/riscv/riscv-gnu-toolchain 
 	$ cd riscv-gnu-toolchain 
 	$ git checkout 2023.01.31 
-	$ ./configure --prefix=$RISCV --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
+	$ ./configure --prefix=$RISCV --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
 	$ make --jobs
 
 Note: make --jobs will reduce compile time by compiling in parallel.  However, adding this option could dramatically increase the memory utilization of your local machine.
diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh
index c4d9ed741..331ca13d6 100755
--- a/bin/wally-tool-chain-install.sh
+++ b/bin/wally-tool-chain-install.sh
@@ -55,7 +55,7 @@ cd $RISCV
 git clone https://github.com/riscv/riscv-gnu-toolchain
 cd riscv-gnu-toolchain
 git checkout 2023.01.31 
-./configure --prefix=${RISCV} --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
+./configure --prefix=${RISCV} --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
 make -j ${NUM_THREADS}
 make install
 

From 962c0189914fe2116fa3ce2522eb8da4d7067107 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 8 Feb 2023 18:24:38 -0600
Subject: [PATCH 43/71] Simplified branch predictor.

---
 src/ifu/bpred/bpred.sv | 62 ++++++++++++++----------------------------
 src/ifu/bpred/btb.sv   |  4 +--
 2 files changed, 23 insertions(+), 43 deletions(-)

diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index 700ec4092..2d4dfe5c2 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -69,12 +69,12 @@ module bpred (
   logic                     PredValidF;
   logic [1:0]               DirPredictionF;
 
-  logic [3:0]               BTBPredInstrClassF, PredInstrClassF, PredInstrClassD, PredInstrClassE;
+  logic [3:0]               BTBPredInstrClassF, PredInstrClassF, PredInstrClassD;
   logic [`XLEN-1:0]         PredPCF, RASPCF;
   logic                     PredictionPCWrongE;
-  logic                     PredictionInstrClassWrongE;
+  logic                     AnyWrongPredInstrClassD, AnyWrongPredInstrClassE;
   logic [3:0]               InstrClassF, InstrClassD, InstrClassE, InstrClassW;
-  logic                     DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
+  logic                     DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE;
   
   logic                     SelBPPredF;
   logic [`XLEN-1:0]         BPPredPCF;
@@ -82,7 +82,6 @@ module bpred (
   logic [`XLEN-1:0] 		PCCorrectE;
   logic [3:0] 				WrongPredInstrClassD;
 
-
   logic BTBTargetWrongE;
   logic RASTargetWrongE;
   logic JumpOrTakenBranchE;
@@ -132,20 +131,15 @@ module bpred (
  -----/\----- EXCLUDED -----/\----- */
   end 
 
-  // this predictor will have two pieces of data,
-  // 1) A direction (1 = Taken, 0 = Not Taken)
-  // 2) Any information which is necessary for the predictor to build its next state.
-  // For a 2 bit table this is the prediction count.
-
   // Part 2 Branch target address prediction
-  // *** For now the BTB will house the direct and indirect targets
+  // BTB contains target address for all CFI
 
   btb TargetPredictor(.clk, .reset, .StallF, .StallD, .StallM, .FlushD, .FlushM,
           .PCNextF, .PCF, .PCD, .PCE,
           .PredPCF,
           .BTBPredInstrClassF,
           .PredValidF,
-          .PredictionInstrClassWrongE,
+          .AnyWrongPredInstrClassE,
           .IEUAdrE,
           .InstrClassD,
           .InstrClassE);
@@ -205,16 +199,15 @@ module bpred (
   flopenrc #(4) InstrClassRegM(clk, reset,  FlushM, ~StallM, InstrClassE, InstrClassM);
   flopenrc #(4) InstrClassRegW(clk, reset,  FlushW, ~StallW, InstrClassM, InstrClassW);
   flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPPredWrongE, BPPredWrongM);
-  flopenrc #(1) JumpOrTakenBranchMReg(clk, reset, FlushM, ~StallM, JumpOrTakenBranchE, JumpOrTakenBranchM);
 
   // branch predictor
   flopenrc #(4) BPPredWrongRegM(clk, reset, FlushM, ~StallM, 
-    {DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, PredictionInstrClassWrongE},
+    {DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, AnyWrongPredInstrClassE},
     {DirPredictionWrongM, BTBPredPCWrongM, RASPredPCWrongM, PredictionInstrClassWrongM});
 
   // pipeline the class
   flopenrc #(4) PredInstrClassRegD(clk, reset, FlushD, ~StallD, PredInstrClassF, PredInstrClassD);
-  flopenrc #(4) PredInstrClassRegE(clk, reset, FlushE, ~StallE, PredInstrClassD, PredInstrClassE);
+  flopenrc #(1) WrongInstrClassRegE(clk, reset, FlushE, ~StallE, AnyWrongPredInstrClassD, AnyWrongPredInstrClassE);
 
   // Check the prediction
   // if it is a CFI then check if the next instruction address (PCD) matches the branch's target or fallthrough address.
@@ -223,11 +216,13 @@ module bpred (
   // The next instruction is always valid as no other flush would occur at the same time as the branch and not
   // also flush the branch.  This will change in a superscaler cpu. 
   assign PredictionPCWrongE = PCCorrectE != PCD;
-  assign BPPredWrongE = PredictionPCWrongE & (|InstrClassE | BPPredClassNonCFIWrongE);
 
-  // The branch direction is checked inside each branch predictor, but does not actually matter for
-  // branch miss prediction recovery.  If the class or direction is wrong, but the target is correct
-  // we an ignore the branch miss-prediction.
+  // branch class prediction wrong.
+  assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD;
+  assign AnyWrongPredInstrClassD = |WrongPredInstrClassD;
+  
+  // Finally indicate if the branch predictor was wrong
+  assign BPPredWrongE = PredictionPCWrongE & (|InstrClassE | AnyWrongPredInstrClassE);
 
   // Output the predicted PC or corrected PC on miss-predict.
   // Selects the BP or PC+2/4.
@@ -242,27 +237,6 @@ module bpred (
   if(`INSTR_CLASS_PRED) mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPPredWrongM, NextValidPCE);
   else	assign NextValidPCE = PCE;
 
-  // Finally we need to check if the class is wrong.  When the class is wrong the BTB needs to be updated.
-  // Also we want to track this in a performance counter.
-  assign PredictionInstrClassWrongE = InstrClassE != PredInstrClassE;
-  // The remaining checks are used for performance counters.
-
-
-
-  // If we have a jump, jump register or jal or jalr and the PC is wrong we need to increment the performance counter.
-  //assign BTBPredPCWrongE = (InstrClassE[3] | InstrClassE[1] | InstrClassE[0]) & PredictionPCWrongE;
-  //assign BTBPredPCWrongE = TargetWrongE & (InstrClassE[3] | InstrClassE[1] | InstrClassE[0]) & PCSrcE;
-  assign BTBPredPCWrongE = BTBTargetWrongE;
-  
-  // similar with RAS. Over counts ras if the class prediction was wrong.
-  //assign RASPredPCWrongE = TargetWrongE & InstrClassE[2] & PCSrcE;
-  assign RASPredPCWrongE = RASTargetWrongE;
-  // Finally if the real instruction class is non CFI but the predictor said it was we need to count.
-  assign BPPredClassNonCFIWrongE = PredictionInstrClassWrongE & ~|InstrClassE;
-
-  // branch class prediction wrong.
-  assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD;
-  
 
   // performance counters
   // 1. class         (class wrong / minstret) (PredictionInstrClassWrongM / csr)                    // Correct now
@@ -270,11 +244,17 @@ module bpred (
   // 3. target ras    (ras target wrong / class[2])
   // 4. direction     (br dir wrong / class[0])
 
-  assign BTBTargetWrongE = (PredPCE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] | InstrClassE[3]) & PCSrcE;
-  assign RASTargetWrongE = (RASPCE != IEUAdrE) & InstrClassE[2] & PCSrcE;
+  // Unforuantely we can't relay on PCD to infer the correctness of the BTB or RAS because the class prediction 
+  // could be wrong or the fall through address selected for branch predict not taken.
+  // By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of
+  // both without the above inaccuracies.
+  assign BTBPredPCWrongE = (PredPCE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] | InstrClassE[3]) & PCSrcE;
+  assign RASPredPCWrongE = (RASPCE != IEUAdrE) & InstrClassE[2] & PCSrcE;
 
   assign JumpOrTakenBranchE = (InstrClassE[0] & PCSrcE) | InstrClassE[1] | InstrClassE[3];
   
+  flopenrc #(1) JumpOrTakenBranchMReg(clk, reset, FlushM, ~StallM, JumpOrTakenBranchE, JumpOrTakenBranchM);
+
   flopenrc #(`XLEN) BTBTargetDReg(clk, reset, FlushD, ~StallD, PredPCF, PredPCD);
   flopenrc #(`XLEN) BTBTargetEReg(clk, reset, FlushE, ~StallE, PredPCD, PredPCE);
 
diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv
index 7cf9ed993..c538636df 100644
--- a/src/ifu/bpred/btb.sv
+++ b/src/ifu/bpred/btb.sv
@@ -39,7 +39,7 @@ module btb #(parameter int Depth = 10 ) (
   output logic [3:0]       BTBPredInstrClassF,                        // BTB's guess at instruction class
   output logic             PredValidF,                             // BTB's guess is valid
   // update
-  input  logic             PredictionInstrClassWrongE,             // BTB's instruction class guess was wrong
+  input  logic             AnyWrongPredInstrClassE,             // BTB's instruction class guess was wrong
   input  logic [`XLEN-1:0] IEUAdrE,                                // Branch/jump target address to insert into btb
   input  logic [3:0]       InstrClassD,                            // Instruction class to insert into btb
   input  logic [3:0]       InstrClassE                             // Instruction class to insert into btb
@@ -98,7 +98,7 @@ module btb #(parameter int Depth = 10 ) (
 
   //assign PredValidF = MatchXF ? 1'b1 : TablePredValidF;
   
-  assign UpdateEn = |InstrClassE | PredictionInstrClassWrongE;
+  assign UpdateEn = |InstrClassE | AnyWrongPredInstrClassE;
 
   // An optimization may be using a PC relative address.
   ram2p1r1wbe #(2**Depth, `XLEN+4) memory(

From 2d7749db7fb9c150977fd32a5bb7fb8b147a604d Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Thu, 9 Feb 2023 14:48:02 -0600
Subject: [PATCH 44/71] Updated globalhistory predictor.

---
 src/ifu/bpred/bpred.sv                    |   3 +-
 src/ifu/bpred/speculativeglobalhistory.sv | 102 +++++++++-------------
 2 files changed, 44 insertions(+), 61 deletions(-)

diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index 2d4dfe5c2..fd9e8a923 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -103,8 +103,7 @@ module bpred (
   end else if (`BPRED_TYPE == "BPSPECULATIVEGLOBAL") begin:Predictor
     speculativeglobalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .DirPredictionF, .DirPredictionWrongE,
-      .BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]),
-      .BranchInstrW(InstrClassW[0]), .WrongPredInstrClassD, .PCSrcE);
+      .PredInstrClassF, .InstrClassD, .InstrClassE, .WrongPredInstrClassD, .PCSrcE);
 	    
   end else if (`BPRED_TYPE == "BPGSHARE") begin:Predictor
     gshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
diff --git a/src/ifu/bpred/speculativeglobalhistory.sv b/src/ifu/bpred/speculativeglobalhistory.sv
index 3ed9ba3e5..51dbb422b 100644
--- a/src/ifu/bpred/speculativeglobalhistory.sv
+++ b/src/ifu/bpred/speculativeglobalhistory.sv
@@ -29,35 +29,31 @@
 `include "wally-config.vh"
 
 module speculativeglobalhistory #(parameter int k = 10 ) (
-  input logic             clk,
-  input logic             reset,
-  input logic             StallF, StallD, StallE, StallM, StallW, 
-  input logic             FlushD, FlushE, FlushM, FlushW,
-  output logic [1:0]      DirPredictionF, 
-  output logic            DirPredictionWrongE,
+  input logic 			  clk,
+  input logic 			  reset,
+  input logic 			  StallF, StallD, StallE, StallM, StallW, 
+  input logic 			  FlushD, FlushE, FlushM, FlushW,
+  output logic [1:0] 	  DirPredictionF, 
+  output logic 			  DirPredictionWrongE,
   // update
-  input logic             BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
-  input logic [3:0]       WrongPredInstrClassD, 
-  input logic             PCSrcE
+  input logic [3:0] 	  PredInstrClassF, InstrClassD, InstrClassE,
+  input logic [3:0] 	  WrongPredInstrClassD, 
+  input logic 			  PCSrcE
 );
 
   logic                    MatchF, MatchD, MatchE;
   logic                    MatchNextX, MatchXF;
 
   logic [1:0]              TableDirPredictionF, DirPredictionD, DirPredictionE;
-  logic [1:0]              NewDirPredictionF, NewDirPredictionD, NewDirPredictionE;
-
-  logic [k-1:0]            GHRF;
-  logic 				   GHRExtraF;
-  logic [k-1:0] 		   GHRD, GHRE, GHRM, GHRW;
-  logic [k-1:0] 		   GHRNextF;
-  logic [k-1:0] 		   GHRNextD;
-  logic [k-1:0] 		   GHRNextE, GHRNextM, GHRNextW;
-  logic [k-1:0]            IndexNextF, IndexF;
-  logic [k-1:0]            IndexD, IndexE;
-  
+  logic [1:0]              NewDirPredictionE;
 
+  logic [k-1:0] 		   GHRF, GHRD, GHRE;
+  logic 				   GHRLastF;
+  logic [k-1:0] 		   GHRNextF, GHRNextD, GHRNextE;
+  logic [k-1:0]            IndexNextF, IndexF, IndexD, IndexE;
   logic [1:0]              ForwardNewDirPrediction, ForwardDirPredictionF;
+
+  logic 				   FlushDOrDirWrong;
   
   assign IndexNextF = GHRNextF;
   assign IndexF = GHRF;
@@ -70,20 +66,20 @@ module speculativeglobalhistory #(parameter int k = 10 ) (
     .rd1(TableDirPredictionF),
     .wa2(IndexE),
     .wd2(NewDirPredictionE),
-    .we2(BranchInstrE & ~StallM & ~FlushM),
+    .we2(InstrClassE[0]),
     .bwe2(1'b1));
 
   // if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage
   // and then register for use in the Fetch stage.
-  assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF);
-  assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD);
-  assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE);
+  assign MatchF = PredInstrClassF[0] & ~FlushD & (IndexNextF == IndexF);
+  assign MatchD = InstrClassD[0] & ~FlushE & (IndexNextF == IndexD);
+  assign MatchE = InstrClassE[0] & ~FlushM & (IndexNextF == IndexE);
   assign MatchNextX = MatchF | MatchD | MatchE;
 
   flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
 
-  assign ForwardNewDirPrediction = MatchF ? NewDirPredictionF :
-                                   MatchD ? NewDirPredictionD :
+  assign ForwardNewDirPrediction = MatchF ? {2{DirPredictionF[1]}} :
+                                   MatchD ? {2{DirPredictionD[1]}} :
                                    NewDirPredictionE ;
   
   flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF);
@@ -94,49 +90,37 @@ module speculativeglobalhistory #(parameter int k = 10 ) (
   flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD);
   flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
 
-  // New prediction pipeline
-  assign NewDirPredictionF = {DirPredictionF[1], DirPredictionF[1]};
   
-  flopenr #(2) NewPredDReg(clk, reset, ~StallD, NewDirPredictionF, NewDirPredictionD);
   satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
 
   // GHR pipeline
-  // this version fails the regression test do to pessimistic x propagation.
-  // assign GHRNextF = FlushD | DirPredictionWrongE ?  GHRNextD[k-1:0] :
-  //                  BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} :
-  //                  GHRF;
 
-  always_comb begin
-	if(FlushD | DirPredictionWrongE) begin
-	  GHRNextF = GHRNextD[k-1:0];
-	end else if(BranchInstrF) GHRNextF = {DirPredictionF[1], GHRF[k-1:1]};
-	else GHRNextF = GHRF;
-  end
+  // If Fetch has a branch, speculatively insert prediction into the GHR
+  // If the front end is flushed or the direction prediction is wrong, reset to
+  // most recent valid GHR.  For a BP wrong this is GHRD with the correct prediction shifted in.
+  // For FlushE this is GHRE.  GHRNextE is both.
+  assign FlushDOrDirWrong = FlushD | DirPredictionWrongE;
+  mux3 #(k) GHRFMux(GHRF, {DirPredictionF[1], GHRF[k-1:1]}, GHRNextE[k-1:0], 
+					{FlushDOrDirWrong, PredInstrClassF[0]}, GHRNextF);
 
-  flopenr  #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF);	
-  flopenr  #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRF[0], GHRExtraF);
+  // Need 1 extra bit to store the shifted out GHRF if repair needs to back shift.
+  flopenr  #(k) GHRFReg(clk, reset, ~StallF | FlushDOrDirWrong, GHRNextF, GHRF);	
+  flopenr  #(1) GHRFLastReg(clk, reset, ~StallF | FlushDOrDirWrong, GHRF[0], GHRLastF);
 
-  // use with out instruction class prediction
-  //assign GHRNextD = FlushD ? GHRNextE[k-1:0] : GHRF[k-1:0];
-  // with instruction class prediction
-  assign GHRNextD = (FlushD | DirPredictionWrongE) ? GHRNextE[k-1:0] :
-					WrongPredInstrClassD[0] & BranchInstrD  ? {DirPredictionD[1], GHRF[k-1:1]} : // shift right
-  					WrongPredInstrClassD[0] & ~BranchInstrD ? {GHRF[k-2:0], GHRExtraF}:       // shift left
-					GHRF[k-1:0];
+  // With instruction class prediction, the class could be wrong and is checked in Decode.
+  // If it is wrong and branch does exist then shift right and insert the prediction.
+  // If the branch does not exist then shift left and use GHRLastF to restore the LSB.
+  logic [k-1:0] 		   GHRClassWrong;
+  mux2 #(k) GHRClassWrongMux({DirPredictionD[1], GHRF[k-1:1]}, {GHRF[k-2:0], GHRLastF}, InstrClassD[0], GHRClassWrong);
+  // As with GHRF FlushD and wrong direction prediction flushes the pipeline and restores to GHRNextE.
+  mux3 #(k) GHRDMux(GHRF, GHRClassWrong, GHRNextE, {FlushDOrDirWrong, WrongPredInstrClassD[0]}, GHRNextD);
 
-  flopenr  #(k) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD);
+  flopenr  #(k) GHRDReg(clk, reset, ~StallD | FlushDOrDirWrong, GHRNextD, GHRD);
 
-  assign GHRNextE = BranchInstrE & ~FlushM ? {PCSrcE, GHRD[k-2:0]} :   // if the branch is not flushed
-					FlushE ? GHRNextM :                                // branch is flushed
-					GHRD;
-  flopenr  #(k) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, GHRE);
+  mux3 #(k) GHREMux(GHRD, GHRE, {PCSrcE, GHRD[k-2:0]}, {InstrClassE[0] & ~FlushM, FlushE}, GHRNextE);
 
-  assign GHRNextM = FlushM ? GHRNextW : GHRE;
-  flopenr  #(k) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM);
-
-  assign GHRNextW = FlushW ? GHRW : GHRM;
-  flopenr  #(k) GHRWReg(clk, reset, (BranchInstrW & ~StallW) | FlushW, GHRNextW, GHRW);
+  flopenr  #(k) GHREReg(clk, reset, ((InstrClassE[0] & ~FlushM) & ~StallE) | FlushE, GHRNextE, GHRE);
   
-  assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
+  assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & InstrClassE[0];
 
 endmodule

From edbf962b5f16c1081df762da49a4d5af85f893b7 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 9 Feb 2023 18:14:26 -0800
Subject: [PATCH 45/71] Test gen header

---
 tests/testgen/testgen_header.S | 13 ++-----------
 1 file changed, 2 insertions(+), 11 deletions(-)

diff --git a/tests/testgen/testgen_header.S b/tests/testgen/testgen_header.S
index 4129782f6..44a74f5d1 100644
--- a/tests/testgen/testgen_header.S
+++ b/tests/testgen/testgen_header.S
@@ -1,21 +1,12 @@
 //
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 ///////////////////////////////////////////
 
 #include "model_test.h"
 #include "arch_test.h"
+RVTEST_ISA("RV64I")
 
 .section .text.init
 .globl rvtest_entry_point

From 8fb513ad35389beadbdf3fed72310818c59a4f55 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 9 Feb 2023 18:24:48 -0800
Subject: [PATCH 46/71] Moved test generators

---
 .../testgen}/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py               | 0
 .../testgen}/testgen-ADDI-XORI-ORI-ANDI-SLTI.py                   | 0
 .../testgen}/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py                   | 0
 .../testgen}/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py                  | 0
 {tests/testgen/imperas => studies/testgen}/testgen-BRANCH.py      | 0
 {tests/testgen/imperas => studies/testgen}/testgen-CSR.py         | 0
 {tests/testgen/imperas => studies/testgen}/testgen-JAL-JALR.py    | 0
 {tests/testgen/imperas => studies/testgen}/testgen-LOAD.py        | 0
 {tests/testgen/imperas => studies/testgen}/testgen-PIPELINE.py    | 0
 {tests/testgen/imperas => studies/testgen}/testgen-SLL-SRL-SRA.py | 0
 .../testgen/imperas => studies/testgen}/testgen-SLLI-SRLI-SRAI.py | 0
 {tests/testgen/imperas => studies/testgen}/testgen-SLTIU.py       | 0
 {tests/testgen/imperas => studies/testgen}/testgen-STORE.py       | 0
 .../testgen/imperas => studies/testgen}/testgen-VIRTUALMEMORY.py  | 0
 14 files changed, 0 insertions(+), 0 deletions(-)
 rename {tests/testgen/imperas => studies/testgen}/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py (100%)
 rename {tests/testgen/imperas => studies/testgen}/testgen-ADDI-XORI-ORI-ANDI-SLTI.py (100%)
 rename {tests/testgen/imperas => studies/testgen}/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py (100%)
 rename {tests/testgen/imperas => studies/testgen}/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py (100%)
 rename {tests/testgen/imperas => studies/testgen}/testgen-BRANCH.py (100%)
 rename {tests/testgen/imperas => studies/testgen}/testgen-CSR.py (100%)
 rename {tests/testgen/imperas => studies/testgen}/testgen-JAL-JALR.py (100%)
 rename {tests/testgen/imperas => studies/testgen}/testgen-LOAD.py (100%)
 rename {tests/testgen/imperas => studies/testgen}/testgen-PIPELINE.py (100%)
 rename {tests/testgen/imperas => studies/testgen}/testgen-SLL-SRL-SRA.py (100%)
 rename {tests/testgen/imperas => studies/testgen}/testgen-SLLI-SRLI-SRAI.py (100%)
 rename {tests/testgen/imperas => studies/testgen}/testgen-SLTIU.py (100%)
 rename {tests/testgen/imperas => studies/testgen}/testgen-STORE.py (100%)
 rename {tests/testgen/imperas => studies/testgen}/testgen-VIRTUALMEMORY.py (100%)

diff --git a/tests/testgen/imperas/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py b/studies/testgen/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py
similarity index 100%
rename from tests/testgen/imperas/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py
rename to studies/testgen/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py
diff --git a/tests/testgen/imperas/testgen-ADDI-XORI-ORI-ANDI-SLTI.py b/studies/testgen/testgen-ADDI-XORI-ORI-ANDI-SLTI.py
similarity index 100%
rename from tests/testgen/imperas/testgen-ADDI-XORI-ORI-ANDI-SLTI.py
rename to studies/testgen/testgen-ADDI-XORI-ORI-ANDI-SLTI.py
diff --git a/tests/testgen/imperas/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py b/studies/testgen/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py
similarity index 100%
rename from tests/testgen/imperas/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py
rename to studies/testgen/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py
diff --git a/tests/testgen/imperas/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py b/studies/testgen/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py
similarity index 100%
rename from tests/testgen/imperas/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py
rename to studies/testgen/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py
diff --git a/tests/testgen/imperas/testgen-BRANCH.py b/studies/testgen/testgen-BRANCH.py
similarity index 100%
rename from tests/testgen/imperas/testgen-BRANCH.py
rename to studies/testgen/testgen-BRANCH.py
diff --git a/tests/testgen/imperas/testgen-CSR.py b/studies/testgen/testgen-CSR.py
similarity index 100%
rename from tests/testgen/imperas/testgen-CSR.py
rename to studies/testgen/testgen-CSR.py
diff --git a/tests/testgen/imperas/testgen-JAL-JALR.py b/studies/testgen/testgen-JAL-JALR.py
similarity index 100%
rename from tests/testgen/imperas/testgen-JAL-JALR.py
rename to studies/testgen/testgen-JAL-JALR.py
diff --git a/tests/testgen/imperas/testgen-LOAD.py b/studies/testgen/testgen-LOAD.py
similarity index 100%
rename from tests/testgen/imperas/testgen-LOAD.py
rename to studies/testgen/testgen-LOAD.py
diff --git a/tests/testgen/imperas/testgen-PIPELINE.py b/studies/testgen/testgen-PIPELINE.py
similarity index 100%
rename from tests/testgen/imperas/testgen-PIPELINE.py
rename to studies/testgen/testgen-PIPELINE.py
diff --git a/tests/testgen/imperas/testgen-SLL-SRL-SRA.py b/studies/testgen/testgen-SLL-SRL-SRA.py
similarity index 100%
rename from tests/testgen/imperas/testgen-SLL-SRL-SRA.py
rename to studies/testgen/testgen-SLL-SRL-SRA.py
diff --git a/tests/testgen/imperas/testgen-SLLI-SRLI-SRAI.py b/studies/testgen/testgen-SLLI-SRLI-SRAI.py
similarity index 100%
rename from tests/testgen/imperas/testgen-SLLI-SRLI-SRAI.py
rename to studies/testgen/testgen-SLLI-SRLI-SRAI.py
diff --git a/tests/testgen/imperas/testgen-SLTIU.py b/studies/testgen/testgen-SLTIU.py
similarity index 100%
rename from tests/testgen/imperas/testgen-SLTIU.py
rename to studies/testgen/testgen-SLTIU.py
diff --git a/tests/testgen/imperas/testgen-STORE.py b/studies/testgen/testgen-STORE.py
similarity index 100%
rename from tests/testgen/imperas/testgen-STORE.py
rename to studies/testgen/testgen-STORE.py
diff --git a/tests/testgen/imperas/testgen-VIRTUALMEMORY.py b/studies/testgen/testgen-VIRTUALMEMORY.py
similarity index 100%
rename from tests/testgen/imperas/testgen-VIRTUALMEMORY.py
rename to studies/testgen/testgen-VIRTUALMEMORY.py

From 9a6d7bb16ddf94362397213120fd3de637dce396 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 9 Feb 2023 18:25:24 -0800
Subject: [PATCH 47/71] Added RVTEST_CASE to testgen header

---
 tests/testgen/testgen_header.S | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/tests/testgen/testgen_header.S b/tests/testgen/testgen_header.S
index 44a74f5d1..a93e5af10 100644
--- a/tests/testgen/testgen_header.S
+++ b/tests/testgen/testgen_header.S
@@ -14,4 +14,7 @@ rvtest_entry_point:
 RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",temp)
+
+
 RVTEST_SIGBASE( x6, wally_signature)

From 91427ed72dfed67f42c89f57dd8b68ebbe9b91c1 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Fri, 10 Feb 2023 09:06:51 -0600
Subject: [PATCH 48/71] RAS and RAS documentation now consistent.

---
 src/ifu/bpred/RASPredictor.sv | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/ifu/bpred/RASPredictor.sv b/src/ifu/bpred/RASPredictor.sv
index 624d8e641..0a841ae11 100644
--- a/src/ifu/bpred/RASPredictor.sv
+++ b/src/ifu/bpred/RASPredictor.sv
@@ -42,7 +42,7 @@ module RASPredictor #(parameter int StackSize = 16 )(
   logic                     CounterEn;
   localparam Depth = $clog2(StackSize);
 
-  logic [Depth-1:0]         NextPtr, Ptr, PtrP1, PtrM1;
+  logic [Depth-1:0]         NextPtr, Ptr, P1, M1, IncDecPtr;
   logic [StackSize-1:0]     [`XLEN-1:0] memory;
   integer        index;
 
@@ -71,10 +71,11 @@ module RASPredictor #(parameter int StackSize = 16 )(
   assign CounterEn = PopF | PushE | RepairD;
 
   assign DecrementPtr = (PopF | DecRepairD) & ~IncrRepairD;
-  mux2 #(Depth) PtrMux(PtrP1, PtrM1, DecrementPtr, NextPtr);
 
-  assign PtrM1 = Ptr - 1'b1;
-  assign PtrP1 = Ptr + 1'b1;
+  assign P1 = 1;
+  assign M1 = '1; // -1
+  mux2 #(Depth) PtrMux(P1, M1, DecrementPtr, IncDecPtr);
+  assign NextPtr = Ptr + IncDecPtr;
 
   flopenr #(Depth) PTR(clk, reset, CounterEn, NextPtr, Ptr);
 
@@ -84,7 +85,7 @@ module RASPredictor #(parameter int StackSize = 16 )(
       for(index=0; index<StackSize; index++)
 		memory[index] <= {`XLEN{1'b0}};
     end else if(PushE) begin
-      memory[PtrP1] <= #1 PCLinkE;
+      memory[NextPtr] <= #1 PCLinkE;
     end
   end
 

From a1bdd9daa7d27600ec4566402776588c3eccc9bd Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Fri, 10 Feb 2023 09:07:06 -0600
Subject: [PATCH 49/71] Added new features to branch predictor analysis script.

---
 bin/parseHPMC.py | 62 ++++++++++++++++++++++++++++++++++++++----------
 1 file changed, 50 insertions(+), 12 deletions(-)

diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py
index 35bb9c82e..5b5ce522d 100755
--- a/bin/parseHPMC.py
+++ b/bin/parseHPMC.py
@@ -28,6 +28,7 @@
 import os
 import sys
 import matplotlib.pyplot as plt
+import re
 
 def ComputeCPI(benchmark):
     'Computes and inserts CPI into benchmark stats.'
@@ -145,6 +146,11 @@ def FormatToPlot(currBenchmark):
 
 if(sys.argv[1] == '-b'):
     configList = []
+    summery = 0
+    if(sys.argv[2] == '-s'):
+        summery = 1
+        sys.argv = sys.argv[1::]
+    print('summery = %d' % summery)
     for config in sys.argv[2::]:
         benchmarks = ProcessFile(config)
         ComputeAverage(benchmarks)
@@ -171,18 +177,50 @@ if(sys.argv[1] == '-b'):
 
     size = len(benchmarkDict)
     index = 1
-    print('Number of plots', size)
-    for benchmarkName in benchmarkDict:
-        currBenchmark = benchmarkDict[benchmarkName]
-        (names, values) = FormatToPlot(currBenchmark)
-        print(names, values)
-        plt.subplot(6, 7, index)
-        plt.bar(names, values)
-        plt.title(benchmarkName)
-        plt.ylabel('BR Dir Miss Rate (%)')
-        #plt.xlabel('Predictor')
-        index += 1
-    #plt.tight_layout()
+    print('summery = %d' % summery)
+    if(summery == 0):
+        print('Number of plots', size)
+        for benchmarkName in benchmarkDict:
+            currBenchmark = benchmarkDict[benchmarkName]
+            (names, values) = FormatToPlot(currBenchmark)
+            print(names, values)
+            plt.subplot(6, 7, index)
+            plt.bar(names, values)
+            plt.title(benchmarkName)
+            plt.ylabel('BR Dir Miss Rate (%)')
+            #plt.xlabel('Predictor')
+            index += 1
+    else:
+        combined = benchmarkDict['All_']
+        (name, value) = FormatToPlot(combined)
+        lst = []
+        dct = {}
+        category = []
+        length = []
+        accuracy = []
+        for index in range(0, len(name)):
+            match = re.match(r"([a-z]+)([0-9]+)", name[index], re.I)
+            percent = 100 -value[index]
+            if match:
+                (PredType, size) = match.groups()
+                category.append(PredType)
+                length.append(size)
+                accuracy.append(percent)
+                if(PredType not in dct):
+                    dct[PredType] = ([size], [percent])
+                else:
+                    (currSize, currPercent) = dct[PredType]
+                    currSize.append(size)
+                    currPercent.append(percent)
+                    dct[PredType] = (currSize, currPercent)
+        print(dct)
+        for cat in dct:
+            (x, y) = dct[cat]
+            plt.scatter(x, y, label=cat)
+            plt.plot(x, y)
+            plt.ylabel('Prediction Accuracy')
+            plt.xlabel('Size (b or k)')
+            plt.legend(loc='upper left')
     plt.show()
     
             

From ca0eb5a5912c788988bbb4927ff29cd6f058cb66 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Fri, 10 Feb 2023 10:33:10 -0600
Subject: [PATCH 50/71] Modified branch predictor to use InstrValidE and
 InstrValidD rather than the more complex InstrClassE | WrongClassE logic.

---
 src/ieu/controller.sv           | 4 ++--
 src/ieu/ieu.sv                  | 4 ++--
 src/ifu/bpred/bpred.sv          | 6 +++---
 src/ifu/ifu.sv                  | 3 ++-
 src/wally/wallypipelinedcore.sv | 5 +++--
 5 files changed, 12 insertions(+), 10 deletions(-)

diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv
index 1819de17c..108b0bb1e 100644
--- a/src/ieu/controller.sv
+++ b/src/ieu/controller.sv
@@ -62,7 +62,8 @@ module controller(
   output logic [2:0]  Funct3M,                 // Instruction's funct3 field
   output logic        RegWriteM,               // Instruction writes a register (needed for Hazard unit)
   output logic        InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$
-  output logic        InstrValidM,             // Instruction is valid
+  output logic        InstrValidD, InstrValidE, InstrValidM, // Instruction is valid
+
   output logic        FWriteIntM,              // FPU controller writes integer register file
   // Writeback stage control signals
   input  logic        StallW, FlushW,          // Stall, flush Writeback stage
@@ -96,7 +97,6 @@ module controller(
   logic        FenceXD;                        // Fence instruction
   logic        InvalidateICacheD, FlushDCacheD;// Invalidate I$, flush D$
   logic        CSRWriteD, CSRWriteE;           // CSR write
-  logic        InstrValidD, InstrValidE;       // Instruction is valid
   logic        PrivilegedD, PrivilegedE;       // Privileged instruction
   logic        InvalidateICacheE, FlushDCacheE;// Invalidate I$, flush D$
   logic [`CTRLW-1:0] ControlsD;                // Main Instruction Decoder control signals
diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv
index 681bd9826..9df95040d 100644
--- a/src/ieu/ieu.sv
+++ b/src/ieu/ieu.sv
@@ -54,7 +54,7 @@ module ieu (
   output logic [4:0]        RdM,                             // Destination register
   input  logic [`XLEN-1:0]  FIntResM,                        // Integer result from FPU (fmv, fclass, fcmp)
   output logic              InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$
-  output logic 		          InstrValidM,                     // Instruction is valid
+  output logic              InstrValidD, InstrValidE, InstrValidM,// Instruction is valid
   // Writeback stage signals
   input  logic [`XLEN-1:0]  FIntDivResultW,                  // Integer divide result from FPU fdivsqrt)
   input  logic [`XLEN-1:0]  CSRReadValW,                     // CSR read value, 
@@ -97,7 +97,7 @@ module ieu (
     .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .MemReadE, .CSRReadE, 
     .Funct3E, .IntDivE, .MDUE, .W64E, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM,
     .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M,
-    .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .FWriteIntM,
+    .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM,
     .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .StoreStallD);
 
   datapath   dp(
diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index fd9e8a923..c2ad9ac91 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -51,6 +51,7 @@ module bpred (
   input logic [31:0]       PostSpillInstrRawF,        // Instruction
 
   // Branch and jump outcome
+  input logic              InstrValidD, InstrValidE,
   input logic              PCSrcE,                    // Executation stage branch is taken
   input logic [`XLEN-1:0]  IEUAdrE,                   // The branch/jump target address
   input logic [`XLEN-1:0]  PCLinkE,                   // The address following the branch instruction. (AKA Fall through address)
@@ -220,8 +221,8 @@ module bpred (
   assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD;
   assign AnyWrongPredInstrClassD = |WrongPredInstrClassD;
   
-  // Finally indicate if the branch predictor was wrong
-  assign BPPredWrongE = PredictionPCWrongE & (|InstrClassE | AnyWrongPredInstrClassE);
+  // branch is wrong only if the PC does not match and both the Decode and Fetch stages have valid instructions.
+  assign BPPredWrongE = PredictionPCWrongE & InstrValidE & InstrValidD;
 
   // Output the predicted PC or corrected PC on miss-predict.
   // Selects the BP or PC+2/4.
@@ -236,7 +237,6 @@ module bpred (
   if(`INSTR_CLASS_PRED) mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPPredWrongM, NextValidPCE);
   else	assign NextValidPCE = PCE;
 
-
   // performance counters
   // 1. class         (class wrong / minstret) (PredictionInstrClassWrongM / csr)                    // Correct now
   // 2. target btb    (btb target wrong / class[0,1,3])  (btb target wrong / (br + j + jal)
diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv
index 956144de2..68350bac5 100644
--- a/src/ifu/ifu.sv
+++ b/src/ifu/ifu.sv
@@ -35,6 +35,7 @@ module ifu (
   // Command from CPU
   input  logic              InvalidateICacheM,                        // Clears all instruction cache valid bits
   input  logic         	    CSRWriteFenceM,                           // CSR write or fence instruction, PCNextF = the next valid PC (typically PCE)
+  input  logic              InstrValidD, InstrValidE, InstrValidM,
 	// Bus interface
   output logic [`PA_BITS-1:0] IFUHADDR,      // Bus address from IFU to EBU
   input  logic [`XLEN-1:0] 	HRDATA,           // Bus read data from IFU to EBU
@@ -322,7 +323,7 @@ module ifu (
   if (`BPRED_SUPPORTED) begin : bpred
     bpred bpred(.clk, .reset,
                 .StallF, .StallD, .StallE, .StallM, .StallW,
-                .FlushD, .FlushE, .FlushM, .FlushW,
+                .FlushD, .FlushE, .FlushM, .FlushW, .InstrValidD, .InstrValidE,
                 .InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCM, .PCSrcE, .IEUAdrE, .PCF, .NextValidPCE,
                 .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .PostSpillInstrRawF, .JumpOrTakenBranchM, .BPPredWrongM,
                 .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM);
diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv
index 2df96d1fb..3a57b9aed 100644
--- a/src/wally/wallypipelinedcore.sv
+++ b/src/wally/wallypipelinedcore.sv
@@ -68,7 +68,7 @@ module wallypipelinedcore (
   logic [`XLEN-1:0]               CSRReadValW, MDUResultW;
   logic [`XLEN-1:0]               UnalignedPCNextF, PCNext2F;
   logic [1:0] 					 MemRWM;
-  logic 						 InstrValidM;
+  logic 						 InstrValidD, InstrValidE, InstrValidM;
   logic                          InstrMisalignedFaultM;
   logic                          IllegalBaseInstrFaultD, IllegalIEUInstrFaultD;
   logic                          InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM;
@@ -166,6 +166,7 @@ module wallypipelinedcore (
   // instruction fetch unit: PC, branch prediction, instruction cache
   ifu ifu(.clk, .reset,
     .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+    .InstrValidM, .InstrValidE, .InstrValidD,
     // Fetch
     .HRDATA, .PCFSpill, .IFUHADDR, .PCNext2F,
     .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE,
@@ -201,7 +202,7 @@ module wallypipelinedcore (
      .RdE, .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM,
      // Writeback stage
      .CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[`XLEN-1:0]),
-     .InstrValidM, .FCvtIntResW, .FCvtIntW,
+     .InstrValidM, .InstrValidE, .InstrValidD, .FCvtIntResW, .FCvtIntW,
      // hazards
      .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
      .FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD, .PCSrcE,

From 6fbca64eb7a3cd6b86d7732b55d46ba8b95b4c10 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Fri, 10 Feb 2023 15:45:56 -0600
Subject: [PATCH 51/71] Experimental branch prediction optimization.

---
 src/ieu/controller.sv           |  4 ++--
 src/ieu/ieu.sv                  |  5 +++--
 src/ifu/bpred/bpred.sv          | 23 ++++++++++++++++-------
 src/ifu/ifu.sv                  |  5 ++++-
 src/wally/wallypipelinedcore.sv |  3 +++
 5 files changed, 28 insertions(+), 12 deletions(-)

diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv
index 108b0bb1e..d66425343 100644
--- a/src/ieu/controller.sv
+++ b/src/ieu/controller.sv
@@ -63,6 +63,8 @@ module controller(
   output logic        RegWriteM,               // Instruction writes a register (needed for Hazard unit)
   output logic        InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$
   output logic        InstrValidD, InstrValidE, InstrValidM, // Instruction is valid
+  output logic        BranchD, BranchE,
+  output logic        JumpD,
 
   output logic        FWriteIntM,              // FPU controller writes integer register file
   // Writeback stage control signals
@@ -85,8 +87,6 @@ module controller(
   logic 	     RegWriteD, RegWriteE;           // RegWrite (register will be written)
   logic [2:0]  ResultSrcD, ResultSrcE, ResultSrcM; // Select which result to write back to register file
   logic [1:0]  MemRWD, MemRWE;                 // Store (write to memory)
-  logic		     JumpD;                          // Jump instruction
-  logic		     BranchD, BranchE;               // Branch instruction
   logic	       ALUOpD;                         // 0 for address generation, 1 for all other operations (must use Funct3)
   logic [2:0]  ALUControlD;                    // Determines ALU operation
   logic 	     ALUSrcAD, ALUSrcBD;             // ALU inputs
diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv
index 9df95040d..9d3a833e9 100644
--- a/src/ieu/ieu.sv
+++ b/src/ieu/ieu.sv
@@ -55,6 +55,8 @@ module ieu (
   input  logic [`XLEN-1:0]  FIntResM,                        // Integer result from FPU (fmv, fclass, fcmp)
   output logic              InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$
   output logic              InstrValidD, InstrValidE, InstrValidM,// Instruction is valid
+  output logic              BranchD, BranchE,
+  output logic              JumpD, JumpE,
   // Writeback stage signals
   input  logic [`XLEN-1:0]  FIntDivResultW,                  // Integer divide result from FPU fdivsqrt)
   input  logic [`XLEN-1:0]  CSRReadValW,                     // CSR read value, 
@@ -87,7 +89,6 @@ module ieu (
   logic [1:0] ForwardAE, ForwardBE;                          // Select signals for forwarding multiplexers
   logic       RegWriteM, RegWriteW;                          // Register will be written in Memory, Writeback stages
   logic       MemReadE, CSRReadE;                            // Load, CSRRead instruction
-  logic       JumpE;                                         // Jump instruction
   logic       BranchSignedE;                                 // Branch does signed comparison on operands
   logic       MDUE;                                          // Multiply/divide instruction
            
@@ -95,7 +96,7 @@ module ieu (
     .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD,
     .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, .StallE, .FlushE, .FlagsE, .FWriteIntE,
     .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .MemReadE, .CSRReadE, 
-    .Funct3E, .IntDivE, .MDUE, .W64E, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM,
+    .Funct3E, .IntDivE, .MDUE, .W64E, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM,
     .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M,
     .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM,
     .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .StoreStallD);
diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index c2ad9ac91..82bc5323d 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -52,6 +52,8 @@ module bpred (
 
   // Branch and jump outcome
   input logic              InstrValidD, InstrValidE,
+  input  logic             BranchD, BranchE,
+  input  logic             JumpD, JumpE,
   input logic              PCSrcE,                    // Executation stage branch is taken
   input logic [`XLEN-1:0]  IEUAdrE,                   // The branch/jump target address
   input logic [`XLEN-1:0]  PCLinkE,                   // The address following the branch instruction. (AKA Fall through address)
@@ -189,11 +191,17 @@ module bpred (
 
   assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF;
 
-  assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5
-  assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5
-  assign InstrClassD[1] = (InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01) | // jump register, but not return
-						  (InstrD[6:0] == 7'h6F & (InstrD[11:7] & 5'h1B) != 5'h01); // jump, RD != x1 or x5
-  assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch
+  //assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5
+  //assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5
+  //assign InstrClassD[1] = (InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01) | // jump register, but not return
+  //                        (InstrD[6:0] == 7'h6F & (InstrD[11:7] & 5'h1B) != 5'h01); // jump, RD != x1 or x5
+  //assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch
+  assign InstrClassD[0] = BranchD;
+  assign InstrClassD[1] = JumpD ;
+  assign InstrClassD[2] = JumpD & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or x5
+  assign InstrClassD[3] = JumpD & (InstrD[11:7] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5
+  
+  
 
   flopenrc #(4) InstrClassRegE(clk, reset,  FlushE, ~StallE, InstrClassD, InstrClassE);
   flopenrc #(4) InstrClassRegM(clk, reset,  FlushM, ~StallM, InstrClassE, InstrClassM);
@@ -247,10 +255,11 @@ module bpred (
   // could be wrong or the fall through address selected for branch predict not taken.
   // By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of
   // both without the above inaccuracies.
-  assign BTBPredPCWrongE = (PredPCE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] | InstrClassE[3]) & PCSrcE;
+  //assign BTBPredPCWrongE = (PredPCE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] | InstrClassE[3]) & PCSrcE;
+  assign BTBPredPCWrongE = (PredPCE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] & ~InstrClassE[2]) & PCSrcE;
   assign RASPredPCWrongE = (RASPCE != IEUAdrE) & InstrClassE[2] & PCSrcE;
 
-  assign JumpOrTakenBranchE = (InstrClassE[0] & PCSrcE) | InstrClassE[1] | InstrClassE[3];
+  assign JumpOrTakenBranchE = (InstrClassE[0] & PCSrcE) | InstrClassE[1];
   
   flopenrc #(1) JumpOrTakenBranchMReg(clk, reset, FlushM, ~StallM, JumpOrTakenBranchE, JumpOrTakenBranchM);
 
diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv
index 68350bac5..51317e0b0 100644
--- a/src/ifu/ifu.sv
+++ b/src/ifu/ifu.sv
@@ -36,6 +36,8 @@ module ifu (
   input  logic              InvalidateICacheM,                        // Clears all instruction cache valid bits
   input  logic         	    CSRWriteFenceM,                           // CSR write or fence instruction, PCNextF = the next valid PC (typically PCE)
   input  logic              InstrValidD, InstrValidE, InstrValidM,
+  input  logic              BranchD, BranchE,
+  input  logic              JumpD, JumpE,
 	// Bus interface
   output logic [`PA_BITS-1:0] IFUHADDR,      // Bus address from IFU to EBU
   input  logic [`XLEN-1:0] 	HRDATA,           // Bus read data from IFU to EBU
@@ -323,7 +325,8 @@ module ifu (
   if (`BPRED_SUPPORTED) begin : bpred
     bpred bpred(.clk, .reset,
                 .StallF, .StallD, .StallE, .StallM, .StallW,
-                .FlushD, .FlushE, .FlushM, .FlushW, .InstrValidD, .InstrValidE,
+                .FlushD, .FlushE, .FlushM, .FlushW, .InstrValidD, .InstrValidE, 
+                .BranchD, .BranchE, .JumpD, .JumpE,
                 .InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCM, .PCSrcE, .IEUAdrE, .PCF, .NextValidPCE,
                 .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .PostSpillInstrRawF, .JumpOrTakenBranchM, .BPPredWrongM,
                 .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM);
diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv
index 3a57b9aed..a03caea15 100644
--- a/src/wally/wallypipelinedcore.sv
+++ b/src/wally/wallypipelinedcore.sv
@@ -162,11 +162,13 @@ module wallypipelinedcore (
   logic                          FCvtIntE;
   logic                          CommittedF;
   logic 						 JumpOrTakenBranchM;
+  logic 						 BranchD, BranchE, JumpD, JumpE;
   
   // instruction fetch unit: PC, branch prediction, instruction cache
   ifu ifu(.clk, .reset,
     .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
     .InstrValidM, .InstrValidE, .InstrValidD,
+    .BranchD, .BranchE, .JumpD, .JumpE,
     // Fetch
     .HRDATA, .PCFSpill, .IFUHADDR, .PCNext2F,
     .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE,
@@ -200,6 +202,7 @@ module wallypipelinedcore (
      .Funct3M, // size and signedness to LSU
      .SrcAM, // to privilege and fpu
      .RdE, .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM,
+     .BranchD, .BranchE, .JumpD, .JumpE,
      // Writeback stage
      .CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[`XLEN-1:0]),
      .InstrValidM, .InstrValidE, .InstrValidD, .FCvtIntResW, .FCvtIntW,

From 91fc883f6a1706ecb28d4d0660a83bac74c5a657 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Fri, 10 Feb 2023 17:09:35 -0600
Subject: [PATCH 52/71] More simplifications to the BP.

---
 src/ifu/bpred/bpred.sv | 24 ++++++++----------------
 1 file changed, 8 insertions(+), 16 deletions(-)

diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index 82bc5323d..0a01469d2 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -76,7 +76,7 @@ module bpred (
   logic [`XLEN-1:0]         PredPCF, RASPCF;
   logic                     PredictionPCWrongE;
   logic                     AnyWrongPredInstrClassD, AnyWrongPredInstrClassE;
-  logic [3:0]               InstrClassF, InstrClassD, InstrClassE, InstrClassW;
+  logic [3:0]               InstrClassF, InstrClassD, InstrClassE;
   logic                     DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE;
   
   logic                     SelBPPredF;
@@ -154,6 +154,7 @@ module bpred (
 	
 	assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]};
 
+//	*** still need to update to use inclusive jump
 	assign cjal = CompressedOpcF == 5'h09 & `XLEN == 32;
 	assign cj = CompressedOpcF == 5'h0d;
 	assign cjr = CompressedOpcF == 5'h14 & ~PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0;
@@ -162,9 +163,10 @@ module bpred (
 	assign InstrClassF[0] = PostSpillInstrRawF[6:0] == 7'h63 | 
 							(`C_SUPPORTED & CompressedOpcF[4:1] == 4'h7);
 	
-	assign InstrClassF[1] = (PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) != 5'h01 & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump register, but not return
-							(PostSpillInstrRawF[6:0] == 7'h6F & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump, RD != x1 or x5
-							(`C_SUPPORTED & (cj | (cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01)) ));
+	//assign InstrClassF[1] = (PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) != 5'h01 & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump register, but not return
+	//						(PostSpillInstrRawF[6:0] == 7'h6F & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump, RD != x1 or x5
+	//						(`C_SUPPORTED & (cj | (cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01)) ));
+	assign InstrClassF[1] = PostSpillInstrRawF[6:0] == 7'h67 | PostSpillInstrRawF[6:0] == 7'h6F | (`C_SUPPORTED & (cjal | cj | cj | cjalr));
 	
 	assign InstrClassF[2] = PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01 | // return must return to ra or r5
 							(`C_SUPPORTED & (cjalr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01));
@@ -173,15 +175,11 @@ module bpred (
 							(`C_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01)));
 	assign PredInstrClassF = InstrClassF;
 	assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | 
-						PredInstrClassF[2] |
-						PredInstrClassF[1] |
-						PredInstrClassF[3];
+						PredInstrClassF[1];
   end else begin
 	assign PredInstrClassF = BTBPredInstrClassF;
 	assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | 
-						PredInstrClassF[2] |
-						(PredInstrClassF[1] & PredValidF) |
-						(PredInstrClassF[3] & PredValidF);
+						PredInstrClassF[1] & PredValidF;
   end
   
   // Part 3 RAS
@@ -191,11 +189,6 @@ module bpred (
 
   assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF;
 
-  //assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5
-  //assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5
-  //assign InstrClassD[1] = (InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01) | // jump register, but not return
-  //                        (InstrD[6:0] == 7'h6F & (InstrD[11:7] & 5'h1B) != 5'h01); // jump, RD != x1 or x5
-  //assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch
   assign InstrClassD[0] = BranchD;
   assign InstrClassD[1] = JumpD ;
   assign InstrClassD[2] = JumpD & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or x5
@@ -205,7 +198,6 @@ module bpred (
 
   flopenrc #(4) InstrClassRegE(clk, reset,  FlushE, ~StallE, InstrClassD, InstrClassE);
   flopenrc #(4) InstrClassRegM(clk, reset,  FlushM, ~StallM, InstrClassE, InstrClassM);
-  flopenrc #(4) InstrClassRegW(clk, reset,  FlushW, ~StallW, InstrClassM, InstrClassW);
   flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPPredWrongE, BPPredWrongM);
 
   // branch predictor

From 2dfbf15ff9169485927d43bf6d49806aa0093fa8 Mon Sep 17 00:00:00 2001
From: Kevin Kim <kevindkim723@gmail.com>
Date: Sat, 11 Feb 2023 19:59:03 -0800
Subject: [PATCH 53/71] fixed typo in LZC

---
 src/generic/lzc.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/generic/lzc.sv b/src/generic/lzc.sv
index 60719c494..ecfd6796a 100644
--- a/src/generic/lzc.sv
+++ b/src/generic/lzc.sv
@@ -33,6 +33,6 @@ module lzc #(parameter WIDTH = 1) (
   always_comb begin
     i = 0;
     while (~num[WIDTH-1-i] & (i < WIDTH)) i = i+1;  // search for leading one
-    ZeroCnt = i[$clog2(WIDTH)-1:0];
+    ZeroCnt = i[$clog2(WIDTH+1)-1:0];
   end
 endmodule

From 51158e94bafddc7cde3557190b87ec7f51d33d9b Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 12 Feb 2023 11:33:43 -0600
Subject: [PATCH 54/71] Removed another bit from btb class.

---
 src/ifu/bpred/RASPredictor.sv             |  6 ++-
 src/ifu/bpred/bpred.sv                    | 47 ++++++++++++-----------
 src/ifu/bpred/btb.sv                      | 19 ++++-----
 src/ifu/bpred/speculativeglobalhistory.sv |  4 +-
 src/ifu/bpred/speculativegshare.sv        |  5 ++-
 5 files changed, 42 insertions(+), 39 deletions(-)

diff --git a/src/ifu/bpred/RASPredictor.sv b/src/ifu/bpred/RASPredictor.sv
index 0a841ae11..40fb5bb15 100644
--- a/src/ifu/bpred/RASPredictor.sv
+++ b/src/ifu/bpred/RASPredictor.sv
@@ -33,8 +33,10 @@ module RASPredictor #(parameter int StackSize = 16 )(
   input  logic             clk,
   input  logic 			   reset, 
   input  logic 			   StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM,
-  input  logic [3:0] 	   WrongPredInstrClassD,                      // Prediction class is wrong
-  input  logic [3:0] 	   InstrClassD, InstrClassE, PredInstrClassF, // Instr class
+  input  logic [2:0] 	   WrongPredInstrClassD,                      // Prediction class is wrong
+  input  logic [3:0] 	   InstrClassD,
+  input  logic [3:0]       InstrClassE,                  // Instr class
+  input  logic [2:0]       PredInstrClassF,
   input  logic [`XLEN-1:0] PCLinkE,                                   // PC of instruction after a jal
   output logic [`XLEN-1:0] RASPCF                                     // Top of the stack
    );
diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index 0a01469d2..8a1eb801b 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -72,22 +72,24 @@ module bpred (
   logic                     PredValidF;
   logic [1:0]               DirPredictionF;
 
-  logic [3:0]               BTBPredInstrClassF, PredInstrClassF, PredInstrClassD;
+  logic [2:0]               BTBPredInstrClassF, PredInstrClassF, PredInstrClassD;
   logic [`XLEN-1:0]         PredPCF, RASPCF;
   logic                     PredictionPCWrongE;
   logic                     AnyWrongPredInstrClassD, AnyWrongPredInstrClassE;
-  logic [3:0]               InstrClassF, InstrClassD, InstrClassE;
+  logic [2:0] 				InstrClassF;
+  logic [3:0]               InstrClassD;
+  logic [3:0] 				InstrClassE;
   logic                     DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE;
   
   logic                     SelBPPredF;
   logic [`XLEN-1:0]         BPPredPCF;
   logic [`XLEN-1:0]         PCNext0F;
   logic [`XLEN-1:0] 		PCCorrectE;
-  logic [3:0] 				WrongPredInstrClassD;
+  logic [2:0] 				WrongPredInstrClassD;
 
-  logic BTBTargetWrongE;
-  logic RASTargetWrongE;
-  logic JumpOrTakenBranchE;
+  logic 					BTBTargetWrongE;
+  logic 					RASTargetWrongE;
+  logic 					JumpOrTakenBranchE;
 
   logic [`XLEN-1:0] PredPCD, PredPCE, RASPCD, RASPCE;
 
@@ -149,30 +151,31 @@ module bpred (
   // the branch predictor needs a compact decoding of the instruction class.
   if (`INSTR_CLASS_PRED == 0) begin : DirectClassDecode
 	logic [4:0] CompressedOpcF;
-	logic [3:0] InstrClassF;
-	logic 		cjal, cj, cjr, cjalr;
+	logic [2:0] InstrClassF;
+	logic 		cjal, cj, cjr, cjalr, CJumpF, CBranchF;
+	logic 		JumpF, BranchF;
 	
 	assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]};
 
-//	*** still need to update to use inclusive jump
 	assign cjal = CompressedOpcF == 5'h09 & `XLEN == 32;
 	assign cj = CompressedOpcF == 5'h0d;
 	assign cjr = CompressedOpcF == 5'h14 & ~PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0;
 	assign cjalr = CompressedOpcF == 5'h14 & PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0;
+	assign CJumpF = cjal | cj | cjr | cjalr;
+	assign CBranchF = CompressedOpcF[4:1] == 4'h7;
+
+	assign JumpF = PostSpillInstrRawF[6:0] == 7'h67 | PostSpillInstrRawF[6:0] == 7'h6F;
+	assign BranchF = PostSpillInstrRawF[6:0] == 7'h63;
 	
-	assign InstrClassF[0] = PostSpillInstrRawF[6:0] == 7'h63 | 
-							(`C_SUPPORTED & CompressedOpcF[4:1] == 4'h7);
-	
-	//assign InstrClassF[1] = (PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) != 5'h01 & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump register, but not return
-	//						(PostSpillInstrRawF[6:0] == 7'h6F & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump, RD != x1 or x5
-	//						(`C_SUPPORTED & (cj | (cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01)) ));
-	assign InstrClassF[1] = PostSpillInstrRawF[6:0] == 7'h67 | PostSpillInstrRawF[6:0] == 7'h6F | (`C_SUPPORTED & (cjal | cj | cj | cjalr));
-	
-	assign InstrClassF[2] = PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01 | // return must return to ra or r5
+	assign InstrClassF[0] = BranchF | (`C_SUPPORTED & CBranchF);
+	assign InstrClassF[1] = JumpF | (`C_SUPPORTED & (cjal | cj | cj | cjalr));
+	assign InstrClassF[2] = (JumpF & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01) | // return must return to ra or r5
 							(`C_SUPPORTED & (cjalr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01));
 	
-	assign InstrClassF[3] = ((PostSpillInstrRawF[6:0] & 7'h77) == 7'h67 & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5
-							(`C_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01)));
+	//assign InstrClassF[3] = (JumpF & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5
+	//						(`C_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01)));
+	
+
 	assign PredInstrClassF = InstrClassF;
 	assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | 
 						PredInstrClassF[1];
@@ -206,7 +209,7 @@ module bpred (
     {DirPredictionWrongM, BTBPredPCWrongM, RASPredPCWrongM, PredictionInstrClassWrongM});
 
   // pipeline the class
-  flopenrc #(4) PredInstrClassRegD(clk, reset, FlushD, ~StallD, PredInstrClassF, PredInstrClassD);
+  flopenrc #(3) PredInstrClassRegD(clk, reset, FlushD, ~StallD, PredInstrClassF, PredInstrClassD);
   flopenrc #(1) WrongInstrClassRegE(clk, reset, FlushE, ~StallE, AnyWrongPredInstrClassD, AnyWrongPredInstrClassE);
 
   // Check the prediction
@@ -218,7 +221,7 @@ module bpred (
   assign PredictionPCWrongE = PCCorrectE != PCD;
 
   // branch class prediction wrong.
-  assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD;
+  assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD[2:0];
   assign AnyWrongPredInstrClassD = |WrongPredInstrClassD;
   
   // branch is wrong only if the PC does not match and both the Decode and Fetch stages have valid instructions.
diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv
index c538636df..2100eb352 100644
--- a/src/ifu/bpred/btb.sv
+++ b/src/ifu/bpred/btb.sv
@@ -36,7 +36,7 @@ module btb #(parameter int Depth = 10 ) (
   input  logic             StallF, StallD, StallM, FlushD, FlushM,
   input  logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE,                 // PC at various stages
   output logic [`XLEN-1:0] PredPCF,                                // BTB's guess at PC
-  output logic [3:0]       BTBPredInstrClassF,                        // BTB's guess at instruction class
+  output logic [2:0]       BTBPredInstrClassF,                        // BTB's guess at instruction class
   output logic             PredValidF,                             // BTB's guess is valid
   // update
   input  logic             AnyWrongPredInstrClassE,             // BTB's instruction class guess was wrong
@@ -50,10 +50,9 @@ module btb #(parameter int Depth = 10 ) (
   logic [Depth-1:0]         PCNextFIndex, PCFIndex, PCDIndex, PCEIndex;
   logic [`XLEN-1:0] 		ResetPC;
   logic 					MatchF, MatchD, MatchE, MatchNextX, MatchXF;
-  logic [`XLEN+4:0] 		ForwardBTBPrediction, ForwardBTBPredictionF;
-  logic [`XLEN+3:0] 		TableBTBPredictionF;
+  logic [`XLEN+3:0] 		ForwardBTBPrediction, ForwardBTBPredictionF;
+  logic [`XLEN+2:0] 		TableBTBPredictionF;
   logic [`XLEN-1:0] 		PredPCD;  
-  logic [3:0] 				PredInstrClassD;  // *** copy of reg outside module
   logic 					UpdateEn;
   logic 					TablePredValidF, PredValidD;
     
@@ -80,10 +79,10 @@ module btb #(parameter int Depth = 10 ) (
   flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
 
   assign ForwardBTBPrediction = MatchF ? {PredValidF, BTBPredInstrClassF, PredPCF} :
-                                MatchD ? {PredValidD, InstrClassD, PredPCD} :
-                                {1'b1, InstrClassE, IEUAdrE} ;
+                                MatchD ? {PredValidD, InstrClassD[2:0], PredPCD} :
+                                {1'b1, InstrClassE[2:0], IEUAdrE} ;
 
-  flopenr #(`XLEN+5) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF);
+  flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF);
 
   assign {PredValidF, BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : {TablePredValidF, TableBTBPredictionF};
 
@@ -96,14 +95,12 @@ module btb #(parameter int Depth = 10 ) (
 	if(~StallF | reset) TablePredValidF = ValidBits[PCNextFIndex];
   end
 
-  //assign PredValidF = MatchXF ? 1'b1 : TablePredValidF;
-  
   assign UpdateEn = |InstrClassE | AnyWrongPredInstrClassE;
 
   // An optimization may be using a PC relative address.
-  ram2p1r1wbe #(2**Depth, `XLEN+4) memory(
+  ram2p1r1wbe #(2**Depth, `XLEN+3) memory(
     .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF),
-     .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1));
+     .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE[2:0], IEUAdrE}), .we2(UpdateEn), .bwe2('1));
 
   flopenrc #(`XLEN+1) BTBD(clk, reset, FlushD, ~StallD, {PredValidF, PredPCF}, {PredValidD, PredPCD});
 
diff --git a/src/ifu/bpred/speculativeglobalhistory.sv b/src/ifu/bpred/speculativeglobalhistory.sv
index 51dbb422b..645ac99e6 100644
--- a/src/ifu/bpred/speculativeglobalhistory.sv
+++ b/src/ifu/bpred/speculativeglobalhistory.sv
@@ -36,8 +36,8 @@ module speculativeglobalhistory #(parameter int k = 10 ) (
   output logic [1:0] 	  DirPredictionF, 
   output logic 			  DirPredictionWrongE,
   // update
-  input logic [3:0] 	  PredInstrClassF, InstrClassD, InstrClassE,
-  input logic [3:0] 	  WrongPredInstrClassD, 
+  input logic [3:0] 	  InstrClassD, InstrClassE,
+  input logic [2:0] 	  PredInstrClassF, WrongPredInstrClassD, 
   input logic 			  PCSrcE
 );
 
diff --git a/src/ifu/bpred/speculativegshare.sv b/src/ifu/bpred/speculativegshare.sv
index 1eb888a90..9d55dc874 100644
--- a/src/ifu/bpred/speculativegshare.sv
+++ b/src/ifu/bpred/speculativegshare.sv
@@ -37,8 +37,9 @@ module speculativegshare #(parameter int k = 10 ) (
   output logic 			  DirPredictionWrongE,
   // update
   input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE,
-  input logic [3:0] 	  PredInstrClassF, InstrClassD, InstrClassE,
-  input logic [3:0] 	  WrongPredInstrClassD, 
+  input logic [2:0] 	  PredInstrClassF,
+  input logic [3:0]       InstrClassD, InstrClassE,
+  input logic [2:0] 	  WrongPredInstrClassD, 
   input logic 			  PCSrcE
 );
 

From 716fbca2b1009e7a6f66977da9564adb94240dd4 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 13 Feb 2023 11:57:25 -0600
Subject: [PATCH 55/71] Partial fix for gshare bugs from the last two weeks.

---
 src/ifu/bpred/bpred.sv             |  2 +-
 src/ifu/bpred/speculativegshare.sv | 15 +++++++++------
 2 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index 8a1eb801b..0976275bc 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -118,7 +118,7 @@ module bpred (
   end else if (`BPRED_TYPE == "BPSPECULATIVEGSHARE") begin:Predictor
     speculativegshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCF, .PCD, .PCE, .DirPredictionF, .DirPredictionWrongE,
-      .PredInstrClassF, .InstrClassD, .InstrClassE, .WrongPredInstrClassD, .PCSrcE);
+      .PredInstrClassF, .InstrClassD, .InstrClassE, .InstrClassM, .WrongPredInstrClassD, .PCSrcE);
 
   end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor
     // *** Fix me
diff --git a/src/ifu/bpred/speculativegshare.sv b/src/ifu/bpred/speculativegshare.sv
index 9d55dc874..bfbd1bbd1 100644
--- a/src/ifu/bpred/speculativegshare.sv
+++ b/src/ifu/bpred/speculativegshare.sv
@@ -38,7 +38,7 @@ module speculativegshare #(parameter int k = 10 ) (
   // update
   input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE,
   input logic [2:0] 	  PredInstrClassF,
-  input logic [3:0]       InstrClassD, InstrClassE,
+  input logic [3:0]       InstrClassD, InstrClassE, InstrClassM,
   input logic [2:0] 	  WrongPredInstrClassD, 
   input logic 			  PCSrcE
 );
@@ -49,9 +49,9 @@ module speculativegshare #(parameter int k = 10 ) (
   logic [1:0]              TableDirPredictionF, DirPredictionD, DirPredictionE;
   logic [1:0]              NewDirPredictionE;
 
-  logic [k-1:0] 		   GHRF, GHRD, GHRE;
+  logic [k-1:0] 		   GHRF, GHRD, GHRE, GHRM;
   logic 				   GHRLastF;
-  logic [k-1:0] 		   GHRNextF, GHRNextD, GHRNextE;
+  logic [k-1:0] 		   GHRNextF, GHRNextD, GHRNextE, GHRNextM;
   logic [k-1:0]            IndexNextF, IndexF, IndexD, IndexE;
   logic [1:0]              ForwardNewDirPrediction, ForwardDirPredictionF;
 
@@ -113,15 +113,18 @@ module speculativegshare #(parameter int k = 10 ) (
   // If it is wrong and branch does exist then shift right and insert the prediction.
   // If the branch does not exist then shift left and use GHRLastF to restore the LSB.
   logic [k-1:0] 		   GHRClassWrong;
-  mux2 #(k) GHRClassWrongMux({DirPredictionD[1], GHRF[k-1:1]}, {GHRF[k-2:0], GHRLastF}, InstrClassD[0], GHRClassWrong);
+  mux2 #(k) GHRClassWrongMux({DirPredictionD[1], GHRF[k-1:1]}, {GHRF[k-2:0], GHRLastF}, ~InstrClassD[0], GHRClassWrong);
   // As with GHRF FlushD and wrong direction prediction flushes the pipeline and restores to GHRNextE.
   mux3 #(k) GHRDMux(GHRF, GHRClassWrong, GHRNextE, {FlushDOrDirWrong, WrongPredInstrClassD[0]}, GHRNextD);
 
   flopenr  #(k) GHRDReg(clk, reset, ~StallD | FlushDOrDirWrong, GHRNextD, GHRD);
 
-  mux3 #(k) GHREMux(GHRD, GHRE, {PCSrcE, GHRD[k-2:0]}, {InstrClassE[0] & ~FlushM, FlushE}, GHRNextE);
+  mux3 #(k) GHREMux(GHRD, GHRNextM, {PCSrcE, GHRD[k-2:0]}, {InstrClassE[0] & ~FlushM, FlushE}, GHRNextE);
 
-  flopenr  #(k) GHREReg(clk, reset, ((InstrClassE[0] & ~FlushM) & ~StallE) | FlushE, GHRNextE, GHRE);
+  flopenr  #(k) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, GHRE);
+
+  assign GHRNextM = FlushM ? GHRM : GHRE;
+  flopenr  #(k) GHRMReg(clk, reset, (InstrClassM[0] & ~StallM) | FlushM, GHRNextM, GHRM);
   
   assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & InstrClassE[0];
 

From 0165fd54b4a5b764073017201ecf109c57f27c23 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 13 Feb 2023 16:14:17 -0600
Subject: [PATCH 56/71] Hacked commit.  Fixes the gshare bugs introduced last
 week. Need to recover the good changes in the next commit.

---
 src/ifu/bpred/RASPredictor.sv      |   7 +-
 src/ifu/bpred/bpred.sv             | 363 ++++++++++++++++++++++++++++-
 src/ifu/bpred/btb.sv               |  16 +-
 src/ifu/bpred/speculativegshare.sv |   4 +-
 4 files changed, 368 insertions(+), 22 deletions(-)

diff --git a/src/ifu/bpred/RASPredictor.sv b/src/ifu/bpred/RASPredictor.sv
index 40fb5bb15..330607af4 100644
--- a/src/ifu/bpred/RASPredictor.sv
+++ b/src/ifu/bpred/RASPredictor.sv
@@ -33,10 +33,10 @@ module RASPredictor #(parameter int StackSize = 16 )(
   input  logic             clk,
   input  logic 			   reset, 
   input  logic 			   StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM,
-  input  logic [2:0] 	   WrongPredInstrClassD,                      // Prediction class is wrong
+  input  logic [3:0] 	   WrongPredInstrClassD,                      // Prediction class is wrong
   input  logic [3:0] 	   InstrClassD,
   input  logic [3:0]       InstrClassE,                  // Instr class
-  input  logic [2:0]       PredInstrClassF,
+  input  logic [3:0]       PredInstrClassF,
   input  logic [`XLEN-1:0] PCLinkE,                                   // PC of instruction after a jal
   output logic [`XLEN-1:0] RASPCF                                     // Top of the stack
    );
@@ -95,6 +95,3 @@ module RASPredictor #(parameter int StackSize = 16 )(
   
   
 endmodule
-
-
-
diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index 0976275bc..b833f99ea 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -72,11 +72,11 @@ module bpred (
   logic                     PredValidF;
   logic [1:0]               DirPredictionF;
 
-  logic [2:0]               BTBPredInstrClassF, PredInstrClassF, PredInstrClassD;
+  logic [3:0]               BTBPredInstrClassF, PredInstrClassF, PredInstrClassD, PredInstrClassE;
   logic [`XLEN-1:0]         PredPCF, RASPCF;
   logic                     PredictionPCWrongE;
   logic                     AnyWrongPredInstrClassD, AnyWrongPredInstrClassE;
-  logic [2:0] 				InstrClassF;
+  logic [3:0] 				InstrClassF;
   logic [3:0]               InstrClassD;
   logic [3:0] 				InstrClassE;
   logic                     DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE;
@@ -85,7 +85,7 @@ module bpred (
   logic [`XLEN-1:0]         BPPredPCF;
   logic [`XLEN-1:0]         PCNext0F;
   logic [`XLEN-1:0] 		PCCorrectE;
-  logic [2:0] 				WrongPredInstrClassD;
+  logic [3:0] 				WrongPredInstrClassD;
 
   logic 					BTBTargetWrongE;
   logic 					RASTargetWrongE;
@@ -149,6 +149,8 @@ module bpred (
           .InstrClassE);
 
   // the branch predictor needs a compact decoding of the instruction class.
+  ///// ********* THIS IS NOT THE ISSUE.
+/* -----\/----- EXCLUDED -----\/-----
   if (`INSTR_CLASS_PRED == 0) begin : DirectClassDecode
 	logic [4:0] CompressedOpcF;
 	logic [2:0] InstrClassF;
@@ -184,6 +186,44 @@ module bpred (
 	assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | 
 						PredInstrClassF[1] & PredValidF;
   end
+ -----/\----- EXCLUDED -----/\----- */
+  // the branch predictor needs a compact decoding of the instruction class.
+  if (`INSTR_CLASS_PRED == 0) begin : DirectClassDecode
+	logic [4:0] CompressedOpcF;
+	logic [3:0] InstrClassF;
+	logic 		cjal, cj, cjr, cjalr;
+	
+	assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]};
+
+	assign cjal = CompressedOpcF == 5'h09 & `XLEN == 32;
+	assign cj = CompressedOpcF == 5'h0d;
+	assign cjr = CompressedOpcF == 5'h14 & ~PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0;
+	assign cjalr = CompressedOpcF == 5'h14 & PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0;
+	
+	assign InstrClassF[0] = PostSpillInstrRawF[6:0] == 7'h63 | 
+							(`C_SUPPORTED & CompressedOpcF[4:1] == 4'h7);
+	
+	assign InstrClassF[1] = (PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) != 5'h01 & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump register, but not return
+							(PostSpillInstrRawF[6:0] == 7'h6F & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump, RD != x1 or x5
+							(`C_SUPPORTED & (cj | (cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01)) ));
+	
+	assign InstrClassF[2] = PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01 | // return must return to ra or r5
+							(`C_SUPPORTED & (cjalr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01));
+	
+	assign InstrClassF[3] = ((PostSpillInstrRawF[6:0] & 7'h77) == 7'h67 & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5
+							(`C_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01)));
+	assign PredInstrClassF = InstrClassF;
+	assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | 
+						PredInstrClassF[2] |
+						PredInstrClassF[1] |
+						PredInstrClassF[3];
+  end else begin
+	assign PredInstrClassF = BTBPredInstrClassF;
+	assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | 
+						PredInstrClassF[2] |
+						(PredInstrClassF[1] & PredValidF) |
+						(PredInstrClassF[3] & PredValidF);
+  end
   
   // Part 3 RAS
   RASPredictor RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
@@ -192,10 +232,17 @@ module bpred (
 
   assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF;
 
+/* -----\/----- EXCLUDED -----\/-----
   assign InstrClassD[0] = BranchD;
   assign InstrClassD[1] = JumpD ;
   assign InstrClassD[2] = JumpD & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or x5
   assign InstrClassD[3] = JumpD & (InstrD[11:7] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5
+ -----/\----- EXCLUDED -----/\----- */
+  assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5
+  assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5
+  assign InstrClassD[1] = (InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01) | // jump register, but not return
+						  (InstrD[6:0] == 7'h6F & (InstrD[11:7] & 5'h1B) != 5'h01); // jump, RD != x1 or x5
+  assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch
   
   
 
@@ -209,8 +256,10 @@ module bpred (
     {DirPredictionWrongM, BTBPredPCWrongM, RASPredPCWrongM, PredictionInstrClassWrongM});
 
   // pipeline the class
-  flopenrc #(3) PredInstrClassRegD(clk, reset, FlushD, ~StallD, PredInstrClassF, PredInstrClassD);
-  flopenrc #(1) WrongInstrClassRegE(clk, reset, FlushE, ~StallE, AnyWrongPredInstrClassD, AnyWrongPredInstrClassE);
+  flopenrc #(4) PredInstrClassRegD(clk, reset, FlushD, ~StallD, PredInstrClassF, PredInstrClassD);
+  //flopenrc #(1) WrongInstrClassRegE(clk, reset, FlushE, ~StallE, AnyWrongPredInstrClassD, AnyWrongPredInstrClassE);
+  flopenrc #(4) PredInstrClassRegE(clk, reset, FlushE, ~StallE, PredInstrClassD, PredInstrClassE);
+  assign AnyWrongPredInstrClassE = InstrClassE != PredInstrClassE;
 
   // Check the prediction
   // if it is a CFI then check if the next instruction address (PCD) matches the branch's target or fallthrough address.
@@ -221,11 +270,12 @@ module bpred (
   assign PredictionPCWrongE = PCCorrectE != PCD;
 
   // branch class prediction wrong.
-  assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD[2:0];
+  assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD[3:0];
   assign AnyWrongPredInstrClassD = |WrongPredInstrClassD;
   
   // branch is wrong only if the PC does not match and both the Decode and Fetch stages have valid instructions.
-  assign BPPredWrongE = PredictionPCWrongE & InstrValidE & InstrValidD;
+  assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE) | (AnyWrongPredInstrClassE & ~|InstrClassE);
+  //assign BPPredWrongE = PredictionPCWrongE & InstrValidE & InstrValidD;
 
   // Output the predicted PC or corrected PC on miss-predict.
   // Selects the BP or PC+2/4.
@@ -265,3 +315,302 @@ module bpred (
   flopenrc #(`XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE);
   
 endmodule
+/* -----\/----- EXCLUDED -----\/-----
+///////////////////////////////////////////
+// bpred.sv
+//
+// Written: Ross Thomposn ross1728@gmail.com
+// Created: 12 February 2021
+// Modified: 19 January 2023
+//
+// Purpose: Branch direction prediction and jump/branch target prediction.
+//          Prediction made during the fetch stage and corrected in the execution stage.
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+`define INSTR_CLASS_PRED 1
+
+module bpred (
+  input  logic             clk, reset,
+  input  logic             StallF, StallD, StallE, StallM, StallW,
+  input  logic             FlushD, FlushE, FlushM, FlushW,
+  // Fetch stage
+  // the prediction
+  input logic              InstrValidD, InstrValidE,
+  input  logic             BranchD, BranchE,
+  input  logic             JumpD, JumpE,
+  input  logic [31:0]      InstrD,                    // Decompressed decode stage instruction. Used to decode instruction class
+  input  logic [`XLEN-1:0] PCNextF,                   // Next Fetch Address
+  input  logic [`XLEN-1:0] PCPlus2or4F,               // PCF+2/4
+  output logic [`XLEN-1:0] PCNext1F,                  // Branch Predictor predicted or corrected fetch address on miss prediction
+  output logic [`XLEN-1:0] NextValidPCE,              // Address of next valid instruction after the instruction in the Memory stage
+
+  // Update Predictor
+  input  logic [`XLEN-1:0] PCF,                       // Fetch stage instruction address
+  input  logic [`XLEN-1:0] PCD,                       // Decode stage instruction address. Also the address the branch predictor took
+  input  logic [`XLEN-1:0] PCE,                       // Execution stage instruction address
+  input  logic [`XLEN-1:0] PCM,                       // Memory stage instruction address
+
+  input logic [31:0]       PostSpillInstrRawF,        // Instruction
+
+  // Branch and jump outcome
+  input logic              PCSrcE,                    // Executation stage branch is taken
+  input logic [`XLEN-1:0]  IEUAdrE,                   // The branch/jump target address
+  input logic [`XLEN-1:0]  PCLinkE,                   // The address following the branch instruction. (AKA Fall through address)
+  output logic [3:0]       InstrClassM,               // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
+  output logic             JumpOrTakenBranchM,        // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
+
+  // Report branch prediction status
+  output logic             BPPredWrongE,              // Prediction is wrong
+  output logic             BPPredWrongM,              // Prediction is wrong
+  output logic             DirPredictionWrongM,       // Prediction direction is wrong
+  output logic             BTBPredPCWrongM,           // Prediction target wrong
+  output logic             RASPredPCWrongM,           // RAS prediction is wrong
+  output logic             PredictionInstrClassWrongM // Class prediction is wrong
+  );
+
+  logic                     PredValidF;
+  logic [1:0]               DirPredictionF;
+
+  logic [3:0]               BTBPredInstrClassF, PredInstrClassF, PredInstrClassD, PredInstrClassE;
+  logic [`XLEN-1:0]         PredPCF, RASPCF;
+  logic                     TargetWrongE;
+  logic                     FallThroughWrongE;
+  logic                     PredictionPCWrongE;
+  logic                     PredictionInstrClassWrongE;
+  logic [3:0]               InstrClassF, InstrClassD, InstrClassE, InstrClassW;
+  logic                     DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
+  
+  logic                     SelBPPredF;
+  logic [`XLEN-1:0]         BPPredPCF;
+  logic [`XLEN-1:0]         PCNext0F;
+  logic [`XLEN-1:0] 		PCCorrectE;
+  logic [3:0] 				WrongPredInstrClassD;
+
+
+  logic BTBTargetWrongE;
+  logic RASTargetWrongE;
+  logic JumpOrTakenBranchE;
+
+  logic [`XLEN-1:0] PredPCD, PredPCE, RASPCD, RASPCE;
+
+  // Part 1 branch direction prediction
+  // look into the 2 port Sram model. something is wrong. 
+  if (`BPRED_TYPE == "BPTWOBIT") begin:Predictor
+    twoBitPredictor #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
+      .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
+      .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
+
+  end else if (`BPRED_TYPE == "BPGLOBAL") begin:Predictor
+    globalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
+      .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
+      .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
+
+/-* -----\/----- EXCLUDED -----\/-----
+  end else if (`BPRED_TYPE == "BPSPECULATIVEGLOBAL") begin:Predictor
+    speculativeglobalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+      .DirPredictionF, .DirPredictionWrongE,
+      .BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]),
+      .BranchInstrW(InstrClassW[0]), .WrongPredInstrClassD, .PCSrcE);
+	    
+  end else if (`BPRED_TYPE == "BPGSHARE") begin:Predictor
+    gshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
+      .PCNextF, .PCE, .DirPredictionF, .DirPredictionWrongE,
+      .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
+ -----/\----- EXCLUDED -----/\----- *-/
+
+  end else if (`BPRED_TYPE == "BPSPECULATIVEGSHARE") begin:Predictor
+    speculativegshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+      .PCNextF, .PCF, .PCD, .PCE, .DirPredictionF, .DirPredictionWrongE,
+      .PredInstrClassF, .InstrClassD, .InstrClassE, .InstrClassM, .WrongPredInstrClassD, .PCSrcE);
+
+  end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor
+    // *** Fix me
+/-* -----\/----- EXCLUDED -----\/-----
+    localHistoryPredictor DirPredictor(.clk,
+      .reset, .StallF, .StallE,
+      .LookUpPC(PCNextF),
+      .Prediction(DirPredictionF),
+      // update
+      .UpdatePC(PCE),
+      .UpdateEN(InstrClassE[0] & ~StallE),
+      .PCSrcE,
+      .UpdatePrediction(InstrClassE[0]));
+ -----/\----- EXCLUDED -----/\----- *-/
+  end 
+
+  // this predictor will have two pieces of data,
+  // 1) A direction (1 = Taken, 0 = Not Taken)
+  // 2) Any information which is necessary for the predictor to build its next state.
+  // For a 2 bit table this is the prediction count.
+
+  // Part 2 Branch target address prediction
+  // *** For now the BTB will house the direct and indirect targets
+
+  btb TargetPredictor(.clk, .reset, .StallF, .StallD, .StallM, .FlushD, .FlushM,
+          .PCNextF, .PCF, .PCD, .PCE,
+          .PredPCF,
+          .BTBPredInstrClassF,
+          .PredValidF,
+          .AnyWrongPredInstrClassE(PredictionInstrClassWrongE),
+          .IEUAdrE,
+          .InstrClassD,
+          .InstrClassE);
+
+  // the branch predictor needs a compact decoding of the instruction class.
+  if (`INSTR_CLASS_PRED == 0) begin : DirectClassDecode
+	logic [4:0] CompressedOpcF;
+	logic [3:0] InstrClassF;
+	logic 		cjal, cj, cjr, cjalr;
+	
+	assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]};
+
+	assign cjal = CompressedOpcF == 5'h09 & `XLEN == 32;
+	assign cj = CompressedOpcF == 5'h0d;
+	assign cjr = CompressedOpcF == 5'h14 & ~PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0;
+	assign cjalr = CompressedOpcF == 5'h14 & PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0;
+	
+	assign InstrClassF[0] = PostSpillInstrRawF[6:0] == 7'h63 | 
+							(`C_SUPPORTED & CompressedOpcF[4:1] == 4'h7);
+	
+	assign InstrClassF[1] = (PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) != 5'h01 & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump register, but not return
+							(PostSpillInstrRawF[6:0] == 7'h6F & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump, RD != x1 or x5
+							(`C_SUPPORTED & (cj | (cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01)) ));
+	
+	assign InstrClassF[2] = PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01 | // return must return to ra or r5
+							(`C_SUPPORTED & (cjalr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01));
+	
+	assign InstrClassF[3] = ((PostSpillInstrRawF[6:0] & 7'h77) == 7'h67 & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5
+							(`C_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01)));
+	assign PredInstrClassF = InstrClassF;
+	assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | 
+						PredInstrClassF[2] |
+						PredInstrClassF[1] |
+						PredInstrClassF[3];
+  end else begin
+	assign PredInstrClassF = BTBPredInstrClassF;
+	assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | 
+						PredInstrClassF[2] |
+						(PredInstrClassF[1] & PredValidF) |
+						(PredInstrClassF[3] & PredValidF);
+  end
+  
+  // Part 3 RAS
+  RASPredictor RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
+							.PredInstrClassF, .InstrClassD, .InstrClassE,
+							.WrongPredInstrClassD, .RASPCF, .PCLinkE);
+
+  assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF;
+
+  assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5
+  assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5
+  assign InstrClassD[1] = (InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01) | // jump register, but not return
+						  (InstrD[6:0] == 7'h6F & (InstrD[11:7] & 5'h1B) != 5'h01); // jump, RD != x1 or x5
+  assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch
+
+  flopenrc #(4) InstrClassRegE(clk, reset,  FlushE, ~StallE, InstrClassD, InstrClassE);
+  flopenrc #(4) InstrClassRegM(clk, reset,  FlushM, ~StallM, InstrClassE, InstrClassM);
+  flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPPredWrongE, BPPredWrongM);
+  flopenrc #(1) JumpOrTakenBranchMReg(clk, reset, FlushM, ~StallM, JumpOrTakenBranchE, JumpOrTakenBranchM);
+
+  // branch predictor
+  flopenrc #(4) BPPredWrongRegM(clk, reset, FlushM, ~StallM, 
+    {DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, PredictionInstrClassWrongE},
+    {DirPredictionWrongM, BTBPredPCWrongM, RASPredPCWrongM, PredictionInstrClassWrongM});
+
+  // pipeline the class
+  flopenrc #(4) PredInstrClassRegD(clk, reset, FlushD, ~StallD, PredInstrClassF, PredInstrClassD);
+  flopenrc #(4) PredInstrClassRegE(clk, reset, FlushE, ~StallE, PredInstrClassD, PredInstrClassE);
+
+  // Check the prediction
+  // first check if the target or fallthrough address matches what was predicted.
+  assign TargetWrongE = IEUAdrE != PCD;
+  assign FallThroughWrongE = PCLinkE != PCD;
+  // If the target is taken check the target rather than fallthrough.  The instruction needs to be a branch if PCSrcE is selected
+  // Remember the bpred can incorrectly predict a non cfi instruction as a branch taken.  If the real instruction is non cfi
+  // it must have selected the fall through.
+  assign PredictionPCWrongE = PCCorrectE != PCD;
+
+//  assign PredictionPCWrongE = (PCSrcE  & (|InstrClassE) ? TargetWrongE : FallThroughWrongE);
+
+  // The branch direction also need to checked.
+  // However if the direction is wrong then the pc will be wrong.  This is only relavent to checking the
+  // accuracy of the direciton prediction.
+  //assign DirPredictionWrongE = (BPPredE[1] ^ PCSrcE) & InstrClassE[0];
+  
+  // Finally we need to check if the class is wrong.  When the class is wrong the BTB needs to be updated.
+  // Also we want to track this in a performance counter.
+  assign PredictionInstrClassWrongE = InstrClassE != PredInstrClassE;
+
+  // We want to output to the instruction fetch if the PC fetched was wrong.  If by chance the predictor was wrong about
+  // the direction or class, but correct about the target we don't have the flush the pipeline.  However we still
+  // need this information to verify the accuracy of the predictors.
+  assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE) | BPPredClassNonCFIWrongE;
+//  assign BPPredWrongE = PredictionPCWrongE & InstrValidE & InstrValidD;
+
+  // If we have a jump, jump register or jal or jalr and the PC is wrong we need to increment the performance counter.
+  //assign BTBPredPCWrongE = (InstrClassE[3] | InstrClassE[1] | InstrClassE[0]) & PredictionPCWrongE;
+  //assign BTBPredPCWrongE = TargetWrongE & (InstrClassE[3] | InstrClassE[1] | InstrClassE[0]) & PCSrcE;
+  assign BTBPredPCWrongE = BTBTargetWrongE;
+  
+  // similar with RAS. Over counts ras if the class prediction was wrong.
+  //assign RASPredPCWrongE = TargetWrongE & InstrClassE[2] & PCSrcE;
+  assign RASPredPCWrongE = RASTargetWrongE;
+  // Finally if the real instruction class is non CFI but the predictor said it was we need to count.
+  assign BPPredClassNonCFIWrongE = PredictionInstrClassWrongE & ~|InstrClassE;
+
+  // branch class prediction wrong.
+  assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD;
+  
+  // Selects the BP or PC+2/4.
+  mux2 #(`XLEN) pcmux0(PCPlus2or4F, BPPredPCF, SelBPPredF, PCNext0F);
+  // If the prediction is wrong select the correct address.
+  mux2 #(`XLEN) pcmux1(PCNext0F, PCCorrectE, BPPredWrongE, PCNext1F);  
+  // Correct branch/jump target.
+  mux2 #(`XLEN) pccorrectemux(PCLinkE, IEUAdrE, PCSrcE, PCCorrectE);
+  
+  // If the fence/csrw was predicted as a taken branch then we select PCF, rather PCE.
+  // Effectively this is PCM+4 or the non-existant PCLinkM
+  //  if(`BPCLASS) begin
+  mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPPredWrongM, NextValidPCE);
+  //  end else begin
+  //	assign NextValidPCE = PCE;
+  //  end
+
+  // performance counters
+  // 1. class         (class wrong / minstret) (PredictionInstrClassWrongM / csr)                    // Correct now
+  // 2. target btb    (btb target wrong / class[0,1,3])  (btb target wrong / (br + j + jal)
+  // 3. target ras    (ras target wrong / class[2])
+  // 4. direction     (br dir wrong / class[0])
+
+  assign BTBTargetWrongE = (PredPCE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] | InstrClassE[3]) & PCSrcE;
+  assign RASTargetWrongE = (RASPCE != IEUAdrE) & InstrClassE[2] & PCSrcE;
+
+  assign JumpOrTakenBranchE = (InstrClassE[0] & PCSrcE) | InstrClassE[1] | InstrClassE[3];
+  
+  flopenrc #(`XLEN) BTBTargetDReg(clk, reset, FlushD, ~StallD, PredPCF, PredPCD);
+  flopenrc #(`XLEN) BTBTargetEReg(clk, reset, FlushE, ~StallE, PredPCD, PredPCE);
+
+  flopenrc #(`XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD);
+  flopenrc #(`XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE);
+  
+endmodule
+ -----/\----- EXCLUDED -----/\----- */
diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv
index 2100eb352..7893ace5f 100644
--- a/src/ifu/bpred/btb.sv
+++ b/src/ifu/bpred/btb.sv
@@ -36,7 +36,7 @@ module btb #(parameter int Depth = 10 ) (
   input  logic             StallF, StallD, StallM, FlushD, FlushM,
   input  logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE,                 // PC at various stages
   output logic [`XLEN-1:0] PredPCF,                                // BTB's guess at PC
-  output logic [2:0]       BTBPredInstrClassF,                        // BTB's guess at instruction class
+  output logic [3:0]       BTBPredInstrClassF,                        // BTB's guess at instruction class
   output logic             PredValidF,                             // BTB's guess is valid
   // update
   input  logic             AnyWrongPredInstrClassE,             // BTB's instruction class guess was wrong
@@ -50,8 +50,8 @@ module btb #(parameter int Depth = 10 ) (
   logic [Depth-1:0]         PCNextFIndex, PCFIndex, PCDIndex, PCEIndex;
   logic [`XLEN-1:0] 		ResetPC;
   logic 					MatchF, MatchD, MatchE, MatchNextX, MatchXF;
-  logic [`XLEN+3:0] 		ForwardBTBPrediction, ForwardBTBPredictionF;
-  logic [`XLEN+2:0] 		TableBTBPredictionF;
+  logic [`XLEN+4:0] 		ForwardBTBPrediction, ForwardBTBPredictionF;
+  logic [`XLEN+3:0] 		TableBTBPredictionF;
   logic [`XLEN-1:0] 		PredPCD;  
   logic 					UpdateEn;
   logic 					TablePredValidF, PredValidD;
@@ -79,10 +79,10 @@ module btb #(parameter int Depth = 10 ) (
   flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
 
   assign ForwardBTBPrediction = MatchF ? {PredValidF, BTBPredInstrClassF, PredPCF} :
-                                MatchD ? {PredValidD, InstrClassD[2:0], PredPCD} :
-                                {1'b1, InstrClassE[2:0], IEUAdrE} ;
+                                MatchD ? {PredValidD, InstrClassD, PredPCD} :
+                                {1'b1, InstrClassE, IEUAdrE} ;
 
-  flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF);
+  flopenr #(`XLEN+5) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF);
 
   assign {PredValidF, BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : {TablePredValidF, TableBTBPredictionF};
 
@@ -98,9 +98,9 @@ module btb #(parameter int Depth = 10 ) (
   assign UpdateEn = |InstrClassE | AnyWrongPredInstrClassE;
 
   // An optimization may be using a PC relative address.
-  ram2p1r1wbe #(2**Depth, `XLEN+3) memory(
+  ram2p1r1wbe #(2**Depth, `XLEN+4) memory(
     .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF),
-     .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE[2:0], IEUAdrE}), .we2(UpdateEn), .bwe2('1));
+     .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1));
 
   flopenrc #(`XLEN+1) BTBD(clk, reset, FlushD, ~StallD, {PredValidF, PredPCF}, {PredValidD, PredPCD});
 
diff --git a/src/ifu/bpred/speculativegshare.sv b/src/ifu/bpred/speculativegshare.sv
index bfbd1bbd1..1dd7d4cdb 100644
--- a/src/ifu/bpred/speculativegshare.sv
+++ b/src/ifu/bpred/speculativegshare.sv
@@ -37,9 +37,9 @@ module speculativegshare #(parameter int k = 10 ) (
   output logic 			  DirPredictionWrongE,
   // update
   input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE,
-  input logic [2:0] 	  PredInstrClassF,
+  input logic [3:0] 	  PredInstrClassF,
   input logic [3:0]       InstrClassD, InstrClassE, InstrClassM,
-  input logic [2:0] 	  WrongPredInstrClassD, 
+  input logic [3:0] 	  WrongPredInstrClassD, 
   input logic 			  PCSrcE
 );
 

From 1cfdd201a5fd358afd389bbbd85cb6f72f6f7d57 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 13 Feb 2023 17:10:24 -0600
Subject: [PATCH 57/71] Partial improvement.

---
 src/ifu/bpred/bpred.sv | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index b833f99ea..a6cb0ccb2 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -220,9 +220,7 @@ module bpred (
   end else begin
 	assign PredInstrClassF = BTBPredInstrClassF;
 	assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | 
-						PredInstrClassF[2] |
-						(PredInstrClassF[1] & PredValidF) |
-						(PredInstrClassF[3] & PredValidF);
+						PredInstrClassF[1] & PredValidF;
   end
   
   // Part 3 RAS
@@ -232,17 +230,18 @@ module bpred (
 
   assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF;
 
-/* -----\/----- EXCLUDED -----\/-----
   assign InstrClassD[0] = BranchD;
   assign InstrClassD[1] = JumpD ;
   assign InstrClassD[2] = JumpD & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or x5
   assign InstrClassD[3] = JumpD & (InstrD[11:7] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5
- -----/\----- EXCLUDED -----/\----- */
+
+/* -----\/----- EXCLUDED -----\/-----
   assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5
   assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5
   assign InstrClassD[1] = (InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01) | // jump register, but not return
 						  (InstrD[6:0] == 7'h6F & (InstrD[11:7] & 5'h1B) != 5'h01); // jump, RD != x1 or x5
   assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch
+ -----/\----- EXCLUDED -----/\----- */
   
   
 
@@ -274,7 +273,7 @@ module bpred (
   assign AnyWrongPredInstrClassD = |WrongPredInstrClassD;
   
   // branch is wrong only if the PC does not match and both the Decode and Fetch stages have valid instructions.
-  assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE) | (AnyWrongPredInstrClassE & ~|InstrClassE);
+  assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE | (AnyWrongPredInstrClassE & ~|InstrClassE));
   //assign BPPredWrongE = PredictionPCWrongE & InstrValidE & InstrValidD;
 
   // Output the predicted PC or corrected PC on miss-predict.

From 10b45ed6c7c217d4cf551eedd0cf295195b49ffe Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 13 Feb 2023 17:23:56 -0600
Subject: [PATCH 58/71] Further branch predictor improvements.

---
 src/ifu/bpred/bpred.sv | 59 +++---------------------------------------
 1 file changed, 4 insertions(+), 55 deletions(-)

diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index a6cb0ccb2..c86c09790 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -149,11 +149,9 @@ module bpred (
           .InstrClassE);
 
   // the branch predictor needs a compact decoding of the instruction class.
-  ///// ********* THIS IS NOT THE ISSUE.
-/* -----\/----- EXCLUDED -----\/-----
   if (`INSTR_CLASS_PRED == 0) begin : DirectClassDecode
 	logic [4:0] CompressedOpcF;
-	logic [2:0] InstrClassF;
+	logic [3:0] InstrClassF;
 	logic 		cjal, cj, cjr, cjalr, CJumpF, CBranchF;
 	logic 		JumpF, BranchF;
 	
@@ -174,49 +172,12 @@ module bpred (
 	assign InstrClassF[2] = (JumpF & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01) | // return must return to ra or r5
 							(`C_SUPPORTED & (cjalr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01));
 	
-	//assign InstrClassF[3] = (JumpF & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5
-	//						(`C_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01)));
-	
-
-	assign PredInstrClassF = InstrClassF;
-	assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | 
-						PredInstrClassF[1];
-  end else begin
-	assign PredInstrClassF = BTBPredInstrClassF;
-	assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | 
-						PredInstrClassF[1] & PredValidF;
-  end
- -----/\----- EXCLUDED -----/\----- */
-  // the branch predictor needs a compact decoding of the instruction class.
-  if (`INSTR_CLASS_PRED == 0) begin : DirectClassDecode
-	logic [4:0] CompressedOpcF;
-	logic [3:0] InstrClassF;
-	logic 		cjal, cj, cjr, cjalr;
-	
-	assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]};
-
-	assign cjal = CompressedOpcF == 5'h09 & `XLEN == 32;
-	assign cj = CompressedOpcF == 5'h0d;
-	assign cjr = CompressedOpcF == 5'h14 & ~PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0;
-	assign cjalr = CompressedOpcF == 5'h14 & PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0;
-	
-	assign InstrClassF[0] = PostSpillInstrRawF[6:0] == 7'h63 | 
-							(`C_SUPPORTED & CompressedOpcF[4:1] == 4'h7);
-	
-	assign InstrClassF[1] = (PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) != 5'h01 & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump register, but not return
-							(PostSpillInstrRawF[6:0] == 7'h6F & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump, RD != x1 or x5
-							(`C_SUPPORTED & (cj | (cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01)) ));
-	
-	assign InstrClassF[2] = PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01 | // return must return to ra or r5
-							(`C_SUPPORTED & (cjalr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01));
-	
-	assign InstrClassF[3] = ((PostSpillInstrRawF[6:0] & 7'h77) == 7'h67 & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5
+	assign InstrClassF[3] = (JumpF & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5
 							(`C_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01)));
+
 	assign PredInstrClassF = InstrClassF;
 	assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | 
-						PredInstrClassF[2] |
 						PredInstrClassF[1] |
-						PredInstrClassF[3];
   end else begin
 	assign PredInstrClassF = BTBPredInstrClassF;
 	assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | 
@@ -235,16 +196,6 @@ module bpred (
   assign InstrClassD[2] = JumpD & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or x5
   assign InstrClassD[3] = JumpD & (InstrD[11:7] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5
 
-/* -----\/----- EXCLUDED -----\/-----
-  assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5
-  assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5
-  assign InstrClassD[1] = (InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01) | // jump register, but not return
-						  (InstrD[6:0] == 7'h6F & (InstrD[11:7] & 5'h1B) != 5'h01); // jump, RD != x1 or x5
-  assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch
- -----/\----- EXCLUDED -----/\----- */
-  
-  
-
   flopenrc #(4) InstrClassRegE(clk, reset,  FlushE, ~StallE, InstrClassD, InstrClassE);
   flopenrc #(4) InstrClassRegM(clk, reset,  FlushM, ~StallM, InstrClassE, InstrClassM);
   flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPPredWrongE, BPPredWrongM);
@@ -256,9 +207,8 @@ module bpred (
 
   // pipeline the class
   flopenrc #(4) PredInstrClassRegD(clk, reset, FlushD, ~StallD, PredInstrClassF, PredInstrClassD);
-  //flopenrc #(1) WrongInstrClassRegE(clk, reset, FlushE, ~StallE, AnyWrongPredInstrClassD, AnyWrongPredInstrClassE);
+  flopenrc #(1) WrongInstrClassRegE(clk, reset, FlushE, ~StallE, AnyWrongPredInstrClassD, AnyWrongPredInstrClassE);
   flopenrc #(4) PredInstrClassRegE(clk, reset, FlushE, ~StallE, PredInstrClassD, PredInstrClassE);
-  assign AnyWrongPredInstrClassE = InstrClassE != PredInstrClassE;
 
   // Check the prediction
   // if it is a CFI then check if the next instruction address (PCD) matches the branch's target or fallthrough address.
@@ -299,7 +249,6 @@ module bpred (
   // could be wrong or the fall through address selected for branch predict not taken.
   // By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of
   // both without the above inaccuracies.
-  //assign BTBPredPCWrongE = (PredPCE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] | InstrClassE[3]) & PCSrcE;
   assign BTBPredPCWrongE = (PredPCE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] & ~InstrClassE[2]) & PCSrcE;
   assign RASPredPCWrongE = (RASPCE != IEUAdrE) & InstrClassE[2] & PCSrcE;
 

From c18ac35332d361260562050f7dc8abe46cf21d96 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 13 Feb 2023 17:29:51 -0600
Subject: [PATCH 59/71] Created copy of gshare.  I think there may be a simpler
 implementation.

---
 src/ifu/bpred/bpred.sv       | 304 +----------------------------------
 src/ifu/bpred/gshare_copy.sv |  80 +++++++++
 testbench/tests.vh           |   2 +-
 3 files changed, 83 insertions(+), 303 deletions(-)
 create mode 100644 src/ifu/bpred/gshare_copy.sv

diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index c86c09790..69bec3e73 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -76,7 +76,6 @@ module bpred (
   logic [`XLEN-1:0]         PredPCF, RASPCF;
   logic                     PredictionPCWrongE;
   logic                     AnyWrongPredInstrClassD, AnyWrongPredInstrClassE;
-  logic [3:0] 				InstrClassF;
   logic [3:0]               InstrClassD;
   logic [3:0] 				InstrClassE;
   logic                     DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE;
@@ -177,7 +176,7 @@ module bpred (
 
 	assign PredInstrClassF = InstrClassF;
 	assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | 
-						PredInstrClassF[1] |
+						PredInstrClassF[1];
   end else begin
 	assign PredInstrClassF = BTBPredInstrClassF;
 	assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | 
@@ -224,7 +223,7 @@ module bpred (
   
   // branch is wrong only if the PC does not match and both the Decode and Fetch stages have valid instructions.
   assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE | (AnyWrongPredInstrClassE & ~|InstrClassE));
-  //assign BPPredWrongE = PredictionPCWrongE & InstrValidE & InstrValidD;
+  //assign BPPredWrongE = PredictionPCWrongE & InstrValidE & InstrValidD; // this does not work for cubic benchmark
 
   // Output the predicted PC or corrected PC on miss-predict.
   // Selects the BP or PC+2/4.
@@ -263,302 +262,3 @@ module bpred (
   flopenrc #(`XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE);
   
 endmodule
-/* -----\/----- EXCLUDED -----\/-----
-///////////////////////////////////////////
-// bpred.sv
-//
-// Written: Ross Thomposn ross1728@gmail.com
-// Created: 12 February 2021
-// Modified: 19 January 2023
-//
-// Purpose: Branch direction prediction and jump/branch target prediction.
-//          Prediction made during the fetch stage and corrected in the execution stage.
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-`include "wally-config.vh"
-
-`define INSTR_CLASS_PRED 1
-
-module bpred (
-  input  logic             clk, reset,
-  input  logic             StallF, StallD, StallE, StallM, StallW,
-  input  logic             FlushD, FlushE, FlushM, FlushW,
-  // Fetch stage
-  // the prediction
-  input logic              InstrValidD, InstrValidE,
-  input  logic             BranchD, BranchE,
-  input  logic             JumpD, JumpE,
-  input  logic [31:0]      InstrD,                    // Decompressed decode stage instruction. Used to decode instruction class
-  input  logic [`XLEN-1:0] PCNextF,                   // Next Fetch Address
-  input  logic [`XLEN-1:0] PCPlus2or4F,               // PCF+2/4
-  output logic [`XLEN-1:0] PCNext1F,                  // Branch Predictor predicted or corrected fetch address on miss prediction
-  output logic [`XLEN-1:0] NextValidPCE,              // Address of next valid instruction after the instruction in the Memory stage
-
-  // Update Predictor
-  input  logic [`XLEN-1:0] PCF,                       // Fetch stage instruction address
-  input  logic [`XLEN-1:0] PCD,                       // Decode stage instruction address. Also the address the branch predictor took
-  input  logic [`XLEN-1:0] PCE,                       // Execution stage instruction address
-  input  logic [`XLEN-1:0] PCM,                       // Memory stage instruction address
-
-  input logic [31:0]       PostSpillInstrRawF,        // Instruction
-
-  // Branch and jump outcome
-  input logic              PCSrcE,                    // Executation stage branch is taken
-  input logic [`XLEN-1:0]  IEUAdrE,                   // The branch/jump target address
-  input logic [`XLEN-1:0]  PCLinkE,                   // The address following the branch instruction. (AKA Fall through address)
-  output logic [3:0]       InstrClassM,               // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
-  output logic             JumpOrTakenBranchM,        // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
-
-  // Report branch prediction status
-  output logic             BPPredWrongE,              // Prediction is wrong
-  output logic             BPPredWrongM,              // Prediction is wrong
-  output logic             DirPredictionWrongM,       // Prediction direction is wrong
-  output logic             BTBPredPCWrongM,           // Prediction target wrong
-  output logic             RASPredPCWrongM,           // RAS prediction is wrong
-  output logic             PredictionInstrClassWrongM // Class prediction is wrong
-  );
-
-  logic                     PredValidF;
-  logic [1:0]               DirPredictionF;
-
-  logic [3:0]               BTBPredInstrClassF, PredInstrClassF, PredInstrClassD, PredInstrClassE;
-  logic [`XLEN-1:0]         PredPCF, RASPCF;
-  logic                     TargetWrongE;
-  logic                     FallThroughWrongE;
-  logic                     PredictionPCWrongE;
-  logic                     PredictionInstrClassWrongE;
-  logic [3:0]               InstrClassF, InstrClassD, InstrClassE, InstrClassW;
-  logic                     DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
-  
-  logic                     SelBPPredF;
-  logic [`XLEN-1:0]         BPPredPCF;
-  logic [`XLEN-1:0]         PCNext0F;
-  logic [`XLEN-1:0] 		PCCorrectE;
-  logic [3:0] 				WrongPredInstrClassD;
-
-
-  logic BTBTargetWrongE;
-  logic RASTargetWrongE;
-  logic JumpOrTakenBranchE;
-
-  logic [`XLEN-1:0] PredPCD, PredPCE, RASPCD, RASPCE;
-
-  // Part 1 branch direction prediction
-  // look into the 2 port Sram model. something is wrong. 
-  if (`BPRED_TYPE == "BPTWOBIT") begin:Predictor
-    twoBitPredictor #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
-      .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
-      .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
-
-  end else if (`BPRED_TYPE == "BPGLOBAL") begin:Predictor
-    globalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
-      .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
-      .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
-
-/-* -----\/----- EXCLUDED -----\/-----
-  end else if (`BPRED_TYPE == "BPSPECULATIVEGLOBAL") begin:Predictor
-    speculativeglobalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-      .DirPredictionF, .DirPredictionWrongE,
-      .BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]),
-      .BranchInstrW(InstrClassW[0]), .WrongPredInstrClassD, .PCSrcE);
-	    
-  end else if (`BPRED_TYPE == "BPGSHARE") begin:Predictor
-    gshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
-      .PCNextF, .PCE, .DirPredictionF, .DirPredictionWrongE,
-      .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
- -----/\----- EXCLUDED -----/\----- *-/
-
-  end else if (`BPRED_TYPE == "BPSPECULATIVEGSHARE") begin:Predictor
-    speculativegshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-      .PCNextF, .PCF, .PCD, .PCE, .DirPredictionF, .DirPredictionWrongE,
-      .PredInstrClassF, .InstrClassD, .InstrClassE, .InstrClassM, .WrongPredInstrClassD, .PCSrcE);
-
-  end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor
-    // *** Fix me
-/-* -----\/----- EXCLUDED -----\/-----
-    localHistoryPredictor DirPredictor(.clk,
-      .reset, .StallF, .StallE,
-      .LookUpPC(PCNextF),
-      .Prediction(DirPredictionF),
-      // update
-      .UpdatePC(PCE),
-      .UpdateEN(InstrClassE[0] & ~StallE),
-      .PCSrcE,
-      .UpdatePrediction(InstrClassE[0]));
- -----/\----- EXCLUDED -----/\----- *-/
-  end 
-
-  // this predictor will have two pieces of data,
-  // 1) A direction (1 = Taken, 0 = Not Taken)
-  // 2) Any information which is necessary for the predictor to build its next state.
-  // For a 2 bit table this is the prediction count.
-
-  // Part 2 Branch target address prediction
-  // *** For now the BTB will house the direct and indirect targets
-
-  btb TargetPredictor(.clk, .reset, .StallF, .StallD, .StallM, .FlushD, .FlushM,
-          .PCNextF, .PCF, .PCD, .PCE,
-          .PredPCF,
-          .BTBPredInstrClassF,
-          .PredValidF,
-          .AnyWrongPredInstrClassE(PredictionInstrClassWrongE),
-          .IEUAdrE,
-          .InstrClassD,
-          .InstrClassE);
-
-  // the branch predictor needs a compact decoding of the instruction class.
-  if (`INSTR_CLASS_PRED == 0) begin : DirectClassDecode
-	logic [4:0] CompressedOpcF;
-	logic [3:0] InstrClassF;
-	logic 		cjal, cj, cjr, cjalr;
-	
-	assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]};
-
-	assign cjal = CompressedOpcF == 5'h09 & `XLEN == 32;
-	assign cj = CompressedOpcF == 5'h0d;
-	assign cjr = CompressedOpcF == 5'h14 & ~PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0;
-	assign cjalr = CompressedOpcF == 5'h14 & PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0;
-	
-	assign InstrClassF[0] = PostSpillInstrRawF[6:0] == 7'h63 | 
-							(`C_SUPPORTED & CompressedOpcF[4:1] == 4'h7);
-	
-	assign InstrClassF[1] = (PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) != 5'h01 & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump register, but not return
-							(PostSpillInstrRawF[6:0] == 7'h6F & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump, RD != x1 or x5
-							(`C_SUPPORTED & (cj | (cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01)) ));
-	
-	assign InstrClassF[2] = PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01 | // return must return to ra or r5
-							(`C_SUPPORTED & (cjalr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01));
-	
-	assign InstrClassF[3] = ((PostSpillInstrRawF[6:0] & 7'h77) == 7'h67 & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5
-							(`C_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01)));
-	assign PredInstrClassF = InstrClassF;
-	assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | 
-						PredInstrClassF[2] |
-						PredInstrClassF[1] |
-						PredInstrClassF[3];
-  end else begin
-	assign PredInstrClassF = BTBPredInstrClassF;
-	assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | 
-						PredInstrClassF[2] |
-						(PredInstrClassF[1] & PredValidF) |
-						(PredInstrClassF[3] & PredValidF);
-  end
-  
-  // Part 3 RAS
-  RASPredictor RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
-							.PredInstrClassF, .InstrClassD, .InstrClassE,
-							.WrongPredInstrClassD, .RASPCF, .PCLinkE);
-
-  assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF;
-
-  assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5
-  assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5
-  assign InstrClassD[1] = (InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01) | // jump register, but not return
-						  (InstrD[6:0] == 7'h6F & (InstrD[11:7] & 5'h1B) != 5'h01); // jump, RD != x1 or x5
-  assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch
-
-  flopenrc #(4) InstrClassRegE(clk, reset,  FlushE, ~StallE, InstrClassD, InstrClassE);
-  flopenrc #(4) InstrClassRegM(clk, reset,  FlushM, ~StallM, InstrClassE, InstrClassM);
-  flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPPredWrongE, BPPredWrongM);
-  flopenrc #(1) JumpOrTakenBranchMReg(clk, reset, FlushM, ~StallM, JumpOrTakenBranchE, JumpOrTakenBranchM);
-
-  // branch predictor
-  flopenrc #(4) BPPredWrongRegM(clk, reset, FlushM, ~StallM, 
-    {DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, PredictionInstrClassWrongE},
-    {DirPredictionWrongM, BTBPredPCWrongM, RASPredPCWrongM, PredictionInstrClassWrongM});
-
-  // pipeline the class
-  flopenrc #(4) PredInstrClassRegD(clk, reset, FlushD, ~StallD, PredInstrClassF, PredInstrClassD);
-  flopenrc #(4) PredInstrClassRegE(clk, reset, FlushE, ~StallE, PredInstrClassD, PredInstrClassE);
-
-  // Check the prediction
-  // first check if the target or fallthrough address matches what was predicted.
-  assign TargetWrongE = IEUAdrE != PCD;
-  assign FallThroughWrongE = PCLinkE != PCD;
-  // If the target is taken check the target rather than fallthrough.  The instruction needs to be a branch if PCSrcE is selected
-  // Remember the bpred can incorrectly predict a non cfi instruction as a branch taken.  If the real instruction is non cfi
-  // it must have selected the fall through.
-  assign PredictionPCWrongE = PCCorrectE != PCD;
-
-//  assign PredictionPCWrongE = (PCSrcE  & (|InstrClassE) ? TargetWrongE : FallThroughWrongE);
-
-  // The branch direction also need to checked.
-  // However if the direction is wrong then the pc will be wrong.  This is only relavent to checking the
-  // accuracy of the direciton prediction.
-  //assign DirPredictionWrongE = (BPPredE[1] ^ PCSrcE) & InstrClassE[0];
-  
-  // Finally we need to check if the class is wrong.  When the class is wrong the BTB needs to be updated.
-  // Also we want to track this in a performance counter.
-  assign PredictionInstrClassWrongE = InstrClassE != PredInstrClassE;
-
-  // We want to output to the instruction fetch if the PC fetched was wrong.  If by chance the predictor was wrong about
-  // the direction or class, but correct about the target we don't have the flush the pipeline.  However we still
-  // need this information to verify the accuracy of the predictors.
-  assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE) | BPPredClassNonCFIWrongE;
-//  assign BPPredWrongE = PredictionPCWrongE & InstrValidE & InstrValidD;
-
-  // If we have a jump, jump register or jal or jalr and the PC is wrong we need to increment the performance counter.
-  //assign BTBPredPCWrongE = (InstrClassE[3] | InstrClassE[1] | InstrClassE[0]) & PredictionPCWrongE;
-  //assign BTBPredPCWrongE = TargetWrongE & (InstrClassE[3] | InstrClassE[1] | InstrClassE[0]) & PCSrcE;
-  assign BTBPredPCWrongE = BTBTargetWrongE;
-  
-  // similar with RAS. Over counts ras if the class prediction was wrong.
-  //assign RASPredPCWrongE = TargetWrongE & InstrClassE[2] & PCSrcE;
-  assign RASPredPCWrongE = RASTargetWrongE;
-  // Finally if the real instruction class is non CFI but the predictor said it was we need to count.
-  assign BPPredClassNonCFIWrongE = PredictionInstrClassWrongE & ~|InstrClassE;
-
-  // branch class prediction wrong.
-  assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD;
-  
-  // Selects the BP or PC+2/4.
-  mux2 #(`XLEN) pcmux0(PCPlus2or4F, BPPredPCF, SelBPPredF, PCNext0F);
-  // If the prediction is wrong select the correct address.
-  mux2 #(`XLEN) pcmux1(PCNext0F, PCCorrectE, BPPredWrongE, PCNext1F);  
-  // Correct branch/jump target.
-  mux2 #(`XLEN) pccorrectemux(PCLinkE, IEUAdrE, PCSrcE, PCCorrectE);
-  
-  // If the fence/csrw was predicted as a taken branch then we select PCF, rather PCE.
-  // Effectively this is PCM+4 or the non-existant PCLinkM
-  //  if(`BPCLASS) begin
-  mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPPredWrongM, NextValidPCE);
-  //  end else begin
-  //	assign NextValidPCE = PCE;
-  //  end
-
-  // performance counters
-  // 1. class         (class wrong / minstret) (PredictionInstrClassWrongM / csr)                    // Correct now
-  // 2. target btb    (btb target wrong / class[0,1,3])  (btb target wrong / (br + j + jal)
-  // 3. target ras    (ras target wrong / class[2])
-  // 4. direction     (br dir wrong / class[0])
-
-  assign BTBTargetWrongE = (PredPCE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] | InstrClassE[3]) & PCSrcE;
-  assign RASTargetWrongE = (RASPCE != IEUAdrE) & InstrClassE[2] & PCSrcE;
-
-  assign JumpOrTakenBranchE = (InstrClassE[0] & PCSrcE) | InstrClassE[1] | InstrClassE[3];
-  
-  flopenrc #(`XLEN) BTBTargetDReg(clk, reset, FlushD, ~StallD, PredPCF, PredPCD);
-  flopenrc #(`XLEN) BTBTargetEReg(clk, reset, FlushE, ~StallE, PredPCD, PredPCE);
-
-  flopenrc #(`XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD);
-  flopenrc #(`XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE);
-  
-endmodule
- -----/\----- EXCLUDED -----/\----- */
diff --git a/src/ifu/bpred/gshare_copy.sv b/src/ifu/bpred/gshare_copy.sv
new file mode 100644
index 000000000..119056c83
--- /dev/null
+++ b/src/ifu/bpred/gshare_copy.sv
@@ -0,0 +1,80 @@
+///////////////////////////////////////////
+// globalHistoryPredictor.sv
+//
+// Written: Shreya Sanghai
+// Email: ssanghai@hmc.edu
+// Created: March 16, 2021
+// Modified: 
+//
+// Purpose: Global History Branch predictor with parameterized global history register
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module gshare_copy #(parameter k = 10) (
+  input logic             clk,
+  input logic             reset,
+  input logic             StallF, StallD, StallE, StallM, 
+  input logic             FlushD, FlushE, FlushM,
+  output logic [1:0]      DirPredictionF, 
+  output logic            DirPredictionWrongE,
+  // update
+  input logic [`XLEN-1:0] PCNextF, PCE,
+  input logic             BranchInstrE, BranchInstrM, PCSrcE
+);
+
+  logic [k-1:0]            IndexNextF, IndexE;
+  logic [1:0]              DirPredictionD, DirPredictionE;
+  logic [1:0]              NewDirPredictionE, NewDirPredictionM;
+
+  logic [k-1:0]            GHRF, GHRD, GHRE, GHR;
+  logic [k-1:0]            GHRNext;
+  logic                    PCSrcM;
+
+  assign IndexNextF = GHR & {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
+  assign IndexE = GHRE & {PCE[k+1] ^ PCE[1], PCE[k:2]};
+  
+  ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
+    .ce1(~StallF), .ce2(~StallM & ~FlushM),
+    .ra1(IndexNextF),
+    .rd1(DirPredictionF),
+    .wa2(IndexE),
+    .wd2(NewDirPredictionE),
+    .we2(BranchInstrE & ~StallM & ~FlushM),
+    .bwe2(1'b1));
+
+  flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, DirPredictionF, DirPredictionD);
+  flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, DirPredictionD, DirPredictionE);
+
+  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
+  flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewDirPredictionE, NewDirPredictionM);
+
+  assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
+
+  assign GHRNext = BranchInstrM ? {PCSrcM, GHR[k-1:1]} : GHR;
+  flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchInstrM, GHRNext, GHR);
+  flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
+    
+  flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
+  flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD);
+  flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE);
+
+
+endmodule
diff --git a/testbench/tests.vh b/testbench/tests.vh
index 1e1065cf1..ec6f04f43 100644
--- a/testbench/tests.vh
+++ b/testbench/tests.vh
@@ -50,9 +50,9 @@ string tvpaths[] = '{
 
   string embench[] = '{
     `EMBENCH,
+    "bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches
     "bd_speedopt_speed/src/aha-mont64/aha-mont64",
     "bd_speedopt_speed/src/crc32/crc32",
-    "bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches
     "bd_speedopt_speed/src/edn/edn",
     "bd_speedopt_speed/src/huffbench/huffbench",
     "bd_speedopt_speed/src/matmult-int/matmult-int",

From 1ab2d0d19bcd27af5f8ec7a44b45dcc7f5974680 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 13 Feb 2023 17:57:05 -0600
Subject: [PATCH 60/71] Fixed bug in basic gshare implementation.  Should be a
 better comparison to the speculative versions now.

---
 src/ifu/bpred/gshare.sv      |  4 ++--
 src/ifu/bpred/gshare_copy.sv | 20 +++++++++++---------
 2 files changed, 13 insertions(+), 11 deletions(-)

diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv
index fde1a0825..4cffbf93d 100644
--- a/src/ifu/bpred/gshare.sv
+++ b/src/ifu/bpred/gshare.sv
@@ -48,8 +48,8 @@ module gshare #(parameter k = 10) (
   logic [k-1:0]            GHRNext;
   logic                    PCSrcM;
 
-  assign IndexNextF = GHR & {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
-  assign IndexE = GHRE & {PCE[k+1] ^ PCE[1], PCE[k:2]};
+  assign IndexNextF = GHR ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
+  assign IndexE = GHRE ^ {PCE[k+1] ^ PCE[1], PCE[k:2]};
   
   ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallM & ~FlushM),
diff --git a/src/ifu/bpred/gshare_copy.sv b/src/ifu/bpred/gshare_copy.sv
index 119056c83..d73bce20b 100644
--- a/src/ifu/bpred/gshare_copy.sv
+++ b/src/ifu/bpred/gshare_copy.sv
@@ -31,16 +31,16 @@
 module gshare_copy #(parameter k = 10) (
   input logic             clk,
   input logic             reset,
-  input logic             StallF, StallD, StallE, StallM, 
-  input logic             FlushD, FlushE, FlushM,
+  input logic             StallF, StallD, StallE, StallM, StallW,
+  input logic             FlushD, FlushE, FlushM, FlushW,
   output logic [1:0]      DirPredictionF, 
   output logic            DirPredictionWrongE,
   // update
-  input logic [`XLEN-1:0] PCNextF, PCE,
+  input logic [`XLEN-1:0] PCNextF, PCM,
   input logic             BranchInstrE, BranchInstrM, PCSrcE
 );
 
-  logic [k-1:0]            IndexNextF, IndexE;
+  logic [k-1:0]            IndexNextF, IndexM;
   logic [1:0]              DirPredictionD, DirPredictionE;
   logic [1:0]              NewDirPredictionE, NewDirPredictionM;
 
@@ -48,16 +48,16 @@ module gshare_copy #(parameter k = 10) (
   logic [k-1:0]            GHRNext;
   logic                    PCSrcM;
 
-  assign IndexNextF = GHR & {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
-  assign IndexE = GHRE & {PCE[k+1] ^ PCE[1], PCE[k:2]};
+  assign IndexNextF = GHRNext ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
+  assign IndexM = GHR ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
   
   ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallM & ~FlushM),
     .ra1(IndexNextF),
     .rd1(DirPredictionF),
-    .wa2(IndexE),
-    .wd2(NewDirPredictionE),
-    .we2(BranchInstrE & ~StallM & ~FlushM),
+    .wa2(IndexM),
+    .wd2(NewDirPredictionM),
+    .we2(BranchInstrM & ~StallW & ~FlushW),
     .bwe2(1'b1));
 
   flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, DirPredictionF, DirPredictionD);
@@ -72,9 +72,11 @@ module gshare_copy #(parameter k = 10) (
   flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchInstrM, GHRNext, GHR);
   flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
     
+/* -----\/----- EXCLUDED -----\/-----
   flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
   flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD);
   flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE);
+ -----/\----- EXCLUDED -----/\----- */
 
 
 endmodule

From 3847d9e39a91fcf49d27fc3cf9fe939303450186 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 13 Feb 2023 18:07:32 -0600
Subject: [PATCH 61/71] Updated global history predictor.

---
 src/ifu/bpred/speculativeglobalhistory.sv | 25 ++++++++++++++---------
 1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/src/ifu/bpred/speculativeglobalhistory.sv b/src/ifu/bpred/speculativeglobalhistory.sv
index 645ac99e6..1ddd3dfe4 100644
--- a/src/ifu/bpred/speculativeglobalhistory.sv
+++ b/src/ifu/bpred/speculativeglobalhistory.sv
@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// speculativeglobalhistory.sv
+// gsharePredictor.sv
 //
 // Written: Shreya Sanghai
 // Email: ssanghai@hmc.edu
@@ -36,8 +36,10 @@ module speculativeglobalhistory #(parameter int k = 10 ) (
   output logic [1:0] 	  DirPredictionF, 
   output logic 			  DirPredictionWrongE,
   // update
-  input logic [3:0] 	  InstrClassD, InstrClassE,
-  input logic [2:0] 	  PredInstrClassF, WrongPredInstrClassD, 
+  input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE,
+  input logic [3:0] 	  PredInstrClassF,
+  input logic [3:0]       InstrClassD, InstrClassE, InstrClassM,
+  input logic [3:0] 	  WrongPredInstrClassD, 
   input logic 			  PCSrcE
 );
 
@@ -47,9 +49,9 @@ module speculativeglobalhistory #(parameter int k = 10 ) (
   logic [1:0]              TableDirPredictionF, DirPredictionD, DirPredictionE;
   logic [1:0]              NewDirPredictionE;
 
-  logic [k-1:0] 		   GHRF, GHRD, GHRE;
+  logic [k-1:0] 		   GHRF, GHRD, GHRE, GHRM;
   logic 				   GHRLastF;
-  logic [k-1:0] 		   GHRNextF, GHRNextD, GHRNextE;
+  logic [k-1:0] 		   GHRNextF, GHRNextD, GHRNextE, GHRNextM;
   logic [k-1:0]            IndexNextF, IndexF, IndexD, IndexE;
   logic [1:0]              ForwardNewDirPrediction, ForwardDirPredictionF;
 
@@ -57,8 +59,8 @@ module speculativeglobalhistory #(parameter int k = 10 ) (
   
   assign IndexNextF = GHRNextF;
   assign IndexF = GHRF;
-  assign IndexD = GHRD[k-1:0];
-  assign IndexE = GHRE[k-1:0];
+  assign IndexD = GHRD;
+  assign IndexE = GHRE;
       
   ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
     .ce1(~StallF | reset), .ce2(~StallM & ~FlushM),
@@ -111,15 +113,18 @@ module speculativeglobalhistory #(parameter int k = 10 ) (
   // If it is wrong and branch does exist then shift right and insert the prediction.
   // If the branch does not exist then shift left and use GHRLastF to restore the LSB.
   logic [k-1:0] 		   GHRClassWrong;
-  mux2 #(k) GHRClassWrongMux({DirPredictionD[1], GHRF[k-1:1]}, {GHRF[k-2:0], GHRLastF}, InstrClassD[0], GHRClassWrong);
+  mux2 #(k) GHRClassWrongMux({DirPredictionD[1], GHRF[k-1:1]}, {GHRF[k-2:0], GHRLastF}, ~InstrClassD[0], GHRClassWrong);
   // As with GHRF FlushD and wrong direction prediction flushes the pipeline and restores to GHRNextE.
   mux3 #(k) GHRDMux(GHRF, GHRClassWrong, GHRNextE, {FlushDOrDirWrong, WrongPredInstrClassD[0]}, GHRNextD);
 
   flopenr  #(k) GHRDReg(clk, reset, ~StallD | FlushDOrDirWrong, GHRNextD, GHRD);
 
-  mux3 #(k) GHREMux(GHRD, GHRE, {PCSrcE, GHRD[k-2:0]}, {InstrClassE[0] & ~FlushM, FlushE}, GHRNextE);
+  mux3 #(k) GHREMux(GHRD, GHRNextM, {PCSrcE, GHRD[k-2:0]}, {InstrClassE[0] & ~FlushM, FlushE}, GHRNextE);
 
-  flopenr  #(k) GHREReg(clk, reset, ((InstrClassE[0] & ~FlushM) & ~StallE) | FlushE, GHRNextE, GHRE);
+  flopenr  #(k) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, GHRE);
+
+  assign GHRNextM = FlushM ? GHRM : GHRE;
+  flopenr  #(k) GHRMReg(clk, reset, (InstrClassM[0] & ~StallM) | FlushM, GHRNextM, GHRM);
   
   assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & InstrClassE[0];
 

From 6ea830cf44a9d9aa1b5d9a0a656e2c8a34e6f7aa Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 13 Feb 2023 18:08:13 -0600
Subject: [PATCH 62/71] Fixed global history predictor.

---
 src/ifu/bpred/speculativeglobalhistory.sv | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/ifu/bpred/speculativeglobalhistory.sv b/src/ifu/bpred/speculativeglobalhistory.sv
index 1ddd3dfe4..8ebda61c5 100644
--- a/src/ifu/bpred/speculativeglobalhistory.sv
+++ b/src/ifu/bpred/speculativeglobalhistory.sv
@@ -36,7 +36,6 @@ module speculativeglobalhistory #(parameter int k = 10 ) (
   output logic [1:0] 	  DirPredictionF, 
   output logic 			  DirPredictionWrongE,
   // update
-  input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE,
   input logic [3:0] 	  PredInstrClassF,
   input logic [3:0]       InstrClassD, InstrClassE, InstrClassM,
   input logic [3:0] 	  WrongPredInstrClassD, 

From f3c8c6e60a7c4998dbdbf65daef96e91e1e876fd Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 13 Feb 2023 18:08:51 -0600
Subject: [PATCH 63/71] More fixeds to global history.

---
 src/ifu/bpred/bpred.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index 69bec3e73..a88845efb 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -107,7 +107,7 @@ module bpred (
   end else if (`BPRED_TYPE == "BPSPECULATIVEGLOBAL") begin:Predictor
     speculativeglobalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .DirPredictionF, .DirPredictionWrongE,
-      .PredInstrClassF, .InstrClassD, .InstrClassE, .WrongPredInstrClassD, .PCSrcE);
+      .PredInstrClassF, .InstrClassD, .InstrClassE, .InstrClassM, .WrongPredInstrClassD, .PCSrcE);
 	    
   end else if (`BPRED_TYPE == "BPGSHARE") begin:Predictor
     gshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,

From fc3baa684684e8ad23f9a07a2dae05367f8edca5 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 13 Feb 2023 18:52:52 -0600
Subject: [PATCH 64/71] Updated gshare (no speculation) to have better
 performance.

---
 src/ifu/bpred/bpred.sv       |  4 +-
 src/ifu/bpred/gshare.sv      | 17 ++++----
 src/ifu/bpred/gshare_copy.sv | 80 ------------------------------------
 3 files changed, 11 insertions(+), 90 deletions(-)
 delete mode 100644 src/ifu/bpred/gshare_copy.sv

diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index 69bec3e73..6ed6c8c86 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -110,8 +110,8 @@ module bpred (
       .PredInstrClassF, .InstrClassD, .InstrClassE, .WrongPredInstrClassD, .PCSrcE);
 	    
   end else if (`BPRED_TYPE == "BPGSHARE") begin:Predictor
-    gshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
-      .PCNextF, .PCE, .DirPredictionF, .DirPredictionWrongE,
+    gshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+      .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
       .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
 
   end else if (`BPRED_TYPE == "BPSPECULATIVEGSHARE") begin:Predictor
diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv
index fde1a0825..35a73fb04 100644
--- a/src/ifu/bpred/gshare.sv
+++ b/src/ifu/bpred/gshare.sv
@@ -31,12 +31,12 @@
 module gshare #(parameter k = 10) (
   input logic             clk,
   input logic             reset,
-  input logic             StallF, StallD, StallE, StallM, 
-  input logic             FlushD, FlushE, FlushM,
+  input logic             StallF, StallD, StallE, StallM, StallW,
+  input logic             FlushD, FlushE, FlushM, FlushW,
   output logic [1:0]      DirPredictionF, 
   output logic            DirPredictionWrongE,
   // update
-  input logic [`XLEN-1:0] PCNextF, PCE,
+  input logic [`XLEN-1:0] PCNextF, PCM,
   input logic             BranchInstrE, BranchInstrM, PCSrcE
 );
 
@@ -44,20 +44,20 @@ module gshare #(parameter k = 10) (
   logic [1:0]              DirPredictionD, DirPredictionE;
   logic [1:0]              NewDirPredictionE, NewDirPredictionM;
 
-  logic [k-1:0]            GHRF, GHRD, GHRE, GHR;
+  logic [k-1:0]            GHRF, GHRD, GHRE, GHRM, GHR;
   logic [k-1:0]            GHRNext;
   logic                    PCSrcM;
 
-  assign IndexNextF = GHR & {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
-  assign IndexE = GHRE & {PCE[k+1] ^ PCE[1], PCE[k:2]};
+  assign IndexNextF = GHR ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
+  assign IndexE = GHRM ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
   
   ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallM & ~FlushM),
     .ra1(IndexNextF),
     .rd1(DirPredictionF),
     .wa2(IndexE),
-    .wd2(NewDirPredictionE),
-    .we2(BranchInstrE & ~StallM & ~FlushM),
+    .wd2(NewDirPredictionM),
+    .we2(BranchInstrM & ~StallW & ~FlushW),
     .bwe2(1'b1));
 
   flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, DirPredictionF, DirPredictionD);
@@ -75,6 +75,7 @@ module gshare #(parameter k = 10) (
   flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
   flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD);
   flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE);
+  flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM);
 
 
 endmodule
diff --git a/src/ifu/bpred/gshare_copy.sv b/src/ifu/bpred/gshare_copy.sv
deleted file mode 100644
index 119056c83..000000000
--- a/src/ifu/bpred/gshare_copy.sv
+++ /dev/null
@@ -1,80 +0,0 @@
-///////////////////////////////////////////
-// globalHistoryPredictor.sv
-//
-// Written: Shreya Sanghai
-// Email: ssanghai@hmc.edu
-// Created: March 16, 2021
-// Modified: 
-//
-// Purpose: Global History Branch predictor with parameterized global history register
-// 
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// 
-// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-`include "wally-config.vh"
-
-module gshare_copy #(parameter k = 10) (
-  input logic             clk,
-  input logic             reset,
-  input logic             StallF, StallD, StallE, StallM, 
-  input logic             FlushD, FlushE, FlushM,
-  output logic [1:0]      DirPredictionF, 
-  output logic            DirPredictionWrongE,
-  // update
-  input logic [`XLEN-1:0] PCNextF, PCE,
-  input logic             BranchInstrE, BranchInstrM, PCSrcE
-);
-
-  logic [k-1:0]            IndexNextF, IndexE;
-  logic [1:0]              DirPredictionD, DirPredictionE;
-  logic [1:0]              NewDirPredictionE, NewDirPredictionM;
-
-  logic [k-1:0]            GHRF, GHRD, GHRE, GHR;
-  logic [k-1:0]            GHRNext;
-  logic                    PCSrcM;
-
-  assign IndexNextF = GHR & {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
-  assign IndexE = GHRE & {PCE[k+1] ^ PCE[1], PCE[k:2]};
-  
-  ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
-    .ce1(~StallF), .ce2(~StallM & ~FlushM),
-    .ra1(IndexNextF),
-    .rd1(DirPredictionF),
-    .wa2(IndexE),
-    .wd2(NewDirPredictionE),
-    .we2(BranchInstrE & ~StallM & ~FlushM),
-    .bwe2(1'b1));
-
-  flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, DirPredictionF, DirPredictionD);
-  flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, DirPredictionD, DirPredictionE);
-
-  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
-  flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewDirPredictionE, NewDirPredictionM);
-
-  assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
-
-  assign GHRNext = BranchInstrM ? {PCSrcM, GHR[k-1:1]} : GHR;
-  flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchInstrM, GHRNext, GHR);
-  flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
-    
-  flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
-  flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD);
-  flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE);
-
-
-endmodule

From 237a1153770dbee3feb459177dbc2817a69b31db Mon Sep 17 00:00:00 2001
From: eroom1966 <moore@imperas.com>
Date: Wed, 15 Feb 2023 11:12:30 +0000
Subject: [PATCH 65/71] add files to support coverage

---
 sim/imperas.ic                 |  1 -
 sim/wally-imperas-cov.do       | 68 ++++++++++++++++++++++++++++++++++
 sim/wally-imperas.do           |  1 +
 testbench/testbench_imperas.sv |  1 +
 4 files changed, 70 insertions(+), 1 deletion(-)
 create mode 100644 sim/wally-imperas-cov.do

diff --git a/sim/imperas.ic b/sim/imperas.ic
index 302773d0e..d28234bbc 100644
--- a/sim/imperas.ic
+++ b/sim/imperas.ic
@@ -1,6 +1,5 @@
 --override cpu/show_c_prefix=T
 --override cpu/unaligned=F
---override cpu/mstatus_FS=1
 --override cpu/ignore_non_leaf_DAU=1
 
 # Enable the Imperas instruction coverage
diff --git a/sim/wally-imperas-cov.do b/sim/wally-imperas-cov.do
new file mode 100644
index 000000000..9ac7a39e4
--- /dev/null
+++ b/sim/wally-imperas-cov.do
@@ -0,0 +1,68 @@
+# wally.do 
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+#
+# Modification by Oklahoma State University & Harvey Mudd College
+# Use with Testbench 
+# James Stine, 2008; David Harris 2021
+# Go Cowboys!!!!!!
+#
+# Takes 1:10 to run RV64IC tests using gui
+
+onbreak {resume}
+
+# create library
+if [file exists work] {
+    vdel -all
+}
+vlib work
+
+# compile source files
+# suppress spurious warnngs about 
+# "Extra checking for conflicts with always_comb done at vopt time"
+# because vsim will run vopt
+
+# start and run simulation
+# remove +acc flag for faster sim during regressions if there is no need to access internal signals
+        # *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN.  For now just live with the warnings.
+vlog +incdir+../config/$1 \
+     +incdir+../config/shared \
+     +define+USE_IMPERAS_DV \
+     +incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \
+     +incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \
+     $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-api-pkg.sv    \
+     $env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-trace.sv      \
+     $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/rvvi-pkg.sv   \
+     $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2api.sv  \
+     $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2log.sv  \
+     \
+     +define+INCLUDE_TRACE2COV +define+COVER_BASE_RV64I +define+COVER_LEVEL_DV_PR_EXT \
+       +define+COVER_RV64I \
+       +define+COVER_RV64C \
+       +define+COVER_RV64M \
+     +incdir+$env(IMPERAS_HOME)/ImpProprietary/source/host/riscvISACOV/source \
+     $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2cov.sv  \
+     \
+     ../testbench/testbench_imperas.sv \
+     ../testbench/common/*.sv   \
+     ../src/*/*.sv \
+     ../src/*/*/*.sv \
+     -suppress 2583 \
+     -suppress 7063  \
+     +acc
+vopt +acc work.testbench -G DEBUG=1 -o workopt 
+vsim workopt +nowarn3829  -fatal 7 \
+     -sv_lib $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model \
+     +testDir=$env(TESTDIR) $env(OTHERFLAGS) +TRACE2COV_ENABLE=1 \
+     -do "coverage save -onexit ./riscv.ucdb"
+
+view wave
+#-- display input and output signals as hexidecimal values
+# add log -recursive /*
+# do wave.do
+
+run -all
+
+noview ../testbench/testbench_imperas.sv
+view wave
+
+quit -f
diff --git a/sim/wally-imperas.do b/sim/wally-imperas.do
index 4164b7bdb..d10c57d57 100644
--- a/sim/wally-imperas.do
+++ b/sim/wally-imperas.do
@@ -34,6 +34,7 @@ vlog +incdir+../config/$1 \
      $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/rvvi-pkg.sv   \
      $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2api.sv  \
      $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2log.sv  \
+     $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2cov.sv  \
      ../testbench/testbench_imperas.sv \
      ../testbench/common/*.sv   \
      ../src/*/*.sv \
diff --git a/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv
index e52a79c2e..c7d987b83 100644
--- a/testbench/testbench_imperas.sv
+++ b/testbench/testbench_imperas.sv
@@ -125,6 +125,7 @@ module testbench;
 
 `ifdef USE_IMPERAS_DV
     trace2log idv_trace2log(rvvi);
+    trace2cov idv_trace2cov(rvvi);
 
     // enabling of comparison types
     trace2api #(.CMP_PC      (1),

From a3aeff2703e33e1328fb87b666d1f182b2475fd3 Mon Sep 17 00:00:00 2001
From: James Stine <james.stine@okstate.edu>
Date: Wed, 15 Feb 2023 18:12:12 -0600
Subject: [PATCH 66/71] Update if-then-else for ram items

---
 src/generic/mem/ram1p1rwbe.sv  | 14 +++++++-------
 src/generic/mem/ram2p1r1wbe.sv |  2 +-
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv
index e33e708a3..f1e784c13 100644
--- a/src/generic/mem/ram1p1rwbe.sv
+++ b/src/generic/mem/ram1p1rwbe.sv
@@ -55,10 +55,10 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) (
      logic [WIDTH-1:0] BitWriteMask;
      for (index=0; index < WIDTH; index++) 
        assign BitWriteMask[index] = bwe[index/8];
-    TS1N28HPCPSVTB64X128M4SW sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
+    ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
 			      .A(addr), .D(din), 
 			      .BWEB(~BitWriteMask), .Q(dout));
-     
+    
   end else if (`USE_SRAM == 1 && WIDTH == 44  && DEPTH == 64) begin
      genvar index;
      // 64 x 44-bit SRAM
@@ -69,15 +69,15 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) (
 			      .A(addr), .D(din), 
 			      .BWEB(~BitWriteMask), .Q(dout));
 
-  end if (`USE_SRAM == 1 && WIDTH == 128 && DEPTH == 32) begin
+  end else if (`USE_SRAM == 1 && WIDTH == 128 && DEPTH == 32) begin
      genvar index;
      // 64 x 128-bit SRAM
      logic [WIDTH-1:0] BitWriteMask;
      for (index=0; index < WIDTH; index++) 
        assign BitWriteMask[index] = bwe[index/8];
-    TS1N28HPCPSVTB64X128M4SW sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
-			      .A(addr), .D(din), 
-			      .BWEB(~BitWriteMask), .Q(dout));
+     ram1p1rwbe_128x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
+				.A(addr), .D(din), 
+				.BWEB(~BitWriteMask), .Q(dout));
      
   end else if (`USE_SRAM == 1 && WIDTH == 22  && DEPTH == 32) begin
      genvar index;
@@ -85,7 +85,7 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) (
      logic [WIDTH-1:0] BitWriteMask;
      for (index=0; index < WIDTH; index++) 
        assign BitWriteMask[index] = bwe[index/8];
-     ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we),
+     ram1p1rwbe_64x22 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we),
 			      .A(addr), .D(din), 
 			      .BWEB(~BitWriteMask), .Q(dout));     
     
diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv
index 08c232bba..da099cdc7 100644
--- a/src/generic/mem/ram2p1r1wbe.sv
+++ b/src/generic/mem/ram2p1r1wbe.sv
@@ -64,7 +64,7 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) (
 				  .QA(rd1),
 				  .QB());
 
-   end if (`USE_SRAM == 1 && WIDTH == 36 && DEPTH == 1024) begin
+   end else if (`USE_SRAM == 1 && WIDTH == 36 && DEPTH == 1024) begin
    
       ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk), 
 				  .CEBA(~ce1), .CEBB(~ce2),

From 9e83b0bfafd4a02eccc46e7fdf98e41ced59962f Mon Sep 17 00:00:00 2001
From: James Stine <james.stine@okstate.edu>
Date: Thu, 16 Feb 2023 08:07:17 -0600
Subject: [PATCH 67/71] Update topo psyn stuff

---
 synthDC/.synopsys_dc.setup | 20 ++++++++++++++++++++
 synthDC/Makefile           |  4 +++-
 synthDC/scripts/synth.tcl  | 30 ++++++++++++++++++++++++++++++
 synthDC/wallySynth.py      |  4 ++--
 4 files changed, 55 insertions(+), 3 deletions(-)

diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup
index 2fdc11c27..1310c4dd7 100755
--- a/synthDC/.synopsys_dc.setup
+++ b/synthDC/.synopsys_dc.setup
@@ -21,6 +21,21 @@ if {$tech == "sky130"} {
     set s10lib /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a
     lappend search_path $s10lib
 }
+elseif {$tech == "tsmc28psyn"} {
+    set TLU /home/jstine/TLU+
+    set s10lib /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a
+    lappend search_path $s10lib
+    set TLUPLUS true
+    set mw_logic1_net VDD
+    set mw_logic0_net VSS
+    set TLU_PDK /import/yukari1/jstine/TLU+/
+    set CAPTABLE $TLU/1p8m/
+    set MW_REFERENCE_LIBRARY /home/jstine/MW
+    set MW_TECH_FILE tcbn28hpcplusbwp7t30p140
+    set MAX_TLU_FILE $CAPTABLE/crn28hpc+_1p08m+ut-alrdl_5x1z1u_typical.tluplus
+    set MIN_TLU_FILE $CAPTABLE/crn28hpc+_1p08m+ut-alrdl_5x1z1u_rcworst.tluplus
+    set PRS_MAP_FILE $MW_REFERENCE_LIBRARY/astro_layername.map
+}
 
 # Synthetic libraries
 set synthetic_library   [list dw_foundation.sldb]
@@ -36,6 +51,11 @@ if {$tech == "sky130"} {
 } elseif {$tech == "tsmc28"} {
     lappend target_library $s10lib/tcbn28hpcplusbwp30p140tt0p9v25c.db
 }
+} elseif {$tech == "tsmc28psyn"} {
+    set mw_reference_library [list ]    
+    lappend target_library $s10lib/tcbn28hpcplusbwp30p140tt0p9v25c.db
+    lappend mw_reference_library $MW_REFERENCE_LIBRARY/tcbn28hpcplusbwp7t30p140    
+}
 
 # Set Link Library
 set link_library "$target_library $synthetic_library"
diff --git a/synthDC/Makefile b/synthDC/Makefile
index 76531d950..d7fb2b914 100755
--- a/synthDC/Makefile
+++ b/synthDC/Makefile
@@ -122,6 +122,8 @@ synth: mkdirecs configs rundc clean
 rundc:
 	dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out
 	
+rundctopo:
+	dc_shell-xg-t -64bit -topographical_mode -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out
 	
 clean:
 	rm -rf $(OUTPUTDIR)/hdl
@@ -132,4 +134,4 @@ clean:
 	rm -f filenames*.log
 	rm -f power.saif
 	rm -f Synopsys_stack_trace_*.txt
-	rm -f crte_*.txt
\ No newline at end of file
+	rm -f crte_*.txt
diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl
index 1040f35ce..830203520 100755
--- a/synthDC/scripts/synth.tcl
+++ b/synthDC/scripts/synth.tcl
@@ -49,6 +49,36 @@ set report_default_significant_digits 6
 set verilogout_show_unconnected_pins "true"
 set vhdlout_show_unconnected_pins "true"
 
+#  Set up MW List
+set MY_LIB_NAME $my_toplevel
+# Create MW
+if { [shell_is_in_topographical_mode] } {
+    echo "In Topographical Mode...processing\n"
+    if {[file isdirectory $MY_LIB_NAME]} {
+	echo "MW directory already here, deleting/readdding."
+	[exec rm -rf $my_toplevel]
+	create_mw_lib  -technology $MW_REFERENCE_LIBRARY/$MW_TECH_FILE.tf \
+	    -mw_reference_library $mw_reference_library $MY_LIB_NAME
+    } else {
+	create_mw_lib  -technology $MW_REFERENCE_LIBRARY/$MW_TECH_FILE.tf \
+	    -mw_reference_library $mw_reference_library $MY_LIB_NAME
+    }
+
+    # Open MW
+    open_mw_lib $MY_LIB_NAME
+    
+    # TLU+
+    set_tlu_plus_files -max_tluplus $MAX_TLU_FILE -min_tluplus $MIN_TLU_FILE \
+	-tech2itf_map $PRS_MAP_FILE
+
+} else {
+    if {[file isdirectory $MY_LIB_NAME]} {
+	[exec rm -rf $my_toplevel]
+	echo "MW directory already here, deleting."
+    }
+    echo "In normal DC mode...processing\n"
+}
+
 # Due to parameterized Verilog must use analyze/elaborate and not 
 # read_verilog/vhdl (change to pull in Verilog and/or VHDL)
 #
diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py
index 3253607d5..cfcfde788 100755
--- a/synthDC/wallySynth.py
+++ b/synthDC/wallySynth.py
@@ -16,7 +16,7 @@ def mask(command):
 
 if __name__ == '__main__':
     
-    techs = ['sky90', 'tsmc28']
+    techs = ['sky90', 'tsmc28', 'tsmc28psyn']
     allConfigs = ['rv32gc', 'rv32imc', 'rv64gc', 'rv64imc', 'rv32e', 'rv32i', 'rv64i']
     freqVaryPct = [-20, -12, -8, -6, -4, -2, 0, 2, 4, 6, 8, 12, 20]
 
@@ -61,4 +61,4 @@ if __name__ == '__main__':
         defaultfreq = 500 if tech == 'sky90' else 1500
         freq = args.targetfreq if args.targetfreq else defaultfreq
         config = args.version if args.version else 'rv64gc'
-        runSynth(config, mod, tech, freq, maxopt, usesram)
\ No newline at end of file
+        runSynth(config, mod, tech, freq, maxopt, usesram)

From 14c6cfb24d514b794bca7468c177b21e860f7d71 Mon Sep 17 00:00:00 2001
From: James Stine <james.stine@okstate.edu>
Date: Thu, 16 Feb 2023 13:38:26 -0600
Subject: [PATCH 68/71] Fix bugs in scripts for synthesis and tsmc28 psyn

---
 synthDC/.synopsys_dc.setup | 13 +++++++------
 synthDC/wallySynth.py      | 14 ++++++++------
 2 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup
index 1310c4dd7..6942e58e6 100755
--- a/synthDC/.synopsys_dc.setup
+++ b/synthDC/.synopsys_dc.setup
@@ -18,20 +18,22 @@ if {$tech == "sky130"} {
     set s9lib $timing_lib/sky90/sky90_sc/V1.7.4/lib
     lappend search_path $s9lib
 } elseif {$tech == "tsmc28"} {
-    set s10lib /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a
+    set pdk /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/
+    set s10lib $pdk/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a
     lappend search_path $s10lib
 }
 elseif {$tech == "tsmc28psyn"} {
     set TLU /home/jstine/TLU+
-    set s10lib /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a
+    set pdk /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/
+    set s10lib $pdk/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a
     lappend search_path $s10lib
     set TLUPLUS true
     set mw_logic1_net VDD
     set mw_logic0_net VSS
-    set TLU_PDK /import/yukari1/jstine/TLU+/
+    set TLU_PDK /home/jstine/TLU+/
     set CAPTABLE $TLU/1p8m/
     set MW_REFERENCE_LIBRARY /home/jstine/MW
-    set MW_TECH_FILE tcbn28hpcplusbwp7t30p140
+    set MW_TECH_FILE tcbn28hpcplusbwp30p140
     set MAX_TLU_FILE $CAPTABLE/crn28hpc+_1p08m+ut-alrdl_5x1z1u_typical.tluplus
     set MIN_TLU_FILE $CAPTABLE/crn28hpc+_1p08m+ut-alrdl_5x1z1u_rcworst.tluplus
     set PRS_MAP_FILE $MW_REFERENCE_LIBRARY/astro_layername.map
@@ -50,11 +52,10 @@ if {$tech == "sky130"} {
     lappend target_library $s9lib/scc9gena_tt_1.2v_25C.db
 } elseif {$tech == "tsmc28"} {
     lappend target_library $s10lib/tcbn28hpcplusbwp30p140tt0p9v25c.db
-}
 } elseif {$tech == "tsmc28psyn"} {
     set mw_reference_library [list ]    
     lappend target_library $s10lib/tcbn28hpcplusbwp30p140tt0p9v25c.db
-    lappend mw_reference_library $MW_REFERENCE_LIBRARY/tcbn28hpcplusbwp7t30p140    
+    lappend mw_reference_library $MW_REFERENCE_LIBRARY/tcbn28hpcplusbwp30p140    
 }
 
 # Set Link Library
diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py
index cfcfde788..876a482d9 100755
--- a/synthDC/wallySynth.py
+++ b/synthDC/wallySynth.py
@@ -5,9 +5,9 @@ import subprocess
 from multiprocessing import Pool
 import argparse
 
-def runSynth(config, mod, tech, freq, maxopt, usesram):
+def runSynth(config, mod, tech, freq, maxopt, usesram, usetopo):
     global pool
-    command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} USESRAM={} MAXCORES=1".format(config, mod, tech, freq, maxopt, usesram)
+    command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} USESRAM={} USETOPO={} MAXCORES=1".format(config, mod, tech, freq, maxopt, usesram, usetopo)
     pool.map(mask, [command])
 
 def mask(command):
@@ -33,32 +33,34 @@ if __name__ == '__main__':
     parser.add_argument("-e", "--tech", choices=techs, help = "Technology")
     parser.add_argument("-o", "--maxopt", action='store_true', help = "Turn on MAXOPT")
     parser.add_argument("-r", "--usesram", action='store_true', help = "Use SRAM modules")
+    parser.add_argument("-topo", "--usetopo", action='store_true', help = "Run physical synthesis")	
 
     args = parser.parse_args()
 
     tech = args.tech if args.tech else 'sky90'
     maxopt = int(args.maxopt)
     usesram = int(args.usesram)
+    usetopo = int(args.usetopop)	
     mod = 'orig'
 
     if args.freqsweep:
         sc = args.freqsweep
         config = args.version if args.version else 'rv32e'
         for freq in [round(sc+sc*x/100) for x in freqVaryPct]: # rv32e freq sweep
-            runSynth(config, mod, tech, freq, maxopt, usesram)
+            runSynth(config, mod, tech, freq, maxopt, usesram, usetopo)
     if args.configsweep:
         defaultfreq = 1500 if tech == 'sky90' else 5000
         freq = args.targetfreq if args.targetfreq else defaultfreq
         for config in ['rv32i', 'rv64gc', 'rv64i', 'rv32gc', 'rv32imc', 'rv32e']: #configs
-            runSynth(config, mod, tech, freq, maxopt, usesram)
+            runSynth(config, mod, tech, freq, maxopt, usesram, usetopo)
     if args.featuresweep:
         defaultfreq = 500 if tech == 'sky90' else 1500
         freq = args.targetfreq if args.targetfreq else defaultfreq
         config = args.version if args.version else 'rv64gc'
         for mod in ['noFPU', 'noMulDiv', 'noPriv', 'PMP0', 'orig']: 
-            runSynth(config, mod, tech, freq, maxopt, usesram)
+            runSynth(config, mod, tech, freq, maxopt, usesram, usetopo)
     else:
         defaultfreq = 500 if tech == 'sky90' else 1500
         freq = args.targetfreq if args.targetfreq else defaultfreq
         config = args.version if args.version else 'rv64gc'
-        runSynth(config, mod, tech, freq, maxopt, usesram)
+        runSynth(config, mod, tech, freq, maxopt, usesram, usetopo)

From 64eeb07c6bbf15e8054d62730a3b277c952e96cf Mon Sep 17 00:00:00 2001
From: James Stine <james.stine@okstate.edu>
Date: Thu, 16 Feb 2023 15:01:52 -0600
Subject: [PATCH 69/71] Get rid of extra CR/LF in .synopsys_dc.setup file

---
 synthDC/.synopsys_dc.setup | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup
index 6942e58e6..ac93f6592 100755
--- a/synthDC/.synopsys_dc.setup
+++ b/synthDC/.synopsys_dc.setup
@@ -21,8 +21,7 @@ if {$tech == "sky130"} {
     set pdk /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/
     set s10lib $pdk/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a
     lappend search_path $s10lib
-}
-elseif {$tech == "tsmc28psyn"} {
+} elseif {$tech == "tsmc28psyn"} {
     set TLU /home/jstine/TLU+
     set pdk /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/
     set s10lib $pdk/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a

From 8e9cf8f3e4d755a7468ce6dc97918473ed4a7e51 Mon Sep 17 00:00:00 2001
From: James Stine <james.stine@okstate.edu>
Date: Thu, 16 Feb 2023 15:16:32 -0600
Subject: [PATCH 70/71] Update bug in Makefile

---
 synthDC/Makefile | 23 ++++++++++++++++++-----
 1 file changed, 18 insertions(+), 5 deletions(-)

diff --git a/synthDC/Makefile b/synthDC/Makefile
index d7fb2b914..9dd2b0aba 100755
--- a/synthDC/Makefile
+++ b/synthDC/Makefile
@@ -21,6 +21,7 @@ export MAXCORES ?= 1
 export MAXOPT ?= 0
 export DRIVE ?= FLOP
 export USESRAM ?= 1
+export USETOPO ?= 0
 
 time := $(shell date +%F-%H-%M)
 hash := $(shell git rev-parse --short HEAD)
@@ -30,8 +31,6 @@ export SAIFPOWER ?= 0
 OLDCONFIGDIR ?= ${WALLY}/config
 export CONFIGDIR ?= $(OUTPUTDIR)/config
 
-
-
 default:
 	@echo "  Basic synthesis procedure for Wally:"
 	@echo "        Invoke with make synth"
@@ -51,6 +50,18 @@ DIRS = $(DIRS32) $(DIRS64)
 
 configs: $(CONFIG)
 $(CONFIG):
+ifeq ($(USETOPO), 0))
+ifeq ($(TECH), tsmc28psyn))
+	@echo "Bad configuration: you cannot use physical synthesis without tsmc28psyn and usetopo (i.e., -topo)"
+	exit 1
+endif
+endif
+ifeq ($(USETOPO), 1))
+ifneq ($(TECH), tsmc28psyn))
+	@echo "Bad configuration: you cannot use usetopo (i.e., -topo) without tsmc28psyn"
+	exit 1
+endif
+endif
 	@echo $(CONFIG)
 	cp -r $(OLDCONFIGDIR)/shared/*.vh $(CONFIGDIR)
 	cp -r $(OLDCONFIGDIR)/$(CONFIG)/* $(CONFIGDIR)
@@ -116,15 +127,17 @@ mkdirecs:
 	@mkdir -p $(OUTPUTDIR)/mapped
 	@mkdir -p $(OUTPUTDIR)/unmapped
 
-
 synth: mkdirecs configs rundc clean
 
 rundc:
+ifeq ($(USETOPO), 0)
 	dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out
+else
 	
-rundctopo:
 	dc_shell-xg-t -64bit -topographical_mode -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out
-	
+endif
+
+
 clean:
 	rm -rf $(OUTPUTDIR)/hdl
 	rm -rf $(OUTPUTDIR)/WORK

From 3347aa7fe8fa3ee06d73451f73b808ee8bc82afd Mon Sep 17 00:00:00 2001
From: James Stine <james.stine@okstate.edu>
Date: Thu, 16 Feb 2023 15:50:31 -0600
Subject: [PATCH 71/71] fix typo - remove extra p at end of script

---
 synthDC/.synopsys_dc.setup | 1 -
 synthDC/wallySynth.py      | 2 +-
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup
index ac93f6592..ccc0c67c8 100755
--- a/synthDC/.synopsys_dc.setup
+++ b/synthDC/.synopsys_dc.setup
@@ -29,7 +29,6 @@ if {$tech == "sky130"} {
     set TLUPLUS true
     set mw_logic1_net VDD
     set mw_logic0_net VSS
-    set TLU_PDK /home/jstine/TLU+/
     set CAPTABLE $TLU/1p8m/
     set MW_REFERENCE_LIBRARY /home/jstine/MW
     set MW_TECH_FILE tcbn28hpcplusbwp30p140
diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py
index 876a482d9..d89964c10 100755
--- a/synthDC/wallySynth.py
+++ b/synthDC/wallySynth.py
@@ -40,7 +40,7 @@ if __name__ == '__main__':
     tech = args.tech if args.tech else 'sky90'
     maxopt = int(args.maxopt)
     usesram = int(args.usesram)
-    usetopo = int(args.usetopop)	
+    usetopo = int(args.usetopo)	
     mod = 'orig'
 
     if args.freqsweep: