From 475220a5ffe86d068f1c271af4881511b6b85c56 Mon Sep 17 00:00:00 2001 From: Daniel Torres Date: Fri, 17 Jun 2022 15:07:16 -0700 Subject: [PATCH] arch bug fixes and testbench changes --- .gitignore | 2 +- pipelined/regression/Makefile | 6 +- pipelined/regression/makefile-memfile | 2 +- pipelined/testbench/testbench.sv | 69 +- pipelined/testbench/tests.vh | 1045 ++++++++++---------- tests/riscof/Makefile | 38 +- tests/riscof/sail_cSim/riscof_sail_cSim.py | 4 +- tests/riscof/spike/spike_rv32imc_isa.yaml | 6 +- 8 files changed, 596 insertions(+), 576 deletions(-) diff --git a/.gitignore b/.gitignore index 700239f3e..c01ccb392 100644 --- a/.gitignore +++ b/.gitignore @@ -32,7 +32,7 @@ testsBP/*/*/*.elf* testsBP/*/OBJ/* testsBP/*/*.a tests/wally-riscv-arch-test/riscv-test-suite/*/I/*/* -tests/riscof/riscof_work*/* +tests/riscof/riscof_work/ tests/riscof/config32.ini tests/riscof/config64.ini tests/linux-testgen/linux-testvectors/* diff --git a/pipelined/regression/Makefile b/pipelined/regression/Makefile index 302ee4a92..0a9e7d993 100644 --- a/pipelined/regression/Makefile +++ b/pipelined/regression/Makefile @@ -3,7 +3,7 @@ make allclean: make all make clean: - make clean -C ../../addins/riscv-arch-test + make clean -C ../../tests/riscof make clean -C ../../tests/wally-riscv-arch-test # make allclean -C ../../tests/imperas-riscv-tests @@ -15,8 +15,8 @@ make all: #make -C ../../tests/imperas-riscv-tests XLEN=64 --jobs # Build riscv-arch-test 64 and 32-bit versions - make -C ../../addins/riscv-arch-test --jobs - make -C ../../addins/riscv-arch-test XLEN=32 --jobs + make -C ../../tests/riscof/ --jobs + make -C ../../tests/riscof/ XLEN=32 --jobs # Build wally-riscv-arch-test make -C ../../tests/wally-riscv-arch-test/ --jobs diff --git a/pipelined/regression/makefile-memfile b/pipelined/regression/makefile-memfile index 33af19538..892e6db9b 100644 --- a/pipelined/regression/makefile-memfile +++ b/pipelined/regression/makefile-memfile @@ -1,6 +1,6 @@ ROOT := ../.. SUFFIX := work -ARCHDIR := $(ROOT)/addins/riscv-arch-test +ARCHDIR := $(ROOT)/tests/riscof WALLYDIR:= $(ROOT)/tests/wally-riscv-arch-test # IMPERASDIR := $(ROOT)/tests/imperas-riscv-tests # ALLDIRS := $(ARCHDIR)/$(SUFFIX) $(WALLYDIR)/$(SUFFIX) $(IMPERASDIR)/$(SUFFIX) diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 6c2e0b89b..d4874b617 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -51,7 +51,6 @@ module testbench; string tests[]; logic [3:0] dummy; - string ProgramAddrMapFile, ProgramLabelMapFile; logic [`AHBW-1:0] HRDATAEXT; logic HREADYEXT, HRESPEXT; logic [31:0] HADDR; @@ -65,6 +64,9 @@ logic [3:0] dummy; logic HCLK, HRESETn; logic [`XLEN-1:0] PCW; + string ProgramAddrMapFile, ProgramLabelMapFile; + integer ProgramAddrLabelArray [string]; + logic DCacheFlushDone, DCacheFlushStart; flopenr #(`XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW); @@ -127,7 +129,7 @@ logic [3:0] dummy; end string signame, memfilename, pathname, objdumpfilename, adrstr, outputfile; - integer outputFilePointer, ProgramLabelMap, ProgramAddrMap; + integer outputFilePointer; logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; logic UARTSin, UARTSout; @@ -193,6 +195,11 @@ logic [3:0] dummy; ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"}; ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"}; + // declare memory labels that interest us, the updateProgramAddrLabelArray task will find the addr of each label and fill the array + // to expand, add more elements to this array and initialize them to zero (also initilaize them to zero at the start of the next test) + ProgramAddrLabelArray = '{ "begin_signature" : 0, + "tohost" : 0 }; + updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray); $display("Read memfile %s", memfilename); reset_ext = 1; # 42; reset_ext = 0; end @@ -217,30 +224,12 @@ logic [3:0] dummy; end // Termination condition (i.e. we finished running current test) if (DCacheFlushDone) begin - // Gets the memory location of begin_signature - adrstr = "0"; - ProgramLabelMap = $fopen(ProgramLabelMapFile, "r"); - ProgramAddrMap = $fopen(ProgramAddrMapFile, "r"); - if (ProgramLabelMap & ProgramAddrMap) begin // check we found both files - while (!$feof(ProgramLabelMap)) begin - string label; - integer returncode; - returncode = $fgets(label, ProgramLabelMap); - returncode = $fgets(adrstr, ProgramAddrMap); - if (label == "begin_signature\n") begin - if (DEBUG) $display("%s begin_signature adrstr: %s", TEST, adrstr); - break; - end - end - end - if (adrstr == "0") begin + integer begin_signature_addr; + begin_signature_addr = ProgramAddrLabelArray["begin_signature"]; + if (!begin_signature_addr) $display("begin_signature addr not found in %s", ProgramLabelMapFile); - end - $fclose(ProgramLabelMap); - $fclose(ProgramAddrMap); - - testadr = ($unsigned(adrstr.atohex()))/(`XLEN/8); - testadrNoBase = (adrstr.atohex() - `RAM_BASE)/(`XLEN/8); + testadr = ($unsigned(begin_signature_addr))/(`XLEN/8); + testadrNoBase = (begin_signature_addr - `RAM_BASE)/(`XLEN/8); #600; // give time for instructions in pipeline to finish if (TEST == "embench") begin // Writes contents of begin_signature to .sim.output file @@ -318,7 +307,6 @@ logic [3:0] dummy; end end // move onto the next test, check to see if we're done - // test = test + 2; test = test + 1; if (test == tests.size()) begin if (totalerrors == 0) $display("SUCCESS! All tests ran without failures."); @@ -336,6 +324,9 @@ logic [3:0] dummy; ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"}; ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"}; + ProgramAddrLabelArray = '{ "begin_signature" : 0, + "tohost" : 0 }; + updateProgramAddrLabelArray(.ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile), .ProgramAddrLabelArray(ProgramAddrLabelArray)); $display("Read memfile %s", memfilename); reset_ext = 1; # 47; reset_ext = 0; end @@ -363,7 +354,8 @@ logic [3:0] dummy; (dut.core.ieu.dp.regf.we3 & dut.core.ieu.dp.regf.a3 == 3 & dut.core.ieu.dp.regf.wd3 == 1)) | - (dut.core.ifu.InstrM == 32'h6f | dut.core.ifu.InstrM == 32'hfc32a423 | dut.core.ifu.InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM; + ((dut.core.ifu.InstrM == 32'h6f | dut.core.ifu.InstrM == 32'hfc32a423 | dut.core.ifu.InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) | + ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" ); DCacheFlushFSM DCacheFlushFSM(.clk(clk), .reset(reset), @@ -523,5 +515,26 @@ module copyShadow end end -endmodule +endmodule +task automatic updateProgramAddrLabelArray; + input string ProgramAddrMapFile, ProgramLabelMapFile; + inout integer ProgramAddrLabelArray [string]; + // Gets the memory location of begin_signature + integer ProgramLabelMapFP, ProgramAddrMapFP; + ProgramLabelMapFP = $fopen(ProgramLabelMapFile, "r"); + ProgramAddrMapFP = $fopen(ProgramAddrMapFile, "r"); + + if (ProgramLabelMapFP & ProgramAddrMapFP) begin // check we found both files + while (!$feof(ProgramLabelMapFP)) begin + string label, adrstr; + integer returncode; + returncode = $fscanf(ProgramLabelMapFP, "%s\n", label); + returncode = $fscanf(ProgramAddrMapFP, "%s\n", adrstr); + if (ProgramAddrLabelArray.exists(label)) + ProgramAddrLabelArray[label] = adrstr.atohex(); + end + end + $fclose(ProgramLabelMapFP); + $fclose(ProgramAddrMapFP); +endtask \ No newline at end of file diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index f01d849b1..8087b80fb 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -33,7 +33,7 @@ string tvpaths[] = '{ "../../addins/imperas-riscv-tests/work/", - "../../addins/riscv-arch-test/work/", + "../../tests/riscof/work/", "../../tests/wally-riscv-arch-test/work/", "../../tests/imperas-riscv-tests/work/", "../../benchmarks/riscv-coremark/work/", @@ -900,573 +900,570 @@ string imperas32f[] = '{ string arch64priv[] = '{ `RISCVARCHTEST, - "rv64i_m/privilege/ebreak", - "rv64i_m/privilege/ecall", - "rv64i_m/privilege/misalign-beq-01", - "rv64i_m/privilege/misalign-bge-01", - "rv64i_m/privilege/misalign-bgeu-01", - "rv64i_m/privilege/misalign-blt-01", - "rv64i_m/privilege/misalign-bltu-01", - "rv64i_m/privilege/misalign-bne-01", - "rv64i_m/privilege/misalign-jal-01", - "rv64i_m/privilege/misalign-ld-01", - "rv64i_m/privilege/misalign-lh-01", - "rv64i_m/privilege/misalign-lhu-01", - "rv64i_m/privilege/misalign-lw-01", - "rv64i_m/privilege/misalign-lwu-01", - "rv64i_m/privilege/misalign-sd-01", - "rv64i_m/privilege/misalign-sh-01", - "rv64i_m/privilege/misalign-sw-01", - "rv64i_m/privilege/misalign1-jalr-01", - "rv64i_m/privilege/misalign2-jalr-01" + "rv64i_m/privilege/src/ebreak.S/ref/ref", + "rv64i_m/privilege/src/ecall.S/ref/ref", + "rv64i_m/privilege/src/misalign1-jalr-01.S/ref/ref", + "rv64i_m/privilege/src/misalign2-jalr-01.S/ref/ref", + "rv64i_m/privilege/src/misalign-beq-01.S/ref/ref", + "rv64i_m/privilege/src/misalign-bge-01.S/ref/ref", + "rv64i_m/privilege/src/misalign-bgeu-01.S/ref/ref", + "rv64i_m/privilege/src/misalign-blt-01.S/ref/ref", + "rv64i_m/privilege/src/misalign-bltu-01.S/ref/ref", + "rv64i_m/privilege/src/misalign-bne-01.S/ref/ref", + "rv64i_m/privilege/src/misalign-jal-01.S/ref/ref", + "rv64i_m/privilege/src/misalign-ld-01.S/ref/ref", + "rv64i_m/privilege/src/misalign-lh-01.S/ref/ref", + "rv64i_m/privilege/src/misalign-lhu-01.S/ref/ref", + "rv64i_m/privilege/src/misalign-lw-01.S/ref/ref", + "rv64i_m/privilege/src/misalign-lwu-01.S/ref/ref", + "rv64i_m/privilege/src/misalign-sd-01.S/ref/ref", + "rv64i_m/privilege/src/misalign-sh-01.S/ref/ref", + "rv64i_m/privilege/src/misalign-sw-01.S/ref/ref" }; string arch64m[] = '{ `RISCVARCHTEST, - "rv64i_m/M/div-01", - "rv64i_m/M/divu-01", - "rv64i_m/M/divuw-01", - "rv64i_m/M/divw-01", - "rv64i_m/M/mul-01", - "rv64i_m/M/mulh-01", - "rv64i_m/M/mulhsu-01", - "rv64i_m/M/mulhu-01", - "rv64i_m/M/mulw-01", - "rv64i_m/M/rem-01", - "rv64i_m/M/remu-01", - "rv64i_m/M/remuw-01", - "rv64i_m/M/remw-01" + "rv64i_m/M/src/div-01.S/ref/ref", + "rv64i_m/M/src/divu-01.S/ref/ref", + "rv64i_m/M/src/divuw-01.S/ref/ref", + "rv64i_m/M/src/divw-01.S/ref/ref", + "rv64i_m/M/src/mul-01.S/ref/ref", + "rv64i_m/M/src/mulh-01.S/ref/ref", + "rv64i_m/M/src/mulhsu-01.S/ref/ref", + "rv64i_m/M/src/mulhu-01.S/ref/ref", + "rv64i_m/M/src/mulw-01.S/ref/ref", + "rv64i_m/M/src/rem-01.S/ref/ref", + "rv64i_m/M/src/remu-01.S/ref/ref", + "rv64i_m/M/src/remuw-01.S/ref/ref", + "rv64i_m/M/src/remw-01.S/ref/ref" }; string arch64c[] = '{ `RISCVARCHTEST, - "rv64i_m/C/cadd-01", - "rv64i_m/C/caddi-01", - "rv64i_m/C/caddi16sp-01", - "rv64i_m/C/caddi4spn-01", - "rv64i_m/C/caddiw-01", - "rv64i_m/C/caddw-01", - "rv64i_m/C/cand-01", - "rv64i_m/C/candi-01", - "rv64i_m/C/cbeqz-01", - "rv64i_m/C/cbnez-01", - "rv64i_m/C/cj-01", - "rv64i_m/C/cjalr-01", - "rv64i_m/C/cjr-01", - "rv64i_m/C/cld-01", - "rv64i_m/C/cldsp-01", - "rv64i_m/C/cli-01", - "rv64i_m/C/clui-01", - "rv64i_m/C/clw-01", - "rv64i_m/C/clwsp-01", - "rv64i_m/C/cmv-01", - "rv64i_m/C/cnop-01", - "rv64i_m/C/cor-01", - "rv64i_m/C/csd-01", - "rv64i_m/C/csdsp-01", - "rv64i_m/C/cslli-01", - "rv64i_m/C/csrai-01", - "rv64i_m/C/csrli-01", - "rv64i_m/C/csub-01", - "rv64i_m/C/csubw-01", - "rv64i_m/C/csw-01", - "rv64i_m/C/cswsp-01", - "rv64i_m/C/cxor-01" + "rv64i_m/C/src/cadd-01.S/ref/ref", + "rv64i_m/C/src/caddi-01.S/ref/ref", + "rv64i_m/C/src/caddi16sp-01.S/ref/ref", + "rv64i_m/C/src/caddi4spn-01.S/ref/ref", + "rv64i_m/C/src/caddiw-01.S/ref/ref", + "rv64i_m/C/src/caddw-01.S/ref/ref", + "rv64i_m/C/src/cand-01.S/ref/ref", + "rv64i_m/C/src/candi-01.S/ref/ref", + "rv64i_m/C/src/cbeqz-01.S/ref/ref", + "rv64i_m/C/src/cbnez-01.S/ref/ref", + "rv64i_m/C/src/cj-01.S/ref/ref", + "rv64i_m/C/src/cjalr-01.S/ref/ref", + "rv64i_m/C/src/cjr-01.S/ref/ref", + "rv64i_m/C/src/cld-01.S/ref/ref", + "rv64i_m/C/src/cldsp-01.S/ref/ref", + "rv64i_m/C/src/cli-01.S/ref/ref", + "rv64i_m/C/src/clui-01.S/ref/ref", + "rv64i_m/C/src/clw-01.S/ref/ref", + "rv64i_m/C/src/clwsp-01.S/ref/ref", + "rv64i_m/C/src/cmv-01.S/ref/ref", + "rv64i_m/C/src/cnop-01.S/ref/ref", + "rv64i_m/C/src/cor-01.S/ref/ref", + "rv64i_m/C/src/csd-01.S/ref/ref", + "rv64i_m/C/src/csdsp-01.S/ref/ref", + "rv64i_m/C/src/cslli-01.S/ref/ref", + "rv64i_m/C/src/csrai-01.S/ref/ref", + "rv64i_m/C/src/csrli-01.S/ref/ref", + "rv64i_m/C/src/csub-01.S/ref/ref", + "rv64i_m/C/src/csubw-01.S/ref/ref", + "rv64i_m/C/src/csw-01.S/ref/ref", + "rv64i_m/C/src/cswsp-01.S/ref/ref", + "rv64i_m/C/src/cxor-01.S/ref/ref" }; string arch64cpriv[] = '{ // `RISCVARCHTEST, - "rv64i_m/C/cebreak-01" + "rv64i_m/C/src/cebreak-01.S/ref/ref" }; string arch64i[] = '{ `RISCVARCHTEST, - "rv64i_m/I/add-01", - "rv64i_m/I/addi-01", - "rv64i_m/I/addiw-01", - "rv64i_m/I/addw-01", - "rv64i_m/I/and-01", - "rv64i_m/I/andi-01", - "rv64i_m/I/auipc-01", - "rv64i_m/I/beq-01", - "rv64i_m/I/bge-01", - "rv64i_m/I/bgeu-01", - "rv64i_m/I/blt-01", - "rv64i_m/I/bltu-01", - "rv64i_m/I/bne-01", - "rv64i_m/I/fence-01", - "rv64i_m/I/jal-01", - "rv64i_m/I/jalr-01", - "rv64i_m/I/lb-align-01", - "rv64i_m/I/lbu-align-01", - "rv64i_m/I/ld-align-01", - "rv64i_m/I/lh-align-01", - "rv64i_m/I/lhu-align-01", - "rv64i_m/I/lui-01", - "rv64i_m/I/lw-align-01", - "rv64i_m/I/lwu-align-01", - "rv64i_m/I/or-01", - "rv64i_m/I/ori-01", - "rv64i_m/I/sb-align-01", - "rv64i_m/I/sd-align-01", - "rv64i_m/I/sh-align-01", - "rv64i_m/I/sll-01", - "rv64i_m/I/slli-01", - "rv64i_m/I/slliw-01", - "rv64i_m/I/sllw-01", - "rv64i_m/I/slt-01", - "rv64i_m/I/slti-01", - "rv64i_m/I/sltiu-01", - "rv64i_m/I/sltu-01", - "rv64i_m/I/sra-01", - "rv64i_m/I/srai-01", - "rv64i_m/I/sraiw-01", - "rv64i_m/I/sraw-01", - "rv64i_m/I/srl-01", - "rv64i_m/I/srli-01", - "rv64i_m/I/srliw-01", - "rv64i_m/I/srlw-01", - "rv64i_m/I/sub-01", - "rv64i_m/I/subw-01", - "rv64i_m/I/sw-align-01", - "rv64i_m/I/xor-01", - "rv64i_m/I/xori-01" + "rv64i_m/I/src/add-01.S/ref/ref", + "rv64i_m/I/src/addi-01.S/ref/ref", + "rv64i_m/I/src/addiw-01.S/ref/ref", + "rv64i_m/I/src/addw-01.S/ref/ref", + "rv64i_m/I/src/and-01.S/ref/ref", + "rv64i_m/I/src/andi-01.S/ref/ref", + "rv64i_m/I/src/auipc-01.S/ref/ref", + "rv64i_m/I/src/beq-01.S/ref/ref", + "rv64i_m/I/src/bge-01.S/ref/ref", + "rv64i_m/I/src/bgeu-01.S/ref/ref", + "rv64i_m/I/src/blt-01.S/ref/ref", + "rv64i_m/I/src/bltu-01.S/ref/ref", + "rv64i_m/I/src/bne-01.S/ref/ref", + "rv64i_m/I/src/fence-01.S/ref/ref", + "rv64i_m/I/src/jal-01.S/ref/ref", + "rv64i_m/I/src/jalr-01.S/ref/ref", + "rv64i_m/I/src/lb-align-01.S/ref/ref", + "rv64i_m/I/src/lbu-align-01.S/ref/ref", + "rv64i_m/I/src/ld-align-01.S/ref/ref", + "rv64i_m/I/src/lh-align-01.S/ref/ref", + "rv64i_m/I/src/lhu-align-01.S/ref/ref", + "rv64i_m/I/src/lui-01.S/ref/ref", + "rv64i_m/I/src/lw-align-01.S/ref/ref", + "rv64i_m/I/src/lwu-align-01.S/ref/ref", + "rv64i_m/I/src/or-01.S/ref/ref", + "rv64i_m/I/src/ori-01.S/ref/ref", + "rv64i_m/I/src/sb-align-01.S/ref/ref", + "rv64i_m/I/src/sd-align-01.S/ref/ref", + "rv64i_m/I/src/sh-align-01.S/ref/ref", + "rv64i_m/I/src/sll-01.S/ref/ref", + "rv64i_m/I/src/slli-01.S/ref/ref", + "rv64i_m/I/src/slliw-01.S/ref/ref", + "rv64i_m/I/src/sllw-01.S/ref/ref", + "rv64i_m/I/src/slt-01.S/ref/ref", + "rv64i_m/I/src/slti-01.S/ref/ref", + "rv64i_m/I/src/sltiu-01.S/ref/ref", + "rv64i_m/I/src/sltu-01.S/ref/ref", + "rv64i_m/I/src/sra-01.S/ref/ref", + "rv64i_m/I/src/srai-01.S/ref/ref", + "rv64i_m/I/src/sraiw-01.S/ref/ref", + "rv64i_m/I/src/sraw-01.S/ref/ref", + "rv64i_m/I/src/srl-01.S/ref/ref", + "rv64i_m/I/src/srli-01.S/ref/ref", + "rv64i_m/I/src/srliw-01.S/ref/ref", + "rv64i_m/I/src/srlw-01.S/ref/ref", + "rv64i_m/I/src/sub-01.S/ref/ref", + "rv64i_m/I/src/subw-01.S/ref/ref", + "rv64i_m/I/src/sw-align-01.S/ref/ref", + "rv64i_m/I/src/xor-01.S/ref/ref", + "rv64i_m/I/src/xori-01.S/ref/ref" }; - string arch64d[] = '{ `RISCVARCHTEST, - "rv64i_m/D/d_fadd_b10-01", - "rv64i_m/D/d_fadd_b1-01", - "rv64i_m/D/d_fadd_b11-01", - "rv64i_m/D/d_fadd_b12-01", - "rv64i_m/D/d_fadd_b13-01", - "rv64i_m/D/d_fadd_b2-01", - "rv64i_m/D/d_fadd_b3-01", - "rv64i_m/D/d_fadd_b4-01", - "rv64i_m/D/d_fadd_b5-01", - "rv64i_m/D/d_fadd_b7-01", - "rv64i_m/D/d_fadd_b8-01", - "rv64i_m/D/d_fclass_b1-01", - "rv64i_m/D/d_fcvt.d.l_b25-01", - "rv64i_m/D/d_fcvt.d.l_b26-01", - "rv64i_m/D/d_fcvt.d.lu_b25-01", - "rv64i_m/D/d_fcvt.d.lu_b26-01", - "rv64i_m/D/d_fcvt.d.s_b1-01", - "rv64i_m/D/d_fcvt.d.s_b22-01", - "rv64i_m/D/d_fcvt.d.s_b23-01", - "rv64i_m/D/d_fcvt.d.s_b24-01", - "rv64i_m/D/d_fcvt.d.s_b27-01", - "rv64i_m/D/d_fcvt.d.s_b28-01", - "rv64i_m/D/d_fcvt.d.s_b29-01", - "rv64i_m/D/d_fcvt.d.w_b25-01", - "rv64i_m/D/d_fcvt.d.w_b26-01", - "rv64i_m/D/d_fcvt.d.wu_b25-01", - "rv64i_m/D/d_fcvt.d.wu_b26-01", - "rv64i_m/D/d_fcvt.l.d_b1-01", - "rv64i_m/D/d_fcvt.l.d_b22-01", - "rv64i_m/D/d_fcvt.l.d_b23-01", - "rv64i_m/D/d_fcvt.l.d_b24-01", - "rv64i_m/D/d_fcvt.l.d_b27-01", - "rv64i_m/D/d_fcvt.l.d_b28-01", - "rv64i_m/D/d_fcvt.l.d_b29-01", - "rv64i_m/D/d_fcvt.lu.d_b1-01", - "rv64i_m/D/d_fcvt.lu.d_b22-01", - "rv64i_m/D/d_fcvt.lu.d_b23-01", - "rv64i_m/D/d_fcvt.lu.d_b24-01", - "rv64i_m/D/d_fcvt.lu.d_b27-01", - "rv64i_m/D/d_fcvt.lu.d_b28-01", - "rv64i_m/D/d_fcvt.lu.d_b29-01", - "rv64i_m/D/d_fcvt.s.d_b1-01", - "rv64i_m/D/d_fcvt.s.d_b22-01", - "rv64i_m/D/d_fcvt.s.d_b23-01", - "rv64i_m/D/d_fcvt.s.d_b24-01", - "rv64i_m/D/d_fcvt.s.d_b27-01", - "rv64i_m/D/d_fcvt.s.d_b28-01", - "rv64i_m/D/d_fcvt.s.d_b29-01", - "rv64i_m/D/d_fcvt.w.d_b1-01", - "rv64i_m/D/d_fcvt.w.d_b22-01", - "rv64i_m/D/d_fcvt.w.d_b23-01", - "rv64i_m/D/d_fcvt.w.d_b24-01", - "rv64i_m/D/d_fcvt.w.d_b27-01", - "rv64i_m/D/d_fcvt.w.d_b28-01", - "rv64i_m/D/d_fcvt.w.d_b29-01", - "rv64i_m/D/d_fcvt.wu.d_b1-01", - "rv64i_m/D/d_fcvt.wu.d_b22-01", - "rv64i_m/D/d_fcvt.wu.d_b23-01", - "rv64i_m/D/d_fcvt.wu.d_b24-01", - "rv64i_m/D/d_fcvt.wu.d_b27-01", - "rv64i_m/D/d_fcvt.wu.d_b28-01", - "rv64i_m/D/d_fcvt.wu.d_b29-01", - // "rv64i_m/D/d_fdiv_b1-01", // RV NaNs need to be positive - // "rv64i_m/D/d_fdiv_b20-01", // looks like flags - // "rv64i_m/D/d_fdiv_b2-01", // also flags - // "rv64i_m/D/d_fdiv_b21-01", // positive NaNs again - // "rv64i_m/D/d_fdiv_b3-01", - // "rv64i_m/D/d_fdiv_b4-01", // flags - // "rv64i_m/D/d_fdiv_b5-01", - // "rv64i_m/D/d_fdiv_b6-01", // flags - // "rv64i_m/D/d_fdiv_b7-01", - // "rv64i_m/D/d_fdiv_b8-01", // flags - // "rv64i_m/D/d_fdiv_b9-01", might be a flag too - "rv64i_m/D/d_feq_b1-01", - "rv64i_m/D/d_feq_b19-01", - "rv64i_m/D/d_fld-align-01", - "rv64i_m/D/d_fle_b1-01", - "rv64i_m/D/d_fle_b19-01", - "rv64i_m/D/d_flt_b1-01", - "rv64i_m/D/d_flt_b19-01", - "rv64i_m/D/d_fmadd_b14-01", - "rv64i_m/D/d_fmadd_b16-01", - "rv64i_m/D/d_fmadd_b17-01", - "rv64i_m/D/d_fmadd_b18-01", - "rv64i_m/D/d_fmadd_b2-01", - "rv64i_m/D/d_fmadd_b3-01", - "rv64i_m/D/d_fmadd_b4-01", - "rv64i_m/D/d_fmadd_b5-01", - "rv64i_m/D/d_fmadd_b6-01", - "rv64i_m/D/d_fmadd_b7-01", - "rv64i_m/D/d_fmadd_b8-01", - "rv64i_m/D/d_fmax_b1-01", - "rv64i_m/D/d_fmax_b19-01", - "rv64i_m/D/d_fmin_b1-01", - "rv64i_m/D/d_fmin_b19-01", - "rv64i_m/D/d_fmsub_b14-01", - "rv64i_m/D/d_fmsub_b16-01", - "rv64i_m/D/d_fmsub_b17-01", - "rv64i_m/D/d_fmsub_b18-01", - "rv64i_m/D/d_fmsub_b2-01", - "rv64i_m/D/d_fmsub_b3-01", - "rv64i_m/D/d_fmsub_b4-01", - "rv64i_m/D/d_fmsub_b5-01", - "rv64i_m/D/d_fmsub_b6-01", - "rv64i_m/D/d_fmsub_b7-01", - "rv64i_m/D/d_fmsub_b8-01", - "rv64i_m/D/d_fmul_b1-01", - "rv64i_m/D/d_fmul_b2-01", - "rv64i_m/D/d_fmul_b3-01", - "rv64i_m/D/d_fmul_b4-01", - "rv64i_m/D/d_fmul_b5-01", - "rv64i_m/D/d_fmul_b6-01", - "rv64i_m/D/d_fmul_b7-01", - "rv64i_m/D/d_fmul_b8-01", - "rv64i_m/D/d_fmul_b9-01", - "rv64i_m/D/d_fmv.d.x_b25-01", - "rv64i_m/D/d_fmv.d.x_b26-01", - "rv64i_m/D/d_fmv.x.d_b1-01", - "rv64i_m/D/d_fmv.x.d_b22-01", - "rv64i_m/D/d_fmv.x.d_b23-01", - "rv64i_m/D/d_fmv.x.d_b24-01", - "rv64i_m/D/d_fmv.x.d_b27-01", - "rv64i_m/D/d_fmv.x.d_b28-01", - "rv64i_m/D/d_fmv.x.d_b29-01", - "rv64i_m/D/d_fnmadd_b14-01", - "rv64i_m/D/d_fnmadd_b16-01", - "rv64i_m/D/d_fnmadd_b17-01", - "rv64i_m/D/d_fnmadd_b18-01", - "rv64i_m/D/d_fnmadd_b2-01", - "rv64i_m/D/d_fnmadd_b3-01", - "rv64i_m/D/d_fnmadd_b4-01", - "rv64i_m/D/d_fnmadd_b5-01", - "rv64i_m/D/d_fnmadd_b6-01", - "rv64i_m/D/d_fnmadd_b7-01", - "rv64i_m/D/d_fnmadd_b8-01", - "rv64i_m/D/d_fnmsub_b14-01", - "rv64i_m/D/d_fnmsub_b16-01", - "rv64i_m/D/d_fnmsub_b17-01", - "rv64i_m/D/d_fnmsub_b18-01", - "rv64i_m/D/d_fnmsub_b2-01", - "rv64i_m/D/d_fnmsub_b3-01", - "rv64i_m/D/d_fnmsub_b4-01", - "rv64i_m/D/d_fnmsub_b5-01", - "rv64i_m/D/d_fnmsub_b6-01", - "rv64i_m/D/d_fnmsub_b7-01", - "rv64i_m/D/d_fnmsub_b8-01", - "rv64i_m/D/d_fsd-align-01", - "rv64i_m/D/d_fsgnj_b1-01", - "rv64i_m/D/d_fsgnjn_b1-01", - "rv64i_m/D/d_fsgnjx_b1-01", - // "rv64i_m/D/d_fsqrt_b1-01", // flg - // "rv64i_m/D/d_fsqrt_b20-01", // flg - // "rv64i_m/D/d_fsqrt_b2-01", // flg - I'm going to stop here with the sqrt - // "rv64i_m/D/d_fsqrt_b3-01", - // "rv64i_m/D/d_fsqrt_b4-01", - // "rv64i_m/D/d_fsqrt_b5-01", - // "rv64i_m/D/d_fsqrt_b7-01", - // "rv64i_m/D/d_fsqrt_b8-01", - // "rv64i_m/D/d_fsqrt_b9-01", - "rv64i_m/D/d_fsub_b10-01", - "rv64i_m/D/d_fsub_b1-01", - "rv64i_m/D/d_fsub_b11-01", - "rv64i_m/D/d_fsub_b12-01", - "rv64i_m/D/d_fsub_b13-01", - "rv64i_m/D/d_fsub_b2-01", - "rv64i_m/D/d_fsub_b3-01", - "rv64i_m/D/d_fsub_b4-01", - "rv64i_m/D/d_fsub_b5-01", - "rv64i_m/D/d_fsub_b7-01", - "rv64i_m/D/d_fsub_b8-01" - }; + "rv64i_m/D/src/d_fadd_b10-01.S/ref/ref", + "rv64i_m/D/src/d_fadd_b1-01.S/ref/ref", + "rv64i_m/D/src/d_fadd_b11-01.S/ref/ref", + "rv64i_m/D/src/d_fadd_b12-01.S/ref/ref", + "rv64i_m/D/src/d_fadd_b13-01.S/ref/ref", + "rv64i_m/D/src/d_fadd_b2-01.S/ref/ref", + "rv64i_m/D/src/d_fadd_b3-01.S/ref/ref", + "rv64i_m/D/src/d_fadd_b4-01.S/ref/ref", + "rv64i_m/D/src/d_fadd_b5-01.S/ref/ref", + "rv64i_m/D/src/d_fadd_b7-01.S/ref/ref", + "rv64i_m/D/src/d_fadd_b8-01.S/ref/ref", + "rv64i_m/D/src/d_fclass_b1-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.d.l_b25-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.d.l_b26-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.d.lu_b25-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.d.lu_b26-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.d.s_b1-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.d.s_b22-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.d.s_b23-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.d.s_b24-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.d.s_b27-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.d.s_b28-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.d.s_b29-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.d.w_b25-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.d.w_b26-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.d.wu_b25-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.d.wu_b26-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.l.d_b1-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.l.d_b22-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.l.d_b23-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.l.d_b24-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.l.d_b27-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.l.d_b28-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.l.d_b29-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.lu.d_b1-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.lu.d_b22-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.lu.d_b23-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.lu.d_b24-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.lu.d_b27-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.lu.d_b28-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.lu.d_b29-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.s.d_b1-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.s.d_b22-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.s.d_b23-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.s.d_b24-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.s.d_b27-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.s.d_b28-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.s.d_b29-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.w.d_b1-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.w.d_b22-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.w.d_b23-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.w.d_b24-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.w.d_b27-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.w.d_b28-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.w.d_b29-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.wu.d_b1-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.wu.d_b22-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.wu.d_b23-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.wu.d_b24-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.wu.d_b27-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.wu.d_b28-01.S/ref/ref", + "rv64i_m/D/src/d_fcvt.wu.d_b29-01.S/ref/ref", + // "rv64i_m/D/src/d_fdiv_b1-01.S/ref/ref", + // "rv64i_m/D/src/d_fdiv_b20-01.S/ref/ref", + // "rv64i_m/D/src/d_fdiv_b2-01.S/ref/ref", + // "rv64i_m/D/src/d_fdiv_b21-01.S/ref/ref", + // "rv64i_m/D/src/d_fdiv_b3-01.S/ref/ref", + // "rv64i_m/D/src/d_fdiv_b4-01.S/ref/ref", + // "rv64i_m/D/src/d_fdiv_b5-01.S/ref/ref", + // "rv64i_m/D/src/d_fdiv_b6-01.S/ref/ref", + // "rv64i_m/D/src/d_fdiv_b7-01.S/ref/ref", + // "rv64i_m/D/src/d_fdiv_b8-01.S/ref/ref", + // "rv64i_m/D/src/d_fdiv_b9-01.S/ref/ref", + "rv64i_m/D/src/d_feq_b1-01.S/ref/ref", + "rv64i_m/D/src/d_feq_b19-01.S/ref/ref", + "rv64i_m/D/src/d_fle_b1-01.S/ref/ref", + "rv64i_m/D/src/d_fle_b19-01.S/ref/ref", + "rv64i_m/D/src/d_flt_b1-01.S/ref/ref", + "rv64i_m/D/src/d_flt_b19-01.S/ref/ref", + "rv64i_m/D/src/d_fmadd_b14-01.S/ref/ref", + "rv64i_m/D/src/d_fmadd_b16-01.S/ref/ref", + "rv64i_m/D/src/d_fmadd_b17-01.S/ref/ref", + "rv64i_m/D/src/d_fmadd_b18-01.S/ref/ref", + "rv64i_m/D/src/d_fmadd_b2-01.S/ref/ref", + "rv64i_m/D/src/d_fmadd_b3-01.S/ref/ref", + "rv64i_m/D/src/d_fmadd_b4-01.S/ref/ref", + "rv64i_m/D/src/d_fmadd_b5-01.S/ref/ref", + "rv64i_m/D/src/d_fmadd_b6-01.S/ref/ref", + "rv64i_m/D/src/d_fmadd_b7-01.S/ref/ref", + "rv64i_m/D/src/d_fmadd_b8-01.S/ref/ref", + "rv64i_m/D/src/d_fmax_b1-01.S/ref/ref", + "rv64i_m/D/src/d_fmax_b19-01.S/ref/ref", + "rv64i_m/D/src/d_fmin_b1-01.S/ref/ref", + "rv64i_m/D/src/d_fmin_b19-01.S/ref/ref", + "rv64i_m/D/src/d_fmsub_b14-01.S/ref/ref", + "rv64i_m/D/src/d_fmsub_b16-01.S/ref/ref", + "rv64i_m/D/src/d_fmsub_b17-01.S/ref/ref", + "rv64i_m/D/src/d_fmsub_b18-01.S/ref/ref", + "rv64i_m/D/src/d_fmsub_b2-01.S/ref/ref", + "rv64i_m/D/src/d_fmsub_b3-01.S/ref/ref", + "rv64i_m/D/src/d_fmsub_b4-01.S/ref/ref", + "rv64i_m/D/src/d_fmsub_b5-01.S/ref/ref", + "rv64i_m/D/src/d_fmsub_b6-01.S/ref/ref", + "rv64i_m/D/src/d_fmsub_b7-01.S/ref/ref", + "rv64i_m/D/src/d_fmsub_b8-01.S/ref/ref", + "rv64i_m/D/src/d_fmul_b1-01.S/ref/ref", + "rv64i_m/D/src/d_fmul_b2-01.S/ref/ref", + "rv64i_m/D/src/d_fmul_b3-01.S/ref/ref", + "rv64i_m/D/src/d_fmul_b4-01.S/ref/ref", + "rv64i_m/D/src/d_fmul_b5-01.S/ref/ref", + "rv64i_m/D/src/d_fmul_b6-01.S/ref/ref", + "rv64i_m/D/src/d_fmul_b7-01.S/ref/ref", + "rv64i_m/D/src/d_fmul_b8-01.S/ref/ref", + "rv64i_m/D/src/d_fmul_b9-01.S/ref/ref", + "rv64i_m/D/src/d_fmv.d.x_b25-01.S/ref/ref", + "rv64i_m/D/src/d_fmv.d.x_b26-01.S/ref/ref", + "rv64i_m/D/src/d_fmv.x.d_b1-01.S/ref/ref", + "rv64i_m/D/src/d_fmv.x.d_b22-01.S/ref/ref", + "rv64i_m/D/src/d_fmv.x.d_b23-01.S/ref/ref", + "rv64i_m/D/src/d_fmv.x.d_b24-01.S/ref/ref", + "rv64i_m/D/src/d_fmv.x.d_b27-01.S/ref/ref", + "rv64i_m/D/src/d_fmv.x.d_b28-01.S/ref/ref", + "rv64i_m/D/src/d_fmv.x.d_b29-01.S/ref/ref", + "rv64i_m/D/src/d_fnmadd_b14-01.S/ref/ref", + "rv64i_m/D/src/d_fnmadd_b16-01.S/ref/ref", + "rv64i_m/D/src/d_fnmadd_b17-01.S/ref/ref", + "rv64i_m/D/src/d_fnmadd_b18-01.S/ref/ref", + "rv64i_m/D/src/d_fnmadd_b2-01.S/ref/ref", + "rv64i_m/D/src/d_fnmadd_b3-01.S/ref/ref", + "rv64i_m/D/src/d_fnmadd_b4-01.S/ref/ref", + "rv64i_m/D/src/d_fnmadd_b5-01.S/ref/ref", + "rv64i_m/D/src/d_fnmadd_b6-01.S/ref/ref", + "rv64i_m/D/src/d_fnmadd_b7-01.S/ref/ref", + "rv64i_m/D/src/d_fnmadd_b8-01.S/ref/ref", + "rv64i_m/D/src/d_fnmsub_b14-01.S/ref/ref", + "rv64i_m/D/src/d_fnmsub_b16-01.S/ref/ref", + "rv64i_m/D/src/d_fnmsub_b17-01.S/ref/ref", + "rv64i_m/D/src/d_fnmsub_b18-01.S/ref/ref", + "rv64i_m/D/src/d_fnmsub_b2-01.S/ref/ref", + "rv64i_m/D/src/d_fnmsub_b3-01.S/ref/ref", + "rv64i_m/D/src/d_fnmsub_b4-01.S/ref/ref", + "rv64i_m/D/src/d_fnmsub_b5-01.S/ref/ref", + "rv64i_m/D/src/d_fnmsub_b6-01.S/ref/ref", + "rv64i_m/D/src/d_fnmsub_b7-01.S/ref/ref", + "rv64i_m/D/src/d_fnmsub_b8-01.S/ref/ref", + "rv64i_m/D/src/d_fsgnj_b1-01.S/ref/ref", + "rv64i_m/D/src/d_fsgnjn_b1-01.S/ref/ref", + "rv64i_m/D/src/d_fsgnjx_b1-01.S/ref/ref", + // "rv64i_m/D/src/d_fsqrt_b1-01.S/ref/ref", + // "rv64i_m/D/src/d_fsqrt_b20-01.S/ref/ref", + // "rv64i_m/D/src/d_fsqrt_b2-01.S/ref/ref", + // "rv64i_m/D/src/d_fsqrt_b3-01.S/ref/ref", + // "rv64i_m/D/src/d_fsqrt_b4-01.S/ref/ref", + // "rv64i_m/D/src/d_fsqrt_b5-01.S/ref/ref", + // "rv64i_m/D/src/d_fsqrt_b7-01.S/ref/ref", + // "rv64i_m/D/src/d_fsqrt_b8-01.S/ref/ref", + // "rv64i_m/D/src/d_fsqrt_b9-01.S/ref/ref", + "rv64i_m/D/src/d_fsub_b10-01.S/ref/ref", + "rv64i_m/D/src/d_fsub_b1-01.S/ref/ref", + "rv64i_m/D/src/d_fsub_b11-01.S/ref/ref", + "rv64i_m/D/src/d_fsub_b12-01.S/ref/ref", + "rv64i_m/D/src/d_fsub_b13-01.S/ref/ref", + "rv64i_m/D/src/d_fsub_b2-01.S/ref/ref", + "rv64i_m/D/src/d_fsub_b3-01.S/ref/ref", + "rv64i_m/D/src/d_fsub_b4-01.S/ref/ref", + "rv64i_m/D/src/d_fsub_b5-01.S/ref/ref", + "rv64i_m/D/src/d_fsub_b7-01.S/ref/ref", + "rv64i_m/D/src/d_fsub_b8-01.S/ref/ref" +}; string arch32priv[] = '{ `RISCVARCHTEST, - "rv32i_m/privilege/ebreak", - "rv32i_m/privilege/ecall", - "rv32i_m/privilege/misalign-beq-01", - "rv32i_m/privilege/misalign-bge-01", - "rv32i_m/privilege/misalign-bgeu-01", - "rv32i_m/privilege/misalign-blt-01", - "rv32i_m/privilege/misalign-bltu-01", - "rv32i_m/privilege/misalign-bne-01", - "rv32i_m/privilege/misalign-jal-01", - "rv32i_m/privilege/misalign-lh-01", - "rv32i_m/privilege/misalign-lhu-01", - "rv32i_m/privilege/misalign-lw-01", - "rv32i_m/privilege/misalign-sh-01", - "rv32i_m/privilege/misalign-sw-01", - "rv32i_m/privilege/misalign1-jalr-01", - "rv32i_m/privilege/misalign2-jalr-01" + "rv32i_m/privilege/src/ebreak.S/ref/ref", + "rv32i_m/privilege/src/ecall.S/ref/ref", + "rv32i_m/privilege/src/misalign1-jalr-01.S/ref/ref", + "rv32i_m/privilege/src/misalign2-jalr-01.S/ref/ref", + "rv32i_m/privilege/src/misalign-beq-01.S/ref/ref", + "rv32i_m/privilege/src/misalign-bge-01.S/ref/ref", + "rv32i_m/privilege/src/misalign-bgeu-01.S/ref/ref", + "rv32i_m/privilege/src/misalign-blt-01.S/ref/ref", + "rv32i_m/privilege/src/misalign-bltu-01.S/ref/ref", + "rv32i_m/privilege/src/misalign-bne-01.S/ref/ref", + "rv32i_m/privilege/src/misalign-jal-01.S/ref/ref", + "rv32i_m/privilege/src/misalign-lh-01.S/ref/ref", + "rv32i_m/privilege/src/misalign-lhu-01.S/ref/ref", + "rv32i_m/privilege/src/misalign-lw-01.S/ref/ref", + "rv32i_m/privilege/src/misalign-sh-01.S/ref/ref", + "rv32i_m/privilege/src/misalign-sw-01.S/ref/ref" }; string arch32m[] = '{ `RISCVARCHTEST, - "rv32i_m/M/div-01", - "rv32i_m/M/divu-01", - "rv32i_m/M/mul-01", - "rv32i_m/M/mulh-01", - "rv32i_m/M/mulhsu-01", - "rv32i_m/M/mulhu-01", - "rv32i_m/M/rem-01", - "rv32i_m/M/remu-01" + "rv32i_m/M/src/div-01.S/ref/ref", + "rv32i_m/M/src/divu-01.S/ref/ref", + "rv32i_m/M/src/mul-01.S/ref/ref", + "rv32i_m/M/src/mulh-01.S/ref/ref", + "rv32i_m/M/src/mulhsu-01.S/ref/ref", + "rv32i_m/M/src/mulhu-01.S/ref/ref", + "rv32i_m/M/src/rem-01.S/ref/ref", + "rv32i_m/M/src/remu-01.S/ref/ref" }; string arch32f[] = '{ `RISCVARCHTEST, - "rv32i_m/F/fadd_b1-01", - "rv32i_m/F/fadd_b10-01", - "rv32i_m/F/fadd_b11-01", - "rv32i_m/F/fadd_b12-01", - "rv32i_m/F/fadd_b13-01", - "rv32i_m/F/fadd_b2-01", - "rv32i_m/F/fadd_b3-01", - "rv32i_m/F/fadd_b4-01", - "rv32i_m/F/fadd_b5-01", - "rv32i_m/F/fadd_b7-01", - "rv32i_m/F/fadd_b8-01", - "rv32i_m/F/fclass_b1-01", - "rv32i_m/F/fcvt.s.w_b25-01", - "rv32i_m/F/fcvt.s.w_b26-01", - "rv32i_m/F/fcvt.s.wu_b25-01", - "rv32i_m/F/fcvt.s.wu_b26-01", - "rv32i_m/F/fcvt.w.s_b1-01", - "rv32i_m/F/fcvt.w.s_b22-01", - "rv32i_m/F/fcvt.w.s_b23-01", - "rv32i_m/F/fcvt.w.s_b24-01", - "rv32i_m/F/fcvt.w.s_b27-01", - "rv32i_m/F/fcvt.w.s_b28-01", - "rv32i_m/F/fcvt.w.s_b29-01", - "rv32i_m/F/fcvt.wu.s_b1-01", - "rv32i_m/F/fcvt.wu.s_b22-01", - "rv32i_m/F/fcvt.wu.s_b23-01", - "rv32i_m/F/fcvt.wu.s_b24-01", - "rv32i_m/F/fcvt.wu.s_b27-01", - "rv32i_m/F/fcvt.wu.s_b28-01", - "rv32i_m/F/fcvt.wu.s_b29-01", - // "rv32i_m/F/fdiv_b1-01", // NaN i'm going to skip div, probably the same problems as the double version - // "rv32i_m/F/fdiv_b2-01", - // "rv32i_m/F/fdiv_b20-01", - // "rv32i_m/F/fdiv_b21-01", - // "rv32i_m/F/fdiv_b3-01", - // "rv32i_m/F/fdiv_b4-01", - // "rv32i_m/F/fdiv_b5-01", - // "rv32i_m/F/fdiv_b6-01", - // "rv32i_m/F/fdiv_b7-01", - // "rv32i_m/F/fdiv_b8-01", - // "rv32i_m/F/fdiv_b9-01", - "rv32i_m/F/feq_b1-01", - "rv32i_m/F/feq_b19-01", - "rv32i_m/F/fle_b1-01", - "rv32i_m/F/fle_b19-01", - "rv32i_m/F/flt_b1-01", - "rv32i_m/F/flt_b19-01", - "rv32i_m/F/flw-align-01", - "rv32i_m/F/fmadd_b1-01", - "rv32i_m/F/fmadd_b14-01", -// --passes but is timeconsuming "rv32i_m/F/fmadd_b15-01", - "rv32i_m/F/fmadd_b16-01", - "rv32i_m/F/fmadd_b17-01", - "rv32i_m/F/fmadd_b18-01", - "rv32i_m/F/fmadd_b2-01", - "rv32i_m/F/fmadd_b3-01", - "rv32i_m/F/fmadd_b4-01", - "rv32i_m/F/fmadd_b5-01", - "rv32i_m/F/fmadd_b6-01", - "rv32i_m/F/fmadd_b7-01", - "rv32i_m/F/fmadd_b8-01", - "rv32i_m/F/fmax_b1-01", - "rv32i_m/F/fmax_b19-01", - "rv32i_m/F/fmin_b1-01", - "rv32i_m/F/fmin_b19-01", - "rv32i_m/F/fmsub_b1-01", - "rv32i_m/F/fmsub_b14-01", - "rv32i_m/F/fmsub_b15-01", - "rv32i_m/F/fmsub_b16-01", - "rv32i_m/F/fmsub_b17-01", - "rv32i_m/F/fmsub_b18-01", - "rv32i_m/F/fmsub_b2-01", - "rv32i_m/F/fmsub_b3-01", - "rv32i_m/F/fmsub_b4-01", - "rv32i_m/F/fmsub_b5-01", - "rv32i_m/F/fmsub_b6-01", - "rv32i_m/F/fmsub_b7-01", - "rv32i_m/F/fmsub_b8-01", - "rv32i_m/F/fmul_b1-01", - "rv32i_m/F/fmul_b2-01", - "rv32i_m/F/fmul_b3-01", - "rv32i_m/F/fmul_b4-01", - "rv32i_m/F/fmul_b5-01", - "rv32i_m/F/fmul_b6-01", - "rv32i_m/F/fmul_b7-01", - "rv32i_m/F/fmul_b8-01", - "rv32i_m/F/fmul_b9-01", - "rv32i_m/F/fmv.w.x_b25-01", - "rv32i_m/F/fmv.w.x_b26-01", - "rv32i_m/F/fmv.x.w_b1-01", - "rv32i_m/F/fmv.x.w_b22-01", - "rv32i_m/F/fmv.x.w_b23-01", - "rv32i_m/F/fmv.x.w_b24-01", - "rv32i_m/F/fmv.x.w_b27-01", - "rv32i_m/F/fmv.x.w_b28-01", - "rv32i_m/F/fmv.x.w_b29-01", - "rv32i_m/F/fnmadd_b1-01", - "rv32i_m/F/fnmadd_b14-01", -// timeconsuming "rv32i_m/F/fnmadd_b15-01", - "rv32i_m/F/fnmadd_b16-01", - "rv32i_m/F/fnmadd_b17-01", - "rv32i_m/F/fnmadd_b18-01", - "rv32i_m/F/fnmadd_b2-01", - "rv32i_m/F/fnmadd_b3-01", - "rv32i_m/F/fnmadd_b4-01", - "rv32i_m/F/fnmadd_b5-01", - "rv32i_m/F/fnmadd_b6-01", - "rv32i_m/F/fnmadd_b7-01", - "rv32i_m/F/fnmadd_b8-01", - "rv32i_m/F/fnmsub_b1-01", - "rv32i_m/F/fnmsub_b14-01", -// timeconsuming "rv32i_m/F/fnmsub_b15-01", - "rv32i_m/F/fnmsub_b16-01", - "rv32i_m/F/fnmsub_b17-01", - "rv32i_m/F/fnmsub_b18-01", - "rv32i_m/F/fnmsub_b2-01", - "rv32i_m/F/fnmsub_b3-01", - "rv32i_m/F/fnmsub_b4-01", - "rv32i_m/F/fnmsub_b5-01", - "rv32i_m/F/fnmsub_b6-01", - "rv32i_m/F/fnmsub_b7-01", - "rv32i_m/F/fnmsub_b8-01", - "rv32i_m/F/fsgnj_b1-01", - "rv32i_m/F/fsgnjn_b1-01", - "rv32i_m/F/fsgnjx_b1-01", - // "rv32i_m/F/fsqrt_b1-01", // flag i am skiping sqrt - // "rv32i_m/F/fsqrt_b2-01", - // "rv32i_m/F/fsqrt_b20-01", - // "rv32i_m/F/fsqrt_b3-01", - // "rv32i_m/F/fsqrt_b4-01", - // "rv32i_m/F/fsqrt_b5-01", - // "rv32i_m/F/fsqrt_b7-01", - // "rv32i_m/F/fsqrt_b8-01", - // "rv32i_m/F/fsqrt_b9-01", - "rv32i_m/F/fsub_b1-01", - "rv32i_m/F/fsub_b10-01", - "rv32i_m/F/fsub_b11-01", - "rv32i_m/F/fsub_b12-01", - "rv32i_m/F/fsub_b13-01", - "rv32i_m/F/fsub_b2-01", - "rv32i_m/F/fsub_b3-01", - "rv32i_m/F/fsub_b4-01", - "rv32i_m/F/fsub_b5-01", - "rv32i_m/F/fsub_b7-01", - "rv32i_m/F/fsub_b8-01", - "rv32i_m/F/fsw-align-01" -}; + "rv32i_m/F/src/fadd_b10-01.S/ref/ref", + "rv32i_m/F/src/fadd_b1-01.S/ref/ref", + "rv32i_m/F/src/fadd_b11-01.S/ref/ref", + "rv32i_m/F/src/fadd_b12-01.S/ref/ref", + "rv32i_m/F/src/fadd_b13-01.S/ref/ref", + "rv32i_m/F/src/fadd_b2-01.S/ref/ref", + "rv32i_m/F/src/fadd_b3-01.S/ref/ref", + "rv32i_m/F/src/fadd_b4-01.S/ref/ref", + "rv32i_m/F/src/fadd_b5-01.S/ref/ref", + "rv32i_m/F/src/fadd_b7-01.S/ref/ref", + "rv32i_m/F/src/fadd_b8-01.S/ref/ref", + "rv32i_m/F/src/fclass_b1-01.S/ref/ref", + "rv32i_m/F/src/fcvt.s.w_b25-01.S/ref/ref", + "rv32i_m/F/src/fcvt.s.w_b26-01.S/ref/ref", + "rv32i_m/F/src/fcvt.s.wu_b25-01.S/ref/ref", + "rv32i_m/F/src/fcvt.s.wu_b26-01.S/ref/ref", + "rv32i_m/F/src/fcvt.w.s_b1-01.S/ref/ref", + "rv32i_m/F/src/fcvt.w.s_b22-01.S/ref/ref", + "rv32i_m/F/src/fcvt.w.s_b23-01.S/ref/ref", + "rv32i_m/F/src/fcvt.w.s_b24-01.S/ref/ref", + "rv32i_m/F/src/fcvt.w.s_b27-01.S/ref/ref", + "rv32i_m/F/src/fcvt.w.s_b28-01.S/ref/ref", + "rv32i_m/F/src/fcvt.w.s_b29-01.S/ref/ref", + "rv32i_m/F/src/fcvt.wu.s_b1-01.S/ref/ref", + "rv32i_m/F/src/fcvt.wu.s_b22-01.S/ref/ref", + "rv32i_m/F/src/fcvt.wu.s_b23-01.S/ref/ref", + "rv32i_m/F/src/fcvt.wu.s_b24-01.S/ref/ref", + "rv32i_m/F/src/fcvt.wu.s_b27-01.S/ref/ref", + "rv32i_m/F/src/fcvt.wu.s_b28-01.S/ref/ref", + "rv32i_m/F/src/fcvt.wu.s_b29-01.S/ref/ref", + // "rv32i_m/F/src/fdiv_b1-01.S/ref/ref", + // "rv32i_m/F/src/fdiv_b20-01.S/ref/ref", + // "rv32i_m/F/src/fdiv_b2-01.S/ref/ref", + // "rv32i_m/F/src/fdiv_b21-01.S/ref/ref", + // "rv32i_m/F/src/fdiv_b3-01.S/ref/ref", + // "rv32i_m/F/src/fdiv_b4-01.S/ref/ref", + // "rv32i_m/F/src/fdiv_b5-01.S/ref/ref", + // "rv32i_m/F/src/fdiv_b6-01.S/ref/ref", + // "rv32i_m/F/src/fdiv_b7-01.S/ref/ref", + // "rv32i_m/F/src/fdiv_b8-01.S/ref/ref", + // "rv32i_m/F/src/fdiv_b9-01.S/ref/ref", + "rv32i_m/F/src/feq_b1-01.S/ref/ref", + "rv32i_m/F/src/feq_b19-01.S/ref/ref", + "rv32i_m/F/src/fle_b1-01.S/ref/ref", + "rv32i_m/F/src/fle_b19-01.S/ref/ref", + "rv32i_m/F/src/flt_b1-01.S/ref/ref", + "rv32i_m/F/src/flt_b19-01.S/ref/ref", + "rv32i_m/F/src/flw-align-01.S/ref/ref", + "rv32i_m/F/src/fmadd_b1-01.S/ref/ref", + "rv32i_m/F/src/fmadd_b14-01.S/ref/ref", + // "rv32i_m/F/src/fmadd_b15-01.S/ref/ref", + "rv32i_m/F/src/fmadd_b16-01.S/ref/ref", + "rv32i_m/F/src/fmadd_b17-01.S/ref/ref", + "rv32i_m/F/src/fmadd_b18-01.S/ref/ref", + "rv32i_m/F/src/fmadd_b2-01.S/ref/ref", + "rv32i_m/F/src/fmadd_b3-01.S/ref/ref", + "rv32i_m/F/src/fmadd_b4-01.S/ref/ref", + "rv32i_m/F/src/fmadd_b5-01.S/ref/ref", + "rv32i_m/F/src/fmadd_b6-01.S/ref/ref", + "rv32i_m/F/src/fmadd_b7-01.S/ref/ref", + "rv32i_m/F/src/fmadd_b8-01.S/ref/ref", + "rv32i_m/F/src/fmax_b1-01.S/ref/ref", + "rv32i_m/F/src/fmax_b19-01.S/ref/ref", + "rv32i_m/F/src/fmin_b1-01.S/ref/ref", + "rv32i_m/F/src/fmin_b19-01.S/ref/ref", + "rv32i_m/F/src/fmsub_b1-01.S/ref/ref", + "rv32i_m/F/src/fmsub_b14-01.S/ref/ref", + "rv32i_m/F/src/fmsub_b15-01.S/ref/ref", + "rv32i_m/F/src/fmsub_b16-01.S/ref/ref", + "rv32i_m/F/src/fmsub_b17-01.S/ref/ref", + "rv32i_m/F/src/fmsub_b18-01.S/ref/ref", + "rv32i_m/F/src/fmsub_b2-01.S/ref/ref", + "rv32i_m/F/src/fmsub_b3-01.S/ref/ref", + "rv32i_m/F/src/fmsub_b4-01.S/ref/ref", + "rv32i_m/F/src/fmsub_b5-01.S/ref/ref", + "rv32i_m/F/src/fmsub_b6-01.S/ref/ref", + "rv32i_m/F/src/fmsub_b7-01.S/ref/ref", + "rv32i_m/F/src/fmsub_b8-01.S/ref/ref", + "rv32i_m/F/src/fmul_b1-01.S/ref/ref", + "rv32i_m/F/src/fmul_b2-01.S/ref/ref", + "rv32i_m/F/src/fmul_b3-01.S/ref/ref", + "rv32i_m/F/src/fmul_b4-01.S/ref/ref", + "rv32i_m/F/src/fmul_b5-01.S/ref/ref", + "rv32i_m/F/src/fmul_b6-01.S/ref/ref", + "rv32i_m/F/src/fmul_b7-01.S/ref/ref", + "rv32i_m/F/src/fmul_b8-01.S/ref/ref", + "rv32i_m/F/src/fmul_b9-01.S/ref/ref", + "rv32i_m/F/src/fmv.w.x_b25-01.S/ref/ref", + "rv32i_m/F/src/fmv.w.x_b26-01.S/ref/ref", + "rv32i_m/F/src/fmv.x.w_b1-01.S/ref/ref", + "rv32i_m/F/src/fmv.x.w_b22-01.S/ref/ref", + "rv32i_m/F/src/fmv.x.w_b23-01.S/ref/ref", + "rv32i_m/F/src/fmv.x.w_b24-01.S/ref/ref", + "rv32i_m/F/src/fmv.x.w_b27-01.S/ref/ref", + "rv32i_m/F/src/fmv.x.w_b28-01.S/ref/ref", + "rv32i_m/F/src/fmv.x.w_b29-01.S/ref/ref", + "rv32i_m/F/src/fnmadd_b1-01.S/ref/ref", + "rv32i_m/F/src/fnmadd_b14-01.S/ref/ref", + // "rv32i_m/F/src/fnmadd_b15-01.S/ref/ref", + "rv32i_m/F/src/fnmadd_b16-01.S/ref/ref", + "rv32i_m/F/src/fnmadd_b17-01.S/ref/ref", + "rv32i_m/F/src/fnmadd_b18-01.S/ref/ref", + "rv32i_m/F/src/fnmadd_b2-01.S/ref/ref", + "rv32i_m/F/src/fnmadd_b3-01.S/ref/ref", + "rv32i_m/F/src/fnmadd_b4-01.S/ref/ref", + "rv32i_m/F/src/fnmadd_b5-01.S/ref/ref", + "rv32i_m/F/src/fnmadd_b6-01.S/ref/ref", + "rv32i_m/F/src/fnmadd_b7-01.S/ref/ref", + "rv32i_m/F/src/fnmadd_b8-01.S/ref/ref", + "rv32i_m/F/src/fnmsub_b1-01.S/ref/ref", + "rv32i_m/F/src/fnmsub_b14-01.S/ref/ref", + // "rv32i_m/F/src/fnmsub_b15-01.S/ref/ref", + "rv32i_m/F/src/fnmsub_b16-01.S/ref/ref", + "rv32i_m/F/src/fnmsub_b17-01.S/ref/ref", + "rv32i_m/F/src/fnmsub_b18-01.S/ref/ref", + "rv32i_m/F/src/fnmsub_b2-01.S/ref/ref", + "rv32i_m/F/src/fnmsub_b3-01.S/ref/ref", + "rv32i_m/F/src/fnmsub_b4-01.S/ref/ref", + "rv32i_m/F/src/fnmsub_b5-01.S/ref/ref", + "rv32i_m/F/src/fnmsub_b6-01.S/ref/ref", + "rv32i_m/F/src/fnmsub_b7-01.S/ref/ref", + "rv32i_m/F/src/fnmsub_b8-01.S/ref/ref", + "rv32i_m/F/src/fsgnj_b1-01.S/ref/ref", + "rv32i_m/F/src/fsgnjn_b1-01.S/ref/ref", + "rv32i_m/F/src/fsgnjx_b1-01.S/ref/ref", + // "rv32i_m/F/src/fsqrt_b1-01.S/ref/ref", + // "rv32i_m/F/src/fsqrt_b20-01.S/ref/ref", + // "rv32i_m/F/src/fsqrt_b2-01.S/ref/ref", + // "rv32i_m/F/src/fsqrt_b3-01.S/ref/ref", + // "rv32i_m/F/src/fsqrt_b4-01.S/ref/ref", + // "rv32i_m/F/src/fsqrt_b5-01.S/ref/ref", + // "rv32i_m/F/src/fsqrt_b7-01.S/ref/ref", + // "rv32i_m/F/src/fsqrt_b8-01.S/ref/ref", + // "rv32i_m/F/src/fsqrt_b9-01.S/ref/ref", + "rv32i_m/F/src/fsub_b10-01.S/ref/ref", + "rv32i_m/F/src/fsub_b1-01.S/ref/ref", + "rv32i_m/F/src/fsub_b11-01.S/ref/ref", + "rv32i_m/F/src/fsub_b12-01.S/ref/ref", + "rv32i_m/F/src/fsub_b13-01.S/ref/ref", + "rv32i_m/F/src/fsub_b2-01.S/ref/ref", + "rv32i_m/F/src/fsub_b3-01.S/ref/ref", + "rv32i_m/F/src/fsub_b4-01.S/ref/ref", + "rv32i_m/F/src/fsub_b5-01.S/ref/ref", + "rv32i_m/F/src/fsub_b7-01.S/ref/ref", + "rv32i_m/F/src/fsub_b8-01.S/ref/ref", + "rv32i_m/F/src/fsw-align-01.S/ref/ref" + }; string arch32c[] = '{ `RISCVARCHTEST, - "rv32i_m/C/cadd-01", - "rv32i_m/C/caddi-01", - "rv32i_m/C/caddi16sp-01", - "rv32i_m/C/caddi4spn-01", - "rv32i_m/C/cand-01", - "rv32i_m/C/candi-01", - "rv32i_m/C/cbeqz-01", - "rv32i_m/C/cbnez-01", - "rv32i_m/C/cj-01", - "rv32i_m/C/cjal-01", - "rv32i_m/C/cjalr-01", - "rv32i_m/C/cjr-01", - "rv32i_m/C/cli-01", - "rv32i_m/C/clui-01", - "rv32i_m/C/clw-01", - "rv32i_m/C/clwsp-01", - "rv32i_m/C/cmv-01", - "rv32i_m/C/cnop-01", - "rv32i_m/C/cor-01", - "rv32i_m/C/cslli-01", - "rv32i_m/C/csrai-01", - "rv32i_m/C/csrli-01", - "rv32i_m/C/csub-01", - "rv32i_m/C/csw-01", - "rv32i_m/C/cswsp-01", - "rv32i_m/C/cxor-01" + "rv32i_m/C/src/cadd-01.S/ref/ref", + "rv32i_m/C/src/caddi-01.S/ref/ref", + "rv32i_m/C/src/caddi16sp-01.S/ref/ref", + "rv32i_m/C/src/caddi4spn-01.S/ref/ref", + "rv32i_m/C/src/cand-01.S/ref/ref", + "rv32i_m/C/src/candi-01.S/ref/ref", + "rv32i_m/C/src/cbeqz-01.S/ref/ref", + "rv32i_m/C/src/cbnez-01.S/ref/ref", + "rv32i_m/C/src/cj-01.S/ref/ref", + "rv32i_m/C/src/cjal-01.S/ref/ref", + "rv32i_m/C/src/cjalr-01.S/ref/ref", + "rv32i_m/C/src/cjr-01.S/ref/ref", + "rv32i_m/C/src/cli-01.S/ref/ref", + "rv32i_m/C/src/clui-01.S/ref/ref", + "rv32i_m/C/src/clw-01.S/ref/ref", + "rv32i_m/C/src/clwsp-01.S/ref/ref", + "rv32i_m/C/src/cmv-01.S/ref/ref", + "rv32i_m/C/src/cnop-01.S/ref/ref", + "rv32i_m/C/src/cor-01.S/ref/ref", + "rv32i_m/C/src/cslli-01.S/ref/ref", + "rv32i_m/C/src/csrai-01.S/ref/ref", + "rv32i_m/C/src/csrli-01.S/ref/ref", + "rv32i_m/C/src/csub-01.S/ref/ref", + "rv32i_m/C/src/csw-01.S/ref/ref", + "rv32i_m/C/src/cswsp-01.S/ref/ref", + "rv32i_m/C/src/cxor-01.S/ref/ref" }; string arch32cpriv[] = '{ // `RISCVARCHTEST, - "rv32i_m/C/cebreak-01" + "rv32i_m/C/src/cebreak-01.S/ref/ref" }; string arch32i[] = '{ `RISCVARCHTEST, - "rv32i_m/I/add-01", - "rv32i_m/I/addi-01", - "rv32i_m/I/and-01", - "rv32i_m/I/andi-01", - "rv32i_m/I/auipc-01", - "rv32i_m/I/beq-01", - "rv32i_m/I/bge-01", - "rv32i_m/I/bgeu-01", - "rv32i_m/I/blt-01", - "rv32i_m/I/bltu-01", - "rv32i_m/I/bne-01", - "rv32i_m/I/fence-01", - "rv32i_m/I/jal-01", - "rv32i_m/I/jalr-01", - "rv32i_m/I/lb-align-01", - "rv32i_m/I/lbu-align-01", - "rv32i_m/I/lh-align-01", - "rv32i_m/I/lhu-align-01", - "rv32i_m/I/lui-01", - "rv32i_m/I/lw-align-01", - "rv32i_m/I/or-01", - "rv32i_m/I/ori-01", - "rv32i_m/I/sb-align-01", - "rv32i_m/I/sh-align-01", - "rv32i_m/I/sll-01", - "rv32i_m/I/slli-01", - "rv32i_m/I/slt-01", - "rv32i_m/I/slti-01", - "rv32i_m/I/sltiu-01", - "rv32i_m/I/sltu-01", - "rv32i_m/I/sra-01", - "rv32i_m/I/srai-01", - "rv32i_m/I/srl-01", - "rv32i_m/I/srli-01", - "rv32i_m/I/sub-01", - "rv32i_m/I/sw-align-01", - "rv32i_m/I/xor-01", - "rv32i_m/I/xori-01" + "rv32i_m/I/src/add-01.S/ref/ref", + "rv32i_m/I/src/addi-01.S/ref/ref", + "rv32i_m/I/src/and-01.S/ref/ref", + "rv32i_m/I/src/andi-01.S/ref/ref", + "rv32i_m/I/src/auipc-01.S/ref/ref", + "rv32i_m/I/src/beq-01.S/ref/ref", + "rv32i_m/I/src/bge-01.S/ref/ref", + "rv32i_m/I/src/bgeu-01.S/ref/ref", + "rv32i_m/I/src/blt-01.S/ref/ref", + "rv32i_m/I/src/bltu-01.S/ref/ref", + "rv32i_m/I/src/bne-01.S/ref/ref", + "rv32i_m/I/src/fence-01.S/ref/ref", + "rv32i_m/I/src/jal-01.S/ref/ref", + "rv32i_m/I/src/jalr-01.S/ref/ref", + "rv32i_m/I/src/lb-align-01.S/ref/ref", + "rv32i_m/I/src/lbu-align-01.S/ref/ref", + "rv32i_m/I/src/lh-align-01.S/ref/ref", + "rv32i_m/I/src/lhu-align-01.S/ref/ref", + "rv32i_m/I/src/lui-01.S/ref/ref", + "rv32i_m/I/src/lw-align-01.S/ref/ref", + "rv32i_m/I/src/or-01.S/ref/ref", + "rv32i_m/I/src/ori-01.S/ref/ref", + "rv32i_m/I/src/sb-align-01.S/ref/ref", + "rv32i_m/I/src/sh-align-01.S/ref/ref", + "rv32i_m/I/src/sll-01.S/ref/ref", + "rv32i_m/I/src/slli-01.S/ref/ref", + "rv32i_m/I/src/slt-01.S/ref/ref", + "rv32i_m/I/src/slti-01.S/ref/ref", + "rv32i_m/I/src/sltiu-01.S/ref/ref", + "rv32i_m/I/src/sltu-01.S/ref/ref", + "rv32i_m/I/src/sra-01.S/ref/ref", + "rv32i_m/I/src/srai-01.S/ref/ref", + "rv32i_m/I/src/srl-01.S/ref/ref", + "rv32i_m/I/src/srli-01.S/ref/ref", + "rv32i_m/I/src/sub-01.S/ref/ref", + "rv32i_m/I/src/sw-align-01.S/ref/ref", + "rv32i_m/I/src/xor-01.S/ref/ref", + "rv32i_m/I/src/xori-01.S/ref/ref" }; string wally64i[] = '{ diff --git a/tests/riscof/Makefile b/tests/riscof/Makefile index 49f762f8f..35bf228d0 100644 --- a/tests/riscof/Makefile +++ b/tests/riscof/Makefile @@ -1,18 +1,28 @@ arch_dir = ../../addins/riscv-arch-test work_dir = "./riscof_work" current_dir = $(shell pwd) +XLEN ?= 64 -all: clone memfile +all: build -clone: +build: mkdir -p $(work_dir) mkdir -p work - sed 's,{0},$(current_dir),g;s,{1},32imc,g' config.ini > config32.ini - sed 's,{0},$(current_dir),g;s,{1},64gc,g' config.ini > config64.ini - riscof run --work-dir=$(work_dir) --config=config64.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env - cp -r $(work_dir)/rv64i_m work/ - riscof run --work-dir=$(work_dir) --config=config32.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env - cp -r $(work_dir)/rv32i_m work/ + sed 's,{0},$(current_dir),g;s,{1},$(XLEN)$(if $(findstring 64,$(XLEN)),gc,imc),g' config.ini > config$(XLEN).ini + riscof run --work-dir=$(work_dir) --config=config$(XLEN).ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser --no-dut-run + mv $(work_dir)/rv$(XLEN)i_m work/ + +# buildold: +# mkdir -p $(work_dir) +# mkdir -p work +# sed 's,{0},$(current_dir),g;s,{1},32imc,g' config.ini > config32.ini +# sed 's,{0},$(current_dir),g;s,{1},64gc,g' config.ini > config64.ini +# riscof run --work-dir=$(work_dir) --config=config32.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser --no-dut-run +# mv -r $(work_dir)/rv32i_m work/ +# riscof run --work-dir=$(work_dir) --config=config64.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser --no-dut-run +# mv -r $(work_dir)/rv64i_m work/ + +# no-dut-run? do we want to run spike? # sed >> config64.ini # (cd $(arch_dir) && riscof validateyaml --config=config.ini) # (cd $(arch_dir) && riscof --verbose info arch-test --clone) @@ -20,12 +30,12 @@ clone: # sed -i 's/riscv{.}-unknown-/riscv64-unknown-/g' $(arch_dir)/spike/riscof_spike.py # sed -i 's/riscv{.}-unknown-/riscv64-unknown-/g' $(arch_dir)/sail_cSim/riscof_sail_cSim.py -memfile: - sleep 1 - find work/rv*/*/ -type f -name "*ref.elf" | while read f; do riscv64-unknown-elf-objdump -S -D "$$f" > "$$f.objdump"; done - find work/rv32*/*/ -type f -name "*ref.elf" | while read f; do riscv64-unknown-elf-elf2hex --bit-width 32 --input "$$f" --output "$$f.memfile"; done - find work/rv64*/*/ -type f -name "*ref.elf" | while read f; do riscv64-unknown-elf-elf2hex --bit-width 64 --input "$$f" --output "$$f.memfile"; done - find work/rv*/*/ -type f -name "*.objdump" | while read f; do extractFunctionRadix.sh $$f; done +# memfile: +# sleep 1 +# # find work/rv*/*/ -type f -name "*ref.elf" | while read f; do riscv64-unknown-elf-objdump -S -D "$$f" > "$$f.objdump"; echo $$f; done +# find work/rv32*/*/ -type f -name "*ref.elf" | while read f; do riscv64-unknown-elf-elf2hex --bit-width 32 --input "$$f" --output "$$f.memfile"; done +# find work/rv64*/*/ -type f -name "*ref.elf" | while read f; do riscv64-unknown-elf-elf2hex --bit-width 64 --input "$$f" --output "$$f.memfile"; done +# find work/rv*/*/ -type f -name "*.objdump" | while read f; do extractFunctionRadix.sh $$f; done clean: rm -f config64.ini diff --git a/tests/riscof/sail_cSim/riscof_sail_cSim.py b/tests/riscof/sail_cSim/riscof_sail_cSim.py index c253dd632..de78070d1 100644 --- a/tests/riscof/sail_cSim/riscof_sail_cSim.py +++ b/tests/riscof/sail_cSim/riscof_sail_cSim.py @@ -98,8 +98,8 @@ class sail_cSim(pluginTemplate): compile_cmd = cmd + ' -D' + " -D".join(testentry['macros']) execute+=compile_cmd+";" - execute += self.objdump_cmd.format(elf, self.xlen, 'ref.disass') - sig_file = os.path.join(test_dir, self.name[:-1] + ".signature") + execute += self.objdump_cmd.format(elf, self.xlen, 'ref.elf.objdump') + sig_file = os.path.join(test_dir, "ref.signature.output") execute += self.sail_exe[self.xlen] + ' --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name) diff --git a/tests/riscof/spike/spike_rv32imc_isa.yaml b/tests/riscof/spike/spike_rv32imc_isa.yaml index fe8f8b115..644e97316 100644 --- a/tests/riscof/spike/spike_rv32imc_isa.yaml +++ b/tests/riscof/spike/spike_rv32imc_isa.yaml @@ -1,11 +1,11 @@ hart_ids: [0] hart0: - ISA: RV32IMCZicsr_Zifencei + ISA: RV32IMFCZicsr_Zifencei physical_addr_sz: 32 User_Spec_Version: '2.3' supported_xlen: [32] misa: - reset-val: 0x40001104 + reset-val: 0x40001124 rv32: accessible: true mxl: @@ -23,7 +23,7 @@ hart0: warl: dependency_fields: [] legal: - - extensions[25:0] bitmask [0x0001104, 0x0000000] + - extensions[25:0] bitmask [0x0001124, 0x0000000] wr_illegal: - Unchanged