diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index 470dc649d..da8a7a2a2 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -219,7 +219,6 @@ module bpred import cvw::*;  #(parameter cvw_t P) (
     assign {BTAWrongM, RASPredPCWrongM} = 0;
   end
 
-  // **** Fix me
   assign IClassM = {CallM, ReturnM, JumpM, BranchM};
   
 endmodule
diff --git a/src/ifu/bpred/localrepairbp.sv b/src/ifu/bpred/localrepairbp.sv
index dac13fd44..7294816a1 100644
--- a/src/ifu/bpred/localrepairbp.sv
+++ b/src/ifu/bpred/localrepairbp.sv
@@ -101,7 +101,7 @@ module localrepairbp import cvw::*; #(parameter cvw_t P,
 
   assign IndexLHRD = {PCE[m+1] ^ PCE[1], PCE[m:2]};
   assign LHRNextE = BranchD ? {BPDirD[1], LHRE[k-1:1]} : LHRE;
-  // *** replace with a small CAM
+  // RT: TODO active research: replace with a small CAM, quantify benefit
   ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**m), .WIDTH(k)) SHB(.clk(clk),
     .ce1(~StallF), .ce2(~StallE & ~FlushE),
     .ra1(IndexLHRNextF),
@@ -110,7 +110,7 @@ module localrepairbp import cvw::*; #(parameter cvw_t P,
     .wd2(LHRNextE),
     .we2(BranchD),
     .bwe2('1));
-  // **** replace with small CAM
+  // RT: TODO active research: replace with small CAM, quantify benefit
   logic [2**m-1:0]        FlushedBits;
   always_ff @(posedge clk) begin // Valid bit array,
     SpeculativeFlushedF <= FlushedBits[IndexLHRNextF];
diff --git a/src/lsu/align.sv b/src/lsu/align.sv
index 25a2c99d7..db37f4a66 100644
--- a/src/lsu/align.sv
+++ b/src/lsu/align.sv
@@ -76,6 +76,8 @@ module align import cvw::*;  #(parameter cvw_t P) (
   logic [$clog2(LLENINBYTES)-1:0]              AccessByteOffsetM;
   logic [$clog2(LLENINBYTES)+2:0]              ShiftAmount;
   logic                                        PotentialSpillM;
+  logic [P.LLEN*3-1:0]                         LSUWriteDataShiftedExtM; 
+
 
   /* verilator lint_off WIDTHEXPAND */
   assign IEUAdrIncrementM = IEUAdrM + LLENINBYTES;
@@ -152,10 +154,9 @@ module align import cvw::*;  #(parameter cvw_t P) (
   assign ReadDataWordSpillShiftedM = ReadDataWordSpillAllM >> ShiftAmount;
   assign DCacheReadDataWordSpillM = ReadDataWordSpillShiftedM[P.LLEN-1:0];
 
-  // write path. Also has the 8:1 shifter muxing for the byteoffset
-  // then it also has the mux to select when a spill occurs
-  logic [P.LLEN*3-1:0] LSUWriteDataShiftedExtM;  // *** RT: Find a better way.  I've extending in both directions so we don't shift in zeros.  The cache expects the writedata to not have any zero data, but instead replicated data.
-
+  // write path. 
+  // 3*LLEN to 2*LLEN funnel shifter to perform left rotation.
+  // Vivado correctly optimizes as 2*LLEN log2(LLEN):1 muxes
   assign LSUWriteDataShiftedExtM = {LSUWriteDataM, LSUWriteDataM, LSUWriteDataM} << ShiftAmount;
   assign LSUWriteDataSpillM = LSUWriteDataShiftedExtM[P.LLEN*3-1:P.LLEN];