diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index 277c4d6c8..bc1564950 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -1472,6 +1472,8 @@ string imperas32f[] = '{ // "rv64i_m/privilege/WALLY-scratch-01", "0040a0", // "rv64i_m/privilege/WALLY-sscratch-s-01", "0040a0", "rv64i_m/privilege/WALLY-trap-01", "0050a0", + "rv64i_m/privilege/WALLY-trap-s-01", "0050a0", + "rv64i_m/privilege/WALLY-trap-u-01", "0050a0", "rv64i_m/privilege/WALLY-MIE-01", "0050a0", "rv64i_m/privilege/WALLY-mtvec-01", "0050a0", "rv64i_m/privilege/WALLY-stvec-01", "0050a0", diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag index 7e6fdc8ff..2d230def1 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag @@ -66,6 +66,8 @@ target_tests_nosim = \ WALLY-PIE-stack-s-01 \ WALLY-trap-sret-01 \ WALLY-trap-01 \ + WALLY-trap-s-01 \ + WALLY-trap-u-01 \ # Have all 0's in references! #WALLY-MEPC \ #WALLY-SEPC \ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output index 8165e85c7..d8f7f8b40 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output @@ -1014,3 +1014,11 @@ deadbeef deadbeef deadbeef deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output index bc760ed62..84519e037 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output @@ -1,219 +1,209 @@ -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef +00000aaa # readback value from writing mie to enable interrupts +00000000 +0000000b # Test 5.3.1.4: mcause from ecall going from M mode to S mode +00000000 +00000000 # mtval of ecall (*** defined to be zero for now) +00000000 +00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000000 # scause from instruction addr misaligned fault +00000000 +800003d2 # stval of faulting instruction adress (0x800003d3) +00000000 +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000001 # scause from an instruction access fault +00000000 +00000000 # stval of faulting instruction address (0x0) +00000000 +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000002 # scause from an Illegal instruction +00000000 +00000000 # stval of faulting instruction (0x0) +00000000 +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000003 # scause from Breakpoint +00000000 +80000404 # stval of breakpoint instruction adress (0x80000404) +00000000 +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000004 # scause from load address misaligned +00000000 +8000040d # stval of misaligned address (0x8000040d) +00000000 +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000005 # scause from load access +00000000 +00000000 # stval of accessed adress (0x0) +00000000 +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000006 # scause from store misaligned +00000000 +80000429 # stval of address with misaligned store instr (0x80000429) +00000000 +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000007 # scause from store access +00000000 +00000000 # stval of accessed address (0x0) +00000000 +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000009 # scause from S mode ecall +00000000 +00000000 # stval of ecall (*** defined to be zero for now) +00000000 +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000008 # scause from U mode ecall +00000000 +00000000 # stval of ecall (*** defined to be zero for now) +00000000 +00000000 # masked out mstatus.mpp = 0 (from U mode), mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +0007ec01 # value to indicate successful vectoring on s soft interrupt +00000000 +00000001 # scause value from s soft interrupt +80000000 +00000000 # stval for ssoft interrupt (0x0) +00000000 +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +0007ec03 # value to indicate successful vectoring on m soft interrupt +00000000 +00000003 # scause value from m soft interrupt +80000000 +00000000 # stval for msoft interrupt (0x0) +00000000 +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +0007ec07 # value to indicate successful vectoring on m time interrupt +00000000 +00000007 # scause value from m time interrupt +80000000 +00000000 # stval for mtime interrupt (0x0) +00000000 +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +0007ec09 # value to indicate successful vectoring on s ext interrupt +00000000 +00000009 # scause value from s ext interrupt +80000000 +00000000 # stval for sext interrupt (0x0) +00000000 +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +0007ec0b # value to indicate successful vectoring on m ext interrupt +00000000 +0000000b # scause value from m ext interrupt +80000000 +00000000 # stval for mext interrupt (0x0) +00000000 +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000009 # scause from S mode ecall +00000000 +00000000 # stval of ecall (*** defined to be zero for now) +00000000 +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable) +ffffffff +00000222 # mideleg after attempted write of all 1's (only some bits are writeable) +00000000 +0000000b # scause from M mode ecall +00000000 +00000000 # stval of ecall (*** defined to be zero for now) +00000000 +00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000000 # scause from instruction addr misaligned fault +00000000 +800003d2 # stval of faulting instruction adress (0x800003d3) +00000000 +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000001 # scause from an instruction access fault +00000000 +00000000 # stval of faulting instruction address (0x0) +00000000 +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000002 # scause from an Illegal instruction +00000000 +00000000 # stval of faulting instruction (0x0) +00000000 +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000003 # scause from Breakpoint +00000000 +80000404 # stval of breakpoint instruction adress (0x80000404) +00000000 +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000004 # scause from load address misaligned +00000000 +8000040d # stval of misaligned address (0x8000040d) +00000000 +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000005 # scause from load access +00000000 +00000000 # stval of accessed adress (0x0) +00000000 +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000006 # scause from store misaligned +00000000 +80000429 # stval of address with misaligned store instr (0x80000429) +00000000 +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000007 # scause from store access +00000000 +00000000 # stval of accessed address (0x0) +00000000 +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000009 # scause from S mode ecall +00000000 +00000000 # stval of ecall (*** defined to be zero for now) +00000000 +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000008 # scause from U mode ecall +00000000 +00000000 # stval of ecall (*** defined to be zero for now) +00000000 +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +0007ec01 # value to indicate successful vectoring on s soft interrupt +00000000 +00000001 # scause value from s soft interrupt +80000000 +00000000 # stval for ssoft interrupt (0x0) +00000000 +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +0007ec09 # value to indicate successful vectoring on s ext interrupt +00000000 +00000009 # scause value from s ext interrupt +80000000 +00000000 # stval for sext interrupt (0x0) +00000000 +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000009 # scause from S mode ecall from test termination +00000000 +00000000 # stval of ecall (*** defined to be zero for now) +00000000 +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 deadbeef deadbeef deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output index bc760ed62..7a1b3dcd8 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output @@ -1,181 +1,181 @@ -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef +00000aaa # readback value from writing mie to enable interrupts +00000000 +0000000b # Test 5.3.1.4: mcause from ecall going from M mode to U mode +00000000 +00000000 # mtval of ecall (*** defined to be zero for now) +00000000 +00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000000 # scause from instruction addr misaligned fault +00000000 +800003d2 # stval of faulting instruction adress (0x800003d3) +00000000 +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000001 # scause from an instruction access fault +00000000 +00000000 # stval of faulting instruction address (0x0) +00000000 +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000002 # scause from an Illegal instruction +00000000 +00000000 # stval of faulting instruction (0x0) +00000000 +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000003 # scause from Breakpoint +00000000 +80000404 # stval of breakpoint instruction adress (0x80000404) +00000000 +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000004 # scause from load address misaligned +00000000 +8000040d # stval of misaligned address (0x8000040d) +00000000 +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000005 # scause from load access +00000000 +00000000 # stval of accessed adress (0x0) +00000000 +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000006 # scause from store misaligned +00000000 +80000429 # stval of address with misaligned store instr (0x80000429) +00000000 +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000007 # scause from store access +00000000 +00000000 # stval of accessed address (0x0) +00000000 +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000008 # scause from U mode ecall +00000000 +00000000 # stval of ecall (*** defined to be zero for now) +00000000 +00000000 # masked out mstatus.mpp = 0 (from U mode), mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +0007ec03 # value to indicate successful vectoring on m soft interrupt +00000000 +00000003 # scause value from m soft interrupt +80000000 +00000000 # stval for msoft interrupt (0x0) +00000000 +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +0007ec07 # value to indicate successful vectoring on m time interrupt +00000000 +00000007 # scause value from m time interrupt +80000000 +00000000 # stval for mtime interrupt (0x0) +00000000 +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +0007ec09 # value to indicate successful vectoring on s ext interrupt +00000000 +00000009 # scause value from s ext interrupt +80000000 +00000000 # stval for sext interrupt (0x0) +00000000 +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +0007ec0b # value to indicate successful vectoring on m ext interrupt +00000000 +0000000b # scause value from m ext interrupt +80000000 +00000000 # stval for mext interrupt (0x0) +00000000 +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000008 # scause from U mode ecall +00000000 +00000000 # stval of ecall (*** defined to be zero for now) +00000000 +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable) +ffffffff +00000222 # mideleg after attempted write of all 1's (only some bits are writeable) +00000000 +0000000b # scause from M mode ecall +00000000 +00000000 # stval of ecall (*** defined to be zero for now) +00000000 +00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000000 # scause from instruction addr misaligned fault +00000000 +800003d2 # stval of faulting instruction adress (0x800003d3) +00000000 +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000001 # scause from an instruction access fault +00000000 +00000000 # stval of faulting instruction address (0x0) +00000000 +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000002 # scause from an Illegal instruction +00000000 +00000000 # stval of faulting instruction (0x0) +00000000 +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000003 # scause from Breakpoint +00000000 +80000404 # stval of breakpoint instruction adress (0x80000404) +00000000 +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000004 # scause from load address misaligned +00000000 +8000040d # stval of misaligned address (0x8000040d) +00000000 +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000005 # scause from load access +00000000 +00000000 # stval of accessed adress (0x0) +00000000 +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000006 # scause from store misaligned +00000000 +80000429 # stval of address with misaligned store instr (0x80000429) +00000000 +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000007 # scause from store access +00000000 +00000000 # stval of accessed address (0x0) +00000000 +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000008 # scause from U mode ecall +00000000 +00000000 # stval of ecall (*** defined to be zero for now) +00000000 +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +0007ec09 # value to indicate successful vectoring on s ext interrupt +00000000 +00000009 # scause value from s ext interrupt +80000000 +00000000 # stval for sext interrupt (0x0) +00000000 +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000008 # scause from U mode ecall from test termination +00000000 +00000000 # stval of ecall (*** defined to be zero for now) +00000000 +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 deadbeef deadbeef deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S index 17100fbbe..5fe7eab4f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S @@ -52,12 +52,10 @@ jal cause_s_soft_interrupt jal cause_m_soft_interrupt jal cause_s_time_interrupt jal cause_m_time_interrupt -//jal cause_s_ext_interrupt_GPIO -jal cause_s_ext_interrupt_IP // cause external interrupt with both sip register and GPIO. +jal cause_s_ext_interrupt_GPIO jal cause_m_ext_interrupt - // try the traps again with mideleg = medeleg = all 1's to ensure traps still go to M mode from M mode WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF @@ -75,10 +73,12 @@ jal cause_ecall // M mode ecall jal cause_s_soft_interrupt // The delegated S mode interrupts should not fire since we're running in M mode. jal cause_m_soft_interrupt -jal cause_s_time_interrupt +jal cause_s_time_interrupt jal cause_m_time_interrupt -//jal cause_s_ext_interrupt_GPIO -jal cause_s_ext_interrupt_IP // cause external interrupt with both sip register and GPIO. +li a3, 0x40 // these interrupts involve a time loop waiting for the interrupt to go off. +// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3 +jal cause_s_ext_interrupt_GPIO +li a3, 0x40 jal cause_m_ext_interrupt diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S index 9a813d9a2..281721ea8 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S @@ -25,34 +25,42 @@ INIT_TESTS +CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses + // test 5.3.1.4 Basic trap tests -TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps +TRAP_HANDLER m, DEBUG=1 // necessary to handle switching privilege modes TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well // Like WALLY-trap, cause all the same traps from S mode and make sure they go to machine mode with zeroed mideleg, medeleg +li x28, 0x2 +csrs sstatus, x28 // set sstatus.SIE bit to 1 +WRITE_READ_CSR mie, 0xFFFF // sie is a subset of mie, so writing this also enables sie. + GOTO_S_MODE -li x28, 0x8 -csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode -// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts +jal cause_instr_addr_misaligned +jal cause_instr_access +jal cause_illegal_instr +jal cause_breakpnt +jal cause_load_addr_misaligned +jal cause_load_acc +jal cause_store_addr_misaligned +jal cause_store_acc +GOTO_U_MODE // Causes S mode ecall +GOTO_S_MODE // Causes U mode ecall -// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) -CAUSE_INSTR_ACCESS -CAUSE_ILLEGAL_INSTR -CAUSE_BREAKPNT -CAUSE_LOAD_ADDR_MISALIGNED -CAUSE_LOAD_ACC -CAUSE_STORE_ADDR_MISALIGNED -CAUSE_STORE_ACC -CAUSE_ECALL - -// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. -// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken -// CAUSE_EXT_INTERRUPT - +jal cause_s_soft_interrupt +jal cause_m_soft_interrupt +//jal cause_s_time_interrupt // *** S time interrupts cannot come from S mode as of 4/19/22. +jal cause_m_time_interrupt +li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off. +// since interrupts are not always enabled, +jal cause_s_ext_interrupt_GPIO +li a3, 0x40 +jal cause_m_ext_interrupt // Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler // We can tell which one becuase the different trap handler modes write different bits of the status register @@ -63,21 +71,27 @@ GOTO_M_MODE // so we can write the delegate registers WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF -GOTO_S_MODE +GOTO_S_MODE // Since we're running in M mode, this ecall will NOT be delegated to S mode -// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) -CAUSE_INSTR_ACCESS -CAUSE_ILLEGAL_INSTR -CAUSE_BREAKPNT -CAUSE_LOAD_ADDR_MISALIGNED -CAUSE_LOAD_ACC -CAUSE_STORE_ADDR_MISALIGNED -CAUSE_STORE_ACC -CAUSE_ECALL +jal cause_instr_addr_misaligned +jal cause_instr_access +jal cause_illegal_instr +jal cause_breakpnt +jal cause_load_addr_misaligned +jal cause_load_acc +jal cause_store_addr_misaligned +jal cause_store_acc +GOTO_U_MODE // Causes S mode ecall +GOTO_S_MODE // Causes U mode ecall + +jal cause_s_soft_interrupt // *** M mode Interrupts cannot be delegated in this implementation +//jal cause_m_soft_interrupt +//jal cause_s_time_interrupt +//jal cause_m_time_interrupt +li a3, 0x40 +jal cause_s_ext_interrupt_GPIO +//jal cause_m_ext_interrupt -// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. -// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken -// CAUSE_EXT_INTERRUPT END_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S index 498c2ee3b..6b90538da 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S @@ -25,6 +25,8 @@ INIT_TESTS +CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses + // test 5.3.1.4 Basic trap tests TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps @@ -32,27 +34,31 @@ TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well // Like WALLY-trap, cause all the same traps from U mode and make sure they go to machine mode with zeroed mideleg, medeleg +li x28, 0x2 +csrs sstatus, x28 // set sstatus.SIE bit to 1. Not strictly necessary but this lets us differentiate which trap handler we went to +WRITE_READ_CSR mie, 0xFFFF + GOTO_U_MODE -// li x28, 0x8 -// csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode -// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts - - -// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) -CAUSE_INSTR_ACCESS -CAUSE_ILLEGAL_INSTR -CAUSE_BREAKPNT -CAUSE_LOAD_ADDR_MISALIGNED -CAUSE_LOAD_ACC -CAUSE_STORE_ADDR_MISALIGNED -CAUSE_STORE_ACC -CAUSE_ECALL - -// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. -// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken -// CAUSE_EXT_INTERRUPT +jal cause_instr_addr_misaligned +jal cause_instr_access +jal cause_illegal_instr +jal cause_breakpnt +jal cause_load_addr_misaligned +jal cause_load_acc +jal cause_store_addr_misaligned +jal cause_store_acc +jal cause_ecall +//jal cause_s_soft_interrupt // *** writing SIP from u mode is illegal +jal cause_m_soft_interrupt +//jal cause_s_time_interrupt // *** S time interrupts cannot come from U mode as of 4/19/22. +jal cause_m_time_interrupt +li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off. +// since interrupts are not always enabled, +jal cause_s_ext_interrupt_GPIO +li a3, 0x40 +jal cause_m_ext_interrupt // Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler // We can tell which one becuase the different trap handler modes write different bits of the status register @@ -65,19 +71,25 @@ WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF GOTO_U_MODE -// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) -CAUSE_INSTR_ACCESS -CAUSE_ILLEGAL_INSTR -CAUSE_BREAKPNT -CAUSE_LOAD_ADDR_MISALIGNED -CAUSE_LOAD_ACC -CAUSE_STORE_ADDR_MISALIGNED -CAUSE_STORE_ACC -CAUSE_ECALL +jal cause_instr_addr_misaligned +jal cause_instr_access +jal cause_illegal_instr +jal cause_breakpnt +jal cause_load_addr_misaligned +jal cause_load_acc +jal cause_store_addr_misaligned +jal cause_store_acc +jal cause_ecall + +//jal cause_s_soft_interrupt // *** S Soft interrupts cannot be caused from u mode since writing SIP is illegal +// *** M mode Interrupts cannot be delegated in this implementation +//jal cause_m_soft_interrupt +//jal cause_s_time_interrupt +//jal cause_m_time_interrupt +li a3, 0x40 +jal cause_s_ext_interrupt_GPIO +//jal cause_m_ext_interrupt -// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. -// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken -// CAUSE_EXT_INTERRUPT END_TESTS