diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl
index b2e1e359e..a5e60a3d5 100644
--- a/fpga/generator/wally.tcl
+++ b/fpga/generator/wally.tcl
@@ -89,8 +89,8 @@ report_clock_interaction                                                -file re
 write_verilog -force -mode funcsim sim/syn-funcsim.v
 
 if {$board=="ArtyA7"} {
-    #source ../constraints/small-debug.xdc
-    source ../constraints/small-debug-rvvi.xdc
+    source ../constraints/small-debug.xdc
+    #source ../constraints/small-debug-rvvi.xdc
 } else {
     source ../constraints/vcu-small-debug.xdc
 }
diff --git a/fpga/src/fpgaTopArtyA7.sv b/fpga/src/fpgaTopArtyA7.sv
index fa2aa59a9..9133baa25 100644
--- a/fpga/src/fpgaTopArtyA7.sv
+++ b/fpga/src/fpgaTopArtyA7.sv
@@ -28,7 +28,7 @@
 
 import cvw::*;
 
-module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 1)
+module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
   (input           default_100mhz_clk,
 (* mark_debug = "true" *)   input           resetn,
    input           south_reset,