From ab82bb397c51b67bd768105a1b6e0efccc2697d7 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 31 Mar 2023 08:32:02 -0700 Subject: [PATCH 1/7] Privilege test improvements --- tests/coverage/priv.S | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/tests/coverage/priv.S b/tests/coverage/priv.S index 3aa3aea5c..008d06be6 100644 --- a/tests/coverage/priv.S +++ b/tests/coverage/priv.S @@ -36,4 +36,30 @@ main: addi t0, zero, 0 csrr t0, stimecmp + # CSR coverage + csrw scause, zero + csrw stval, zero + csrw scounteren, zero + csrw satp, zero + + # satp write with mstatus.TVM = 1 + bseti t0, zero, 20 + csrs mstatus, t0 + csrw satp, zero + + # STIMECMP from S mode + li t0, 1 + ecall # enter S-mode + csrw stimecmp, zero + li t0, 3 + ecall # return to M-mode + csrsi mcounteren, 2 # mcounteren_tm = 1 + li t0, 1 + ecall # supervisor mode again + csrw stimecmp, zero + li t0, 3 + ecall # machine mode again + + + j done From fd0c9e973d98b05176a81c6f275838344713afba Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 31 Mar 2023 08:33:46 -0700 Subject: [PATCH 2/7] Coverage improvements in ieu, hazard units --- sim/coverage-exclusions-rv64gc.do | 6 +++++- src/hazard/hazard.sv | 2 ++ src/ieu/bmu/bmuctrl.sv | 6 ++++-- src/ieu/controller.sv | 2 ++ src/lsu/lsu.sv | 2 +- src/privileged/csr.sv | 2 +- 6 files changed, 15 insertions(+), 5 deletions(-) diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do index 9905c897b..d58e4c514 100644 --- a/sim/coverage-exclusions-rv64gc.do +++ b/sim/coverage-exclusions-rv64gc.do @@ -24,8 +24,12 @@ #// and limitations under the License. #//////////////////////////////////////////////////////////////////////////////////////////////// +# This file should be a last resort. It's preferable to put +# // coverage off +# statements inline with the code whenever possible. + # LZA (i<64) statement confuses coverage tool -# This is ugly to exlcude the whole file - is there a better option +# This is ugly to exlcude the whole file - is there a better option? // coverage off isn't working coverage exclude -srcfile lzc.sv diff --git a/src/hazard/hazard.sv b/src/hazard/hazard.sv index cf3a22c1f..bc9f7baa0 100644 --- a/src/hazard/hazard.sv +++ b/src/hazard/hazard.sv @@ -88,7 +88,9 @@ module hazard ( assign StallWCause = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause); // Stall each stage for cause or if the next stage is stalled + // coverage off: StallFCause is always 0 assign #1 StallF = StallFCause | StallD; + // coverage on assign #1 StallD = StallDCause | StallE; assign #1 StallE = StallECause | StallM; assign #1 StallM = StallMCause | StallW; diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 90d031a14..0bfbfeb49 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -101,8 +101,10 @@ module bmuctrl( BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // sign extend instruction else if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0])) BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0; // count instruction - 17'b0110011_0000100_100: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32) +// // coverage off: This case can't occur in RV64 +// 17'b0110011_0000100_100: if (`XLEN == 32) +// BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32) +// // coverage on 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0; // andn 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0; // orn 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 5d0b78457..2174b96c3 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -264,7 +264,9 @@ module controller( end else assign sltD = (Funct3D == 3'b010); // Combine base and bit manipulation signals + // coverage off: IllegalERegAdr can't occur in rv64gc; only applicable to E mode assign IllegalBaseInstrD = (ControlsD[0] & IllegalBitmanipInstrD) | IllegalERegAdrD ; + // coverage on assign RegWriteD = BaseRegWriteD | BRegWriteD; assign W64D = BaseW64D | BW64D; assign ALUSrcBD = BaseALUSrcBD | BALUSrcBD; diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 0b0bc81e3..f2e147f00 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -149,7 +149,7 @@ module lsu ( // MMU include PMP and is needed if any privileged supported ///////////////////////////////////////////////////////////////////////////////////////////// - if(`VIRTMEM_SUPPORTED) begin : VIRTMEM_SUPPORTED + if(`VIRTMEM_SUPPORTED) begin : hptw hptw hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF, .DTLBMissM, .DTLBWriteM, .InstrUpdateDAF, .DataUpdateDAM, .FlushW, .DCacheStallM, .SATP_REGW, .PCSpillF, diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index 688218b7b..db142de5f 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -202,7 +202,7 @@ module csr #(parameter assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM; assign UngatedCSRMWriteM = CSRWriteM & (PrivilegeModeW == `M_MODE); assign CSRMWriteM = UngatedCSRMWriteM & InstrValidNotFlushedM; - assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW) & InstrValidNotFlushedM; + assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW) & InstrValidNotFlushedM; assign CSRUWriteM = CSRWriteM & InstrValidNotFlushedM; assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE); assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED; From fa17487d6774b75016c9b85688a5584cca190625 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 31 Mar 2023 08:37:16 -0700 Subject: [PATCH 3/7] Merged privileged test --- tests/coverage/priv.S | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/tests/coverage/priv.S b/tests/coverage/priv.S index 0d59a2555..008d06be6 100644 --- a/tests/coverage/priv.S +++ b/tests/coverage/priv.S @@ -36,7 +36,6 @@ main: addi t0, zero, 0 csrr t0, stimecmp -<<<<<<< HEAD # CSR coverage csrw scause, zero csrw stval, zero @@ -63,13 +62,4 @@ main: -======= - # Test write to STVAL, SCAUSE, SEPC, and STIMECMP CSRs - li t0, 0 - csrw stval, t0 - csrw scause, t0 - csrw sepc, t0 - csrw stimecmp, t0 - ->>>>>>> 37d289cf44530c3e3a6f53e54b06e6eda7f0c3c1 j done From 69805b4a60d731665644315f5411a983e7e6522c Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 31 Mar 2023 09:15:15 -0700 Subject: [PATCH 4/7] Regression update --- sim/regression-wally | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/sim/regression-wally b/sim/regression-wally index 7a509c890..045d7b947 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -49,6 +49,7 @@ configs = [ ] def getBuildrootTC(boot): INSTR_LIMIT = 4000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM +# INSTR_LIMIT = 8000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM MAX_EXPECTED = 246000000 # *** TODO: replace this with a search for the login prompt. if boot: name="buildrootboot" @@ -56,7 +57,12 @@ def getBuildrootTC(boot): BRgrepstr="WallyHostname login:" else: name="buildroot" - BRcmd="vsim > {} -c < {} -c < {} -c < Date: Fri, 31 Mar 2023 09:59:38 -0700 Subject: [PATCH 5/7] regression cleanup; unable to run buildroot coverage because of different config file --- sim/Makefile | 3 ++- sim/imperas.ic | 4 ++-- sim/regression-wally | 17 +++++------------ sim/wally-batch.do | 13 ++++++++++--- tests/coverage/ieu.S | 6 ++++++ 5 files changed, 25 insertions(+), 18 deletions(-) diff --git a/sim/Makefile b/sim/Makefile index 540c9418f..9cf3f0034 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -18,7 +18,8 @@ all: riscoftests memfiles coveragetests coverage: #make -C ../tests/coverage --jobs #iter-elf.bash --cover --search ../tests/coverage - vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb riscv.ucdb -logfile cov/log + vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb cov/buildroot_buildroot.ucdb riscv.ucdb -logfile cov/log +# vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb riscv.ucdb /home/rthompson/buildroot_buildroot-no-trace.ucdb -logfile cov/log vcover report -details cov/cov.ucdb > cov/rv64gc_coverage_details.rpt vcover report cov/cov.ucdb -details -instance=/core/ebu. > cov/rv64gc_coverage_ebu.rpt vcover report cov/cov.ucdb -details -instance=/core/priv. > cov/rv64gc_coverage_priv.rpt diff --git a/sim/imperas.ic b/sim/imperas.ic index 167c0cc44..fe8220399 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -6,7 +6,7 @@ # Core settings --override cpu/unaligned=F --override cpu/ignore_non_leaf_DAU=1 ---override cpu/wfi_is_nop=T +#--override cpu/wfi_is_nop=T --override cpu/mimpid=0x100 --override cpu/misa_Extensions_mask=0x0 @@ -49,7 +49,7 @@ # Add Imperas simulator application instruction tracing --override cpu/show_c_prefix=T ---trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange --traceafter 10500000 +--trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange --traceafter 800000 # Exceptions and pagetables debug --override cpu/debugflags=6 diff --git a/sim/regression-wally b/sim/regression-wally index 045d7b947..c70177206 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -49,7 +49,6 @@ configs = [ ] def getBuildrootTC(boot): INSTR_LIMIT = 4000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM -# INSTR_LIMIT = 8000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM MAX_EXPECTED = 246000000 # *** TODO: replace this with a search for the login prompt. if boot: name="buildrootboot" @@ -182,8 +181,6 @@ def main(): try: os.chdir(regressionDir) os.mkdir("logs") - #print(os.getcwd()) - #print(regressionDir) except: pass try: @@ -204,9 +201,11 @@ def main(): TIMEOUT_DUR = 30*7200 # seconds configs=[getBuildrootTC(boot=True)] elif '-coverage' in sys.argv: - TIMEOUT_DUR = 20*60 # seconds - configs.append(getBuildrootTC(boot=False)) - os.system('rm cov/*.ucdb') + TIMEOUT_DUR = 20*60 # seconds + # Presently don't run buildroot because it has a different config and can't be merged with the rv64gc coverage. + # Also it is slow to run. + # configs.append(getBuildrootTC(boot=False)) + os.system('rm -f cov/*.ucdb') else: TIMEOUT_DUR = 10*60 # seconds configs.append(getBuildrootTC(boot=False)) @@ -228,12 +227,6 @@ def main(): # Coverage report if coverage: os.system('make coverage') - #print('Generating coverage report') - #os.system('vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb -logfile cov/log') - #os.system('vcover report -details cov/cov.ucdb > cov/rv64gc_coverage_details.rpt') - #os.system('vcover report -below 100 cov/cov.ucdb > cov/rv64gc_coverage.rpt') - #os.system('vcover report -recursive cov/cov.ucdb > cov/rv64gc_recursive.rpt') - #os.system('vcover report -details -threshH 100 -html cov/cov.ucdb') # Count the number of failures if num_fail: print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail) diff --git a/sim/wally-batch.do b/sim/wally-batch.do index 7815e94fc..df49518c1 100644 --- a/sim/wally-batch.do +++ b/sim/wally-batch.do @@ -46,7 +46,7 @@ mkdir -p cov # Check if measuring coverage set coverage 0 if {$argc >= 3} { - if {$3 eq "-coverage"} { + if {$3 eq "-coverage" || ($argc >= 7 && $7 eq "-coverage")} { set coverage 1 } } @@ -61,8 +61,14 @@ if {$argc >= 3} { if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 # start and run simulation - vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt - vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286 -fatal 7 + if { $coverage } { + echo "wally-batch buildroot coverage" + vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt +cover=sbecf + vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286 -fatal 7 -cover + } else { + vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt + vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286 -fatal 7 + } run -all run -all @@ -139,6 +145,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { } if {$coverage} { + echo "Saving coverage to ${1}_${2}.ucdb" do coverage-exclusions-rv64gc.do # beware: this assumes testing the rv64gc configuration coverage save -instance /testbench/dut/core cov/${1}_${2}.ucdb } diff --git a/tests/coverage/ieu.S b/tests/coverage/ieu.S index e1b239371..3fd56686f 100644 --- a/tests/coverage/ieu.S +++ b/tests/coverage/ieu.S @@ -28,6 +28,11 @@ main: + # Division test (having trouble with buildroot) + li x11, 0x384000 + li x12, 0x1c2000 + divuw x9, x11, x12 + # Test clz with all bits being 0 li t0, 0 clz t1, t0 @@ -61,5 +66,6 @@ main: .word 0x6080101B // Illegal BMU similar to count word .word 0x6030101B // Illegal BMU similar to count word + j done From c1ec1cb09c9638f4317ad46f5cbfd65ad67b953a Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 31 Mar 2023 10:54:03 -0700 Subject: [PATCH 6/7] Added SSTC support to imperas.ic and wallyTracer. Fixes many of the privileged tests --- sim/imperas.ic | 10 +++++++++- testbench/common/wallyTracer.sv | 6 ++++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/sim/imperas.ic b/sim/imperas.ic index fe8220399..beadba6fa 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -10,10 +10,15 @@ --override cpu/mimpid=0x100 --override cpu/misa_Extensions_mask=0x0 -# THIS NEEDS FIXING to 16 --override cpu/PMP_registers=16 --override cpu/PMP_undefined=T +# Wally-specific non-default configuraiton +--override refRoot/cpu/Sstc=T +# Zba doesn't seem to exist - Lee is finding the name +#--override refRoot/cpu/Zba=T + + # Illegal instruction should not contain the bit pattern # illegal pmp read contained this # --override cpu/tval_ii_code=F @@ -47,8 +52,11 @@ #-override refRoot/cpu/cv/cover=basic #-override refRoot/cpu/cv/extensions=RV32I + + # Add Imperas simulator application instruction tracing --override cpu/show_c_prefix=T + --trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange --traceafter 800000 # Exceptions and pagetables debug diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 4df1956ad..221c8d7f8 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -162,6 +162,7 @@ module wallyTracer(rvviTrace rvvi); CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW; CSRArray[12'h142] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; CSRArray[12'h144] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW; + CSRArray[12'h14D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW; // user CSRs CSRArray[12'h001] = testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW; CSRArray[12'h002] = testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW; @@ -211,6 +212,7 @@ module wallyTracer(rvviTrace rvvi); CSRArray[12'h143] = CSRArrayOld[12'h143]; CSRArray[12'h142] = CSRArrayOld[12'h142]; CSRArray[12'h144] = CSRArrayOld[12'h144]; + CSRArray[12'h14D] = CSRArrayOld[12'h14D]; // user CSRs CSRArray[12'h001] = CSRArrayOld[12'h001]; CSRArray[12'h002] = CSRArrayOld[12'h002]; @@ -329,6 +331,7 @@ module wallyTracer(rvviTrace rvvi); CSRArrayOld[12'h143] = CSRArray[12'h143]; CSRArrayOld[12'h142] = CSRArray[12'h142]; CSRArrayOld[12'h144] = CSRArray[12'h144]; + CSRArrayOld[12'h14D] = CSRArray[12'h14D]; // user CSRs CSRArrayOld[12'h001] = CSRArray[12'h001]; CSRArrayOld[12'h002] = CSRArray[12'h002]; @@ -376,6 +379,7 @@ module wallyTracer(rvviTrace rvvi); assign #2 CSR_W[12'h143] = (CSRArrayOld[12'h143] != CSRArray[12'h143]) ? 1 : 0; assign #2 CSR_W[12'h142] = (CSRArrayOld[12'h142] != CSRArray[12'h142]) ? 1 : 0; assign #2 CSR_W[12'h144] = (CSRArrayOld[12'h144] != CSRArray[12'h144]) ? 1 : 0; + assign #2 CSR_W[12'h14D] = (CSRArrayOld[12'h14D] != CSRArray[12'h14D]) ? 1 : 0; assign #2 CSR_W[12'h001] = (CSRArrayOld[12'h001] != CSRArray[12'h001]) ? 1 : 0; assign #2 CSR_W[12'h002] = (CSRArrayOld[12'h002] != CSRArray[12'h002]) ? 1 : 0; assign #2 CSR_W[12'h003] = (CSRArrayOld[12'h003] != CSRArray[12'h003]) ? 1 : 0; @@ -412,6 +416,7 @@ module wallyTracer(rvviTrace rvvi); assign rvvi.csr_wb[0][0][12'h143] = CSR_W[12'h143]; assign rvvi.csr_wb[0][0][12'h142] = CSR_W[12'h142]; assign rvvi.csr_wb[0][0][12'h144] = CSR_W[12'h144]; + assign rvvi.csr_wb[0][0][12'h14D] = CSR_W[12'h14D]; assign rvvi.csr_wb[0][0][12'h001] = CSR_W[12'h001]; assign rvvi.csr_wb[0][0][12'h002] = CSR_W[12'h002]; assign rvvi.csr_wb[0][0][12'h003] = CSR_W[12'h003]; @@ -448,6 +453,7 @@ module wallyTracer(rvviTrace rvvi); assign rvvi.csr[0][0][12'h143] = CSRArray[12'h143]; assign rvvi.csr[0][0][12'h142] = CSRArray[12'h142]; assign rvvi.csr[0][0][12'h144] = CSRArray[12'h144]; + assign rvvi.csr[0][0][12'h14D] = CSRArray[12'h14D]; assign rvvi.csr[0][0][12'h001] = CSRArray[12'h001]; assign rvvi.csr[0][0][12'h002] = CSRArray[12'h002]; assign rvvi.csr[0][0][12'h003] = CSRArray[12'h003]; From a6117e9befca7ee2452fbac1f803073c2fea8ea6 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 3 Apr 2023 17:55:30 -0700 Subject: [PATCH 7/7] Updated imperas.ic to enable B extension --- sim/imperas.ic | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/sim/imperas.ic b/sim/imperas.ic index beadba6fa..2295c9d45 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -15,9 +15,8 @@ # Wally-specific non-default configuraiton --override refRoot/cpu/Sstc=T -# Zba doesn't seem to exist - Lee is finding the name -#--override refRoot/cpu/Zba=T - +--override cpu/add_implicit_Extensions=B +--override cpu/bitmanip_version=1.0.0 # Illegal instruction should not contain the bit pattern # illegal pmp read contained this