diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile
index d9b5694ed..0078be133 100644
--- a/fpga/generator/Makefile
+++ b/fpga/generator/Makefile
@@ -28,8 +28,8 @@ vcu108: FPGA_VCU
 genesys2: export XILINX_PART := xc7k325tffg900-2
 genesys2: export XILINX_BOARD := digilentinc.com:genesys2:part0:1.1
 genesys2: export board := genesys2
-genesys2: export SYSTEMCLOCK := 25000000
-genesys2: export MAXSDCCLOCK  := 12500000
+genesys2: export SYSTEMCLOCK := 40000000
+genesys2: export MAXSDCCLOCK  := 10000000
 genesys2: FPGA_GENESYS2
 
 # variables computed from config
diff --git a/linux/devicetree/wally-genesys2.dts b/linux/devicetree/wally-genesys2.dts
index 14d442b86..66b59a18a 100644
--- a/linux/devicetree/wally-genesys2.dts
+++ b/linux/devicetree/wally-genesys2.dts
@@ -21,8 +21,8 @@
 	cpus {
 		#address-cells = <0x01>;
 		#size-cells = <0x00>;
-		clock-frequency = <25000000>;
-		timebase-frequency = <25000000>;
+		clock-frequency = <40000000>;
+		timebase-frequency = <40000000>;
 
 		cpu@0 {
 			phandle = <0x01>;
@@ -54,7 +54,7 @@
 		refclk: refclk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
-			clock-frequency = <25000000>;
+			clock-frequency = <40000000>;
 			clock-output-names = "xtal";
 		};
 
@@ -73,7 +73,7 @@
 		uart@10000000 {
 			interrupts = <0x0a>;
 			interrupt-parent = <0x03>;
-			clock-frequency = <25000000>;
+			clock-frequency = <40000000>;
 			reg = <0x00 0x10000000 0x00 0x100>;
 			compatible = "ns16550a";
 		};