From 877c4eefd1565d5726ea3ffb787f9b239717bb97 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 06:55:39 -0700 Subject: [PATCH 01/14] Fixed typo in csrm --- pipelined/src/privileged/csrm.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/privileged/csrm.sv b/pipelined/src/privileged/csrm.sv index b32d30d26..33ffa0ecf 100644 --- a/pipelined/src/privileged/csrm.sv +++ b/pipelined/src/privileged/csrm.sv @@ -187,7 +187,7 @@ module csrm #(parameter MARCHID: CSRMReadValM = 0; MIMPID: CSRMReadValM = `XLEN'h100; // pipelined implementation MHARTID: CSRMReadValM = MHARTID_REGW; // hardwired to 0 - MCONFIGPTR: CSRReadValM = 0; // hardwired to 0 + MCONFIGPTR: CSRMReadValM = 0; // hardwired to 0 MSTATUS: CSRMReadValM = MSTATUS_REGW; MSTATUSH: CSRMReadValM = MSTATUSH_REGW; MTVEC: CSRMReadValM = MTVEC_REGW; From 4b0bf937ff113fd501cc1cba865483b448c997d1 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 14:05:27 +0000 Subject: [PATCH 02/14] Removed unused ch5 assembly example --- examples/asm/ch5/Makefile | 10 ---------- examples/asm/ch5/ch5 | Bin 1080 -> 0 bytes examples/asm/ch5/ch5.S | 16 ---------------- examples/asm/ch5/ch5.debug | 38 ------------------------------------- examples/asm/ch5/example | Bin 6072 -> 0 bytes 5 files changed, 64 deletions(-) delete mode 100644 examples/asm/ch5/Makefile delete mode 100755 examples/asm/ch5/ch5 delete mode 100644 examples/asm/ch5/ch5.S delete mode 100644 examples/asm/ch5/ch5.debug delete mode 100755 examples/asm/ch5/example diff --git a/examples/asm/ch5/Makefile b/examples/asm/ch5/Makefile deleted file mode 100644 index 6f1cd89d4..000000000 --- a/examples/asm/ch5/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -ch5.debug: ch5 - riscv64-unknown-elf-objdump -D ch5 > ch5.debug - -ch5: ch5.S Makefile - riscv64-unknown-elf-gcc -nodefaultlibs -nostartfiles -o ch5 ch5.S -# -ffreestanding -# -nostdlib - -clean: - rm -f ch5 ch5.debug \ No newline at end of file diff --git a/examples/asm/ch5/ch5 b/examples/asm/ch5/ch5 deleted file mode 100755 index 3684ea3833c315acc061fcbd46daf2616e3a457e..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1080 zcmb_aO-sW-5S{c3y+sfyc&XTf7gK3Pya-8Yl|m^>_26mAml|x7kgTPiRP^AX2Y-%7 z|C0CvbT*mAHX6LRhxcaR%)Xudxa;;03yK1A6yO8IY?>f|PKnn-8kCWA*vG666(}cF zLi--lE9Ds_B!ij?k2M`O>ngM!RIs0F5TI-{5h5?PC!lO$SdJ!pyIwQgVPgTNfC~YR z02?9o%EKadC(kioQv^E9oG7|2!TaZ&l!Pk@Dlnt_koh&zpELS8>MHuos`4Jv72Ao9 zKI)=AAU)gX0qHN9`d*IDS&r`H=+`;^(BR{+VcX~J6W{J@0XTv0!YBwrVC-@fSmua@ zf#-8Ks-rUO7^enncaM4l#&F&q4q125Nn$IGSEh!K$ vzIwWM)>D+eQT;J3DB)c6xI}uDco`Y@|1nfD%{G?ZU;OLe*5A|mzxw|IBGX>; diff --git a/examples/asm/ch5/ch5.S b/examples/asm/ch5/ch5.S deleted file mode 100644 index cfba56458..000000000 --- a/examples/asm/ch5/ch5.S +++ /dev/null @@ -1,16 +0,0 @@ -# ch5.s -# David_Harris@hmc.edu 14 December 2021 - -.section .text.init - -.globl _start -_start: - lw x1, 4(x0) - sw x1, 8(x0) - add x2, x1, x1 - beq x1, x2, done -loop: - jal x0, loop -done: - -.end diff --git a/examples/asm/ch5/ch5.debug b/examples/asm/ch5/ch5.debug deleted file mode 100644 index 28027a62e..000000000 --- a/examples/asm/ch5/ch5.debug +++ /dev/null @@ -1,38 +0,0 @@ - -ch5: file format elf64-littleriscv - - -Disassembly of section .text: - -0000000000010078 <_start>: - 10078: 00402083 lw ra,4(zero) # 4 <_start-0x10074> - 1007c: 00102423 sw ra,8(zero) # 8 <_start-0x10070> - 10080: 00108133 add sp,ra,ra - 10084: 00208463 beq ra,sp,1008c - -0000000000010088 : - 10088: 0000006f j 10088 - -Disassembly of section .riscv.attributes: - -0000000000000000 <.riscv.attributes>: - 0: 3241 addiw tp,tp,-16 - 2: 0000 unimp - 4: 7200 ld s0,32(a2) - 6: 7369 lui t1,0xffffa - 8: 01007663 bgeu zero,a6,14 <_start-0x10064> - c: 0028 addi a0,sp,8 - e: 0000 unimp - 10: 7205 lui tp,0xfffe1 - 12: 3676 fld fa2,376(sp) - 14: 6934 ld a3,80(a0) - 16: 7032 0x7032 - 18: 5f30 lw a2,120(a4) - 1a: 326d addiw tp,tp,-5 - 1c: 3070 fld fa2,224(s0) - 1e: 615f 7032 5f30 0x5f307032615f - 24: 3266 fld ft4,120(sp) - 26: 3070 fld fa2,224(s0) - 28: 645f 7032 5f30 0x5f307032645f - 2e: 30703263 0x30703263 - ... diff --git a/examples/asm/ch5/example b/examples/asm/ch5/example deleted file mode 100755 index a9b74047949c0c1022323eb3f86a6a5e588b2095..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 6072 zcmeHLZ%iD=6@UBZ4qxpiU`TOlHwMlHm(mL)wBRN|$Dadir6h{$RF0Y~%ie;|x#P}z zi({f%xj&ot`aHd53G8*2Q)61IXJCynjC z*`0x7xl=#%LludUX5P$ie(%kjH?y;|`-kJmbmJ+jN%1Y7fVG{DqHtDrvuA==_MJAugU*ws*_o!rgNo)_DZ&V9yp4z^5 zVv$rSKr$NrpfJJRDm)bZ!f`n2nFn`%F*;RfvsFHL&a8d6d>*E^&I7FBJypQ9&O?dq z=%jF-yY;|aV?o(;!+?F3*pB|$gSO8#rEvH;%!#(~PG{uCE#BM6#Uil?;T%OyG7-H+ zc*O!h5AtG>LfaV6jWrfTJ!RAO*~)==h^!ahk1jkOI64(el_kjdTtV5@9n&7K$Cu0# zn+qL|=0_c0xb4@jz!+JPq~NfDIQ>C zq$hG5oOx-Ou&2R^dBTPg^Mr^J^MrsB^8}9)^8|+y^8}#8jIp_S^Zw*W0xrIu9I%!Hq_ob-f8z<)|>jr`}vnI?`?W<{6*d`V?5#&Lon*SQ>P3Jiq7{$kUxo6IBNbd zG7Li15ZpWxtr(i;Qv$N$b;FyLqCswEu;SkzebO-GOUEm=*Tml+$S15f=blUOsY|Dw z=u6*e7uIj2$*P{~@py6VT9Si;7cLby9NW}+r${b}rT+Dmxk6-p zP9&nOTr1~sj0x%JLcDHp^KYj{+YYuXO;_!p7KwVeR`j4P+Lm1NS6di&u+nS;vVY5_EAd%)OpLg32Lqht#&8$kjA50e zlk{Aurf0@o+BSOuA`hC+arL)NIZY+&|GGTqRb;e4Doa zN4363Le)}$6f!BgN#P}hf(5ghT?+UvXYcn+hJd$yb}wI!3s7zGm-GuDf;%g212&)K zcI@!RM)qc1>JcChCbQyemPi>j0UQ}Evr4RraO0k}qW}RuW4`pW1UBd36MZgA97yDe z9qT>FZSa@;XR~|Kz*okH+`xz(cCW&wkzT=)!#JFzabQdMs(}koZ;A8Uh-aH`+OWn! zN5;1vfj-N@Kbr&p5OEHc*0CMGhe-N6=4|8sGY5Vp2R@qv$1k_6_P@-5=UPV|7b4p_ zqM5Ar^NocQSM1wTid*-2t$_YX*5_q+4&0vuk0G9q`?-CSK_G4$=@>TGiVMhQ@k-jOp8!+KwLH+D#pHz@V^gI%&; z^6Eh?EXjQbKnVsyepOe!uA1x&!;U0tn%pm`y}H&9-I^RwC2wCK&=0|`y{e+)TSt;I zU`MH65X4{t-?{Q&(Ua0MlDeV<-)3 zDCq0Oz;8iwhHof$wlw~ z7|Ts!5YmE57=gtVXCPutJ9jPyq$?bjOjiSHAgt;TkbS*ih7_sGT~v+u8!-lOh5G}# z+=WutOu2{EaJ%W?Qumn44z8tOfh)sZmtoEoHU)YDF5Gbe+(_Uu?kFx<*EL^PpRSTO z-T$68q6u<>uyc;xTTW8bFXMl?%!H5CvQ&yKqR(jTe#8Dp(%+JcI@b30vFE-FeRi%_ zQzE-hFazxTV6qN7?$6L??-4iEXS`hc&DfFYKf718Q+@Vcw(7I?c8fkc@86(5Gd3_H zl~#YAMx0U8njV(4X3*xfL^;KZ^^wX|lOvbumqnizTL?TZ~)BC$wz(BK^;9otRbs EKb_svjsO4v From 15659b05e4f120b931e5e52175f5869fb2881de9 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 14:09:52 +0000 Subject: [PATCH 03/14] Simplifed mstatus.TSR handling --- pipelined/src/privileged/privdec.sv | 11 ++++++----- pipelined/src/privileged/privileged.sv | 6 ++---- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/pipelined/src/privileged/privdec.sv b/pipelined/src/privileged/privdec.sv index ed5b51d4f..ae831144b 100644 --- a/pipelined/src/privileged/privdec.sv +++ b/pipelined/src/privileged/privdec.sv @@ -34,7 +34,7 @@ module privdec ( input logic [31:20] InstrM, input logic PrivilegedM, IllegalIEUInstrFaultM, IllegalCSRAccessM, IllegalFPUInstrM, - input logic TrappedSRETM, WFITimeoutM, + input logic WFITimeoutM, input logic [1:0] PrivilegeModeW, input logic STATUS_TSR, STATUS_TVM, input logic [1:0] STATUS_FS, @@ -43,18 +43,19 @@ module privdec ( logic IllegalPrivilegedInstrM, IllegalOrDisabledFPUInstrM; - // xRET defined in Privileged Spect 3.2.2 + // Decode privileged instructions assign sretM = PrivilegedM & (InstrM[31:20] == 12'b000100000010) & `S_SUPPORTED & - PrivilegeModeW[0] & ~STATUS_TSR; + (PrivilegeModeW == `M_MODE || PrivilegeModeW == `S_MODE & ~STATUS_TSR); assign mretM = PrivilegedM & (InstrM[31:20] == 12'b001100000010) & (PrivilegeModeW == `M_MODE); - assign ecallM = PrivilegedM & (InstrM[31:20] == 12'b000000000000); assign ebreakM = PrivilegedM & (InstrM[31:20] == 12'b000000000001); assign wfiM = PrivilegedM & (InstrM[31:20] == 12'b000100000101); assign sfencevmaM = PrivilegedM & (InstrM[31:25] == 7'b0001001) & (PrivilegeModeW == `M_MODE | (PrivilegeModeW == `S_MODE & ~STATUS_TVM)); + + // Fault on illegal instructions assign IllegalPrivilegedInstrM = PrivilegedM & ~(sretM|mretM|ecallM|ebreakM|wfiM|sfencevmaM); assign IllegalOrDisabledFPUInstrM = IllegalFPUInstrM | (STATUS_FS == 2'b00); assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalOrDisabledFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM | - TrappedSRETM | WFITimeoutM; + WFITimeoutM; endmodule diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index abcbeecbe..523326a31 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -95,7 +95,7 @@ module privileged ( logic IllegalFPUInstrM; logic InstrPageFaultD, InstrPageFaultE, InstrPageFaultM; logic InstrAccessFaultD, InstrAccessFaultE, InstrAccessFaultM; - logic IllegalInstrFaultM, TrappedSRETM; + logic IllegalInstrFaultM; logic MTrapM, STrapM, UTrapM; (* mark_debug = "true" *) logic InterruptM; @@ -129,8 +129,6 @@ module privileged ( end else NextPrivilegeModeM = PrivilegeModeW; end - assign TrappedSRETM = sretM & STATUS_TSR & PrivilegeModeW == `S_MODE; - flopenl #(2) privmodereg(clk, reset, ~StallW, NextPrivilegeModeM, `M_MODE, PrivilegeModeW); /////////////////////////////////////////// @@ -149,7 +147,7 @@ module privileged ( /////////////////////////////////////////// privdec pmd(.InstrM(InstrM[31:20]), - .PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, .TrappedSRETM, .WFITimeoutM, + .PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, .WFITimeoutM, .PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_FS, .IllegalInstrFaultM, .sretM, .mretM, .ecallM, .ebreakM, .wfiM, .sfencevmaM); From 8372bc86a79c0bce6da9b35c97c6d8061498b7df Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 14:36:15 +0000 Subject: [PATCH 04/14] Removing unused signals --- addins/embench-iot | 2 +- addins/riscv-arch-test | 2 +- addins/riscv-dv | 2 +- addins/riscv-tests | 2 +- pipelined/regression/lint-wally | 4 +- pipelined/src/cache/sram1p1rw.sv | 1 - pipelined/src/fpu/fma.sv | 14 +- pipelined/src/fpu/fpu.sv | 4 +- pipelined/src/mmu/tlbcontrol.sv | 2 - pipelined/src/ppa/ppa.sv | 324 ------------------------------- 10 files changed, 15 insertions(+), 342 deletions(-) delete mode 100644 pipelined/src/ppa/ppa.sv diff --git a/addins/embench-iot b/addins/embench-iot index 261a65e0a..2d2aaa7b8 160000 --- a/addins/embench-iot +++ b/addins/embench-iot @@ -1 +1 @@ -Subproject commit 261a65e0a2d3e8d62d81b1d8fe7e309a096bc6a9 +Subproject commit 2d2aaa7b85c60219c591555b647dfa1785ffe1b3 diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index 307c77b26..effd553a6 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86 +Subproject commit effd553a6a91ed9b0ba251796a8a44505a45174f diff --git a/addins/riscv-dv b/addins/riscv-dv index a7e27bc04..cb4295f9c 160000 --- a/addins/riscv-dv +++ b/addins/riscv-dv @@ -1 +1 @@ -Subproject commit a7e27bc046405f0dbcde091be99f5a5d564e2172 +Subproject commit cb4295f9ce5da2881d7746015a6105adb8f09071 diff --git a/addins/riscv-tests b/addins/riscv-tests index cf04274f5..3e2bf06b0 160000 --- a/addins/riscv-tests +++ b/addins/riscv-tests @@ -1 +1 @@ -Subproject commit cf04274f50621fd9ef9147793cca6dd1657985c7 +Subproject commit 3e2bf06b071a77ae62c09bf07c5229d1f9397d94 diff --git a/pipelined/regression/lint-wally b/pipelined/regression/lint-wally index 564973a39..e68d13c25 100755 --- a/pipelined/regression/lint-wally +++ b/pipelined/regression/lint-wally @@ -5,9 +5,9 @@ export PATH=$PATH:/usr/local/bin/ verilator=`which verilator` basepath=$(dirname $0)/.. -for config in rv32e rv64gc rv32gc rv32ic ; do +for config in rv64gc rv32e rv32gc rv32ic ; do echo "$config linting..." - if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes); then + if !($verilator --Wall --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes); then echo "Exiting after $config lint due to errors or warnings" exit 1 fi diff --git a/pipelined/src/cache/sram1p1rw.sv b/pipelined/src/cache/sram1p1rw.sv index 5a7da75dd..ac16ae9bf 100644 --- a/pipelined/src/cache/sram1p1rw.sv +++ b/pipelined/src/cache/sram1p1rw.sv @@ -43,7 +43,6 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) ( logic [WIDTH-1:0] StoredData[DEPTH-1:0]; logic [$clog2(DEPTH)-1:0] AdrD; - logic WriteEnableD; always_ff @(posedge clk) AdrD <= Adr; diff --git a/pipelined/src/fpu/fma.sv b/pipelined/src/fpu/fma.sv index db8ecaf2f..69d6fc8ee 100644 --- a/pipelined/src/fpu/fma.sv +++ b/pipelined/src/fpu/fma.sv @@ -41,7 +41,7 @@ module fma( input logic [`NE-1:0] XExpE, YExpE, ZExpE, // input exponents - execute stage input logic [`NF:0] XManE, YManE, ZManE, // input mantissa - execute stage input logic XSgnM, YSgnM, // input signs - memory stage - input logic [`NE-1:0] XExpM, YExpM, ZExpM, // input exponents - memory stage + input logic [`NE-1:0] ZExpM, // input exponents - memory stage input logic [`NF:0] XManM, YManM, ZManM, // input mantissa - memory stage input logic XDenormE, YDenormE, ZDenormE, // is denorm input logic XZeroE, YZeroE, ZZeroE, // is zero - execute stage @@ -85,7 +85,7 @@ module fma( {AddendStickyE, KillProdE, InvZE, NormCntE, NegSumE, ZSgnEffE, PSgnE, FOpCtrlE[2]&~FOpCtrlE[1]&~FOpCtrlE[0]}, {AddendStickyM, KillProdM, InvZM, NormCntM, NegSumM, ZSgnEffM, PSgnM, Mult}); - fma2 fma2(.XSgnM, .YSgnM, .XExpM, .YExpM, .ZExpM, .XManM, .YManM, .ZManM, + fma2 fma2(.XSgnM, .YSgnM, .ZExpM, .XManM, .YManM, .ZManM, .FrmM, .FmtM, .ProdExpM, .AddendStickyM, .KillProdM, .SumM, .NegSumM, .InvZM, .NormCntM, .ZSgnEffM, .PSgnM, .XZeroM, .YZeroM, .ZZeroM, .XInfM, .YInfM, .ZInfM, .XNaNM, .YNaNM, .ZNaNM, .XSNaNM, .YSNaNM, .ZSNaNM, .Mult, .FMAResM, .FMAFlgM); @@ -283,6 +283,7 @@ module align( // - Denormal numbers have a diffrent exponent value depending on the precision assign ZExpVal = ZDenormE ? Denorm : ZExpE; // assign AlignCnt = ProdExpE - {2'b0, ZExpVal} + (`NF+3); + // *** can we use ProdExpE instead of XExp/YExp to save an adder? DH 5/12/22 assign AlignCnt = XZeroE|YZeroE ? -1 : {2'b0, XExpVal} + {2'b0, YExpVal} - {2'b0, (`NE)'(`BIAS)} + `NF+3 - {2'b0, ZExpVal}; // Defualt Addition without shifting @@ -433,7 +434,7 @@ endmodule module fma2( input logic XSgnM, YSgnM, // input signs - input logic [`NE-1:0] XExpM, YExpM, ZExpM, // input exponents + input logic [`NE-1:0] ZExpM, // input exponents input logic [`NF:0] XManM, YManM, ZManM, // input mantissas input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude input logic [`FPSIZES/3:0] FmtM, // precision 1 = double 0 = single @@ -481,7 +482,7 @@ module fma2( // Normalization /////////////////////////////////////////////////////////////////////////////// - normalize normalize(.SumM, .ZExpM, .ProdExpM, .NormCntM, .FmtM, .KillProdM, .AddendStickyM, .NormSum, .NegSumM, + normalize normalize(.SumM, .ZExpM, .ProdExpM, .NormCntM, .FmtM, .KillProdM, .AddendStickyM, .NormSum, .SumZero, .NormSumSticky, .UfSticky, .SumExp, .ResultDenorm); @@ -529,7 +530,7 @@ module fma2( // Select the result /////////////////////////////////////////////////////////////////////////////// - resultselect resultselect(.XSgnM, .YSgnM, .XExpM, .YExpM, .ZExpM, .XManM, .YManM, .ZManM, + resultselect resultselect(.XSgnM, .YSgnM, .ZExpM, .XManM, .YManM, .ZManM, .FrmM, .FmtM, .AddendStickyM, .KillProdM, .XInfM, .YInfM, .ZInfM, .XNaNM, .YNaNM, .ZNaNM, .RoundAdd, .ZSgnEffM, .PSgnM, .ResultSgn, .CalcPlus1, .Invalid, .Overflow, .Underflow, .ResultDenorm, .ResultExp, .ResultFrac, .FMAResM); @@ -577,7 +578,6 @@ module normalize( input logic [`FPSIZES/3:0] FmtM, // precision 1 = double 0 = single input logic KillProdM, // is the product set to zero input logic AddendStickyM, // the sticky bit caclulated from the aligned addend - input logic NegSumM, // was the sum negitive output logic [`NF+2:0] NormSum, // normalized sum output logic SumZero, // is the sum zero output logic NormSumSticky, UfSticky, // sticky bits @@ -1095,7 +1095,7 @@ endmodule module resultselect( input logic XSgnM, YSgnM, // input signs - input logic [`NE-1:0] XExpM, YExpM, ZExpM, // input exponents + input logic [`NE-1:0] ZExpM, // input exponents input logic [`NF:0] XManM, YManM, ZManM, // input mantissas input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude input logic [`FPSIZES/3:0] FmtM, // precision 1 = double 0 = single diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index 0fc9e8635..b8105cf92 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -87,7 +87,7 @@ module fpu ( logic XSgnE, YSgnE, ZSgnE; // input's sign - execute stage logic XSgnM, YSgnM; // input's sign - memory stage logic [10:0] XExpE, YExpE, ZExpE; // input's exponent - execute stage - logic [10:0] XExpM, YExpM, ZExpM; // input's exponent - memory stage + logic [10:0] ZExpM; // input's exponent - memory stage logic [52:0] XManE, YManE, ZManE; // input's fraction - execute stage logic [52:0] XManM, YManM, ZManM; // input's fraction - memory stage logic XNaNE, YNaNE, ZNaNE; // is the input a NaN - execute stage @@ -189,7 +189,7 @@ module fpu ( fma fma (.clk, .reset, .FlushM, .StallM, .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, - .XSgnM, .YSgnM, .XExpM, .YExpM, .ZExpM, .XManM, .YManM, .ZManM, + .XSgnM, .YSgnM, .ZExpM, .XManM, .YManM, .ZManM, .XNaNM, .YNaNM, .ZNaNM, .XZeroM, .YZeroM, .ZZeroM, .XInfM, .YInfM, .ZInfM, .XSNaNM, .YSNaNM, .ZSNaNM, .FOpCtrlE, diff --git a/pipelined/src/mmu/tlbcontrol.sv b/pipelined/src/mmu/tlbcontrol.sv index 3ab7a5c2a..5a9e4852d 100644 --- a/pipelined/src/mmu/tlbcontrol.sv +++ b/pipelined/src/mmu/tlbcontrol.sv @@ -58,8 +58,6 @@ module tlbcontrol #(parameter ITLB = 0) ( ); // Sections of the page table entry - logic [11:0] PageOffset; - logic [`SVMODE_BITS-1:0] SVMode; logic [1:0] EffectivePrivilegeMode; logic PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R, PTE_V; // Useful PTE Control Bits diff --git a/pipelined/src/ppa/ppa.sv b/pipelined/src/ppa/ppa.sv deleted file mode 100644 index 3fdbbfae3..000000000 --- a/pipelined/src/ppa/ppa.sv +++ /dev/null @@ -1,324 +0,0 @@ -// ppa.sv -// Teo Ene & David_Harris@hmc.edu 11 May 2022 -// & mmasserfrye@hmc.edu -// Measure PPA of various building blocks - -module ppa_comparator_16 #(parameter WIDTH=16) ( - input logic [WIDTH-1:0] a, b, - input logic sgnd, - output logic [1:0] flags); - - ppa_comparator #(WIDTH) comp (.*); -endmodule - -module ppa_comparator_32 #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] a, b, - input logic sgnd, - output logic [1:0] flags); - - ppa_comparator #(WIDTH) comp (.*); -endmodule - -module ppa_comparator_64 #(parameter WIDTH=64) ( - input logic [WIDTH-1:0] a, b, - input logic sgnd, - output logic [1:0] flags); - - ppa_comparator #(WIDTH) comp (.*); -endmodule - -module ppa_comparator #(parameter WIDTH=16) ( - input logic [WIDTH-1:0] a, b, - input logic sgnd, - output logic [1:0] flags); - - logic eq, lt, ltu; - logic [WIDTH-1:0] af, bf; - - // For signed numbers, flip most significant bit - assign af = {a[WIDTH-1] ^ sgnd, a[WIDTH-2:0]}; - assign bf = {b[WIDTH-1] ^ sgnd, b[WIDTH-2:0]}; - - // behavioral description gives best results - assign eq = (af == bf); - assign lt = (af < bf); - assign flags = {eq, lt}; -endmodule - -module ppa_add_16 #(parameter WIDTH=16) ( - input logic [WIDTH-1:0] a, b, - output logic [WIDTH-1:0] y); - - assign y = a + b; -endmodule - -module ppa_add_32 #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] a, b, - output logic [WIDTH-1:0] y); - - assign y = a + b; -endmodule - -module ppa_add_64 #(parameter WIDTH=64) ( - input logic [WIDTH-1:0] a, b, - output logic [WIDTH-1:0] y); - - assign y = a + b; -endmodule - -module ppa_mult_16 #(parameter WIDTH=16) ( - input logic [WIDTH-1:0] a, b, - output logic [WIDTH*2-1:0] y); //is this right width - assign y = a * b; -endmodule - -module ppa_mult_32 #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] a, b, - output logic [WIDTH*2-1:0] y); //is this right width - assign y = a * b; -endmodule - -module ppa_mult_64 #(parameter WIDTH=64) ( - input logic [WIDTH-1:0] a, b, - output logic [WIDTH*2-1:0] y); //is this right width - assign y = a * b; -endmodule - -module ppa_alu #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] A, B, - input logic [2:0] ALUControl, - input logic [2:0] Funct3, - output logic [WIDTH-1:0] Result, - output logic [WIDTH-1:0] Sum); - - logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult; - logic Carry, Neg; - logic LT, LTU; - logic W64, SubArith, ALUOp; - logic [2:0] ALUFunct; - logic Asign, Bsign; - - // Extract control signals - // W64 indicates RV64 W-suffix instructions acting on lower 32-bit word - // SubArith indicates subtraction - // ALUOp = 0 for address generation addition or 1 for regular ALU - assign {W64, SubArith, ALUOp} = ALUControl; - - // addition - assign CondInvB = SubArith ? ~B : B; - assign {Carry, Sum} = A + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; - - // Shifts - shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift)); - - // condition code flags based on subtract output Sum = A-B - // Overflow occurs when the numbers being subtracted have the opposite sign - // and the result has the opposite sign of A - assign Neg = Sum[WIDTH-1]; - assign Asign = A[WIDTH-1]; - assign Bsign = B[WIDTH-1]; - assign LT = Asign & ~Bsign | Asign & Neg | ~Bsign & Neg; // simplified from Overflow = Asign & Bsign & Asign & Neg; LT = Neg ^ Overflow - assign LTU = ~Carry; - - // SLT - assign SLT = {{(WIDTH-1){1'b0}}, LT}; - assign SLTU = {{(WIDTH-1){1'b0}}, LTU}; - - // Select appropriate ALU Result - assign ALUFunct = Funct3 & {3{ALUOp}}; // Force ALUFunct to 0 to Add when ALUOp = 0 - always_comb - casez (ALUFunct) - 3'b000: FullResult = Sum; // add or sub - 3'b?01: FullResult = Shift; // sll, sra, or srl - 3'b010: FullResult = SLT; // slt - 3'b011: FullResult = SLTU; // sltu - 3'b100: FullResult = A ^ B; // xor - 3'b110: FullResult = A | B; // or - 3'b111: FullResult = A & B; // and - endcase - - // support W-type RV64I ADDW/SUBW/ADDIW/Shifts that sign-extend 32-bit result to 64 bits - if (WIDTH==64) assign Result = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; - else assign Result = FullResult; -endmodule - -module ppa_shiftleft #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] a, - input logic [$clog2(WIDTH)-1:0] amt, - output logic [WIDTH-1:0] y); - - assign y = a << amt; -endmodule - -module ppa_shifter ( - input logic [`XLEN-1:0] A, - input logic [`LOG_XLEN-1:0] Amt, - input logic Right, Arith, W64, - output logic [`XLEN-1:0] Y); - - logic [2*`XLEN-2:0] z, zshift; - logic [`LOG_XLEN-1:0] amttrunc, offset; - - // Handle left and right shifts with a funnel shifter. - // For RV32, only 32-bit shifts are needed. - // For RV64, 32 and 64-bit shifts are needed, with sign extension. - - // funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong) - if (`XLEN==32) begin:shifter // RV32 - always_comb // funnel mux - if (Right) - if (Arith) z = {{31{A[31]}}, A}; - else z = {31'b0, A}; - else z = {A, 31'b0}; - assign amttrunc = Amt; // shift amount - end else begin:shifter // RV64 - always_comb // funnel mux - if (W64) begin // 32-bit shifts - if (Right) - if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]}; - else z = {95'b0, A[31:0]}; - else z = {32'b0, A[31:0], 63'b0}; - end else begin - if (Right) - if (Arith) z = {{63{A[63]}}, A}; - else z = {63'b0, A}; - else z = {A, 63'b0}; - end - assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32 or 64-bit shift - end - - // opposite offset for right shfits - assign offset = Right ? amttrunc : ~amttrunc; - - // funnel operation - assign zshift = z >> offset; - assign Y = zshift[`XLEN-1:0]; -endmodule - -module ppa_prioritythermometer #(parameter N = 8) ( - input logic [N-1:0] a, - output logic [N-1:0] y); - - // Carefully crafted so design compiler will synthesize into a fast tree structure - // Rather than linear. - - // create thermometer code mask - genvar i; - assign y[0] = ~a[0]; - for (i=1; i Date: Thu, 12 May 2022 14:49:58 +0000 Subject: [PATCH 05/14] Clean up unused signals --- pipelined/src/lsu/atomic.sv | 4 ++-- pipelined/src/lsu/lrsc.sv | 2 +- pipelined/src/lsu/lsu.sv | 2 +- pipelined/src/mmu/hptw.sv | 1 - pipelined/src/muldiv/muldiv.sv | 2 +- pipelined/src/privileged/csr.sv | 6 +++--- pipelined/src/privileged/csrc.sv | 2 +- pipelined/src/privileged/csri.sv | 1 - pipelined/src/privileged/privileged.sv | 10 +++++----- pipelined/src/privileged/trap.sv | 5 ++--- pipelined/src/wally/wallypipelinedcore.sv | 5 ++--- 11 files changed, 18 insertions(+), 22 deletions(-) diff --git a/pipelined/src/lsu/atomic.sv b/pipelined/src/lsu/atomic.sv index a5dd06ac4..5a0753974 100644 --- a/pipelined/src/lsu/atomic.sv +++ b/pipelined/src/lsu/atomic.sv @@ -32,7 +32,7 @@ module atomic ( input logic clk, - input logic reset, FlushW, StallW, + input logic reset, StallW, input logic [`XLEN-1:0] ReadDataM, input logic [`XLEN-1:0] LSUWriteDataM, input logic [`PA_BITS-1:0] LSUPAdrM, @@ -52,7 +52,7 @@ module atomic ( .result(AMOResult)); mux2 #(`XLEN) wdmux(LSUWriteDataM, AMOResult, LSUAtomicM[1], AMOWriteDataM); assign MemReadM = PreLSURWM[1] & ~IgnoreRequest; - lrsc lrsc(.clk, .reset, .FlushW, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .LSUPAdrM, + lrsc lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .LSUPAdrM, .SquashSCW, .LSURWM); endmodule diff --git a/pipelined/src/lsu/lrsc.sv b/pipelined/src/lsu/lrsc.sv index 66b2ac3d6..a99f6f838 100644 --- a/pipelined/src/lsu/lrsc.sv +++ b/pipelined/src/lsu/lrsc.sv @@ -34,7 +34,7 @@ module lrsc ( input logic clk, reset, - input logic FlushW, StallW, + input logic StallW, input logic MemReadM, input logic [1:0] PreLSURWM, output logic [1:0] LSURWM, diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index eaad232df..b7ecb868f 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -251,7 +251,7 @@ module lsu ( // Atomic operations ///////////////////////////////////////////////////////////////////////////////////////////// if (`A_SUPPORTED) begin:atomic - atomic atomic(.clk, .reset, .FlushW, .StallW, .ReadDataM, .LSUWriteDataM, .LSUPAdrM, + atomic atomic(.clk, .reset, .StallW, .ReadDataM, .LSUWriteDataM, .LSUPAdrM, .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest, .AMOWriteDataM, .SquashSCW, .LSURWM); end else begin:lrsc diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv index eb0fc9bd0..f96d69f0d 100644 --- a/pipelined/src/mmu/hptw.sv +++ b/pipelined/src/mmu/hptw.sv @@ -61,7 +61,6 @@ module hptw logic DTLBWalk; // register TLBs translation miss requests logic [`PPN_BITS-1:0] BasePageTablePPN; logic [`PPN_BITS-1:0] CurrentPPN; - logic MemWrite; logic Executable, Writable, Readable, Valid, PTE_U; logic Misaligned, MegapageMisaligned; logic ValidPTE, LeafPTE, ValidLeafPTE, ValidNonLeafPTE; diff --git a/pipelined/src/muldiv/muldiv.sv b/pipelined/src/muldiv/muldiv.sv index 53eef5eb7..5fa717e5f 100644 --- a/pipelined/src/muldiv/muldiv.sv +++ b/pipelined/src/muldiv/muldiv.sv @@ -41,7 +41,6 @@ module muldiv ( output logic [`XLEN-1:0] MDUResultW, // Divide Done output logic DivBusyE, - output logic DivE, // hazards input logic StallM, StallW, FlushM, FlushW, TrapM ); @@ -52,6 +51,7 @@ module muldiv ( logic [`XLEN*2-1:0] ProdM; logic DivSignedE; + logic DivE; logic W64M; // Multiplier diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index 0cae3905e..5fee3d384 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -41,7 +41,7 @@ module csr #(parameter input logic StallE, StallM, StallW, input logic [31:0] InstrM, input logic [`XLEN-1:0] PCM, SrcAM, - input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, wfiM, InterruptM, + input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, mretM, sretM, wfiM, InterruptM, input logic MTimerInt, MExtInt, SExtInt, MSwInt, input logic [63:0] MTIME_CLINT, input logic InstrValidM, FRegWriteM, LoadStallD, @@ -135,7 +135,7 @@ module csr #(parameter csri csri(.clk, .reset, .InstrValidNotFlushedM, .StallW, .CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM, .MExtInt, .SExtInt, .MTimerInt, .MSwInt, - .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .MIDELEG_REGW, .IP_REGW_writeable); + .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .IP_REGW_writeable); csrsr csrsr(.clk, .reset, .StallW, .WriteMSTATUSM, .WriteMSTATUSHM, .WriteSSTATUSM, .TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW, @@ -145,7 +145,7 @@ module csr #(parameter .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM, .STATUS_FS, .BigEndianM); csrc counters(.clk, .reset, - .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW, + .StallE, .StallM, .StallW, .FlushM, .FlushW, .InstrValidM, .LoadStallD, .CSRMWriteM, .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, diff --git a/pipelined/src/privileged/csrc.sv b/pipelined/src/privileged/csrc.sv index 9d1417985..dbb6af756 100644 --- a/pipelined/src/privileged/csrc.sv +++ b/pipelined/src/privileged/csrc.sv @@ -43,7 +43,7 @@ module csrc #(parameter ) ( input logic clk, reset, input logic StallE, StallM, StallW, - input logic FlushE, FlushM, FlushW, + input logic FlushM, FlushW, input logic InstrValidM, LoadStallD, CSRMWriteM, input logic BPPredDirWrongM, input logic BTBPredPCWrongM, diff --git a/pipelined/src/privileged/csri.sv b/pipelined/src/privileged/csri.sv index 5089b0f86..672a7acca 100644 --- a/pipelined/src/privileged/csri.sv +++ b/pipelined/src/privileged/csri.sv @@ -43,7 +43,6 @@ module csri #(parameter input logic [`XLEN-1:0] CSRWriteValM, input logic [11:0] CSRAdrM, (* mark_debug = "true" *) input logic MExtInt, SExtInt, MTimerInt, MSwInt, - input logic [11:0] MIDELEG_REGW, output logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, (* mark_debug = "true" *) output logic [11:0] IP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0 ); diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index 523326a31..ecec2b23e 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -39,7 +39,7 @@ module privileged ( output logic [`XLEN-1:0] PrivilegedNextPCM, output logic RetM, TrapM, output logic ITLBFlushF, DTLBFlushM, - input logic InstrValidM, CommittedM, DivE, + input logic InstrValidM, CommittedM, input logic FRegWriteM, LoadStallD, input logic BPPredDirWrongM, input logic BTBPredPCWrongM, @@ -97,7 +97,7 @@ module privileged ( logic InstrAccessFaultD, InstrAccessFaultE, InstrAccessFaultM; logic IllegalInstrFaultM; - logic MTrapM, STrapM, UTrapM; + logic MTrapM, STrapM; (* mark_debug = "true" *) logic InterruptM; logic STATUS_SPP, STATUS_TSR, STATUS_TW, STATUS_TVM; @@ -158,7 +158,7 @@ module privileged ( .FlushE, .FlushM, .FlushW, .StallE, .StallM, .StallW, .InstrM, .PCM, .SrcAM, - .CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .UTrapM, .mretM, .sretM, .wfiM, .InterruptM, + .CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .mretM, .sretM, .wfiM, .InterruptM, .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, @@ -225,8 +225,8 @@ module privileged ( .PCM, .IEUAdrM, .InstrM, - .InstrValidM, .CommittedM, .DivE, - .TrapM, .MTrapM, .STrapM, .UTrapM, .RetM, + .InstrValidM, .CommittedM, + .TrapM, .MTrapM, .STrapM, .RetM, .InterruptM, .IntPendingM, .ExceptionM, .PrivilegedNextPCM, .CauseM, .NextFaultMtvalM); diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index 953696a9a..2fc393032 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -46,8 +46,8 @@ module trap ( input logic [`XLEN-1:0] PCM, input logic [`XLEN-1:0] IEUAdrM, input logic [31:0] InstrM, - input logic InstrValidM, CommittedM, DivE, - output logic TrapM, MTrapM, STrapM, UTrapM, RetM, + input logic InstrValidM, CommittedM, + output logic TrapM, MTrapM, STrapM, RetM, output logic InterruptM, IntPendingM, output logic ExceptionM, output logic [`XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM @@ -59,7 +59,6 @@ module trap ( (* mark_debug = "true" *) logic [11:0] PendingIntsM, ValidIntsM; //logic InterruptM; logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector; - logic Exception1M; // Determine pending enabled interrupts // interrupt if any sources are pending diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index ab0d0d309..e165adc37 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -86,7 +86,6 @@ module wallypipelinedcore ( logic PCSrcE; logic CSRWritePendingDEM; logic DivBusyE; - logic DivE; logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD; logic SquashSCW; // floating point unit signals @@ -323,7 +322,7 @@ module wallypipelinedcore ( .InstrM, .CSRReadValW, .PrivilegedNextPCM, .RetM, .TrapM, .ITLBFlushF, .DTLBFlushM, - .InstrValidM, .CommittedM, .DivE, + .InstrValidM, .CommittedM, .FRegWriteM, .LoadStallD, .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM, @@ -360,7 +359,7 @@ module wallypipelinedcore ( .clk, .reset, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E, - .MDUResultW, .DivBusyE, .DivE, + .MDUResultW, .DivBusyE, .StallM, .StallW, .FlushM, .FlushW, .TrapM ); end else begin // no M instructions supported From e2dea3bb89c99243bded9d9cd7f79e7fac9941d3 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 15:10:10 +0000 Subject: [PATCH 06/14] Removed more unused signals, simplified csri state --- pipelined/src/fpu/fpu.sv | 4 +-- pipelined/src/privileged/csr.sv | 11 ++++---- pipelined/src/privileged/csri.sv | 35 ++++++++------------------ pipelined/src/privileged/csrs.sv | 9 +++---- pipelined/src/privileged/privileged.sv | 6 ++--- pipelined/src/privileged/trap.sv | 2 +- pipelined/testbench/testbench-linux.sv | 6 ++--- 7 files changed, 27 insertions(+), 46 deletions(-) diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index b8105cf92..47f29a198 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -253,8 +253,8 @@ module fpu ( // E/M pipe registers // flopenrc #(64) EMFpReg1(clk, reset, FlushM, ~StallM, FSrcXE, FSrcXM); - flopenrc #(65) EMFpReg2 (clk, reset, FlushM, ~StallM, {XSgnE,XExpE,XManE}, {XSgnM,XExpM,XManM}); - flopenrc #(65) EMFpReg3 (clk, reset, FlushM, ~StallM, {YSgnE,YExpE,YManE}, {YSgnM,YExpM,YManM}); + flopenrc #(55) EMFpReg2 (clk, reset, FlushM, ~StallM, {XSgnE,XManE}, {XSgnM,XManM}); + flopenrc #(55) EMFpReg3 (clk, reset, FlushM, ~StallM, {YSgnE,YManE}, {YSgnM,YManM}); flopenrc #(64) EMFpReg4 (clk, reset, FlushM, ~StallM, {ZExpE,ZManE}, {ZExpM,ZManM}); flopenrc #(12) EMFpReg5 (clk, reset, FlushM, ~StallM, {XZeroE, YZeroE, ZZeroE, XInfE, YInfE, ZInfE, XNaNE, YNaNE, ZNaNE, XSNaNE, YSNaNE, ZSNaNE}, diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index 5fee3d384..20114b15a 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -62,7 +62,7 @@ module csr #(parameter output logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW, output logic [`XLEN-1:0] MEDELEG_REGW, output logic [`XLEN-1:0] SATP_REGW, - output logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, MIDELEG_REGW, + output logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, output logic STATUS_MIE, STATUS_SIE, output logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, STATUS_TW, output logic [1:0] STATUS_FS, @@ -71,7 +71,6 @@ module csr #(parameter input logic [4:0] SetFflagsM, output logic [2:0] FRM_REGW, -// output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW, output logic [`XLEN-1:0] CSRReadValW, output logic IllegalCSRAccessM, BigEndianM ); @@ -96,7 +95,7 @@ module csr #(parameter logic IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM, InsufficientCSRPrivilegeM; logic IllegalCSRMWriteReadonlyM; logic [`XLEN-1:0] CSRReadVal2M; - logic [11:0] IP_REGW_writeable; + logic [11:0] MIP_REGW_writeable; logic InstrValidNotFlushedM; assign InstrValidNotFlushedM = ~StallW & ~FlushW; @@ -107,7 +106,7 @@ module csr #(parameter CSRSrcM = InstrM[14] ? {{(`XLEN-5){1'b0}}, InstrM[19:15]} : SrcAM; // CSR set and clear for MIP/SIP should only touch internal state, not interrupt inputs - if (CSRAdrM == MIP | CSRAdrM == SIP) CSRReadVal2M = {{(`XLEN-12){1'b0}}, IP_REGW_writeable}; + if (CSRAdrM == MIP | CSRAdrM == SIP) CSRReadVal2M = {{(`XLEN-12){1'b0}}, MIP_REGW_writeable}; else CSRReadVal2M = CSRReadValM; // Compute AND/OR modification @@ -135,7 +134,7 @@ module csr #(parameter csri csri(.clk, .reset, .InstrValidNotFlushedM, .StallW, .CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM, .MExtInt, .SExtInt, .MTimerInt, .MSwInt, - .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .IP_REGW_writeable); + .MIP_REGW, .MIE_REGW, .MIP_REGW_writeable); csrsr csrsr(.clk, .reset, .StallW, .WriteMSTATUSM, .WriteMSTATUSHM, .WriteSSTATUSM, .TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW, @@ -166,7 +165,7 @@ module csr #(parameter .STATUS_TVM, .CSRWriteValM, .PrivilegeModeW, .CSRSReadValM, .STVEC_REGW, .SEPC_REGW, .SCOUNTEREN_REGW, - .SATP_REGW, .SIP_REGW, .SIE_REGW, + .SATP_REGW, .MIP_REGW, .MIE_REGW, .WriteSSTATUSM, .IllegalCSRSAccessM); csru csru(.clk, .reset, .InstrValidNotFlushedM, .StallW, .CSRUWriteM, .CSRAdrM, .CSRWriteValM, .STATUS_FS, .CSRUReadValM, diff --git a/pipelined/src/privileged/csri.sv b/pipelined/src/privileged/csri.sv index 672a7acca..bebad50dd 100644 --- a/pipelined/src/privileged/csri.sv +++ b/pipelined/src/privileged/csri.sv @@ -43,11 +43,10 @@ module csri #(parameter input logic [`XLEN-1:0] CSRWriteValM, input logic [11:0] CSRAdrM, (* mark_debug = "true" *) input logic MExtInt, SExtInt, MTimerInt, MSwInt, - output logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, - (* mark_debug = "true" *) output logic [11:0] IP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0 + output logic [11:0] MIP_REGW, MIE_REGW, + (* mark_debug = "true" *) output logic [11:0] MIP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0 ); - logic [11:0] IP_REGW, IE_REGW; logic [11:0] MIP_WRITE_MASK, SIP_WRITE_MASK, MIE_WRITE_MASK; logic WriteMIPM, WriteMIEM, WriteSIPM, WriteSIEM; @@ -62,8 +61,8 @@ module csri #(parameter // SEIP, STIP, SSIP is writable in MIP if S mode exists // SSIP is writable in SIP if S mode exists if (`S_SUPPORTED) begin:mask - assign MIP_WRITE_MASK = 12'h222; // SEIP, STIP, SSIP are writable in MIP (20210108-draft 3.1.9) - assign SIP_WRITE_MASK = 12'h002; // SSIP is writable in SIP (privileged 20210108-draft 4.1.3) + assign MIP_WRITE_MASK = 12'h222; // SEIP, STIP, SSIP are writeable in MIP (20210108-draft 3.1.9) + assign SIP_WRITE_MASK = 12'h002; // SSIP is writeable in SIP (privileged 20210108-draft 4.1.3) assign MIE_WRITE_MASK = 12'hAAA; end else begin:mask assign MIP_WRITE_MASK = 12'h000; @@ -71,25 +70,13 @@ module csri #(parameter assign MIE_WRITE_MASK = 12'h888; end always @(posedge clk) - if (reset) IP_REGW_writeable <= 12'b0; - else if (WriteMIPM) IP_REGW_writeable <= (CSRWriteValM[11:0] & MIP_WRITE_MASK); - else if (WriteSIPM) IP_REGW_writeable <= (CSRWriteValM[11:0] & SIP_WRITE_MASK); + if (reset) MIP_REGW_writeable <= 12'b0; + else if (WriteMIPM) MIP_REGW_writeable <= (CSRWriteValM[11:0] & MIP_WRITE_MASK); + else if (WriteSIPM) MIP_REGW_writeable <= (CSRWriteValM[11:0] & SIP_WRITE_MASK) | (MIP_REGW_writeable & ~SIP_WRITE_MASK); always @(posedge clk) - if (reset) IE_REGW <= 12'b0; - else if (WriteMIEM) IE_REGW <= (CSRWriteValM[11:0] & MIE_WRITE_MASK); // MIE controls M and S fields - else if (WriteSIEM) IE_REGW <= (CSRWriteValM[11:0] & 12'h222) | (IE_REGW & 12'h888); // only S fields - - assign IP_REGW = {MExtInt,1'b0,SExtInt|IP_REGW_writeable[9],1'b0,MTimerInt,1'b0,IP_REGW_writeable[5],1'b0,MSwInt,1'b0,IP_REGW_writeable[1],1'b0}; - - assign MIP_REGW = IP_REGW; - assign MIE_REGW = IE_REGW; - - if (`S_SUPPORTED) begin - assign SIP_REGW = IP_REGW & 12'h222; - assign SIE_REGW = IE_REGW & 12'h222; - end else begin - assign SIP_REGW = 12'b0; - assign SIE_REGW = 12'b0; - end + if (reset) MIE_REGW <= 12'b0; + else if (WriteMIEM) MIE_REGW <= (CSRWriteValM[11:0] & MIE_WRITE_MASK); // MIE controls M and S fields + else if (WriteSIEM) MIE_REGW <= (CSRWriteValM[11:0] & 12'h222) | (MIE_REGW & 12'h888); // only S fields + assign MIP_REGW = {MExtInt,1'b0,SExtInt|MIP_REGW_writeable[9],1'b0,MTimerInt,1'b0,MIP_REGW_writeable[5],1'b0,MSwInt,1'b0,MIP_REGW_writeable[1],1'b0}; endmodule diff --git a/pipelined/src/privileged/csrs.sv b/pipelined/src/privileged/csrs.sv index fb0b5cef7..e707c770d 100644 --- a/pipelined/src/privileged/csrs.sv +++ b/pipelined/src/privileged/csrs.sv @@ -61,14 +61,11 @@ module csrs #(parameter (* mark_debug = "true" *) output logic [`XLEN-1:0] SEPC_REGW, output logic [31:0] SCOUNTEREN_REGW, output logic [`XLEN-1:0] SATP_REGW, - (* mark_debug = "true" *) input logic [11:0] SIP_REGW, SIE_REGW, + (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, output logic WriteSSTATUSM, output logic IllegalCSRSAccessM ); - //logic [`XLEN-1:0] zero = 0; - //logic [31:0] allones = {32{1'b1}}; - //logic [`XLEN-1:0] SEDELEG_MASK = ~(zero | 3'b111 << 9); // sedeleg[11:9] hardwired to zero per Privileged Spec 3.1.8 // Supervisor mode CSRs sometimes supported if (`S_SUPPORTED) begin:csrs @@ -105,8 +102,8 @@ module csrs #(parameter case (CSRAdrM) SSTATUS: CSRSReadValM = SSTATUS_REGW; STVEC: CSRSReadValM = STVEC_REGW; - SIP: CSRSReadValM = {{(`XLEN-12){1'b0}}, SIP_REGW}; - SIE: CSRSReadValM = {{(`XLEN-12){1'b0}}, SIE_REGW}; + SIP: CSRSReadValM = {{(`XLEN-12){1'b0}}, MIP_REGW & 12'h222}; // only read supervisor fields + SIE: CSRSReadValM = {{(`XLEN-12){1'b0}}, MIE_REGW & 12'h222}; // only read supervisor fields SSCRATCH: CSRSReadValM = SSCRATCH_REGW; SEPC: CSRSReadValM = SEPC_REGW; SCAUSE: CSRSReadValM = SCAUSE_REGW; diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index ecec2b23e..05a98eb11 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -102,7 +102,7 @@ module privileged ( logic STATUS_SPP, STATUS_TSR, STATUS_TW, STATUS_TVM; logic STATUS_MIE, STATUS_SIE; - logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW; + logic [11:0] MIP_REGW, MIE_REGW; logic md; logic StallMQ; logic WFITimeoutM; @@ -171,7 +171,7 @@ module privileged ( .MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW, .MEDELEG_REGW, .SATP_REGW, - .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .MIDELEG_REGW, + .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW, .STATUS_FS, .PMPCFG_ARRAY_REGW, @@ -220,7 +220,7 @@ module privileged ( .mretM, .sretM, .PrivilegeModeW, .NextPrivilegeModeM, .MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW, - .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .MIDELEG_REGW, + .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .STATUS_MIE, .STATUS_SIE, .PCM, .IEUAdrM, diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index 2fc393032..1b8e562b9 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -41,7 +41,7 @@ module trap ( (* mark_debug = "true" *) input logic mretM, sretM, input logic [1:0] PrivilegeModeW, NextPrivilegeModeM, (* mark_debug = "true" *) input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW, - (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, MIDELEG_REGW, + (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, input logic STATUS_MIE, STATUS_SIE, input logic [`XLEN-1:0] PCM, input logic [`XLEN-1:0] IEUAdrM, diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index d18ba9994..0173e35b3 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -146,8 +146,8 @@ module testbench; `define HPMCOUNTER `CSR_BASE.counters.counters.HPMCOUNTER_REGW `define MEDELEG `CSR_BASE.csrm.deleg.MEDELEGreg.q `define MIDELEG `CSR_BASE.csrm.deleg.MIDELEGreg.q - `define MIE `CSR_BASE.csri.IE_REGW - `define MIP `CSR_BASE.csri.IP_REGW_writeable + `define MIE `CSR_BASE.csri.MIE_REGW + `define MIP `CSR_BASE.csri.MIP_REGW_writeable `define MCAUSE `CSR_BASE.csrm.MCAUSEreg.q `define SCAUSE `CSR_BASE.csrs.csrs.SCAUSEreg.q `define MEPC `CSR_BASE.csrm.MEPCreg.q @@ -692,8 +692,6 @@ module testbench; "sstatus": `checkCSR(`CSR_BASE.csrs.SSTATUS_REGW) "mtvec": `checkCSR(`CSR_BASE.csrm.MTVEC_REGW) "mie": `checkCSR(`CSR_BASE.csrm.MIE_REGW) - "sip": `checkCSR(`CSR_BASE.csrs.SIP_REGW) - "sie": `checkCSR(`CSR_BASE.csrs.SIE_REGW) "mideleg": `checkCSR(`CSR_BASE.csrm.MIDELEG_REGW) "medeleg": `checkCSR(`CSR_BASE.csrm.MEDELEG_REGW) "mepc": `checkCSR(`CSR_BASE.csrm.MEPC_REGW) From 7e764fbda1c63882e23a416f9b8e4baaf5de270e Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 15:15:30 +0000 Subject: [PATCH 07/14] More unused signal cleanup --- pipelined/src/fpu/fpu.sv | 19 +++---------------- pipelined/src/fpu/fsgn.sv | 1 - pipelined/src/ieu/datapath.sv | 4 ---- pipelined/src/privileged/privileged.sv | 2 +- pipelined/src/privileged/trap.sv | 3 +-- 5 files changed, 5 insertions(+), 24 deletions(-) diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index 47f29a198..5149b05e8 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -212,25 +212,12 @@ module fpu ( .XNaNQ, .YNaNQ, .XInfQ, .YInfQ, .XZeroQ, .YZeroQ, .load_preload, .FDivBusyE, .done(FDivSqrtDoneE), .AS_Result(FDivResM), .Flags(FDivFlgM)); - // convert from signle to double and vice versa + // other FP execution units cvtfp cvtfp (.XExpE, .XManE, .XSgnE, .XZeroE, .XDenormE, .XInfE, .XNaNE, .XSNaNE, .FrmE, .FmtE, .CvtFpResE, .CvtFpFlgE); - - // compare unit - // - computation is done in one stage - // - writes to FP file durring min/max instructions - // - other comparisons write a 1 or 0 to the integer register fcmp fcmp (.FmtE, .FOpCtrlE, .XSgnE, .YSgnE, .XExpE, .YExpE, .XManE, .YManE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .XSNaNE, .YSNaNE, .FSrcXE, .FSrcYE, .CmpNVE, .CmpResE); - - // sign injection unit - fsgn fsgn (.SgnOpCodeE(FOpCtrlE[1:0]), .XSgnE, .YSgnE, .FSrcXE, .FmtE, .XExpMaxE, - .SgnResE); - - // classify - fclassify fclassify (.XSgnE, .XDenormE, .XZeroE, .XNaNE, .XInfE, .XNormE, - .XSNaNE, .ClassResE); - - // Convert + fsgn fsgn (.SgnOpCodeE(FOpCtrlE[1:0]), .XSgnE, .YSgnE, .FSrcXE, .FmtE, .SgnResE); + fclassify fclassify (.XSgnE, .XDenormE, .XZeroE, .XNaNE, .XInfE, .XNormE, .XSNaNE, .ClassResE); fcvt fcvt (.XSgnE, .XExpE, .XManE, .XZeroE, .XNaNE, .XInfE, .XDenormE, .ForwardedSrcAE, .FOpCtrlE, .FmtE, .FrmE, .CvtResE, .CvtFlgE); diff --git a/pipelined/src/fpu/fsgn.sv b/pipelined/src/fpu/fsgn.sv index efe6ece34..b95fd078f 100755 --- a/pipelined/src/fpu/fsgn.sv +++ b/pipelined/src/fpu/fsgn.sv @@ -3,7 +3,6 @@ module fsgn ( input logic XSgnE, YSgnE, // X and Y sign bits input logic [63:0] FSrcXE, // X - input logic XExpMaxE, // max possible exponent (all ones) input logic FmtE, // precision 1 = double 0 = single input logic [1:0] SgnOpCodeE, // operation control output logic [63:0] SgnResE // result diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index 8178f1656..90b5f0335 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -77,11 +77,7 @@ module datapath ( // Execute stage signals logic [`XLEN-1:0] R1E, R2E; logic [`XLEN-1:0] ExtImmE; - - // logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, SrcAE2, SrcBE2; // *** MAde forwardedsrcae an output to get rid of a mux in the critical path. logic [`XLEN-1:0] SrcAE, SrcBE; - logic [`XLEN-1:0] SrcAE2, SrcBE2; - logic [`XLEN-1:0] ALUResultE, AltResultE, IEUResultE; // Memory stage signals logic [`XLEN-1:0] IEUResultM; diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index 05a98eb11..7d58228be 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -212,7 +212,7 @@ module privileged ( {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE}, {IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM, IllegalFPUInstrM}); // *** it should be possible to combine some of these faults earlier to reduce module boundary crossings and save flops dh 5 july 2021 - trap trap(.clk, .reset, + trap trap(.reset, .InstrMisalignedFaultM, .InstrAccessFaultM, .IllegalInstrFaultM, .BreakpointFaultM, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, .LoadAccessFaultM, .StoreAmoAccessFaultM, .EcallFaultM, .InstrPageFaultM, diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index 1b8e562b9..611378de3 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -32,8 +32,7 @@ `include "wally-config.vh" module trap ( - input logic clk, - input logic reset, + input logic reset, (* mark_debug = "true" *) input logic InstrMisalignedFaultM, InstrAccessFaultM, IllegalInstrFaultM, (* mark_debug = "true" *) input logic BreakpointFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM, (* mark_debug = "true" *) input logic LoadAccessFaultM, StoreAmoAccessFaultM, EcallFaultM, InstrPageFaultM, From 5acb52637543121e8a98f8f97cd83e040eac4f4a Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 15:21:09 +0000 Subject: [PATCH 08/14] More unused signal cleanup --- pipelined/src/ifu/ifu.sv | 3 --- pipelined/src/lsu/lsu.sv | 6 ++---- pipelined/src/privileged/privileged.sv | 4 +--- pipelined/src/privileged/trap.sv | 2 +- pipelined/src/wally/wallypipelinedcore.sv | 5 +---- 5 files changed, 5 insertions(+), 15 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index e8460def9..d10bb95f6 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -65,7 +65,6 @@ module ifu ( output logic InstrPageFaultF, output logic IllegalIEUInstrFaultD, output logic InstrMisalignedFaultM, - input logic ExceptionM, // mmu management input logic [1:0] PrivilegeModeW, input logic [`XLEN-1:0] PTE, @@ -183,11 +182,9 @@ module ifu ( localparam integer WORDSPERLINE = (CACHE_ENABLED) ? `ICACHE_LINELENINBITS/`XLEN : 1; localparam integer LINELEN = (CACHE_ENABLED) ? `ICACHE_LINELENINBITS : `XLEN; localparam integer LOGWPL = (`DMEM == `MEM_CACHE) ? $clog2(WORDSPERLINE) : 1; - logic [LINELEN-1:0] ReadDataLine; logic [LINELEN-1:0] ICacheBusWriteData; logic [`PA_BITS-1:0] ICacheBusAdr; logic ICacheBusAck; - logic [31:0] temp; logic SelUncachedAdr; busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index b7ecb868f..e6458385e 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -93,7 +93,7 @@ module lsu ( logic [6:0] LSUFunct7M; logic [1:0] LSUAtomicM; (* mark_debug = "true" *) logic [`XLEN+1:0] PreLSUPAdrM; - logic [11:0] PreLSUAdrE, LSUAdrE; + logic [11:0] LSUAdrE; logic CPUBusy; logic DCacheStallM; logic CacheableM; @@ -131,7 +131,7 @@ module lsu ( end else begin assign {InterlockStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = '0; assign IgnoreRequestTrapM = TrapM; assign CPUBusy = StallW; assign PreLSURWM = MemRWM; - assign LSUAdrE = PreLSUAdrE; assign PreLSUAdrE = IEUAdrE[11:0]; + assign LSUAdrE = IEUAdrE[11:0]; assign PreLSUPAdrM = IEUAdrExtM; assign LSUFunct3M = Funct3M; assign LSUFunct7M = Funct7M; assign LSUAtomicM = AtomicM; assign LSUWriteDataM = WriteDataM; @@ -202,13 +202,11 @@ module lsu ( localparam integer WORDSPERLINE = (CACHE_ENABLED) ? `DCACHE_LINELENINBITS/`XLEN : 1; localparam integer LINELEN = (CACHE_ENABLED) ? `DCACHE_LINELENINBITS : `XLEN; localparam integer LOGWPL = (CACHE_ENABLED) ? $clog2(WORDSPERLINE) : 1; - logic [LINELEN-1:0] ReadDataLineM; logic [LINELEN-1:0] DCacheBusWriteData; logic [`PA_BITS-1:0] DCacheBusAdr; logic DCacheWriteLine; logic DCacheFetchLine; logic DCacheBusAck; - logic SelBus; logic [LOGWPL-1:0] WordCount; busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busdp( diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index 7d58228be..ca3a34224 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -69,7 +69,6 @@ module privileged ( input logic StoreAmoAccessFaultM, input logic SelHPTW, - output logic ExceptionM, output logic IllegalFPUInstrE, output logic [1:0] PrivilegeModeW, output logic [`XLEN-1:0] SATP_REGW, @@ -228,8 +227,7 @@ module privileged ( .InstrValidM, .CommittedM, .TrapM, .MTrapM, .STrapM, .RetM, .InterruptM, .IntPendingM, - .ExceptionM, - .PrivilegedNextPCM, .CauseM, .NextFaultMtvalM); + .PrivilegedNextPCM, .CauseM, .NextFaultMtvalM); endmodule diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index 611378de3..4ae9a5fa9 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -48,13 +48,13 @@ module trap ( input logic InstrValidM, CommittedM, output logic TrapM, MTrapM, STrapM, RetM, output logic InterruptM, IntPendingM, - output logic ExceptionM, output logic [`XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM // output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW, // input logic WriteMIPM, WriteSIPM, WriteUIPM, WriteMIEM, WriteSIEM, WriteUIEM ); logic MIntGlobalEnM, SIntGlobalEnM; + logic ExceptionM; (* mark_debug = "true" *) logic [11:0] PendingIntsM, ValidIntsM; //logic InterruptM; logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector; diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index e165adc37..0ca52dc55 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -156,7 +156,6 @@ module wallypipelinedcore ( logic InstrAccessFaultF; logic [2:0] LSUBusSize; - logic ExceptionM; logic DCacheMiss; logic DCacheAccess; logic ICacheMiss; @@ -169,8 +168,6 @@ module wallypipelinedcore ( .clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushF, .FlushD, .FlushE, .FlushM, .FlushW, - - .ExceptionM, // Fetch .IFUBusHRDATA, .IFUBusAck, .PCF, .IFUBusAdr, .IFUBusRead, .IFUStallF, @@ -338,7 +335,7 @@ module wallypipelinedcore ( // *** do these need to be split up into one for dmem and one for ifu? // instead, could we only care about the instr and F pins that come from ifu and only care about the load/store and m pins that come from dmem? .InstrAccessFaultF, .LoadAccessFaultM, .StoreAmoAccessFaultM, .SelHPTW, - .ExceptionM, .IllegalFPUInstrE, + .IllegalFPUInstrE, .PrivilegeModeW, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, From 4c5e361b00f8a4906bd14de61d37af9dab6dfb9a Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 15:26:08 +0000 Subject: [PATCH 09/14] More unused signal cleanup --- pipelined/src/ifu/ifu.sv | 4 ++-- pipelined/src/wally/wallypipelinedcore.sv | 9 +++------ 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index d10bb95f6..be340b2e6 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -33,8 +33,8 @@ module ifu ( input logic clk, reset, - input logic StallF, StallD, StallE, StallM, StallW, - input logic FlushF, FlushD, FlushE, FlushM, FlushW, + input logic StallF, StallD, StallE, StallM, + input logic FlushF, FlushD, FlushE, FlushM, // Bus interface (* mark_debug = "true" *) input logic [`XLEN-1:0] IFUBusHRDATA, (* mark_debug = "true" *) input logic IFUBusAck, diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index 0ca52dc55..ccbc25df3 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -63,13 +63,11 @@ module wallypipelinedcore ( // new signals that must connect through DP logic MDUE, W64E; logic CSRReadM, CSRWriteM, PrivilegedM; - logic [1:0] AtomicE; logic [1:0] AtomicM; logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE; //, SrcAE, SrcBE; (* mark_debug = "true" *) logic [`XLEN-1:0] SrcAM; logic [2:0] Funct3E; - // logic [31:0] InstrF; - logic [31:0] InstrD, InstrW; + logic [31:0] InstrD; (* mark_debug = "true" *) logic [31:0] InstrM; logic [`XLEN-1:0] PCF, PCD, PCE, PCLinkE; (* mark_debug = "true" *) logic [`XLEN-1:0] PCM; @@ -166,8 +164,8 @@ module wallypipelinedcore ( ifu ifu( .clk, .reset, - .StallF, .StallD, .StallE, .StallM, .StallW, - .FlushF, .FlushD, .FlushE, .FlushM, .FlushW, + .StallF, .StallD, .StallE, .StallM, + .FlushF, .FlushD, .FlushE, .FlushM, // Fetch .IFUBusHRDATA, .IFUBusAck, .PCF, .IFUBusAdr, .IFUBusRead, .IFUStallF, @@ -217,7 +215,6 @@ module wallypipelinedcore ( // Memory stage interface .SquashSCW, // from LSU .MemRWM, // read/write control goes to LSU - .AtomicE, // atomic control goes to LSU .AtomicM, // atomic control goes to LSU .WriteDataE, // Write data to LSU .Funct3M, // size and signedness to LSU From 61199ccd133322e7a353e07b41be15303033f141 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 15:39:44 +0000 Subject: [PATCH 10/14] More signal cleanup --- pipelined/regression/lint-wally | 4 ++-- pipelined/src/fpu/fpu.sv | 4 ++-- pipelined/src/ieu/controller.sv | 2 +- pipelined/src/ieu/ieu.sv | 3 +-- 4 files changed, 6 insertions(+), 7 deletions(-) diff --git a/pipelined/regression/lint-wally b/pipelined/regression/lint-wally index e68d13c25..564973a39 100755 --- a/pipelined/regression/lint-wally +++ b/pipelined/regression/lint-wally @@ -5,9 +5,9 @@ export PATH=$PATH:/usr/local/bin/ verilator=`which verilator` basepath=$(dirname $0)/.. -for config in rv64gc rv32e rv32gc rv32ic ; do +for config in rv32e rv64gc rv32gc rv32ic ; do echo "$config linting..." - if !($verilator --Wall --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes); then + if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes); then echo "Exiting after $config lint due to errors or warnings" exit 1 fi diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index 5149b05e8..9a78a36b2 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -240,8 +240,8 @@ module fpu ( // E/M pipe registers // flopenrc #(64) EMFpReg1(clk, reset, FlushM, ~StallM, FSrcXE, FSrcXM); - flopenrc #(55) EMFpReg2 (clk, reset, FlushM, ~StallM, {XSgnE,XManE}, {XSgnM,XManM}); - flopenrc #(55) EMFpReg3 (clk, reset, FlushM, ~StallM, {YSgnE,YManE}, {YSgnM,YManM}); + flopenrc #(54) EMFpReg2 (clk, reset, FlushM, ~StallM, {XSgnE,XManE}, {XSgnM,XManM}); + flopenrc #(54) EMFpReg3 (clk, reset, FlushM, ~StallM, {YSgnE,YManE}, {YSgnM,YManM}); flopenrc #(64) EMFpReg4 (clk, reset, FlushM, ~StallM, {ZExpE,ZManE}, {ZExpM,ZManM}); flopenrc #(12) EMFpReg5 (clk, reset, FlushM, ~StallM, {XZeroE, YZeroE, ZZeroE, XInfE, YInfE, ZInfE, XNaNE, YNaNE, ZNaNE, XSNaNE, YSNaNE, ZSNaNE}, diff --git a/pipelined/src/ieu/controller.sv b/pipelined/src/ieu/controller.sv index cb7e3f2fd..41bad29e0 100644 --- a/pipelined/src/ieu/controller.sv +++ b/pipelined/src/ieu/controller.sv @@ -52,7 +52,6 @@ module controller( output logic MDUE, W64E, output logic JumpE, output logic SCE, - output logic [1:0] AtomicE, // Memory stage control signals input logic StallM, FlushM, output logic [1:0] MemRWM, @@ -107,6 +106,7 @@ module controller( logic BranchFlagE; logic IEURegWriteE; logic IllegalERegAdrD; + logic [1:0] AtomicE; // Extract fields assign OpD = InstrD[6:0]; diff --git a/pipelined/src/ieu/ieu.sv b/pipelined/src/ieu/ieu.sv index a10d1f92f..8fe310370 100644 --- a/pipelined/src/ieu/ieu.sv +++ b/pipelined/src/ieu/ieu.sv @@ -50,7 +50,6 @@ module ieu ( // Memory stage interface input logic SquashSCW, // from LSU output logic [1:0] MemRWM, // read/write control goes to LSU - output logic [1:0] AtomicE, // atomic control goes to LSU output logic [1:0] AtomicM, // atomic control goes to LSU output logic [`XLEN-1:0] WriteDataE, // Address and write data to LSU @@ -98,7 +97,7 @@ module ieu ( .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, .StallE, .FlushE, .FlagsE, .FWriteIntE, .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .MemReadE, .CSRReadE, .Funct3E, .MDUE, .W64E, .JumpE, .StallM, .FlushM, .MemRWM, - .CSRReadM, .CSRWriteM, .PrivilegedM, .SCE, .AtomicE, .AtomicM, .Funct3M, + .CSRReadM, .CSRWriteM, .PrivilegedM, .SCE, .AtomicM, .Funct3M, .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .FWriteIntM, .StallW, .FlushW, .RegWriteW, .ResultSrcW, .CSRWritePendingDEM, .StoreStallD); From 21c1e5882906e62f4c45643a8ec07fdbbf7262b7 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 16:16:42 +0000 Subject: [PATCH 11/14] Partitioned privilege mode fsm into new module --- pipelined/src/privileged/privileged.sv | 8 ++-- pipelined/src/privileged/privmode.sv | 66 ++++++++++++++++++++++++++ pipelined/testbench/testbench-linux.sv | 2 +- 3 files changed, 72 insertions(+), 4 deletions(-) create mode 100644 pipelined/src/privileged/privmode.sv diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index ca3a34224..647407472 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -81,8 +81,6 @@ module privileged ( output logic BreakpointFaultM, EcallFaultM, wfiM, IntPendingM, BigEndianM ); - logic [1:0] NextPrivilegeModeM; - logic [`XLEN-1:0] CauseM, NextFaultMtvalM; logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW; logic [`XLEN-1:0] MEDELEG_REGW; @@ -102,15 +100,18 @@ module privileged ( logic STATUS_SPP, STATUS_TSR, STATUS_TW, STATUS_TVM; logic STATUS_MIE, STATUS_SIE; logic [11:0] MIP_REGW, MIE_REGW; - logic md; logic StallMQ; logic WFITimeoutM; + logic [1:0] NextPrivilegeModeM; /////////////////////////////////////////// // track the current privilege level /////////////////////////////////////////// + privmode privmode(.clk, .reset, .StallW, .TrapM, .mretM, .sretM, .CauseM, + .MEDELEG_REGW, .MIDELEG_REGW, .STATUS_MPP, .STATUS_SPP, .NextPrivilegeModeM, .PrivilegeModeW); + /* // get bits of DELEG registers based on CAUSE assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM[`LOG_XLEN-1:0]]; @@ -129,6 +130,7 @@ module privileged ( end flopenl #(2) privmodereg(clk, reset, ~StallW, NextPrivilegeModeM, `M_MODE, PrivilegeModeW); +*/ /////////////////////////////////////////// // WFI timeout Privileged Spec 3.1.6.5 diff --git a/pipelined/src/privileged/privmode.sv b/pipelined/src/privileged/privmode.sv new file mode 100644 index 000000000..d48c57d53 --- /dev/null +++ b/pipelined/src/privileged/privmode.sv @@ -0,0 +1,66 @@ +/////////////////////////////////////////// +// privmode.sv +// +// Written: David_Harris@hmc.edu 12 May 2022 +// Modified: +// +// Purpose: Track privilege mode +// See RISC-V Privileged Mode Specification 20190608 3.1.10-11 +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module privmode ( + input logic clk, reset, + input logic StallW, TrapM, mretM, sretM, + input logic [`XLEN-1:0] CauseM, MEDELEG_REGW, + input logic [11:0] MIDELEG_REGW, + input logic [1:0] STATUS_MPP, + input logic STATUS_SPP, + output logic [1:0] NextPrivilegeModeM, PrivilegeModeW +); + + if (`U_SUPPORTED) begin:privmode + logic md; + + // get bits of DELEG registers based on CAUSE + assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM[`LOG_XLEN-1:0]]; + + // PrivilegeMode FSM + always_comb begin + if (TrapM) begin // Change privilege based on DELEG registers (see 3.1.8) + if (`S_SUPPORTED & md & (PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE)) + NextPrivilegeModeM = `S_MODE; + else NextPrivilegeModeM = `M_MODE; + end else if (mretM) NextPrivilegeModeM = STATUS_MPP; + else if (sretM) NextPrivilegeModeM = {1'b0, STATUS_SPP}; + else NextPrivilegeModeM = PrivilegeModeW; + end + + flopenl #(2) privmodereg(clk, reset, ~StallW, NextPrivilegeModeM, `M_MODE, PrivilegeModeW); + end else begin // only machine mode supported + assign NextPrivilegeModeM = `M_MODE; + assign PrivilegeModeW = `M_MODE; + end +endmodule \ No newline at end of file diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index 0173e35b3..f405af48f 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -138,7 +138,7 @@ module testbench; `define RF dut.core.ieu.dp.regf.rf `define PC dut.core.ifu.pcreg.q `define PRIV_BASE dut.core.priv.priv - `define PRIV `PRIV_BASE.privmodereg.q + `define PRIV `PRIV_BASE.privmode.privmode.privmodereg.q `define CSR_BASE `PRIV_BASE.csr `define MEIP `PRIV_BASE.MExtInt `define SEIP `PRIV_BASE.SExtInt From 1d01bc98a423163e80f165803cd04b50d30ca911 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 16:22:39 +0000 Subject: [PATCH 12/14] Moved WFI timeout into privdec --- pipelined/src/privileged/privdec.sv | 19 +++++++++++-- pipelined/src/privileged/privileged.sv | 37 +++----------------------- 2 files changed, 20 insertions(+), 36 deletions(-) diff --git a/pipelined/src/privileged/privdec.sv b/pipelined/src/privileged/privdec.sv index ae831144b..da1807103 100644 --- a/pipelined/src/privileged/privdec.sv +++ b/pipelined/src/privileged/privdec.sv @@ -32,18 +32,21 @@ `include "wally-config.vh" module privdec ( + input logic clk, reset, input logic [31:20] InstrM, input logic PrivilegedM, IllegalIEUInstrFaultM, IllegalCSRAccessM, IllegalFPUInstrM, - input logic WFITimeoutM, input logic [1:0] PrivilegeModeW, - input logic STATUS_TSR, STATUS_TVM, + input logic STATUS_TSR, STATUS_TVM, STATUS_TW, input logic [1:0] STATUS_FS, output logic IllegalInstrFaultM, output logic sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM); logic IllegalPrivilegedInstrM, IllegalOrDisabledFPUInstrM; + logic WFITimeoutM; + /////////////////////////////////////////// // Decode privileged instructions + /////////////////////////////////////////// assign sretM = PrivilegedM & (InstrM[31:20] == 12'b000100000010) & `S_SUPPORTED & (PrivilegeModeW == `M_MODE || PrivilegeModeW == `S_MODE & ~STATUS_TSR); assign mretM = PrivilegedM & (InstrM[31:20] == 12'b001100000010) & (PrivilegeModeW == `M_MODE); @@ -53,7 +56,19 @@ module privdec ( assign sfencevmaM = PrivilegedM & (InstrM[31:25] == 7'b0001001) & (PrivilegeModeW == `M_MODE | (PrivilegeModeW == `S_MODE & ~STATUS_TVM)); + /////////////////////////////////////////// + // WFI timeout Privileged Spec 3.1.6.5 + /////////////////////////////////////////// + if (`U_SUPPORTED) begin:wfi + logic [`WFI_TIMEOUT_BIT:0] WFICount, WFICountPlus1; + assign WFICountPlus1 = WFICount + 1; + floprc #(`WFI_TIMEOUT_BIT+1) wficountreg(clk, reset, ~wfiM, WFICountPlus1, WFICount); // count while in WFI + assign WFITimeoutM = ((STATUS_TW & PrivilegeModeW != `M_MODE) | (`S_SUPPORTED & PrivilegeModeW == `U_MODE)) & WFICount[`WFI_TIMEOUT_BIT]; + end else assign WFITimeoutM = 0; + + /////////////////////////////////////////// // Fault on illegal instructions + /////////////////////////////////////////// assign IllegalPrivilegedInstrM = PrivilegedM & ~(sretM|mretM|ecallM|ebreakM|wfiM|sfencevmaM); assign IllegalOrDisabledFPUInstrM = IllegalFPUInstrM | (STATUS_FS == 2'b00); assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalOrDisabledFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM | diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index 647407472..74b419944 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -111,45 +111,14 @@ module privileged ( privmode privmode(.clk, .reset, .StallW, .TrapM, .mretM, .sretM, .CauseM, .MEDELEG_REGW, .MIDELEG_REGW, .STATUS_MPP, .STATUS_SPP, .NextPrivilegeModeM, .PrivilegeModeW); - /* - // get bits of DELEG registers based on CAUSE - assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM[`LOG_XLEN-1:0]]; - - // PrivilegeMode FSM - always_comb begin - if (TrapM) begin // Change privilege based on DELEG registers (see 3.1.8) - if (`S_SUPPORTED & md & (PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE)) - NextPrivilegeModeM = `S_MODE; - else NextPrivilegeModeM = `M_MODE; - end else if (mretM) NextPrivilegeModeM = STATUS_MPP; - else if (sretM) begin - if (STATUS_TSR & PrivilegeModeW == `S_MODE) begin - NextPrivilegeModeM = PrivilegeModeW; - end else NextPrivilegeModeM = {1'b0, STATUS_SPP}; - end else NextPrivilegeModeM = PrivilegeModeW; - end - - flopenl #(2) privmodereg(clk, reset, ~StallW, NextPrivilegeModeM, `M_MODE, PrivilegeModeW); -*/ - - /////////////////////////////////////////// - // WFI timeout Privileged Spec 3.1.6.5 - /////////////////////////////////////////// - if (`U_SUPPORTED) begin:wfi - logic [`WFI_TIMEOUT_BIT:0] WFICount, WFICountPlus1; - assign WFICountPlus1 = WFICount + 1; - floprc #(`WFI_TIMEOUT_BIT+1) wficountreg(clk, reset, ~wfiM, WFICountPlus1, WFICount); // count while in WFI - assign WFITimeoutM = ((STATUS_TW & PrivilegeModeW != `M_MODE) | (`S_SUPPORTED & PrivilegeModeW == `U_MODE)) & WFICount[`WFI_TIMEOUT_BIT]; - end else assign WFITimeoutM = 0; - /////////////////////////////////////////// // decode privileged instructions /////////////////////////////////////////// - privdec pmd(.InstrM(InstrM[31:20]), - .PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, .WFITimeoutM, - .PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_FS, .IllegalInstrFaultM, + privdec pmd(.clk, .reset, .InstrM(InstrM[31:20]), + .PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, + .PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .STATUS_FS, .IllegalInstrFaultM, .sretM, .mretM, .ecallM, .ebreakM, .wfiM, .sfencevmaM); /////////////////////////////////////////// From 9f8dca5190a69f2a658f8b4e6cb91aeae463a102 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 16:41:52 +0000 Subject: [PATCH 13/14] Moved TLB Flush logic into privdec --- pipelined/src/hazard/hazard.sv | 2 ++ pipelined/src/privileged/privdec.sv | 18 ++++++++++++++++-- pipelined/src/privileged/privileged.sv | 15 ++------------- 3 files changed, 20 insertions(+), 15 deletions(-) diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv index b0e13f5f9..159ee10ec 100644 --- a/pipelined/src/hazard/hazard.sv +++ b/pipelined/src/hazard/hazard.sv @@ -60,6 +60,8 @@ module hazard( // A stage must stall if the next stage is stalled // If any stages are stalled, the first stage that isn't stalled must flush. + // *** can stalls be pushed into earlier stages (e.g. no stall after Decode?) + assign StallFCause = CSRWritePendingDEM & ~(TrapM | RetM | BPPredWrongE); // stall in decode if instruction is a load/mul/csr dependent on previous assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FPUStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE); diff --git a/pipelined/src/privileged/privdec.sv b/pipelined/src/privileged/privdec.sv index da1807103..7bf96d6f4 100644 --- a/pipelined/src/privileged/privdec.sv +++ b/pipelined/src/privileged/privdec.sv @@ -33,16 +33,18 @@ module privdec ( input logic clk, reset, + input logic StallM, input logic [31:20] InstrM, input logic PrivilegedM, IllegalIEUInstrFaultM, IllegalCSRAccessM, IllegalFPUInstrM, input logic [1:0] PrivilegeModeW, input logic STATUS_TSR, STATUS_TVM, STATUS_TW, input logic [1:0] STATUS_FS, - output logic IllegalInstrFaultM, + output logic IllegalInstrFaultM, ITLBFlushF, DTLBFlushM, output logic sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM); logic IllegalPrivilegedInstrM, IllegalOrDisabledFPUInstrM; logic WFITimeoutM; + logic StallMQ; /////////////////////////////////////////// // Decode privileged instructions @@ -65,7 +67,19 @@ module privdec ( floprc #(`WFI_TIMEOUT_BIT+1) wficountreg(clk, reset, ~wfiM, WFICountPlus1, WFICount); // count while in WFI assign WFITimeoutM = ((STATUS_TW & PrivilegeModeW != `M_MODE) | (`S_SUPPORTED & PrivilegeModeW == `U_MODE)) & WFICount[`WFI_TIMEOUT_BIT]; end else assign WFITimeoutM = 0; - + + /////////////////////////////////////////// + // sfence.vma causes TLB flushes + /////////////////////////////////////////// + // sets ITLBFlush to pulse for one cycle of the sfence.vma instruction + // In this instr we want to flush the tlb and then do a pagetable walk to update the itlb and continue the program. + // But we're still in the stalled sfence instruction, so if itlbflushf == sfencevmaM, tlbflush would never drop and + // the tlbwrite would never take place after the pagetable walk. by adding in ~StallMQ, we are able to drop itlbflush + // after a cycle AND pulse it for another cycle on any further back-to-back sfences. + flopr #(1) StallMReg(.clk, .reset, .d(StallM), .q(StallMQ)); + assign ITLBFlushF = sfencevmaM & ~StallMQ; + assign DTLBFlushM = sfencevmaM; + /////////////////////////////////////////// // Fault on illegal instructions /////////////////////////////////////////// diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index 74b419944..20803449f 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -100,11 +100,8 @@ module privileged ( logic STATUS_SPP, STATUS_TSR, STATUS_TW, STATUS_TVM; logic STATUS_MIE, STATUS_SIE; logic [11:0] MIP_REGW, MIE_REGW; - logic StallMQ; - logic WFITimeoutM; logic [1:0] NextPrivilegeModeM; - /////////////////////////////////////////// // track the current privilege level /////////////////////////////////////////// @@ -116,9 +113,10 @@ module privileged ( // decode privileged instructions /////////////////////////////////////////// - privdec pmd(.clk, .reset, .InstrM(InstrM[31:20]), + privdec pmd(.clk, .reset, .StallM, .InstrM(InstrM[31:20]), .PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, .PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .STATUS_FS, .IllegalInstrFaultM, + .ITLBFlushF, .DTLBFlushM, .sretM, .mretM, .ecallM, .ebreakM, .wfiM, .sfencevmaM); /////////////////////////////////////////// @@ -158,15 +156,6 @@ module privileged ( assign BreakpointFaultM = ebreakM; // could have other causes too assign EcallFaultM = ecallM; - flopr #(1) StallMReg(.clk, .reset, .d(StallM), .q(StallMQ)); - assign ITLBFlushF = sfencevmaM & ~StallMQ; - assign DTLBFlushM = sfencevmaM; - // sets ITLBFlush to pulse for one cycle of the sfence.vma instruction - // In this instr we want to flush the tlb and then do a pagetable walk to update the itlb and continue the program. - // But we're still in the stalled sfence instruction, so if itlbflushf == sfencevmaM, tlbflush would never drop and - // the tlbwrite would never take place after the pagetable walk. by adding in ~StallMQ, we are able to drop itlbflush - // after a cycle AND pulse it for another cycle on any further back-to-back sfences. - // A page fault might occur because of insufficient privilege during a TLB // lookup or a improperly formatted page table during walking From 449472ba58b342302ddd4004d89f301b2f48a12e Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 16:45:53 +0000 Subject: [PATCH 14/14] Moved Breakpoint and Ecall fault logic into privdec --- pipelined/src/privileged/privdec.sv | 10 +++++++++- pipelined/src/privileged/privileged.sv | 12 +++--------- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/pipelined/src/privileged/privdec.sv b/pipelined/src/privileged/privdec.sv index 7bf96d6f4..8271f332a 100644 --- a/pipelined/src/privileged/privdec.sv +++ b/pipelined/src/privileged/privdec.sv @@ -40,11 +40,13 @@ module privdec ( input logic STATUS_TSR, STATUS_TVM, STATUS_TW, input logic [1:0] STATUS_FS, output logic IllegalInstrFaultM, ITLBFlushF, DTLBFlushM, - output logic sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM); + output logic EcallFaultM, BreakpointFaultM, + output logic sretM, mretM, wfiM, sfencevmaM); logic IllegalPrivilegedInstrM, IllegalOrDisabledFPUInstrM; logic WFITimeoutM; logic StallMQ; + logic ebreakM, ecallM; /////////////////////////////////////////// // Decode privileged instructions @@ -68,6 +70,12 @@ module privdec ( assign WFITimeoutM = ((STATUS_TW & PrivilegeModeW != `M_MODE) | (`S_SUPPORTED & PrivilegeModeW == `U_MODE)) & WFICount[`WFI_TIMEOUT_BIT]; end else assign WFITimeoutM = 0; + /////////////////////////////////////////// + // Extract exceptions by name and handle them + /////////////////////////////////////////// + assign BreakpointFaultM = ebreakM; // could have other causes from a debugger + assign EcallFaultM = ecallM; + /////////////////////////////////////////// // sfence.vma causes TLB flushes /////////////////////////////////////////// diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index 20803449f..7ee6ebc44 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -86,7 +86,7 @@ module privileged ( logic [`XLEN-1:0] MEDELEG_REGW; logic [11:0] MIDELEG_REGW; - logic sretM, mretM, ecallM, ebreakM, sfencevmaM; + logic sretM, mretM, sfencevmaM; logic IllegalCSRAccessM; logic IllegalIEUInstrFaultE, IllegalIEUInstrFaultM; logic IllegalFPUInstrM; @@ -116,8 +116,8 @@ module privileged ( privdec pmd(.clk, .reset, .StallM, .InstrM(InstrM[31:20]), .PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, .PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .STATUS_FS, .IllegalInstrFaultM, - .ITLBFlushF, .DTLBFlushM, - .sretM, .mretM, .ecallM, .ebreakM, .wfiM, .sfencevmaM); + .ITLBFlushF, .DTLBFlushM, .EcallFaultM, .BreakpointFaultM, + .sretM, .mretM, .wfiM, .sfencevmaM); /////////////////////////////////////////// // Control and Status Registers @@ -149,12 +149,6 @@ module privileged ( .CSRReadValW, .IllegalCSRAccessM, .BigEndianM); - /////////////////////////////////////////// - // Extract exceptions by name and handle them - /////////////////////////////////////////// - - assign BreakpointFaultM = ebreakM; // could have other causes too - assign EcallFaultM = ecallM; // A page fault might occur because of insufficient privilege during a TLB