diff --git a/pipelined/src/ebu/ahbinterface.sv b/pipelined/src/ebu/ahbinterface.sv
index 63449fe8d..ff50f54f5 100644
--- a/pipelined/src/ebu/ahbinterface.sv
+++ b/pipelined/src/ebu/ahbinterface.sv
@@ -1,15 +1,14 @@
 ///////////////////////////////////////////
 // ahbinterface.sv
 //
-// Written: Ross Thompson ross1728@gmail.com August 29, 2022
-// Modified: 
+// Written: Ross Thompson ross1728@gmail.com
+// Created: August 29, 2022
+// Modified: 18 January 2023
 //
-// Purpose: Cache/Bus data path.
-// Bus Side logic
-// register the fetch data from the next level of memory.
-// This register should be necessary for timing.  There is no register in the uncore or
-// ahblite controller between the memories and this cache.
+// Purpose: Translates LSU simple memory requests into AHB transactions (NON_SEQ).
 // 
+// Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.21)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
@@ -30,7 +29,9 @@
 
 `include "wally-config.vh"
 
-module ahbinterface #(parameter LSU = 0) ( // **** modify to use LSU/ifu parameter to control widths of buses
+module ahbinterface #(
+  parameter LSU = 0                                   // 1: LSU bus width is `XLEN, 0: IFU bus width is 32 bits
+)( 
   input logic 							HCLK, HRESETn,
   // bus interface
   input logic 							HREADY,       // AHB peripheral ready
diff --git a/pipelined/src/ebu/busfsm.sv b/pipelined/src/ebu/busfsm.sv
index 1e8af036c..830253227 100644
--- a/pipelined/src/ebu/busfsm.sv
+++ b/pipelined/src/ebu/busfsm.sv
@@ -1,10 +1,13 @@
 ///////////////////////////////////////////
 // busfsm.sv
 //
-// Written: Ross Thompson ross1728@gmail.com December 29, 2021
-// Modified: 
+// Written: Ross Thompson ross1728@gmail.com
+// Created: December 29, 2021
+// Modified: 18 January 2023
 //
-// Purpose: Load/Store Unit's interface to BUS for cacheless system
+// Purpose: Simple NON_SEQ (no burst) AHB controller.
+//
+// Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.23)
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
@@ -55,13 +58,13 @@ module busfsm (
   
   always_comb begin
 	  case(CurrState)
-	    ADR_PHASE: if(HREADY & |BusRW)  NextState = DATA_PHASE;
-                 else                 NextState = ADR_PHASE;
-      DATA_PHASE: if(HREADY)          NextState = MEM3;
-		          else                    NextState = DATA_PHASE;
-      MEM3: if(Stall)                 NextState = MEM3;
-		    else                          NextState = ADR_PHASE;
-	    default:                        NextState = ADR_PHASE;
+	    ADR_PHASE: if(HREADY & |BusRW) NextState = DATA_PHASE;
+                 else                  NextState = ADR_PHASE;
+      DATA_PHASE: if(HREADY)           NextState = MEM3;
+		          else                 NextState = DATA_PHASE;
+      MEM3: if(Stall)                  NextState = MEM3;
+		    else                       NextState = ADR_PHASE;
+	    default:                       NextState = ADR_PHASE;
 	  endcase
   end