From 5f5cc514b82f1ad8e033919c045d83564b35eff4 Mon Sep 17 00:00:00 2001
From: bbracker <bbracker@hmc.edu>
Date: Wed, 2 Mar 2022 16:00:19 +0000
Subject: [PATCH] fix buildroot checkpointing and add it back to regression

---
 pipelined/regression/regression-wally  | 2 +-
 pipelined/testbench/testbench-linux.sv | 9 ++++++---
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally
index 4c2d0d8b6..9565c7295 100755
--- a/pipelined/regression/regression-wally
+++ b/pipelined/regression/regression-wally
@@ -60,7 +60,7 @@ tc = TestCase(
       variant="rv64gc",
       cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do buildroot buildroot-checkpoint $RISCV 400100000 400000001 400000000\n!", # *** will this work with rv64gc rather than buildroot config?
       grepstr="400100000 instructions")
-#configs.append(tc) #temporarily removed until I make this checkpoint
+configs.append(tc)
 
 tests64gc = ["arch64i", "arch64priv", "arch64c",  "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64m", "wally64a",  "imperas64c", "wally64priv"] # , "imperas64mmu" "wally64i", #,  "testsBP64"] 
 for test in tests64gc:
diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv
index 73f6a5501..0c58f7b72 100644
--- a/pipelined/testbench/testbench-linux.sv
+++ b/pipelined/testbench/testbench-linux.sv
@@ -310,6 +310,8 @@ module testbench;
     force dut.core.priv.priv.ExtIntM = 0;    
     $sformat(testvectorDir,"%s/linux-testvectors/",RISCV_DIR);
     $sformat(linuxImageDir,"%s/buildroot/output/images/",RISCV_DIR);
+    if (CHECKPOINT!=0)
+      $sformat(checkpointDir,"%s/linux-testvectors/checkpoint%0d/",RISCV_DIR,CHECKPOINT);
     $readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
     $readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem);
     ProgramAddrMapFile = {linuxImageDir,"vmlinux.objdump.addr"};
@@ -319,7 +321,10 @@ module testbench;
     readResult = $fread(dut.uncore.bootrom.bootrom.RAM,memFile);
     $fclose(memFile);
     // initialize RAM
-    memFile = $fopen({testvectorDir,"ram.bin"}, "rb");
+    if (CHECKPOINT==0) 
+      memFile = $fopen({testvectorDir,"ram.bin"}, "rb");
+    else
+      memFile = $fopen({checkpointDir,"ram.bin"}, "rb");
     readResult = $fread(dut.uncore.ram.ram.RAM,memFile);
     $fclose(memFile);
     if (CHECKPOINT==0) begin // normal
@@ -327,8 +332,6 @@ module testbench;
       traceFileE = $fopen({testvectorDir,"all.txt"}, "r");
       InstrCountW = '0;
     end else begin // checkpoint
-      $sformat(checkpointDir,"checkpoint%0d/",CHECKPOINT);
-      checkpointDir = {testvectorDir,checkpointDir};
       //$readmemh({checkpointDir,"ram.txt"}, dut.uncore.ram.ram.RAM);
       traceFileE = $fopen({checkpointDir,"all.txt"}, "r");
       traceFileM = $fopen({checkpointDir,"all.txt"}, "r");