From 60e70c1986b8df2da2f1b5e538fd0cbc60590dc4 Mon Sep 17 00:00:00 2001
From: David Harris <David_Harris@hmc.edu>
Date: Mon, 8 Apr 2024 05:57:18 -0700
Subject: [PATCH] Fixed testbench-fp replication length for regression-wally
 --testfloat.  Changed regression-wally to expect -- in named arguments.

---
 bin/regression-wally      | 28 ++++++++++++++++------------
 testbench/testbench_fp.sv |  6 +++---
 2 files changed, 19 insertions(+), 15 deletions(-)

diff --git a/bin/regression-wally b/bin/regression-wally
index c161a9340..bdb58fea0 100755
--- a/bin/regression-wally
+++ b/bin/regression-wally
@@ -254,20 +254,20 @@ os.chdir(regressionDir)
 coveragesim = "questa"  # Questa is required for code/functional coverage
 defaultsim = "questa"   # Default simulator for all other tests; change to Verilator when flow is ready
 
-coverage = '-coverage' in sys.argv
-fp = '-fp' in sys.argv
-nightly = '-nightly' in sys.argv
-testfloat = '-testfloat' in sys.argv
+coverage = '--coverage' in sys.argv
+fp = '--fp' in sys.argv
+nightly = '--nightly' in sys.argv
+testfloat = '--testfloat' in sys.argv
 
 if (nightly):
-    nightMode = "-nightly";
+    nightMode = "--nightly";
     sims = ["questa", "verilator", "vcs"]
 else:
     nightMode = "";
     sims = [defaultsim]
 
 if (coverage):  # only run RV64GC tests in coverage mode
-    coverStr = '-coverage'
+    coverStr = '--coverage'
 else:
    coverStr = ''
 
@@ -302,6 +302,8 @@ if (testfloat):
     testfloatconfigs = ["fdqh_ieee_rv64gc", "fdq_ieee_rv64gc", "fdh_ieee_rv64gc", "fd_ieee_rv64gc", "fh_ieee_rv64gc", "f_ieee_rv64gc", "fdqh_ieee_rv32gc", "f_ieee_rv32gc"]
     for config in testfloatconfigs:
         tests = ["div", "sqrt", "add", "sub", "mul", "cvtint", "cvtfp", "fma", "cmp"]
+        if ("f_" in config):
+            tests.remove("cvtfp")
         for test in tests:
             tc = TestCase(
                     name=test,
@@ -343,6 +345,8 @@ if (testfloat):
         if ("ieee" in config):
             tests.append("cvtint")
             tests.append("cvtfp")
+        if ("f_" in config):
+            tests.remove("cvtfp")
         for test in tests:
             tc = TestCase(
                     name=test,
@@ -362,26 +366,26 @@ def main():
         except:
             pass
  
-    if '-makeTests' in sys.argv:
+    if '--makeTests' in sys.argv:
         os.chdir(regressionDir)
         os.system('./make-tests.sh | tee ./logs/make-tests.log')
 
-    if '-all' in sys.argv:
+    if '--all' in sys.argv:
         TIMEOUT_DUR = 30*7200 # seconds
         #configs.append(getBuildrootTC(boot=True))
-    elif '-buildroot' in sys.argv:
+    elif '--buildroot' in sys.argv:
         TIMEOUT_DUR = 30*7200 # seconds
         #configs=[getBuildrootTC(boot=True)]
-    elif '-coverage' in sys.argv:
+    elif '--coverage' in sys.argv:
         TIMEOUT_DUR = 20*60 # seconds    
     #   Presently don't run buildroot because it has a different config and can't be merged with the rv64gc coverage.
     #   Also it is slow to run.   
     #    configs.append(getBuildrootTC(boot=False))
         os.system('rm -f cov/*.ucdb')
-    elif '-nightly' in sys.argv:
+    elif '--nightly' in sys.argv:
         TIMEOUT_DUR = 60*1440 # 1 day
         #configs.append(getBuildrootTC(boot=False))
-    elif '-testfloat' in sys.argv:
+    elif '--testfloat' in sys.argv:
         TIMEOUT_DUR = 60*60 # seconds
     else:
         TIMEOUT_DUR = 10*60 # seconds
diff --git a/testbench/testbench_fp.sv b/testbench/testbench_fp.sv
index ba35a3c14..f124ec334 100644
--- a/testbench/testbench_fp.sv
+++ b/testbench/testbench_fp.sv
@@ -1275,7 +1275,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
 		 2'b01:	begin // quad -> long
                     X = {TestVector[8+P.XLEN+P.Q_LEN-1:8+(P.XLEN)]};
                     SrcA = {P.XLEN{1'bx}};
-                    Ans = {{(P.FLEN-64){1'b0}}, TestVector[8+(P.XLEN-1):8]};
+                    Ans = {{(P.FLEN > 64 ? P.FLEN-64 : 0){1'b0}}, TestVector[8+(P.XLEN-1):8]};
 		 end
 		 2'b00:	begin // quad -> int
                     X = {TestVector[8+32+P.Q_LEN-1:8+(32)]};
@@ -1327,7 +1327,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
 		 2'b01:	begin // single -> long
                     X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.XLEN+P.S_LEN-1:8+(P.XLEN)]};
                     SrcA = {P.XLEN{1'bx}};
-                    Ans = {{(P.FLEN-64){1'b0}}, TestVector[8+(P.XLEN-1):8]};
+                    Ans = {{(P.FLEN > 64 ? P.FLEN-64 : 0){1'b0}}, TestVector[8+(P.XLEN-1):8]};
 		 end
 		 2'b00:	begin // single -> int
                     X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+32+P.S_LEN-1:8+(32)]};
@@ -1353,7 +1353,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
 		 2'b01:	begin // half -> long
                     X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.XLEN+P.H_LEN-1:8+(P.XLEN)]};
                     SrcA = {P.XLEN{1'bx}};
-                    Ans = {{(P.FLEN-64){1'b0}}, TestVector[8+(P.XLEN-1):8]};
+                    Ans = {{(P.FLEN > 64 ? P.FLEN-64 : 0){1'b0}}, TestVector[8+(P.XLEN-1):8]};
 		 end
 		 2'b00:	begin // half -> int
                     X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+32+P.H_LEN-1:8+(32)]};