From 616830a3f0557bac29ad777349bff5c8d5329307 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 2 Feb 2021 13:53:13 -0500
Subject: [PATCH] Cleaned up hazard interface

---
 wally-pipelined/src/hazard/hazard.sv            | 9 +++++----
 wally-pipelined/src/ieu/ieu.sv                  | 5 ++---
 wally-pipelined/src/wally/wallypipelinedhart.sv | 5 -----
 wally-pipelined/src/wally/wallypipelinedsoc.sv  | 3 +--
 4 files changed, 8 insertions(+), 14 deletions(-)

diff --git a/wally-pipelined/src/hazard/hazard.sv b/wally-pipelined/src/hazard/hazard.sv
index 2cec1f826..2fe0541a5 100644
--- a/wally-pipelined/src/hazard/hazard.sv
+++ b/wally-pipelined/src/hazard/hazard.sv
@@ -26,10 +26,11 @@
 `include "wally-config.vh"
 
 module hazard(
-  // Detect hazardsss
-  input  logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW,
-  input  logic       PCSrcE, MemReadE, 
-  input  logic       RegWriteM, RegWriteW, CSRWritePendingDEM, RetM, TrapM,
+  // Detect hazards
+//  input  logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW,
+//  input  logic       MemReadE, 
+//  input  logic       RegWriteM, RegWriteW, 
+  input  logic       PCSrcE, CSRWritePendingDEM, RetM, TrapM,
   input  logic       LoadStallD,
   input  logic       InstrStall, DataStall,
   // Stall outputs
diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv
index e0af5c7df..48f9a9dfc 100644
--- a/wally-pipelined/src/ieu/ieu.sv
+++ b/wally-pipelined/src/ieu/ieu.sv
@@ -51,9 +51,7 @@ module ieu (
   input  logic             RetM, TrapM,
   output logic             LoadStallD,
   output logic             PCSrcE,
-//  output logic 	           MemReadE,
-  output logic             RegWriteM,
-  output logic             RegWriteW,
+
   output logic             CSRWriteM, PrivilegedM,
   output logic             CSRWritePendingDEM
 );
@@ -68,6 +66,7 @@ module ieu (
   // forwarding signals
   logic [4:0]       Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW;
   logic [1:0]       ForwardAE, ForwardBE;
+  logic             RegWriteM, RegWriteW;
   logic             MemReadE;
            
   controller c(.OpD(InstrD[6:0]), .Funct3D(InstrD[14:12]), .Funct7b5D(InstrD[30]), .*);
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index 8a00ecb51..dcf1490f5 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -72,13 +72,8 @@ module wallypipelinedhart (
   logic [`XLEN-1:0] zero = 0;
 
   logic        PCSrcE;
-  logic        RegWriteM;
-  logic 	     MemReadE;
-  logic        RegWriteW;
   logic        CSRWritePendingDEM;
   logic        LoadStallD;
-  logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW;
-//  logic       TargetSrcE;
   logic [4:0] SetFflagsM;
   logic [2:0] FRM_REGW;
   logic       FloatRegWriteW;
diff --git a/wally-pipelined/src/wally/wallypipelinedsoc.sv b/wally-pipelined/src/wally/wallypipelinedsoc.sv
index 1f08fbf8e..9b0ed2456 100644
--- a/wally-pipelined/src/wally/wallypipelinedsoc.sv
+++ b/wally-pipelined/src/wally/wallypipelinedsoc.sv
@@ -61,7 +61,6 @@ module wallypipelinedsoc (
   // Uncore signals
   logic [`AHBW-1:0] HRDATA;   // from AHB mux in uncore
   logic             HREADY, HRESP;
-//  logic            UnsignedLoadM;
   logic        InstrAccessFaultF, DataAccessFaultM;
   logic        TimerIntM, SwIntM; // from CLINT
   logic        ExtIntM = 0; // not yet connected
@@ -69,6 +68,6 @@ module wallypipelinedsoc (
   // instantiate processor and memories
   wallypipelinedhart hart(.*);
 
-  imem imem(.AdrF(PCF[`XLEN-1:1]), .*);
+  imem imem(.AdrF(PCF[`XLEN-1:1]), .*); // temporary until uncore memory is finished***
   uncore uncore(.HWDATAIN(HWDATA), .*);
 endmodule
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