diff --git a/config/shared/test-shared.vh b/config/shared/test-shared.vh index 04961071f..96ef1e929 100644 --- a/config/shared/test-shared.vh +++ b/config/shared/test-shared.vh @@ -93,7 +93,7 @@ localparam FMT2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? 2'd0 : 2'd2); localparam BIAS2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? S_BIAS : H_BIAS); // division constants -localparam DIVN = (((NF(DIVb + 1 +NF+1) & (CVTLEN+NF+1)>(3*NF+ /* verilator lint_off STMTDLY */ /* verilator lint_off ASSIGNDLY */ -/* verilator lint_off PINCONNECTEMPTY */ \ No newline at end of file +/* verilator lint_off PINCONNECTEMPTY */ diff --git a/sim/wave.do b/sim/wave.do index e9461d589..73aaf02d8 100644 --- a/sim/wave.do +++ b/sim/wave.do @@ -11,37 +11,37 @@ add wave -noupdate /testbench/FunctionName/FunctionName/FunctionAddr add wave -noupdate /testbench/FunctionName/FunctionName/ProgramAddrIndex add wave -noupdate /testbench/FunctionName/FunctionName/FunctionName add wave -noupdate /testbench/FunctionName/FunctionName/ProgramAddrMapLineCount -add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/RetM -add wave -noupdate -group HDU -group hazards -color Pink /testbench/dut/core/hzu/TrapM -add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/LoadStallD -add wave -noupdate -group HDU -group hazards /testbench/dut/core/ifu/IFUStallF -add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/LSUStallM -add wave -noupdate -group HDU -group hazards /testbench/dut/core/MDUStallD -add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/DivBusyE -add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/FDivBusyE -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallF -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallD -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallE -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallM -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallW +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/RetM +add wave -noupdate -expand -group HDU -group hazards -color Pink /testbench/dut/core/hzu/TrapM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/LoadStallD +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/ifu/IFUStallF +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/LSUStallM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/MDUStallD +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/DivBusyE +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/FDivBusyE +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM +add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW +add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallF +add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallD +add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallE +add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallM +add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallW add wave -noupdate -group {instruction pipeline} /testbench/InstrFName add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD @@ -74,26 +74,27 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM add wave -noupdate -group {WriteBack stage} /testbench/PCW add wave -noupdate -group {WriteBack stage} /testbench/InstrW add wave -noupdate -group {WriteBack stage} /testbench/InstrWName -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MCAUSE_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEPC_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIDELEG_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIE_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW -add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW -add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW -add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MCAUSE_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MEPC_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIDELEG_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIE_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW +add wave -noupdate -expand -group CSRs {/testbench/dut/core/priv/priv/csr/MSTATUS_REGW[21]} +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW +add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW +add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW +add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW +add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS add wave -noupdate -group Bpred -expand -group {branch update selection inputs} -divider {class check} add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE @@ -520,8 +521,8 @@ add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/c add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1} add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0} add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1} -add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]} -add wave -noupdate -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]} +add wave -noupdate -group {Performance Counters} -label MCYCLE -radix hexadecimal {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]} +add wave -noupdate -group {Performance Counters} -label MINSTRET -radix hexadecimal {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]} add wave -noupdate -group {Performance Counters} -expand -group BP -label Branch -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]} add wave -noupdate -group {Performance Counters} -expand -group BP -label {BP Dir Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]} add wave -noupdate -group {Performance Counters} -expand -group BP -label {Jump (Not Return)} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]} @@ -594,26 +595,19 @@ add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PREADY add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PWDATA add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSTRB add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PENABLE -add wave -noupdate /testbench/LoadMem -add wave -noupdate /testbench/CurrState -add wave -noupdate /testbench/DCacheFlushStart -add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/InstrMName -add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ieu/c/InstrValidM -add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ieu/dp/regf/a3 -add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ieu/dp/regf/rf -add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ieu/dp/regf/wd3 -add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ieu/dp/regf/we3 -add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/ifu/InstrM -add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -label {Contributors: DCacheFlushStart} -group {Contributors: sim:/testbench/DCacheFlushStart} /testbench/ecf -add wave -noupdate /testbench/ecf -add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/memory/ce -add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/memory/we -add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/memory/addr -add wave -noupdate /testbench/dut/uncore/uncore/ram/ram/memory/dout -add wave -noupdate /testbench/reset +add wave -noupdate /testbench/dut/core/priv/priv/privmode/PrivilegeModeW +add wave -noupdate /testbench/dut/core/priv/priv/STATUS_MIE +add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/STATUS_TW +add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/PrivilegeModeW +add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/wfi/WFICount +add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/WFITimeoutM +add wave -noupdate -expand -group rvvi /testbench/wallyTracer/clk +add wave -noupdate -expand -group rvvi /testbench/wallyTracer/InstrValidW +add wave -noupdate -expand -group rvvi /testbench/wallyTracer/PCW +add wave -noupdate -expand -group rvvi /testbench/wallyTracer/InstrRawW +add wave -noupdate -expand -group rvvi /testbench/wallyTracer/valid TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {320072 ns} 0} {{Cursor 4} {19809168 ns} 1} +WaveRestoreCursors {{Cursor 4} {6170 ns} 0} {{Cursor 4} {19809168 ns} 1} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -629,4 +623,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {319935 ns} {320329 ns} +WaveRestoreZoom {6124 ns} {6284 ns} diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index c543348e5..ede8f258e 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -200,7 +200,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( ((P.XLEN == 64) & (Funct3D == 3'b011)); assign BFunctD = Funct3D[2:1] != 2'b01; // legal branches assign JRFunctD = Funct3D == 3'b000; - assign PFunctD = Funct3D == 3'b000 & Rs1D == 5'b0 & RdD == 5'b0; + assign PFunctD = Funct3D == 3'b000 & RdD == 5'b0; assign CSRFunctD = Funct3D[1:0] != 2'b00; assign IWValidFunct3D = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b101; end else begin:legalcheck2 diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index fd2496c44..a95ba8299 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -54,11 +54,9 @@ module csrm import cvw::*; #(parameter cvw_t P) ( logic [P.XLEN-1:0] MISA_REGW, MHARTID_REGW; logic [P.XLEN-1:0] MSCRATCH_REGW, MTVAL_REGW, MCAUSE_REGW; logic [P.XLEN-1:0] MENVCFGH_REGW; - logic [63:0] MENVCFG_PreWriteValM, MENVCFG_WriteValM; logic WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM; logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM; logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM; - logic WriteMENVCFGM; // Machine CSRs localparam MVENDORID = 12'hF11; @@ -82,7 +80,6 @@ module csrm import cvw::*; #(parameter cvw_t P) ( localparam MCAUSE = 12'h342; localparam MTVAL = 12'h343; localparam MIP = 12'h344; - localparam MTINST = 12'h34A; localparam PMPCFG0 = 12'h3A0; // .. up to 15 more at consecutive addresses localparam PMPADDR0 = 12'h3B0; @@ -146,7 +143,6 @@ module csrm import cvw::*; #(parameter cvw_t P) ( assign WriteMCAUSEM = MTrapM | (CSRMWriteM & (CSRAdrM == MCAUSE)); assign WriteMTVALM = MTrapM | (CSRMWriteM & (CSRAdrM == MTVAL)); assign WriteMCOUNTERENM = CSRMWriteM & (CSRAdrM == MCOUNTEREN); - assign WriteMENVCFGM = CSRMWriteM & (CSRAdrM == MENVCFG); assign WriteMCOUNTINHIBITM = CSRMWriteM & (CSRAdrM == MCOUNTINHIBIT); assign IllegalCSRMWriteReadonlyM = UngatedCSRMWriteM & (CSRAdrM == MVENDORID | CSRAdrM == MARCHID | CSRAdrM == MIMPID | CSRAdrM == MHARTID); @@ -168,28 +164,33 @@ module csrm import cvw::*; #(parameter cvw_t P) ( flopenr #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW); end else assign MCOUNTEREN_REGW = '0; - // MENVCFG is always 64 bits even for RV32 - assign MENVCFG_WriteValM = { - MENVCFG_PreWriteValM[63] & P.SSTC_SUPPORTED, - MENVCFG_PreWriteValM[62] & P.SVPBMT_SUPPORTED, - 54'b0, - MENVCFG_PreWriteValM[7] & P.ZICBOZ_SUPPORTED, - MENVCFG_PreWriteValM[6:4] & {3{P.ZICBOM_SUPPORTED}}, - 3'b0, - MENVCFG_PreWriteValM[0] & P.S_SUPPORTED & P.VIRTMEM_SUPPORTED - }; - - if (P.XLEN == 64) begin - assign MENVCFG_PreWriteValM = CSRWriteValM; - flopenr #(P.XLEN) MENVCFGreg(clk, reset, WriteMENVCFGM, MENVCFG_WriteValM, MENVCFG_REGW); - assign MENVCFGH_REGW = 0; - end else begin - logic WriteMENVCFGHM; - assign MENVCFG_PreWriteValM = {CSRWriteValM, CSRWriteValM}; - assign WriteMENVCFGHM = CSRMWriteM & (CSRAdrM == MENVCFGH) & (P.XLEN==32); - flopenr #(P.XLEN) MENVCFGreg(clk, reset, WriteMENVCFGM, MENVCFG_WriteValM[31:0], MENVCFG_REGW[31:0]); - flopenr #(P.XLEN) MENVCFGHreg(clk, reset, WriteMENVCFGHM, MENVCFG_WriteValM[63:32], MENVCFG_REGW[63:32]); - assign MENVCFGH_REGW = MENVCFG_REGW[63:32]; + // MENVCFG register + if (P.U_SUPPORTED) begin // menvcfg only exists if there is a lower privilege to control + logic WriteMENVCFGM; + logic [63:0] MENVCFG_PreWriteValM, MENVCFG_WriteValM; + assign WriteMENVCFGM = CSRMWriteM & (CSRAdrM == MENVCFG); + // MENVCFG is always 64 bits even for RV32 + assign MENVCFG_WriteValM = { + MENVCFG_PreWriteValM[63] & P.SSTC_SUPPORTED, + MENVCFG_PreWriteValM[62] & P.SVPBMT_SUPPORTED, + 54'b0, + MENVCFG_PreWriteValM[7] & P.ZICBOZ_SUPPORTED, + MENVCFG_PreWriteValM[6:4] & {3{P.ZICBOM_SUPPORTED}}, + 3'b0, + MENVCFG_PreWriteValM[0] & P.S_SUPPORTED & P.VIRTMEM_SUPPORTED + }; + if (P.XLEN == 64) begin + assign MENVCFG_PreWriteValM = CSRWriteValM; + flopenr #(P.XLEN) MENVCFGreg(clk, reset, WriteMENVCFGM, MENVCFG_WriteValM, MENVCFG_REGW); + assign MENVCFGH_REGW = 0; + end else begin // RV32 has high and low halves + logic WriteMENVCFGHM; + assign MENVCFG_PreWriteValM = {CSRWriteValM, CSRWriteValM}; + assign WriteMENVCFGHM = CSRMWriteM & (CSRAdrM == MENVCFGH) & (P.XLEN==32); + flopenr #(P.XLEN) MENVCFGreg(clk, reset, WriteMENVCFGM, MENVCFG_WriteValM[31:0], MENVCFG_REGW[31:0]); + flopenr #(P.XLEN) MENVCFGHreg(clk, reset, WriteMENVCFGHM, MENVCFG_WriteValM[63:32], MENVCFG_REGW[63:32]); + assign MENVCFGH_REGW = MENVCFG_REGW[63:32]; + end end // Read machine mode CSRs @@ -197,6 +198,7 @@ module csrm import cvw::*; #(parameter cvw_t P) ( logic [5:0] entry; always_comb begin entry = '0; + CSRMReadValM = 0; IllegalCSRMAccessM = !(P.S_SUPPORTED) & (CSRAdrM == MEDELEG | CSRAdrM == MIDELEG); // trap on DELEG register access when no S or N-mode if (CSRAdrM >= PMPADDR0 & CSRAdrM < PMPADDR0 + P.PMP_ENTRIES) // reading a PMP entry CSRMReadValM = {{(P.XLEN-(P.PA_BITS-2)){1'b0}}, PMPADDR_ARRAY_REGW[CSRAdrM - PMPADDR0]}; @@ -219,7 +221,8 @@ module csrm import cvw::*; #(parameter cvw_t P) ( MHARTID: CSRMReadValM = MHARTID_REGW; // hardwired to 0 MCONFIGPTR: CSRMReadValM = 0; // hardwired to 0 MSTATUS: CSRMReadValM = MSTATUS_REGW; - MSTATUSH: CSRMReadValM = MSTATUSH_REGW; + MSTATUSH: if (P.XLEN==32) CSRMReadValM = MSTATUSH_REGW; + else IllegalCSRMAccessM = 1; MTVEC: CSRMReadValM = MTVEC_REGW; MEDELEG: CSRMReadValM = {{(P.XLEN-16){1'b0}}, MEDELEG_REGW}; MIDELEG: CSRMReadValM = {{(P.XLEN-12){1'b0}}, MIDELEG_REGW}; @@ -229,16 +232,13 @@ module csrm import cvw::*; #(parameter cvw_t P) ( MEPC: CSRMReadValM = MEPC_REGW; MCAUSE: CSRMReadValM = MCAUSE_REGW; MTVAL: CSRMReadValM = MTVAL_REGW; - MTINST: CSRMReadValM = 0; // implemented as trivial zero MCOUNTEREN: CSRMReadValM = {{(P.XLEN-32){1'b0}}, MCOUNTEREN_REGW}; - MENVCFG: CSRMReadValM = MENVCFG_REGW[P.XLEN-1:0]; - MENVCFGH: CSRMReadValM = MENVCFGH_REGW; + MENVCFG: if (P.U_SUPPORTED) CSRMReadValM = MENVCFG_REGW[P.XLEN-1:0]; + else IllegalCSRMAccessM = 1; + MENVCFGH: if (P.U_SUPPORTED & P.XLEN==32) CSRMReadValM = MENVCFGH_REGW; + else IllegalCSRMAccessM = 1; MCOUNTINHIBIT: CSRMReadValM = {{(P.XLEN-32){1'b0}}, MCOUNTINHIBIT_REGW}; - - default: begin - CSRMReadValM = 0; - IllegalCSRMAccessM = 1; - end + default: IllegalCSRMAccessM = 1; endcase end // verilator lint_on WIDTH diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv index 55db35f63..f474627f8 100644 --- a/src/privileged/csrsr.sv +++ b/src/privileged/csrsr.sv @@ -54,7 +54,6 @@ module csrsr import cvw::*; #(parameter cvw_t P) ( // STATUS REGISTER FIELD // See Privileged Spec Section 3.1.6 // Lower privilege status registers are a subset of the full status register - // *** consider adding MBE, SBE, UBE fields, parameterized to be fixed or adjustable if (P.XLEN==64) begin: csrsr64 // RV64 assign MSTATUS_REGW = {STATUS_SD, 25'b0, STATUS_MBE, STATUS_SBE, STATUS_SXL, STATUS_UXL, 9'b0, STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV, diff --git a/testbench/common/functionName.sv b/testbench/common/functionName.sv index 8498a425d..7aebedea8 100644 --- a/testbench/common/functionName.sv +++ b/testbench/common/functionName.sv @@ -119,8 +119,8 @@ module FunctionName import cvw::*; #(parameter cvw_t P) ( // initial begin always @ (negedge reset) begin // clear out the old mapping between programs. - ProgramAddrMapMemory.delete(); - ProgramLabelMapMemory.delete(); + ProgramAddrMapMemory.delete(); + ProgramLabelMapMemory.delete(); $readmemh(ProgramAddrMapFile, ProgramAddrMapMemory); // we need to count the number of lines in the file so we can set FunctionRadixLineCount.