diff --git a/fpga/constraints/constraints.xdc b/fpga/constraints/constraints.xdc
index 6eacaae43..27ac0eec3 100644
--- a/fpga/constraints/constraints.xdc
+++ b/fpga/constraints/constraints.xdc
@@ -3,7 +3,7 @@
 # mmcm_clkout0 is the clock output of the DDR4 memory interface / 4.
 # This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP.
 
-create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 [get_pins wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
+create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
 
 ##### GPI ####
 set_property PACKAGE_PIN BB24 [get_ports {GPI[0]}]
diff --git a/fpga/generator/xlnx_ddr4.tcl b/fpga/generator/xlnx_ddr4.tcl
index 5602ca50f..3be538532 100644
--- a/fpga/generator/xlnx_ddr4.tcl
+++ b/fpga/generator/xlnx_ddr4.tcl
@@ -41,7 +41,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
 			CONFIG.C0.DDR4_CLKOUT0_DIVIDE {6} \
 			CONFIG.Reference_Clock {Differential} \
 			CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
-			CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {10} \
+			CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {40} \
 			CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
 			CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {208} \
 			CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \
diff --git a/pipelined/src/uncore/sdc/SDC.sv b/pipelined/src/uncore/sdc/SDC.sv
index c1fac8ddf..2aa548d87 100644
--- a/pipelined/src/uncore/sdc/SDC.sv
+++ b/pipelined/src/uncore/sdc/SDC.sv
@@ -64,7 +64,7 @@ module SDC
 
 
   // Register outputs
-  logic [7:0] 		    CLKDiv;
+  logic signed [7:0] 		    CLKDiv;
   logic [2:0] 		    Command;
   logic [63:9] 		    Address;
   
@@ -331,8 +331,7 @@ module SDC
 
 
   clkdivider #(8) clkdivider(.i_COUNT_IN_MAX(CLKDiv),
-//			     .i_EN(CLKDiv != 'b1),
-			     .i_EN('1),							 
+			     .i_EN(CLKDiv <= 0), // enable if < 0 (msb is 1)
 			     .i_CLK(CLKGate),
 			     .i_RST(~HRESETn | CLKDivUpdateEn),
 			     .o_CLK(SDCCLKIn));
@@ -358,7 +357,7 @@ module SDC
 		.o_ERROR_CODE_Q(ErrorCode),
 		.o_FATAL_ERROR(FatalError),
 		.i_COUNT_IN_MAX(-8'd62),
-		.LIMIT_SD_TIMERS(1'b1)); // *** must change this to 0 for real hardware.
+		.LIMIT_SD_TIMERS(1'b0)); // *** must change this to 0 for real hardware.
 
   
 endmodule