From 654f3d1940d42c41ec024f7834b77d00538bf4fe Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 13 Sep 2021 12:40:40 -0400 Subject: [PATCH] Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64 --- .../regression/sim-wally-arch-batch-rv32ic | 3 + wally-pipelined/src/privileged/trap.sv | 1 + wally-pipelined/testbench/testbench-arch.sv | 151 ++++++++++-------- 3 files changed, 84 insertions(+), 71 deletions(-) create mode 100755 wally-pipelined/regression/sim-wally-arch-batch-rv32ic diff --git a/wally-pipelined/regression/sim-wally-arch-batch-rv32ic b/wally-pipelined/regression/sim-wally-arch-batch-rv32ic new file mode 100755 index 000000000..bfe114068 --- /dev/null +++ b/wally-pipelined/regression/sim-wally-arch-batch-rv32ic @@ -0,0 +1,3 @@ +vsim -c <