From e81445be5dd61639589e1c965ccf9e358db1dbdd Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 24 Apr 2023 11:06:53 -0500
Subject: [PATCH 01/13] Fixed the local branch predictor so that it at least
 compiles.

---
 src/ifu/bpred/bpred.sv                 | 14 ++++-------
 src/ifu/bpred/localHistoryPredictor.sv | 35 +++++++++++++++++---------
 2 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index 881150b3f..94bbdb517 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -127,19 +127,15 @@ module bpred (
       .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE,
       .BranchE, .BranchM, .PCSrcE);
   
-  end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor
-    // *** Fix me
-/* -----\/----- EXCLUDED -----\/-----
+  end else if (`BPRED_TYPE == "BP_LOCAL") begin:Predictor
     localHistoryPredictor DirPredictor(.clk,
-      .reset, .StallF, .StallE,
+      .reset, .StallD, .StallF, .StallE, .FlushD, .FlushE, 
       .LookUpPC(PCNextF),
-      .Prediction(BPDirPredF),
+      .BPDirPredF,
       // update
       .UpdatePC(PCE),
-      .UpdateEN(InstrClassE[0] & ~StallE),
-      .PCSrcE,
-      .UpdatePrediction(InstrClassE[0]));
- -----/\----- EXCLUDED -----/\----- */
+      .UpdateEN(BranchE & ~StallE),
+      .PCSrcE);
   end 
 
   // Part 2 Branch target address prediction
diff --git a/src/ifu/bpred/localHistoryPredictor.sv b/src/ifu/bpred/localHistoryPredictor.sv
index cde1fa7d3..e34ef80ac 100644
--- a/src/ifu/bpred/localHistoryPredictor.sv
+++ b/src/ifu/bpred/localHistoryPredictor.sv
@@ -32,13 +32,14 @@ module localHistoryPredictor #(parameter m = 6,    // 2^m = number of local hist
                                          k = 10) ( // number of past branches stored
   input  logic             clk,
   input  logic             reset,
-  input  logic             StallF,  StallE,
+  input  logic             StallD, StallF,  StallE,
+  input  logic             FlushD, FlushE,
   input  logic [`XLEN-1:0] LookUpPC,
-  output logic [1:0]       Prediction,
+  output logic [1:0]       BPDirPredF,
   // update
   input logic [`XLEN-1:0]  UpdatePC,
-  input logic              UpdateEN, PCSrcE, 
-  input logic [1:0]        UpdatePrediction
+  input logic              UpdateEN, PCSrcE
+
 );
 
   logic [2**m-1:0][k-1:0]  LHRNextF;
@@ -47,6 +48,9 @@ module localHistoryPredictor #(parameter m = 6,    // 2^m = number of local hist
   logic [1:0]              PredictionMemory;
   logic                    DoForwarding, DoForwardingF, DoForwardingPHT, DoForwardingPHTF;
   logic [1:0]              UpdatePredictionF;
+  logic [1:0]              BPDirPredD, BPDirPredE;
+  logic [1:0]              NewBPDirPredE, NewBPDirPredM;
+  
 
   assign LHRFNext = {PCSrcE, LHRF[k-1:1]}; 
   assign UpdatePCIndex = {UpdatePC[m+1] ^ UpdatePC[1], UpdatePC[m:2]};
@@ -77,20 +81,20 @@ module localHistoryPredictor #(parameter m = 6,    // 2^m = number of local hist
   // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT 
   // LHR referes to the address that the past k branches points to in the prediction stage 
   // LHRE refers to the address that the past k branches points to in the exectution stage
-  ram2p1r1wb #(k, 2) PHT(.clk(clk), 
-    .reset(reset),
+  ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
+    .ce1(~StallF), .ce2(UpdateEN),
     .ra1(ForwardLHRNext),
     .rd1(PredictionMemory),
-    .ren1(~StallF),
     .wa2(LHRFNext),
-    .wd2(UpdatePrediction),
-    .wen2(UpdateEN),
-    .bwe2(2'b11));
+    .wd2(NewBPDirPredE),
+    .we2(UpdateEN),
+    .bwe2(1'b1));
 
 
   
   assign DoForwardingPHT = LHRFNext == ForwardLHRNext; 
 
+
   // register the update value and the forwarding signal into the Fetch stage
   // TODO: add stall logic ***
   flopr #(1) DoForwardingReg(.clk(clk),
@@ -100,11 +104,14 @@ module localHistoryPredictor #(parameter m = 6,    // 2^m = number of local hist
   
   flopr #(2) UpdatePredictionReg(.clk(clk),
      .reset(reset),
-     .d(UpdatePrediction),
+     .d(NewBPDirPredE),
      .q(UpdatePredictionF));
 
-  assign Prediction = DoForwardingPHTF ? UpdatePredictionF : PredictionMemory;
+  assign BPDirPredF = DoForwardingPHTF ? UpdatePredictionF : PredictionMemory;
   
+  flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, BPDirPredF, BPDirPredD);
+  flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, BPDirPredD, BPDirPredE);
+
   //pipeline for LHR
   flopenrc #(k) LHRFReg(.clk(clk),
    .reset(reset),
@@ -112,6 +119,10 @@ module localHistoryPredictor #(parameter m = 6,    // 2^m = number of local hist
    .clear(1'b0),
    .d(ForwardLHRNext),
    .q(LHRF));
+
+   
+  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredE), .NewState(NewBPDirPredE));
+   
   /*
    flopenrc #(k) LHRDReg(.clk(clk),
    .reset(reset),

From 5777b90407a6782e05d38bbdf9838a379632b0aa Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 24 Apr 2023 13:05:28 -0500
Subject: [PATCH 02/13] Might actually have a correct implementation of local
 history branch prediction.

---
 src/ifu/bpred/bpred.sv                 |  12 +-
 src/ifu/bpred/localHistoryPredictor.sv | 166 ++++++++++---------------
 2 files changed, 67 insertions(+), 111 deletions(-)

diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index 94bbdb517..38684a309 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -128,14 +128,10 @@ module bpred (
       .BranchE, .BranchM, .PCSrcE);
   
   end else if (`BPRED_TYPE == "BP_LOCAL") begin:Predictor
-    localHistoryPredictor DirPredictor(.clk,
-      .reset, .StallD, .StallF, .StallE, .FlushD, .FlushE, 
-      .LookUpPC(PCNextF),
-      .BPDirPredF,
-      // update
-      .UpdatePC(PCE),
-      .UpdateEN(BranchE & ~StallE),
-      .PCSrcE);
+    localHistoryPredictor #(6, 10)
+DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+      .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE,
+      .BranchE, .BranchM, .PCSrcE);
   end 
 
   // Part 2 Branch target address prediction
diff --git a/src/ifu/bpred/localHistoryPredictor.sv b/src/ifu/bpred/localHistoryPredictor.sv
index e34ef80ac..9223f0c7d 100644
--- a/src/ifu/bpred/localHistoryPredictor.sv
+++ b/src/ifu/bpred/localHistoryPredictor.sv
@@ -1,10 +1,11 @@
 ///////////////////////////////////////////
-// locallHistoryPredictor.sv
+// gsharebasic.sv
 //
-// Written: Shreya Sanghai
-// Email: ssanghai@hmc.edu
-// Created: March 16, 2021
-// Modified: 
+// Written: Ross Thompson
+// Email: ross1728@gmail.com
+// Created: 16 March 2021
+// Adapted from ssanghai@hmc.edu (Shreya Sanghai) global history predictor implementation.
+// Modified: 20 February 2023 
 //
 // Purpose: Global History Branch predictor with parameterized global history register
 // 
@@ -28,114 +29,73 @@
 
 `include "wally-config.vh"
 
-module localHistoryPredictor #(parameter m = 6,    // 2^m = number of local history branches
-                                         k = 10) ( // number of past branches stored
-  input  logic             clk,
-  input  logic             reset,
-  input  logic             StallD, StallF,  StallE,
-  input  logic             FlushD, FlushE,
-  input  logic [`XLEN-1:0] LookUpPC,
-  output logic [1:0]       BPDirPredF,
+module localHistoryPredictor #(parameter m = 6, // 2^m = number of local history branches 
+                               parameter k = 10) ( // number of past branches stored
+  input logic             clk,
+  input logic             reset,
+  input logic             StallF, StallD, StallE, StallM, StallW,
+  input logic             FlushD, FlushE, FlushM, FlushW,
+  output logic [1:0]      BPDirPredF, 
+  output logic            BPDirPredWrongE,
   // update
-  input logic [`XLEN-1:0]  UpdatePC,
-  input logic              UpdateEN, PCSrcE
-
+  input logic [`XLEN-1:0] PCNextF, PCM,
+  input logic             BranchE, BranchM, PCSrcE
 );
 
-  logic [2**m-1:0][k-1:0]  LHRNextF;
-  logic [k-1:0]            LHRF, ForwardLHRNext, LHRFNext;
-  logic [m-1:0]            LookUpPCIndex, UpdatePCIndex;
-  logic [1:0]              PredictionMemory;
-  logic                    DoForwarding, DoForwardingF, DoForwardingPHT, DoForwardingPHTF;
-  logic [1:0]              UpdatePredictionF;
-  logic [1:0]              BPDirPredD, BPDirPredE;
-  logic [1:0]              NewBPDirPredE, NewBPDirPredM;
+  logic [k-1:0]           IndexNextF, IndexM;
+  logic [1:0]             BPDirPredD, BPDirPredE;
+  logic [1:0]             NewBPDirPredE, NewBPDirPredM;
+
+  logic [k-1:0]           GHRF, GHRD, GHRE, GHRM, GHR;
+  logic [k-1:0]           GHRNext;
+  logic                   PCSrcM;
+  logic [2**m-1:0][k-1:0]  LHR;
+  logic [m-1:0]            IndexLHRNextF, IndexLHRM;
   
+  logic                    UpdateM;
 
-  assign LHRFNext = {PCSrcE, LHRF[k-1:1]}; 
-  assign UpdatePCIndex = {UpdatePC[m+1] ^ UpdatePC[1], UpdatePC[m:2]};
-  assign LookUpPCIndex = {LookUpPC[m+1] ^ LookUpPC[1], LookUpPC[m:2]};  
-
-  // INCASE we do ahead pipelining
-  //    ram2p1r1wb #(m,k) LHR(.clk(clk)),
-  //                 .reset(reset),
-  //                 .RA1(LookUpPCIndex), // need hashing function to get correct PC address 
-  //                 .RD1(LHRF),
-  //                 .REN1(~StallF),
-  //                 .WA1(UpdatePCIndex),
-  //                 .WD1(LHRENExt),
-  //                 .WEN1(UpdateEN),
-  //                 .BitWEN1(2'b11));  
-
-  genvar      index;
-  for (index = 0; index < 2**m; index = index +1) begin:localhist
-    flopenr #(k) LocalHistoryRegister(.clk, .reset, .en(UpdateEN & (index == UpdatePCIndex)),
-                                      .d(LHRFNext), .q(LHRNextF[index]));
-  end 
-
-  // need to forward when updating to the same address as reading.
-  // first we compare to see if the update and lookup addreses are the same
-  assign DoForwarding = LookUpPCIndex == UpdatePCIndex;
-  assign ForwardLHRNext = DoForwarding ? LHRFNext :LHRNextF[LookUpPCIndex]; 
-
-  // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT 
-  // LHR referes to the address that the past k branches points to in the prediction stage 
-  // LHRE refers to the address that the past k branches points to in the exectution stage
+  assign IndexNextF = GHRNext;
+  assign IndexM = GHRM;
+  
   ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
-    .ce1(~StallF), .ce2(UpdateEN),
-    .ra1(ForwardLHRNext),
-    .rd1(PredictionMemory),
-    .wa2(LHRFNext),
-    .wd2(NewBPDirPredE),
-    .we2(UpdateEN),
+    .ce1(~StallF), .ce2(~StallW & ~FlushW),
+    .ra1(IndexNextF),
+    .rd1(BPDirPredF),
+    .wa2(IndexM),
+    .wd2(NewBPDirPredM),
+    .we2(BranchM),
     .bwe2(1'b1));
 
-
-  
-  assign DoForwardingPHT = LHRFNext == ForwardLHRNext; 
-
-
-  // register the update value and the forwarding signal into the Fetch stage
-  // TODO: add stall logic ***
-  flopr #(1) DoForwardingReg(.clk(clk),
-        .reset(reset),
-        .d(DoForwardingPHT),
-        .q(DoForwardingPHTF));
-  
-  flopr #(2) UpdatePredictionReg(.clk(clk),
-     .reset(reset),
-     .d(NewBPDirPredE),
-     .q(UpdatePredictionF));
-
-  assign BPDirPredF = DoForwardingPHTF ? UpdatePredictionF : PredictionMemory;
-  
   flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, BPDirPredF, BPDirPredD);
   flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, BPDirPredD, BPDirPredE);
 
-  //pipeline for LHR
-  flopenrc #(k) LHRFReg(.clk(clk),
-   .reset(reset),
-   .en(~StallF),
-   .clear(1'b0),
-   .d(ForwardLHRNext),
-   .q(LHRF));
-
-   
   satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredE), .NewState(NewBPDirPredE));
-   
-  /*
-   flopenrc #(k) LHRDReg(.clk(clk),
-   .reset(reset),
-   .en(~StallD),
-   .clear(FlushD),
-   .d(LHRF),
-   .q(LHRD));
-   
-   flopenrc #(k) LHREReg(.clk(clk),
-   .reset(reset),
-   .en(~StallE),
-   .clear(FlushE),
-   .d(LHRD),
-   .q(LHRE));
-   */
+  flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM);
+
+  assign BPDirPredWrongE = PCSrcE != BPDirPredE[1] & BranchE;
+
+  assign GHRNext = BranchM ? {PCSrcM, GHR[k-1:1]} : GHR;
+
+  // this is local history
+  genvar      index;
+  assign UpdateM = BranchM & ~StallM & ~FlushM;
+  assign IndexLHRM = {PCM[m+1] ^ PCM[1], PCM[m:2]};
+  for (index = 0; index < 2**m; index = index +1) begin:localhist
+    flopenr #(k) LocalHistoryRegister(.clk, .reset, .en(UpdateM & (index == IndexLHRM)),
+                                      .d(GHRNext), .q(LHR[index]));
+  end
+  assign IndexLHRNextF = {PCNextF[m+1] ^ PCNextF[1], PCNextF[m:2]};
+  assign GHR = LHR[IndexLHRNextF];
+
+  // this is global history
+  //flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchM, GHRNext, GHR);
+
+  flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
+    
+  flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
+  flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD);
+  flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE);
+  flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM);
+
+
 endmodule

From 4eff75449a88878ef41909f4d5f6cd65d76a1215 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 1 May 2023 15:45:27 -0500
Subject: [PATCH 03/13] Maybe have the baseline local history predictor
 working.

---
 src/ifu/bpred/localHistoryPredictor.sv | 28 +++++++++++++-------------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/src/ifu/bpred/localHistoryPredictor.sv b/src/ifu/bpred/localHistoryPredictor.sv
index 9223f0c7d..60471b701 100644
--- a/src/ifu/bpred/localHistoryPredictor.sv
+++ b/src/ifu/bpred/localHistoryPredictor.sv
@@ -46,16 +46,16 @@ module localHistoryPredictor #(parameter m = 6, // 2^m = number of local history
   logic [1:0]             BPDirPredD, BPDirPredE;
   logic [1:0]             NewBPDirPredE, NewBPDirPredM;
 
-  logic [k-1:0]           GHRF, GHRD, GHRE, GHRM, GHR;
-  logic [k-1:0]           GHRNext;
+  logic [k-1:0]           LHRF, LHRD, LHRE, LHRM, LHR;
+  logic [k-1:0]           LHRNextW;
   logic                   PCSrcM;
-  logic [2**m-1:0][k-1:0]  LHR;
+  logic [2**m-1:0][k-1:0]  LHRArray;
   logic [m-1:0]            IndexLHRNextF, IndexLHRM;
   
   logic                    UpdateM;
 
-  assign IndexNextF = GHRNext;
-  assign IndexM = GHRM;
+  assign IndexNextF = LHR;
+  assign IndexM = LHRM;
   
   ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallW & ~FlushW),
@@ -74,28 +74,28 @@ module localHistoryPredictor #(parameter m = 6, // 2^m = number of local history
 
   assign BPDirPredWrongE = PCSrcE != BPDirPredE[1] & BranchE;
 
-  assign GHRNext = BranchM ? {PCSrcM, GHR[k-1:1]} : GHR;
+  assign LHRNextW = BranchM ? {PCSrcM, LHRM[k-1:1]} : LHRM;
 
   // this is local history
   genvar      index;
-  assign UpdateM = BranchM & ~StallM & ~FlushM;
+  assign UpdateM = BranchM & ~StallW & ~FlushW;
   assign IndexLHRM = {PCM[m+1] ^ PCM[1], PCM[m:2]};
   for (index = 0; index < 2**m; index = index +1) begin:localhist
     flopenr #(k) LocalHistoryRegister(.clk, .reset, .en(UpdateM & (index == IndexLHRM)),
-                                      .d(GHRNext), .q(LHR[index]));
+                                      .d(LHRNextW), .q(LHRArray[index]));
   end
   assign IndexLHRNextF = {PCNextF[m+1] ^ PCNextF[1], PCNextF[m:2]};
-  assign GHR = LHR[IndexLHRNextF];
+  assign LHR = LHRArray[IndexLHRNextF];
 
   // this is global history
-  //flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchM, GHRNext, GHR);
+  //flopenr #(k) LHRReg(clk, reset, ~StallM & ~FlushM & BranchM, LHRNextW, LHR);
 
   flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
     
-  flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
-  flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD);
-  flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE);
-  flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM);
+  flopenrc #(k) LHRFReg(clk, reset, FlushD, ~StallF, LHR, LHRF);
+  flopenrc #(k) LHRDReg(clk, reset, FlushD, ~StallD, LHRF, LHRD);
+  flopenrc #(k) LHREReg(clk, reset, FlushE, ~StallE, LHRD, LHRE);
+  flopenrc #(k) LHRMReg(clk, reset, FlushM, ~StallM, LHRE, LHRM);
 
 
 endmodule

From 0904a9b97f7c551b71c3a5ebbfa4255db5a5ffb3 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Tue, 2 May 2023 10:52:41 -0500
Subject: [PATCH 04/13] Swapped the m and k parameters for local history
 predictor.

---
 src/ifu/bpred/bpred.sv | 4 ++--
 testbench/tests.vh     | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index 38684a309..4be60b57f 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -28,7 +28,7 @@
 
 `include "wally-config.vh"
 
-`define INSTR_CLASS_PRED 1
+`define INSTR_CLASS_PRED 0
 
 module bpred (
   input  logic             clk, reset,
@@ -128,7 +128,7 @@ module bpred (
       .BranchE, .BranchM, .PCSrcE);
   
   end else if (`BPRED_TYPE == "BP_LOCAL") begin:Predictor
-    localHistoryPredictor #(6, 10)
+    localHistoryPredictor #(`BPRED_NUM_LHR, `BPRED_SIZE)
 DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE,
       .BranchE, .BranchM, .PCSrcE);
diff --git a/testbench/tests.vh b/testbench/tests.vh
index ffe718188..fde90f591 100644
--- a/testbench/tests.vh
+++ b/testbench/tests.vh
@@ -2057,8 +2057,8 @@ string arch64zbs[] = '{
 
  string custom[] = '{
     `CUSTOM,
-    "debug",
     "simple",
+    "debug",
     "cacheTest"
  };
   string testsBP64[] = '{

From 08b237b8784133ec9a4702bab7d90405c460f8ee Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Tue, 2 May 2023 11:01:46 -0500
Subject: [PATCH 05/13] Added comment explaining the difference between global
 history and local history basic implementations.

---
 src/ifu/bpred/localHistoryPredictor.sv | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/ifu/bpred/localHistoryPredictor.sv b/src/ifu/bpred/localHistoryPredictor.sv
index 60471b701..e2f267fff 100644
--- a/src/ifu/bpred/localHistoryPredictor.sv
+++ b/src/ifu/bpred/localHistoryPredictor.sv
@@ -74,6 +74,12 @@ module localHistoryPredictor #(parameter m = 6, // 2^m = number of local history
 
   assign BPDirPredWrongE = PCSrcE != BPDirPredE[1] & BranchE;
 
+  // this is the main difference between global and local history basic implementations rather than
+  // having multiple history registers.  In global, the ghr wraps back into itself directly without
+  // being pipelined.  IE. GHR is not read in F and then pipelined to M where it is updated.  Instead
+  // GHR is just read in M and updated.  GHR is still pipelined so that the PHT is updated with the correct
+  // GHR.  Local history in contrast must pipeline the specific history register read during F and then update
+  // that same one in M.  This implementation does not forward if a branch matches in the D, E, or M stages.
   assign LHRNextW = BranchM ? {PCSrcM, LHRM[k-1:1]} : LHRM;
 
   // this is local history

From 414c79b923cac0f8500553ba34b0a8f617674100 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Tue, 2 May 2023 11:11:04 -0500
Subject: [PATCH 06/13] Updated configs for local branch history `defines.

---
 config/buildroot/wally-config.vh                            | 1 +
 config/fpga/wally-config.vh                                 | 1 +
 config/rv32e/wally-config.vh                                | 1 +
 config/rv32gc/wally-config.vh                               | 3 ++-
 config/rv32i/wally-config.vh                                | 1 +
 config/rv32imc/wally-config.vh                              | 1 +
 config/rv64fpquad/wally-config.vh                           | 1 +
 config/rv64gc/wally-config.vh                               | 4 +++-
 config/rv64i/wally-config.vh                                | 1 +
 src/ifu/bpred/bpred.sv                                      | 4 ++--
 src/ifu/bpred/{localHistoryPredictor.sv => localbpbasic.sv} | 4 ++--
 11 files changed, 16 insertions(+), 6 deletions(-)
 rename src/ifu/bpred/{localHistoryPredictor.sv => localbpbasic.sv} (96%)

diff --git a/config/buildroot/wally-config.vh b/config/buildroot/wally-config.vh
index 236574288..0957dd003 100644
--- a/config/buildroot/wally-config.vh
+++ b/config/buildroot/wally-config.vh
@@ -132,6 +132,7 @@
 `define BPRED_SUPPORTED 1
 `define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 `define BPRED_SIZE 10
+`define BPRED_NUM_LHR 6
 `define BTB_SIZE 10
 
 
diff --git a/config/fpga/wally-config.vh b/config/fpga/wally-config.vh
index 1f7447f4d..9230c148e 100644
--- a/config/fpga/wally-config.vh
+++ b/config/fpga/wally-config.vh
@@ -141,6 +141,7 @@
 `define BPRED_SUPPORTED 1
 `define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 `define BPRED_SIZE 12
+`define BPRED_NUM_LHR 6
 `define BTB_SIZE 10
 
 
diff --git a/config/rv32e/wally-config.vh b/config/rv32e/wally-config.vh
index aee0e5410..700117e3d 100644
--- a/config/rv32e/wally-config.vh
+++ b/config/rv32e/wally-config.vh
@@ -136,6 +136,7 @@
 `define BPRED_SUPPORTED 0
 `define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 `define BPRED_SIZE 10
+`define BPRED_NUM_LHR 6
 `define BTB_SIZE 10
 
 `define SVADU_SUPPORTED 0
diff --git a/config/rv32gc/wally-config.vh b/config/rv32gc/wally-config.vh
index 37eff79ea..d6f75ba08 100644
--- a/config/rv32gc/wally-config.vh
+++ b/config/rv32gc/wally-config.vh
@@ -133,8 +133,9 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_SUPPORTED 1
-`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
+`define BPRED_TYPE "BP_LOCAL_BASIC" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 `define BPRED_SIZE 16
+`define BPRED_NUM_LHR 8
 `define BTB_SIZE 10
 
 `define SVADU_SUPPORTED 1
diff --git a/config/rv32i/wally-config.vh b/config/rv32i/wally-config.vh
index d75d0c462..585499169 100644
--- a/config/rv32i/wally-config.vh
+++ b/config/rv32i/wally-config.vh
@@ -136,6 +136,7 @@
 `define BPRED_SUPPORTED 0
 `define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 `define BPRED_SIZE 10
+`define BPRED_NUM_LHR 6
 `define BTB_SIZE 10
 
 `define SVADU_SUPPORTED 0
diff --git a/config/rv32imc/wally-config.vh b/config/rv32imc/wally-config.vh
index 42442d46e..093d92bd7 100644
--- a/config/rv32imc/wally-config.vh
+++ b/config/rv32imc/wally-config.vh
@@ -135,6 +135,7 @@
 `define BPRED_SUPPORTED 0
 `define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 `define BPRED_SIZE 10
+`define BPRED_NUM_LHR 6
 `define BTB_SIZE 10
 
 `define SVADU_SUPPORTED 0
diff --git a/config/rv64fpquad/wally-config.vh b/config/rv64fpquad/wally-config.vh
index 34d7628e0..45725645f 100644
--- a/config/rv64fpquad/wally-config.vh
+++ b/config/rv64fpquad/wally-config.vh
@@ -138,6 +138,7 @@
 `define BPRED_SUPPORTED 1
 `define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 `define BPRED_SIZE 10
+`define BPRED_NUM_LHR 6
 `define BTB_SIZE 10
 
 `define SVADU_SUPPORTED 0
diff --git a/config/rv64gc/wally-config.vh b/config/rv64gc/wally-config.vh
index b44351ef2..69f4cdcfb 100644
--- a/config/rv64gc/wally-config.vh
+++ b/config/rv64gc/wally-config.vh
@@ -136,8 +136,10 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_SUPPORTED 1
-`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
+//`define BPRED_TYPE "BP_GLOBAL_BASIC" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
+`define BPRED_TYPE "BP_LOCAL_BASIC" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 `define BPRED_SIZE 10
+`define BPRED_NUM_LHR 6
 `define BTB_SIZE 10
 
 `define SVADU_SUPPORTED 1
diff --git a/config/rv64i/wally-config.vh b/config/rv64i/wally-config.vh
index 34c37f73a..61ac725db 100644
--- a/config/rv64i/wally-config.vh
+++ b/config/rv64i/wally-config.vh
@@ -138,6 +138,7 @@
 `define BPRED_SUPPORTED 0
 `define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 `define BPRED_SIZE 10
+`define BPRED_NUM_LHR 6
 `define BTB_SIZE 10
 
 `define SVADU_SUPPORTED 0
diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index 4be60b57f..c3ac87232 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -127,8 +127,8 @@ module bpred (
       .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE,
       .BranchE, .BranchM, .PCSrcE);
   
-  end else if (`BPRED_TYPE == "BP_LOCAL") begin:Predictor
-    localHistoryPredictor #(`BPRED_NUM_LHR, `BPRED_SIZE)
+  end else if (`BPRED_TYPE == "BP_LOCAL_BASIC") begin:Predictor
+    localbpbasic #(`BPRED_NUM_LHR, `BPRED_SIZE)
 DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE,
       .BranchE, .BranchM, .PCSrcE);
diff --git a/src/ifu/bpred/localHistoryPredictor.sv b/src/ifu/bpred/localbpbasic.sv
similarity index 96%
rename from src/ifu/bpred/localHistoryPredictor.sv
rename to src/ifu/bpred/localbpbasic.sv
index e2f267fff..de0d94414 100644
--- a/src/ifu/bpred/localHistoryPredictor.sv
+++ b/src/ifu/bpred/localbpbasic.sv
@@ -29,8 +29,8 @@
 
 `include "wally-config.vh"
 
-module localHistoryPredictor #(parameter m = 6, // 2^m = number of local history branches 
-                               parameter k = 10) ( // number of past branches stored
+module localbpbasic #(parameter m = 6, // 2^m = number of local history branches 
+                      parameter k = 10) ( // number of past branches stored
   input logic             clk,
   input logic             reset,
   input logic             StallF, StallD, StallE, StallM, StallW,

From 8b0791b6b59f99215c80a6222f11d6df76346a2f Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 3 May 2023 12:52:32 -0500
Subject: [PATCH 07/13] I think ahead pipelining is working for local history.

---
 bin/parseHPMC.py              |   7 ++-
 sim/bpred-sim.py              |  33 +++++++---
 src/ifu/bpred/bpred.sv        |   9 ++-
 src/ifu/bpred/localaheadbp.sv | 111 ++++++++++++++++++++++++++++++++++
 src/ifu/bpred/localbpbasic.sv |   8 +--
 testbench/testbench.sv        |  17 +++++-
 6 files changed, 166 insertions(+), 19 deletions(-)
 create mode 100644 src/ifu/bpred/localaheadbp.sv

diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py
index 5b5e0d98b..7d65f120c 100755
--- a/bin/parseHPMC.py
+++ b/bin/parseHPMC.py
@@ -279,12 +279,13 @@ if(sys.argv[1] == '-b'):
                     dct[PredType] = (currSize, currPercent)
         print(dct)
         fig, axes = plt.subplots()
-        marker={'twobit' : '^', 'gshare' : 'o', 'global' : 's', 'gshareBasic' : '*', 'globalBasic' : 'x', 'btb': 'x', 'twobitCModel' : 'x', 'gshareCModel' : '*'}
-        colors={'twobit' : 'black', 'gshare' : 'blue', 'global' : 'dodgerblue', 'gshareBasic' : 'turquoise', 'globalBasic' : 'lightsteelblue', 'btb' : 'blue', 'twobitCModel' : 'gray', 'gshareCModel' : 'dodgerblue'}
+        marker={'twobit' : '^', 'gshare' : 'o', 'global' : 's', 'gshareBasic' : '*', 'globalBasic' : 'x', 'btb': 'x', 'twobitCModel' : 'x', 'gshareCModel' : '*', 'tenlocal' : '.', 'eightlocal' : ',', 'fourlocal' : 'x'}
+        colors={'twobit' : 'black', 'gshare' : 'blue', 'global' : 'dodgerblue', 'gshareBasic' : 'turquoise', 'globalBasic' : 'lightsteelblue', 'btb' : 'blue', 'twobitCModel' : 'gray', 'gshareCModel' : 'dodgerblue', 'tenlocal' : 'lightblue', 'eightlocal' : 'lightblue', 'fourlocal' : 'lightblue'}
         for cat in dct:
             (x, y) = dct[cat]
             x=[int(2**int(v)) for v in x]
-            print(x, y)
+            #print(x, y)
+            print(cat)
             axes.plot(x,y, color=colors[cat])
             axes.scatter(x,y, label=cat, marker=marker[cat], color=colors[cat])
             #plt.scatter(x, y, label=cat)
diff --git a/sim/bpred-sim.py b/sim/bpred-sim.py
index 60574e371..256658a6c 100755
--- a/sim/bpred-sim.py
+++ b/sim/bpred-sim.py
@@ -46,18 +46,33 @@ configs = [
     )
 ]
 
+# bpdSize = [6, 8, 10, 12, 14, 16]
+# bpdType = ['twobit', 'gshare', 'global', 'gshare_basic', 'global_basic', 'local_basic']
+# for CurrBPType in bpdType:
+#     for CurrBPSize in bpdSize:
+#         name = CurrBPType+str(CurrBPSize)
+#         configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_TYPE=\"BP_" + CurrBPType.upper() + "\" +define+BPRED_SIZE=" + str(CurrBPSize)
+#         tc = TestCase(
+#             name=name,
+#             variant="rv32gc",
+#             cmd="vsim > {} -c <<!\ndo wally-batch.do  rv32gc configOptions " + name + " embench " + configOptions,
+#             grepstr="")
+#         configs.append(tc)
+
 bpdSize = [6, 8, 10, 12, 14, 16]
-bpdType = ['twobit', 'gshare', 'global', 'gshare_basic', 'global_basic']
+LHRSize = [4, 8, 10]
+bpdType = ['local_basic']
 for CurrBPType in bpdType:
     for CurrBPSize in bpdSize:
-        name = CurrBPType+str(CurrBPSize)
-        configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_TYPE=\"BP_" + CurrBPType.upper() + "\" +define+BPRED_SIZE=" + str(CurrBPSize)
-        tc = TestCase(
-            name=name,
-            variant="rv32gc",
-            cmd="vsim > {} -c <<!\ndo wally-batch.do  rv32gc configOptions " + name + " embench " + configOptions,
-            grepstr="")
-        configs.append(tc)
+        for CurrLHRSize in  LHRSize:
+            name = str(CurrLHRSize)+CurrBPType+str(CurrBPSize)
+            configOptions = "+define+INSTR_CLASS_PRED=0 +define+BPRED_TYPE=\"BP_" + CurrBPType.upper() + "\" +define+BPRED_SIZE=" + str(CurrBPSize) + " +define+BPRED_NUM_LHR=" + str(CurrLHRSize) + " "
+            tc = TestCase(
+                name=name,
+                variant="rv32gc",
+                cmd="vsim > {} -c <<!\ndo wally-batch.do  rv32gc configOptions " + name + " embench " + configOptions,
+                grepstr="")
+            configs.append(tc)
 
 import os
 from multiprocessing import Pool, TimeoutError
diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index c3ac87232..2034851bc 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -128,8 +128,13 @@ module bpred (
       .BranchE, .BranchM, .PCSrcE);
   
   end else if (`BPRED_TYPE == "BP_LOCAL_BASIC") begin:Predictor
-    localbpbasic #(`BPRED_NUM_LHR, `BPRED_SIZE)
-DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+    localbpbasic #(`BPRED_NUM_LHR, `BPRED_SIZE) DirPredictor(.clk, .reset, 
+      .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+      .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE,
+      .BranchE, .BranchM, .PCSrcE);
+  end else if (`BPRED_TYPE == "BP_LOCAL_AHEAD") begin:Predictor
+    localaheadbp #(`BPRED_NUM_LHR, `BPRED_SIZE) DirPredictor(.clk, .reset, 
+      .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE,
       .BranchE, .BranchM, .PCSrcE);
   end 
diff --git a/src/ifu/bpred/localaheadbp.sv b/src/ifu/bpred/localaheadbp.sv
new file mode 100644
index 000000000..a0bc12fe3
--- /dev/null
+++ b/src/ifu/bpred/localaheadbp.sv
@@ -0,0 +1,111 @@
+///////////////////////////////////////////
+// gsharebasic.sv
+//
+// Written: Ross Thompson
+// Email: ross1728@gmail.com
+// Created: 16 March 2021
+// Adapted from ssanghai@hmc.edu (Shreya Sanghai) global history predictor implementation.
+// Modified: 20 February 2023 
+//
+// Purpose: Global History Branch predictor with parameterized global history register
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module localaheadbp #(parameter m = 6, // 2^m = number of local history branches 
+                      parameter k = 10) ( // number of past branches stored
+  input logic             clk,
+  input logic             reset,
+  input logic             StallF, StallD, StallE, StallM, StallW,
+  input logic             FlushD, FlushE, FlushM, FlushW,
+  output logic [1:0]      BPDirPredF, 
+  output logic            BPDirPredWrongE,
+  // update
+  input logic [`XLEN-1:0] PCNextF, PCM,
+  input logic             BranchE, BranchM, PCSrcE
+);
+
+  logic [k-1:0]           IndexNextF, IndexM;
+  logic [1:0]             BPDirPredD, BPDirPredE;
+  logic [1:0]             NewBPDirPredE, NewBPDirPredM;
+
+  logic [k-1:0]           LHRF, LHRD, LHRE, LHRM, LHRNextF;
+  logic [k-1:0]           LHRNextW;
+  logic                   PCSrcM;
+  logic [2**m-1:0][k-1:0] LHRArray;
+  logic [m-1:0]           IndexLHRNextF, IndexLHRM;
+  logic [`XLEN-1:0]       PCW;
+  
+  
+  logic                    UpdateM;
+
+  //assign IndexNextF = LHR;
+  assign IndexM = LHRM;
+  
+  ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
+    .ce1(~StallF), .ce2(~StallW & ~FlushW),
+    .ra1(LHRNextF),
+    .rd1(BPDirPredF),
+    .wa2(IndexM),
+    .wd2(NewBPDirPredM),
+    .we2(BranchM),
+    .bwe2(1'b1));
+
+  flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, BPDirPredF, BPDirPredD);
+  flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, BPDirPredD, BPDirPredE);
+
+  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredE), .NewState(NewBPDirPredE));
+  flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM);
+
+  assign BPDirPredWrongE = PCSrcE != BPDirPredE[1] & BranchE;
+
+  // This is the main difference between global and local history basic implementations. In global, 
+  // the ghr wraps back into itself directly without
+  // being pipelined.  I.E. GHR is not read in F and then pipelined to M where it is updated.  Instead
+  // GHR is both read and update in M.  GHR is still pipelined so that the PHT is updated with the correct
+  // GHR.  Local history in contrast must pipeline the specific history register read during F and then update
+  // that same one in M.  This implementation does not forward if a branch matches in the D, E, or M stages.
+  assign LHRNextW = BranchM ? {PCSrcM, LHRM[k-1:1]} : LHRM;
+
+  // this is local history
+  //genvar      index;
+  //assign UpdateM = BranchM & ~StallW & ~FlushW;
+  assign IndexLHRM = {PCW[m+1] ^ PCW[1], PCW[m:2]};
+  assign IndexLHRNextF = {PCNextF[m+1] ^ PCNextF[1], PCNextF[m:2]};
+
+  ram2p1r1wbe #(2**m, k) BHT(.clk(clk),
+    .ce1(~StallF), .ce2(~StallW & ~FlushW),
+    .ra1(IndexLHRNextF),
+    .rd1(LHRNextF),
+    .wa2(IndexLHRM),
+    .wd2(LHRNextW),
+    .we2(BranchM),
+    .bwe2('1));  
+
+  flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
+    
+  flopenrc #(k) LHRFReg(clk, reset, FlushD, ~StallF, LHRNextF, LHRF);
+  flopenrc #(k) LHRDReg(clk, reset, FlushD, ~StallD, LHRF, LHRD);
+  flopenrc #(k) LHREReg(clk, reset, FlushE, ~StallE, LHRD, LHRE);
+  flopenrc #(k) LHRMReg(clk, reset, FlushM, ~StallM, LHRE, LHRM);
+
+  flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
+
+endmodule
diff --git a/src/ifu/bpred/localbpbasic.sv b/src/ifu/bpred/localbpbasic.sv
index de0d94414..a874dfce2 100644
--- a/src/ifu/bpred/localbpbasic.sv
+++ b/src/ifu/bpred/localbpbasic.sv
@@ -74,10 +74,10 @@ module localbpbasic #(parameter m = 6, // 2^m = number of local history branches
 
   assign BPDirPredWrongE = PCSrcE != BPDirPredE[1] & BranchE;
 
-  // this is the main difference between global and local history basic implementations rather than
-  // having multiple history registers.  In global, the ghr wraps back into itself directly without
-  // being pipelined.  IE. GHR is not read in F and then pipelined to M where it is updated.  Instead
-  // GHR is just read in M and updated.  GHR is still pipelined so that the PHT is updated with the correct
+  // This is the main difference between global and local history basic implementations. In global, 
+  // the ghr wraps back into itself directly without
+  // being pipelined.  I.E. GHR is not read in F and then pipelined to M where it is updated.  Instead
+  // GHR is both read and update in M.  GHR is still pipelined so that the PHT is updated with the correct
   // GHR.  Local history in contrast must pipeline the specific history register read during F and then update
   // that same one in M.  This implementation does not forward if a branch matches in the D, E, or M stages.
   assign LHRNextW = BranchM ? {PCSrcM, LHRM[k-1:1]} : LHRM;
diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index 9021b6448..0112c24bd 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -28,7 +28,7 @@
 `include "wally-config.vh"
 `include "tests.vh"
 
-`define PrintHPMCounters 0
+`define PrintHPMCounters 1
 `define BPRED_LOGGER 0
 `define I_CACHE_ADDR_LOGGER 0
 `define D_CACHE_ADDR_LOGGER 0
@@ -536,6 +536,21 @@ module testbench;
   if (`BPRED_SUPPORTED) begin
     integer adrindex;
 
+    // local history only
+    if (`BPRED_TYPE == "BP_LOCAL_AHEAD") begin
+      always @(*) begin
+        if(reset) begin
+          for(adrindex = 0; adrindex < 2**`BPRED_NUM_LHR; adrindex++) begin
+            force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex] = 0;
+          end
+            #1;
+          for(adrindex = 0; adrindex < 2**`BPRED_NUM_LHR; adrindex++) begin
+            release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex];
+          end
+        end
+      end
+    end
+
     always @(*) begin
       if(reset) begin
         for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin

From 060d40853ad03b7b02f0aece9f2233b294f9e2b1 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 3 May 2023 17:41:38 -0500
Subject: [PATCH 08/13] Ahead pipelining is not yet working. :(

---
 src/ifu/bpred/bpred.sv        |  2 +-
 src/ifu/bpred/localaheadbp.sv | 19 +++++++++++--------
 2 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index 2034851bc..f7cec5be7 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -135,7 +135,7 @@ module bpred (
   end else if (`BPRED_TYPE == "BP_LOCAL_AHEAD") begin:Predictor
     localaheadbp #(`BPRED_NUM_LHR, `BPRED_SIZE) DirPredictor(.clk, .reset, 
       .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-      .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE,
+      .PCNextF, .PCM, .BPDirPredD(BPDirPredF), .BPDirPredWrongE,
       .BranchE, .BranchM, .PCSrcE);
   end 
 
diff --git a/src/ifu/bpred/localaheadbp.sv b/src/ifu/bpred/localaheadbp.sv
index a0bc12fe3..e6577770b 100644
--- a/src/ifu/bpred/localaheadbp.sv
+++ b/src/ifu/bpred/localaheadbp.sv
@@ -35,7 +35,7 @@ module localaheadbp #(parameter m = 6, // 2^m = number of local history branches
   input logic             reset,
   input logic             StallF, StallD, StallE, StallM, StallW,
   input logic             FlushD, FlushE, FlushM, FlushW,
-  output logic [1:0]      BPDirPredF, 
+  output logic [1:0]      BPDirPredD, 
   output logic            BPDirPredWrongE,
   // update
   input logic [`XLEN-1:0] PCNextF, PCM,
@@ -43,10 +43,11 @@ module localaheadbp #(parameter m = 6, // 2^m = number of local history branches
 );
 
   logic [k-1:0]           IndexNextF, IndexM;
-  logic [1:0]             BPDirPredD, BPDirPredE;
+  //logic [1:0]             BPDirPredD, BPDirPredE;
+  logic [1:0]             BPDirPredE;
   logic [1:0]             NewBPDirPredE, NewBPDirPredM;
 
-  logic [k-1:0]           LHRF, LHRD, LHRE, LHRM, LHRNextF;
+  logic [k-1:0]           LHRF, LHRD, LHRE, LHRM, LHRW, LHRNextF;
   logic [k-1:0]           LHRNextW;
   logic                   PCSrcM;
   logic [2**m-1:0][k-1:0] LHRArray;
@@ -61,14 +62,14 @@ module localaheadbp #(parameter m = 6, // 2^m = number of local history branches
   
   ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallW & ~FlushW),
-    .ra1(LHRNextF),
-    .rd1(BPDirPredF),
+    .ra1(LHRF),
+    .rd1(BPDirPredD),
     .wa2(IndexM),
     .wd2(NewBPDirPredM),
     .we2(BranchM),
     .bwe2(1'b1));
 
-  flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, BPDirPredF, BPDirPredD);
+  //flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, BPDirPredF, BPDirPredD);
   flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, BPDirPredD, BPDirPredE);
 
   satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredE), .NewState(NewBPDirPredE));
@@ -93,7 +94,7 @@ module localaheadbp #(parameter m = 6, // 2^m = number of local history branches
   ram2p1r1wbe #(2**m, k) BHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallW & ~FlushW),
     .ra1(IndexLHRNextF),
-    .rd1(LHRNextF),
+    .rd1(LHRF),
     .wa2(IndexLHRM),
     .wd2(LHRNextW),
     .we2(BranchM),
@@ -101,10 +102,12 @@ module localaheadbp #(parameter m = 6, // 2^m = number of local history branches
 
   flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
     
-  flopenrc #(k) LHRFReg(clk, reset, FlushD, ~StallF, LHRNextF, LHRF);
+  //flopenrc #(k) LHRFReg(clk, reset, FlushD, ~StallF, LHRNextF, LHRF);
+  //assign LHRF = LHRNextF;
   flopenrc #(k) LHRDReg(clk, reset, FlushD, ~StallD, LHRF, LHRD);
   flopenrc #(k) LHREReg(clk, reset, FlushE, ~StallE, LHRD, LHRE);
   flopenrc #(k) LHRMReg(clk, reset, FlushM, ~StallM, LHRE, LHRM);
+  flopenrc #(k) LHRWReg(clk, reset, FlushW, ~StallW, LHRNextW, LHRW);
 
   flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
 

From 8235042ba2c8595326f790a39951b2a20e054006 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Thu, 4 May 2023 14:11:34 -0500
Subject: [PATCH 09/13] Maybe I finally have the ahead pipelined local history
 predictor working.

---
 src/ifu/bpred/bpred.sv        |  2 +-
 src/ifu/bpred/localaheadbp.sv | 16 ++++++++--------
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index f7cec5be7..cb7dc7fbd 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -135,7 +135,7 @@ module bpred (
   end else if (`BPRED_TYPE == "BP_LOCAL_AHEAD") begin:Predictor
     localaheadbp #(`BPRED_NUM_LHR, `BPRED_SIZE) DirPredictor(.clk, .reset, 
       .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-      .PCNextF, .PCM, .BPDirPredD(BPDirPredF), .BPDirPredWrongE,
+      .PCNextF, .PCM, .BPDirPredF(BPDirPredF), .BPDirPredWrongE,
       .BranchE, .BranchM, .PCSrcE);
   end 
 
diff --git a/src/ifu/bpred/localaheadbp.sv b/src/ifu/bpred/localaheadbp.sv
index e6577770b..80b1c12d1 100644
--- a/src/ifu/bpred/localaheadbp.sv
+++ b/src/ifu/bpred/localaheadbp.sv
@@ -35,7 +35,7 @@ module localaheadbp #(parameter m = 6, // 2^m = number of local history branches
   input logic             reset,
   input logic             StallF, StallD, StallE, StallM, StallW,
   input logic             FlushD, FlushE, FlushM, FlushW,
-  output logic [1:0]      BPDirPredD, 
+  output logic [1:0]      BPDirPredF, 
   output logic            BPDirPredWrongE,
   // update
   input logic [`XLEN-1:0] PCNextF, PCM,
@@ -43,8 +43,8 @@ module localaheadbp #(parameter m = 6, // 2^m = number of local history branches
 );
 
   logic [k-1:0]           IndexNextF, IndexM;
-  //logic [1:0]             BPDirPredD, BPDirPredE;
-  logic [1:0]             BPDirPredE;
+  logic [1:0]             BPDirPredD, BPDirPredE;
+  //logic [1:0]             BPDirPredE;
   logic [1:0]             NewBPDirPredE, NewBPDirPredM;
 
   logic [k-1:0]           LHRF, LHRD, LHRE, LHRM, LHRW, LHRNextF;
@@ -58,18 +58,18 @@ module localaheadbp #(parameter m = 6, // 2^m = number of local history branches
   logic                    UpdateM;
 
   //assign IndexNextF = LHR;
-  assign IndexM = LHRM;
+  assign IndexM = LHRW;
   
   ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallW & ~FlushW),
     .ra1(LHRF),
-    .rd1(BPDirPredD),
+    .rd1(BPDirPredF),
     .wa2(IndexM),
     .wd2(NewBPDirPredM),
     .we2(BranchM),
     .bwe2(1'b1));
 
-  //flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, BPDirPredF, BPDirPredD);
+  flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, BPDirPredF, BPDirPredD);
   flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, BPDirPredD, BPDirPredE);
 
   satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredE), .NewState(NewBPDirPredE));
@@ -83,7 +83,7 @@ module localaheadbp #(parameter m = 6, // 2^m = number of local history branches
   // GHR is both read and update in M.  GHR is still pipelined so that the PHT is updated with the correct
   // GHR.  Local history in contrast must pipeline the specific history register read during F and then update
   // that same one in M.  This implementation does not forward if a branch matches in the D, E, or M stages.
-  assign LHRNextW = BranchM ? {PCSrcM, LHRM[k-1:1]} : LHRM;
+  assign LHRNextW = BranchM ? {PCSrcM, LHRW[k-1:1]} : LHRW;
 
   // this is local history
   //genvar      index;
@@ -107,7 +107,7 @@ module localaheadbp #(parameter m = 6, // 2^m = number of local history branches
   flopenrc #(k) LHRDReg(clk, reset, FlushD, ~StallD, LHRF, LHRD);
   flopenrc #(k) LHREReg(clk, reset, FlushE, ~StallE, LHRD, LHRE);
   flopenrc #(k) LHRMReg(clk, reset, FlushM, ~StallM, LHRE, LHRM);
-  flopenrc #(k) LHRWReg(clk, reset, FlushW, ~StallW, LHRNextW, LHRW);
+  flopenrc #(k) LHRWReg(clk, reset, FlushW, ~StallW, LHRM, LHRW);
 
   flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
 

From ee1e380fad52a28ab9ff7c64e8466a743e39816f Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Thu, 4 May 2023 16:17:31 -0500
Subject: [PATCH 10/13] Almost working ahead pipelined local history predictor.

---
 src/ifu/bpred/bpred.sv        |  2 +-
 src/ifu/bpred/localaheadbp.sv | 23 +++++++++++++----------
 2 files changed, 14 insertions(+), 11 deletions(-)

diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index cb7dc7fbd..f7cec5be7 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -135,7 +135,7 @@ module bpred (
   end else if (`BPRED_TYPE == "BP_LOCAL_AHEAD") begin:Predictor
     localaheadbp #(`BPRED_NUM_LHR, `BPRED_SIZE) DirPredictor(.clk, .reset, 
       .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-      .PCNextF, .PCM, .BPDirPredF(BPDirPredF), .BPDirPredWrongE,
+      .PCNextF, .PCM, .BPDirPredD(BPDirPredF), .BPDirPredWrongE,
       .BranchE, .BranchM, .PCSrcE);
   end 
 
diff --git a/src/ifu/bpred/localaheadbp.sv b/src/ifu/bpred/localaheadbp.sv
index 80b1c12d1..617a5fca1 100644
--- a/src/ifu/bpred/localaheadbp.sv
+++ b/src/ifu/bpred/localaheadbp.sv
@@ -35,7 +35,7 @@ module localaheadbp #(parameter m = 6, // 2^m = number of local history branches
   input logic             reset,
   input logic             StallF, StallD, StallE, StallM, StallW,
   input logic             FlushD, FlushE, FlushM, FlushW,
-  output logic [1:0]      BPDirPredF, 
+  output logic [1:0]      BPDirPredD, 
   output logic            BPDirPredWrongE,
   // update
   input logic [`XLEN-1:0] PCNextF, PCM,
@@ -43,9 +43,10 @@ module localaheadbp #(parameter m = 6, // 2^m = number of local history branches
 );
 
   logic [k-1:0]           IndexNextF, IndexM;
-  logic [1:0]             BPDirPredD, BPDirPredE;
-  //logic [1:0]             BPDirPredE;
-  logic [1:0]             NewBPDirPredE, NewBPDirPredM;
+  //logic [1:0]             BPDirPredD, BPDirPredE;
+  logic [1:0]             BPDirPredE;
+  logic [1:0]             BPDirPredM;
+  logic [1:0]             NewBPDirPredE, NewBPDirPredM, NewBPDirPredW;
 
   logic [k-1:0]           LHRF, LHRD, LHRE, LHRM, LHRW, LHRNextF;
   logic [k-1:0]           LHRNextW;
@@ -63,19 +64,21 @@ module localaheadbp #(parameter m = 6, // 2^m = number of local history branches
   ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallW & ~FlushW),
     .ra1(LHRF),
-    .rd1(BPDirPredF),
+    .rd1(BPDirPredD),
     .wa2(IndexM),
-    .wd2(NewBPDirPredM),
+    .wd2(NewBPDirPredW),
     .we2(BranchM),
     .bwe2(1'b1));
 
-  flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, BPDirPredF, BPDirPredD);
+  //flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, BPDirPredF, BPDirPredD);
   flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, BPDirPredD, BPDirPredE);
+  flopenrc #(2) PredictionRegM(clk, reset,  FlushM, ~StallM, BPDirPredE, BPDirPredM);
 
-  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredE), .NewState(NewBPDirPredE));
-  flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM);
+  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredM), .NewState(NewBPDirPredM));
+  //flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM);
+  flopenrc #(2) NewPredictionRegW(clk, reset,  FlushW, ~StallW, NewBPDirPredM, NewBPDirPredW);
 
-  assign BPDirPredWrongE = PCSrcE != BPDirPredE[1] & BranchE;
+  assign BPDirPredWrongE = PCSrcE != BPDirPredM[1] & BranchE;
 
   // This is the main difference between global and local history basic implementations. In global, 
   // the ghr wraps back into itself directly without

From 42517bae6f1a25df142b2295c7dc4407d6615d07 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Thu, 4 May 2023 16:54:41 -0500
Subject: [PATCH 11/13] Fixed bug in local history predictor.

---
 src/ifu/bpred/localaheadbp.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/ifu/bpred/localaheadbp.sv b/src/ifu/bpred/localaheadbp.sv
index 617a5fca1..67f8df8dd 100644
--- a/src/ifu/bpred/localaheadbp.sv
+++ b/src/ifu/bpred/localaheadbp.sv
@@ -62,7 +62,7 @@ module localaheadbp #(parameter m = 6, // 2^m = number of local history branches
   assign IndexM = LHRW;
   
   ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
-    .ce1(~StallF), .ce2(~StallW & ~FlushW),
+    .ce1(~StallD), .ce2(~StallW & ~FlushW),
     .ra1(LHRF),
     .rd1(BPDirPredD),
     .wa2(IndexM),

From 3a98fb8680a694493bb3cbc3edc64a7c70b81fae Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Fri, 5 May 2023 15:23:45 -0500
Subject: [PATCH 12/13] Baseline localhistory with speculative repair built.

---
 src/ifu/bpred/bpred.sv         |   5 ++
 src/ifu/bpred/localrepairbp.sv | 137 +++++++++++++++++++++++++++++++++
 testbench/testbench.sv         |   2 +-
 3 files changed, 143 insertions(+), 1 deletion(-)
 create mode 100644 src/ifu/bpred/localrepairbp.sv

diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
index f7cec5be7..50415d449 100644
--- a/src/ifu/bpred/bpred.sv
+++ b/src/ifu/bpred/bpred.sv
@@ -137,6 +137,11 @@ module bpred (
       .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCM, .BPDirPredD(BPDirPredF), .BPDirPredWrongE,
       .BranchE, .BranchM, .PCSrcE);
+  end else if (`BPRED_TYPE == "BP_LOCAL_REPAIR") begin:Predictor
+    localreapirbp #(`BPRED_NUM_LHR, `BPRED_SIZE) DirPredictor(.clk, .reset, 
+      .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
+      .PCNextF, .PCE, .PCM, .BPDirPredD(BPDirPredF), .BPDirPredWrongE,
+      .BranchD, .BranchE, .BranchM, .PCSrcE);
   end 
 
   // Part 2 Branch target address prediction
diff --git a/src/ifu/bpred/localrepairbp.sv b/src/ifu/bpred/localrepairbp.sv
new file mode 100644
index 000000000..c3d4fc404
--- /dev/null
+++ b/src/ifu/bpred/localrepairbp.sv
@@ -0,0 +1,137 @@
+///////////////////////////////////////////
+// gsharebasic.sv
+//
+// Written: Ross Thompson
+// Email: ross1728@gmail.com
+// Created: 16 March 2021
+// Adapted from ssanghai@hmc.edu (Shreya Sanghai) global history predictor implementation.
+// Modified: 20 February 2023 
+//
+// Purpose: Global History Branch predictor with parameterized global history register
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module localreapirbp #(parameter m = 6, // 2^m = number of local history branches 
+                      parameter k = 10) ( // number of past branches stored
+  input logic             clk,
+  input logic             reset,
+  input logic             StallF, StallD, StallE, StallM, StallW,
+  input logic             FlushD, FlushE, FlushM, FlushW,
+  output logic [1:0]      BPDirPredD, 
+  output logic            BPDirPredWrongE,
+  // update
+  input logic [`XLEN-1:0] PCNextF, PCE, PCM,
+  input logic             BranchD, BranchE, BranchM, PCSrcE
+);
+
+  //logic [1:0]             BPDirPredD, BPDirPredE;
+  logic [1:0]             BPDirPredE;
+  logic [1:0]             BPDirPredM;
+  logic [1:0]             NewBPDirPredE, NewBPDirPredM, NewBPDirPredW;
+
+  logic [k-1:0]           LHRF, LHRD, LHRE, LHRM, LHRW, LHRNextF;
+  logic [k-1:0]           LHRNextW;
+  logic                   PCSrcM;
+  logic [2**m-1:0][k-1:0] LHRArray;
+  logic [m-1:0]           IndexLHRNextF, IndexLHRM;
+  logic [`XLEN-1:0]       PCW;
+
+  logic [k-1:0]           LHRCommittedF, LHRSpeculativeF;
+  logic [m-1:0]           IndexLHRD;
+  logic [k-1:0]           LHRNextE;
+  logic                   SpeculativeFlushedF;
+  
+  
+  ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
+    .ce1(~StallD), .ce2(~StallW & ~FlushW),
+    .ra1(LHRF),
+    .rd1(BPDirPredD),
+    .wa2(LHRW),
+    .wd2(NewBPDirPredW),
+    .we2(BranchM),
+    .bwe2(1'b1));
+
+  //flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, BPDirPredF, BPDirPredD);
+  flopenrc #(2) PredictionRegE(clk, reset,  FlushE, ~StallE, BPDirPredD, BPDirPredE);
+  flopenrc #(2) PredictionRegM(clk, reset,  FlushM, ~StallM, BPDirPredE, BPDirPredM);
+
+  satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredM), .NewState(NewBPDirPredM));
+  //flopenrc #(2) NewPredictionRegM(clk, reset,  FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM);
+  flopenrc #(2) NewPredictionRegW(clk, reset,  FlushW, ~StallW, NewBPDirPredM, NewBPDirPredW);
+
+  assign BPDirPredWrongE = PCSrcE != BPDirPredM[1] & BranchE;
+
+  // This is the main difference between global and local history basic implementations. In global, 
+  // the ghr wraps back into itself directly without
+  // being pipelined.  I.E. GHR is not read in F and then pipelined to M where it is updated.  Instead
+  // GHR is both read and update in M.  GHR is still pipelined so that the PHT is updated with the correct
+  // GHR.  Local history in contrast must pipeline the specific history register read during F and then update
+  // that same one in M.  This implementation does not forward if a branch matches in the D, E, or M stages.
+  assign LHRNextW = BranchM ? {PCSrcM, LHRW[k-1:1]} : LHRW;
+
+  // this is local history
+  assign IndexLHRM = {PCW[m+1] ^ PCW[1], PCW[m:2]};
+  assign IndexLHRNextF = {PCNextF[m+1] ^ PCNextF[1], PCNextF[m:2]};
+
+  ram2p1r1wbe #(2**m, k) BHT(.clk(clk),
+    .ce1(~StallF), .ce2(~StallW & ~FlushW),
+    .ra1(IndexLHRNextF),
+    .rd1(LHRCommittedF),
+    .wa2(IndexLHRM),
+    .wd2(LHRNextW),
+    .we2(BranchM),
+    .bwe2('1));
+
+  assign IndexLHRD = {PCE[m+1] ^ PCE[1], PCE[m:2]};
+  assign LHRNextE = BranchD ? {BPDirPredD[1], LHRE[k-1:1]} : LHRE;
+  // *** replace with a small CAM
+  ram2p1r1wbe #(2**m, k) SHB(.clk(clk),
+    .ce1(~StallF), .ce2(~StallE & ~FlushE),
+    .ra1(IndexLHRNextF),
+    .rd1(LHRSpeculativeF),
+    .wa2(IndexLHRD),
+    .wd2(LHRNextE),
+    .we2(BranchD),
+    .bwe2('1));
+  // **** replace with small CAM
+  logic [2**m-1:0]        FlushedBits;
+  always_ff @(posedge clk) begin // Valid bit array,
+    SpeculativeFlushedF <= #1 FlushedBits[IndexLHRNextF];
+    if (reset | FlushD) FlushedBits        <= #1 '1;
+    if(BranchD & ~StallE & ~FlushE) begin
+      FlushedBits[IndexLHRD] <= #1 '0;
+    end
+  end
+
+  mux2 #(k) LHRMux(LHRSpeculativeF, LHRCommittedF, SpeculativeFlushedF, LHRF);
+
+  flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
+    
+  //flopenrc #(k) LHRFReg(clk, reset, FlushD, ~StallF, LHRNextF, LHRF);
+  //assign LHRF = LHRNextF;
+  flopenrc #(k) LHRDReg(clk, reset, FlushD, ~StallD, LHRF, LHRD);
+  flopenrc #(k) LHREReg(clk, reset, FlushE, ~StallE, LHRD, LHRE);
+  flopenrc #(k) LHRMReg(clk, reset, FlushM, ~StallM, LHRE, LHRM);
+  flopenrc #(k) LHRWReg(clk, reset, FlushW, ~StallW, LHRM, LHRW);
+
+  flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
+
+endmodule
diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index 0112c24bd..441e6f0ea 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -537,7 +537,7 @@ module testbench;
     integer adrindex;
 
     // local history only
-    if (`BPRED_TYPE == "BP_LOCAL_AHEAD") begin
+    if (`BPRED_TYPE == "BP_LOCAL_AHEAD" | `BPRED_TYPE == "BP_LOCAL_REPAIR") begin
       always @(*) begin
         if(reset) begin
           for(adrindex = 0; adrindex < 2**`BPRED_NUM_LHR; adrindex++) begin

From d545a2ec74120b0ca591c2bf8f70caf02e558ad2 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Thu, 11 May 2023 14:56:26 -0500
Subject: [PATCH 13/13] Partially working local history repair.

---
 bin/parseHPMC.py               |   4 +-
 config/rv32gc/wally-config.vh  |   2 +-
 config/rv64gc/wally-config.vh  |   6 +-
 sim/bpred-sim.py               |   2 +-
 sim/wave.do                    | 237 ++++++++++-----------------------
 src/ifu/bpred/localrepairbp.sv |   1 +
 6 files changed, 79 insertions(+), 173 deletions(-)

diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py
index 7d65f120c..9e08f2c7a 100755
--- a/bin/parseHPMC.py
+++ b/bin/parseHPMC.py
@@ -279,8 +279,8 @@ if(sys.argv[1] == '-b'):
                     dct[PredType] = (currSize, currPercent)
         print(dct)
         fig, axes = plt.subplots()
-        marker={'twobit' : '^', 'gshare' : 'o', 'global' : 's', 'gshareBasic' : '*', 'globalBasic' : 'x', 'btb': 'x', 'twobitCModel' : 'x', 'gshareCModel' : '*', 'tenlocal' : '.', 'eightlocal' : ',', 'fourlocal' : 'x'}
-        colors={'twobit' : 'black', 'gshare' : 'blue', 'global' : 'dodgerblue', 'gshareBasic' : 'turquoise', 'globalBasic' : 'lightsteelblue', 'btb' : 'blue', 'twobitCModel' : 'gray', 'gshareCModel' : 'dodgerblue', 'tenlocal' : 'lightblue', 'eightlocal' : 'lightblue', 'fourlocal' : 'lightblue'}
+        marker={'twobit' : '^', 'gshare' : 'o', 'global' : 's', 'gshareBasic' : '*', 'globalBasic' : 'x', 'btb': 'x', 'twobitCModel' : 'x', 'gshareCModel' : '*', 'tenlocal' : '.', 'eightlocal' : ',', 'fourlocal' : 'x', 'tenlocalahead' : '.', 'eightlocalahead' : ',', 'fourlocalahead' : 'x', 'tenlocalrepair' : 'x'}
+        colors={'twobit' : 'black', 'gshare' : 'blue', 'global' : 'dodgerblue', 'gshareBasic' : 'turquoise', 'globalBasic' : 'lightsteelblue', 'btb' : 'blue', 'twobitCModel' : 'gray', 'gshareCModel' : 'dodgerblue', 'tenlocal' : 'lightblue', 'eightlocal' : 'lightblue', 'fourlocal' : 'lightblue', 'tenlocalahead' : 'lightblue', 'eightlocalahead' : 'lightblue', 'fourlocalahead' : 'lightblue', 'tenlocalrepair' : 'lightblue'}
         for cat in dct:
             (x, y) = dct[cat]
             x=[int(2**int(v)) for v in x]
diff --git a/config/rv32gc/wally-config.vh b/config/rv32gc/wally-config.vh
index d6f75ba08..896e10bab 100644
--- a/config/rv32gc/wally-config.vh
+++ b/config/rv32gc/wally-config.vh
@@ -133,7 +133,7 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_SUPPORTED 1
-`define BPRED_TYPE "BP_LOCAL_BASIC" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
+`define BPRED_TYPE "BP_LOCAL_REPAIR" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 `define BPRED_SIZE 16
 `define BPRED_NUM_LHR 8
 `define BTB_SIZE 10
diff --git a/config/rv64gc/wally-config.vh b/config/rv64gc/wally-config.vh
index 69f4cdcfb..15edef590 100644
--- a/config/rv64gc/wally-config.vh
+++ b/config/rv64gc/wally-config.vh
@@ -137,9 +137,9 @@
 
 `define BPRED_SUPPORTED 1
 //`define BPRED_TYPE "BP_GLOBAL_BASIC" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
-`define BPRED_TYPE "BP_LOCAL_BASIC" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
-`define BPRED_SIZE 10
-`define BPRED_NUM_LHR 6
+`define BPRED_TYPE "BP_LOCAL_REPAIR" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
+`define BPRED_SIZE 6
+`define BPRED_NUM_LHR 4
 `define BTB_SIZE 10
 
 `define SVADU_SUPPORTED 1
diff --git a/sim/bpred-sim.py b/sim/bpred-sim.py
index 256658a6c..4f1757cb8 100755
--- a/sim/bpred-sim.py
+++ b/sim/bpred-sim.py
@@ -61,7 +61,7 @@ configs = [
 
 bpdSize = [6, 8, 10, 12, 14, 16]
 LHRSize = [4, 8, 10]
-bpdType = ['local_basic']
+bpdType = ['local_repair']
 for CurrBPType in bpdType:
     for CurrBPSize in bpdSize:
         for CurrLHRSize in  LHRSize:
diff --git a/sim/wave.do b/sim/wave.do
index 5aa5deb0a..fdf958bd6 100644
--- a/sim/wave.do
+++ b/sim/wave.do
@@ -6,12 +6,6 @@ add wave -noupdate /testbench/reset
 add wave -noupdate /testbench/reset_ext
 add wave -noupdate /testbench/memfilename
 add wave -noupdate /testbench/dut/core/SATP_REGW
-add wave -noupdate /testbench/FunctionName/FunctionName/PCD
-add wave -noupdate /testbench/FunctionName/FunctionName/PCE
-add wave -noupdate /testbench/FunctionName/FunctionName/PCF
-add wave -noupdate /testbench/FunctionName/FunctionName/PCM
-add wave -noupdate /testbench/FunctionName/FunctionName/PCM_temp
-add wave -noupdate /testbench/FunctionName/FunctionName/PCMOld
 add wave -noupdate /testbench/dut/core/InstrValidM
 add wave -noupdate /testbench/FunctionName/FunctionName/FunctionAddr
 add wave -noupdate /testbench/FunctionName/FunctionName/ProgramAddrIndex
@@ -38,15 +32,16 @@ add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv
 add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
 add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
 add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallF
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallD
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM
+add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
+add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
+add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM
+add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW
+add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallF
+add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallD
+add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallE
+add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallM
+add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallW
 add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
 add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
 add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
@@ -66,10 +61,10 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD
 add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD
 add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D
 add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D
-add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE
-add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE
-add wave -noupdate -group {Execution Stage} /testbench/InstrEName
-add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
+add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/PCE
+add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE
+add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
+add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
 add wave -noupdate -expand -group {Memory Stage} /testbench/FunctionName/FunctionName/FunctionName
 add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrValidM
 add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
@@ -99,9 +94,9 @@ add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
 add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW
 add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW
 add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS
-add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check}
-add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
-add wave -noupdate -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
+add wave -noupdate -expand -group Bpred -expand -group {branch update selection inputs} -divider {class check}
+add wave -noupdate -expand -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
+add wave -noupdate -expand -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
 add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
 add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE
 add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
@@ -120,8 +115,6 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core
 add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultW
 add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/A
 add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/B
-add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/Result
-add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/ALUControl
 add wave -noupdate -group alu -divider internals
 add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1D
 add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2D
@@ -152,23 +145,24 @@ add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core
 add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUDisable
 add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSelect
 add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUSelect
+add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/ebufsmarb/CurrState
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
-add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHTRANS
-add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHADDR
-add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHBURST
-add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHREADY
-add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/HRDATA
-add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUReq
-add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHTRANS
-add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHSIZE
-add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHBURST
-add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHADDR
-add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/HRDATA
-add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWRITE
-add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWSTRB
-add wave -noupdate -group AHB -expand -group LSU /testbench/dut/core/ebu/ebu/LSUHWDATA
-add wave -noupdate -group AHB -expand -group LSU -color Pink /testbench/dut/core/lsu/LSUHREADY
+add wave -noupdate -group AHB -group IFU /testbench/dut/core/ebu/ebu/IFUHTRANS
+add wave -noupdate -group AHB -group IFU /testbench/dut/core/ebu/ebu/IFUHADDR
+add wave -noupdate -group AHB -group IFU /testbench/dut/core/ebu/ebu/IFUHBURST
+add wave -noupdate -group AHB -group IFU /testbench/dut/core/ebu/ebu/IFUHREADY
+add wave -noupdate -group AHB -group IFU /testbench/dut/core/HRDATA
+add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUReq
+add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUHTRANS
+add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUHSIZE
+add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUHBURST
+add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUHADDR
+add wave -noupdate -group AHB -group LSU /testbench/dut/core/HRDATA
+add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUHWRITE
+add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUHWSTRB
+add wave -noupdate -group AHB -group LSU /testbench/dut/core/ebu/ebu/LSUHWDATA
+add wave -noupdate -group AHB -group LSU -color Pink /testbench/dut/core/lsu/LSUHREADY
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HCLK
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESETn
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HREADY
@@ -210,12 +204,10 @@ add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/d
 add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
 add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrE
 add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrM
-add wave -noupdate -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
 add wave -noupdate -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
 add wave -noupdate -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
 add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
 add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
-add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CAdr
 add wave -noupdate -group lsu -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
 add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
 add wave -noupdate -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
@@ -235,7 +227,6 @@ add wave -noupdate -group lsu -group dcache -group flush /testbench/dut/core/lsu
 add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
 add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
 add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr
-add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
 add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
 add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
 add wave -noupdate -group lsu -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
@@ -252,60 +243,25 @@ add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM[62]}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/we}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
-add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
@@ -323,7 +279,6 @@ add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way3
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
 add wave -noupdate -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
-add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr
 add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
 add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
 add wave -noupdate -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
@@ -362,22 +317,27 @@ add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMASt
 add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
 add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
 add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
-add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWalk
-add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/WalkerState
-add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWAdr
-add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PTE
-add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/NextPageType
-add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PageType
-add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ValidNonLeafPTE
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk
+add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType
+add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE
 add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
 add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
-add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ITLBWriteF
-add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWriteM
-add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSULoadAccessFaultM
-add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSUStoreAmoAccessFaultM
-add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWInstrAccessFaultM
-add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LoadAccessFaultM
-add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/StoreAmoAccessFaultM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/DCacheStallM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM
+add wave -noupdate -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault
 add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr
 add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr
 add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/MExtInt
@@ -396,9 +356,6 @@ add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/un
 add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/max_priority_with_irqs
 add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/irqs_at_max_priority
 add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/threshMask
-add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsIn
-add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsOut
-add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsEn
 add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIntr
 add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PSEL
 add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/PADDR
@@ -462,7 +419,6 @@ add wave -noupdate -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF
 add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUStallF
 add wave -noupdate -group ifu -group Spill /testbench/dut/core/ifu/Spill/spill/CurrState
 add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/SpillF
-add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallD
 add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissF
 add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF
 add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE
@@ -483,54 +439,6 @@ add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and
 add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr
 add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
 add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/RAM}
-add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/bwe}
-add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/dout}
-add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/RAM}
 add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
 add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF
 add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/VAdr
@@ -556,10 +464,10 @@ add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/c
 add wave -noupdate -expand -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
 add wave -noupdate -expand -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
 add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label Branch -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BP Dir Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
 add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {Jump (Not Return)} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]}
 add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label Return -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]}
 add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BP Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]}
-add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BP Dir Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
 add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BTA Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
 add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {RAS Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
 add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
@@ -609,34 +517,31 @@ add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELNoneD
 add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELPLICD
 add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HRDATA
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/rd
-add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF
 add wave -noupdate -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE
 add wave -noupdate -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
 add wave -noupdate -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushE
-add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF
-add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD
-add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE
 add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD
-add wave -noupdate -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF
-add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE
 add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM
 add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF
 add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF
-add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/DCacheAccess
-add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/ICacheMiss
-add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/ICacheAccess
-add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/DCacheMiss
-add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/InstrValidNotFlushedM
-add wave -noupdate /testbench/clk
-add wave -noupdate /testbench/HPMCSample/InitialHPMCOUNTERH
-add wave -noupdate /testbench/HPMCSample/EndSample
-add wave -noupdate /testbench/HPMCSample/StartSample
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/LHRNextF
+add wave -noupdate /testbench/dut/core/ifu/PCF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/LHRF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/LHRD
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/LHRE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/LHRM
+add wave -noupdate -label BHT /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BHT/mem
+add wave -noupdate /testbench/reset
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPDirPredD
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCW
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchM
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/LHRNextW
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewBPDirPredM
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/LHRF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/LHRCommittedF
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {391801 ns} 1} {{Cursor 4} {23 ns} 0} {{Cursor 5} {394987 ns} 1}
-quietly wave cursor active 4
+WaveRestoreCursors {{Cursor 4} {12208 ns} 1} {{Cursor 4} {30 ns} 0}
+quietly wave cursor active 2
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 194
 configure wave -justifyvalue left
@@ -651,4 +556,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {0 ns} {52 ns}
+WaveRestoreZoom {0 ns} {176 ns}
diff --git a/src/ifu/bpred/localrepairbp.sv b/src/ifu/bpred/localrepairbp.sv
index c3d4fc404..485214302 100644
--- a/src/ifu/bpred/localrepairbp.sv
+++ b/src/ifu/bpred/localrepairbp.sv
@@ -121,6 +121,7 @@ module localreapirbp #(parameter m = 6, // 2^m = number of local history branche
     end
   end
 
+  //assign SpeculativeFlushedF = '1;
   mux2 #(k) LHRMux(LHRSpeculativeF, LHRCommittedF, SpeculativeFlushedF, LHRF);
 
   flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);