diff --git a/addins/cvw-arch-verif b/addins/cvw-arch-verif index bbcba7864..189974e49 160000 --- a/addins/cvw-arch-verif +++ b/addins/cvw-arch-verif @@ -1 +1 @@ -Subproject commit bbcba78647080dee82e96bc1b8ff9cd9a3cf7fa1 +Subproject commit 189974e497d7b8d2c08bb1d151b1ccdeaf3a64c9 diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index ce04b4930..7152865ac 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit ce04b4930545ae4c81e2f3b6f6935e2aac08679e +Subproject commit 7152865aca51062c87ff2cbb014e199a24bdc874 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-spi-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-spi-01.reference_output index 425866ac2..027e02f54 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-spi-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-spi-01.reference_output @@ -238,46 +238,6 @@ 0000001F -00000062 # hardware interlock - -00000026 - -000000D2 - -0000002D - -00000048 - -00000037 - -00000026 - -00000015 - -00000084 - -00000073 - -00000062 - -00000051 - -00000046 - -00000035 - -00000024 - -00000013 - -00000064 - -00000053 - -00000042 - -00000031 - 00000001 #watermark interrupts 00000000 #read mip diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-spi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-spi-01.S index 4048c4c4c..a004a5ea0 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-spi-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-spi-01.S @@ -547,101 +547,6 @@ test_cases: #.4byte 0x0, 0x00000000, spi_data_wait # wait for transmission to end #.4byte rx_data, 0x000000F0, read32_test # read rx_data -#=========== Test Hardware Interlock ================ - -# interlock in base case - -.4byte fmt, 0x00080000, write32_test # reset fmt register -.4byte rx_mark, 0x0000001, write32_test # preset rx watermark b/c of hardware interlock -.4byte tx_data, 0x00000062, write32_test # initiate transmission -.4byte sck_mode, 0x00000002, write32_test # flip polarity during transmission -.4byte tx_data, 0x00000026, write32_test # transmit second frame w/ control register updated -.4byte 0x0, 0x00000001, spi_data_wait -.4byte rx_data, 0x00000062, read32_test -.4byte rx_data, 0x00000026, read32_test # clear rx fifo -.4byte sck_mode, 0x00000000, write32_test # reset polarity - -# interlock in case where cs_mode is auto, but there is minimal intercs delay - -.4byte delay0, 0x00000001, write32_test # set sck-cs delay to 0, with sck.pha 0 there is 0 delay -.4byte tx_data, 0x000000D2, write32_test # initiate transmission -.4byte sck_mode, 0x00000002, write32_test # flip sck polarity -.4byte tx_data, 0x0000002D, write32_test # transmit second frame -.4byte 0x0, 0x00000001, spi_data_wait -.4byte rx_data, 0x000000D2, read32_test -.4byte rx_data, 0x0000002D, read32_test # clear rx fifo -.4byte sck_mode, 0x00000000, write32_test # reset polarity - -# interlock in case where cs_mode = hold, 0 intercs delay -.4byte delay0, 0x00010001, write32_test # reset delay0 -.4byte sck_mode, 0x00000000, write32_test # reset polarity -.4byte cs_mode, 0x00000002, write32_test # set cs_mode to hold -.4byte tx_data, 0x15263748, spi_burst_send # place 4 frames into tx fifo -.4byte sck_mode, 0x00000002, write32_test # flip polarity (should change 2 second frame) -.4byte 0x0, 0x00000001, spi_data_wait # wait for second transmission to end -.4byte rx_mark, 0x0000003, write32_test # preset rx watermark b/c of hardware interlock -.4byte sck_mode, 0x00000000, write32_test # flip polarity again -.4byte 0x0, 0x00000003, spi_data_wait # wait for final frame -.4byte rx_data, 0x00000048, read32_test -.4byte rx_data, 0x00000037, read32_test -.4byte rx_data, 0x00000026, read32_test -.4byte rx_data, 0x00000015, read32_test #clear rx fifo - -# interlock in case where cs_mode = hold, intercs delay - -.4byte sck_mode, 0x00000000, write32_test # reset polarity -.4byte delay1, 0x00010001, write32_test # set intercs delay to 1 -.4byte rx_mark, 0x0000001, write32_test # preset rx watermark b/c of hardware interlock -.4byte tx_data, 0x51627384, spi_burst_send # place 4 frames into tx fifo -.4byte sck_mode, 0x00000002, write32_test # flip polarity (should change 2 second frame) -.4byte 0x0, 0x00000001, spi_data_wait # wait for second transmission to end -.4byte rx_mark, 0x0000003, write32_test # preset rx watermark b/c of hardware interlock -.4byte sck_mode, 0x00000000, write32_test # flip polarity again -.4byte 0x0, 0x00000003, spi_data_wait # wait for final frame -.4byte rx_data, 0x00000084, read32_test -.4byte rx_data, 0x00000073, read32_test -.4byte rx_data, 0x00000062, read32_test -.4byte rx_data, 0x00000051, read32_test #clear rx fifo - -# repeat previous set of tests with cs_mode = off - -.4byte cs_mode, 0x00000003, write32_test # set cs_mode to hold -.4byte rx_mark, 0x0000001, write32_test # preset rx watermark b/c of hardware interlock -.4byte tx_data, 0x13243546, spi_burst_send # place 4 frames into tx fifo -.4byte sck_mode, 0x00000002, write32_test # flip polarity (should change 2 second frame) -.4byte 0x0, 0x00000001, spi_data_wait # wait for second transmission to end -.4byte rx_mark, 0x0000003, write32_test # preset rx watermark b/c of hardware interlock -.4byte sck_mode, 0x00000000, write32_test # flip polarity again -.4byte 0x0, 0x00000003, spi_data_wait # wait for final frame -.4byte rx_data, 0x00000046, read32_test -.4byte rx_data, 0x00000035, read32_test -.4byte rx_data, 0x00000024, read32_test -.4byte rx_data, 0x00000013, read32_test #clear rx fifo - -# interlock in case where cs_mode = hold, intercs delay - -.4byte sck_mode, 0x00000000, write32_test # reset polarity -.4byte delay1, 0x00000000, write32_test # set intercs delay to 0 -.4byte rx_mark, 0x0000001, write32_test # preset rx watermark b/c of hardware interlock -.4byte tx_data, 0x31425364, spi_burst_send # place 4 frames into tx fifo -.4byte sck_mode, 0x00000002, write32_test # flip polarity (should change 2 second frame) -.4byte 0x0, 0x00000001, spi_data_wait # wait for second transmission to end -.4byte rx_mark, 0x0000003, write32_test # preset rx watermark b/c of hardware interlock -.4byte sck_mode, 0x00000000, write32_test # flip polarity again -.4byte 0x0, 0x00000003, spi_data_wait # wait for final frame -.4byte rx_data, 0x00000064, read32_test -.4byte rx_data, 0x00000053, read32_test -.4byte rx_data, 0x00000042, read32_test -.4byte rx_data, 0x00000031, read32_test #clear rx fifo - - - - - - - - - # =========== Test watermark interrupts =========== diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-spi-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-spi-01.reference_output index 7520479ce..8d9ae8bbc 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-spi-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-spi-01.reference_output @@ -238,46 +238,6 @@ 00000000 0000001F 00000000 -00000062 # hardware interlock -00000000 -00000026 -00000000 -000000D2 -00000000 -0000002D -00000000 -00000048 -00000000 -00000037 -00000000 -00000026 -00000000 -00000015 -00000000 -00000084 -00000000 -00000073 -00000000 -00000062 -00000000 -00000051 -00000000 -00000046 -00000000 -00000035 -00000000 -00000024 -00000000 -00000013 -00000000 -00000064 -00000000 -00000053 -00000000 -00000042 -00000000 -00000031 -00000000 00000001 #watermark interrupts 00000000 00000000 #read mip diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-spi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-spi-01.S index 2a04f02f0..0f189b5e6 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-spi-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-spi-01.S @@ -551,94 +551,6 @@ test_cases: #.8byte 0x0, 0x00000000, spi_data_wait # wait for transmission to end #.8byte rx_data, 0x000000F0, read32_test # read rx_data -#=========== Test Hardware Interlock ================ - -# interlock in base case - -.8byte fmt, 0x00080000, write32_test # reset fmt register -.8byte rx_mark, 0x0000001, write32_test # preset rx watermark b/c of hardware interlock -.8byte tx_data, 0x00000062, write32_test # initiate transmission -.8byte sck_mode, 0x00000002, write32_test # flip polarity during transmission -.8byte tx_data, 0x00000026, write32_test # transmit second frame w/ control register updated -.8byte 0x0, 0x00000001, spi_data_wait -.8byte rx_data, 0x00000062, read32_test -.8byte rx_data, 0x00000026, read32_test # clear rx fifo -.8byte sck_mode, 0x00000000, write32_test # reset polarity - -# interlock in case where cs_mode is auto, but there is minimal intercs delay - -.8byte delay0, 0x00000001, write32_test # set sck-cs delay to 0, with sck.pha 0 there is 0 delay -.8byte tx_data, 0x000000D2, write32_test # initiate transmission -.8byte sck_mode, 0x00000002, write32_test # flip sck polarity -.8byte tx_data, 0x0000002D, write32_test # transmit second frame -.8byte 0x0, 0x00000001, spi_data_wait -.8byte rx_data, 0x000000D2, read32_test -.8byte rx_data, 0x0000002D, read32_test # clear rx fifo -.8byte sck_mode, 0x00000000, write32_test # reset polarity - -# interlock in case where cs_mode = hold, 0 intercs delay -.8byte delay0, 0x00010001, write32_test # reset delay0 -.8byte sck_mode, 0x00000000, write32_test # reset polarity -.8byte cs_mode, 0x00000002, write32_test # set cs_mode to hold -.8byte tx_data, 0x15263748, spi_burst_send # place 4 frames into tx fifo -.8byte sck_mode, 0x00000002, write32_test # flip polarity (should change 2 second frame) -.8byte 0x0, 0x00000001, spi_data_wait # wait for second transmission to end -.8byte rx_mark, 0x0000003, write32_test # preset rx watermark b/c of hardware interlock -.8byte sck_mode, 0x00000000, write32_test # flip polarity again -.8byte 0x0, 0x00000003, spi_data_wait # wait for final frame -.8byte rx_data, 0x00000048, read32_test -.8byte rx_data, 0x00000037, read32_test -.8byte rx_data, 0x00000026, read32_test -.8byte rx_data, 0x00000015, read32_test #clear rx fifo - -# interlock in case where cs_mode = hold, intercs delay - -.8byte sck_mode, 0x00000000, write32_test # reset polarity -.8byte delay1, 0x00010001, write32_test # set intercs delay to 1 -.8byte rx_mark, 0x0000001, write32_test # preset rx watermark b/c of hardware interlock -.8byte tx_data, 0x51627384, spi_burst_send # place 4 frames into tx fifo -.8byte sck_mode, 0x00000002, write32_test # flip polarity (should change 2 second frame) -.8byte 0x0, 0x00000001, spi_data_wait # wait for second transmission to end -.8byte rx_mark, 0x0000003, write32_test # preset rx watermark b/c of hardware interlock -.8byte sck_mode, 0x00000000, write32_test # flip polarity again -.8byte 0x0, 0x00000003, spi_data_wait # wait for final frame -.8byte rx_data, 0x00000084, read32_test -.8byte rx_data, 0x00000073, read32_test -.8byte rx_data, 0x00000062, read32_test -.8byte rx_data, 0x00000051, read32_test #clear rx fifo - -# repeat previous set of tests with cs_mode = off - -.8byte cs_mode, 0x00000003, write32_test # set cs_mode to hold -.8byte rx_mark, 0x0000001, write32_test # preset rx watermark b/c of hardware interlock -.8byte tx_data, 0x13243546, spi_burst_send # place 4 frames into tx fifo -.8byte sck_mode, 0x00000002, write32_test # flip polarity (should change 2 second frame) -.8byte 0x0, 0x00000001, spi_data_wait # wait for second transmission to end -.8byte rx_mark, 0x0000003, write32_test # preset rx watermark b/c of hardware interlock -.8byte sck_mode, 0x00000000, write32_test # flip polarity again -.8byte 0x0, 0x00000003, spi_data_wait # wait for final frame -.8byte rx_data, 0x00000046, read32_test -.8byte rx_data, 0x00000035, read32_test -.8byte rx_data, 0x00000024, read32_test -.8byte rx_data, 0x00000013, read32_test #clear rx fifo - -# interlock in case where cs_mode = hold, intercs delay - -.8byte sck_mode, 0x00000000, write32_test # reset polarity -.8byte delay1, 0x00000000, write32_test # set intercs delay to 0 -.8byte rx_mark, 0x0000001, write32_test # preset rx watermark b/c of hardware interlock -.8byte tx_data, 0x31425364, spi_burst_send # place 4 frames into tx fifo -.8byte sck_mode, 0x00000002, write32_test # flip polarity (should change 2 second frame) -.8byte 0x0, 0x00000001, spi_data_wait # wait for second transmission to end -.8byte rx_mark, 0x0000003, write32_test # preset rx watermark b/c of hardware interlock -.8byte sck_mode, 0x00000000, write32_test # flip polarity again -.8byte 0x0, 0x00000003, spi_data_wait # wait for final frame -.8byte rx_data, 0x00000064, read32_test -.8byte rx_data, 0x00000053, read32_test -.8byte rx_data, 0x00000042, read32_test -.8byte rx_data, 0x00000031, read32_test #clear rx fifo - -