diff --git a/tests/wally-riscv-arch-test/Makefile.include b/tests/wally-riscv-arch-test/Makefile.include
index 727aebde2..001fd1623 100644
--- a/tests/wally-riscv-arch-test/Makefile.include
+++ b/tests/wally-riscv-arch-test/Makefile.include
@@ -1,6 +1,5 @@
 # set TARGETDIR to point to the directory which contains a sub-folder in the same name as the target
-export TARGETDIR ?= /home/harris/riscv-wally/addins/riscv-isa-sim/arch_test_target
-#export TARGETDIR ?= ~/riscv-wally/addins/riscv-isa-sim/arch_test_target
+export TARGETDIR ?= ${RISCV}/riscv-isa-sim/arch_test_target
 
 export RISCV_PREFIX = riscv64-unknown-elf-
 
diff --git a/wally-pipelined/testbench/testbench.sv b/wally-pipelined/testbench/testbench.sv
index 68bd1e936..6134ab287 100644
--- a/wally-pipelined/testbench/testbench.sv
+++ b/wally-pipelined/testbench/testbench.sv
@@ -289,13 +289,14 @@ logic [3:0] dummy;
   // Termination condition
   // terminate on a specific ECALL after li x3,1 for old Imperas tests, 
   // or sw	gp,-56(t0) for new Imperas tests
+  // or sw gp, -56(t0) 
   // or on a jump to self infinite loop (6f) for RISC-V Arch tests
   assign DCacheFlushStart = dut.hart.priv.priv.EcallFaultM && 
 			    (dut.hart.ieu.dp.regf.rf[3] == 1 || 
 			     (dut.hart.ieu.dp.regf.we3 && 
 			      dut.hart.ieu.dp.regf.a3 == 3 && 
 			      dut.hart.ieu.dp.regf.wd3 == 1)) ||
-          (dut.hart.ifu.InstrM == 32'h6f || dut.hart.ifu.InstrM == 32'hfc32a423) && dut.hart.ieu.c.InstrValidM;
+          (dut.hart.ifu.InstrM == 32'h6f || dut.hart.ifu.InstrM == 32'hfc32a423 || dut.hart.ifu.InstrM == 32'hfc32a823) && dut.hart.ieu.c.InstrValidM;
   
   DCacheFlushFSM DCacheFlushFSM(.clk(clk),
 				.reset(reset),