diff --git a/bin/derivgen.pl b/bin/derivgen.pl index 21ffc7019..dbb856781 100755 --- a/bin/derivgen.pl +++ b/bin/derivgen.pl @@ -96,7 +96,7 @@ foreach my $key (@derivnames) { my @ent = @{$entry}; my $param = $ent[0]; my $value = $ent[1]; - if ($line =~ s/$param\s*=\s*.*;/$param = $value;/) { + if ($line =~ s/\b$param\s*=\s*.*;/$param = $value;/) { $hit{$param} = 1; # print("Hit: new line in $config for $param is $line"); } @@ -130,4 +130,4 @@ sub printref { print join('_', @{$entry}), ', '; } print("\n"); -} \ No newline at end of file +} diff --git a/bin/regression-wally b/bin/regression-wally index add2bd24a..0e641dceb 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -93,7 +93,7 @@ derivconfigtests = [ ["nodcache_rv64gc", ["ahb64"]], ["nocache_rv64gc", ["ahb64"]], -# Atomic variatnts +# Atomic variants ["zaamo_rv64gc", ["arch64i", "arch64a_amo"]], ["zalrsc_rv64gc", ["arch64i", "wally64a_lrsc"]], ["zaamo_rv32gc", ["arch32i", "arch32a_amo"]], @@ -122,6 +122,16 @@ derivconfigtests = [ ["zknd_rv64gc", ["arch64i", "arch64zknd"]], ["zknh_rv64gc", ["arch64i", "arch64zknh"]], +# No privilege modes variants + ["noS_rv32gc", ["arch32i", "arch32f", "arch32priv", "arch32c", "arch32m", "arch32a_amo", "arch32zifencei", "arch32zicond", + "arch32zba", "arch32zfaf", "arch32zfad", "wally32a_lrsc", "arch32zcb", "arch32zbkx", "arch32zknd"]], + ["noS_rv64gc", ["arch64i", "arch64f", "arch64priv", "arch64c", "arch64m", "arch64a_amo", "arch64zifencei", "arch64zicond", + "arch64zba", "arch64zfaf", "arch64zfad", "wally64a_lrsc", "arch64zcb", "arch64zbkx", "arch64zknd"]], + ["noU_rv32gc", ["arch32i", "arch32f", "arch32priv", "arch32c", "arch32m", "arch32a_amo", "arch32zifencei", "arch32zicond", + "arch32zba", "arch32zfaf", "arch32zfad", "wally32a_lrsc", "arch32zcb", "arch32zbkx", "arch32zknd"]], + ["noU_rv64gc", ["arch64i", "arch64f", "arch64priv", "arch64c", "arch64m", "arch64a_amo", "arch64zifencei", "arch64zicond", + "arch64zba", "arch64zfaf", "arch64zfad", "wally64a_lrsc", "arch64zcb", "arch64zbkx", "arch64zknd"]], + ### add misaligned tests # fp/int divider permutations diff --git a/bin/wally-tool-chain-install-redhat.sh b/bin/wally-tool-chain-install-redhat.sh index 547182f64..8ad49a57f 100755 --- a/bin/wally-tool-chain-install-redhat.sh +++ b/bin/wally-tool-chain-install-redhat.sh @@ -123,7 +123,7 @@ if [ "$FAMILY" = rhel ]; then # Packages are grouped by which tool requires them, split by line. # If mutltipole tools need a package, it is included in the first tool only # General/Wally specific, riscv-gnu-toolchain, qemu, spike, verilator - sudo dnf install -y git make cmake python3.12 python3-pip curl wget ftp tar pkgconfig dialog mutt ssmtp \ + sudo dnf install -y git make cmake python3.12 python3-pip curl wget ftp tar pkgconfig dialog mutt ssmtp gcc-gfortran boost-devel\ autoconf automake libmpc-devel mpfr-devel gmp-devel gawk bison flex texinfo gperf libtool patchutils bc gcc gcc-c++ zlib-devel expat-devel libslirp-devel \ glib2-devel libfdt-devel pixman-devel bzip2 ninja-build \ dtc boost-regex boost-system \ diff --git a/bin/wally-tool-chain-install-unified.sh b/bin/wally-tool-chain-install-unified.sh index 5815fea25..bbaa39a73 100755 --- a/bin/wally-tool-chain-install-unified.sh +++ b/bin/wally-tool-chain-install-unified.sh @@ -124,7 +124,7 @@ if [ "$FAMILY" = rhel ]; then # Packages are grouped by which tool requires them, split by line. # If mutltipole tools need a package, it is included in the first tool only # General/Wally specific, riscv-gnu-toolchain, qemu, spike, verilator - sudo dnf install -y git make cmake python3.12 python3-pip curl wget ftp tar pkgconfig dialog mutt ssmtp \ + sudo dnf install -y git make cmake python3.12 python3-pip curl wget ftp tar pkgconfig dialog mutt ssmtp gcc-gfortran \ autoconf automake libmpc-devel mpfr-devel gmp-devel gawk bison flex texinfo gperf libtool patchutils bc gcc gcc-c++ zlib-devel expat-devel libslirp-devel \ glib2-devel libfdt-devel pixman-devel bzip2 ninja-build \ dtc boost-regex boost-system \ @@ -145,7 +145,7 @@ elif [ "$FAMILY" = ubuntu ]; then # Packages are grouped by which tool requires them, split by line. # If mutltipole tools need a package, it is included in the first tool only # General/Wally specific, riscv-gnu-toolchain, qemu, spike, verilator, sail - sudo apt install -y git make cmake python3 python3-pip python3-venv curl wget ftp tar pkg-config dialog mutt ssmtp \ + sudo apt install -y git make cmake python3 python3-pip python3-venv curl wget ftp tar pkg-config dialog mutt ssmtp gfortran libboost-all-dev \ autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat1-dev ninja-build libglib2.0-dev libslirp-dev \ libfdt-dev libpixman-1-dev \ device-tree-compiler libboost-regex-dev libboost-system-dev \ diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 8c5e0e4a3..3a81e3f06 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -64,7 +64,7 @@ sudo apt upgrade -y # Packages are grouped by which tool requires them, split by line. # If mutltipole tools need a package, it is included in the first tool only # General/Wally specific, riscv-gnu-toolchain, qemu, spike, verilator, sail -sudo apt install -y git make cmake python3 python3-pip python3-venv curl wget ftp tar pkg-config dialog mutt ssmtp \ +sudo apt install -y git make cmake python3 python3-pip python3-venv curl wget ftp tar pkg-config dialog mutt ssmtp gfortran libboost-all-dev \ autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat1-dev ninja-build libglib2.0-dev libslirp-dev \ libfdt-dev libpixman-1-dev \ device-tree-compiler libboost-regex-dev libboost-system-dev \ diff --git a/config/derivlist.txt b/config/derivlist.txt index 04f02a181..48f69e7cf 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -58,15 +58,17 @@ PLIC_SDC_ID 32'd20 BPRED_SIZE 32'd12 # The syn configurations are trimmed down for faster synthesis. -deriv syn_rv32e rv32e -DTIM_RANGE 64'h1FF -IROM_RANGE 64'h1FF -BOOTROM_RANGE 64'h1FF -UNCORE_RAM_RANGE 64'h1FF -WAYSIZEINBYTES 32'd512 -NUMWAYS 32'd1 -BPRED_SIZE 32'd5 -BTB_SIZE 32'd5 +deriv syn_rv32e rv32e +DTIM_RANGE 64'h1FF +IROM_RANGE 64'h1FF +BOOTROM_RANGE 64'h1FF +UNCORE_RAM_RANGE 64'h1FF +DCACHE_WAYSIZEINBYTES 32'd512 +ICACHE_WAYSIZEINBYTES 32'd512 +DCACHE_NUMWAYS 32'd1 +ICACHE_NUMWAYS 32'd1 +BPRED_SIZE 32'd5 +BTB_SIZE 32'd5 # The other syn configurations have the same trimming deriv syn_rv32i rv32i syn_rv32e @@ -101,10 +103,15 @@ ZICSR_SUPPORTED 0 deriv syn_rv64gc_noFPU syn_rv64gc_noPriv F_SUPPORTED 0 +ZCF_SUPPORTED 0 D_SUPPORTED 0 +ZCD_SUPPORTED 0 + deriv syn_sram_rv64gc_noFPU syn_sram_rv64gc_noPriv F_SUPPORTED 0 +ZCF_SUPPORTED 0 D_SUPPORTED 0 +ZCD_SUPPORTED 0 deriv syn_rv64gc_noMulDiv syn_rv64gc_noFPU M_SUPPORTED 0 @@ -389,22 +396,24 @@ VIRTMEM_SUPPORTED 0 deriv nodcache_rv32gc rv32gc DCACHE_SUPPORTED 0 D_SUPPORTED 0 +ZCD_SUPPORTED 0 ZALRSC_SUPPORTED 0 ZAAMO_SUPPORTED 0 ZICBOM_SUPPORTED 0 ZICBOZ_SUPPORTED 0 -VIRTMEM_SUPPORTED 0 +VIRTMEM_SUPPORTED 0 # nocache_rv32gc must also disable several features incompatible with no cache deriv nocache_rv32gc rv32gc ICACHE_SUPPORTED 0 DCACHE_SUPPORTED 0 D_SUPPORTED 0 +ZCD_SUPPORTED 0 ZALRSC_SUPPORTED 0 ZAAMO_SUPPORTED 0 ZICBOM_SUPPORTED 0 ZICBOZ_SUPPORTED 0 -VIRTMEM_SUPPORTED 0 +VIRTMEM_SUPPORTED 0 deriv noicache_rv64gc rv64gc ICACHE_SUPPORTED 0 @@ -777,14 +786,38 @@ ZKND_SUPPORTED 0 ZKNE_SUPPORTED 0 ZKNH_SUPPORTED 1 +deriv noS_rv32gc rv32gc +S_SUPPORTED 0 +SSTC_SUPPORTED 0 +VIRTMEM_SUPPORTED 0 +SVINVAL_SUPPORTED 0 +SVADU_SUPPORTED 0 + +deriv noS_rv64gc rv64gc +S_SUPPORTED 0 +SSTC_SUPPORTED 0 +VIRTMEM_SUPPORTED 0 +SVPBMT_SUPPORTED 0 +SVNAPOT_SUPPORTED 0 +SVINVAL_SUPPORTED 0 +SVADU_SUPPORTED 0 + +deriv noU_rv32gc noS_rv32gc +U_SUPPORTED 0 + +deriv noU_rv64gc noS_rv64gc +U_SUPPORTED 0 + # Floating-point modes supported deriv f_rv32gc rv32gc D_SUPPORTED 0 +ZCD_SUPPORTED 0 ZFH_SUPPORTED 0 deriv fh_rv32gc rv32gc D_SUPPORTED 0 +ZCD_SUPPORTED 0 ZFH_SUPPORTED 1 deriv fd_rv32gc rv32gc @@ -803,10 +836,12 @@ ZFH_SUPPORTED 1 deriv f_rv64gc rv64gc D_SUPPORTED 0 +ZCD_SUPPORTED 0 ZFH_SUPPORTED 0 deriv fh_rv64gc rv64gc D_SUPPORTED 0 +ZCD_SUPPORTED 0 ZFH_SUPPORTED 1 deriv fd_rv64gc rv64gc @@ -866,100 +901,124 @@ IEEE754 1 #### F_only, RK variable deriv f_div_2_1_rv32gc div_2_1_rv32gc D_SUPPORTED 0 +ZCD_SUPPORTED 0 ZFH_SUPPORTED 0 deriv f_div_2_2_rv32gc div_2_2_rv32gc D_SUPPORTED 0 +ZCD_SUPPORTED 0 ZFH_SUPPORTED 0 deriv f_div_2_4_rv32gc div_2_4_rv32gc D_SUPPORTED 0 +ZCD_SUPPORTED 0 ZFH_SUPPORTED 0 deriv f_div_4_1_rv32gc div_4_1_rv32gc D_SUPPORTED 0 +ZCD_SUPPORTED 0 ZFH_SUPPORTED 0 deriv f_div_4_2_rv32gc div_4_2_rv32gc D_SUPPORTED 0 +ZCD_SUPPORTED 0 ZFH_SUPPORTED 0 deriv f_div_4_4_rv32gc div_4_4_rv32gc D_SUPPORTED 0 +ZCD_SUPPORTED 0 ZFH_SUPPORTED 0 deriv f_div_2_1_rv64gc div_2_1_rv64gc D_SUPPORTED 0 +ZCD_SUPPORTED 0 ZFH_SUPPORTED 0 deriv f_div_2_2_rv64gc div_2_2_rv64gc D_SUPPORTED 0 +ZCD_SUPPORTED 0 ZFH_SUPPORTED 0 deriv f_div_2_4_rv64gc div_2_4_rv64gc D_SUPPORTED 0 +ZCD_SUPPORTED 0 ZFH_SUPPORTED 0 deriv f_div_4_1_rv64gc div_4_1_rv64gc D_SUPPORTED 0 +ZCD_SUPPORTED 0 ZFH_SUPPORTED 0 deriv f_div_4_2_rv64gc div_4_2_rv64gc D_SUPPORTED 0 +ZCD_SUPPORTED 0 ZFH_SUPPORTED 0 deriv f_div_4_4_rv64gc div_4_4_rv64gc D_SUPPORTED 0 +ZCD_SUPPORTED 0 ZFH_SUPPORTED 0 #### FH_only, RK variable deriv fh_div_2_1_rv32gc div_2_1_rv32gc D_SUPPORTED 0 +ZCD_SUPPORTED 0 ZFH_SUPPORTED 1 deriv fh_div_2_2_rv32gc div_2_2_rv32gc D_SUPPORTED 0 +ZCD_SUPPORTED 0 ZFH_SUPPORTED 1 deriv fh_div_2_4_rv32gc div_2_4_rv32gc D_SUPPORTED 0 +ZCD_SUPPORTED 0 ZFH_SUPPORTED 1 deriv fh_div_4_1_rv32gc div_4_1_rv32gc D_SUPPORTED 0 +ZCD_SUPPORTED 0 ZFH_SUPPORTED 1 deriv fh_div_4_2_rv32gc div_4_2_rv32gc D_SUPPORTED 0 +ZCD_SUPPORTED 0 ZFH_SUPPORTED 1 deriv fh_div_4_4_rv32gc div_4_4_rv32gc D_SUPPORTED 0 +ZCD_SUPPORTED 0 ZFH_SUPPORTED 1 deriv fh_div_2_1_rv64gc div_2_1_rv64gc D_SUPPORTED 0 +ZCD_SUPPORTED 0 ZFH_SUPPORTED 1 deriv fh_div_2_2_rv64gc div_2_2_rv64gc D_SUPPORTED 0 +ZCD_SUPPORTED 0 ZFH_SUPPORTED 1 deriv fh_div_2_4_rv64gc div_2_4_rv64gc D_SUPPORTED 0 +ZCD_SUPPORTED 0 ZFH_SUPPORTED 1 deriv fh_div_4_1_rv64gc div_4_1_rv64gc D_SUPPORTED 0 +ZCD_SUPPORTED 0 ZFH_SUPPORTED 1 deriv fh_div_4_2_rv64gc div_4_2_rv64gc D_SUPPORTED 0 +ZCD_SUPPORTED 0 ZFH_SUPPORTED 1 deriv fh_div_4_4_rv64gc div_4_4_rv64gc D_SUPPORTED 0 +ZCD_SUPPORTED 0 ZFH_SUPPORTED 1 # FD only , rk variable diff --git a/sim/vcs/run_vcs b/sim/vcs/run_vcs index 5601e57b2..80385f6ba 100755 --- a/sim/vcs/run_vcs +++ b/sim/vcs/run_vcs @@ -90,7 +90,7 @@ RTL_FILES="$INCLUDE_DIRS $(find ${SRC} -name "*.sv" ! -path "${SRC}/generic/mem/ # Simulation and Coverage Commands OUTPUT="sim_out" -VCS_CMD="vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L,noSV-PIU,noSTASKW_CO,noSTASKW_CO1,noSTASKW_RMCOF +vcs+vcdpluson -suppress +warn -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -ntb_opts sensitive_dyn +define+SIM_VCS ${INCLUDE_PATH} $RTL_FILES" +VCS_CMD="vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L,noSV-PIU,noSTASKW_CO,noSTASKW_CO1,noSTASKW_RMCOF +vcs+vcdpluson -suppress +warn -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -ntb_opts sensitive_dyn ${INCLUDE_PATH} $RTL_FILES" SIMV_CMD="./${WKDIR}/$OUTPUT +TEST=${TESTSUITE} ${PLUSARGS}" COV_FILES="${TB}/coverage/test_pmp_coverage.sv" COV_OPTIONS="-cm line+cond+branch+fsm+tgl -cm_log ${WKDIR}/coverage.log -cm_dir ${WKDIR}/COVERAGE" diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index b849cd7e6..13dedffa2 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -259,10 +259,12 @@ module csr import cvw::*; #(parameter cvw_t P) ( assign SCOUNTEREN_REGW = '0; assign SATP_REGW = '0; assign IllegalCSRSAccessM = 1'b1; + assign STimerInt = '0; + assign SENVCFG_REGW = '0; end // Floating Point CSRs in User Mode only needed if Floating Point is supported - if (P.F_SUPPORTED | P.D_SUPPORTED) begin:csru + if (P.F_SUPPORTED) begin:csru csru #(P) csru(.clk, .reset, .InstrValidNotFlushedM, .CSRUWriteM, .CSRAdrM, .CSRWriteValM, .STATUS_FS, .CSRUReadValM, .SetFflagsM, .FRM_REGW, .WriteFRMM, .WriteFFLAGSM, diff --git a/src/privileged/csri.sv b/src/privileged/csri.sv index b3db38e8a..41f018e91 100644 --- a/src/privileged/csri.sv +++ b/src/privileged/csri.sv @@ -73,6 +73,7 @@ module csri import cvw::*; #(parameter cvw_t P) ( assign MIP_WRITE_MASK = 12'h000; assign SIP_WRITE_MASK = 12'h000; assign MIE_WRITE_MASK = 12'h888; + assign STIP = '0; end always_ff @(posedge clk) if (reset) MIP_REGW_writeable <= 12'b0; diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index 58ca290e2..a964de2ea 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -195,6 +195,9 @@ module csrm import cvw::*; #(parameter cvw_t P) ( flopenr #(P.XLEN) MENVCFGHreg(clk, reset, WriteMENVCFGHM, MENVCFG_WriteValM[63:32], MENVCFG_REGW[63:32]); assign MENVCFGH_REGW = MENVCFG_REGW[63:32]; end + end else begin + assign MENVCFG_REGW = '0; + assign MENVCFGH_REGW = '0; end // Read machine mode CSRs diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv index 22f34124c..dc970921e 100644 --- a/src/privileged/csrsr.sv +++ b/src/privileged/csrsr.sv @@ -99,7 +99,7 @@ module csrsr import cvw::*; #(parameter cvw_t P) ( assign STATUS_UXL = P.U_SUPPORTED ? 2'b10 : 2'b00; // 10 if user mode supported assign STATUS_SUM = P.S_SUPPORTED & P.VIRTMEM_SUPPORTED & STATUS_SUM_INT; // override reigster with 0 if supervisor mode not supported assign STATUS_MPRV = P.U_SUPPORTED & STATUS_MPRV_INT; // override with 0 if user mode not supported - assign STATUS_FS = (P.S_SUPPORTED & (P.F_SUPPORTED | P.D_SUPPORTED)) ? STATUS_FS_INT : 2'b00; // off if no FP + assign STATUS_FS = P.F_SUPPORTED ? STATUS_FS_INT : 2'b00; // off if no FP assign STATUS_SD = (STATUS_FS == 2'b11) | (STATUS_XS == 2'b11); // dirty state logic assign STATUS_XS = 2'b00; // No additional user-mode state to be dirty diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 9f2b42a5a..be0422550 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -54,7 +54,7 @@ module testbench; `ifdef VERILATOR import "DPI-C" function string getenvval(input string env_name); string RISCV_DIR = getenvval("RISCV"); // "/opt/riscv"; - `elsif SIM_VCS + `elsif VCS import "DPI-C" function string getenv(input string env_name); string RISCV_DIR = getenv("RISCV"); // "/opt/riscv"; `else @@ -419,12 +419,10 @@ module testbench; $display("Coverage tests don't get checked"); end else if (ElfFile != "none") begin $display("Single Elf file tests are not signatured verified."); -`ifdef VERILATOR // this macro is defined when verilator is used - $finish; // Simulator Verilator needs $finish to terminate simulation. -`elsif SIM_VCS // this macro is defined when vcs is used - $finish; // Simulator VCS needs $finish to terminate simulation. +`ifdef QUESTA + $stop; // if this is changed to $finish for Questa, wally-batch.do does not go to the next step to run coverage, and wally.do terminates without allowing GUI debug `else - $stop; // if this is changed to $finish for Questa, wally-batch.do does not go to the next step to run coverage, and wally.do terminates without allowing GUI debug + $finish; `endif end else begin // for tests with no self checking mechanism, read .signature.output file and compare to check for errors @@ -440,12 +438,10 @@ module testbench; if (test == tests.size()) begin if (totalerrors == 0) $display("SUCCESS! All tests ran without failures."); else $display("FAIL: %d test programs had errors", totalerrors); -`ifdef VERILATOR // this macro is defined when verilator is used - $finish; // Simulator Verilator needs $finish to terminate simulation. -`elsif SIM_VCS // this macro is defined when vcs is used - $finish; // Simulator VCS needs $finish to terminate simulation. +`ifdef QUESTA + $stop; // if this is changed to $finish for Questa, wally-batch.do does not go to the next step to run coverage, and wally.do terminates without allowing GUI debug `else - $stop; // if this is changed to $finish for Questa, wally-batch.do does not go to the next step to run coverage, and wally.do terminates without allowing GUI debug + $finish; `endif end end diff --git a/testbench/testbench_fp.sv b/testbench/testbench_fp.sv index f800a9fed..7287e6962 100644 --- a/testbench/testbench_fp.sv +++ b/testbench/testbench_fp.sv @@ -1083,7 +1083,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( end Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; end - 2'b00: if (P.S_SUPPORTED) begin // single + 2'b00: if (P.F_SUPPORTED) begin // single if (OpCtrl === `FMA_OPCTRL) begin X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+4*(P.S_LEN)-1:8+3*(P.S_LEN)]}; Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]}; @@ -1125,7 +1125,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]}; Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; end - 2'b00: if (P.S_SUPPORTED) begin // single + 2'b00: if (P.F_SUPPORTED) begin // single X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]}; Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; end @@ -1146,7 +1146,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]}; Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; end - 2'b00: if (P.S_SUPPORTED) begin // single + 2'b00: if (P.F_SUPPORTED) begin // single X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]}; Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]}; Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; @@ -1169,7 +1169,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[12+(P.D_LEN)-1:12]}; Ans = {{P.FLEN-1{1'b0}}, TestVector[8]}; end - 2'b00: if (P.S_SUPPORTED) begin // single + 2'b00: if (P.F_SUPPORTED) begin // single X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[12+2*(P.S_LEN)-1:12+(P.S_LEN)]}; Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[12+(P.S_LEN)-1:12]}; Ans = {{P.FLEN-1{1'b0}}, TestVector[8]}; @@ -1222,7 +1222,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( end endcase end - 2'b00: if (P.S_SUPPORTED) begin // single + 2'b00: if (P.F_SUPPORTED) begin // single case (OpCtrl[1:0]) 2'b11: begin // quad X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.Q_LEN-1:8+(P.Q_LEN)]}; @@ -1252,7 +1252,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.D_LEN-1:8+(P.D_LEN)]}; Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; end - 2'b00: if (P.S_SUPPORTED) begin // single + 2'b00: if (P.F_SUPPORTED) begin // single X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.S_LEN-1:8+(P.S_LEN)]}; Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; end @@ -1317,7 +1317,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( end endcase end - 2'b00: if (P.S_SUPPORTED) begin // single + 2'b00: if (P.F_SUPPORTED) begin // single // {is the integer a long, is the opperation to an integer} casez ({OpCtrl[2:1]}) 2'b11: begin // long -> single diff --git a/tests/coverage/Makefile b/tests/coverage/Makefile index 6e13dc000..e09d17fa3 100644 --- a/tests/coverage/Makefile +++ b/tests/coverage/Makefile @@ -17,7 +17,7 @@ all: $(OBJECTS) # Change many things if bit width isn't 64 %.elf: $(SRCDIR)/%.$(SEXT) WALLY-init-lib.h Makefile - riscv64-unknown-elf-gcc -g -o $@ -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom -mabi=lp64 -mcmodel=medany \ + riscv64-unknown-elf-gcc -g -o $@ -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 -mcmodel=medany \ -nostartfiles -T../../examples/link/link.ld $< riscv64-unknown-elf-objdump -S -D $@ > $@.objdump riscv64-unknown-elf-elf2hex --bit-width 64 --input $@ --output $@.memfile diff --git a/tests/riscof/Makefile b/tests/riscof/Makefile index 89dd6835e..aaa8a8344 100644 --- a/tests/riscof/Makefile +++ b/tests/riscof/Makefile @@ -43,7 +43,10 @@ wally64: riscof run --work-dir=$(work_dir) --config=config64.ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run rsync -a $(work_dir)/rv64i_m/ $(wally_workdir)/rv64i_m/ || echo "error suppressed" # Also copy F and D tests to RV64 - rsync -a $(work_dir)/rv32i_m/ $(wally_workdir)/rv64i_m/ || echo "error suppressed" + rsync -a $(work_dir)/rv32i_m/ $(wally_workdir)/rv64i_m/ || echo "error suppressed" + +quad64: + riscof run --work-dir=$(work_dir) --config=config64.ini --suite=$(wally_dir)/riscv-test-suite/rv64i_m/Q/riscv-ctg/tests/ --env=$(wally_dir)/riscv-test-suite/env #wally32e: # riscof run --work-dir=$(work_dir) --config=config32e.ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run diff --git a/tests/riscof/sail_cSim/riscof_sail_cSim.py b/tests/riscof/sail_cSim/riscof_sail_cSim.py index eeb024d36..9abe67040 100644 --- a/tests/riscof/sail_cSim/riscof_sail_cSim.py +++ b/tests/riscof/sail_cSim/riscof_sail_cSim.py @@ -70,6 +70,8 @@ class sail_cSim(pluginTemplate): self.isa += 'd' if "Zcb" in ispec["ISA"]: # for some strange reason, Sail requires a command line argument to enable Zcb self.sailargs += "--enable-zcb" + if "Q" in ispec["ISA"]: + self.isa += 'q' objdump = "riscv64-unknown-elf-objdump".format(self.xlen) if shutil.which(objdump) is None: logger.error(objdump+": executable not found. Please check environment setup.") diff --git a/tests/riscof/spike/riscof_spike.py b/tests/riscof/spike/riscof_spike.py index f5b8ea317..2d3eb2a37 100644 --- a/tests/riscof/spike/riscof_spike.py +++ b/tests/riscof/spike/riscof_spike.py @@ -107,6 +107,8 @@ class spike(pluginTemplate): self.isa += 'f' if "D" in ispec["ISA"]: self.isa += 'd' + if "Q" in ispec["ISA"]: + self.isa += 'q' if "C" in ispec["ISA"]: self.isa += 'c' if "Zicsr" in ispec["ISA"]: diff --git a/tests/riscof/spike/spike_rv32gc_isa.yaml b/tests/riscof/spike/spike_rv32gc_isa.yaml index 1e2474023..3fde70700 100644 --- a/tests/riscof/spike/spike_rv32gc_isa.yaml +++ b/tests/riscof/spike/spike_rv32gc_isa.yaml @@ -1,5 +1,6 @@ hart_ids: [0] hart0: +# ISA: RV32IMAFDCZicboz_Zicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh physical_addr_sz: 32 User_Spec_Version: '2.3' diff --git a/tests/riscof/spike/spike_rv64gc_isa.yaml b/tests/riscof/spike/spike_rv64gc_isa.yaml index 5b3f2f47d..0a939e001 100644 --- a/tests/riscof/spike/spike_rv64gc_isa.yaml +++ b/tests/riscof/spike/spike_rv64gc_isa.yaml @@ -1,11 +1,14 @@ hart_ids: [0] hart0: - ISA: RV64IMAFDQCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh +# ISA: RV64IMAFDQCSUZicboz_Zicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh + ISA: RV64IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh +# ISA: RV64IMAFDQCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh physical_addr_sz: 56 User_Spec_Version: '2.3' supported_xlen: [64] misa: - reset-val: 0x800000000015112D + reset-val: 0x800000000014112D +# reset-val: 0x800000000015112D rv32: accessible: false rv64: diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/README.md b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/README.md new file mode 100644 index 000000000..c624e624b --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/README.md @@ -0,0 +1,68 @@ +# Quad Precision Floating Point Tests for Wally +## Shreesh Kulkarni +## Email : kshreesh5@gmail.com +## Date : 26th June, 2024 + + +This folder consists of all the required files and tools to generate Q tests for Wally via riscv-ctg, riscv-isac and riscof. + +NOTE : Only some of the IBM tests are currently supporting Quad testing. + +Tests which are working : ibm1, ibm9,ibm21,ibm23,ibm24,ibm25,ibm26,ibm27,ibm28,ibm29 +These ibm tests can be included in the riscv-ctg tests generation command, along with riscof. + +The tests which are currently breaking due to overflow errors are : ibm2,ibm3,ibm4,ibm5,ibm6,ibm7,ibm8,ibm10,ibm11,ibm12,ibm13,ibm14,ibm15,ibm16,ibm17,ibm18,ibm19,ibm20,ibm22 + +These tests cannnot generate Quad tests yet due to underlying errors. + + +Changes Made : fp_dataset.py in riscv-isac -> This dataset consists of 10 IBM floating point tests generators for Quads + +riscv-ctg-> This folder consists of the CTG tool which is responsible for generating the assembly files for Quads by using the fp_dataset.py in riscv-isac. CGF files were added for each of the IBM floating point tests. + +riscof -> The riscof directory in Wally was changed to include some Quad precision template files for compilation. Along with modification of scripts and yaml files to support FLEN=128 + + + + +Start by installing riscv-ctg via the following commands : + + +cd $WALLY/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg + +pip3 install --editable . + +Once installed, generate the assembly files in the tests directory{cvw/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/tests} for the specific opcode by running this command : + +riscv_ctg --base-isa rv64i --flen 128 --cgf ./sample_cgfs/dataset.cgf --cgf ./sample_cgfs/sample_cgfs_fext/RV32D/fadd.q.cgf -d ./tests/ --randomize -v debug -p2 + +NOTE : The following warning might be generated : +WARNING | Neither mnemonics nor csr_comb node not found in covergroup: datasets + +This can be ignored as this warning tells us that not all IBM tests have been included as only a limited number of them support Quads currently. + +You can choose the corresponding cgf file for the opcode you wish to generate tests. + +This command was referenced in the following Issue generated in the riscv-ctg repository. +(CTG Issue 111){https://github.com/riscv-software-src/riscv-ctg/issues/111} + +You should now see some assembly tests pertaining to your selected opcode in the tests directory(cvw/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/tests). + +To finally generate the SAIL signatures and dut/ref log/assembly files, RISCOF will be used to compile our generated tests from CTG. + +The following command will invoke riscof and generate a riscof-work directory with all the selected tests and log files, SAIL signatures and dis-assembly files. + +PATH=/home/jcarlin/REPOS/sail-riscv/c_emulator/current:$PATH +cd $WALLY/tests/riscof +make quad64 + + +NOTE : The above command will generate the following error. + +ERROR | /home/skulkarni/cvw/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/tests/fadd.q_b1-01.S : - : Failed + +This is because and SAIL and SPIKE's signatures do not match. This needs further debugging. + +The log-files, disassembly files and reference SAIL signatures can be viewed in the riscof-work directory(cvw/tests/riscof/riscof_work/) + + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/CHANGELOG.md b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/CHANGELOG.md new file mode 100644 index 000000000..71683e365 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/CHANGELOG.md @@ -0,0 +1,204 @@ +# CHANGELOG + +This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html). + +Please note the header `WIP-DEV` is to always remain indicating the changes done on the dev branch. +Only when a release to the main branch is done, the contents of the WIP-DEV are put under a +versioned header while the `WIP-DEV` is left empty + +## [0.12.2] - 2024-03-06 +- Add Zfa support. + +## [0.12.1] - 2024-02-27 +- Fix test.yml + +## [0.12.0] - 2024-02-22 +- Update generator.py to take care of hard coded register testcases only if a hard coded register is assigned in the op_comb node of a coverpoint of an instruction. +- Add hardcoded register testcases to dataset.cgf and rv32im.cgf +- Define rs1_val_data for c.ldsp in imc.yaml +- Update "opcode" to "mnemonics" in the cgf files +- Delete main.yml +- Update test.yml for CI +- Define rs1_val_data for instructions from zicfiss.cgf in template.yaml +- Add "warning" in the verbose definition +- Add unratified Zicfiss extension +- Add unratified Zicfilp extension +- Add corner case of division for division operations for RV64 +- Fix csr_comb to write test information +- Add unratified Zaamo subcomponent of A extension +- Add unratified B extension +- Fix issues with csr_comb +- Minor fix in kslraw.u in rv32ip +- Fix incorrect 'sig:' entry in aes32dsi in template.yaml +- Add sig and sz for instructions in template.yaml +- Minor change of rd definition in c.lui in rv32ec +- Minor fix in rv32i_k +- Add rs1_val_data, rs2_val_data, imm_val_data for instructions in template.yaml +- Comment xlenlim out of val_comb in rv32i_b, rv64i_b +- Fix the formats of leading_ones, leading_zeros, trailing_ones, trailing_zeros for instructions in rv32i_b, rv32e_b +- Add op_comb for instructions in rv32i_zcb +- Add rs1_val_data for instructions in imc.yaml +- Add op_comb and val_comb for instructions in rv32ic, rv64ic, rv32ec +- Add corner case of division for division operations for RV32 +- Comment print statements out from generator.py +- Fix whitespaces on empty lines in yaml template files. +- Add unratified Zabha extension +- Add support for unratified Zcmop extension +- Add support for unratified Zimop extension +- Add missing coverage for hard coded register testcases +- Updated CONTRIBUTING.rst to capture the new git strategy adopted to follow a monthly release cadence. +- Add Zifencei, Bit Manipulation and Privilege tests cgf files for RV32E +- Add unratified Zacas extension +- Add support for standard Atomic(A) extension + +## [0.11.1] - 2023-08-15 +- Fixed hex values handling for K extensions +- Fixed set indexing error during opcomb gen +- Fixed whitespaces on empty lines in yaml template files. + +## [0.11.0] - 2022-12-11 +- Added support for csr_comb test generation + +## [0.10.4] - 2023-03-28 +- Adding Zicond support + +## [0.10.3] - 2022-11-22 +- Fixed canary definition + +## [0.10.2] - 2022-10-20 +- Fixed use of lowercase LI. +- Fixed correctval to ?? in comments. +- Fixed sw to SREG for K tests. +- Added canaries and signature boundary labels. + +## [0.10.1] - 2022-09-30 +- Added support for evaluating derived fields for evaluating coverpoints using the instruction object class + +## [0.10.0] - 2022-09-05 +- Added support for bitmanip and crypto scalar coverpoint test generation + +## [0.9.0] - 2022-08-25 +- Added support for cross_comb coverpoint test generation + +## [0.8.0] - 2022-08-08 +- Added support for a distributed template database. +- Added generic mechanisms to generate data sections based on test instances. +- Update templates for floating point tests. +- Fix test generation and macros for floating point tests. + +## [0.7.2] +- Fix errors related to global variables across processes. + +## [0.7.1] - 2022-02-07 +- Fixed mistune version for doc build. + +## [0.7.0] - 2022-02-05 +- Included support for pseudoinstructions + +## [0.6.3] - 2022-03-14 +- Read the vxsat.OV flag before updating signatures in TEST_PKRR_OP() macro +- Use RDOV() macro to read the vxsat.OV flag. + +## [0.6.2] - 2022-03-15 +- Added method to generate data patterns for bitmanip instructions. + +## [0.6.1] - 2022-03-04 +- Check the vxsat.OV flag for P-extension instructions that saturate their results. +- Correct test generation of P-extension instructions affected by the template.yaml ISA node change in 0.6.0. +- update SIGUPD macros to automatically adjust base and offset if offset gets too big + +## [0.6.0] - 2022-01-27 +- Add CGFs for B extensions. +- Modify ISA node in template.yaml to support multiple ISAs per instruction. + +## [0.5.9] - 2021-12-20 +- Add CGFs for P extensions +- Add support for P extension test generation + +## [0.5.8] - 2021-10-21 +- Updated and added bitmanip_real_world.py script to generate test with real world patterns. + +## [0.5.7] - 2021-09-20 +- Fix the generation of rv32ec/cswsp test + +## [0.5.6] - 2021-09-19 +- rvtest\_data section now includes 16 bytes of rotated versions of `0xbabecafe` + +## [0.5.5] - 2021-09-10 +- Add CGFs for F&D extensions +- Add support for F & D extension test generation +- Add support for test splitting based on number of macro instances +- Add macro based signature entry sizes + +## [0.5.4] - 2021-09-02 +- Updated logger to enable logging for API calls. + +## [0.5.3] - 2021-08-12 + +- Update instruction format of aes32 and sm4 instructions for K extensions. +- Improve the coverage of S-boxes for sm4 instructions by setting overlap = "Y" in byte_count. + +## [0.5.2] - 2021-08-09 +- Fix sign of immediate value for branching instructions while filtering. +- Fix instruction generation while result shadowing. + +## [0.5.1] - 2021-07-16 +- Update the sample cgf for RV32E +- fix the generation of RV32E Tests + +## [0.5.0] - 2021-05-27 +- support for K extension and subextension instructions +- support for comments in coverpoints +- added std_op field in template.yaml to indicate is standard-instruction the pseudo op belongs to. +- added support for parsing #nosat in coverpoint which disables the solvers for the current resolution. +- added sample cgf files for rv64ik and rv32ik + +## [0.4.5] - 2021-05-15 +- Minor code restructure to support API calls. +- Fixes to include env files in pip package. + +## [0.4.4] - 2021-02-23 +- Added missing coverpoints for JALR +- fixed CI to run main.yml on pushes to master. +- added version check for PRs in test.yml + +## [0.4.3] - 2021-02-23 +- Updated CI to actions + +## [0.4.2] - 2021-01-15 +- Fixed header base_isa argument +- Change header configuration argument list +- Remove first empty line in assembler output +- Add header randomization argument + +## [0.4.1] - 2020-12-13 +- Fixed correctval generation for existing ops. +- Fixed signedness of operand values for m ext instructions. +- Added operation strings for m and c extensions. + +## [0.4.0] - 2020-11-19 +- Added base_isa as option in cli +- Added support for register set based on base isa. +- Reformatted output values in tests to be hex strings. +- change compliance_model to model_test + +## [0.3.0] - 2020-11-18 +- minor doc updates +- renamed compliance_test.h to arch_test.h +- added aliasing macros for v0.1 compliance framework +- split datasets and coverpoints into multiple cgfs +- support for multiple cgf as inputs +- added support for special datasets to relevant instructions +- adding explicit entry point label to all tests +- remove x2 as coverpoint in cswsp and csdsp + +## [0.2.0] - 2020-11-10 +- initial draft of CTG +- parallelization support added +- random solvers can be used +- support rv32/64imc instructions +- docs updated + +## [0.1.0] - 2020-07025 +- initial draft + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/CONTRIBUTING.rst b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/CONTRIBUTING.rst new file mode 100644 index 000000000..391e27116 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/CONTRIBUTING.rst @@ -0,0 +1,119 @@ +.. See LICENSE.incore for details + +.. highlight:: shell + +====================== +Developer Contribution +====================== + +Contributions are welcome, and they are greatly appreciated and credit will always be given. + +You can contribute in many ways: + +Types of Contributions +---------------------- + +Report Bugs +~~~~~~~~~~~ + +Report bugs at https://github.com/riscv-software-src/riscv-ctg/issues/. + +Submit Feedback +~~~~~~~~~~~~~~~ + +The best way to send feedback is to file an issue at https://github.com/riscv-software-src/riscv-ctg/issues/. + +If you are proposing a feature: + +* Explain in detail how it would work. +* Keep the scope as narrow as possible, to make it easier to implement. +* Remember that this is a volunteer-driven project, and that contributions + are welcome :) + +Git Strategy +------------ + +The repo adopts a simple git strategy where all contributions to the repo are made to the ``dev`` +branch (i.e. all Pull-Requests must use ``dev`` as the target branch). On a monthly cadence (decided +and controlled by the SIG-ARCH-TEST members) the ``dev`` branch will be merged to the ``main`` to by +the official maintainers of the repo. This will create an official release capturing all the +development over the month into a single release. + +To implement the above strategy successfully the following needs be followed: + +* Developers: All pull-requests from developers must target the ``dev`` branch and the PR must +contain an entry in the CHANGELOG.md file under `[WIP-DEV]` section. +* Maintainers: When a making a release the maintainers shall assign semantic version number by +updating the CHANGELOG and the respective python files before raising a PR from the `dev` to `main`. + +Get Started! +------------ + +Ready to contribute? Here's how to set up `riscv_ctg` for local development. + +1. Fork the `riscv_ctg` repo on GitHub. +2. Clone your fork locally and checkout the ``dev`` branch:: + + $ git clone https://github.com/riscv-software-src/riscv-ctg.git -b dev + +3. Create an issue and WIP merge request that creates a working branch for you:: + + $ git checkout -b name-of-your-bugfix-or-feature + + Now you can make your changes locally. + +4. When you're done making changes, check that your changes pass pytest + tests, including testing other Python versions with tox:: + + $ cd tests + $ pytest test_riscv_ctg.py -v + +5. Commit your changes and push your branch to GitLab:: + + $ git add . + $ git commit -m "Your detailed description of your changes." + $ git push origin name-of-your-bugfix-or-feature + +6. Submit a pull-request through the GitHub website. Make sure the pull-request is on the `dev` +branch of the origin repo. + +7. Do not forget to make an entry in the CHANGELOG.md file under the `[WIP-DEV]` section +highlighting the changes you have done. + +Merge Request Guidelines +------------------------ + +Before you submit a merge request, check that it meets these guidelines: + +1. The merge request should include tests (if any). +2. If the merge request adds functionality, the docs should be updated. +3. The target branch must always be the `dev` branch. + + +Versioning (only for maintainers) +--------------------------------- + +When issuing pull requests to the main branch (from dev), a version entry in the CHANGELOG.md is mandatory. The tool adheres to +the [`Semantic Versioning`](https://semver.org/spec/v2.0.0.html) scheme. Following guidelines must +be followed while assigning a new version number : + +- Patch-updates: all doc updates (like typos, more clarification,etc). +- Minor-updates: Fixing bugs in current features, adding new features which do not break current + features or working. Adding new extensions. +- Major-updates: Backward incompatible changes. + +Note: You can have either a patch or minor or major update. +Note: In case of a conflict, the maintainers will decide the final version to be assigned. + +To update the version of the python package for deployment you can use `bumpversion` (installed +using ``pip install bumpversion``):: + +$ bumpversion --no-tag --config-file setup.cfg patch # last arg can be: major or minor or patch + +If you don't have bumpversion installed you can manually update the version in the following files: + +- change the value of variable ``current_version`` in `./setup.cfg` +- change the value of variable ``__version__`` in `./riscv_ctg/__init__.py` + + + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/LICENSE.incore b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/LICENSE.incore new file mode 100644 index 000000000..c1c837a28 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/LICENSE.incore @@ -0,0 +1,30 @@ +BSD 3-Clause License + +Copyright (c) 2020, InCore Semiconductors Pvt. Ltd. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +* Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/MANIFEST.in b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/MANIFEST.in new file mode 100644 index 000000000..25aeae64e --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/MANIFEST.in @@ -0,0 +1,9 @@ +include LICENSE.incore +include README.rst +include riscv_ctg/requirements.txt +recursive-include riscv_ctg/data/ * +recursive-include riscv_ctg/env/ * + +recursive-exclude * __pycache__ +recursive-exclude * *.py[co] +recursive-exclude tests/ * diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/README.rst b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/README.rst new file mode 100644 index 000000000..43f12f3de --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/README.rst @@ -0,0 +1,7 @@ +################################################# +**RISC-V Compliance Test Generator** : RISC-V CTG +################################################# + + +Latest documentation of riscv_ctg : `click here `_ + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/Makefile new file mode 100644 index 000000000..2da5341cd --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/Makefile @@ -0,0 +1,26 @@ +# See LICENSE.incore for details + +# Minimal makefile for Sphinx documentation +# + +# You can set these variables from the command line. +SPHINXOPTS = +SPHINXBUILD = sphinx-build +SPHINXPROJ = riscv_ctg +SOURCEDIR = source +BUILDDIR = build + +# Put it first so that "make" without argument is like "make help". +help: + @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) + +.PHONY: help Makefile + +# Catch-all target: route all unknown targets to Sphinx using the new +# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). +%: Makefile + @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) + +clean: + @$(SPHINXBUILD) -M clean "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/README.md b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/README.md new file mode 100644 index 000000000..50c16d0d6 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/README.md @@ -0,0 +1,15 @@ +# Build the docs + +## For PDF +``` +pip install -r requirements.txt +make latexpdf +evince build/latex/*.pdf +``` + +## HTML +``` +pip install -r requirements.txt +make html +firefox build/html/index.html +``` diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/requirements.txt b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/requirements.txt new file mode 100644 index 000000000..56bbcfbe5 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/requirements.txt @@ -0,0 +1,38 @@ +alabaster==0.7.12 +Babel==2.7.0 +Cerberus==1.3.1 +certifi==2019.6.16 +chardet==3.0.4 +doc8==0.8.0 +docutils==0.14 +gitdb2==2.0.5 +idna==2.8 +imagesize==1.1.0 +Jinja2==2.10.1 +MarkupSafe==1.1.1 +oyaml==0.9 +packaging==19.0 +pbr==5.3.1 +Pygments==2.4.2 +pyparsing==2.4.0 +python-dateutil==2.8.0 +pytz==2019.1 +PyYAML==5.1.1 +requests==2.22.0 +restructuredtext-lint==1.3.0 +ruamel.yaml==0.15.97 +six==1.12.0 +smmap2==2.0.5 +snowballstemmer==1.2.1 +Sphinx==3.0.4 +sphinx-rtd-theme==0.4.3 +sphinxcontrib-autoyaml==0.5.0 +sphinxcontrib-mermaid +sphinxcontrib-websupport==1.1.2 +sphinxcontrib-bibtex==1.0.0 +stevedore==1.30.1 +urllib3==1.25.3 +twine==1.13.0 +sphinx_tabs +m2r2==0.2.7 +mistune==0.8.4 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/_static/custom.css b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/_static/custom.css new file mode 100644 index 000000000..784228836 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/_static/custom.css @@ -0,0 +1,305 @@ +/* -- Extra CSS styles for Zephyr content (RTD theme) ----------------------- */ + +/* make the page width fill the window */ +.wy-nav-content { + max-width: none; +} + +/* pygments tweak for white-on-black console */ +/* hold off on this change for now + +.highlight-console .highlight { + background-color: black; +} +.highlight-console .highlight .go, .highlight-console .highlight .gp { + color: white; +} +.highlight-console .highlight .hll { + background-color: white; +} +.highlight-console .highlight .hll .go, .highlight-console .highlight .hll .gp { + color: black; + font-weight: bold; +} +*/ + +/* tweak doc version selection */ +.rst-versions { + position: static !important; +} + + +.rst-versions .rst-current-version { + padding: 5px; + background-color: #2980B9; + color: #80FF80; +} + +.rst-versions .rst-other-versions { + padding: 5px; +} + +div.rst-other-versions dl { + margin-bottom: 0; +} + +/* tweak spacing after a toctree, fixing issue from sphinx-tabs */ +.toctree-wrapper ul, ul.simple ol.simple { + margin-bottom: 24px !important; +} + +/* code block highlight color in rtd changed to lime green, no no no */ + +.rst-content tt.literal, .rst-content code.literal, .highlight { + background: #f0f0f0; +} +.rst-content tt.literal, .rst-content code.literal { + color: #000000; +} + +/* code literal links should be blue, and purple after visiting */ +a.internal code.literal { + color: #2980B9; +} +a.internal:visited code.literal { + color: #9B59B9; +} + +/* Make the version number more visible */ +.wy-side-nav-search>div.version { + color: rgba(255,255,255,1); +} + +/* squish the space between a paragraph before a list */ +div > p + ul, div > p + ol { + margin-top: -20px; +} + +/* squish space before an hlist in a list */ +li table.hlist { + margin-top: -10px; + margin-bottom: 5px; +} + +/* add some space before the figure caption */ +p.caption { +# border-top: 1px solid; + margin-top: 1em; +} + +/* decrease line leading a bit, 24px is too wide */ + +p { + line-height: 22px; +} + +/* add a colon after the figure/table number (before the caption) */ +span.caption-number::after { + content: ": "; +} + +p.extrafooter { + text-align: right; + margin-top: -36px; +} + +table.align-center { + display: table !important; +} + +/* put the table caption at the bottom, as done for figures */ +table { + caption-side: bottom; +} + +.code-block-caption { + color: #000; + font: italic 85%/1 arial,sans-serif; + padding: 1em 0; + text-align: center; +} + +/* make .. hlist:: tables fill the page */ +table.hlist { + width: 95% !important; + table-layout: fixed; +} + +/* override rtd theme white-space no-wrap in table heading and content */ +th,td { + white-space: normal !important; +} + +/* dbk tweak for doxygen-generated API headings (for RTD theme) */ +.rst-content dl.group>dt, .rst-content dl.group>dd>p { + display:none !important; +} +.rst-content dl.group { + margin: 0 0 12px 0px; +} +.rst-content dl.group>dd { + margin-left: 0 !important; +} +.rst-content p.breathe-sectiondef-title { + text-decoration: underline; /* dbk for API sub-headings */ + font-size: 1.25rem; + font-weight: bold; + margin-bottom: 12px; +} +.rst-content div.breathe-sectiondef { + padding-left: 0 !important; +} + +/* doxygenXX item color tweaks, light blue background with dark blue top border */ +.rst-content dl:not(.docutils) dl dt, dl:not(.docutils,.rst-other-versions) dt { + background: #e7f2fa !important; + border-top: none !important; + border-left: none !important; */ +} + + +/* tweak display of option tables to make first column wider */ +col.option { + width: 25%; +} + +/* tweak format for (:kbd:`F10`) */ +kbd +{ + -moz-border-radius:3px; + -moz-box-shadow:0 1px 0 rgba(0,0,0,0.2),0 0 0 2px #fff inset; + -webkit-border-radius:3px; + -webkit-box-shadow:0 1px 0 rgba(0,0,0,0.2),0 0 0 2px #fff inset; + background-color:#f7f7f7; + border:1px solid #ccc; + border-radius:3px; + box-shadow:0 1px 0 rgba(0,0,0,0.2),0 0 0 2px #fff inset; + color:#333; + display:inline-block; + font-family:Arial,Helvetica,sans-serif; + font-size:11px; + line-height:1.4; + margin:0 .1em; + padding:.1em .6em; + text-shadow:0 1px 0 #fff; +} + +/* home page grid display */ + +.grid { + list-style-type: none !important; + display: -webkit-box; + display: -ms-flexbox; + display: flex; + -ms-flex-wrap: wrap; + flex-wrap: wrap; + -webkit-box-pack: center; + -ms-flex-pack: center; + justify-content: center; + margin: 1rem auto; + max-width: calc((250px + 2rem) * 4); +} + +.grid-item { + list-style-type: none !important; + -webkit-box-flex: 0; + -ms-flex: 0 0 auto; + flex: 0 0 auto; + width: 200px; + text-align: center; + margin: 1rem; +} + +.grid-item a { + display: block; + width: 200px; + height: 200px; + padding: 20px; + display: -webkit-box; + display: -ms-flexbox; + display: flex; + -webkit-box-orient: vertical; + -webkit-box-direction: normal; + -ms-flex-direction: column; + flex-direction: column; + -webkit-box-pack: center; + -ms-flex-pack: center; + justify-content: center; + -webkit-box-align: center; + -ms-flex-align: center; + align-items: center; + border: 1px solid #c6cbce; + background-color: #1ab4e7; + color: white; +} + +.grid-item h2 { + font-size: 1.1rem; +} + +.grid-item img { + margin-bottom: 1.1rem; + max-width: 75%; +} + + +.grid-item a:hover { + background-color: #1892BA; + color: white; +} + + +.grid-item p { + margin-top: 0.5rem; + color: #333e48; +} + +.grid-icon { + line-height: 1.8; + font-size: 4rem; + color: white; +} + +/* add a class for multi-column support + * in docs to replace use of .hlist with + * a .. rst-class:: rst-columns + */ + +.rst-columns { + column-width: 18em; +} + +/* numbered "h2" steps */ + +body { + counter-reset: step-count; +} + +div.numbered-step h2::before { + counter-increment: step-count; + content: counter(step-count); + background: #cccccc; + border-radius: 0.8em; + -moz-border-radius: 0.8em; + -webkit-border-radius: 0.8em; + color: #ffffff; + display: inline-block; + font-weight: bold; + line-height: 1.6em; + margin-right: 5px; + text-align: center; + width: 1.6em; +} + +/* tweak bottom margin of a code block in a list */ + +.tab div[class^='highlight']:last-child { + margin-bottom: 1em; +} + +/* force table content font-size in responsive tables to be 100% + * fixing larger font size for paragraphs in the kconfig tables */ + +.wy-table-responsive td p { + font-size:100%; +} diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/_static/incore_logo.png b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/_static/incore_logo.png new file mode 100644 index 000000000..dfbf6c43d Binary files /dev/null and b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/_static/incore_logo.png differ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/_static/l1cache.png b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/_static/l1cache.png new file mode 100644 index 000000000..08d980f20 Binary files /dev/null and b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/_static/l1cache.png differ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/_static/onlyC.png b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/_static/onlyC.png new file mode 100644 index 000000000..2c80aa79f Binary files /dev/null and b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/_static/onlyC.png differ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/_static/riscv-ctg.png b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/_static/riscv-ctg.png new file mode 100644 index 000000000..6871c6ff7 Binary files /dev/null and b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/_static/riscv-ctg.png differ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/_static/theme_overrides.css b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/_static/theme_overrides.css new file mode 100644 index 000000000..63ee6cc74 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/_static/theme_overrides.css @@ -0,0 +1,13 @@ +/* override table width restrictions */ +@media screen and (min-width: 767px) { + + .wy-table-responsive table td { + /* !important prevents the common CSS stylesheets from overriding + this as on RTD they are loaded after this stylesheet */ + white-space: normal !important; + } + + .wy-table-responsive { + overflow: visible !important; + } +} diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/_templates/breadcrumbs.html b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/_templates/breadcrumbs.html new file mode 100644 index 000000000..6c6493a1c --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/_templates/breadcrumbs.html @@ -0,0 +1,14 @@ +{% extends "!breadcrumbs.html" %} +{% block breadcrumbs %} + + {# parameterize default name "Docs" in breadcrumb via docs_title in conf.py #} + {% if not docs_title %} + {% set docs_title = "Docs" %} + {% endif %} + +
  • {{ docs_title }} »
    • + {% for doc in parents %} +
  • {{ doc.title }} »
    • + {% endfor %} +
  • {{ title }}
    • +{% endblock %} diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/_templates/layout.html b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/_templates/layout.html new file mode 100644 index 000000000..24c127eb4 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/_templates/layout.html @@ -0,0 +1,14 @@ +{% extends "!layout.html" %} +{% block document %} + {% if is_release %} +
    + The latest development version + of this page may be more current than this released {{ version }} version. +
    + {% endif %} + {{ super() }} +{% endblock %} +{% block menu %} + {% include "versions.html" %} + {{ super() }} +{% endblock %} diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/_templates/versions.html b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/_templates/versions.html new file mode 100644 index 000000000..5b5362b52 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/_templates/versions.html @@ -0,0 +1,25 @@ +{# Add rst-badge after rst-versions for small badge style. #} +
    + + RISC-V Compatibility Test Generator + v: {{ current_version }} + + +
    +
    +
    {{ _('Release Versions') }}
    + {% for slug, url in versions %} +
    {{ slug }}
    + {% endfor %} +
    +
    +
    {{ _('Quick Links') }}
    +
    + Project Home +
    +
    + Releases +
    +
    +
    +
    diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/add_instr.rst b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/add_instr.rst new file mode 100644 index 000000000..3f2afc39e --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/add_instr.rst @@ -0,0 +1,48 @@ +.. _add_instr: + +################################### +Adding Support for New instructions +################################### + +This section discusses the tasks required to add support of a new instruction generation in CTG. + +Update the Attributes YAML +-------------------------- + +The first step would be to update the attributes YAML to define a node for the new instruction. The +new node must follow the same :ref:`template ` as defined earlier. + +One must try to use the existing datasets and fields as much as possible and avoid creation of new +redundant datasets unless absolutely required. One can also define abstract functions to generate +the datasets on the go instead of having to elaborate them completely in the YAML itself. + +Some of the abstract functions are available in :meth:`~riscv_ctg.constants` for reference. + +Create a new format +------------------- + +If the instruction uses a new instruction format type, which is not already present in the CTG +currently, then the behavior of that will have to be defined in the :meth:`~riscv_ctg.generator` +class. + +This would involve updating the dictionaries :meth:`~riscv_ctg.generator.OPS` and +:meth:`~riscv_ctg.generator.VALS` with the new type. Next create a function ``__XX_instr__`` in +:meth:`~riscv_ctg.generator` similar to the existing ones which defines how the +:ref:`op_comb and val_comb ` solutions are merged to create the corresponding instruction. + +Additional Register Allocations +------------------------------- + +Currently the signature register allocation assumes a max of 3 registers being used by an +instruction. However, if your instruction uses more registers then the +:meth:`~riscv_ctg.generator.Generator.swreg` function will also need an update. + +Similarly the test register allocation function :meth:`~riscv_ctg.generator.Generator.testreg` function will +also have to be updated. + +Adding Instruction Macros +------------------------- + +CTG does not generate direct instruction. It rather uses the template field in the attributes YAML +as a template to generate tests. This template is usually an assembly macro. The definition of these +macros must be defined in ``env/arch_test.h`` header file. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/cli.rst b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/cli.rst new file mode 100644 index 000000000..6addf049b --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/cli.rst @@ -0,0 +1,91 @@ +.. See LICENSE.incore for details + +===== +Usage +===== +Once you have RISCV-CTG installed, executing ``riscv_ctg --help`` should print the following on the terminal. :: + + Usage: riscv_ctg [OPTIONS] + + Options: + --version Show the version and exit. + -v, --verbose [info|error|debug] + Set verbose level + -d, --out-dir PATH Output directory path + -r, --randomize Randomize Outputs. + -cf, --cgf PATH Path to the cgf file(s). Multiple allowed. + -p, --procs INTEGER Max number of processes to spawn + -bi, --base-isa [rv32e|rv32i|rv64i] + Base ISA string for the tests. + --help Show this message and exit. + +To use RISC-V Compatibility Test Generator in a project:: + + import riscv_ctg + +Running the Test generator +========================== + +In order to generate the tests for **RV32I** the following command is used. :: + + $ mkdir tests/ + $ riscv_ctg -v debug -d ./tests/ -r -cf ./sample_cgfs/dataset.cgf -cf ./sample_cgfs/rv32i.cgf -bi rv32i -p2 + +Suite Characteristics +===================== + +Directory structure +------------------- + +The various `.S` files are the tests themselves. + +.. code-block:: console + + . + ├── Addi.S + ├── Add.S + ├── Andi.S + ├── And.S + ├── Auipc.S + ├── Beq.S + ├── Bge.S + ├── Bgeu.S + ├── Blt.S + ├── Bltu.S + ├── Bne.S + ├── env # Contains the necessary environment files + │   ├── arch_test.h # Header file containing the macros used in tests + │   └── encoding.h # Header file containing varios encodings required + ├── Jalr.S + ├── Jal.S + ├── Lb-align.S + ├── Lbu-align.S + ├── Lh-align.S + ├── Lhu-align.S + ├── Lui.S + ├── Lw-align.S + ├── Ori.S + ├── Or.S + ├── Sb-align.S + ├── Sh-align.S + ├── Slli.S + ├── Sll.S + ├── Slti.S + ├── Sltiu.S + ├── Slt.S + ├── Sltu.S + ├── Srai.S + ├── Sra.S + ├── Srli.S + ├── Srl.S + ├── Sub.S + ├── Sw-align.S + ├── Xori.S + └── Xor.S + +Test Structure +-------------- + +All tests follow the test-spec format available here: `Test Spec Format`_ + +.. _Test Spec Format: https://riscof.readthedocs.io/en/latest/testformat.html#test-format-spec diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/code.rst b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/code.rst new file mode 100644 index 000000000..e07bdaa66 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/code.rst @@ -0,0 +1,21 @@ + +.. _code: + +Code Docs +######### + +Generator-Module +================= + +.. automodule:: riscv_ctg.generator + :members: + :special-members: + :private-members: + +Constants-Module +================ + +.. automodule:: riscv_ctg.constants + :members: + :special-members: + :private-members: diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/conf.py b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/conf.py new file mode 100644 index 000000000..74e98437c --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/conf.py @@ -0,0 +1,450 @@ +# See LICENSE.incore for details + + +# riscv_ctg documentation build configuration file, created by +# sphinx-quickstart on Fri Jun 9 13:47:02 2017. +# +# This file is execfile()d with the current directory set to its +# containing dir. +# +# Note that not all possible configuration values are present in this +# autogenerated file. +# +# All configuration values have a default; values that are commented out +# serve to show the default. + +import sys +import os +import shlex +import re + +def get_version(): + changelog = open('../../CHANGELOG.md','r').read() + x = re.findall(r'## \[(.*?)\] -',changelog)[0] + return str(x) + +sys.path.insert(0, os.path.abspath('../..')) +sys.setrecursionlimit(1500) + +# General information about the project. +project = 'RISC-V Compatibility Test Generator' +copyright = u'2020 InCore Semiconductors Pvt. Ltd' + +author = '' + +version = str(get_version()) +# The full version, including alpha/beta/rc tags +release = version + +def setup(app): + app.add_stylesheet("custom.css") + app.add_css_file("_static/custom.css") + +# -- General configuration --------------------------------------------------- + +# If your documentation needs a minimal Sphinx version, state it here. +#needs_sphinx = '1.0' + +# Add any Sphinx extension module names here, as strings. They can be +# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom +# ones. +needs_sphinx = '1.7.5' +extensions = [ + 'sphinx.ext.autodoc', + 'sphinx.ext.doctest', + 'sphinx.ext.intersphinx', + 'sphinx.ext.todo', + 'sphinx.ext.coverage', + 'sphinx.ext.mathjax', + 'sphinx.ext.viewcode', + 'sphinxcontrib.autoyaml', + 'sphinxcontrib.bibtex', + 'sphinx_tabs.tabs', + 'm2r2' +] + +# Add any paths that contain templates here, relative to this directory. +templates_path = ['_templates'] + +# The suffix(es) of source filenames. +# You can specify multiple suffix as a list of string: +source_suffix = ['.rst', '.md'] +#source_suffix = '.rst' + +# The encoding of source files. +#source_encoding = 'utf-8-sig' + +# The master toctree document. +master_doc = 'index' + + +# The language for content autogenerated by Sphinx. Refer to documentation +# for a list of supported languages. +# +# This is also used if you do content translation via gettext catalogs. +# Usually you set "language" from the command line for these cases. +language = None + +# List of patterns, relative to source directory, that match files and +# directories to ignore when looking for source files. +exclude_patterns = ['_build'] + +# The name of the Pygments (syntax highlighting) style to use. +pygments_style = 'sphinx' + + +# -- Options for HTML output ------------------------------------------------- + +# If true, `todo` and `todoList` produce output, else they produce nothing. +todo_include_todos = True + + +# -- Options for HTML output ---------------------------------------------- + +github_url = 'https://github.com/riscv/riscv-ctg' +html_show_sourcelink = True +# The theme to use for HTML and HTML Help pages. See the documentation for +# a list of builtin themes. +# +#html_theme = 'bootstrap' +#html_theme = 'alabaster' +import sphinx_rtd_theme +html_theme_path = [sphinx_rtd_theme.get_html_theme_path()] +html_theme = 'sphinx_rtd_theme' +html_theme_options = { + 'prev_next_buttons_location': 'both', + 'display_version': True, + 'includehidden': False, + 'collapse_navigation':True, + 'sticky_navigation': True, + 'navigation_depth': 4, + 'includehidden': True, + 'titles_only': False + } +#html_sidebars = { +# "**": ["about.html", "navigation.html", "searchbox.html", "donate.html"] +#} + +# Add any paths that contain custom static files (such as style sheets) here, +# relative to this directory. They are copied after the builtin static files, +# so a file named "default.css" will overwrite the builtin "default.css". +html_static_path = ['_static'] +html_logo='_static/incore_logo.png' +html_show_license = True +docs_title = 'Docs / %s' %(version) +# The name of an image file (within the static path) to use as favicon of the +# docs. This file should be a Windows icon file (.ico) being 16x16 or 32x32 +# pixels large. +html_favicon = '_static/onlyC.png' +html_context = { + 'show_license': html_show_license, + 'docs_title': docs_title, + 'is_release': False, + 'theme_logo_only': False, + 'current_version': version, + } +html_last_updated_fmt = '%b %d, %Y' +# If false, no module index is generated. +html_domain_indices = False + +# If false, no index is generated. +html_use_index = True + +# If true, the index is split into individual pages for each letter. +html_split_index = True + +# If true, links to the reST sources are added to the pages. +html_show_sourcelink = False + +# If true, "Created using Sphinx" is shown in the HTML footer. Default is True. +html_show_sphinx = False + +# If true, license is shown in the HTML footer. Default is True. +html_show_license = True + +# Custom sidebar templates, must be a dictionary that maps document names +# to template names. +# +# The default sidebars (for documents that don't match any pattern) are +# defined by theme itself. Builtin themes are using these templates by +# default: ``['localtoc.html', 'relations.html', 'sourcelink.html', +# 'searchbox.html']``. +# +# html_sidebars = {} + + + +# Output file base name for HTML help builder. +htmlhelp_basename = 'RISC-V Compatibility Test Generator' + +# -- Options for LaTeX output --------------------------------------------- + +# -- Options for LaTeX output ------------------------------------------------ +latex_engine='xelatex' +numfig = True +latex_elements = { + # The paper size ('letterpaper' or 'a4paper'). +# + 'papersize': 'letterpaper', + 'releasename':version, + 'extraclassoptions': 'openany, twoside', + + # Sonny, Lenny, Glenn, Conny, Rejne, Bjarne and Bjornstrup + #'fncychap': '\\usepackage[Bjornstrup]{fncychap}', + 'fncychap': '\\usepackage{fancyhdr}', + 'fontpkg': '\\usepackage{amsmath,amsfonts,amssymb,amsthm}', + + 'figure_align':'htbp', + # The font size ('10pt', '11pt' or '12pt'). +# + 'pointsize': '12pt', + + # Additional stuff for the LaTeX preamble. +# + 'preamble': r''' + % change the fon to san-serif + %\renewcommand{\familydefault}{\sfdefault} + + %%%%%%%%%%%%%%%%%%%% Meher %%%%%%%%%%%%%%%%%% + %%%add number to subsubsection 2=subsection, 3=subsubsection + %%% below subsubsection is not good idea. + \setcounter{secnumdepth}{3} + % + %%%% Table of content upto 2=subsection, 3=subsubsection + \setcounter{tocdepth}{2} + + \usepackage{amsmath,amsfonts,amssymb,amsthm} + \usepackage{graphicx} + \usepackage{array, caption, tabularx, ragged2e, booktabs, longtable} + \usepackage{stfloats} + \usepackage{multirow} + \usepackage{gensymb} + \usepackage{fontspec} + \setmainfont{Ubuntu Light} + \definecolor{light-gray}{gray}{0.85} + \usepackage{color,xesearch} + \usepackage{soul} + \sethlcolor{light-gray} + \makeatletter + + %%% reduce spaces for Table of contents, figures and tables + %%% it is used "\addtocontents{toc}{\vskip -1.2cm}" etc. in the document + \usepackage[notlot,nottoc,notlof]{} + + \usepackage{color} + \usepackage{transparent} + \usepackage{eso-pic} + \usepackage{lipsum} + + \usepackage{footnotebackref} %%link at the footnote to go to the place of footnote in the text + + %% spacing between line + \usepackage{setspace} + %%%%\onehalfspacing + %%%%\doublespacing + \singlespacing + + + %%%%%%%%%%% datetime + \usepackage{datetime} + + \newdateformat{MonthYearFormat}{% + \monthname[\THEMONTH], \THEYEAR} + + + %% RO, LE will not work for 'oneside' layout. + %% Change oneside to twoside in document class + \pagestyle{fancy} + \makeatletter + \fancypagestyle{normal}{ + \fancyhf{} + + %%% Alternating Header for oneside + %\fancyhead[L]{\ifthenelse{\isodd{\value{page}}}{ \small \nouppercase{\leftmark} }{}} + %\fancyhead[R]{\ifthenelse{\isodd{\value{page}}}{}{ \small \nouppercase{\rightmark} }} + + %%% Alternating Header for two side + \fancyhead[RO]{\small \nouppercase{\leftmark}} + \fancyhead[RE]{\small \nouppercase{\leftmark}} + \fancyhead[LE,LO]{\py@HeaderFamily \@title\sphinxheadercomma\releasename} + %\fancyhead[RE,RO]{\py@HeaderFamily \c@chapter} + + %% for oneside: change footer at right side. If you want to use Left and right then use same as header defined above. + %\fancyfoot[R]{\ifthenelse{\isodd{\value{page}}}{{\tiny Meher Krishna Patel} }{\href{http://pythondsp.readthedocs.io/en/latest/pythondsp/toc.html}{\tiny PythonDSP}}} + + %%% Alternating Footer for two side + \fancyfoot[LO, LE]{\small \bf{Copyright \textcopyright \the\year \textbf{ } InCore Semiconductors Pvt. Ltd.}} + %\fancyfoot[LO, LE]{\scriptsize \bf{RISC-V Compatibility Test Generator}} + + %%% page number + \fancyfoot[RO, RE]{\thepage} + + \renewcommand{\headrulewidth}{0.4pt} + \renewcommand{\footrulewidth}{0.4pt} + } + \makeatother + \RequirePackage{tocbibind} %%% comment this to remove page number for following + \addto\captionsenglish{\renewcommand{\contentsname}{Table of contents}} + \addto\captionsenglish{\renewcommand{\listfigurename}{List of figures}} + \addto\captionsenglish{\renewcommand{\listtablename}{List of tables}} + % \addto\captionsenglish{\renewcommand{\chaptername}{Chapter}} + + + %%reduce spacing for itemize + \usepackage{enumitem} + \setlist{nosep} + + %%%%%%%%%%% Quote Styles at the top of chapter + \usepackage{epigraph} + \setlength{\epigraphwidth}{0.8\columnwidth} + \newcommand{\chapterquote}[2]{\epigraphhead[60]{\epigraph{\textit{#1}}{\textbf {\textit{--#2}}}}} + %%%%%%%%%%% Quote for all places except Chapter + \newcommand{\sectionquote}[2]{{\quote{\textit{``#1''}}{\textbf {\textit{--#2}}}}} + + \linespread{1} + ''', + + + 'maketitle': r''' + \pagenumbering{Roman} %%% to avoid page 1 conflict with actual page 1 + + \begin{titlepage} + \centering + + \begin{figure}[!h] + \centering + \includegraphics[scale=0.2]{incore_logo.png} + \end{figure} + \vspace*{40mm} %%% * is used to give space from top + \textbf{\Huge {RISC-V Compatibility Test Generator}} + \vspace*{40mm} %%% * is used to give space from top + + + \vspace{10mm} + \Large \textbf{{Release: \releasename}} + \vspace{10mm} + + Last update on : \today + + \vspace*{0mm} + %\small Last updated : \MonthYearFormat\today + + + %% \vfill adds at the bottom + \vfill + Copyright \textcopyright \the\year \textbf{ } InCore Semiconductors Pvt. Ltd. + \end{titlepage} + \sloppy + + \clearpage +% \pagenumbering{roman} + \tableofcontents + \clearpage + \listoffigures + \clearpage + \listoftables + \clearpage + \pagenumbering{arabic} + ''', + # Latex figure (float) alignment +# + # 'figure_align': 'htbp', + 'sphinxsetup': \ + 'hmargin={0.7in,0.7in}, vmargin={1in,1in}, \ + verbatimwithframe=true, \ + TitleColor={rgb}{0,0,0}, \ + HeaderFamily=\\rmfamily\\bfseries, \ + InnerLinkColor={rgb}{0,0,1}, \ + OuterLinkColor={rgb}{0,0,1}', + + 'tableofcontents':' ', + + + +} + +#latex_elements = { +# # The paper size ('letterpaper' or 'a4paper'). +# # +# 'papersize': 'letterpaper', +# +# # The font size ('10pt', '11pt' or '12pt'). +# # +# 'pointsize': '10pt', +# +# # Additional stuff for the LaTeX preamble. +# # +# 'preamble': '', +# +# # Latex figure (float) alignment +# # +# 'figure_align': 'htbp', +# +# 'atendofbody' : ' InCore Semiconductors Pvt. Ltd.' +#} + +# Grouping the document tree into LaTeX files. List of tuples +# (source start file, target name, title, +# author, documentclass [howto, manual, or own class]). +latex_documents = [ + (master_doc, 'riscv_ctg.tex', 'RISC-V CTG Documentation', + 'InCore Semiconductors Pvt. Ltd.', 'manual'), +] + +latex_logo = '_static/incore_logo.png' + +latex_show_pagerefs = True + +# -- Options for manual page output ------------------------------------------ + +# One entry per manual page. List of tuples +# (source start file, name, description, authors, manual section). +man_pages = [ + (master_doc, 'riscv_ctg', 'RISC-V CTG Documentation', + 'InCore Semiconductors Pvt. Ltd.', 1) +] + + +# -- Options for Texinfo output ---------------------------------------------- + +# Grouping the document tree into Texinfo files. List of tuples +# (source start file, target name, title, author, +# dir menu entry, description, category) +texinfo_documents = [ + (master_doc, 'riscv_ctg', 'RISC-V CTG Documentation', + 'InCore Semiconductors Pvt. Ltd.', 'One line description of project.', + 'Miscellaneous'), +] + +# -- Options for Epub output ------------------------------------------------- + +# Bibliographic Dublin Core info. +epub_title = project +epub_author = author +epub_publisher = author +epub_copyright = copyright + +# The unique identifier of the text. This can be a ISBN number +# or the project homepage. +# +# epub_identifier = '' + +# A unique identification for the text. +# +# epub_uid = '' + +# A list of files that should not be packed into the epub file. +epub_exclude_files = ['search.html'] + + +# -- Extension configuration ------------------------------------------------- + +# -- Options for intersphinx extension --------------------------------------- + +# Example configuration for intersphinx: refer to the Python standard library. +intersphinx_mapping = {'https://docs.python.org/': None} + +# -- Options for todo extension ---------------------------------------------- + +# If true, `todo` and `todoList` produce output, else they produce nothing. +todo_include_todos = True diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/contributing.rst b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/contributing.rst new file mode 100644 index 000000000..ac7b6bcf3 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/contributing.rst @@ -0,0 +1 @@ +.. include:: ../../CONTRIBUTING.rst diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/cross_comb.rst b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/cross_comb.rst new file mode 100644 index 000000000..b876e4eff --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/cross_comb.rst @@ -0,0 +1,35 @@ +************************************************ +Test Generation using Cross Coverage Coverpoints +************************************************ + +Coverpoints constituting multiple instructions can help identify interesting instruction +sequences which have architectural significance such as structural hazards and data hazards. +The coverpoint node associated with the test generation is ``cross_comb`` defined `here `_. + +The test generator employs a constraint solver to generate relevant instruction sequence for a +``cross_comb`` coverpoint. + +Example +------- + + **Coverpoint Definition** + + An example cross combination coverpoint is given below: :: + + add: + cross_comb: + "[add : ? : rv32i_arith : ? : sub] :: [a=rd : ? : ? : ? : ?] :: [? : rs1==a or rs2==a : rs1==a or rs2==a : rs1==a or rs2==a : rd==a]" + + **Possible assembly sequence** + + A possible sequence of instructions CTG would generate is: :: + + add x3, x3, x4 + addi x5, x3, 1 + sub x6, x4, x3 + addi x4, x3, -3 + sub x3, x5, x6 + +The test generator also embeds appropriate macros for initialization of registers and signature region pointing registers. + +Note: The cross-combination test generator as of now, does not support load, store and branch instructions \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/csr_comb.rst b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/csr_comb.rst new file mode 100644 index 000000000..f9f596de8 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/csr_comb.rst @@ -0,0 +1,26 @@ +************************************************* +Test Generation using CSR Combination Coverpoints +************************************************* + +CSR Combination Coverpoints can help checking for some basic compliance with the privileged +part of the RISC-V spec by specifying conditions on the CSR values. +The coverpoint node associated with the test generation is ``csr_comb`` defined `here `_. + +Currently, the test generation is only possible for the coverpoints that test for the values of subfields in CSRs. +Thus, the only supported coverpoints are the form ``csr_reg & mask == val``, where: + +* ``mask`` and ``val`` are allowed to be any valid python expressions. +* ``csr_reg`` is allowed to be operated by a bit shift operator, i.e., ``(csr_reg >> shift) & mask == val`` is allowed where ``shift`` is a valid python expression. +* functions ``old("csr_name")`` and ``write("csr_name")`` are allowed to be used in the place of ``csr_reg`` to access the old value and write value of a CSR respectively. +* combination of multiple conditions with ``and`` and ``or`` is allowed. + +Example +------- + + **Coverpoint Definition** + + An example CSR combination coverpoint is given below: :: + + misa: + csr_comb: + 'old("misa") & 0x4 == 0 and (write("misa") >> 12) & 1 == 0 and misa & 0x1000 == 0x1000': 0 \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/diagrams/git_flow.png b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/diagrams/git_flow.png new file mode 100644 index 000000000..6c2db349b Binary files /dev/null and b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/diagrams/git_flow.png differ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/index.rst b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/index.rst new file mode 100644 index 000000000..a81b7407e --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/index.rst @@ -0,0 +1,25 @@ +.. See LICENSE.incore for details + +.. _home: + +RISC-V Compatibility Test Generator Documentation +################################################# + +Welcome to RISC-V Compatibility Test Generator documentation. + +For information about the changes and additions for releases, +please refer to the :ref:`Revisions ` documentation. + +.. toctree:: + :glob: + :maxdepth: 1 + :numbered: + + overview + installation + cli + add_instr + code + contributing + revisions + licensing diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/index_bkp b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/index_bkp new file mode 100644 index 000000000..e04f03405 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/index_bkp @@ -0,0 +1,103 @@ +.. See LICENSE.incore for details + +.. _home: + +RISC-V Compliance Test Generator Documentation +############################################### + +Welcome to RISC-V Compliance Test Generator documentation version: |version| + +For information about the changes and additions for releases, +please refer to the :ref:`Revisions ` documentation. + +.. raw:: html + + + +.. include:: + +.. only:: latex + + .. note:: + + This document provides detailed information of the IPs generated and maintained by InCore + Semiconductors Pvt. Ltd. + + **Proprietary Notice** + + Copyright (c) 2020, InCore Semiconductors Pvt. Ltd. + + Information in this document is provided "as is" with faults, if any. + + InCore expressly disclaims all warranties, representations, and conditions of any kind, whether + express or implied, including, but not limited to, the implied warranties or conditions of + merchantability, fitness for a particular purpose and non-infringement. + + InCore does not assume any liability rising out of the application or use of any product or circuit, + and specifically disclaims any and all liability, including without limitation indirect, incidental, + special, exemplary, or consequential damages. + + InCore reserves the right to make changes without further notice to any products herein. + +.. only:: html + + Sections + ******** + +.. toctree:: + :glob: + :maxdepth: 1 + :numbered: + + overview + getting_started + features + installation + cli + tests + contriburing + revisions + licensing diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/installation.rst b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/installation.rst new file mode 100644 index 000000000..49a85c240 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/installation.rst @@ -0,0 +1,162 @@ +.. See LICENSE.incore for details + +.. highlight:: shell + +============ +Installation +============ + +Install Python +============== + +.. tabs:: + + .. tab:: Ubuntu + + + Ubuntu 17.10 and 18.04 by default come with python-3.6.9 which is sufficient for using riscv-ctg. + + If you are are Ubuntu 16.10 and 17.04 you can directly install python3.6 using the Universe + repository + + .. code-block:: shell-session + + $ sudo apt-get install python3.6 + $ pip3 install --upgrade pip + + If you are using Ubuntu 14.04 or 16.04 you need to get python3.6 from a Personal Package Archive + (PPA) + + .. code-block:: shell-session + + $ sudo add-apt-repository ppa:deadsnakes/ppa + $ sudo apt-get update + $ sudo apt-get install python3.6 -y + $ pip3 install --upgrade pip + + You should now have 2 binaries: ``python3`` and ``pip3`` available in your $PATH. + You can check the versions as below + + .. code-block:: shell-session + + $ python3 --version + Python 3.6.9 + $ pip3 --version + pip 20.1 from .local/lib/python3.6/site-packages/pip (python 3.6) + + .. tab:: CentOS7 + + The CentOS 7 Linux distribution includes Python 2 by default. However, as of CentOS 7.7, Python 3 + is available in the base package repository which can be installed using the following commands + + .. code-block:: shell-session + + $ sudo yum update -y + $ sudo yum install -y python3 + $ pip3 install --upgrade pip + + For versions prior to 7.7 you can install python3.6 using third-party repositories, such as the + IUS repository + + .. code-block:: shell-session + + $ sudo yum update -y + $ sudo yum install yum-utils + $ sudo yum install https://centos7.iuscommunity.org/ius-release.rpm + $ sudo yum install python36u + $ pip3 install --upgrade pip + + You can check the versions + + .. code-block:: shell-session + + $ python3 --version + Python 3.6.8 + $ pip --version + pip 20.1 from .local/lib/python3.6/site-packages/pip (python 3.6) + +Using Virtualenv for Python +--------------------------- + +Many a times users face issues in installing and managing multiple python versions. This is actually +a major issue as many gui elements in Linux use the default python versions, in which case installing +python3.6 using the above methods might break other software. We thus advise the use of **pyenv** to +install python3.6. + +For Ubuntu and CentosOS, please follow the steps here: https://github.com/pyenv/pyenv#basic-github-checkout + +RHEL users can find more detailed guides for virtual-env here: https://developers.redhat.com/blog/2018/08/13/install-python3-rhel/#create-env + +Once you have pyenv installed do the following to install python 3.6.0:: + + $ pyenv install 3.6.0 + $ pip3 install --upgrade pip + $ pyenv shell 3.6.0 + +You can check the version in the **same shell**:: + + $ python --version + Python 3.6.0 + $ pip --version + pip 20.1 from .local/lib/python3.6/site-packages/pip (python 3.6) + +Install RISC-V CTG (From Git) +============================================================= + +To install RISC-V Compatibility Test Generator, run this command in your terminal: + +.. code-block:: console + + $ python3 -m pip3 install git+https://github.com/riscv/riscv-ctg.git + +This is the preferred method to install RISC-V Compatibility Test Generator, as it will always install the most recent stable release. + +If you don't have `pip`_ installed, this `Python installation guide`_ can guide +you through the process. + +.. _pip: https://pip.pypa.io +.. _Python installation guide: http://docs.python-guide.org/en/latest/starting/installation/ + +Install RISC-V CTG (via pip) +===================================================== + +.. note:: If you are using `pyenv` as mentioned above, make sure to enable that environment before + performing the following steps. + +.. code-block:: bash + + $ pip3 install riscv_ctg + +To update an already installed version of RISCV-CTG to the latest version: + +.. code-block:: bash + + $ pip3 install -U riscv_ctg + +To checkout a specific version of riscv_ctg: + +.. code-block:: bash + + $ pip3 install riscv_ctg==1.x.x + +Install CTG for Dev +=================== + +The sources for RISC-V Compatibility Test Generator can be downloaded from the `Github repo`_. + +You can clone the repository: + +.. code-block:: console + + $ git clone https://github.com/riscv/riscv-ctg + + +Once you have a copy of the source, you can install it with: + +.. code-block:: console + + $ cd riscv_ctg + $ pip3 install --editable . + + +.. _Github repo: https://github.com/riscv/riscv-ctg diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/licensing.rst b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/licensing.rst new file mode 100644 index 000000000..abb965d15 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/licensing.rst @@ -0,0 +1,10 @@ +.. See LICENSE.incore for details + +##################### +Licensing and Support +##################### + +Please review the LICENSE.* files in the `repository `_ for licensing details. + +For more information about support, customization and other IP developments +please write to info@incoresemi.com. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/overview.rst b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/overview.rst new file mode 100644 index 000000000..e7d265bc6 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/overview.rst @@ -0,0 +1,166 @@ +.. See LICENSE.incore for details + +######## +Overview +######## + +RISCV-CTG is the RISC-V based Compatibility Test Generator. This tool is used to generate tests used in +the official `RISC-V Architectural Test Suite `_ and +the RISC-V architectural test framework `RISCOF `_. All tests generated by +the CTG are compliant with the official `Test Format Spec `_. + +The CTG is similar to a constrained test generator capable of generating tests targeting a specific +set of constraints. These constraints are supplied to the CTG using the `Coverage Group Format +`_ (CGF) File. The CGF file contains various +cover-points for different instructions. The CTG treats each cover-point as a constraint and employs a +solver to identify potential solutions. CTG uses the constraint satisfaction problem (CSPs) solvers +offered by the `python-constraint `_ package. + +Target Audience +=============== + +The target users/audience of the CTG would be verification and design engineers who would like to +create a suite of tests focusing on covering specific corner cases. These tests could then be used +as way of demonstrating the capabilities of the instruction itself. + +Note, that the capabilities of the CTG is completely limited by the limitations of the cover-points +in the CGF. A more elaborate CGF covering all corner cases of an instruction can be supplied to CTG +to create a near verification test for that instruction. + + +CTG Components and Flow +======================= + +The following diagram shows the internal flow of data of the CTG. The following sections will +discuss briefly about the working of the CTG. + +.. figure:: _static/riscv-ctg.png + :align: center + :alt: riscv-isac + + +.. _attributes: + +Instr Attributes +---------------- + +In order to generate tests for a given instructions attributes of the instruction need to be known +before hand. This information is stored within the CTG in a YAML format known as the `attributes file +`_. + +Each node in the attributes files has the following structure: + +.. code-block:: yaml + + name: # name of the instruction + xlen: # list of XLEN values under which this instruction is applicable + isa: # RISC-V ISA extension this instruction attribute belongs to + operation: # a python evaluated string which defines the function of the instruction + formattype: # a string indicating the format type of the instruction + rs1_op_data: # a list of legal registers that can be used as operand 1 + rs2_op_data: # a list of legal registers that can be used as operand 2 + rd_op_data: # a list of legal registers that can be used as destination + rs1_val_data: # a list of integers that can be used as values for operand 1 + rs2_val_data: # a list of integers that can be used as values for operand 2 + template: # a string indicating the assembly macro to be used to creating tests. + +Following is an example of the "add" instruction attribute + +.. code-block:: yaml + + add: + xlen: [32,64] + isa: I + operation: 'hex((rs1_val + rs2_val) & (2**(xlen)-1))' + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: | + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + + +Note in the above example `gen_sign_dataset(**)` and `gen_sp_dataset(**)` are custom functions +defined within the CTG to generate the relevant data points required for those fields. + +.. note:: \*all_reg is an alias to a node defined in the attributes yaml prior to the add node. + +.. _opval_comb: + +Op and Val Combinations +----------------------- + +The first two stages of the CTG receive the input CGF file and identify solutions for the +operands and value combinations. These solutions are carried out independent of each other. During +these phases solvers are employed to find solutions which satisfy the corresponding cover-points. +Immediate values are also assigned here. + +If randomization is enabled, then random solvers are employed. + + +Instruction Creation +-------------------- + +In this stage, the operand and value combination solutions derived in the previous phases are combined with +each other in this phase to complete all the fields of the instruction under test. + + +Signature and Test Register Allocation +--------------------------------------- + +Each instance of the instruction should also be provided a signature register to save the result of +the operation and an additional test register to perform alternate target-specific checks or debug. + +The registers are allocated in a greedy fashion, such that maximum number of instructions use the +same signature and test registers. This thus leads to minimal transfer of pointers across registers. + +CorrectVal Generation +--------------------- + +.. warning:: This feature is a WIP and is not completely supported yet. + +For a few arithmetic instructions like add, sll, sub, etc the corresponding operation field in the +:ref:`attributes ` YAML can be easily defined to capture the behavior of those +instructions. In this, phase CTG uses those fields to define the expected values/result of those +operations. These correctval fields in the tests can be used to perform inline checking of results +and debug failures. + +Generate Tests +-------------- + +Finally, with all the fields defined, specific templates of the tests which conform to the Test +Format Spec are used to generate the assembly files for each instruction. + +Parallel Runs +------------- + +Since CTG employs CSP solvers the runtime of certain constraints involving large data sets can soon +shoot up. Also typically CTG is used to generate a suite of test across instructions instead of a +single test. Thus to reduce runtime in suite generations, CTG internally allocates a cover-group in +the CGF to an individual host-process thereby parallelizing the runs. + +Why Random Solvers? +=================== + +The random solvers are essential in boosting speed. With loosely defined constraints in the CGF, +(like ``rs1_val >0 and rs2_val>0``) the solvers may spend quite some time to find all the solutions +when the datasets are large. Random solvers on the other hand provide the first solution that +satisfies the problem and quit after that, thereby saving time. + +A second benefit of using random values for loosely defined constraints, is that it increases the +chances of covering multiple cover-points (that may be presented later) in the same instruction. This +thereby reduces the number of instructions required to cover all the cover-points mentioned in the +cover-group of the CGF. + +One must note that at no point is the coverage of the test compromised due to the use of random +solvers. + +A obvious down-side of using random solvers is the fact that the same test cannot be reproduced +again. However, the typical intent of users of CTG would be to generates tests satisfying the +cover-points defined in the CGF. Since that is guaranteed by CTG, the reproducibility issue can be +set aside. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/pseudo_op_support.rst b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/pseudo_op_support.rst new file mode 100644 index 000000000..7a98a481d --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/pseudo_op_support.rst @@ -0,0 +1,45 @@ +******************************** +Pseudo-Ops Support for RISCV-CTG +******************************** + +Coverpoints are defined in a CGF file under the ``opcode`` node in the CGF. This is a misnomer as ISAC and CTG +deals with mnemonics of the instruction rather than the actual encoding. In order to deal with mnemonics of pseudo-Ops, +and its congruent base instruction definition, changes are brought to the CGF format. + +Format +###### +The ``opcode`` field is renamed to ``mnemonics``. To support pseudo-instructions two new fields ``base_op`` and ``p_op_cond`` +are added to the covergroups. The ``base_op`` and ``p_op_cond`` are optional fields which specify the base operation and the +condition over the different fields of the instruction which when satisfied results in the instruction being recognized as the +pseudo-op mentioned in ``mnemonics``. As an example, ``zext.h`` is a pseudo-op of ``pack`` in RV32 and ``packw`` in RV64 with ``rs2`` +equal to ``x0``. Covergroup for ``zext.h`` pseudo-op can be expressed as follows: :: + + zext.h_32: + config: + - check ISA:=regex(.*RV32.*B.*) + - check ISA:=regex(.*RV32.*Zbb.*) + mnemonics: + zext.h: 0 + base_op: packw + p_op_cond: rs2 == x0 + ... + + zext.h_64: + config: + - check ISA:=regex(.*RV64.*B.*) + - check ISA:=regex(.*RV64.*Zbb.*) + mnemonics: + zext.h: 0 + base_op: pack + p_op_cond: rs2 == x0 + ... + +During CTG runtime, the ``base_op`` field is checked for in every covergroup. The template corresponding to the instruction found +in ``base_op`` node is extracted to generate the test. If ``base_op`` node does not exist, the instruction found in ``mnemonics`` +is used to extract the required template. ``p_op_cond`` fields are not used as additional constraints for the corresponding pseudo-op. +This is due to the assumption that test generation for a base-op encompasses all pseudo-ops associated with the base-op. + +Note +#### +- The ``p_op_cond`` node is relevant only if the ``base_op`` node has been defined. +- The ``mnemonics`` node is allowed to have multiple entries only if the ``base_op`` node is empty. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/refs.bib b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/refs.bib new file mode 100644 index 000000000..6ae893ac7 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/refs.bib @@ -0,0 +1,19 @@ +@article{riscvpriv, +author = {RISC-V ISA Privileged Specification}, +year = {2020}, +title = {}, +journal = {https://riscv.org/specifications/privileged-isa/}, +} +@article{riscv, +author = {RISC-V ISA Unprivileged Specification}, +year = {2020}, +title = {}, +journal = {https://riscv.org/specifications/isa-spec-pdf/}, +} + +@article{riscvdebug, + author = {RISC-V ISA Debug Specification}, + year = {2020}, + title = {}, + journal = {https://riscv.org/specifications/debug-specification/} +} diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/revisions.rst b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/revisions.rst new file mode 100644 index 000000000..affc7aa43 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/source/revisions.rst @@ -0,0 +1,7 @@ +.. raw:: latex + + \pagebreak + +.. _revisions: + +.. mdinclude:: ../../CHANGELOG.md diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/sphinxext/cairosvgconverter.py b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/sphinxext/cairosvgconverter.py new file mode 100644 index 000000000..11bf2fc6f --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/docs/sphinxext/cairosvgconverter.py @@ -0,0 +1,38 @@ +# -*- coding: utf-8 -*- +""" +""" +from sphinx.errors import ExtensionError +from sphinx.locale import _ +from sphinx.transforms.post_transforms.images import ImageConverter +from sphinx.util import logging +from sphinx.util.osutil import ENOENT, EPIPE, EINVAL +from cairosvg import svg2pdf + +logger = logging.getLogger(__name__) + +class CairoSvgConverter(ImageConverter): + conversion_rules = [ + ('image/svg+xml', 'application/pdf'), + ] + + def is_available(self): + # type: () -> bool + return True + + def convert(self, _from, _to): + # type: (unicode, unicode) -> bool + """Converts the image to expected one.""" + svg2pdf(url=_from, write_to=_to) + + return True + + +def setup(app): + # type: (Sphinx) -> Dict[unicode, Any] + app.add_post_transform(CairoSvgConverter) + + return { + 'version': 'builtin', + 'parallel_read_safe': True, + 'parallel_write_safe': True, + } diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg.egg-info/PKG-INFO b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg.egg-info/PKG-INFO new file mode 100644 index 000000000..f210ec6d3 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg.egg-info/PKG-INFO @@ -0,0 +1,27 @@ +Metadata-Version: 2.1 +Name: riscv-ctg +Version: 0.12.2 +Summary: RISC-V CTG +Home-page: https://github.com/riscv/riscv-ctg +Author: InCore Semiconductors Pvt. Ltd. +Author-email: info@incoresemi.com +License: BSD-3-Clause +Keywords: riscv_ctg +Platform: UNKNOWN +Classifier: Programming Language :: Python :: 3.6 +Classifier: License :: OSI Approved :: BSD License +Classifier: Development Status :: 4 - Beta +Requires-Python: >=3.6.0 +License-File: LICENSE.incore + +################################################# +**RISC-V Compliance Test Generator** : RISC-V CTG +################################################# + + +Latest documentation of riscv_ctg : `click here `_ + + + + + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg.egg-info/SOURCES.txt b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg.egg-info/SOURCES.txt new file mode 100644 index 000000000..939685b75 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg.egg-info/SOURCES.txt @@ -0,0 +1,31 @@ +LICENSE.incore +MANIFEST.in +README.rst +setup.cfg +setup.py +riscv_ctg/__init__.py +riscv_ctg/constants.py +riscv_ctg/cross_comb.py +riscv_ctg/csr_comb.py +riscv_ctg/ctg.py +riscv_ctg/dsp_function.py +riscv_ctg/function_generators.py +riscv_ctg/generator.py +riscv_ctg/helpers.py +riscv_ctg/log.py +riscv_ctg/main.py +riscv_ctg/requirements.txt +riscv_ctg/utils.py +riscv_ctg.egg-info/PKG-INFO +riscv_ctg.egg-info/SOURCES.txt +riscv_ctg.egg-info/dependency_links.txt +riscv_ctg.egg-info/entry_points.txt +riscv_ctg.egg-info/not-zip-safe +riscv_ctg.egg-info/requires.txt +riscv_ctg.egg-info/top_level.txt +riscv_ctg/data/fd.yaml +riscv_ctg/data/imc.yaml +riscv_ctg/data/template.yaml +riscv_ctg/env/arch_test.h +riscv_ctg/env/encoding.h +riscv_ctg/env/riscv-isac.code-workspace \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg.egg-info/dependency_links.txt b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg.egg-info/dependency_links.txt new file mode 100644 index 000000000..8b1378917 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg.egg-info/dependency_links.txt @@ -0,0 +1 @@ + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg.egg-info/entry_points.txt b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg.egg-info/entry_points.txt new file mode 100644 index 000000000..0aecdda14 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg.egg-info/entry_points.txt @@ -0,0 +1,3 @@ +[console_scripts] +riscv_ctg = riscv_ctg.main:cli + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg.egg-info/not-zip-safe b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg.egg-info/not-zip-safe new file mode 100644 index 000000000..8b1378917 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg.egg-info/not-zip-safe @@ -0,0 +1 @@ + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg.egg-info/requires.txt b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg.egg-info/requires.txt new file mode 100644 index 000000000..d5eed5c26 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg.egg-info/requires.txt @@ -0,0 +1,5 @@ +click +colorlog +python-constraint +riscv_isac>=0.14.0 +ruamel.yaml>=0.16.0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg.egg-info/top_level.txt b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg.egg-info/top_level.txt new file mode 100644 index 000000000..b5d255bde --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg.egg-info/top_level.txt @@ -0,0 +1,2 @@ +riscv_ctg +tests diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/__init__.py b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/__init__.py new file mode 100644 index 000000000..29adebcf3 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/__init__.py @@ -0,0 +1,7 @@ +# See LICENSE.incore for details + +"""Top-level package for RISC-V Compliance Test Generator.""" + +__author__ = """InCore Semiconductors Pvt Ltd""" +__email__ = 'incorebot@gmail.com' +__version__ = '0.12.2' diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/constants.py b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/constants.py new file mode 100644 index 000000000..3f3f80176 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/constants.py @@ -0,0 +1,334 @@ +# See LICENSE.incore for details + +import os +from math import * +from string import Template +from riscv_isac.fp_dataset import * + +root = os.path.abspath(os.path.dirname(__file__)) + +cwd = os.getcwd() +env = os.path.join(root,"env") + +default_regset = ['x0' ,'x1' ,'x2' ,'x3' ,'x4' ,'x5' ,'x6' ,'x7' ,'x8' ,'x9' + ,'x10' ,'x11' ,'x12' ,'x13' ,'x14' ,'x15' ,'x16' ,'x17' ,'x18' ,'x19' + ,'x20' ,'x21' ,'x22' ,'x23' ,'x24' ,'x25' ,'x26' ,'x27' ,'x28' ,'x29' + ,'x30' ,'x31'] +default_fregset = ['f0' ,'f1' ,'f2' ,'f3' ,'f4' ,'f5' ,'f6' ,'f7' ,'f8' ,'f9' + ,'f10' ,'f11' ,'f12' ,'f13' ,'f14' ,'f15' ,'f16' ,'f17' ,'f18' ,'f19' + ,'f20' ,'f21' ,'f22' ,'f23' ,'f24' ,'f25' ,'f26' ,'f27' ,'f28' ,'f29' + ,'f30' ,'f31'] +e_regset = ['x0' ,'x1' ,'x2' ,'x3' ,'x4' ,'x5' ,'x6' ,'x7' ,'x8' ,'x9' + ,'x10' ,'x11' ,'x12' ,'x13' ,'x14' ,'x15'] +default_regset_mx0 = ['x1' ,'x2' ,'x3' ,'x4' ,'x5' ,'x6' ,'x7' ,'x8' ,'x9' + ,'x10' ,'x11' ,'x12' ,'x13' ,'x14' ,'x15' ,'x16' ,'x17' ,'x18' ,'x19' + ,'x20' ,'x21' ,'x22' ,'x23' ,'x24' ,'x25' ,'x26' ,'x27' ,'x28' ,'x29' + ,'x30' ,'x31'] + +def sign_extend(value, bits): + sign_bit = 1 << (bits - 1) + return (value & (sign_bit - 1)) - (value & sign_bit) + +def twos(val,bits): + ''' + A function to generate the two's complement of a number which is of + arbitrary width + + :param val: the input which can be either a hexadecimal string or integer + :param bits: size of the input in terms of bits. + + :type val: Union[int, str] + :type bits: int + + :return: integer value in 2's complement representation + ''' + if isinstance(val,str): + if '0x' in val: + val = int(val,16) + else: + val = int(val,2) + if (val & (1 << (bits - 1))) != 0: + val = val - (1 << bits) + return val + +def gen_imm_dataset(bit_width): + ''' + Function to enumerate a dataset for immediate values: + - [0,2**bit_width] + + :param bit_width: Integer defining the size of the input + :type bit_width: int + :return: a list of integers + ''' + usign_val = (2**(bit_width)) + dataset = [] + for i in range(usign_val): + dataset.append(i) + return dataset + +def gen_sp_dataset(bit_width,sign=True): + ''' + Function generates a special dataset of interesting values: + - [3*1/3,3*2/3,5,5*1/5,5*2/5] + - sqrt (bit_width<<1) + - +/-1 variants of the above + + :param bit_width: Integer defining the size of the input + :param sign: Boolen value specifying whether the dataset should be interpreted as signed numbers or not. + :type sign: bool + :type bit_width: int + :return: a list of integers + ''' + if sign: + conv_func = lambda x: twos(x,bit_width) + sqrt_min = int(-sqrt(2**(bit_width-1))) + sqrt_max = int(sqrt((2**(bit_width-1)-1))) + else: + sqrt_min = 0 + sqrt_max = int(sqrt((2**bit_width)-1)) + conv_func = lambda x:(int(x,16) if '0x' in x else int(x,2)) if isinstance(x,str) else x + + dataset = [3, "0x"+"".join(["5"]*int(bit_width/4)), "0x"+"".join(["a"]*int(bit_width/4)), 5, "0x"+"".join(["3"]*int(bit_width/4)), "0x"+"".join(["6"]*int(bit_width/4))] + dataset = list(map(conv_func,dataset)) + [int(sqrt(abs(conv_func("0x8"+"".join(["0"]*int((bit_width/4)-1)))))*(-1 if sign else 1))] + [sqrt_min,sqrt_max] + return dataset + [x - 1 if x > 0 else 0 for x in dataset] + [x+1 for x in dataset] + +# def gen_fp_dataset(flen,instr,field): +# return (ibm_dataset(flen,instr,field)) # Dataset will be returned by isac + +def gen_sign_dataset(bit_width): + ''' + Function to generate the signed data set with datapoints from the following patterns. + - alternating ones + - alternating zeros + - walking ones + - walking zeros + - max val + - min val + - max val/2 + - min val/2 + - [-10,10] + + :param bit_width: integer defining the size of the input + :type bit_width: int + :return: a list of integers + ''' + rval_w0_base = ['1']*(bit_width-1)+['0'] + rval_w1_base = ['0']*(bit_width-1)+['1'] + data = [(-2**(bit_width-1)),int((-2**(bit_width-1))/2),0,(2**(bit_width-1)-1),int((2**(bit_width-1)-1)/2)] + list(range(-10,10)) + data += [twos(''.join(rval_w1_base[n:] + rval_w1_base[:n]),bit_width) for n in range(bit_width)] + data += [twos(''.join(rval_w0_base[n:] + rval_w0_base[:n]),bit_width) for n in range(bit_width)] + t1 =( '' if bit_width%2 == 0 else '1') + ''.join(['01']*int(bit_width/2)) + t2 =( '' if bit_width%2 == 0 else '0') + ''.join(['10']*int(bit_width/2)) + data += [twos(t1,bit_width),twos(t2,bit_width)] + return list(set(data)) + +def gen_usign_dataset(bit_width): + ''' + Function to generate the unsigned dataset + - alternating ones + - alternating zeros + - walking ones + - walking zeros + - max val + - min val + - max val/2 + - min val/2 + - [0,20] + + :param bit_width: integer defining the size of the input + :type bit_width: int + :return: a list of integers + ''' + rval_w0_base = ['1']*(bit_width-1)+['0'] + rval_w1_base = ['0']*(bit_width-1)+['1'] + data = [0,((2**bit_width)-1),int(((2**bit_width)-1)/2)] + list(range(0,20)) + data += [int(''.join(rval_w1_base[n:] + rval_w1_base[:n]),2) for n in range(bit_width)] + data += [int(''.join(rval_w0_base[n:] + rval_w0_base[:n]),2) for n in range(bit_width)] + t1 =( '' if bit_width%2 == 0 else '1') + ''.join(['01']*int(bit_width/2)) + t2 =( '' if bit_width%2 == 0 else '0') + ''.join(['10']*int(bit_width/2)) + data += [int(t1,2),int(t2,2)] + return list(set(data)) + +def zerotoxlen(bit_width): + vals = [] + for i in range(bit_width): + vals.append(i) + return vals + +def gen_bitmanip_dataset(bit_width,sign=True): + ''' + Function generates a special dataset of interesting values for bitmanip: + 0x0, 0x3, 0xc, 0x5,0xa,0x6,0x9 each of the pattern exenteding for bit_width + for 32 bit + 0x33333333,0xcccccccc,0x55555555, 0xaaaaaaaaa,0x66666666,0x99999999 + for 64 bit + 0x3333333333333333,0xcccccccccccccccc,0x5555555555555555, 0xaaaaaaaaaaaaaaaaa, + 0x6666666666666666,0x9999999999999999 + - +1 and -1 variants of the above pattern + + :param bit_width: Integer defining the size of the input + :param sign: Boolen value specifying whether the dataset should be interpreted as signed numbers or not. + :type sign: bool + :type bit_width: int + :return: a list of integers + ''' + if sign: + conv_func = lambda x: twos(x,bit_width) + else: + conv_func = lambda x:(int(x,16) if '0x' in x else int(x,2)) if isinstance(x,str) else x + +# dataset for 0x5, 0xa, 0x3, 0xc, 0x6, 0x9 patterns + + dataset = ["0x"+"".join(["5"]*int(bit_width/4)), "0x"+"".join(["a"]*int(bit_width/4)), "0x"+"".join(["3"]*int(bit_width/4)), "0x"+"".join(["6"]*int(bit_width/4)),"0x"+"".join(["9"]*int(bit_width/4)),"0x"+"".join(["c"]*int(bit_width/4))] + dataset = list(map(conv_func,dataset)) + +# dataset0 is for 0,1 and 0xf pattern. 0xf pattern is added instead of -1 so that code for checking coverpoints in coverage.py +# is kept simple. + + dataset0 = [0,1,"0x"+"".join(["f"]*int(bit_width/4))] + dataset0 = list(map(conv_func,dataset0)) + +# increment each value in dataset, increment each value in dataset, add them to the dataset + return dataset + [x - 1 for x in dataset] + [x+1 for x in dataset] + dataset0 + +template_fnames = ["template.yaml","imc.yaml","fd.yaml"] + +template_files = [os.path.join(root,"data/"+f) for f in template_fnames] + +usage = Template(''' +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : $version +// timestamp : $time +// usage : riscv_ctg \\ +// -- cgf $cgf \\ +// -- xlen $xlen $randomize \\ +// ----------- +//''') + +copyright_string = ''' +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +//''' + +comment_template = ''' +// This assembly file tests the $opcode instruction of the RISC-V $extension extension for the $label covergroup. +// ''' + +cross_comment_template = ''' +// This assembly file is used for the test of cross-combination coverpoint described in $label covergroup. +''' + +csr_comb_comment_template = ''' +// This assembly file is used for the test of CSR-combination coverpoint described in $label covergroup. +''' + +test_template = Template(copyright_string + comment_template+''' +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("$isa") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +$test + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +$data +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +$sig + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END +''') + +cross_test_template = Template(copyright_string + cross_comment_template+''' +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("$isa") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +$test + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +$data +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +$sig +RVMODEL_DATA_END +''') + +csr_comb_test_template = Template(copyright_string + csr_comb_comment_template + ''' +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("$isa") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +$test + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +$data +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +$sig +RVMODEL_DATA_END +''') + +case_template = Template(''' +RVTEST_CASE($num,"//$cond;def TEST_CASE_1=True;",$cov_label) +''') + +part_template = Template(''' +#ifdef TEST_CASE_1 +$case_str +$code +#endif +''') + +signode_template = Template(''' +$label: + .fill $n*$sz,4,0xdeadbeef +''') + +csr_reg_write_to_field_template = Template(''' +WRITE_TO_CSR_FIELD_W_MASK($csr_reg, $restore_reg, $temp_reg1, $temp_reg2, $mask, $val) +''') + +csr_reg_read_and_sig_upd_template = Template(''' +READ_CSR_REG_AND_UPD_SIG($csr_reg, $dest_reg, $offset, $base_reg) +''') + +csr_reg_restore_template = Template(''' +RESTORE_CSR_REG($csr_reg, $restore_reg) +''') diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/cross_comb.py b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/cross_comb.py new file mode 100644 index 000000000..25112a264 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/cross_comb.py @@ -0,0 +1,501 @@ +# See LICENSE.incore for details +import random +from constraint import * + +import riscv_isac.utils as isac_utils +from riscv_ctg import constants + +import riscv_ctg.utils as utils +import riscv_ctg.constants as const +from riscv_ctg.constants import * +from riscv_ctg.log import logger +from riscv_ctg.__init__ import __version__ +from riscv_ctg.generator import OPS +from riscv_ctg.dsp_function import * + +INSTR_FORMAT = { + 'rformat' : '$instr $rd, $rs1, $rs2', + 'iformat' : '$instr $rd, $rs1, SEXT_IMM($imm_val)', + 'sformat' : '$instr $rs2, $imm_val($rs1)', + 'bsformat' : '$instr $rd, $rs2, $imm_val', + 'bformat' : '$instr $rs1, $rs2, $label', + 'uformat' : '$instr $rd, $imm_val', + 'jformat' : '$instr $rd, $imm', + 'crformat' : '$instr $rs1 $rs2', + 'cmvformat' : '$instr $rd, $rs2', + 'ciformat' : '$instr $rd, $imm_val', + 'cssformat' : '$instr $rs2, $imm_val($rs1)', + 'ciwformat' : '$instr $rd, x2, $imm_val', + 'clformat' : '$instr $rd, $imm_val($rs1)', + 'csformat' : '$instr $rs2, $imm_val($rs2)', + 'caformat' : '$instr', + 'cbformat' : '$instr', + 'cjformat' : '$instr', + 'kformat' : '$instr', + 'frformat' : '$instr $rd, $rs1, $rs2', + 'fsrformat' : '$instr $rd, $rs1', + 'fr4format' : '$instr $rd, $rs1, $rs2, $rs3', + 'pbrrformat' : '$instr $rd, $rs1, $rs2', + 'phrrformat' : '$instr $rd, $rs1, $rs2', + 'pbrformat' : '$instr $rd, $rs1', + 'phrformat' : '$instr $rd, $rs1', + 'pbriformat' : '$instr $rd, $rs1, SEXT_IMM($imm_val)' , + 'phriformat' : '$instr $rd, $rs1, SEXT_IMM($imm_val)', + 'psbrrformat' : '$instr $rd, $rs1, $rs2', + 'pshrrformat' : '$instr $rd, $rs1, $rs2', + 'pwrrformat' : '$instr $rd, $rs1, $rs2', + 'pwriformat' : '$instr $rd, $rs1, SEXT_IMM($imm_val)' , + 'pwrformat' : '$instr $rd, $rs1', + 'pswrrformat' : '$instr $rd, $rs1, $rs2', + 'pwhrrformat' : '$instr $rd, $rs1, $rs2', + 'pphrrformat' : '$instr $rd, $rs1, $rs2', + 'ppbrrformat' : '$instr $rd, $rs1, $rs2', + 'prrformat' : '$instr ', + 'prrrformat' : '$instr', + 'dcasrformat' : '$instr ' +} +'''Dictionary to store instruction formats''' + +REG_INIT = { +'x1' : 'LI (x1, (0xFEEDBEADFEEDBEAD & MASK))', +'x2' : 'LI (x2, (0xFF76DF56FF76DF56 & MASK))', +'x3' : 'LI (x3, (0x7FBB6FAB7FBB6FAB & MASK))', +'x4' : 'LI (x4, (0xBFDDB7D5BFDDB7D5 & MASK))', +'x5' : 'LI (x5, (0xAB7FFB6FAB7FBB6F & MASK))', +'x6' : 'LI (x6, (0x6FAB71BB6F7B7FBB & MASK))', +'x7' : 'LI (x7, (0xB7FBB6FAB7FBB6FA & MASK))', +'x8' : 'LI (x8, (0x5BFDDB7D5BFDDB7D & MASK))', +'x9' : 'LI (x9, (0xADFEEDBEADFEEDBE & MASK))', +'x10' : 'LI (x10, (0x56FF76DF56FF76DF & MASK))', +'x11' : 'LI (x11, (0xAB7FBB6FAB7FBB6F & MASK))', +'x12' : 'LI (x12, (0xD5BFDDB7D5BFDDB7 & MASK))', +'x13' : 'LI (x13, (0xEADFEEDBEADFEEDB & MASK))', +'x14' : 'LI (x14, (0xF56FF76DF56FF76D & MASK))', +'x15' : 'LI (x15, (0xFAB7FBB6FAB7FBB6 & MASK))', +'x16' : 'LI (x16, (0x7D5BFDDB7D5BFDDB & MASK))', +'x17' : 'LI (x17, (0xBEADFEEDBEADFEED & MASK))', +'x18' : 'LI (x18, (0xDF56FF76DF56FF76 & MASK))', +'x19' : 'LI (x19, (0x6FAB7FBB6FAB7FBB & MASK))', +'x20' : 'LI (x20, (0xB7D5BFDDB7D5BFDD & MASK))', +'x21' : 'LI (x21, (0xDBEADFEEDBEADFEE & MASK))', +'x22' : 'LI (x22, (0x6DF56FF76DF56FF7 & MASK))', +'x23' : 'LI (x23, (0xB6FAB7FBB6FAB7FB & MASK))', +'x24' : 'LI (x24, (0xDB7D5BFDDB7D5BFD & MASK))', +'x25' : 'LI (x25, (0xEDBEADFEEDBEADFE & MASK))', +'x26' : 'LI (x26, (0x76DF56FF76DF56FF & MASK))', +'x27' : 'LI (x27, (0xBB6FAB7FBB6FAB7F & MASK))', +'x28' : 'LI (x28, (0xDDB7D5BFDDB7D5BF & MASK))', +'x29' : 'LI (x29, (0xEEDBEADFEEDBEADF & MASK))', +'x30' : 'LI (x30, (0xF76DF56FF76DF56F & MASK))', +'x31' : 'LI (x31, (0xFBB6FAB7FBB6FAB7 & MASK))', +} +''' Initial values for general purpose and floating point registers''' + +class cross(): + ''' + A cross class to genereate RISC-V assembly tests for cross-combination coverpoints. + ''' + + def __init__(self, base_isa_str, xlen_in, randomize, label): + global xlen + global flen + global base_isa + + # Template dictionary + self.OP_TEMPLATE = utils.load_yamls(const.template_files) + + xlen = xlen_in + base_isa = base_isa_str + + self.randomize = randomize + self.label = label + + # Flag if floating point instructions are chosen + self.if_fp = False + + def cross_comb(self, cgf_node): + ''' + This function finds solution for various cross-combinations defined by the coverpoints + in the CGF under the `cross_comb` node of the covergroup. + ''' + logger.debug('Generating CrossComb') + full_solution = [] + + if 'cross_comb' in cgf_node: + cross_comb = set(cgf_node['cross_comb']) + else: + return + + isa_set = [] + + # Generate register file and variables + reg_file = const.default_regset + for each in reg_file: + exec(f"{each} = '{each}'") + + dntcare_instrs = isac_utils.import_instr_alias(base_isa + '_arith') + isac_utils.import_instr_alias(base_isa + '_shift') + + # This function retrieves available operands in a string + def get_oprs(opr_str): + opr_lst = [] + if opr_str.find('rd') != -1: + opr_lst.append('rd') + if opr_str.find('rs1') != -1: + opr_lst.append('rs1') + if opr_str.find('rs2') != -1: + opr_lst.append('rs2') + if opr_str.find('rs3') != -1: + opr_lst.append('rs3') + + return opr_lst + + # Add conditions mentioned in the condition list in the cross-comb coverpoint + def add_cond(local_var): + def eval_conds(*oprs_lst): + i = 0 + for opr in oprs: + exec(opr + "='" + oprs_lst[i] + "'", local_var) + i = i + 1 + return eval(cond, locals(), local_var) + return eval_conds + + solution = [] + for each in cross_comb: + + solution = [] + + # Parse cross-comb coverpoint + parts = each.split('::') + + data = parts[0].replace(' ', '')[1:-1].split(':') + assgn_lst = parts[1].replace(' ', '')[1:-1].split(':') + cond_lst = parts[2].lstrip().rstrip()[1:-1].split(':') + + # Initialize CSP + problem = Problem() + + for i in range(len(data)): + if data[i] == '?': + # When instruction is not specified, + # - Gather conditions and assigngments if any and list requisite operands + # - Choose instruction from base instruction set based on operands + # - Based on conditions, choose operand values. Choose immediate value if required + # - Evaluate assignments + + # Get corresponding conditions and accordingly chose instruction + cond = cond_lst[i] + assgn = assgn_lst[i] + + if cond.find('?') != -1: # Don't care condition + + # Check variables in assignment list and generate required operand list + opr_lst = get_oprs(assgn) + + # Get possible instructions based on the operand list + problem.reset() + problem.addVariable('i', dntcare_instrs) + problem.addConstraint(lambda i: all(item in OPS[self.OP_TEMPLATE[i]['formattype']] for item in opr_lst)) + instrs_sol = problem.getSolutions() + + instrs_sol = [list(each.items())[0][1] for each in instrs_sol] + + else: # If condition is specified + + opr_lst = [] + + # Extract required operands from condition list + opr_lst += get_oprs(cond) + + # Extract required operands from assignment list + opr_lst += get_oprs(assgn) + + # Remove redundant operands + opr_lst = list(set(opr_lst)) + + # Get possible instructions + problem.reset() + problem.addVariable('i', dntcare_instrs) + problem.addConstraint(lambda i: all(item in OPS[self.OP_TEMPLATE[i]['formattype']] for item in opr_lst)) + instrs_sol = problem.getSolutions() + + instrs_sol = [list(each.items())[0][1] for each in instrs_sol] + + # Randomly choose an instruction + instr = random.choice(instrs_sol) + isa_set += (self.OP_TEMPLATE[instr]['isa']) + + # Choose operand values + formattype = self.OP_TEMPLATE[instr]['formattype'] + oprs = OPS[formattype] + instr_template = self.OP_TEMPLATE[instr] + + # Choose register values + problem.reset() + for opr in oprs: + opr_dom = instr_template[opr + '_op_data'] + problem.addVariable(opr, eval(opr_dom)) + + # Since rd = x0 is a trivial operation, it has to be excluded + if 'rd' in oprs: + # exclude zeros + def exc_rd_zero(*oprs_lst): + pos = oprs.index('rd') + if oprs_lst[pos] == 'x0': + return False + return True + + problem.addConstraint(exc_rd_zero, oprs) + + # Add additional contraints if any + if cond.find('?') != -1: + opr_sols = problem.getSolutions() + else: + local_vars = locals() + problem.addConstraint(add_cond(local_vars), oprs) + opr_sols = problem.getSolutions() + + opr_vals = random.choice(opr_sols) + + # Assign operand values to operands + for opr, val in opr_vals.items(): + exec(opr + "='" + val + "'") + + # Generate immediate value if required + if 'imm_val_data' in instr_template: + imm_val = eval(instr_template['imm_val_data']) + opr_vals['imm_val'] = random.choice(imm_val) + + # Get assignments if any and execute them + if assgn_lst[i] != '?': + assgns = assgn_lst[i].split(';') + for each in assgns: + exec(each) + + # Set floating point flag if instruction belongs to F or D extension + if instr[0] == 'f' and instr != 'fence': + self.if_fp = True + + opr_vals['instr'] = instr + solution += [opr_vals] + + else: + # When instruction(s)/alias is specified, + # - If an instruction is specified, operands are directly extracted and assigned values according to conditions + # - If a tuple of instructions is specified, one of the instruction is chosen at random + # - If an alias is specified, the alias is already substituted by its equivalent tuple of instructions at this point + # through expand_cgf method. + # - Immediate values are generated if required + # - Assignments are evaluated + cond = cond_lst[i] + assgn = assgn_lst[i] + + # Gather required operands + opr_lst = get_oprs(cond) + opr_lst += get_oprs(assgn) + + opr_lst = list(set(opr_lst)) + + if data[i] in self.OP_TEMPLATE: # If single instruction + instr = data[i] + else: + if data[i].find('(') != -1: # If data is a tuple of instructions + instrs_sol = data[i][1:-1].split(',') + instr = random.choice(instrs_sol) + else: + logger.error('Invalid instruction/alias in cross_comb: ' + data[i]) + + # Gather operands + formattype = self.OP_TEMPLATE[instr]['formattype'] + oprs = OPS[formattype] + instr_template = self.OP_TEMPLATE[instr] + + problem.reset() + for opr in oprs: + opr_dom = instr_template[opr + '_op_data'] + problem.addVariable(opr, eval(opr_dom)) + + # Since rd = x0 is a trivial operation, it has to be excluded + if 'rd' in oprs: + # exclude zeros + def exc_rd_zero(*oprs_lst): + pos = oprs.index('rd') + if oprs_lst[pos] == 'x0': + return False + return True + + problem.addConstraint(exc_rd_zero, oprs) + + # Assign values to operands + if cond.find('?') != -1: + opr_sols = problem.getSolutions() + else: + local_vars = locals() + problem.addConstraint(add_cond(local_vars), oprs) + opr_sols = problem.getSolutions() + + # Get operand values + opr_vals = random.choice(opr_sols) + + # Assign operand values to operands + for opr, val in opr_vals.items(): + exec(opr + "='" + val + "'") + + # Generate immediate value if required + if 'imm_val_data' in instr_template: + imm_val = eval(instr_template['imm_val_data']) + opr_vals['imm_val'] = random.choice(imm_val) + + # Execute assignments + # Get assignments if any and execute them + if assgn_lst[i] != '?': + assgns = assgn_lst[i].split(';') + for each in assgns: + exec(each) + + isa_set += (self.OP_TEMPLATE[instr]['isa']) + + # Set floating point flag if instruction belongs to F or D extension + if instr[0] == 'f' and instr != 'fence': + self.if_fp = True + + opr_vals['instr'] = instr + solution += [opr_vals] + + full_solution += [solution] + + self.isa = list(set(isa_set)) + return full_solution + + def swreg(cross_comb_instrs): + ''' + This function generates the register which can be used as a signature pointer for each instruction. + It also generates the register which stores the value used by floating point registers + ''' + + global base_isa + + op_vals = {'x0'} + + for instr_dict in cross_comb_instrs: + for key, val in instr_dict.items(): + if key != 'instr' and key != 'imm_val': + op_vals.add(val) + + swreg_sol = set(['x'+str(x) for x in range(0,32 if 'e' not in base_isa else 16)]) - op_vals + + sreg = random.choice(list(swreg_sol)) + freg_Sol = swreg_sol - set(sreg) + freg = random.choice(list(freg_Sol)) + return (sreg, freg) + + def get_reginit_str(cross_comb_instrs, freg): + ''' + This function fetches the register initlialization macro to initialize + used destination instructions after the cross-coverpoint instruction sequence + generation + + Input argument: + - cross_comb_instrs type: list(dict()) Holds info of various instructions in the sequence + + Return: + - List of initialization strings + ''' + + reg_init_lst = set() + + for instr_dict in cross_comb_instrs: + if 'rd' in instr_dict: + rd_val = instr_dict['rd'] + if rd_val[0] == 'f': + freg_init = REG_INIT[freg].replace('& MASK', '>> FREGWIDTH') + reg_init_lst.add(freg_init + '\n' + 'FLREG ' + rd_val + ', 0(' + freg + ')') + else: + reg_init_lst.add(REG_INIT[instr_dict['rd']]) + return list(reg_init_lst) + + def write_test(self, fprefix, cgf_node, usage_str, cov_label, full_solution): + ''' + Generate instruction sequence and write them into an assembly file + + #TODO Initialization of floating point registers + #TODO Handling loads/stores and branches in the sequence + ''' + global base_isa + + code = '\n' + data = [".align 4","rvtest_data:",".word 0xbabecafe", \ + ".word 0xabecafeb", ".word 0xbecafeba", ".word 0xecafebab"] + sig = [''] + sreg_dict = dict() + + # If floating point instructions are available + if self.if_fp: + code += "RVTEST_FP_ENABLE()" + + # Generate ISA and extension string + extension = "" + rvxlen = "RV"+str(xlen) + op_node_isa = ",".join([rvxlen + isa for isa in self.isa]) + op_node_isa = op_node_isa.replace("I","E") if 'e' in base_isa else op_node_isa + extension = op_node_isa.replace('I',"").replace('E',"") + + # Handle solutions related to each cross combination coverpoint + for cross_sol in full_solution: + + # Designate signature update register + (sreg, freg) = cross.swreg(cross_sol) + + # Designate count of sreg for signature label generation + if sreg not in sreg_dict: + sreg_dict[sreg] = 0 + else: + count = sreg_dict[sreg] + 1 + sreg_dict[sreg] = count + + sig_label = "signature_" + sreg + "_" + str(sreg_dict[sreg]) + code = code + "\nRVTEST_SIGBASE(" + sreg + ", "+ sig_label + ")\n\n" + + rd_lst = set() + # Generate instruction corresponding to each instruction dictionary + # Append signature update statements to store rd value after each instruction + code += '// Cross-combination test sequence\n' + for each in cross_sol: + + if 'rd' in each: + rd_lst.add(each['rd']) + + instr_str_format = Template(INSTR_FORMAT[self.OP_TEMPLATE[each['instr']]['formattype']]) + instr_str = instr_str_format.substitute(each) + code = code + instr_str + '\n' + + # Append .fill assembly directives to initialize signature regions + sig.append(signode_template.safe_substitute(label = sig_label, n = len(rd_lst))) + + offset = 0 + code += '\n// Store destination register values in the test signature region\n' + # Add signature update statement(s) for unique number of rds + for rd in rd_lst: + if rd[0] == 'f': + sig_upd = f'RVTEST_SIGUPD_F({sreg}, {rd}, {offset})' + else: + sig_upd = f'RVTEST_SIGUPD({sreg}, {rd}, {offset})' + offset = offset + int(xlen/8) + code = code + sig_upd + '\n' + + # Initialize registers for next cross-comb coverpoint + code = code + '\n// Initialize used registers\n' + '\n'.join(cross.get_reginit_str(cross_sol, freg)) + '\n' + + case_str = ''.join([case_template.safe_substitute(xlen = xlen,num = i, cond = cond, cov_label = cov_label) for i, cond in enumerate(cgf_node['config'])]) + test = part_template.safe_substitute(case_str = case_str, code = code) + + # Write test to file + with open(fprefix + '_cross-comb.S', 'w') as fp: + fp.write(usage_str + const.cross_test_template.safe_substitute(opcode = cov_label, + isa = op_node_isa, + test = test, + data = '\n'.join(data), + sig = '\n'.join(sig), + label = cov_label, + extension = extension + ) + ) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/csr_comb.py b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/csr_comb.py new file mode 100644 index 000000000..ef75d388c --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/csr_comb.py @@ -0,0 +1,425 @@ +# See LICENSE.incore for details +import re +import functools + +from riscv_ctg.log import logger +from riscv_ctg.constants import * + +import tokenize as tkn +from io import BytesIO + +OPS = ['not', 'and', 'or'] +OP_PRIORITY = { + 'not': -1, + 'and': -2, + 'or' : -3, +} + +CSR_REGS = ['mvendorid', 'marchid', 'mimpid', 'mhartid', 'mstatus', 'misa', 'medeleg', 'mideleg', 'mie', 'mtvec', 'mcounteren', 'mscratch', 'mepc', 'mcause', 'mtval', 'mip', 'pmpcfg0', 'pmpcfg1', 'pmpcfg2', 'pmpcfg3', 'mcycle', 'minstret', 'mcycleh', 'minstreth', 'mcountinhibit', 'tselect', 'tdata1', 'tdata2', 'tdata3', 'dcsr', 'dpc', 'dscratch0', 'dscratch1', 'sstatus', 'sedeleg', 'sideleg', 'sie', 'stvec', 'scounteren', 'sscratch', 'sepc', 'scause', 'stval', 'sip', 'satp', 'vxsat', 'fflags', 'frm', 'fcsr', 'CSR_SRMCFG'] +csr_regs_capture_group = f'({"|".join(CSR_REGS)})' +csr_regs_with_modifiers_capture_group = r'(write|old) *\( *"' + csr_regs_capture_group + r'" *\)' + +csr_comb_covpt_regex_strings = [ + csr_regs_capture_group + r' *& *([^ ].*)== *([^ ].*)', # regular + r'\( *' + csr_regs_capture_group + r' *(>>|<<) *([^ ].*)\) *& *([^ ].*)== *([^ ].*)', # with bitshifts only + csr_regs_with_modifiers_capture_group + r' *& *([^ ].*)== *([^ ].*)', # with modifiers only + r'\( *' + csr_regs_with_modifiers_capture_group + r' *(>>|<<) *([^ ].*)\) *& *([^ ].*)== *([^ ].*)', # with bitshifts and modifiers +] + +csr_comb_covpt_regexes = [re.compile(regex_string) for regex_string in csr_comb_covpt_regex_strings] + +def tokenize(s): + result = [] + g = tkn.tokenize(BytesIO(s.encode('utf-8')).readline) + for tok_num, tok_val, _, _, _ in g: + if tok_num in [tkn.ENCODING, tkn.NEWLINE, tkn.ENDMARKER]: + continue + result.append((tok_num, tok_val)) + return result + +def untokenize(tokens): + return tkn.untokenize(tokens) + +# a dummy class acting as an interface for boolean expressions +class BooleanExpression: + def SAT(self): + # returns the complete list of solutions for this expression's satisfiability + # a single solution is a tuple of two lists: + # - the literals in the first list must evaluate to true + # - the literals in the second list must evaluate to false + raise Exception("not implemented") + + def __str__(self): + raise Exception("not implemented") + +class NotExpression(BooleanExpression): + def __init__(self, operand): + self.operand = operand + + def SAT(self): + return [(operand_f, operand_t) for operand_t, operand_f in self.operand.SAT()] + + def __str__(self): + return f'not ({str(self.operand)})' + +class AndExpression(BooleanExpression): + def __init__(self, lhs, rhs): + self.lhs = lhs + self.rhs = rhs + + def SAT(self): + return [(lhs_t + rhs_t, lhs_f + rhs_f) for lhs_t, lhs_f in self.lhs.SAT() for rhs_t, rhs_f in self.rhs.SAT()] + + def __str__(self): + return f'({str(self.lhs)}) and ({str(self.rhs)})' + +class OrExpression(BooleanExpression): + def __init__(self, lhs, rhs): + self.lhs = lhs + self.rhs = rhs + + def SAT(self): + lhs_SAT = self.lhs.SAT() + rhs_SAT = self.rhs.SAT() + + sols = [] + for lhs_t, lhs_f in lhs_SAT: + for rhs_t, rhs_f in rhs_SAT: + sols.extend([ + (lhs_t + rhs_f, lhs_f + rhs_t), + (lhs_f + rhs_t, lhs_t + rhs_f), + (lhs_t + rhs_t, lhs_f + rhs_f), + ]) + + return sols + + def __str__(self): + return f'({str(self.lhs)}) or ({str(self.rhs)})' + +class LiteralExpression(BooleanExpression): + def __init__(self, val): + self.val = val + + def SAT(self): + return [([self.val], [])] + + def __str__(self): + return str(self.val) + +# This function parses coverpoints for the CSR-combination node +# The coverpoints are assumed of the form: multiple condition clauses combined with and's and or's +# A coverpoint condition clause is assumed of the form: 'csr_reg & mask == val' or '(csr_reg >> shift) & mask == val' +def parse_csr_covpt(covpt): + toks = tokenize(covpt) + + bracket_depth = 0 + clause_depths = [] + for tok_num, tok_val in toks: + if tok_val == '(': + bracket_depth += 1 + elif tok_val == ')': + bracket_depth -= 1 + elif tok_val == '==': + clause_depths.append(bracket_depth) + + bracket_depth = 0 + operator_stack = [] + clause_stack = [] + clause_index = 0 + current_clause = [] + current_clause_depth = clause_depths[clause_index] + for tok_num, tok_val in toks: + if tok_val == '(': + bracket_depth += 1 + + if bracket_depth > current_clause_depth: + current_clause.append((tok_num, tok_val)) + else: + operator_stack.append('(') + elif tok_val == ')': + bracket_depth -= 1 + + if current_clause: + if bracket_depth < current_clause_depth: + clause_stack.append(LiteralExpression(untokenize(current_clause))) + while operator_stack[-1] != '(': + op = operator_stack.pop() + if op == 'not': + operand = clause_stack.pop() + clause_stack.append(NotExpression(operand)) + else: + rhs = clause_stack.pop() + lhs = clause_stack.pop() + clause_stack.append(AndExpression(lhs, rhs) if op == 'and' else OrExpression(lhs, rhs)) + operator_stack.pop() + + current_clause = [] + clause_index += 1 + if (clause_index >= len(clause_depths)): + break + current_clause_depth = clause_depths[clause_index] + else: + current_clause.append((tok_num, tok_val)) + else: + while operator_stack[-1] != '(': + op = operator_stack.pop() + if op == 'not': + operand = clause_stack.pop() + clause_stack.append(NotExpression(operand)) + else: + rhs = clause_stack.pop() + lhs = clause_stack.pop() + clause_stack.append(AndExpression(lhs, rhs) if op == 'and' else OrExpression(lhs, rhs)) + operator_stack.pop() + elif tok_val in OPS: + if current_clause: + clause_stack.append(LiteralExpression(untokenize(current_clause))) + current_clause = [] + clause_index += 1 + current_clause_depth = clause_depths[clause_index] + + # prioritize not over and over or + while len(operator_stack) > 0 and operator_stack[-1] in OPS and OP_PRIORITY[operator_stack[-1]] > OP_PRIORITY[tok_val]: + op = operator_stack.pop() + if op == 'not': + operand = clause_stack.pop() + clause_stack.append(NotExpression(operand)) + else: + rhs = clause_stack.pop() + lhs = clause_stack.pop() + clause_stack.append(AndExpression(lhs, rhs) if op == 'and' else OrExpression(lhs, rhs)) + + operator_stack.append(tok_val) + else: + current_clause.append((tok_num, tok_val)) + + if current_clause: + clause_stack.append(LiteralExpression(untokenize(current_clause))) + + while len(operator_stack) > 0: + op = operator_stack.pop() + if op == 'not': + operand = clause_stack.pop() + clause_stack.append(NotExpression(operand)) + else: + rhs = clause_stack.pop() + lhs = clause_stack.pop() + clause_stack.append(AndExpression(lhs, rhs) if op == 'and' else OrExpression(lhs, rhs)) + + bool_expr = clause_stack.pop() + return bool_expr + +# This function extracts the csr register, the field mask, the field value and the csr register modifier (if present) from the coverpoint clause +# The coverpoint clause is assumed of the format: 'csr_reg & mask == val' or '(csr_reg >> shift) & mask == val' +# Modifiers `old()` and `write()` are also allowed on the `csr_reg`s. Example: `old("csr_reg") & mask == val` +# csr_reg must be a valid csr register; mask and val are allowed to be valid python expressions +def get_csr_mask_val_modifier(clause, instr_dict={}): + clause = clause.strip() + for i, regex in enumerate(csr_comb_covpt_regexes): + regex_match = regex.match(clause) + if regex_match is not None: + if i == 0: # regular covpt + csr_reg, mask_expr, val_expr = regex_match.groups() + mask = eval(mask_expr, {}, instr_dict) + val = eval(val_expr, {}, instr_dict) + return csr_reg, mask, val, None + elif i == 1: # with bitshifts only + csr_reg, shift_op, shift_expr, mask_expr, val_expr = regex_match.groups() + shift = eval(shift_expr, {}, instr_dict) + mask = eval(mask_expr, {}, instr_dict) + val = eval(val_expr, {}, instr_dict) + if shift_op == '>>': + mask = mask << shift + val = val << shift + else: + mask = mask >> shift + val = val >> shift + return csr_reg, mask, val, None + elif i == 2: # with modifiers only + mod, csr_reg, mask_expr, val_expr = regex_match.groups() + mask = eval(mask_expr, {}, instr_dict) + val = eval(val_expr, {}, instr_dict) + return csr_reg, mask, val, mod + elif i == 3: # with both modifiers and bitshifts + mod, csr_reg, shift_op, shift_expr, mask_expr, val_expr = regex_match.groups() + shift = eval(shift_expr, {}, instr_dict) + mask = eval(mask_expr, {}, instr_dict) + val = eval(val_expr, {}, instr_dict) + if shift_op == '>>': + mask = mask << shift + val = val << shift + else: + mask = mask >> shift + val = val >> shift + return csr_reg, mask, val, mod + return None, None, None, None + +class GeneratorCSRComb(): + ''' + A class to generate RISC-V assembly tests for CSR-combination coverpoints. + ''' + + def __init__(self, base_isa, xlen, randomize): + self.base_isa = base_isa + "_Zicsr" + self.xlen = xlen + self.randomize = randomize + + def csr_comb(self, cgf_node): + logger.debug('Generating tests for csr_comb') + if 'csr_comb' in cgf_node: + csr_comb = set(cgf_node['csr_comb']) + else: + return + + temp_regs = ['x30', 'x31'] + dest_reg = 'x29' + + instr_dict = [] + offset = 0 + + for covpt in csr_comb: + try: + bool_expr = parse_csr_covpt(covpt) + sols = bool_expr.SAT() + except: + logger.error(f'Invalid csr_comb coverpoint: {covpt}') + continue + + for sol, _ in sols: + reg_mask_val_mod_dict = {} # maps a csr_reg to the 6-tuple [mask, val, write_mask, write_val, old_mask, old_val] + reg_with_mod = None + for clause in sol: + csr_reg, mask, val, mod = get_csr_mask_val_modifier(clause, {'xlen': self.xlen}) + + if csr_reg is None: + logger.error(f'Skipping invalid csr_comb coverpoint condition clause: {clause}') + continue + if mod is not None: + if reg_with_mod is None: reg_with_mod = csr_reg + elif reg_with_mod != csr_reg: + logger.error(f'Skipping invalid csr_comb solution with modifiers on more than one registers for the coverpoint: {covpt}') + continue + + if not csr_reg in reg_mask_val_mod_dict: + if mod == 'old': + reg_mask_val_mod_dict[csr_reg] = [0, 0, 0, 0, mask, val] + elif mod == 'write': + reg_mask_val_mod_dict[csr_reg] = [0, 0, mask, val, 0, 0] + else: + reg_mask_val_mod_dict[csr_reg] = [mask, val, 0, 0, 0, 0] + else: + if mod == 'old': + reg_mask_val_mod_dict[csr_reg][4] |= mask + reg_mask_val_mod_dict[csr_reg][5] |= val + elif mod == 'write': + reg_mask_val_mod_dict[csr_reg][2] |= mask + reg_mask_val_mod_dict[csr_reg][3] |= val + else: + reg_mask_val_mod_dict[csr_reg][0] |= mask + reg_mask_val_mod_dict[csr_reg][1] |= val + + reg_mask_val_arr = list(reg_mask_val_mod_dict.items()) + reg_mask_val_arr.sort(key=functools.cmp_to_key(lambda x, y: 1 if x[0] == reg_with_mod else -1)) # put the register with modifier at the end + + instr_dict_csr_writes = [] + instr_dict_csr_restores = [] + uniq_csr_regs = [] + restore_reg = 1 + for csr_reg, mask_val in reg_mask_val_arr: + mask, val, write_mask, write_val, old_mask, old_val = mask_val + if old_mask != 0: + instr_dict_csr_writes.append({ + 'csr_reg': csr_reg, 'mask': hex(old_mask), 'val': hex(old_val), 'restore_reg': f'x{restore_reg}', + 'temp_reg1': temp_regs[0], 'temp_reg2': temp_regs[1] + }) + instr_dict_csr_restores.append({ + 'csr_reg': csr_reg, 'restore_reg': f'x{restore_reg}' + }) + restore_reg += 1 + + if write_mask != 0: + instr_dict_csr_writes.append({ + 'csr_reg': csr_reg, 'mask': hex(write_mask), 'val': hex(write_val), 'restore_reg': f'x{restore_reg}', + 'temp_reg1': temp_regs[0], 'temp_reg2': temp_regs[1] + }) + instr_dict_csr_restores.append({ + 'csr_reg': csr_reg, 'restore_reg': f'x{restore_reg}' + }) + restore_reg += 1 + elif mask != 0: + instr_dict_csr_writes.append({ + 'csr_reg': csr_reg, 'mask': hex(mask), 'val': hex(val), 'restore_reg': f'x{restore_reg}', + 'temp_reg1': temp_regs[0], 'temp_reg2': temp_regs[1] + }) + instr_dict_csr_restores.append({ + 'csr_reg': csr_reg, 'restore_reg': f'x{restore_reg}' + }) + restore_reg += 1 + + if csr_reg not in uniq_csr_regs: + uniq_csr_regs.append(csr_reg) + + instr_dict_csr_restores.reverse() + + instr_dict_csr_read_and_sig_upds = [] + for csr_reg in uniq_csr_regs: + instr_dict_csr_read_and_sig_upds.append({ + 'csr_reg': csr_reg, 'dest_reg': dest_reg, 'offset': offset + }) + offset += (self.xlen >> 3) + + instr_dict.append((instr_dict_csr_writes, instr_dict_csr_read_and_sig_upds, instr_dict_csr_restores)) + + return instr_dict + + def write_test(self, fprefix, cgf_node, usage_str, cov_label, instr_dict): + base_reg = 'x28' + + code = [""] + data = [".align 4","rvtest_data:",".word 0xbabecafe", \ + ".word 0xabecafeb", ".word 0xbecafeba", ".word 0xecafebab"] + sig = [""] + + sig_label = f"signature_{base_reg}_0" + sig.append(signode_template.safe_substitute(label = sig_label, n = len(instr_dict), sz = '(XLEN/32)')) + code.append(f"RVTEST_SIGBASE({base_reg}, {sig_label})\n") + + for i, instr in enumerate(instr_dict): + csr_writes, csr_read_sig_upds, csr_restores = instr + + for j, csr_write in enumerate(csr_writes): + code.extend([ + f"\ninst_{i}_csr_write_{j}:", + csr_reg_write_to_field_template.safe_substitute({ + 'base_reg': base_reg, **csr_write + }) + ]) + + for j, csr_read_sig_upd in enumerate(csr_read_sig_upds): + code.extend([ + f"\ninst_{i}_csr_read_sig_upd_{j}:", + csr_reg_read_and_sig_upd_template.safe_substitute({ + 'base_reg': base_reg, **csr_read_sig_upd + }) + ]) + + for j, csr_restore in enumerate(csr_restores): + code.extend([ + f"\ninst_{i}_csr_restore_{j}:", + csr_reg_restore_template.safe_substitute({ + 'base_reg': base_reg, **csr_restore + }) + ]) + + case_str = ''.join([case_template.safe_substitute(xlen = self.xlen, num = i, cov_label = cov_label) for i, cond in enumerate(cgf_node.get('config', []))]) + test_str = part_template.safe_substitute(case_str = case_str, code = '\n'.join(code)) + fname = fprefix + '_csr-comb.S' + logger.debug("Writing Test to %s", str(fname)) + with open(fname, 'w') as fp: + fp.write(usage_str + csr_comb_test_template.safe_substitute( + isa = self.base_isa.upper(), # how to get the extensions? + test = test_str, + data = '\n'.join(data), + sig = '\n'.join(sig), + label = cov_label + )) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/ctg.py b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/ctg.py new file mode 100644 index 000000000..9d7c0fa81 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/ctg.py @@ -0,0 +1,131 @@ +# See LICENSE.incore file for details + +import copy +import os,re +import multiprocessing as mp + +import time +import shutil +from riscv_ctg.log import logger +import riscv_ctg.utils as utils +import riscv_ctg.constants as const +from riscv_isac.cgf_normalize import expand_cgf +from riscv_ctg.generator import Generator +from riscv_ctg.cross_comb import cross +from riscv_ctg.csr_comb import GeneratorCSRComb +from math import * +from riscv_ctg.__init__ import __version__ + +def create_test(usage_str, node,label,base_isa,max_inst, op_template, randomize, out_dir, xlen, flen): + iflen = 0 + if 'mnemonics' not in node and 'csr_comb' not in node: + logger.warning("Neither mnemonics nor csr_comb node not found in covergroup: " + str(label)) + return + if 'ignore' in node: + logger.info("Ignoring :" + str(label)) + if node['ignore']: + return + + if 'mnemonics' in node: + # Function to encompass checks and test generation + def gen_test(op_node, opcode): + iflen = 0 + if xlen not in op_node['xlen']: + logger.warning("Skipping {0} since its not supported in current XLEN:".format(opcode)) + return + if 'flen' in op_node: + if flen not in op_node['flen']: + logger.warning("Skipping {0} since its not supported in current FLEN({1}):".format(\ + opcode, flen)) + return + iflen = min(op_node['flen']) + fprefix = os.path.join(out_dir,str(label)) + logger.info('Generating Test for :' + str(label) +"-" + opcode) + formattype = op_node['formattype'] + gen = Generator(formattype,op_node,opcode,randomize,xlen,flen,iflen,base_isa) + op_comb = gen.opcomb(node) + val_comb = gen.valcomb(node) + instr_dict = gen.correct_val( + gen.valreg( + gen.testreg( + gen.swreg( + gen.gen_inst(op_comb, val_comb, node))))) + logger.info("Writing tests for :"+str(label)) + my_dict = gen.reformat_instr(instr_dict) + gen.write_test(fprefix,node,label,my_dict, op_node, usage_str, max_inst) + + # If base_op defined in covergroup, extract corresponding template + # else go through the instructions defined in mnemonics label + op_node = None + if 'base_op' in node: + # Extract pseudo and base instructions + base_op = node['base_op'] + pseudop = list(node['mnemonics'].keys())[0] + if base_op in op_template and pseudop in op_template: + op_node = copy.deepcopy(op_template[base_op]) + pseudo_template = op_template[pseudop] + + # Ovewrite/add nodes from pseudoinstruction template in base instruction template + for key, val in pseudo_template.items(): + op_node[key] = val + + # Generate tests + gen_test(op_node, pseudop) + else: + for opcode in node['mnemonics']: + if opcode in op_template: + op_node = op_template[opcode] + # Generate tests + gen_test(op_node, opcode) + else: + logger.warning(str(opcode) + " not found in template file. Skipping") + return + + if 'cross_comb' in node: + fprefix = os.path.join(out_dir,str(label)) + cross_obj = cross(base_isa, xlen, randomize, label) + cross_instr_dict = cross_obj.cross_comb(node) + logger.info('Writing cross-comb test') + cross_obj.write_test(fprefix, node, usage_str, label, cross_instr_dict) + + if op_node is None: + # Return if there is no corresponding template + logger.warning("Skipping :" + str(opcode)) + return + + if 'csr_comb' in node: + fprefix = os.path.join(out_dir,str(label)) + csr_comb_gen = GeneratorCSRComb(base_isa, xlen, randomize) + csr_comb_instr_dict = csr_comb_gen.csr_comb(node) + logger.info('Writing tests for csr_comb') + csr_comb_gen.write_test(fprefix, node, usage_str, label, csr_comb_instr_dict) + +def ctg(verbose, out, random ,xlen_arg,flen_arg, cgf_file,num_procs,base_isa, max_inst): + logger.level(verbose) + logger.info('****** RISC-V Compliance Test Generator {0} *******'.format(__version__ )) + logger.info('Copyright (c) 2020, InCore Semiconductors Pvt. Ltd.') + logger.info('All Rights Reserved.') + logger.info("Copying env folder to Output directory.") + env_dir = os.path.join(out,"env") + if not os.path.exists(env_dir): + shutil.copytree(const.env,env_dir) + xlen = int(xlen_arg) + flen = int(flen_arg) + out_dir = out + randomize = random + mytime = time.asctime(time.gmtime(time.time()) ) + ' GMT' + cgf_argument = '' + for cf in cgf_file: + cgf_argument += '// --cgf {} \\\n'.format(cf) + randomize_argument = '' + if random is True: + randomize_argument = ' \\\n// --randomize' + usage_str = const.usage.safe_substitute(base_isa=base_isa, \ + cgf=cgf_argument, version = __version__, time=mytime, \ + randomize=randomize_argument,xlen=str(xlen_arg)) + op_template = utils.load_yamls(const.template_files) + cgf = expand_cgf(cgf_file,xlen,flen) + pool = mp.Pool(num_procs) + results = pool.starmap(create_test, [(usage_str, node,label,base_isa,max_inst, op_template, + randomize, out_dir, xlen, flen) for label,node in cgf.items()]) + pool.close() diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/data/fd.yaml b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/data/fd.yaml new file mode 100644 index 000000000..39d41eca6 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/data/fd.yaml @@ -0,0 +1,2203 @@ +# See LICENSE.incore for details +fadd.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr + - IFD_Zicsr + flen: [32,64] + std_op: + formattype: 'rformat' + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fadd.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) +fadd.q: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFDQ_Zicsr + flen: [128] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + rs1_val_data: 'gen_sign_dataset(128)' + rs2_val_data: 'gen_sign_dataset(128)' + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsub.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr + - IFD_Zicsr + flen: [32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsub.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmul.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr + - IFD_Zicsr + flen: [32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmul.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fdiv.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr + - IFD_Zicsr + flen: [32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fdiv.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsqrt.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr + - IFD_Zicsr + flen: [32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr */ + TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsqrt.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr */ + TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmadd.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 3 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr + - IFD_Zicsr + flen: [32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'r4format' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rs3_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; + testreg:$testreg; fcsr_val:$fcsr */ + TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmadd.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 3 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'r4format' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rs3_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; + testreg:$testreg; fcsr_val:$fcsr */ + TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmsub.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 3 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr + - IFD_Zicsr + flen: [32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'r4format' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rs3_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; + testreg:$testreg; fcsr_val:$fcsr */ + TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmsub.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 3 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'r4format' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rs3_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; + testreg:$testreg; fcsr_val:$fcsr */ + TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fnmadd.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 3 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr + - IFD_Zicsr + flen: [32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'r4format' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rs3_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; + testreg:$testreg; fcsr_val:$fcsr */ + TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fnmadd.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 3 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'r4format' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rs3_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; + testreg:$testreg; fcsr_val:$fcsr */ + TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fnmsub.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 3 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr + - IFD_Zicsr + flen: [32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'r4format' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rs3_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; + testreg:$testreg; fcsr_val:$fcsr */ + TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fnmsub.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 3 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'r4format' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rs3_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; + testreg:$testreg; fcsr_val:$fcsr */ + TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsgnj.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr + - IFD_Zicsr + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsgnj.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsgnjn.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr + - IFD_Zicsr + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsgnjn.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsgnjx.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr + - IFD_Zicsr + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fsgnjx.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmin.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr + - IFD_Zicsr + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmin.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmax.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr + - IFD_Zicsr + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmax.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +feq.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr + - IFD_Zicsr + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +feq.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +flt.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr + - IFD_Zicsr + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +flt.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fle.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr + - IFD_Zicsr + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fle.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmv.w.x: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '4' + val_template: "'.word $val;'" + load_instr: "lw" + xlen: [32,64] + isa: + - IF_Zicsr + - IFD_Zicsr + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_fregs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIO_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fmv.x.w: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr + - IFD_Zicsr + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fcvt.w.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr + - IFD_Zicsr + flen: [32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.w.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.wu.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr + - IFD_Zicsr + flen: [32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.wu.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.l.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [64] + isa: + - IFD_Zicsr + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.lu.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [64] + isa: + - IFD_Zicsr + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fmv.x.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [64] + isa: + - IFD_Zicsr + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fcvt.s.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr */ + TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fcvt.d.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr */ + TEST_FPSR_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fcvt.s.w: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '4' + val_template: "'.word $val;'" + load_instr: "lw" + xlen: [32,64] + isa: + - IF_Zicsr + - IFD_Zicsr + flen: [32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_fregs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.s.wu: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '4' + val_template: "'.word $val;'" + load_instr: "LREGWU" + xlen: [32,64] + isa: + - IF_Zicsr + - IFD_Zicsr + flen: [32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_fregs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.d.w: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '4' + val_template: "'.word $val;'" + load_instr: "lw" + xlen: [32,64] + isa: + - IFD_Zicsr + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_fregs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIO_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.d.wu: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '4' + val_template: "'.word $val;'" + load_instr: "LREGWU" + xlen: [32,64] + isa: + - IFD_Zicsr + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_fregs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIO_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.d.l: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '8' + val_template: "'.dword $val;'" + load_instr: "ld" + xlen: [64] + isa: + - IFD_Zicsr + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_fregs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.d.lu: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '8' + val_template: "'.dword $val;'" + load_instr: "ld" + xlen: [64] + isa: + - IFD_Zicsr + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_fregs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fmv.d.x: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '8' + val_template: "'.dword $val;'" + load_instr: "ld" + xlen: [64] + isa: + - IFD_Zicsr + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_fregs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIO_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fclass.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr + - IFD_Zicsr + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fclass.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32, 64] + isa: + - IFD_Zicsr + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +# The val nodes are present in the fmem ops right now as a hack to force allocation of flagreg. Once +# anxilliary registers are moved to their own functions, this can be removed. +fsw: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_fregs + xlen: [32,64] + isa: + - IF_Zicsr + - IFD_Zicsr + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'sformat' + ea_align_data: '[0,1,2,3]' + rs2_val_data: '[0xABCDEF12]' + imm_val_data: 'gen_sign_dataset(12)' + template: |- + // $comment + // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg; + // valreg: $valaddr_reg; valoffset: $val_offset + TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset) + +flw: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '4' + val_template: "''" + load_instr: "flw" + rs1_op_data: *all_regs_mx0 + rd_op_data: *all_fregs + xlen: [32,64] + std_op: + isa: + - IF_Zicsr + - IFD_Zicsr + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'iformat' + ea_align_data: '[0,1,2,3]' + imm_val_data: 'gen_sign_dataset(12)' + template: |- + // $comment + // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg + TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg) + +fsd: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_fregs + std_op: + xlen: [32,64] + isa: + - IFD_Zicsr + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'sformat' + ea_align_data: '[0,1,2,3]' + rs2_val_data: '[0x0123456789ABCDEF]' + imm_val_data: 'gen_sign_dataset(12)' + template: |- + // $comment + // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg; + // valreg: $valaddr_reg; valoffset: $val_offset + TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset) + +fld: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '8' + val_template: "''" + load_instr: "fld" + rs1_op_data: *all_regs_mx0 + rd_op_data: *all_fregs + xlen: [32,64] + std_op: + isa: + - IFD_Zicsr + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'iformat' + ea_align_data: '[0,1,2,3]' + imm_val_data: 'gen_sign_dataset(12)' + template: |- + // $comment + // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flag_reg + TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg) + +fsq: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_fregs + std_op: + xlen: [32,64] + isa: + - IFDQ_Zicsr + flen: [128] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'sformat' + ea_align_data: '[0,1,2,3]' + rs2_val_data: '[0x0123456789ABCDEF]' + imm_val_data: 'gen_sign_dataset(12)' + template: |- + // $comment + // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg; + // valreg: $valaddr_reg; valoffset: $val_offset + TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset) + +flq: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '16' + val_template: "''" + load_instr: "fld" + rs1_op_data: *all_regs_mx0 + rd_op_data: *all_fregs + xlen: [32,64] + std_op: + isa: + - IFDQ_Zicsr + flen: [128] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'iformat' + ea_align_data: '[0,1,2,3]' + imm_val_data: 'gen_sign_dataset(12)' + template: |- + // $comment + // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flag_reg + TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg) + +fcvt.l.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [64] + std_op: + isa: + - IF_Zicsr + - IFD_Zicsr + flen: [32,64] + rm_val_data: '[0,1,2,3,4,7]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.lu.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [64] + isa: + - IF_Zicsr + - IFD_Zicsr + flen: [32,64] + rm_val_data: '[0,1,2,3,4,7]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.s.l: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '8' + val_template: "'.dword $val;'" + load_instr: "ld" + xlen: [64] + isa: + - IF_Zicsr + - IFD_Zicsr + std_op: + flen: [32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_fregs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvt.s.lu: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: '8' + val_template: "'.dword $val;'" + load_instr: "ld" + xlen: [64] + isa: + - IF_Zicsr + - IFD_Zicsr + flen: [32,64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_regs + rd_op_data: *all_fregs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +# +# Zfa extension +# + +fminm.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfa + - IFD_Zicsr_Zfa + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fminm.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr_Zfa + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmaxm.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfa + - IFD_Zicsr_Zfa + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmaxm.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr_Zfa + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr; + correctval:??; testreg:$testreg + */ + TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fround.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfa + - IFD_Zicsr_Zfa + flen: [32,64] + std_op: + formattype: 'fsrformat' + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + rs1_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr */ + TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fround.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr_Zfa + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr */ + TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +froundnx.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfa + - IFD_Zicsr_Zfa + flen: [32,64] + std_op: + formattype: 'fsrformat' + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + rs1_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr */ + TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +froundnx.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr_Zfa + flen: [64] + rm_val_data: '[7,0,1,2,3,4]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_fregs + template: |- + + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:$rm_val; correctval:??; testreg:$testreg; + fcsr_val: $fcsr */ + TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmvh.x.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32] + isa: + - IFD_Zicsr_Zfa + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fmvp.d.x: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: '4' + val_template: "'.word $val;'" + load_instr: "lw" + xlen: [32] + isa: + - IFD_Zicsr_Zfa + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_fregs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FPIOIO_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fcvtmod.w.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 1 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr_Zfa + flen: [64] + rm_val_data: '[1]' + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'fsrformat' + rs1_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; + val_offset:$val_offset; rmval:rtz; correctval:??; testreg:$testreg; + fcsr_val:$fcsr*/ + TEST_FPID_OP($inst, $rd, $rs1, rtz, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr) + +fltq.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfa + - IFD_Zicsr_Zfa + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fltq.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr_Zfa + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fleq.s: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IF_Zicsr_Zfa + - IFD_Zicsr_Zfa + flen: [32,64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) + +fleq.d: + sig: + stride: 2 + sz: 'SIGALIGN' + val: + stride: 2 + sz: 'FLEN/8' + val_template: "'NAN_BOXED($val,$width,FLEN)'" + load_instr: "FLREG" + xlen: [32,64] + isa: + - IFD_Zicsr_Zfa + flen: [64] + fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]' + std_op: + formattype: 'rformat' + rs1_op_data: *all_fregs + rs2_op_data: *all_fregs + rd_op_data: *all_regs + template: |- + // $comment + /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:??; testreg:$testreg; + fcsr_val: $fcsr*/ + TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/data/imc.yaml b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/data/imc.yaml new file mode 100644 index 000000000..be5b19953 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/data/imc.yaml @@ -0,0 +1,1890 @@ +# See LICENSE.incore for details +add: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - I + operation: 'hex((rs1_val + rs2_val) & (2**(xlen)-1))' + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +sub: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + isa: + - I + operation: 'hex((rs1_val - rs2_val) & (2**(xlen)-1))' + formattype: 'rformat' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + + +addw: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + xlen: [64] + std_op: + isa: + - I + operation: 'hex(sign_extend( (rs1_val & 0xFFFFFFFF) + (rs2_val & 0xFFFFFFFF) ,32))' + formattype: 'rformat' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +subw: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + xlen: [64] + std_op: + isa: + - I + operation: 'hex(sign_extend( (rs1_val & 0xFFFFFFFF) - (rs2_val & 0xFFFFFFFF) ,32))' + formattype: 'rformat' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +and: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + operation: 'hex((rs1_val & rs2_val) & (2**(xlen)-1))' + formattype: 'rformat' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +or: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + operation: 'hex((rs1_val | rs2_val) & (2**(xlen)-1))' + formattype: 'rformat' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +slt: + rs1_op_data: *all_regs + sig: + stride: 1 + sz: 'XLEN/8' + rs2_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + operation: 'hex(int(rs1_val < rs2_val) & (2**(xlen)-1))' + formattype: 'rformat' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +sltu: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + operation: 'hex(int(rs1_val < rs2_val) & (2**(xlen)-1))' + formattype: 'rformat' + rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)' + rs2_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +xor: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + operation: 'hex((rs1_val ^ rs2_val) & (2**(xlen)-1))' + formattype: 'rformat' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +sllw: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + xlen: [64] + std_op: + isa: + - I + operation: 'hex(sign_extend((rs1_val << (rs2_val%32)) ,32))' + formattype: 'rformat' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_usign_dataset(5)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +srlw: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + xlen: [64] + std_op: + isa: + - I + operation: 'hex(sign_extend((rs1_val & 0xffffffff) >> (rs2_val%32), 32))' + formattype: 'rformat' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_usign_dataset(5)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +sraw: + rs1_op_data: *all_regs + sig: + stride: 1 + sz: 'XLEN/8' + rs2_op_data: *all_regs + rd_op_data: *all_regs + xlen: [64] + std_op: + isa: + - I + operation: 'hex(sign_extend((sign_extend(rs1_val,32) >> ((rs2_val & 0xffffffff) %32))& 0xffffffff ,32))' + formattype: 'rformat' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_usign_dataset(5)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +sll: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + operation: 'hex((rs1_val << (rs2_val%xlen)) & (2**(xlen)-1))' + formattype: 'rformat' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_usign_dataset(ceil(log(xlen,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +srl: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + operation: 'hex((rs1_val & (2**(xlen)-1)) >> (rs2_val%xlen))' + formattype: 'rformat' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_usign_dataset(ceil(log(xlen,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +sra: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + operation: 'hex(rs1_val >> (rs2_val%xlen) )' + formattype: 'rformat' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_usign_dataset(ceil(log(xlen,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +addi: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +addiw: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [64] + std_op: + isa: + - I + operation: 'hex(sign_extend( (rs1_val & 0xFFFFFFFF) + (imm_val & 0xffffffff) , 32))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12,True)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +slti: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + operation: 'hex(int(rs1_val < imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12,True)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +sltiu: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + operation: 'hex(int(rs1_val < int(imm_val if imm_val&0x800 == 0 else imm_val + int("0x"+"".join("f"*int((xlen-12)/4)+"000"),16))) & (2**(xlen)-1))' + rs1_val_data: 'gen_usign_dataset(xlen)+ gen_sp_dataset(xlen,False)' + imm_val_data: 'gen_usign_dataset(12)+ gen_sp_dataset(12,False)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +andi: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + operation: 'hex((rs1_val & imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +ori: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + operation: 'hex((rs1_val | imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +xori: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + operation: 'hex((rs1_val ^ imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +slli: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + operation: 'hex((rs1_val << imm_val) & (2**(xlen)-1))' + formattype: 'iformat' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_usign_dataset(ceil(log(xlen,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +srli: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + operation: 'hex((rs1_val & (2**(xlen)-1)) >> imm_val)' + formattype: 'iformat' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_usign_dataset(ceil(log(xlen,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +srai: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + operation: 'hex(rs1_val >> (imm_val))' + formattype: 'iformat' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_usign_dataset(ceil(log(xlen,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +slliw: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [64] + std_op: + isa: + - I + operation: 'hex(sign_extend((rs1_val << imm_val) , 32))' + formattype: 'iformat' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_usign_dataset(5)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +srliw: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [64] + std_op: + isa: + - I + operation: 'hex(sign_extend((rs1_val & 0xFFFFFFFF) >> imm_val , 32))' + formattype: 'iformat' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_usign_dataset(5)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +sraiw: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [64] + std_op: + isa: + - I + operation: 'hex(sign_extend((sign_extend(rs1_val,32) >> ((imm_val & 0xfff) %32)) & 0xffffffff, 32))' + formattype: 'iformat' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_usign_dataset(5)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +lui: + sig: + stride: 1 + sz: 'XLEN/8' + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + operation: 'hex(sign_extend(imm_val << (12), 32))' + formattype: 'uformat' + imm_val_data: 'gen_usign_dataset(20)+ gen_sp_dataset(20,False)' + template: |- + + // $comment + // opcode: $inst ; dest:$rd; immval:$imm_val + TEST_CASE($testreg, $rd, $correctval, $swreg, $offset, $inst $rd,$imm_val) + +auipc: + sig: + stride: 1 + sz: 'XLEN/8' + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + operation: 'hex(sign_extend(imm_val << (12) ,32))' + formattype: 'uformat' + imm_val_data: 'gen_usign_dataset(20)+ gen_sp_dataset(20, False)' + template: |- + + // $comment + // opcode: $inst ; dest:$rd; immval:$imm_val + TEST_AUIPC($inst, $rd, $correctval, $imm_val, $swreg, $offset, $testreg) + +beq: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + formattype: 'bformat' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + ea_align_data: '[0,1,2,3]' + imm_val_data: 'list(filter(lambda x: x%2==0,gen_sign_dataset(12)))' + template: |- + + // $comment + // opcode: $inst, op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; immval:$imm_val; align:$ea_align + TEST_BRANCH_OP($inst, $testreg, $rs1, $rs2, $rs1_val, $rs2_val, $imm_val, $label, $swreg, $offset,$ea_align) + +bge: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + formattype: 'bformat' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + ea_align_data: '[0,1,2,3]' + imm_val_data: 'list(filter(lambda x: x%2==0,gen_sign_dataset(12)))' + template: |- + + // $comment + // opcode: $inst, op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; immval:$imm_val; align:$ea_align + TEST_BRANCH_OP($inst, $testreg, $rs1, $rs2, $rs1_val, $rs2_val, $imm_val, $label, $swreg, $offset,$ea_align) + +bgeu: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + formattype: 'bformat' + rs1_val_data: 'gen_usign_dataset(xlen)+ gen_sp_dataset(xlen,False)' + rs2_val_data: 'gen_usign_dataset(xlen)+ gen_sp_dataset(xlen,False)' + ea_align_data: '[0,1,2,3]' + imm_val_data: 'list(filter(lambda x: x%2==0,gen_sign_dataset(12)))' + template: |- + + // $comment + // opcode: $inst, op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; immval:$imm_val; align:$ea_align + TEST_BRANCH_OP($inst, $testreg, $rs1, $rs2, $rs1_val, $rs2_val, $imm_val, $label, $swreg, $offset,$ea_align) + +blt: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + formattype: 'bformat' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + ea_align_data: '[0,1,2,3]' + imm_val_data: 'list(filter(lambda x: x%2==0,gen_sign_dataset(12)))' + template: |- + + // $comment + // opcode: $inst, op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; immval:$imm_val; align:$ea_align + TEST_BRANCH_OP($inst, $testreg, $rs1, $rs2, $rs1_val, $rs2_val, $imm_val, $label, $swreg, $offset,$ea_align) + +bltu: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + formattype: 'bformat' + rs1_val_data: 'gen_usign_dataset(xlen)+ gen_sp_dataset(xlen,False)' + rs2_val_data: 'gen_usign_dataset(xlen)+ gen_sp_dataset(xlen,False)' + ea_align_data: '[0,1,2,3]' + imm_val_data: 'list(filter(lambda x: x%2==0,gen_sign_dataset(12)))' + template: |- + + // $comment + // opcode: $inst, op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; immval:$imm_val; align:$ea_align + TEST_BRANCH_OP($inst, $testreg, $rs1, $rs2, $rs1_val, $rs2_val, $imm_val, $label, $swreg, $offset,$ea_align) + +bne: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + formattype: 'bformat' + rs1_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen) ' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen) ' + ea_align_data: '[0,1,2,3]' + imm_val_data: 'list(filter(lambda x: x%2==0,gen_sign_dataset(12)))' + template: |- + + // $comment + // opcode: $inst, op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; immval:$imm_val; align:$ea_align + TEST_BRANCH_OP($inst, $testreg, $rs1, $rs2, $rs1_val, $rs2_val, $imm_val, $label, $swreg, $offset,$ea_align) + +sd: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + xlen: [64] + std_op: + isa: + - I + formattype: 'sformat' + ea_align_data: '[0,1,2,3,4,5,6,7]' + rs2_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: 'gen_sign_dataset(12)' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align + TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,$ea_align) + +sw: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + formattype: 'sformat' + ea_align_data: '[0,1,2,3]' + rs2_val_data: 'gen_sign_dataset(xlen)' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)' + template: |- + + // $comment + // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align + TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,$ea_align) + +sh: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + formattype: 'sformat' + ea_align_data: '[0,1,2,3]' + rs2_val_data: 'gen_sign_dataset(xlen)' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)' + template: |- + + // $comment + // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align + TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,$ea_align) + +sb: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + formattype: 'sformat' + ea_align_data: '[0,1,2,3]' + rs2_val_data: 'gen_sign_dataset(xlen)' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)' + template: |- + + // $comment + // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align + TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,$ea_align) + +ld: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs_mx0 + rd_op_data: *all_regs + isa: + - I + xlen: [64] + std_op: + formattype: 'iformat' + ea_align_data: '[0,1,2,3,4,5,6,7]' + imm_val_data: 'gen_sign_dataset(12)' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align + TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,$ea_align) + +lwu: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs_mx0 + rd_op_data: *all_regs + isa: + - I + xlen: [64] + std_op: + formattype: 'iformat' + ea_align_data: '[0,1,2,3]' + imm_val_data: 'gen_sign_dataset(12)' + rs1_val_data: 'gen_usign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align + TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,$ea_align) + +lw: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs_mx0 + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + formattype: 'iformat' + ea_align_data: '[0,1,2,3]' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)' + template: |- + + // $comment + // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align + TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,$ea_align) + +lhu: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs_mx0 + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + formattype: 'iformat' + ea_align_data: '[0,1,2,3]' + rs1_val_data: 'gen_usign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)' + template: |- + + // $comment + // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align + TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,$ea_align) + +lh: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs_mx0 + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + formattype: 'iformat' + ea_align_data: '[0,1,2,3]' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)' + template: |- + + // $comment + // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align + TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,$ea_align) + +lbu: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs_mx0 + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + formattype: 'iformat' + ea_align_data: '[0,1,2,3]' + imm_val_data: 'gen_sign_dataset(12)' + rs1_val_data: 'gen_usign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align + TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,$ea_align) + +lb: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs_mx0 + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + formattype: 'iformat' + ea_align_data: '[0,1,2,3]' + imm_val_data: 'gen_sign_dataset(12)' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align + TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,$ea_align) + +jal: + sig: + stride: 1 + sz: 'XLEN/8' + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + formattype: 'jformat' + ea_align_data: '[0,1,2,3]' + imm_val_data: 'list(filter(lambda x: x%2==0,gen_sign_dataset(20)))' + template: |- + + // $comment + // opcode: jal; dest:$rd; immval:$imm_val; align:$ea_align + TEST_JAL_OP($testreg, $rd, $imm_val, $label, $swreg, $offset,$ea_align) + +jalr: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs_mx0 + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - I + formattype: 'iformat' + ea_align_data: '[0,1,2,3]' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)' + template: |- + + // $comment + // opcode: jalr; op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align + TEST_JALR_OP($testreg, $rd, $rs1, $imm_val, $swreg, $offset,$ea_align) + +mul: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IM + formattype: 'rformat' + operation: 'hex((rs1_val * rs2_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +mulh: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IM + formattype: 'rformat' + operation: 'hex(((rs1_val * rs2_val)>>xlen) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +mulhu: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IM + formattype: 'rformat' + operation: 'hex(((rs1_val * rs2_val)>>xlen) & (2**(xlen)-1))' + rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)' + rs2_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +mulhsu: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IM + formattype: 'rformat' + operation: 'hex(((rs1_val * (rs2_val if rs2_val>=0 else int(hex((1<>xlen) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +div: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IM + formattype: 'rformat' + operation: 'hex(int(abs(rs1_val)//abs(rs2_val))) if (rs1_val * rs2_val > 0) else hex(-int(abs(rs1_val)//abs(rs2_val))) if rs2_val != 0 else "0x"+("F"*int(xlen/4))' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True) + [-(2**(xlen-1))]' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +divu: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IM + formattype: 'rformat' + operation: 'hex(int(rs1_val // rs2_val) & (2**(xlen)-1)) if rs2_val!=0 else "0x"+("F"*int(xlen/4))' + rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)' + rs2_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +rem: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IM + formattype: 'rformat' + # operation: 'hex(rs1_val if rs2_val==0 or (rs1_val 0 else hex(-int(abs(rs1_val) % abs(rs2_val)))' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True) + [-(2**(xlen-1))]' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +remu: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IM + formattype: 'rformat' + operation: 'hex(rs1_val) if rs2_val == 0 else hex(int(abs(rs1_val) % abs(rs2_val))) ' + rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)' + rs2_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +mulw: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + xlen: [64] + std_op: + isa: + - IM + formattype: 'rformat' + operation: 'hex(sign_extend((rs1_val & 0xFFFFFFFF) * (rs2_val & 0xFFFFFFFF) ,32))' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +divw: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + xlen: [64] + std_op: + isa: + - IM + formattype: 'rformat' + # operation: 'hex(sign_extend(int((rs1_val & 0xFFFFFFFF) // (rs2_val & 0xFFFFFFFF)) ,32)) if (rs2_val&0xFFFFFFFF)!=0 else "0x"+("F"*int(xlen/4))' + operation: 'hex(sign_extend(int(abs(sign_extend(rs1_val,32))//abs(sign_extend(rs2_val,32))),32)) if (sign_extend(rs1_val,32) * sign_extend(rs2_val,32) > 0) else hex(-int(abs(sign_extend(rs1_val,32))//abs(sign_extend(rs2_val, 32)))) if sign_extend(rs2_val,32) != 0 else "0x"+("F"*int(xlen/4))' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +divuw: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + xlen: [64] + std_op: + isa: + - IM + formattype: 'rformat' + operation: 'hex(sign_extend(int((rs1_val & 0xFFFFFFFF) // (rs2_val & 0xFFFFFFFF)) ,32)) if (rs2_val&0xFFFFFFFF)!=0 else "0x"+("F"*int(xlen/4))' + rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)' + rs2_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +remw: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + xlen: [64] + std_op: + isa: + - IM + formattype: 'rformat' + # operation: 'hex(sign_extend(((rs1_val & 0xFFFFFFFF) % (rs2_val & 0xFFFFFFFF)) , 32)) if (rs2_val&0xFFFFFFFF)!=0 else hex(rs1_val)' + operation: 'hex(sign_extend(rs1_val,32)) if (rs2_val&0xffffffff) == 0 else hex(sign_extend(int(abs(sign_extend(rs1_val,32)) % abs(sign_extend(rs2_val,32))),32)) if sign_extend(rs1_val,32) > 0 else hex(-int(abs(sign_extend(rs1_val,32)) % abs(sign_extend(rs2_val,32))))' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +remuw: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + xlen: [64] + std_op: + isa: + - IM + formattype: 'rformat' + operation: 'hex(sign_extend((rs1_val & 0xFFFFFFFF) % (rs2_val & 0xFFFFFFFF) , 32)) if (rs2_val&0xFFFFFFFF)!=0 else hex(sign_extend(rs1_val,32))' + rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)' + rs2_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +c.mv: + sig: + stride: 1 + sz: 'XLEN/8' + rs2_op_data: *all_regs_mx0 + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IC + formattype: 'cmvformat' + operation: 'hex(rs2_val)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst; op2:$rs2; dest:$rd; op2val:$rs2_val + TEST_CMV_OP( $inst, $rd, $rs2, $correctval, $rs2_val, $swreg, $offset, $testreg) + +c.add: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs_mx0 + xlen: [32,64] + std_op: + isa: + - IC + formattype: 'crformat' + operation: 'hex((rs1_val + rs2_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val + TEST_CR_OP( $inst, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +c.addw: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *c_regs + rs2_op_data: *c_regs + xlen: [64] + std_op: + isa: + - IC + formattype: 'crformat' + operation: 'hex(sign_extend((rs1_val + rs2_val) ,32))' + rs1_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val + TEST_CR_OP( $inst, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +c.and: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *c_regs + rs2_op_data: *c_regs + xlen: [32,64] + std_op: + isa: + - IC + formattype: 'crformat' + operation: 'hex((rs1_val & rs2_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val + TEST_CR_OP( $inst, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +c.or: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *c_regs + rs2_op_data: *c_regs + xlen: [32,64] + std_op: + isa: + - IC + formattype: 'crformat' + operation: 'hex((rs1_val | rs2_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val + TEST_CR_OP( $inst, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +c.xor: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *c_regs + rs2_op_data: *c_regs + xlen: [32,64] + std_op: + isa: + - IC + formattype: 'crformat' + operation: 'hex((rs1_val ^ rs2_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val + TEST_CR_OP( $inst, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +c.sub: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *c_regs + rs2_op_data: *c_regs + xlen: [32,64] + std_op: + isa: + - IC + formattype: 'crformat' + operation: 'hex((rs1_val - rs2_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val + TEST_CR_OP( $inst, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +c.subw: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *c_regs + rs2_op_data: *c_regs + xlen: [64] + std_op: + isa: + - IC + formattype: 'crformat' + operation: 'hex(sign_extend((rs1_val & 0xFFFFFFFF) - (rs2_val & 0xFFFFFFFF) ,32))' + rs1_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val + TEST_CR_OP( $inst, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +c.andi: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *c_regs + xlen: [32,64] + std_op: + isa: + - IC + formattype: 'cbformat' + operation: 'hex((rs1_val & imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)' + imm_val_data: 'gen_sign_dataset(6)+gen_sp_dataset(6)' + template: |- + + // $comment + // opcode: $inst; op1:$rs1; immval:$imm_val + TEST_CI_OP( $inst, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +c.nop: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IC + formattype: 'ciformat' + imm_val_data: 'gen_sign_dataset(6)' + rs1_data: "['x0']" + rs1_val_data: "[0]" + template: |- + // $comment + // opcode:$inst; immval:$imm_val + TEST_CNOP_OP($inst, $testreg, $imm_val, $swreg, $offset) + +c.addi: + sig: + stride: 1 + sz: 'XLEN/8' + rd_op_data: *all_regs_mx0 + xlen: [32,64] + std_op: + isa: + - IC + formattype: 'ciformat' + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen)' + imm_val_data: 'gen_sign_dataset(6) + gen_sp_dataset(6)' + template: |- + + // $comment + // opcode:$inst; op1:$rd; dest:$rd op1val:$rs1_val; immval:$imm_val + TEST_CI_OP( $inst, $rd, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +c.addiw: + sig: + stride: 1 + sz: 'XLEN/8' + rd_op_data: *all_regs_mx0 + xlen: [64] + std_op: + isa: + - IC + formattype: 'ciformat' + operation: 'hex(sign_extend(((rs1_val & 0xFFFFFFFF) + (imm_val & 0xffffffff)) , 32))' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen)' + imm_val_data: 'gen_sign_dataset(6) + gen_sp_dataset(6)' + template: |- + + // $comment + // opcode:$inst; op1:$rd; dest:$rd op1val:$rs1_val; immval:$imm_val + TEST_CI_OP( $inst, $rd, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +c.addi16sp: + sig: + stride: 1 + sz: 'XLEN/8' + rd_op_data: "['x2']" + xlen: [32,64] + std_op: + isa: + - IC + formattype: 'ciformat' + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: 'list(filter( lambda x: x!=0 , [ 16*x for x in gen_sign_dataset(6)])) + [496]' + template: |- + + // $comment + // opcode:$inst; op1:x2; dest:x2 op1val:$rs1_val; immval:$imm_val + TEST_CI_OP( $inst, x2, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +c.addi4spn: + sig: + stride: 1 + sz: 'XLEN/8' + rd_op_data: *c_regs + xlen: [32,64] + std_op: + isa: + - IC + formattype: 'ciwformat' + operation: 'hex(imm_val)' + imm_val_data: 'list(filter( lambda x: x!=0 , [ 4*x for x in gen_usign_dataset(8)]))' + template: |- + + // $comment + // opcode:$inst; dest:$rd; immval:$imm_val + TEST_CADDI4SPN_OP( $inst, $rd, $correctval, $imm_val, $swreg, $offset, $testreg) + +c.slli: + sig: + stride: 1 + sz: 'XLEN/8' + rd_op_data: *c_regs + xlen: [32,64] + std_op: + isa: + - IC + formattype: 'ciformat' + operation: 'hex((rs1_val << imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen)' + imm_val_data: 'list(filter(lambda x: x!=0, gen_usign_dataset(ceil(log(xlen,2)))))' + template: |- + + // $comment + // opcode:$inst; op1:$rd; dest:$rd op1val:$rs1_val; immval:$imm_val + TEST_CI_OP( $inst, $rd, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +c.srli: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *c_regs + xlen: [32,64] + std_op: + isa: + - IC + formattype: 'cbformat' + operation: 'hex(((rs1_val & (2**(xlen)-1)) >> imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen)' + imm_val_data: 'list(filter(lambda x: x!=0, gen_usign_dataset(ceil(log(xlen,2)))))' + template: |- + + // $comment + // opcode:$inst; op1:$rs1; dest:$rs1 op1val:$rs1_val; immval:$imm_val + TEST_CI_OP( $inst, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +c.srai: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *c_regs + xlen: [32,64] + std_op: + isa: + - IC + formattype: 'cbformat' + operation: 'hex(rs1_val >> (imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen)' + imm_val_data: 'list(filter(lambda x: x!=0, gen_usign_dataset(ceil(log(xlen,2)))))' + template: |- + + // $comment + // opcode:$inst; op1:$rs1; dest:$rs1 op1val:$rs1_val; immval:$imm_val + TEST_CI_OP( $inst, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +c.li: + sig: + stride: 1 + sz: 'XLEN/8' + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IC + formattype: 'ciformat' + operation : 'hex(sign_extend(imm_val,6))' + imm_val_data: 'gen_sign_dataset(6)' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)' + template: |- + + // $comment + // opcode:$inst; dest:$rd; immval:$imm_val + TEST_CASE($testreg, $rd, $correctval, $swreg, $offset, $inst $rd, $imm_val;) + +c.lui: + sig: + stride: 1 + sz: 'XLEN/8' + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IC + formattype: 'ciformat' + operation: 'hex(sign_extend(imm_val << 12,32))' + rs1_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: 'list(filter(lambda x: x!=0 ,gen_usign_dataset(6)))' + template: |- + + // $comment + // opcode:$inst; op1:$rd; dest:$rd op1val:$rs1_val; immval:$imm_val + TEST_CI_OP( $inst, $rd, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +c.sw: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *c_regs + rs2_op_data: *c_regs + xlen: [32,64] + std_op: + isa: + - IC + formattype: 'csformat' + rs1_val_data: '[0]' + rs2_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: '[x*4 for x in gen_usign_dataset(5)]' + template: |- + + // $comment + // opcode:$inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val + TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,0) + +c.sd: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *c_regs + rs2_op_data: *c_regs + xlen: [64] + std_op: + isa: + - IC + formattype: 'csformat' + rs1_val_data: '[0]' + rs2_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: '[x*8 for x in gen_usign_dataset(5)]' + template: |- + + // $comment + // opcode:$inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val + TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,0) + +c.ld: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *c_regs + rd_op_data: *c_regs + xlen: [64] + std_op: + isa: + - IC + formattype: 'clformat' + rs1_val_data: '[0]' + imm_val_data: '[x*8 for x in gen_usign_dataset(5)]' + template: |- + + // $comment + // opcode: $inst; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,$rs1_val) + +c.lw: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *c_regs + rd_op_data: *c_regs + xlen: [32,64] + std_op: + isa: + - IC + formattype: 'clformat' + rs1_val_data: '[0]' + imm_val_data: '[x*4 for x in gen_usign_dataset(5)]' + template: |- + + // $comment + // opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val + TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,0) + +c.lwsp: + sig: + stride: 1 + sz: 'XLEN/8' + rd_op_data: *all_regs_mx0 + xlen: [32,64] + std_op: + isa: + - IC + formattype: 'ciformat' + imm_val_data: '[x*4 for x in gen_usign_dataset(6)]' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val + TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,0) + +c.ldsp: + sig: + stride: 1 + sz: 'XLEN/8' + rd_op_data: *all_regs_mx0 + xlen: [64] + std_op: + isa: + - IC + formattype: 'ciformat' + imm_val_data: '[x*8 for x in gen_usign_dataset(6)]' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst; op1:x2; dest:$rd; immval:$imm_val + TEST_LOAD($swreg,$testreg,$index,x2,$rd,$imm_val,$offset,$inst,0) + +c.swsp: + sig: + stride: 1 + sz: 'XLEN/8' + rs2_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IC + formattype: 'cssformat' + rs2_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: '[x*4 for x in gen_usign_dataset(6)]' + template: |- + + // $comment + // opcode:$inst; op1:x2; op2:$rs2; op2val:$rs2_val; immval:$imm_val + TEST_STORE($swreg,$testreg,$index,x2,$rs2,$rs2_val,$imm_val,$offset,$inst,0) + +c.sdsp: + sig: + stride: 1 + sz: 'XLEN/8' + rs2_op_data: *all_regs + xlen: [64] + std_op: + isa: + - IC + formattype: 'cssformat' + rs2_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: '[x*8 for x in gen_usign_dataset(6)]' + template: |- + + // $comment + // opcode:$inst; op1:x2; op2:$rs2; op2val:$rs2_val; immval:$imm_val + TEST_STORE($swreg,$testreg,$index,x2,$rs2,$rs2_val,$imm_val,$offset,$inst,0) + +c.beqz: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *c_regs + xlen: [32,64] + std_op: + isa: + - IC + formattype: 'cbformat' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen)' + imm_val_data: 'list(filter(lambda x: (x >=4 and x<250) or (x<=-4 and x>=-250),[x*2 for x in gen_sign_dataset(8)]))' + template: |- + + // $comment + // opcode:$inst; op1:$rs1; op1val:$rs1_val; immval:$imm_val + TEST_CBRANCH_OP($inst, $testreg, $rs1, $rs1_val, $imm_val, $label, $swreg, $offset) + +c.bnez: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *c_regs + xlen: [32,64] + std_op: + isa: + - IC + formattype: 'cbformat' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)' + imm_val_data: 'list(filter(lambda x: (x >=4 and x<250) if x>0 else (x<=-4 and x>=-250),[x*2 for x in gen_sign_dataset(8)]))' + template: |- + + // $comment + // opcode: $inst; op1:$rs1; op1val:$rs1_val; immval:$imm_val + TEST_CBRANCH_OP($inst, $testreg, $rs1, $rs1_val, $imm_val, $label, $swreg, $offset) + +c.j: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IC + formattype: 'cjformat' + imm_val_data: 'list(filter(lambda x: (x >=4 and x<2030) if x>0 else (x<=-4 and x> -2030 ),[x*2 for x in gen_sign_dataset(11)]))' + template: |- + + // $comment + // opcode:$inst; immval:$imm_val + TEST_CJ_OP($inst, $testreg, $imm_val, $label, $swreg, $offset) + +c.jal: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IC + formattype: 'cbformat' + imm_val_data: 'list(filter(lambda x: (x >=4 and x<2030) if x>0 else (x<=-4 and x> -2030 ),[x*2 for x in gen_sign_dataset(11)]))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)' + template: |- + + // $comment + // opcode:$inst; immval:$imm_val + TEST_CJAL_OP($inst, $testreg, $imm_val, $label, $swreg, $offset) + +c.jr: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs_mx0 + xlen: [32,64] + std_op: + isa: + - IC + formattype: 'crformat' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)' + template: |- + + // $comment + // opcode: c.jr; op1:$rs1 + TEST_CJR_OP($testreg, $rs1, $swreg, $offset) + +c.jalr: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs_mx0 + xlen: [32,64] + std_op: + isa: + - IC + formattype: 'crformat' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)' + template: |- + + // $comment + // opcode: c.jalr; op1:$rs1 + TEST_CJALR_OP($testreg, $rs1, $swreg, $offset) + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/data/template.yaml b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/data/template.yaml new file mode 100644 index 000000000..7910d20c6 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/data/template.yaml @@ -0,0 +1,12662 @@ +# See LICENSE.incore for details +metadata: + all_regs: &all_regs "['x'+str(x) for x in range(0,32 if 'e' not in base_isa else 16)]" + all_fregs: &all_fregs "['f'+str(x) for x in range(0,32 if 'e' not in base_isa else 16)]" + all_regs_mx0: &all_regs_mx0 "['x'+str(x) for x in range(1,32 if 'e' not in base_isa else 16)]" + c_regs: &c_regs "['x'+str(x) for x in range(8,16)]" + pair_regs: &pair_regs "['x'+str(x) for x in range(2,32 if 'e' not in base_isa else 16, 2 if xlen == 32 else 1)]" + rv32rv64pair_regs: &rv32rv64pair_regs "['x'+str(x) for x in range(2,30 if 'e' not in base_isa else 16, 2)]" + +aes32dsi: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))' + xlen: [32] + std_op: + isa: + - IZk + - IZkn + - IZknd + formattype: 'bsformat' + template: |- + + // $comment + // opcode: $inst; rd:$rd; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; immval:$imm_val + TEST_RRI_OP($inst, $rd, $rs1, $rs2, $imm_val, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +aes32dsmi: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))' + xlen: [32] + std_op: + isa: + - IZk + - IZkn + - IZknd + formattype: 'bsformat' + template: |- + + // $comment + // opcode: $inst; rd:$rd; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; immval:$imm_val + TEST_RRI_OP($inst, $rd, $rs1, $rs2, $imm_val, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +aes32esi: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))' + xlen: [32] + std_op: + isa: + - IZk + - IZkn + - IZkne + formattype: 'bsformat' + template: |- + + // $comment + // opcode: $inst; rd:$rd; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; immval:$imm_val + TEST_RRI_OP($inst, $rd, $rs1, $rs2, $imm_val, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +aes32esmi: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))' + xlen: [32] + std_op: + isa: + - IZk + - IZkn + - IZkne + formattype: 'bsformat' + template: |- + + // $comment + // opcode: $inst; rd:$rd; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; immval:$imm_val + TEST_RRI_OP($inst, $rd, $rs1, $rs2, $imm_val, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +sm4ed: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))' + xlen: [32,64] + std_op: + isa: + - IZks + - IZksed + formattype: 'bsformat' + template: |- + + // $comment + // opcode: $inst; rd:$rd; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; immval:$imm_val + TEST_RRI_OP($inst, $rd, $rs1, $rs2, $imm_val, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +sm4ks: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))' + xlen: [32,64] + std_op: + isa: + - IZks + - IZksed + formattype: 'bsformat' + template: |- + + // $comment + // opcode: $inst; rd:$rd; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; immval:$imm_val + TEST_RRI_OP($inst, $rd, $rs1, $rs2, $imm_val, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +sha256sig0: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZk + - IZkn + - IZknh + formattype: 'kformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + LI($rs1,$rs1_val) + sha256sig0 $rd, $rs1 + SREG $rd, $offset($swreg) + RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval) + +sha256sig1: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZk + - IZkn + - IZknh + formattype: 'kformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + LI($rs1,$rs1_val) + sha256sig1 $rd, $rs1 + SREG $rd, $offset($swreg) + RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval) + +sha256sum0: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZk + - IZkn + - IZknh + formattype: 'kformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + LI($rs1,$rs1_val) + sha256sum0 $rd, $rs1 + SREG $rd, $offset($swreg) + RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval) + +sha256sum1: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZk + - IZkn + - IZknh + formattype: 'kformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + LI($rs1,$rs1_val) + sha256sum1 $rd, $rs1 + SREG $rd, $offset($swreg) + RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval) + +sm3p0: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZks + - IZksh + formattype: 'kformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + LI($rs1,$rs1_val) + sm3p0 $rd, $rs1 + SREG $rd, $offset($swreg) + RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval) + +sm3p1: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZks + - IZksh + formattype: 'kformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + LI($rs1,$rs1_val) + sm3p1 $rd, $rs1 + SREG $rd, $offset($swreg) + RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval) + +sha512sig0h: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32] + std_op: + isa: + - IZk + - IZkn + - IZknh + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +sha512sig0l: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32] + std_op: + isa: + - IZk + - IZkn + - IZknh + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +sha512sig1h: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32] + std_op: + isa: + - IZk + - IZkn + - IZknh + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +sha512sig1l: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32] + std_op: + isa: + - IZk + - IZkn + - IZknh + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +sha512sum0r: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32] + std_op: + isa: + - IZk + - IZkn + - IZknh + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +sha512sum1r: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32] + std_op: + isa: + - IZk + - IZkn + - IZknh + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +rol: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + operation: 'hex((rs1_val << (rs2_val%xlen)) & (2**(xlen)-1))' + isa: + - IZbb + - IZbkb + - IZk + - IZkn + - IZks + - IB + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +rev.b: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: grevi + isa: + - I + formattype: 'kformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + LI($rs1,$rs1_val) + grevi $rd, $rs1, 7 + SREG $rd, $offset($swreg) + RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval) + +zip: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32] + std_op: shfli + isa: + - IZk + - IZbkb + - IZkn + - IZks + formattype: 'kformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + LI($rs1,$rs1_val) + zip $rd, $rs1 + SREG $rd, $offset($swreg) + RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval) + +unzip: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32] + std_op: unshfli + isa: + - IZk + - IZbkb + - IZkn + - IZks + formattype: 'kformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + LI($rs1,$rs1_val) + unzip $rd, $rs1 + SREG $rd, $offset($swreg) + RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval) + +pack: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZk + - IZbkb + - IZkn + - IZks + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +packu: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - I + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +packh: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZk + - IZbkb + - IZkn + - IZks + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +xperm.n: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - I + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +xperm.b: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - I + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +aes64ds: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IZk + - IZkn + - IZknd + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +aes64dsm: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IZk + - IZkn + - IZknd + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +aes64es: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IZk + - IZkn + - IZkne + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +aes64esm: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IZk + - IZkn + - IZkne + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +aes64ks1i: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IZk + - IZkn + - IZknd + - IZkne + formattype: 'iformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + imm_val_data: 'gen_usign_dataset(ceil(log(xlen,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +aes64ks2: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IZk + - IZkn + - IZknd + - IZkne + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +sha512sig0: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IZk + - IZkn + - IZknh + formattype: 'kformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + LI($rs1,$rs1_val) + sha512sig0 $rd, $rs1 + SREG $rd, $offset($swreg) + RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval) + +sha512sig1: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IZk + - IZkn + - IZknh + formattype: 'kformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + LI($rs1,$rs1_val) + sha512sig1 $rd, $rs1 + SREG $rd, $offset($swreg) + RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval) + +sha512sum0: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IZk + - IZkn + - IZknh + formattype: 'kformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + LI($rs1,$rs1_val) + sha512sum0 $rd, $rs1 + SREG $rd, $offset($swreg) + RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval) + +sha512sum1: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IZk + - IZkn + - IZknh + formattype: 'kformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + LI($rs1,$rs1_val) + sha512sum1 $rd, $rs1 + SREG $rd, $offset($swreg) + RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval) + +aes64im: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IZk + - IZkn + - IZknd + formattype: 'kformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + LI($rs1,$rs1_val) + aes64im $rd, $rs1 + SREG $rd, $offset($swreg) + RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval) + +rolw: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IZbb + - IZbkb + - IZk + - IZkn + - IZks + - IB + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +rev8.w: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: grevi + isa: + - I + formattype: 'kformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + LI($rs1,$rs1_val) + grevi $rd, $rs1, 24 + SREG $rd, $offset($swreg) + RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval) + +packw: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IZk + - IZbkb + - IZkn + - IZks + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +packuw: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - I + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +add.uw: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IZba + - IB + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_bitmanip_dataset(xlen,False)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_bitmanip_dataset(xlen,False)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +sh1add: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZba + - IB + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen) + gen_bitmanip_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_bitmanip_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +sh1add.uw: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IZba + - IB + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)' + rs2_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +sh2add: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZba + - IB + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_bitmanip_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_bitmanip_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +sh2add.uw: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IZba + - IB + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)' + rs2_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +sh3add: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZba + - IB + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_bitmanip_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_bitmanip_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +sh3add.uw: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IZba + - IB + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)' + rs2_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +slli.uw: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IZba + - IB + formattype: 'iformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + operation: 'hex(sign_extend((rs1_val << imm_val) , 32))' + rs1_val_data: 'gen_usign_dataset(xlen)+ gen_bitmanip_dataset(xlen,False)' + imm_val_data: 'gen_usign_dataset(5)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +andn: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZbb + - IZbkb + - IZk + - IZkn + - IZks + - IB + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + operation: 'hex((rs1_val & rs2_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)' + rs2_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +# 3.1.1. 16-bit Addition & Subtraction Instructions + +add16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +radd16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +uradd16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + rs2_h0_val_data: 'gen_usign_dataset(16)' + rs2_h1_val_data: 'gen_usign_dataset(16)' + rs2_h2_val_data: 'gen_usign_dataset(16)' + rs2_h3_val_data: 'gen_usign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +kadd16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +ukadd16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + rs2_h0_val_data: 'gen_usign_dataset(16)' + rs2_h1_val_data: 'gen_usign_dataset(16)' + rs2_h2_val_data: 'gen_usign_dataset(16)' + rs2_h3_val_data: 'gen_usign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +sub16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + + +rsub16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + + +ursub16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + rs2_h0_val_data: 'gen_usign_dataset(16)' + rs2_h1_val_data: 'gen_usign_dataset(16)' + rs2_h2_val_data: 'gen_usign_dataset(16)' + rs2_h3_val_data: 'gen_usign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +ksub16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +uksub16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + rs2_h0_val_data: 'gen_usign_dataset(16)' + rs2_h1_val_data: 'gen_usign_dataset(16)' + rs2_h2_val_data: 'gen_usign_dataset(16)' + rs2_h3_val_data: 'gen_usign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +cras16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +rcras16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + + +urcras16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + rs2_h0_val_data: 'gen_usign_dataset(16)' + rs2_h1_val_data: 'gen_usign_dataset(16)' + rs2_h2_val_data: 'gen_usign_dataset(16)' + rs2_h3_val_data: 'gen_usign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +kcras16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +clz: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZbb + - IB + formattype: 'kformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_usign_dataset(xlen)+gen_sign_dataset(xlen)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +clzw: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IZbb + - IB + formattype: 'kformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +cpop: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZbb + - IB + formattype: 'kformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_usign_dataset(xlen)+gen_sign_dataset(xlen)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +cpopw: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IZbb + - IB + formattype: 'kformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +ctz: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZbb + - IB + formattype: 'kformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_usign_dataset(xlen)+gen_sign_dataset(xlen)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +ctzw: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IZbb + - IB + formattype: 'kformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_usign_dataset(xlen)+gen_sign_dataset(xlen)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +max: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZbb + - IB + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen) + gen_bitmanip_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_bitmanip_dataset(xlen,True)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +ukcras16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + rs2_h0_val_data: 'gen_usign_dataset(16)' + rs2_h1_val_data: 'gen_usign_dataset(16)' + rs2_h2_val_data: 'gen_usign_dataset(16)' + rs2_h3_val_data: 'gen_usign_dataset(16)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +maxu: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZbb + - IB + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)' + rs2_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +crsa16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +min: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZbb + - IB + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen) + gen_bitmanip_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_bitmanip_dataset(xlen,True)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +rcrsa16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +minu: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZbb + - IB + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)' + rs2_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +urcrsa16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + rs2_h0_val_data: 'gen_usign_dataset(16)' + rs2_h1_val_data: 'gen_usign_dataset(16)' + rs2_h2_val_data: 'gen_usign_dataset(16)' + rs2_h3_val_data: 'gen_usign_dataset(16)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +kcrsa16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +orc.b: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: orc.b + isa: + - IZbb + - IB + formattype: 'kformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)+[16909320,33818625,67633410,134283780,72624976414508040,145249888404506625,290483284134592770,576744443617542660]' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +orn: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZbb + - IZbkb + - IZk + - IZkn + - IZks + - IB + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)' + rs2_val_data: 'gen_usign_dataset(xlen) + gen_bitmanip_dataset(xlen,False)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +ukcrsa16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + rs2_h0_val_data: 'gen_usign_dataset(16)' + rs2_h1_val_data: 'gen_usign_dataset(16)' + rs2_h2_val_data: 'gen_usign_dataset(16)' + rs2_h3_val_data: 'gen_usign_dataset(16)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +stas16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +rstas16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +rev8: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: grevi + isa: + - IZbb + - IZbkb + - IZk + - IZkn + - IZks + - IB + formattype: 'kformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)+gen_bitmanip_dataset(xlen,False)+[16909320,33818625,67633410,134283780,72624976414508040,145249888404506625,290483284134592770,576744443617542660]' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + LI($rs1,$rs1_val) + rev8 $rd, $rs1 + RVTEST_SIGUPD($swreg,$rd,$offset) + RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval) + + +ror: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZbb + - IZbkb + - IZk + - IZkn + - IZks + - IB + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_usign_dataset(ceil(log(xlen,2)))' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +urstas16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + rs2_h0_val_data: 'gen_usign_dataset(16)' + rs2_h1_val_data: 'gen_usign_dataset(16)' + rs2_h2_val_data: 'gen_usign_dataset(16)' + rs2_h3_val_data: 'gen_usign_dataset(16)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +kstas16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +ukstas16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + rs2_h0_val_data: 'gen_usign_dataset(16)' + rs2_h1_val_data: 'gen_usign_dataset(16)' + rs2_h2_val_data: 'gen_usign_dataset(16)' + rs2_h3_val_data: 'gen_usign_dataset(16)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +rori: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZbb + - IZbkb + - IZk + - IZkn + - IZks + - IB + formattype: 'iformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_usign_dataset(ceil(log(xlen,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +roriw: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IZbb + - IZbkb + - IZk + - IZkn + - IZks + - IB + formattype: 'iformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_usign_dataset(ceil(log(xlen,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +rorw: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IZbb + - IZbkb + - IZk + - IZkn + - IZks + - IB + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)' + rs2_val_data: 'gen_usign_dataset(ceil(log(xlen,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +stsa16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +rstsa16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +urstsa16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + rs2_h0_val_data: 'gen_usign_dataset(16)' + rs2_h1_val_data: 'gen_usign_dataset(16)' + rs2_h2_val_data: 'gen_usign_dataset(16)' + rs2_h3_val_data: 'gen_usign_dataset(16)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +sext.b: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZbb + - IB + formattype: 'kformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +sext.h: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZbb + - IB + formattype: 'kformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)+[65408]' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +xnor: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZbb + - IZbkb + - IZk + - IZkn + - IZks + - IB + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_usign_dataset(xlen)+gen_bitmanip_dataset(xlen,False)' + rs2_val_data: 'gen_usign_dataset(xlen)+gen_bitmanip_dataset(xlen,False)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +kstsa16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +ukstsa16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + rs2_h0_val_data: 'gen_usign_dataset(16)' + rs2_h1_val_data: 'gen_usign_dataset(16)' + rs2_h2_val_data: 'gen_usign_dataset(16)' + rs2_h3_val_data: 'gen_usign_dataset(16)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +zext.h: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZbb + - IB + formattype: 'kformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_usign_dataset(xlen)+[65408]' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +clmul: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZbc + - IZbkc + - IZk + - IZkn + - IZks + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + + +# 3.1.2. 8-bit Addition & Subtraction Instructions + +add8: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + rs2_b0_val_data: 'gen_sign_dataset(8)' + rs2_b1_val_data: 'gen_sign_dataset(8)' + rs2_b2_val_data: 'gen_sign_dataset(8)' + rs2_b3_val_data: 'gen_sign_dataset(8)' + rs2_b4_val_data: 'gen_sign_dataset(8)' + rs2_b5_val_data: 'gen_sign_dataset(8)' + rs2_b6_val_data: 'gen_sign_dataset(8)' + rs2_b7_val_data: 'gen_sign_dataset(8)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +clmulh: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZbc + - IZbkc + - IZk + - IZkn + - IZks + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + + +radd8: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + rs2_b0_val_data: 'gen_sign_dataset(8)' + rs2_b1_val_data: 'gen_sign_dataset(8)' + rs2_b2_val_data: 'gen_sign_dataset(8)' + rs2_b3_val_data: 'gen_sign_dataset(8)' + rs2_b4_val_data: 'gen_sign_dataset(8)' + rs2_b5_val_data: 'gen_sign_dataset(8)' + rs2_b6_val_data: 'gen_sign_dataset(8)' + rs2_b7_val_data: 'gen_sign_dataset(8)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + + +clmulr: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZbc + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +uradd8: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_usign_dataset(8)' + rs1_b1_val_data: 'gen_usign_dataset(8)' + rs1_b2_val_data: 'gen_usign_dataset(8)' + rs1_b3_val_data: 'gen_usign_dataset(8)' + rs1_b4_val_data: 'gen_usign_dataset(8)' + rs1_b5_val_data: 'gen_usign_dataset(8)' + rs1_b6_val_data: 'gen_usign_dataset(8)' + rs1_b7_val_data: 'gen_usign_dataset(8)' + rs2_b0_val_data: 'gen_usign_dataset(8)' + rs2_b1_val_data: 'gen_usign_dataset(8)' + rs2_b2_val_data: 'gen_usign_dataset(8)' + rs2_b3_val_data: 'gen_usign_dataset(8)' + rs2_b4_val_data: 'gen_usign_dataset(8)' + rs2_b5_val_data: 'gen_usign_dataset(8)' + rs2_b6_val_data: 'gen_usign_dataset(8)' + rs2_b7_val_data: 'gen_usign_dataset(8)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +bclr: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZbs + - IB + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'zerotoxlen(xlen)+gen_usign_dataset(xlen)+[-1]' + rs2_val_data: 'zerotoxlen(xlen)+gen_usign_dataset(xlen)+[-1]' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + + +kadd8: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + rs2_b0_val_data: 'gen_sign_dataset(8)' + rs2_b1_val_data: 'gen_sign_dataset(8)' + rs2_b2_val_data: 'gen_sign_dataset(8)' + rs2_b3_val_data: 'gen_sign_dataset(8)' + rs2_b4_val_data: 'gen_sign_dataset(8)' + rs2_b5_val_data: 'gen_sign_dataset(8)' + rs2_b6_val_data: 'gen_sign_dataset(8)' + rs2_b7_val_data: 'gen_sign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +ukadd8: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_usign_dataset(8)' + rs1_b1_val_data: 'gen_usign_dataset(8)' + rs1_b2_val_data: 'gen_usign_dataset(8)' + rs1_b3_val_data: 'gen_usign_dataset(8)' + rs1_b4_val_data: 'gen_usign_dataset(8)' + rs1_b5_val_data: 'gen_usign_dataset(8)' + rs1_b6_val_data: 'gen_usign_dataset(8)' + rs1_b7_val_data: 'gen_usign_dataset(8)' + rs2_b0_val_data: 'gen_usign_dataset(8)' + rs2_b1_val_data: 'gen_usign_dataset(8)' + rs2_b2_val_data: 'gen_usign_dataset(8)' + rs2_b3_val_data: 'gen_usign_dataset(8)' + rs2_b4_val_data: 'gen_usign_dataset(8)' + rs2_b5_val_data: 'gen_usign_dataset(8)' + rs2_b6_val_data: 'gen_usign_dataset(8)' + rs2_b7_val_data: 'gen_usign_dataset(8)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +bclri: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZbs + - IB + formattype: 'iformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'zerotoxlen(xlen)+[-1]' + imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +bext: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZbs + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'zerotoxlen(xlen)+gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'zerotoxlen(xlen)+gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +sub8: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + rs2_b0_val_data: 'gen_sign_dataset(8)' + rs2_b1_val_data: 'gen_sign_dataset(8)' + rs2_b2_val_data: 'gen_sign_dataset(8)' + rs2_b3_val_data: 'gen_sign_dataset(8)' + rs2_b4_val_data: 'gen_sign_dataset(8)' + rs2_b5_val_data: 'gen_sign_dataset(8)' + rs2_b6_val_data: 'gen_sign_dataset(8)' + rs2_b7_val_data: 'gen_sign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +rsub8: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + rs2_b0_val_data: 'gen_sign_dataset(8)' + rs2_b1_val_data: 'gen_sign_dataset(8)' + rs2_b2_val_data: 'gen_sign_dataset(8)' + rs2_b3_val_data: 'gen_sign_dataset(8)' + rs2_b4_val_data: 'gen_sign_dataset(8)' + rs2_b5_val_data: 'gen_sign_dataset(8)' + rs2_b6_val_data: 'gen_sign_dataset(8)' + rs2_b7_val_data: 'gen_sign_dataset(8)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + + +bexti: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZbs + - IB + formattype: 'iformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'zerotoxlen(xlen)+gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +binv: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZbs + - IB + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'zerotoxlen(xlen)+gen_usign_dataset(xlen)+gen_sign_dataset(xlen)' + rs2_val_data: 'zerotoxlen(xlen)+gen_usign_dataset(xlen)+gen_sign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + + +ursub8: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_usign_dataset(8)' + rs1_b1_val_data: 'gen_usign_dataset(8)' + rs1_b2_val_data: 'gen_usign_dataset(8)' + rs1_b3_val_data: 'gen_usign_dataset(8)' + rs1_b4_val_data: 'gen_usign_dataset(8)' + rs1_b5_val_data: 'gen_usign_dataset(8)' + rs1_b6_val_data: 'gen_usign_dataset(8)' + rs1_b7_val_data: 'gen_usign_dataset(8)' + rs2_b0_val_data: 'gen_usign_dataset(8)' + rs2_b1_val_data: 'gen_usign_dataset(8)' + rs2_b2_val_data: 'gen_usign_dataset(8)' + rs2_b3_val_data: 'gen_usign_dataset(8)' + rs2_b4_val_data: 'gen_usign_dataset(8)' + rs2_b5_val_data: 'gen_usign_dataset(8)' + rs2_b6_val_data: 'gen_usign_dataset(8)' + rs2_b7_val_data: 'gen_usign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + + +ksub8: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + rs2_b0_val_data: 'gen_sign_dataset(8)' + rs2_b1_val_data: 'gen_sign_dataset(8)' + rs2_b2_val_data: 'gen_sign_dataset(8)' + rs2_b3_val_data: 'gen_sign_dataset(8)' + rs2_b4_val_data: 'gen_sign_dataset(8)' + rs2_b5_val_data: 'gen_sign_dataset(8)' + rs2_b6_val_data: 'gen_sign_dataset(8)' + rs2_b7_val_data: 'gen_sign_dataset(8)' + template: |- + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + + +binvi: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZbs + - IB + formattype: 'iformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'zerotoxlen(xlen)+gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +bset: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZbs + - IB + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'zerotoxlen(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'zerotoxlen(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +uksub8: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_usign_dataset(8)' + rs1_b1_val_data: 'gen_usign_dataset(8)' + rs1_b2_val_data: 'gen_usign_dataset(8)' + rs1_b3_val_data: 'gen_usign_dataset(8)' + rs1_b4_val_data: 'gen_usign_dataset(8)' + rs1_b5_val_data: 'gen_usign_dataset(8)' + rs1_b6_val_data: 'gen_usign_dataset(8)' + rs1_b7_val_data: 'gen_usign_dataset(8)' + rs2_b0_val_data: 'gen_usign_dataset(8)' + rs2_b1_val_data: 'gen_usign_dataset(8)' + rs2_b2_val_data: 'gen_usign_dataset(8)' + rs2_b3_val_data: 'gen_usign_dataset(8)' + rs2_b4_val_data: 'gen_usign_dataset(8)' + rs2_b5_val_data: 'gen_usign_dataset(8)' + rs2_b6_val_data: 'gen_usign_dataset(8)' + rs2_b7_val_data: 'gen_usign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +# 3.1.3. 16-bit Shift Instructions + +sra16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'pshrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_val_data: 'gen_usign_dataset(ceil(log(16,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +srai16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phriformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + imm_val_data: 'gen_imm_dataset(4)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +sra16.u: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'pshrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_val_data: 'gen_usign_dataset(ceil(log(16,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +srai16.u: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phriformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + imm_val_data: 'gen_imm_dataset(4)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +srl16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'pshrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + rs2_val_data: 'gen_usign_dataset(ceil(log(16,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +srli16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phriformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + imm_val_data: 'gen_imm_dataset(4)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +srl16.u: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'pshrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + rs2_val_data: 'gen_usign_dataset(ceil(log(16,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +srli16.u: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phriformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + imm_val_data: 'gen_imm_dataset(4)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +sll16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'pshrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + rs2_val_data: 'gen_usign_dataset(ceil(log(16,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +slli16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phriformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + imm_val_data: 'gen_imm_dataset(4)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +ksll16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'pshrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_val_data: 'gen_usign_dataset(ceil(log(16,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kslli16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phriformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + imm_val_data: 'gen_imm_dataset(4)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_PKIMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $rs1, $swreg, $offset, $testreg) + +kslra16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16,xlen + formattype: 'pshrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_val_data: 'gen_sign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kslra16.u: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16,xlen + formattype: 'pshrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + rs2_val_data: 'gen_sign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +# 3.1.4. 8-bit Shift Instructions + +sra8: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'psbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + rs2_val_data: 'gen_usign_dataset(ceil(log(8,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +srai8: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbriformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + imm_val_data: 'gen_imm_dataset(3)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +sra8.u: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'psbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + rs2_val_data: 'gen_usign_dataset(ceil(log(8,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +srai8.u: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbriformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + imm_val_data: 'gen_imm_dataset(3)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +srl8: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'psbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_usign_dataset(8)' + rs1_b1_val_data: 'gen_usign_dataset(8)' + rs1_b2_val_data: 'gen_usign_dataset(8)' + rs1_b3_val_data: 'gen_usign_dataset(8)' + rs1_b4_val_data: 'gen_usign_dataset(8)' + rs1_b5_val_data: 'gen_usign_dataset(8)' + rs1_b6_val_data: 'gen_usign_dataset(8)' + rs1_b7_val_data: 'gen_usign_dataset(8)' + rs2_val_data: 'gen_usign_dataset(ceil(log(8,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +srli8: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbriformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_usign_dataset(8)' + rs1_b1_val_data: 'gen_usign_dataset(8)' + rs1_b2_val_data: 'gen_usign_dataset(8)' + rs1_b3_val_data: 'gen_usign_dataset(8)' + rs1_b4_val_data: 'gen_usign_dataset(8)' + rs1_b5_val_data: 'gen_usign_dataset(8)' + rs1_b6_val_data: 'gen_usign_dataset(8)' + rs1_b7_val_data: 'gen_usign_dataset(8)' + imm_val_data: 'gen_imm_dataset(3)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +srl8.u: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'psbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_usign_dataset(8)' + rs1_b1_val_data: 'gen_usign_dataset(8)' + rs1_b2_val_data: 'gen_usign_dataset(8)' + rs1_b3_val_data: 'gen_usign_dataset(8)' + rs1_b4_val_data: 'gen_usign_dataset(8)' + rs1_b5_val_data: 'gen_usign_dataset(8)' + rs1_b6_val_data: 'gen_usign_dataset(8)' + rs1_b7_val_data: 'gen_usign_dataset(8)' + rs2_val_data: 'gen_usign_dataset(ceil(log(8,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +srli8.u: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbriformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_usign_dataset(8)' + rs1_b1_val_data: 'gen_usign_dataset(8)' + rs1_b2_val_data: 'gen_usign_dataset(8)' + rs1_b3_val_data: 'gen_usign_dataset(8)' + rs1_b4_val_data: 'gen_usign_dataset(8)' + rs1_b5_val_data: 'gen_usign_dataset(8)' + rs1_b6_val_data: 'gen_usign_dataset(8)' + rs1_b7_val_data: 'gen_usign_dataset(8)' + imm_val_data: 'gen_imm_dataset(3)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +sll8: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'psbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_usign_dataset(8)' + rs1_b1_val_data: 'gen_usign_dataset(8)' + rs1_b2_val_data: 'gen_usign_dataset(8)' + rs1_b3_val_data: 'gen_usign_dataset(8)' + rs1_b4_val_data: 'gen_usign_dataset(8)' + rs1_b5_val_data: 'gen_usign_dataset(8)' + rs1_b6_val_data: 'gen_usign_dataset(8)' + rs1_b7_val_data: 'gen_usign_dataset(8)' + rs2_val_data: 'gen_usign_dataset(ceil(log(8,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +slli8: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbriformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_usign_dataset(8)' + rs1_b1_val_data: 'gen_usign_dataset(8)' + rs1_b2_val_data: 'gen_usign_dataset(8)' + rs1_b3_val_data: 'gen_usign_dataset(8)' + rs1_b4_val_data: 'gen_usign_dataset(8)' + rs1_b5_val_data: 'gen_usign_dataset(8)' + rs1_b6_val_data: 'gen_usign_dataset(8)' + rs1_b7_val_data: 'gen_usign_dataset(8)' + imm_val_data: 'gen_imm_dataset(3)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +ksll8: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'psbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + rs2_val_data: 'gen_usign_dataset(ceil(log(8,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kslli8: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbriformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + imm_val_data: 'gen_imm_dataset(3)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_PKIMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $rs1, $swreg, $offset, $testreg) + +kslra8: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8,xlen + formattype: 'psbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + rs2_val_data: 'gen_sign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kslra8.u: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8,xlen + formattype: 'psbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_usign_dataset(8)' + rs1_b1_val_data: 'gen_usign_dataset(8)' + rs1_b2_val_data: 'gen_usign_dataset(8)' + rs1_b3_val_data: 'gen_usign_dataset(8)' + rs1_b4_val_data: 'gen_usign_dataset(8)' + rs1_b5_val_data: 'gen_usign_dataset(8)' + rs1_b6_val_data: 'gen_usign_dataset(8)' + rs1_b7_val_data: 'gen_usign_dataset(8)' + rs2_val_data: 'gen_sign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +# 3.1.5. 16-bit Compare Instructions + +cmpeq16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +scmplt16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +scmple16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +ucmplt16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + rs2_h0_val_data: 'gen_usign_dataset(16)' + rs2_h1_val_data: 'gen_usign_dataset(16)' + rs2_h2_val_data: 'gen_usign_dataset(16)' + rs2_h3_val_data: 'gen_usign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +ucmple16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + rs2_h0_val_data: 'gen_usign_dataset(16)' + rs2_h1_val_data: 'gen_usign_dataset(16)' + rs2_h2_val_data: 'gen_usign_dataset(16)' + rs2_h3_val_data: 'gen_usign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +# 3.1.6. 8-bit Compare Instructions + +cmpeq8: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + rs2_b0_val_data: 'gen_sign_dataset(8)' + rs2_b1_val_data: 'gen_sign_dataset(8)' + rs2_b2_val_data: 'gen_sign_dataset(8)' + rs2_b3_val_data: 'gen_sign_dataset(8)' + rs2_b4_val_data: 'gen_sign_dataset(8)' + rs2_b5_val_data: 'gen_sign_dataset(8)' + rs2_b6_val_data: 'gen_sign_dataset(8)' + rs2_b7_val_data: 'gen_sign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +scmplt8: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + rs2_b0_val_data: 'gen_sign_dataset(8)' + rs2_b1_val_data: 'gen_sign_dataset(8)' + rs2_b2_val_data: 'gen_sign_dataset(8)' + rs2_b3_val_data: 'gen_sign_dataset(8)' + rs2_b4_val_data: 'gen_sign_dataset(8)' + rs2_b5_val_data: 'gen_sign_dataset(8)' + rs2_b6_val_data: 'gen_sign_dataset(8)' + rs2_b7_val_data: 'gen_sign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +scmple8: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + rs2_b0_val_data: 'gen_sign_dataset(8)' + rs2_b1_val_data: 'gen_sign_dataset(8)' + rs2_b2_val_data: 'gen_sign_dataset(8)' + rs2_b3_val_data: 'gen_sign_dataset(8)' + rs2_b4_val_data: 'gen_sign_dataset(8)' + rs2_b5_val_data: 'gen_sign_dataset(8)' + rs2_b6_val_data: 'gen_sign_dataset(8)' + rs2_b7_val_data: 'gen_sign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +ucmplt8: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_usign_dataset(8)' + rs1_b1_val_data: 'gen_usign_dataset(8)' + rs1_b2_val_data: 'gen_usign_dataset(8)' + rs1_b3_val_data: 'gen_usign_dataset(8)' + rs1_b4_val_data: 'gen_usign_dataset(8)' + rs1_b5_val_data: 'gen_usign_dataset(8)' + rs1_b6_val_data: 'gen_usign_dataset(8)' + rs1_b7_val_data: 'gen_usign_dataset(8)' + rs2_b0_val_data: 'gen_usign_dataset(8)' + rs2_b1_val_data: 'gen_usign_dataset(8)' + rs2_b2_val_data: 'gen_usign_dataset(8)' + rs2_b3_val_data: 'gen_usign_dataset(8)' + rs2_b4_val_data: 'gen_usign_dataset(8)' + rs2_b5_val_data: 'gen_usign_dataset(8)' + rs2_b6_val_data: 'gen_usign_dataset(8)' + rs2_b7_val_data: 'gen_usign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +ucmple8: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_usign_dataset(8)' + rs1_b1_val_data: 'gen_usign_dataset(8)' + rs1_b2_val_data: 'gen_usign_dataset(8)' + rs1_b3_val_data: 'gen_usign_dataset(8)' + rs1_b4_val_data: 'gen_usign_dataset(8)' + rs1_b5_val_data: 'gen_usign_dataset(8)' + rs1_b6_val_data: 'gen_usign_dataset(8)' + rs1_b7_val_data: 'gen_usign_dataset(8)' + rs2_b0_val_data: 'gen_usign_dataset(8)' + rs2_b1_val_data: 'gen_usign_dataset(8)' + rs2_b2_val_data: 'gen_usign_dataset(8)' + rs2_b3_val_data: 'gen_usign_dataset(8)' + rs2_b4_val_data: 'gen_usign_dataset(8)' + rs2_b5_val_data: 'gen_usign_dataset(8)' + rs2_b6_val_data: 'gen_usign_dataset(8)' + rs2_b7_val_data: 'gen_usign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +# 3.1.7. 16-bit Multiply Instructions + +smul16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + p64_profile: 'pnn' + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *pair_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +smulx16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + p64_profile: 'pnn' + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *pair_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +umul16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + p64_profile: 'pnn' + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *pair_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + rs2_h0_val_data: 'gen_usign_dataset(16)' + rs2_h1_val_data: 'gen_usign_dataset(16)' + rs2_h2_val_data: 'gen_usign_dataset(16)' + rs2_h3_val_data: 'gen_usign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +umulx16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + p64_profile: 'pnn' + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *pair_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + rs2_h0_val_data: 'gen_usign_dataset(16)' + rs2_h1_val_data: 'gen_usign_dataset(16)' + rs2_h2_val_data: 'gen_usign_dataset(16)' + rs2_h3_val_data: 'gen_usign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +khm16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +khmx16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +# 3.1.8. 8-bit Multiply Instructions + +smul8: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + p64_profile: 'pnn' + formattype: 'pbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *pair_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + rs2_b0_val_data: 'gen_sign_dataset(8)' + rs2_b1_val_data: 'gen_sign_dataset(8)' + rs2_b2_val_data: 'gen_sign_dataset(8)' + rs2_b3_val_data: 'gen_sign_dataset(8)' + rs2_b4_val_data: 'gen_sign_dataset(8)' + rs2_b5_val_data: 'gen_sign_dataset(8)' + rs2_b6_val_data: 'gen_sign_dataset(8)' + rs2_b7_val_data: 'gen_sign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +smulx8: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + p64_profile: 'pnn' + formattype: 'pbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *pair_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + rs2_b0_val_data: 'gen_sign_dataset(8)' + rs2_b1_val_data: 'gen_sign_dataset(8)' + rs2_b2_val_data: 'gen_sign_dataset(8)' + rs2_b3_val_data: 'gen_sign_dataset(8)' + rs2_b4_val_data: 'gen_sign_dataset(8)' + rs2_b5_val_data: 'gen_sign_dataset(8)' + rs2_b6_val_data: 'gen_sign_dataset(8)' + rs2_b7_val_data: 'gen_sign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +umul8: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + p64_profile: 'pnn' + formattype: 'pbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *pair_regs + rs1_b0_val_data: 'gen_usign_dataset(8)' + rs1_b1_val_data: 'gen_usign_dataset(8)' + rs1_b2_val_data: 'gen_usign_dataset(8)' + rs1_b3_val_data: 'gen_usign_dataset(8)' + rs1_b4_val_data: 'gen_usign_dataset(8)' + rs1_b5_val_data: 'gen_usign_dataset(8)' + rs1_b6_val_data: 'gen_usign_dataset(8)' + rs1_b7_val_data: 'gen_usign_dataset(8)' + rs2_b0_val_data: 'gen_usign_dataset(8)' + rs2_b1_val_data: 'gen_usign_dataset(8)' + rs2_b2_val_data: 'gen_usign_dataset(8)' + rs2_b3_val_data: 'gen_usign_dataset(8)' + rs2_b4_val_data: 'gen_usign_dataset(8)' + rs2_b5_val_data: 'gen_usign_dataset(8)' + rs2_b6_val_data: 'gen_usign_dataset(8)' + rs2_b7_val_data: 'gen_usign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +umulx8: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + p64_profile: 'pnn' + formattype: 'pbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *pair_regs + rs1_b0_val_data: 'gen_usign_dataset(8)' + rs1_b1_val_data: 'gen_usign_dataset(8)' + rs1_b2_val_data: 'gen_usign_dataset(8)' + rs1_b3_val_data: 'gen_usign_dataset(8)' + rs1_b4_val_data: 'gen_usign_dataset(8)' + rs1_b5_val_data: 'gen_usign_dataset(8)' + rs1_b6_val_data: 'gen_usign_dataset(8)' + rs1_b7_val_data: 'gen_usign_dataset(8)' + rs2_b0_val_data: 'gen_usign_dataset(8)' + rs2_b1_val_data: 'gen_usign_dataset(8)' + rs2_b2_val_data: 'gen_usign_dataset(8)' + rs2_b3_val_data: 'gen_usign_dataset(8)' + rs2_b4_val_data: 'gen_usign_dataset(8)' + rs2_b5_val_data: 'gen_usign_dataset(8)' + rs2_b6_val_data: 'gen_usign_dataset(8)' + rs2_b7_val_data: 'gen_usign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +khm8: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + rs2_b0_val_data: 'gen_sign_dataset(8)' + rs2_b1_val_data: 'gen_sign_dataset(8)' + rs2_b2_val_data: 'gen_sign_dataset(8)' + rs2_b3_val_data: 'gen_sign_dataset(8)' + rs2_b4_val_data: 'gen_sign_dataset(8)' + rs2_b5_val_data: 'gen_sign_dataset(8)' + rs2_b6_val_data: 'gen_sign_dataset(8)' + rs2_b7_val_data: 'gen_sign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +khmx8: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + rs2_b0_val_data: 'gen_sign_dataset(8)' + rs2_b1_val_data: 'gen_sign_dataset(8)' + rs2_b2_val_data: 'gen_sign_dataset(8)' + rs2_b3_val_data: 'gen_sign_dataset(8)' + rs2_b4_val_data: 'gen_sign_dataset(8)' + rs2_b5_val_data: 'gen_sign_dataset(8)' + rs2_b6_val_data: 'gen_sign_dataset(8)' + rs2_b7_val_data: 'gen_sign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +# 3.1.9. 16-bit Misc Instructions + +smin16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +umin16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + rs2_h0_val_data: 'gen_usign_dataset(16)' + rs2_h1_val_data: 'gen_usign_dataset(16)' + rs2_h2_val_data: 'gen_usign_dataset(16)' + rs2_h3_val_data: 'gen_usign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +smax16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +umax16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + rs2_h0_val_data: 'gen_usign_dataset(16)' + rs2_h1_val_data: 'gen_usign_dataset(16)' + rs2_h2_val_data: 'gen_usign_dataset(16)' + rs2_h3_val_data: 'gen_usign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +sclip16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phriformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + imm_val_data: 'gen_imm_dataset(4)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_PKIMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $rs1, $swreg, $offset, $testreg) + +uclip16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phriformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + imm_val_data: 'gen_imm_dataset(4)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_PKIMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $rs1, $swreg, $offset, $testreg) + +kabs16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_PKR_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $rs1, $swreg, $offset, $testreg) + +clrs16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +clz16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +swap16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +# 3.1.10. 8-bit Misc Instructions + +smin8: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + rs2_b0_val_data: 'gen_sign_dataset(8)' + rs2_b1_val_data: 'gen_sign_dataset(8)' + rs2_b2_val_data: 'gen_sign_dataset(8)' + rs2_b3_val_data: 'gen_sign_dataset(8)' + rs2_b4_val_data: 'gen_sign_dataset(8)' + rs2_b5_val_data: 'gen_sign_dataset(8)' + rs2_b6_val_data: 'gen_sign_dataset(8)' + rs2_b7_val_data: 'gen_sign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +umin8: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_usign_dataset(8)' + rs1_b1_val_data: 'gen_usign_dataset(8)' + rs1_b2_val_data: 'gen_usign_dataset(8)' + rs1_b3_val_data: 'gen_usign_dataset(8)' + rs1_b4_val_data: 'gen_usign_dataset(8)' + rs1_b5_val_data: 'gen_usign_dataset(8)' + rs1_b6_val_data: 'gen_usign_dataset(8)' + rs1_b7_val_data: 'gen_usign_dataset(8)' + rs2_b0_val_data: 'gen_usign_dataset(8)' + rs2_b1_val_data: 'gen_usign_dataset(8)' + rs2_b2_val_data: 'gen_usign_dataset(8)' + rs2_b3_val_data: 'gen_usign_dataset(8)' + rs2_b4_val_data: 'gen_usign_dataset(8)' + rs2_b5_val_data: 'gen_usign_dataset(8)' + rs2_b6_val_data: 'gen_usign_dataset(8)' + rs2_b7_val_data: 'gen_usign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +smax8: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + rs2_b0_val_data: 'gen_sign_dataset(8)' + rs2_b1_val_data: 'gen_sign_dataset(8)' + rs2_b2_val_data: 'gen_sign_dataset(8)' + rs2_b3_val_data: 'gen_sign_dataset(8)' + rs2_b4_val_data: 'gen_sign_dataset(8)' + rs2_b5_val_data: 'gen_sign_dataset(8)' + rs2_b6_val_data: 'gen_sign_dataset(8)' + rs2_b7_val_data: 'gen_sign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +umax8: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_usign_dataset(8)' + rs1_b1_val_data: 'gen_usign_dataset(8)' + rs1_b2_val_data: 'gen_usign_dataset(8)' + rs1_b3_val_data: 'gen_usign_dataset(8)' + rs1_b4_val_data: 'gen_usign_dataset(8)' + rs1_b5_val_data: 'gen_usign_dataset(8)' + rs1_b6_val_data: 'gen_usign_dataset(8)' + rs1_b7_val_data: 'gen_usign_dataset(8)' + rs2_b0_val_data: 'gen_usign_dataset(8)' + rs2_b1_val_data: 'gen_usign_dataset(8)' + rs2_b2_val_data: 'gen_usign_dataset(8)' + rs2_b3_val_data: 'gen_usign_dataset(8)' + rs2_b4_val_data: 'gen_usign_dataset(8)' + rs2_b5_val_data: 'gen_usign_dataset(8)' + rs2_b6_val_data: 'gen_usign_dataset(8)' + rs2_b7_val_data: 'gen_usign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +kabs8: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_PKR_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $rs1, $swreg, $offset, $testreg) + +sclip8: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbriformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + imm_val_data: 'gen_imm_dataset(3)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_PKIMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $rs1, $swreg, $offset, $testreg) + +uclip8: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbriformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_usign_dataset(8)' + rs1_b1_val_data: 'gen_usign_dataset(8)' + rs1_b2_val_data: 'gen_usign_dataset(8)' + rs1_b3_val_data: 'gen_usign_dataset(8)' + rs1_b4_val_data: 'gen_usign_dataset(8)' + rs1_b5_val_data: 'gen_usign_dataset(8)' + rs1_b6_val_data: 'gen_usign_dataset(8)' + rs1_b7_val_data: 'gen_usign_dataset(8)' + imm_val_data: 'gen_imm_dataset(3)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_PKIMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $rs1, $swreg, $offset, $testreg) + +clrs8: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +clz8: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_usign_dataset(8)' + rs1_b1_val_data: 'gen_usign_dataset(8)' + rs1_b2_val_data: 'gen_usign_dataset(8)' + rs1_b3_val_data: 'gen_usign_dataset(8)' + rs1_b4_val_data: 'gen_usign_dataset(8)' + rs1_b5_val_data: 'gen_usign_dataset(8)' + rs1_b6_val_data: 'gen_usign_dataset(8)' + rs1_b7_val_data: 'gen_usign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +swap8: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_usign_dataset(8)' + rs1_b1_val_data: 'gen_usign_dataset(8)' + rs1_b2_val_data: 'gen_usign_dataset(8)' + rs1_b3_val_data: 'gen_usign_dataset(8)' + rs1_b4_val_data: 'gen_usign_dataset(8)' + rs1_b5_val_data: 'gen_usign_dataset(8)' + rs1_b6_val_data: 'gen_usign_dataset(8)' + rs1_b7_val_data: 'gen_usign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +# 3.1.11. 8-bit Unpacking Instructions + +sunpkd810: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +sunpkd820: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +sunpkd830: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +sunpkd831: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +sunpkd832: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +zunpkd810: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_usign_dataset(8)' + rs1_b1_val_data: 'gen_usign_dataset(8)' + rs1_b2_val_data: 'gen_usign_dataset(8)' + rs1_b3_val_data: 'gen_usign_dataset(8)' + rs1_b4_val_data: 'gen_usign_dataset(8)' + rs1_b5_val_data: 'gen_usign_dataset(8)' + rs1_b6_val_data: 'gen_usign_dataset(8)' + rs1_b7_val_data: 'gen_usign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +zunpkd820: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_usign_dataset(8)' + rs1_b1_val_data: 'gen_usign_dataset(8)' + rs1_b2_val_data: 'gen_usign_dataset(8)' + rs1_b3_val_data: 'gen_usign_dataset(8)' + rs1_b4_val_data: 'gen_usign_dataset(8)' + rs1_b5_val_data: 'gen_usign_dataset(8)' + rs1_b6_val_data: 'gen_usign_dataset(8)' + rs1_b7_val_data: 'gen_usign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +zunpkd830: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_usign_dataset(8)' + rs1_b1_val_data: 'gen_usign_dataset(8)' + rs1_b2_val_data: 'gen_usign_dataset(8)' + rs1_b3_val_data: 'gen_usign_dataset(8)' + rs1_b4_val_data: 'gen_usign_dataset(8)' + rs1_b5_val_data: 'gen_usign_dataset(8)' + rs1_b6_val_data: 'gen_usign_dataset(8)' + rs1_b7_val_data: 'gen_usign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +zunpkd831: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_usign_dataset(8)' + rs1_b1_val_data: 'gen_usign_dataset(8)' + rs1_b2_val_data: 'gen_usign_dataset(8)' + rs1_b3_val_data: 'gen_usign_dataset(8)' + rs1_b4_val_data: 'gen_usign_dataset(8)' + rs1_b5_val_data: 'gen_usign_dataset(8)' + rs1_b6_val_data: 'gen_usign_dataset(8)' + rs1_b7_val_data: 'gen_usign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +zunpkd832: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_usign_dataset(8)' + rs1_b1_val_data: 'gen_usign_dataset(8)' + rs1_b2_val_data: 'gen_usign_dataset(8)' + rs1_b3_val_data: 'gen_usign_dataset(8)' + rs1_b4_val_data: 'gen_usign_dataset(8)' + rs1_b5_val_data: 'gen_usign_dataset(8)' + rs1_b6_val_data: 'gen_usign_dataset(8)' + rs1_b7_val_data: 'gen_usign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +# 3.2 Partial-SIMD Data Processing Instructions + +pkbb16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + rs2_h0_val_data: 'gen_usign_dataset(16)' + rs2_h1_val_data: 'gen_usign_dataset(16)' + rs2_h2_val_data: 'gen_usign_dataset(16)' + rs2_h3_val_data: 'gen_usign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +pkbt16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + rs2_h0_val_data: 'gen_usign_dataset(16)' + rs2_h1_val_data: 'gen_usign_dataset(16)' + rs2_h2_val_data: 'gen_usign_dataset(16)' + rs2_h3_val_data: 'gen_usign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +pktb16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + rs2_h0_val_data: 'gen_usign_dataset(16)' + rs2_h1_val_data: 'gen_usign_dataset(16)' + rs2_h2_val_data: 'gen_usign_dataset(16)' + rs2_h3_val_data: 'gen_usign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +pktt16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + rs2_h0_val_data: 'gen_usign_dataset(16)' + rs2_h1_val_data: 'gen_usign_dataset(16)' + rs2_h2_val_data: 'gen_usign_dataset(16)' + rs2_h3_val_data: 'gen_usign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) +# 3.2.2 Most Significant Word 32x32 Multiply & Add Instructions +smmul: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +smmul.u: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + rs1_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + rs2_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + rs2_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +kmmac: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + rs1_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + rs2_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + rs2_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmmac.u: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + rs1_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + rs2_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + rs2_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmmsb: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + rs1_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + rs2_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + rs2_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmmsb.u: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + rs1_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + rs2_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + rs2_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kwmmul: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + rs1_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + rs2_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + rs2_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kwmmul.u: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + rs1_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + rs2_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + rs2_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + + +# 3.2.3 Most Significant Word 32x16 Multiply & Add Instructions +smmwb: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32, 16 + formattype: 'pwhrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +smmwb.u: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32, 16 + formattype: 'pwhrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +smmwt: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32, 16 + formattype: 'pwhrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +smmwt.u: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32, 16 + formattype: 'pwhrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +kmmawb: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32, 16 + formattype: 'pwhrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmmawb.u: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32, 16 + formattype: 'pwhrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmmawt: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32, 16 + formattype: 'pwhrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmmawt.u: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32, 16 + formattype: 'pwhrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmmwb2: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32, 16 + formattype: 'pwhrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + + +kmmwb2.u: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32, 16 + formattype: 'pwhrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmmwt2: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32, 16 + formattype: 'pwhrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmmwt2.u: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32, 16 + formattype: 'pwhrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + + +kmmawb2: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32, 16 + formattype: 'pwhrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmmawb2.u: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32, 16 + formattype: 'pwhrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmmawt2: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32, 16 + formattype: 'pwhrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmmawt2.u: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32, 16 + formattype: 'pwhrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + + +# 3.2.4 Signed 16-bit Multiply with 32-bit Add/Subtract Instructions + +smbb16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +smbt16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +smtt16: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +kmda: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmxda: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +smds: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +smdrs: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +smxds: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +kmabb: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmabt: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmatt: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmada: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmaxda: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmads: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmadrs: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmaxds: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmsda: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmsxda: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +# 3.2.5 Signed 16-bit Multiply with 64-bit Add/Subtract Instructions + +smal: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 64,16 + p64_profile: 'ppn' + formattype: 'pphrrformat' + rs1_op_data: *pair_regs + rs2_op_data: *all_regs + + rd_op_data: *pair_regs + rs1_val_data: 'gen_sign_dataset(64)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val64; op2val:$rs2_val; + TEST_P64_PPN_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $swreg, $offset, $testreg) + + +# 3.2.6 Miscellaneous Instructions + +sclip32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwriformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + imm_val_data: 'gen_imm_dataset(5)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_PKIMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $rs1, $swreg, $offset, $testreg) + +uclip32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwriformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + imm_val_data: 'gen_imm_dataset(5)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_PKIMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $rs1, $swreg, $offset, $testreg) + +clrs32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +clz32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +pbsad: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_usign_dataset(8)' + rs1_b1_val_data: 'gen_usign_dataset(8)' + rs1_b2_val_data: 'gen_usign_dataset(8)' + rs1_b3_val_data: 'gen_usign_dataset(8)' + rs1_b4_val_data: 'gen_usign_dataset(8)' + rs1_b5_val_data: 'gen_usign_dataset(8)' + rs1_b6_val_data: 'gen_usign_dataset(8)' + rs1_b7_val_data: 'gen_usign_dataset(8)' + rs2_b0_val_data: 'gen_usign_dataset(8)' + rs2_b1_val_data: 'gen_usign_dataset(8)' + rs2_b2_val_data: 'gen_usign_dataset(8)' + rs2_b3_val_data: 'gen_usign_dataset(8)' + rs2_b4_val_data: 'gen_usign_dataset(8)' + rs2_b5_val_data: 'gen_usign_dataset(8)' + rs2_b6_val_data: 'gen_usign_dataset(8)' + rs2_b7_val_data: 'gen_usign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +pbsada: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_usign_dataset(8)' + rs1_b1_val_data: 'gen_usign_dataset(8)' + rs1_b2_val_data: 'gen_usign_dataset(8)' + rs1_b3_val_data: 'gen_usign_dataset(8)' + rs1_b4_val_data: 'gen_usign_dataset(8)' + rs1_b5_val_data: 'gen_usign_dataset(8)' + rs1_b6_val_data: 'gen_usign_dataset(8)' + rs1_b7_val_data: 'gen_usign_dataset(8)' + rs2_b0_val_data: 'gen_usign_dataset(8)' + rs2_b1_val_data: 'gen_usign_dataset(8)' + rs2_b2_val_data: 'gen_usign_dataset(8)' + rs2_b3_val_data: 'gen_usign_dataset(8)' + rs2_b4_val_data: 'gen_usign_dataset(8)' + rs2_b5_val_data: 'gen_usign_dataset(8)' + rs2_b6_val_data: 'gen_usign_dataset(8)' + rs2_b7_val_data: 'gen_usign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +# 3.2.7. 8-bit Multiply with 32-bit Add Instructions + +smaqa: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + rs2_b0_val_data: 'gen_sign_dataset(8)' + rs2_b1_val_data: 'gen_sign_dataset(8)' + rs2_b2_val_data: 'gen_sign_dataset(8)' + rs2_b3_val_data: 'gen_sign_dataset(8)' + rs2_b4_val_data: 'gen_sign_dataset(8)' + rs2_b5_val_data: 'gen_sign_dataset(8)' + rs2_b6_val_data: 'gen_sign_dataset(8)' + rs2_b7_val_data: 'gen_sign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +umaqa: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_usign_dataset(8)' + rs1_b1_val_data: 'gen_usign_dataset(8)' + rs1_b2_val_data: 'gen_usign_dataset(8)' + rs1_b3_val_data: 'gen_usign_dataset(8)' + rs1_b4_val_data: 'gen_usign_dataset(8)' + rs1_b5_val_data: 'gen_usign_dataset(8)' + rs1_b6_val_data: 'gen_usign_dataset(8)' + rs1_b7_val_data: 'gen_usign_dataset(8)' + rs2_b0_val_data: 'gen_usign_dataset(8)' + rs2_b1_val_data: 'gen_usign_dataset(8)' + rs2_b2_val_data: 'gen_usign_dataset(8)' + rs2_b3_val_data: 'gen_usign_dataset(8)' + rs2_b4_val_data: 'gen_usign_dataset(8)' + rs2_b5_val_data: 'gen_usign_dataset(8)' + rs2_b6_val_data: 'gen_usign_dataset(8)' + rs2_b7_val_data: 'gen_usign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +smaqa.su: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 8 + formattype: 'pbrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_b0_val_data: 'gen_sign_dataset(8)' + rs1_b1_val_data: 'gen_sign_dataset(8)' + rs1_b2_val_data: 'gen_sign_dataset(8)' + rs1_b3_val_data: 'gen_sign_dataset(8)' + rs1_b4_val_data: 'gen_sign_dataset(8)' + rs1_b5_val_data: 'gen_sign_dataset(8)' + rs1_b6_val_data: 'gen_sign_dataset(8)' + rs1_b7_val_data: 'gen_sign_dataset(8)' + rs2_b0_val_data: 'gen_sign_dataset(8)' + rs2_b1_val_data: 'gen_sign_dataset(8)' + rs2_b2_val_data: 'gen_sign_dataset(8)' + rs2_b3_val_data: 'gen_sign_dataset(8)' + rs2_b4_val_data: 'gen_sign_dataset(8)' + rs2_b5_val_data: 'gen_sign_dataset(8)' + rs2_b6_val_data: 'gen_sign_dataset(8)' + rs2_b7_val_data: 'gen_sign_dataset(8)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +# 3.3.1 64-bit Addition & Subtraction Instructions + +add64: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32] + std_op: + isa: + - IPZicsr + bit_width: 64 + p64_profile: 'ppp' + formattype: 'prrformat' + rs1_op_data: *pair_regs + rs2_op_data: *pair_regs + rd_op_data: *pair_regs + rs1_val_data: 'gen_sign_dataset(64)' + rs2_val_data: 'gen_sign_dataset(64)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val64 op2val:$rs2_val64 + TEST_P64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $swreg, $offset, $testreg) + +radd64: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 64 + p64_profile: 'ppp' + formattype: 'prrformat' + rs1_op_data: *pair_regs + rs2_op_data: *pair_regs + rd_op_data: *pair_regs + rs1_val_data: 'gen_sign_dataset(64)' + rs2_val_data: 'gen_sign_dataset(64)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val64; op2val:$rs2_val64; + TEST_P64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $swreg, $offset, $testreg) + +uradd64: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 64 + p64_profile: 'ppp' + formattype: 'prrformat' + rs1_op_data: *pair_regs + rs2_op_data: *pair_regs + rd_op_data: *pair_regs + rs1_val_data: 'gen_usign_dataset(64)' + rs2_val_data: 'gen_usign_dataset(64)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val64; op2val:$rs2_val64; + TEST_P64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $swreg, $offset, $testreg) + +kadd64: + sig: + stride: 3 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 64 + p64_profile: 'ppp' + formattype: 'prrformat' + rs1_op_data: *pair_regs + rs2_op_data: *pair_regs + rd_op_data: *pair_regs + rs1_val_data: 'gen_sign_dataset(64)' + rs2_val_data: 'gen_sign_dataset(64)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val64; op2val:$rs2_val64; + TEST_PK64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $rs1, $swreg, $offset, $testreg) + +ukadd64: + sig: + stride: 3 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 64 + p64_profile: 'ppp' + formattype: 'prrformat' + rs1_op_data: *pair_regs + rs2_op_data: *pair_regs + rd_op_data: *pair_regs + rs1_val_data: 'gen_usign_dataset(64)' + rs2_val_data: 'gen_usign_dataset(64)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val64; op2val:$rs2_val64; + TEST_PK64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $rs1, $swreg, $offset, $testreg) + +sub64: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32] + std_op: + isa: + - IPZicsr + bit_width: 64 + p64_profile: 'ppp' + formattype: 'prrformat' + rs1_op_data: *pair_regs + rs2_op_data: *pair_regs + rd_op_data: *pair_regs + rs1_val_data: 'gen_sign_dataset(64)' + rs2_val_data: 'gen_sign_dataset(64)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val64; op2val:$rs2_val64; + TEST_P64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $swreg, $offset, $testreg) + +rsub64: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 64 + p64_profile: 'ppp' + formattype: 'prrformat' + rs1_op_data: *pair_regs + rs2_op_data: *pair_regs + rd_op_data: *pair_regs + rs1_val_data: 'gen_sign_dataset(64)' + rs2_val_data: 'gen_sign_dataset(64)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val64; op2val:$rs2_val64; + TEST_P64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $swreg, $offset, $testreg) + +ursub64: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 64 + p64_profile: 'ppp' + formattype: 'prrformat' + rs1_op_data: *pair_regs + rs2_op_data: *pair_regs + rd_op_data: *pair_regs + rs1_val_data: 'gen_usign_dataset(64)' + rs2_val_data: 'gen_usign_dataset(64)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val64; op2val:$rs2_val64; + TEST_P64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $swreg, $offset, $testreg) + +ksub64: + sig: + stride: 3 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 64 + p64_profile: 'ppp' + formattype: 'prrformat' + rs1_op_data: *pair_regs + rs2_op_data: *pair_regs + rd_op_data: *pair_regs + rs1_val_data: 'gen_sign_dataset(64)' + rs2_val_data: 'gen_sign_dataset(64)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val64; op2val:$rs2_val64; + TEST_PK64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $rs1, $swreg, $offset, $testreg) + +uksub64: + sig: + stride: 3 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 64 + p64_profile: 'ppp' + formattype: 'prrformat' + rs1_op_data: *pair_regs + rs2_op_data: *pair_regs + rd_op_data: *pair_regs + rs1_val_data: 'gen_usign_dataset(64)' + rs2_val_data: 'gen_usign_dataset(64)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val64; op2val:$rs2_val64; + TEST_PK64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $rs1, $swreg, $offset, $testreg) +# 3.2.2 32-bit Multiply with 64-bit Add/Subtract Instructions + +smar64: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + p64_profile: 'pnn' + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *pair_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +smsr64: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + p64_profile: 'pnn' + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *pair_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +umar64: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + p64_profile: 'pnn' + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *pair_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_w0_val_data: 'gen_usign_dataset(32)' + rs2_w1_val_data: 'gen_usign_dataset(32)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +umsr64: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + p64_profile: 'pnn' + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *pair_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_w0_val_data: 'gen_usign_dataset(32)' + rs2_w1_val_data: 'gen_usign_dataset(32)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +kmar64: + sig: + stride: 3 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + p64_profile: 'pnn' + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *pair_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PK64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmsr64: + sig: + stride: 3 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + p64_profile: 'pnn' + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *pair_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PK64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +ukmar64: + sig: + stride: 3 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + p64_profile: 'pnn' + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *pair_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_w0_val_data: 'gen_usign_dataset(32)' + rs2_w1_val_data: 'gen_usign_dataset(32)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PK64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +ukmsr64: + sig: + stride: 3 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + p64_profile: 'pnn' + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *pair_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_w0_val_data: 'gen_usign_dataset(32)' + rs2_w1_val_data: 'gen_usign_dataset(32)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PK64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + + +# 3.3.3 Signed 16-bit Multiply with 64-bit Add/Subtract Instructions + +smalbb: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + p64_profile: 'pnn' + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *pair_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +smalbt: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + p64_profile: 'pnn' + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *pair_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +smaltt: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + p64_profile: 'pnn' + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *pair_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +smalda: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + p64_profile: 'pnn' + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *pair_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +smalxda: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + p64_profile: 'pnn' + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *pair_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +smalds: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + p64_profile: 'pnn' + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *pair_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +smaldrs: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + p64_profile: 'pnn' + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *pair_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +smalxds: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + p64_profile: 'pnn' + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *pair_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +smslda: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + p64_profile: 'pnn' + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *pair_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +smslxda: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + p64_profile: 'pnn' + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *pair_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +# 3.4.1 Q15 Saturation Instructions + +kaddh: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +ksubh: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +khmbb: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +khmbt: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +khmtt: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +ukaddh: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + rs2_h0_val_data: 'gen_usign_dataset(16)' + rs2_h1_val_data: 'gen_usign_dataset(16)' + rs2_h2_val_data: 'gen_usign_dataset(16)' + rs2_h3_val_data: 'gen_usign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +uksubh: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_usign_dataset(16)' + rs1_h1_val_data: 'gen_usign_dataset(16)' + rs1_h2_val_data: 'gen_usign_dataset(16)' + rs1_h3_val_data: 'gen_usign_dataset(16)' + rs2_h0_val_data: 'gen_usign_dataset(16)' + rs2_h1_val_data: 'gen_usign_dataset(16)' + rs2_h2_val_data: 'gen_usign_dataset(16)' + rs2_h3_val_data: 'gen_usign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +# 3.4.2 Q31 Saturation Instructions + +kaddw: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +ukaddw: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_w0_val_data: 'gen_usign_dataset(32)' + rs2_w1_val_data: 'gen_usign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +ksubw: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +uksubw: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_w0_val_data: 'gen_usign_dataset(32)' + rs2_w1_val_data: 'gen_usign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kdmbb: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kdmbt: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kdmtt: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kslraw: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kslraw.u: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +ksllw: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pswrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_val_data: 'gen_usign_dataset(ceil(log(32,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kslliw: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwriformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + imm_val_data: 'gen_imm_dataset(5)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_PKIMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $rs1, $swreg, $offset, $testreg) + +kdmabb: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kdmabt: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kdmatt: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kabsw: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_PKR_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $rs1, $swreg, $offset, $testreg) + +# 3.4.3. 32-bit Computation Instructions + +raddw: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +uraddw: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_w0_val_data: 'gen_usign_dataset(32)' + rs2_w1_val_data: 'gen_usign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +rsubw: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +ursubw: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_w0_val_data: 'gen_usign_dataset(32)' + rs2_w1_val_data: 'gen_usign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +mulr64: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + p64_profile: 'pnn' + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *pair_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs2_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_w1_val_data: 'gen_usign_dataset(32)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; + TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +mulsr64: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + p64_profile: 'pnn' + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *pair_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +maddr32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + rs1_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + rs2_w0_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + rs2_w1_val_data: 'gen_sign_dataset(32) + gen_sp_dataset(32,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +msubr32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +# 3.4.4 Overflow/Saturation Status Manipulation Instructions +# alias for CSRR Rd, vxsat +# rdov: +# sig: +# stride: 1 +# sz: 'XLEN/8' +# rd_op_data: *all_regs +# xlen: [32,64] +# std_op: +# isa: +# - IP +# formattype: 'uformat' +# imm_val_data: 'gen_usign_dataset(2)' +# template: |- +# +# // $comment +# // opcode: $inst ; dest:$rd +# TEST_CASE($testreg, $rd, $correctval, $swreg, $offset, $inst $rd) + +# alias for CSRRCI x0, vxsat, 1 +# clrov: +# sig: +# stride: 1 +# sz: 'XLEN/8' +# rd_op_data: *all_regs +# xlen: [32,64] +# std_op: +# isa: +# - IP +# formattype: 'uformat' +# imm_val_data: 'gen_usign_dataset(2)' +# template: |- +# +# // $comment +# // opcode: $inst +# TEST_CASE($testreg, x0, $correctval, $swreg, $offset, $inst) + +# 3.4.5. Miscellaneous Instructions + +ave: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +sra.u: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +srai.u: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + formattype: 'iformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +bitrev: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +bitrevi: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + formattype: 'iformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +wext: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 64, 8 + p64_profile: 'npn' + formattype: 'ppbrrformat' + rs1_op_data: *pair_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(64)' + rs2_b0_val_data: 'gen_usign_dataset(8)' + rs2_b1_val_data: 'gen_usign_dataset(8)' + rs2_b2_val_data: 'gen_usign_dataset(8)' + rs2_b3_val_data: 'gen_usign_dataset(8)' + rs2_b4_val_data: 'gen_usign_dataset(8)' + rs2_b5_val_data: 'gen_usign_dataset(8)' + rs2_b6_val_data: 'gen_usign_dataset(8)' + rs2_b7_val_data: 'gen_usign_dataset(8)' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val64; op2val:$rs2_val + TEST_P64_NPN_OP($inst, $rd, $rs1, $rs1_hi, $rs2, $correctval, $rs1_val, $rs1_val_hi, $rs2_val, $swreg, $offset, $testreg) + +wexti: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + bit_width: 64 + p64_profile: 'npi' + formattype: 'iformat' + rs1_op_data: *pair_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(64)' + imm_val_data: 'gen_imm_dataset(ceil(log(32,2)))' + + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val64; immval:$imm_val + TEST_P64_NP_OP($inst, $rd, $rs1, $rs1_hi, $correctval, $rs1_val, $rs1_val_hi, $imm_val, $swreg, $offset, $testreg) + + +insb: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IPZicsr + formattype: 'iformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2))-3)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +# 8. RV64 Only Instructions +# Table 27. (RV64 Only) SIMD 32-bit Add/Subtract Instructions + +add32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +radd32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +uradd32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_w0_val_data: 'gen_usign_dataset(32)' + rs2_w1_val_data: 'gen_usign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +kadd32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +ukadd32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_w0_val_data: 'gen_usign_dataset(32)' + rs2_w1_val_data: 'gen_usign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +sub32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +rsub32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +ursub32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_w0_val_data: 'gen_usign_dataset(32)' + rs2_w1_val_data: 'gen_usign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +ksub32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +uksub32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_w0_val_data: 'gen_usign_dataset(32)' + rs2_w1_val_data: 'gen_usign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +cras32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +rcras32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +urcras32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_w0_val_data: 'gen_usign_dataset(32)' + rs2_w1_val_data: 'gen_usign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +kcras32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +ukcras32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_w0_val_data: 'gen_usign_dataset(32)' + rs2_w1_val_data: 'gen_usign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +crsa32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +rcrsa32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +urcrsa32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_w0_val_data: 'gen_usign_dataset(32)' + rs2_w1_val_data: 'gen_usign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +kcrsa32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +ukcrsa32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_w0_val_data: 'gen_usign_dataset(32)' + rs2_w1_val_data: 'gen_usign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +stas32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +rstas32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +urstas32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_w0_val_data: 'gen_usign_dataset(32)' + rs2_w1_val_data: 'gen_usign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +kstas32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +ukstas32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_w0_val_data: 'gen_usign_dataset(32)' + rs2_w1_val_data: 'gen_usign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +stsa32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +rstsa32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +urstsa32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_w0_val_data: 'gen_usign_dataset(32)' + rs2_w1_val_data: 'gen_usign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +kstsa32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +ukstsa32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_w0_val_data: 'gen_usign_dataset(32)' + rs2_w1_val_data: 'gen_usign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +# Table 28. (RV64 Only) SIMD 32-bit Shift Instructions + +sra32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pswrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_val_data: 'gen_usign_dataset(ceil(log(32,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +srai32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwriformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + imm_val_data: 'gen_imm_dataset(5)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +sra32.u: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pswrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_val_data: 'gen_usign_dataset(ceil(log(32,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +srai32.u: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwriformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + imm_val_data: 'gen_imm_dataset(5)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +srl32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pswrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_val_data: 'gen_usign_dataset(ceil(log(32,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +srli32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwriformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + imm_val_data: 'gen_imm_dataset(5)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +srl32.u: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pswrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_val_data: 'gen_usign_dataset(ceil(log(32,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +srli32.u: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwriformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + imm_val_data: 'gen_imm_dataset(5)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +sll32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pswrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_val_data: 'gen_usign_dataset(ceil(log(32,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +slli32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwriformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + imm_val_data: 'gen_imm_dataset(5)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +ksll32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pswrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_val_data: 'gen_usign_dataset(ceil(log(32,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kslli32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwriformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + imm_val_data: 'gen_imm_dataset(5)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_PKIMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $rs1, $swreg, $offset, $testreg) + +kslra32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32,xlen + formattype: 'pswrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_val_data: 'gen_sign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kslra32.u: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32,xlen + formattype: 'pswrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_val_data: 'gen_sign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +# Table 29. (RV64 Only) SIMD 32-bit Miscellaneous Instructions + +smin32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +umin32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_w0_val_data: 'gen_usign_dataset(32)' + rs2_w1_val_data: 'gen_usign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +smax32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +umax32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_w0_val_data: 'gen_usign_dataset(32)' + rs2_w1_val_data: 'gen_usign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +kabs32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + TEST_PKR_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $rs1, $swreg, $offset, $testreg) + +# Table 30. (RV64 Only) SIMD Q15 saturating Multiply Instructions + +khmbb16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +khmbt16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +khmtt16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kdmbb16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kdmbt16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kdmtt16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kdmabb16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kdmabt16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kdmatt16: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 16 + formattype: 'phrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_h0_val_data: 'gen_sign_dataset(16)' + rs1_h1_val_data: 'gen_sign_dataset(16)' + rs1_h2_val_data: 'gen_sign_dataset(16)' + rs1_h3_val_data: 'gen_sign_dataset(16)' + rs2_h0_val_data: 'gen_sign_dataset(16)' + rs2_h1_val_data: 'gen_sign_dataset(16)' + rs2_h2_val_data: 'gen_sign_dataset(16)' + rs2_h3_val_data: 'gen_sign_dataset(16)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +# Table 31. (RV64 Only) 32-bit Multiply Instructions + +smbb32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +smbt32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +smtt32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +# Table 32. (RV64 Only) 32-bit Multiply & Add Instructions + +kmabb32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmabt32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmatt32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +# Table 33. (RV64 Only) 32-bit Parallel Multiply & Add Instructions + +kmda32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmxda32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmada32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmaxda32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmads32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmadrs32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmaxds32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmsda32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +kmsxda32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg) + +smds32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +smdrs32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +smxds32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + rs2_w0_val_data: 'gen_sign_dataset(32)' + rs2_w1_val_data: 'gen_sign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +# Table 34. (RV64 Only) Non-SIMD 32-bit Shift Instructions + +sraiw.u: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwriformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_sign_dataset(32)' + rs1_w1_val_data: 'gen_sign_dataset(32)' + imm_val_data: 'gen_imm_dataset(5)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +# Table 35. (RV64 Only) 32-bit Packing Instructions + +pkbb32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_w0_val_data: 'gen_usign_dataset(32)' + rs2_w1_val_data: 'gen_usign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +pkbt32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_w0_val_data: 'gen_usign_dataset(32)' + rs2_w1_val_data: 'gen_usign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +pktb32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_w0_val_data: 'gen_usign_dataset(32)' + rs2_w1_val_data: 'gen_usign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +pktt32: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IPZicsr + bit_width: 32 + formattype: 'pwrrformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_w0_val_data: 'gen_usign_dataset(32)' + rs1_w1_val_data: 'gen_usign_dataset(32)' + rs2_w0_val_data: 'gen_usign_dataset(32)' + rs2_w1_val_data: 'gen_usign_dataset(32)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +bseti: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZbs + - IB + formattype: 'iformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'zerotoxlen(xlen)' + imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg) + +xperm4: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZk + - IZbkx + - IZkn + - IZks + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_usign_dataset(xlen)+gen_sign_dataset(xlen)' + rs2_val_data: 'gen_usign_dataset(xlen)+gen_sign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +xperm8: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZk + - IZbkx + - IZkn + - IZks + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen)+gen_sign_dataset(xlen)' + rs2_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen)+gen_sign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +brev8: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: brev8 + isa: + - IZbkb + - IZk + - IZkn + - IZks + formattype: 'kformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)+gen_bitmanip_dataset(xlen,False)+[16909320,33818625,67633410,134283780,72624976414508040,145249888404506625,290483284134592770,576744443617542660]' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; + LI($rs1,$rs1_val) + brev8 $rd, $rs1 + RVTEST_SIGUPD($swreg,$rd,$offset) + RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval) + +# place holder for gorci instruction until it is rattified +gorci: + stride: 1 + xlen: [32,64] + std_op: gorci + isa: + - IB + formattype: 'iformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val; + LI($rs1,$rs1_val) + gorci $rd, $rs1, $imm_val + SREG $rd, $offset($swreg) + RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval) + +# place holder for grevi instruction until it is rattified +grevi: + stride: 1 + xlen: [32,64] + std_op: grevi + isa: + - IB + formattype: 'iformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val; + LI($rs1,$rs1_val) + grevi $rd, $rs1, $imm_val + SREG $rd, $offset($swreg) + RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval) + +shfli: + stride: 1 + xlen: [32] + std_op: shfli + isa: + - IB + formattype: 'iformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val; + LI($rs1,$rs1_val) + shfli $rd, $rs1, $imm_val + SREG $rd, $offset($swreg) + RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval) + +unshfli: + stride: 1 + xlen: [32] + std_op: unshfli + isa: + - IB + formattype: 'iformat' + rs1_op_data: *all_regs + rd_op_data: *all_regs + template: |- + + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val; + LI($rs1,$rs1_val) + unshfli $rd, $rs1, $imm_val + SREG $rd, $offset($swreg) + RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval) + +czero.eqz: + std_op: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + isa: + - IZicond + operation: 'hex(int(rs2_val != 0) * rs1_val)' + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +czero.nez: + std_op: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + isa: + - IZicond + operation: 'hex(int(rs2_val == 0) * rs1_val)' + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +amoadd.w: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + - IZaamo + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amoand.w: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + - IZaamo + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amoswap.w: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + - IZaamo + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amoxor.w: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + - IZaamo + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amoor.w: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + - IZaamo + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amomin.w: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + - IZaamo + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amominu.w: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + - IZaamo + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amomax.w: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + - IZaamo + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amomaxu.w: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + - IZaamo + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amoadd.d: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IA + - IZaamo + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amoand.d: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IA + - IZaamo + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amoswap.d: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IA + - IZaamo + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amoxor.d: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IA + - IZaamo + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amoor.d: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IA + - IZaamo + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amomin.d: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IA + - IZaamo + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amominu.d: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IA + - IZaamo + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amomax.d: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IA + - IZaamo + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amomaxu.d: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IA + - IZaamo + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amocas.w: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZacas + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *pair_regs + rd_op_data: *pair_regs + rs1_val_data: 'gen_sign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)' + + template: |- + + // $comment + // opcode: $inst ; dest:$rd; addr:$rs1; src:$rs2; swap_val:$rs2_val; swreg:$swreg; $offset + TEST_CAS_OP($inst, $rd, $rs1, $rs2, $rs2_val, $swreg, $offset); + +amocas.d_32: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32] + std_op: + isa: + - IZacas + bit_width: 64 + dcas_profile: 'pnp' + formattype: 'dcasrformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *pair_regs + rd_op_data: *pair_regs + rs1_val_data: 'gen_sign_dataset(64)' + rs2_val_data: 'gen_sign_dataset(64)' + + template: |- + + // $comment + // opcode: $inst ; dest($rd, $rd_hi) addr:$rs1; src:($rs2, $rs2_hi); swap_val:($rs2_val, $rs2_val_hi); swreg:$swreg; $offset + TEST_DCAS_OP(amocas.d, $rd, $rd_hi, $rs1, $rs2, $rs2_hi, $rs2_val, $rs2_val_hi, $swreg, $offset); + +amocas.d_64: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IZacas + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *pair_regs + rd_op_data: *pair_regs + rs1_val_data: 'gen_sign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)' + + template: |- + + // $comment + // opcode: $inst ; dest:$rd; addr:$rs1; src:$rs2; swap_val:$rs2_val; swreg:$swreg; $offset + TEST_CAS_OP(amocas.d, $rd, $rs1, $rs2, $rs2_val, $swreg, $offset); + +amocas.q: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IZacas + bit_width: 128 + dcas_profile: 'pnp' + formattype: 'dcasrformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(128)' + rs2_val_data: 'gen_sign_dataset(128)' + + template: |- + + // $comment + // opcode: $inst ; dest($rd, $rd_hi) addr:$rs1; src:($rs2, $rs2_hi); swap_val:($rs2_val, $rs2_val_hi), swreg:$swreg, $offset + TEST_DCAS_OP($inst, $rd, $rd_hi, $rs1, $rs2, $rs2_hi, $rs2_val, $rs2_val_hi, $swreg, $offset); + +c.lbu: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *c_regs + rd_op_data: *c_regs + xlen: [32,64] + std_op: + isa: + - I_Zca_Zcb + formattype: 'clformat' + rs1_val_data: '[0]' + imm_val_data: 'gen_usign_dataset(2)' + template: |- + + // $comment + // opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val + TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,0) + +c.lhu: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *c_regs + rd_op_data: *c_regs + xlen: [32,64] + std_op: + isa: + - I_Zca_Zcb + formattype: 'clformat' + rs1_val_data: '[0]' + imm_val_data: 'gen_usign_dataset(2)' + template: |- + + // $comment + // opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val + TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,0) + +c.lh: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *c_regs + rd_op_data: *c_regs + xlen: [32,64] + std_op: + isa: + - I_Zca_Zcb + formattype: 'clformat' + rs1_val_data: '[0]' + imm_val_data: 'gen_usign_dataset(2)' + template: |- + + // $comment + // opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val + TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,0) + +c.sb: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *c_regs + rs2_op_data: *c_regs + xlen: [32,64] + std_op: + isa: + - I_Zca_Zcb + formattype: 'csformat' + rs1_val_data: '[0]' + rs2_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: 'gen_usign_dataset(2)' + template: |- + + // $comment + // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val + TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,0) + +c.sh: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *c_regs + rs2_op_data: *c_regs + xlen: [32,64] + std_op: + isa: + - I_Zca_Zcb + formattype: 'csformat' + rs1_val_data: '[0]' + rs2_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: 'gen_usign_dataset(2)' + template: |- + + // $comment + // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val + TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,0) + +c.sext.b: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - I_Zca_Zcb_Zbb + formattype: 'ckformat' + rs1_op_data: *c_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val; + TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +c.sext.h: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - I_Zca_Zcb_Zbb + formattype: 'ckformat' + rs1_op_data: *c_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)+[65408]' + template: |- + + // $comment + // opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val; + TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +c.zext.b: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - I_Zca_Zcb + formattype: 'ckformat' + rs1_op_data: *c_regs + rs1_val_data: 'gen_usign_dataset(xlen)+[128]' + template: |- + + // $comment + // opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val; + TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +c.zext.h: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - I_Zca_Zcb_Zbb + formattype: 'ckformat' + rs1_op_data: *c_regs + rs1_val_data: 'gen_usign_dataset(xlen)+[65408]' + template: |- + + // $comment + // opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val; + TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +c.zext.w: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - I_Zca_Zcb_Zba + formattype: 'ckformat' + rs1_op_data: *c_regs + rs1_val_data: 'gen_usign_dataset(xlen)+[65408]' + template: |- + + // $comment + // opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val; + TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +c.not: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - I_Zca_Zcb + formattype: 'kformat' + rs1_op_data: *c_regs + rs1_val_data: 'gen_usign_dataset(xlen)+[65408]' + template: |- + + // $comment + // opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val; + TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) + +c.mul: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *c_regs + rs2_op_data: *c_regs + xlen: [32,64] + std_op: + isa: + - IM_Zca_Zcb + formattype: 'crformat' + operation: 'hex((rs1_val * rs2_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val + TEST_CR_OP( $inst, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +amoadd.b: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amoand.b: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amoswap.b: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amoxor.b: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amoor.b: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amomin.b: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amominu.b: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amomax.b: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amomaxu.b: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amocas.b: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZacas + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)' + + template: |- + + // $comment + // opcode: $inst ; dest:$rd; addr:$rs1; src:$rs2; swap_val:$rs2_val; swreg:$swreg; $offset + TEST_CAS_OP($inst, $rd, $rs1, $rs2, $rs2_val, $swreg, $offset); + +amoadd.h: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amoand.h: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amoswap.h: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amoxor.h: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amoor.h: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amomin.h: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amominu.h: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amomax.h: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amomaxu.h: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset) + +amocas.h: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZacas + formattype: 'rformat' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)' + + template: |- + + // $comment + // opcode: $inst ; dest:$rd; addr:$rs1; src:$rs2; swap_val:$rs2_val; swreg:$swreg; $offset + TEST_CAS_OP($inst, $rd, $rs1, $rs2, $rs2_val, $swreg, $offset); + +mop.rr.0: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZimop + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +mop.rr.1: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZimop + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +mop.rr.2: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZimop + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +mop.rr.3: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZimop + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +mop.rr.4: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZimop + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +mop.rr.5: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZimop + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +mop.rr.6: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZimop + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +mop.rr.7: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZimop + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val + TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg) + +mop.r.0: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.1: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.2: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.3: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.4: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.5: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.6: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.7: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.8: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.9: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.10: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.11: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.12: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.13: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.14: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.15: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.16: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.17: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.18: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.19: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.20: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.21: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.22: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.23: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.24: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.25: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.26: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.27: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.28: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.29: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.30: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +mop.r.31: + sig: + stride: 1 + sz: 'XLEN/8' + rs1_op_data: *all_regs + rd_op_data: *all_regs + xlen: [32,64] + std_op: + isa: + - IZimop + operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)' + formattype: 'iformat' + template: |- + + // $comment + // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val + TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg) + +c.mop.1: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - ICZcmop + formattype: 'cjformat' + imm_val_data: 'gen_sign_dataset(6)' + template: |- + // $comment + // opcode:$inst; immval:$imm_val + TEST_CMOP_OP($inst, x1, $imm_val, $swreg, $testreg, $offset) + +c.mop.3: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - ICZcmop + formattype: 'cjformat' + imm_val_data: 'gen_sign_dataset(6)' + template: |- + // $comment + // opcode:$inst; immval:$imm_val + TEST_CMOP_OP($inst, x3, $imm_val, $swreg, $testreg, $offset) + +c.mop.5: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - ICZcmop + formattype: 'cjformat' + imm_val_data: 'gen_sign_dataset(6)' + template: |- + // $comment + // opcode:$inst; immval:$imm_val + TEST_CMOP_OP($inst, x5, $imm_val, $swreg, $testreg, $offset) + +c.mop.7: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - ICZcmop + formattype: 'cjformat' + imm_val_data: 'gen_sign_dataset(6)' + template: |- + // $comment + // opcode:$inst; immval:$imm_val + TEST_CMOP_OP($inst, x7, $imm_val, $swreg, $testreg, $offset) + +c.mop.9: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - ICZcmop + formattype: 'cjformat' + imm_val_data: 'gen_sign_dataset(6)' + template: |- + // $comment + // opcode:$inst; immval:$imm_val + TEST_CMOP_OP($inst, x9, $imm_val, $swreg, $testreg, $offset) + +c.mop.11: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - ICZcmop + formattype: 'cjformat' + imm_val_data: 'gen_sign_dataset(6)' + template: |- + // $comment + // opcode:$inst; immval:$imm_val + TEST_CMOP_OP($inst, x11, $imm_val, $swreg, $testreg, $offset) + +c.mop.13: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - ICZcmop + formattype: 'cjformat' + imm_val_data: 'gen_sign_dataset(6)' + template: |- + // $comment + // opcode:$inst; immval:$imm_val + TEST_CMOP_OP($inst, x13, $imm_val, $swreg, $testreg, $offset) + +c.mop.15: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - ICZcmop + formattype: 'cjformat' + imm_val_data: 'gen_sign_dataset(6)' + template: |- + // $comment + // opcode:$inst; immval:$imm_val + TEST_CMOP_OP($inst, x15, $imm_val, $swreg, $testreg, $offset) + +lpad-m: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZicfilp + formattype: 'uformat' + imm_val_data: 'gen_usign_dataset(20)+ gen_sp_dataset(20,False)' + template: |- + // $comment + // opcode: lpad ; dest:x0; immval:$imm_val + TEST_LPAD_MMODE($testreg, $swreg, $offset, $imm_val) + +lpad-s: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZicfilp + formattype: 'uformat' + imm_val_data: 'gen_usign_dataset(20)+ gen_sp_dataset(20,False)' + template: |- + // $comment + // opcode: lpad ; dest:x0; immval:$imm_val + TEST_LPAD_SMODE($testreg, $swreg, $offset, $imm_val) + +lpad-u: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IZicfilp + formattype: 'uformat' + imm_val_data: 'gen_usign_dataset(20)+ gen_sp_dataset(20,False)' + template: |- + // $comment + // opcode: lpad ; dest:x0; immval:$imm_val + TEST_LPAD_UMODE($testreg, $swreg, $offset, $imm_val) + +sspushpopchk_u: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32, 64] + std_op: + isa: + - I_Zicfiss_Zicsr + formattype: 'rformat' + rs1_val_data: 'gen_sign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)' + template: |- + // $comment + TEST_SSPUSH_SSPOP_OP($swreg, $offset, $rs2_val, Umode) + +sspushpopchk_s: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32, 64] + std_op: + isa: + - I_Zicfiss_Zicsr + formattype: 'rformat' + rs1_val_data: 'gen_sign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)' + template: |- + // $comment + TEST_SSPUSH_SSPOP_OP($swreg, $offset, $rs2_val, Smode) + +c.sspushpopchk_u: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32, 64] + std_op: + isa: + - IC_Zicfiss_Zicsr + formattype: 'crformat' + rs1_val_data: 'gen_sign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)' + template: |- + // $comment + TEST_C_SSPUSH_SSPOP_OP($swreg, $offset, $rs2_val, Umode) + +c.sspushpopchk_s: + sig: + stride: 1 + sz: 'XLEN/8' + xlen: [32, 64] + std_op: + isa: + - IC_Zicfiss_Zicsr + formattype: 'crformat' + rs1_val_data: 'gen_sign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)' + template: |- + // $comment + TEST_C_SSPUSH_SSPOP_OP($swreg, $offset, $rs2_val, Smode) + +ssamoswap.w_s: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA_Zicfiss_Zicsr + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + // $comment + // opcode: $inst ; dest: $rd op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; $swreg; $testreg; Priv + #ifndef ZICFISS_SETUP_DONE + .set zicfiss_setup_done, 0 + #define ZICFISS_SETUP_DONE 1 + #endif + TEST_SSAMOSWAP_OP(ssamoswap.w, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $testreg, Smode) + +ssamoswap.d_s: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IA_Zicfiss_Zicsr + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + // $comment + // opcode: $inst ; dest: $rd op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; $swreg; $testreg; Priv + #ifndef ZICFISS_SETUP_DONE + .set zicfiss_setup_done, 0 + #define ZICFISS_SETUP_DONE 1 + #endif + TEST_SSAMOSWAP_OP(ssamoswap.d, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $testreg, Smode) + +ssamoswap.w_u: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [32,64] + std_op: + isa: + - IA_Zicfiss_Zicsr + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + // $comment + // opcode: $inst ; dest: $rd op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; $swreg; $testreg; Priv + #ifndef ZICFISS_SETUP_DONE + .set zicfiss_setup_done, 0 + #define ZICFISS_SETUP_DONE 1 + #endif + TEST_SSAMOSWAP_OP(ssamoswap.w, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $testreg, Umode) + +ssamoswap.d_u: + sig: + stride: 2 + sz: 'XLEN/8' + xlen: [64] + std_op: + isa: + - IA_Zicfiss_Zicsr + formattype: 'rformat' + rs1_op_data: *all_regs + rs2_op_data: *all_regs + rd_op_data: *all_regs + rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)' + template: |- + // $comment + // opcode: $inst ; dest: $rd op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; $swreg; $testreg; Priv + #ifndef ZICFISS_SETUP_DONE + .set zicfiss_setup_done, 0 + #define ZICFISS_SETUP_DONE 1 + #endif + TEST_SSAMOSWAP_OP(ssamoswap.d, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $testreg, Umode) + +ssrdp_s: + sig: + stride: 1 + sz: 'XLEN/8' + rd_op_data: *all_regs_mx0 + xlen: [32,64] + std_op: + isa: + - I_Zicfiss_Zicsr + rs1_val_data: 'gen_sign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)' + formattype: 'rformat' + template: |- + // $comment + // opcode:ssrdp; dest: $rd; $swreg; $testreg; Priv + #ifndef ZICFISS_SETUP_DONE + .set zicfiss_setup_done, 0 + #define ZICFISS_SETUP_DONE 1 + #endif + TEST_SSRDP_OP(ssrdp, $rd, $swreg, $testreg, Smode) + +ssrdp_u: + sig: + stride: 1 + sz: 'XLEN/8' + rd_op_data: *all_regs_mx0 + xlen: [32,64] + std_op: + isa: + - I_Zicfiss_Zicsr + rs1_val_data: 'gen_sign_dataset(xlen)' + rs2_val_data: 'gen_sign_dataset(xlen)' + formattype: 'rformat' + template: |- + // $comment + // opcode:ssrdp; dest: $rd; $swreg; $testreg; Priv + #ifndef ZICFISS_SETUP_DONE + .set zicfiss_setup_done, 0 + #define ZICFISS_SETUP_DONE 1 + #endif + TEST_SSRDP_OP(ssrdp, $rd, $swreg, $testreg, Umode) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/dsp_function.py b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/dsp_function.py new file mode 100644 index 000000000..2e4a0343d --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/dsp_function.py @@ -0,0 +1,253 @@ +def simd_val_vars(operand, xlen, bit_width): + ''' + This function generates the operand value variables for SIMD elements of the given operand. + + :param operand: a string indicating the name of the desired operand. + :param xlen: an integer indicating the XLEN value to be used. + :param bit_width: an integer indicating the element bit width for the current SIMD format. + + :type operand: str + :type xlen: int + :type bit_width: int + :return: a list containing the element value variables for the given operand. + ''' + val_list = [] + nelms = xlen // bit_width + if bit_width == 8: + sz = "b" + elif bit_width == 16: + sz = "h" + elif bit_width == 32: + sz = "w" + elif bit_width == 64: + sz = "d" + else: + sz = "q" + for i in range(nelms): + val_list += [f"{operand}_{sz}{i}_val"] + return val_list + +def get_fmt_sz(bit_width): + if bit_width == 8: + fmt = f"#02x" + elif bit_width == 16: + fmt = f"#04x" + elif bit_width == 32: + fmt = f"#08x" + elif bit_width == 64: + fmt = f"#016x" + else: + fmt = f"#032x" + if bit_width == 8: + sz = "b" + elif bit_width == 16: + sz = "h" + elif bit_width == 32: + sz = "w" + elif bit_width == 64: + sz = "d" + else: + sz = "q" + + return fmt, sz + +def gen_fmt(bit_width): + ''' + This function generate fmt string by bit_width. + + :param bit_width: an integer indicating the element bit width of the current RVP instruction. + + :type bit_width: int + ''' + + if bit_width == 8: + fmt = f"#02x" + elif bit_width == 16: + fmt = f"#04x" + elif bit_width == 32: + fmt = f"#08x" + elif bit_width == 64: + fmt = f"#016x" + else: + fmt = f"032x" + return fmt + +def gen_sz(bit_width): + ''' + This function generate size string by bit_width. + + :param bit_width: an integer indicating the element bit width of the current RVP instruction. + + :type bit_width: int + ''' + + if bit_width == 8: + sz = "b" + elif bit_width == 16: + sz = "h" + elif bit_width == 32: + sz = "w" + elif bit_width == 64: + sz = "d" + else: + sz = "q" + return sz + +def concat_simd_data(instr_dict, xlen, _bit_width): + ''' + This function concatenates all element of a SIMD register into a single value in the hex format. + + :param instr_dict: a dict holding metadata and operand data for the current instruction. + :param xlen: an integer indicating the XLEN value to be used. + :param bit_width: an integer or string of integer pair indicating the element bit width of rs1/rs2 of the current RVP instruction. + + :type instr_dict: dict + :type xlen: int + :type bit_width: int + ''' + if type(_bit_width)==str: + _bit_width = eval(_bit_width) + + if type(_bit_width)==tuple: + bit_width1, bit_width2 = _bit_width + else: + bit_width1, bit_width2 = _bit_width, _bit_width + + for instr in instr_dict: + if 'rs1' in instr: + twocompl_offset = 1<= 3 and p64_profile[1]=='p' else xlen + rs2_width = 64 if len(p64_profile) >= 3 and p64_profile[2]=='p' else xlen + rd_width = 64 if len(p64_profile) >= 3 and p64_profile[0]=='p' else xlen + else: + rs1_width = 128 if len(p64_profile) >= 3 and p64_profile[1]=='p' else xlen + rs2_width = 128 if len(p64_profile) >= 3 and p64_profile[2]=='p' else xlen + rd_width = 128 if len(p64_profile) >= 3 and p64_profile[0]=='p' else xlen + + for instr in instr_dict: + if 'rs1' in instr: + twocompl_offset = 1< xlen: + instr['rs1_val'] = format(0xffffffff & rs1_val, f"#0{2+xlen//4}x") + instr['rs1_val_hi'] = format(0xffffffff & (rs1_val>>32), f"#0{2+xlen//4}x") + instr['rs1_hi'] = incr_reg_num(instr['rs1']) + else: + instr['rs1_val'] = format(rs1_val, f"#0{2+xlen//4}x") + if rs1_width == 64 and (len(p64_profile) >= 3): + instr['rs1_val64'] = format(rs1_val, f"#018x") + + if 'rs2' in instr: + twocompl_offset = 1< xlen: + instr['rs2_val'] = format(0xffffffff & rs2_val, f"#0{2+xlen//4}x") + instr['rs2_val_hi'] = format(0xffffffff & (rs2_val>>32), f"#0{2+xlen//4}x") + instr['rs2_hi'] = incr_reg_num(instr['rs2']) + else: + instr['rs2_val'] = format(rs2_val, f"#0{2+xlen//4}x") + if rs2_width == 64 and (len(p64_profile) >= 3): + instr['rs2_val64'] = format(rs2_val, f"#018x") + + if 'rd' in instr and rd_width > xlen: + instr['rd_hi'] = incr_reg_num(instr['rd']) + + if 'imm_val' in instr: + imm_val = int(instr['imm_val']) + instr['imm_val'] = format(imm_val, f"#0x") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/env/arch_test.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/env/arch_test.h new file mode 100644 index 000000000..72e8802ac --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/env/arch_test.h @@ -0,0 +1,1517 @@ +#include "encoding.h" +// TODO the following should come from the YAML. +#ifndef NUM_SPECD_INTCAUSES + #define NUM_SPECD_INTCAUSES 16 +#endif +//#define RVTEST_FIXED_LEN +#ifndef UNROLLSZ + #define UNROLLSZ 5 +#endif +// #ifndef rvtest_gpr_save +// #define rvtest_gpr_save +// #endif + +//----------------------------------------------------------------------- +// RV Arch Test Macros +//----------------------------------------------------------------------- +#ifndef RVMODEL_SET_MSW_INT + #warning "RVMODEL_SET_MSW_INT is not defined by target. Declaring as empty macro" + #define RVMODEL_SET_MSW_INT +#endif + +#ifndef RVMODEL_CLEAR_MSW_INT + #warning "RVMODEL_CLEAR_MSW_INT is not defined by target. Declaring as empty macro" + #define RVMODEL_CLEAR_MSW_INT +#endif + +#ifndef RVMODEL_CLEAR_MTIMER_INT + #warning "RVMODEL_CLEAR_MTIMER_INT is not defined by target. Declaring as empty macro" + #define RVMODEL_CLEAR_MTIMER_INT +#endif + +#ifndef RVMODEL_CLEAR_MEXT_INT + #warning "RVMODEL_CLEAR_MEXT_INT is not defined by target. Declaring as empty macro" + #define RVMODEL_CLEAR_MEXT_INT +#endif + +#ifdef RVTEST_FIXED_LEN + #define LI(reg, val)\ + .option push;\ + .option norvc;\ + .align UNROLLSZ;\ + li reg,val;\ + .align UNROLLSZ;\ + .option pop; + + #define LA(reg, val)\ + .option push;\ + .option norvc;\ + .align UNROLLSZ;\ + la reg,val;\ + .align UNROLLSZ;\ + .option pop; + +#else + #define LI(reg,val);\ + .option push;\ + .option norvc;\ + li reg,val;\ + .option pop; + + #define LA(reg,val);\ + .option push;\ + .option norvc;\ + la reg,val;\ + .option pop; +#endif +#if XLEN==64 + #define SREG sd + #define LREG ld + #define LREGWU lwu + #define REGWIDTH 8 + #define MASK 0xFFFFFFFFFFFFFFFF + +#else + #if XLEN==32 + #define SREG sw + #define LREG lw + #define LREGWU lw + #define REGWIDTH 4 + #define MASK 0xFFFFFFFF + + #endif +#endif + +#if FLEN==64 + #define FLREG fld + #define FSREG fsd + #define FREGWIDTH 8 + #define SIGALIGN 8 +#if FLEN==32 + #define FLREG flw + #define FSREG fsw + #define FREGWIDTH 4 +#if FLEN==128 // Add support for quad precision (128-bit floating-point) + #define FLREG flq // Load quad precision + #define FSREG fsq // Store quad precision + #define FREGWIDTH 16 // Quad precision register width + #define SIGALIGN 16 // Alignment for quad precision +#endif +#endif +#endif + + +/*#if FLEN>XLEN + #define SIGALIGN FREGWIDTH +#else + #define SIGALIGN REGWIDTH +#endif*/ + + +#if SIGALIGN==16 + #define CANARY \ + .quad 0x6F5CA309E7D4B2816F5CA309E7D4B281 // Specific 128-bit canary value +#elif SIGALIGN==8 + #define CANARY \ + .dword 0x6F5CA309E7D4B281 +#else + #define CANARY \ + .word 0x6F5CA309 +#endif + + +#define MMODE_SIG 3 +#define RLENG (REGWIDTH<<3) + +#define RVTEST_ISA(_STR) + +#ifndef DATA_REL_TVAL_MSK + #define DATA_REL_TVAL_MSK 0x0F05 << (REGWIDTH*8-16) +#endif + +#ifndef CODE_REL_TVAL_MSK + #define CODE_REL_TVAL_MSK 0xD008 << (REGWIDTH*8-16) +#endif + +#define NAN_BOXED(__val__,__width__,__max__) \ + .if __width__ == 32 ;\ + .word __val__ ;\ + .elseif __width__ == 64 ;\ + .dword __val__ ;\ + .elseif __width__ == 128 ;\ + .quad __val__ ;\ + .endif ;\ + .if __max__ > __width__ ;\ + .set pref_bytes,(__max__-__width__)/32 ;\ + .else ;\ + .set pref_bytes, 0 ;\ + .endif ;\ + .rept pref_bytes ;\ + .word 0xffffffff ;\ + .endr ; + + +#define ZERO_EXTEND(__val__,__width__,__max__) \ + .if __max__ > __width__ ;\ + .set pref_bytes,(__max__-__width__)/32 ;\ + .else ;\ + .set pref_bytes, 0 ;\ + .endif ;\ + .rept pref_bytes ;\ + .word 0 ;\ + .endr ;\ + .if __width__ == 32 ;\ + .word __val__ ;\ + .elseif __width__ == 64 ;\ + .dword __val__ ;\ + .elseif __width__ == 128 ;\ + .quad __val__ ;\ + .endif; + +// ----------------------------------- CODE BEGIN w/ TRAP HANDLER START ------------------------ // + +.macro RVTEST_CODE_BEGIN + .align UNROLLSZ + .section .text.init; + .globl rvtest_init; \ + rvtest_init: +#ifdef rvtest_mtrap_routine + LA(x1, rvtest_trap_prolog ); + jalr ra, x1 + rvtest_prolog_done: +#endif + LI (x1, (0xFEEDBEADFEEDBEAD & MASK)); + LI (x2, (0xFF76DF56FF76DF56 & MASK)); + LI (x3, (0x7FBB6FAB7FBB6FAB & MASK)); + LI (x4, (0xBFDDB7D5BFDDB7D5 & MASK)); + LA (x5, rvtest_code_begin); + LA (x6, rvtest_data_begin); + LI (x7, (0xB7FBB6FAB7FBB6FA & MASK)); + LI (x8, (0x5BFDDB7D5BFDDB7D & MASK)); + LI (x9, (0xADFEEDBEADFEEDBE & MASK)); + LI (x10, (0x56FF76DF56FF76DF & MASK)); + LI (x11, (0xAB7FBB6FAB7FBB6F & MASK)); + LI (x12, (0xD5BFDDB7D5BFDDB7 & MASK)); + LI (x13, (0xEADFEEDBEADFEEDB & MASK)); + LI (x14, (0xF56FF76DF56FF76D & MASK)); + LI (x15, (0xFAB7FBB6FAB7FBB6 & MASK)); + #ifndef RVTEST_E + LI (x16, (0x7D5BFDDB7D5BFDDB & MASK)); + LI (x17, (0xBEADFEEDBEADFEED & MASK)); + LI (x18, (0xDF56FF76DF56FF76 & MASK)); + LI (x19, (0x6FAB7FBB6FAB7FBB & MASK)); + LI (x20, (0xB7D5BFDDB7D5BFDD & MASK)); + LI (x21, (0xDBEADFEEDBEADFEE & MASK)); + LI (x22, (0x6DF56FF76DF56FF7 & MASK)); + LI (x23, (0xB6FAB7FBB6FAB7FB & MASK)); + LI (x24, (0xDB7D5BFDDB7D5BFD & MASK)); + LI (x25, (0xEDBEADFEEDBEADFE & MASK)); + LI (x26, (0x76DF56FF76DF56FF & MASK)); + LI (x27, (0xBB6FAB7FBB6FAB7F & MASK)); + LI (x28, (0xDDB7D5BFDDB7D5BF & MASK)); + LI (x29, (0xEEDBEADFEEDBEADF & MASK)); + LI (x30, (0xF76DF56FF76DF56F & MASK)); + LI (x31, (0xFBB6FAB7FBB6FAB7 & MASK)); + #endif + .globl rvtest_code_begin + rvtest_code_begin: +.endm + +// --------------------------------- CODE BEGIN w/ TRAP HANDLER END -----------------------------// + +.macro RVTEST_CODE_END + .align 4; + .global rvtest_code_end + rvtest_code_end: +#ifdef rvtest_mtrap_routine + .option push + .option norvc + j exit_cleanup + + rvtest_trap_prolog: + /******************************************************************************/ + /**** Prolog, to be run before any tests ****/ + /**** #include 1 copy of this per mode in rvmodel_boot code? ****/ + /**** ------------------------------------------------------------------- ****/ + /**** if xTVEC isn't completely RW, then we need to change the code at its ****/ + /**** target. The entire trap trampoline and mtrap handler replaces the ****/ + /**** area pointed to by mtvec, after saving its original contents first. ****/ + /**** If it isn't possible to fully write that area, restore and fail. ****/ + /******************************************************************************/ + + //trap_handler_prolog; enter with t1..t6 available + + init_mscratch: + la t1, trapreg_sv + csrrw t1, CSR_MSCRATCH, t1 // swap old mscratch. mscratch not points to trapreg_sv + la t2, mscratch_save + SREG t1, 0(t2) // save old mscratch in mscratch_save region + csrr t1, CSR_MSCRATCH // read the trapreg_sv address + LA( t2, mtrap_sigptr ) // locate the start of the trap signature + SREG t2, 0(t1) // save mtrap_sigptr at first location of trapreg_sv + init_mtvec: + la t1, mtrampoline + la t4, mtvec_save + csrrw t2, CSR_MTVEC, t1 // swap mtvec and trap_trampoline + SREG t2, 0(t4) // save orig mtvec + csrr t3, CSR_MTVEC // now read new_mtval back + beq t3, t1, rvtest_prolog_done // if mtvec==trap_trampoline, mtvec is writable, continue + + /****************************************************************/ + /**** fixed mtvec, can't move it so move trampoline instead ****/ + /**** t1=trampoline, t2=oldmtvec, t3=save area, t4=save end ****/ + /****************************************************************/ + + // t2 = dut's original mtvec setting + // t1 = mtrampoline address + init_tramp: /**** copy trampoline at mtvec tgt ****/ + + csrw CSR_MTVEC, t2 // restore orig mtvec, will now attemp to copy trampoline to it + la t3, tramptbl_sv // addr of save area + addi t4, t3, NUM_SPECD_INTCAUSES*4 // end of save area + + overwrite_tt: // now build new trampoline table with offsets base from curr mtvec + lw t6, 0(t2) // get original mtvec target + sw t6, 0(t3) // save it + lw t5, 0(t1) // get trampoline src + sw t5, 0(t2) // overwrite mtvec target + lw t6, 0(t2) // rd it back to make sure it was written + bne t6, t5, resto_tramp // table isn't fully writable, restore and give up + addi t1, t1, 4 // next src index + addi t2, t2, 4 // next tgt index + addi t3, t3, 4 // next save index + bne t3, t4, overwrite_tt // not done, loop + j rvtest_prolog_done + + resto_tramp: // vector table not writeable, restore + LREG t1, 16(t4) // load mscratch_SAVE at fixed offset from table end + csrw CSR_MSCRATCH, t1 // restore mscratch + LREG t4, 8(t4) // load mtvec_SAVE (used as end of loop marker) + + + resto_loop: // goes backwards, t2= dest vec tbl ptr, t3=src save area ptr, t4=vec tbl begin + lw t6, 0(t3) // read saved tgt entry + sw t6, 0(t2) // restore original tgt + addi t2, t2, -4 // prev tgt index + addi t3, t3, -4 // prev save index + bne t2, t4, resto_loop // didn't restore to begining yet, loop + + j rvtest_end // failure to replace trampoline + + + #define mhandler \ + csrrw sp, CSR_MSCRATCH, sp; \ + SREG t6, 6*REGWIDTH(sp); \ + jal t6, common_prolog; + + /**********************************************************************/ + /**** This is the entry point for all m-modetraps, vectored or not.****/ + /**** At entry, mscratch will contain a pointer to a scratch area. ****/ + /**** This is an array of branches at 4B intevals that spreads out ****/ + /**** to an array of 32B mhandler macros for specd int causes, and ****/ + /**** to a return for anything above that (which causes a mismatch)****/ + /**********************************************************************/ + mtrampoline: // 64 or 32 entry table + .set value, 0 + .rept NUM_SPECD_INTCAUSES // located at each possible int vectors + j mtrap_handler + 12*(value) //offset < +/- 1MB + .set value, value + 1 + .endr + .rept RLENG-NUM_SPECD_INTCAUSES // fill at each impossible entry + mret + .endr + + mtrap_handler: /* after executing, sp points to temp save area, t4 is PC */ + .rept NUM_SPECD_INTCAUSES + mhandler + .endr + + common_prolog: + la t5, common_mhandler + jr t5 + /*********************************************************************/ + /**** common code for all ints & exceptions, will fork to handle ****/ + /**** each separately. The common handler first stores trap mode+ ****/ + /**** vector, and mcause signatures. All traps have 4wd sigs, but ****/ + /**** sw and timer ints only store 3 of the 4. ****/ + /**** sig offset Exception ExtInt SWInt TimerInt ****/ + /**** 0: tval IntID -1 -1 ****/ + /**** 4: mepc mip mip mip ****/ + /**** 8: <---------------------- mcause -------------> ****/ + /**** 12: <--------------------- Vect+mode ----------> ****/ + /*********************************************************************/ + /* in general, CSRs loaded in t2, addresses into t3 */ + + common_mhandler: /* enter with link in t6 */ + SREG t5, 5*REGWIDTH(sp) + SREG t4, 4*REGWIDTH(sp) + SREG t3, 3*REGWIDTH(sp) + SREG t2, 2*REGWIDTH(sp) + SREG t1, 1*REGWIDTH(sp) /* save other temporaries */ + + LREG t1, 0(sp) /* load trap sig pointer (runs backwards from DATA_END) */ + + LA( t3, mtrampoline) + sub t2, t6, t3 /* reloc “link” to 0..63 to show which int vector was taken */ + addi t2, t2, MMODE_SIG /* insert mode# into 1:0 */ + SREG t2, 0*REGWIDTH(t1) /* save 1st sig value, (vect, trapmode) */ + sv_mcause: + csrr t2, CSR_MCAUSE + SREG t2, 1*REGWIDTH(t1) /* save 2nd sig value, (mcause) */ + + bltz t2, common_mint_handler /* this is a interrupt, not a trap */ + + /********************************************************************/ + /**** This is the exceptions specific code, storing relative mepc****/ + /**** & relative tval signatures. tval is relocated by code or ****/ + /**** data start, or 0 depending on mcause. mepc signature value ****/ + /**** is relocated by code start, and restored adjusted depending****/ + /**** on op alignment so trapped op isn't re-executed. ****/ + /********************************************************************/ + common_mexcpt_handler: + csrr t2, CSR_MEPC + sv_mepc: + LA( t3, rvtest_prolog_done) /* offset to compensate for different loader offsets */ + sub t4, t2, t3 /* convert mepc to rel offset of beginning of test*/ + SREG t4, 2*REGWIDTH(t1) /* save 3rd sig value, (rel mepc) into trap signature area */ + adj_mepc: //adj mepc so there is padding after op, and its 8B aligned + andi t4, t2, 0x2 /* set to 2 if mepc was misaligned */ + sub t2, t2, t4 /* adjust mepc to prev 4B alignment */ + addi t2, t2, 0x8 /* adjust mepc, so it skips past the op, has padding & is 4B aligned */ + csrw CSR_MEPC, t2 /* restore adjusted value, has 1,2, or 3 bytes of padding */ + + + /* calculate relative mtval if it’s an address (by code_begin or data_begin amt) */ + /* note that masks that determine this are implementation specific from YAML */ + + /* masks are bit reversed, so mcause==0 bit is in MSB (so different for RV32 and RV64) */ + + adj_mtval: + csrr t2, CSR_MCAUSE /* code begin adjustment amount already in t3 */ + + LI(t4, CODE_REL_TVAL_MSK) /* trap#s 12, 3,1,0, -- adjust w/ code_begin */ + sll t4, t4, t2 /* put bit# in MSB */ + bltz t4, sv_mtval /* correct adjustment is code_begin in t3 */ + + LA( t3, mtrap_sigptr) /* adjustment assuming access is to signature region */ + LI(t4, DATA_REL_TVAL_MSK) /* trap#s not 14, 11..8, 2 adjust w/ data_begin */ + sll t4, t4, t2 /* put bit# in MSB */ + bgez t4, no_adj /* correct adjustment is data_begin in t3 */ + sigbound_chk: + csrr t4, CSR_MTVAL /* do a bounds check on mtval */ + bge t3, t4, sv_mtval /* if mtval is greater than the rvmodel_data_begin then use that as anchor */ + LA( t3, rvtest_data_begin) /* else change anchor to rvtest_data_begin */ + blt t3, t4, sv_mtval /* before the signature, use data_begin adj */ + mv t4, t3 /* use sig relative adjust */ + no_adj: + LI(t3, 0) /* else zero adjustment amt */ + + // For Illegal op handling + addi t2, t2, -2 /* check if mcause==2 (illegal op) */ + bnez t2, sv_mtval /* not illegal op, no special treatment */ + csrr t2, CSR_MTVAL + bnez t2, sv_mtval /* mtval isn’t zero, no special treatment */ + illop: + LI(t5, 0x20000) /* get mprv mask */ + csrrs t5, CSR_MSTATUS, t5 /* set mprv while saving the old value */ + csrr t3, CSR_MEPC + lhu t2, 0(t3) /* load 1st 16b of opc w/ old priv, endianess*/ + andi t4, t2, 0x3 + addi t4, t4, -0x3 /* does opcode[1:0]==0b11? (Meaning >16b op) */ + bnez t4, sv_mtval /* entire mtval is in tt2, adj amt will be set to zero */ + lhu t4, 2(t3) + sll t4, t4, 16 + or t3, t2, t4 /* get 2nd hwd, align it & insert it into opcode */ + csrw CSR_MSTATUS, t5 /* restore mstatus */ + +/*******FIXME: this will not handle 48 or 64b opcodes in an RV64) ********/ + + sv_mtval: + csrr t2, CSR_MTVAL + sub t2, t2, t3 /* perform mtval adjust by either code or data position or zero*/ + SREG t2, 3*REGWIDTH(t1) /* save 4th sig value, (rel mtval) into trap signature area */ + + resto_rtn: /* restore and return */ + addi t1, t1,4*REGWIDTH /* adjust trap signature ptr (traps always save 4 words) */ + SREG t1, 0*REGWIDTH(sp) /* save updated trap sig pointer (pts to trap_sigptr */ + + LREG t1, 1*REGWIDTH(sp) + LREG t2, 2*REGWIDTH(sp) + LREG t3, 3*REGWIDTH(sp) + LREG t4, 4*REGWIDTH(sp) + LREG t5, 5*REGWIDTH(sp) + LREG t6, 6*REGWIDTH(sp) /* restore temporaries */ + + csrrw sp, CSR_MSCRATCH, sp /* restore sp from scratch */ + mret + + common_mint_handler: /* t1 has sig ptr, t2 has mcause */ + + LI(t3, 1) + sll t3, t3, t2 /* create mask 1<> 1); \ + csrs mstatus, a0; \ + csrwi fcsr, 0 + +#ifdef pext_check_vxsat_ov +#define RVTEST_VXSAT_ENABLE()\ + li a0, MSTATUS_VS & (MSTATUS_VS >> 1); \ + csrs mstatus, a0; \ + clrov +#else +#define RVTEST_VXSAT_ENABLE() +#endif + +#define RVTEST_SIGBASE(_R,_TAG) \ + LA(_R,_TAG);\ + .set offset,0; + +.set offset,0; +#define _ARG5(_1ST,_2ND, _3RD,_4TH,_5TH,...) _5TH +#define _ARG4(_1ST,_2ND, _3RD,_4TH,...) _4TH +#define _ARG3(_1ST,_2ND, _3RD, ...) _3RD +#define _ARG2(_1ST,_2ND, ...) _2ND +#define _ARG1(_1ST,...) _1ST +#define NARG(...) _ARG5(__VA_OPT__(__VA_ARGS__,)4,3,2,1,0) + +#define LOAD_MEM_VAL(_LINST, _AREG, _RD, _OFF, _TREG) \ + .if _OFF >= 2048 ;\ + .set _off, _OFF%2048 ;\ + LI(_TREG, _OFF-_off) ;\ + add _AREG,_AREG,_TREG ;\ + .else ;\ + .set _off, _OFF ;\ + .endif ;\ + _LINST _RD, _off(_AREG) ;\ + .if _OFF >= 2048 ;\ + sub _AREG,_AREG,_TREG ;\ + .endif + + /* use this function to ensure individual signature stores don't exceed offset limits */ + /* if they would, then update the base by offset & reduce offset by -2048 */ + /* there is an option to pre-increment offset if there was a previous signture store */ + +#define CHK_OFFSET(_BREG, _SZ, _PRE_INC) \ + .if (_PRE_INC!=0) ;\ + .set offset, offset+_SZ ;\ + .endif ;\ + .if offset>=2048 ;\ + addi _BREG, _BREG, (2048 - _SZ) ;\ + .set offset, offset -(2048 - _SZ) ;\ + .endif + + + /* automatically adjust base and offset if offset gets too big */ + /* RVTEST_SIGUPD(basereg, sigreg) stores sigreg at offset(basereg) and updates offset by regwidth */ + /* RVTEST_SIGUPD(basereg, sigreg,newoff) stores sigreg at newoff(basereg) and updates offset to regwidth+newoff */ +#define RVTEST_SIGUPD(_BR,_R,...) \ + .if NARG(__VA_ARGS__) == 1 ;\ + .set offset,_ARG1(__VA_OPT__(__VA_ARGS__,0)) ;\ + .endif ;\ + CHK_OFFSET(_BR,REGWIDTH,0);\ + SREG _R,offset(_BR) ;\ + .set offset,offset+REGWIDTH + +#define RVTEST_SIGUPD_F(_BR,_R,_F,...) \ + .if NARG(__VA_ARGS__) == 1 ;\ + .set offset,_ARG1(__VA_OPT__(__VA_ARGS__,0)) ;\ + .endif ;\ + .if (offset & (SIGALIGN-1)) != 0 ;\ + .warning "Incorrect Offset Alignment for Signature.";\ + .err ;\ + .endif ;\ + CHK_OFFSET(_BR,SIGALIGN,0);\ + FSREG _R,offset(_BR) ;\ + CHK_OFFSET(_BR,SIGALIGN,1);\ + SREG _F,offset(_BR) ;\ + .set offset,offset+(SIGALIGN) + + +#define RVTEST_SIGUPD_FID(_BR,_R,_F,...) \ + .if NARG(__VA_ARGS__) == 1 ;\ + .set offset,_ARG1(__VA_OPT__(__VA_ARGS__,0)) ;\ + .endif ;\ + .if (offset & (SIGALIGN-1)) != 0 ;\ + .warning "Incorrect Offset Alignment for Signature.";\ + .err ;\ + .endif ;\ + CHK_OFFSET(_BR,SIGALIGN,0);\ + SREG _R,offset(_BR) ;\ + CHK_OFFSET(_BR,SIGALIGN,1);\ + SREG _F,offset(_BR) ;\ + .set offset,offset+(SIGALIGN) + +// for updating signatures when 'rd' is a paired register (64-bit) in Zpsfoperand extension in RV32. +#define RVTEST_SIGUPD_P64(_BR,_R,_R_HI,...) \ + .if NARG(__VA_ARGS__) == 0 ;\ + RVTEST_SIGUPD_FID(_BR,_R,_R_HI) ;\ + .else ;\ + RVTEST_SIGUPD_FID(_BR,_R,_R_HI,_ARG1(__VA_OPT__(__VA_ARGS__,0)));\ + .endif + +// for reading vxsat.OV flag in P-ext; and only reads the flag when Zicsr extension is present +#ifdef pext_check_vxsat_ov +#define RDOV(_F)\ + rdov _F +#else +#define RDOV(_F)\ + nop +#endif + +// for updating signatures that include flagreg when 'rd' is a paired register (64-bit) in Zpsfoperand extension in RV32. +#define RVTEST_SIGUPD_PK64(_BR,_R,_R_HI,_F,...)\ + .if NARG(__VA_ARGS__) == 1 ;\ + .set offset,_ARG1(__VA_OPT__(__VA_ARGS__,0)) ;\ + .endif ;\ + CHK_OFFSET(_BR,REGWIDTH,0);\ + SREG _R,offset(_BR) ;\ + CHK_OFFSET(_BR,REGWIDTH,1);\ + SREG _R_HI,offset+REGWIDTH(_BR) ;\ + RDOV(_F) ;\ + CHK_OFFSET(_BR,REGWIDTH,1);\ + SREG _F,offset+2*REGWIDTH(_BR) ;\ + .set offset,offset+(3*REGWIDTH) + +// for updating signatures that include flagreg for P-ext saturation instructions (RV32/RV64). +#define RVTEST_SIGUPD_PK(_BR,_R,_F,OFFSET)\ + RVTEST_SIGUPD_FID(_BR,_R,_F,OFFSET) + +#define RVTEST_VALBASEUPD(_BR,...)\ + .if NARG(__VA_ARGS__) == 0;\ + addi _BR,_BR,2040;\ + .endif;\ + .if NARG(__VA_ARGS__) == 1;\ + LA(_BR,_ARG1(__VA_ARGS__,x0));\ + .endif; + +#define RVTEST_VALBASEMOV(_NR,_BR)\ + add _NR, _BR, x0; +/* + * RVTEST_BASEUPD(base reg) - updates the base register the last signature address + REGWIDTH + * RVTEST_BASEUPD(base reg, new reg) - moves value of the next signature region to update into new reg + * The hidden variable offset is reset always +*/ + +#define RVTEST_BASEUPD(_BR,...)\ + .if NARG(__VA_ARGS__) == 0;\ + addi _BR,_BR,offset;\ + .endif;\ + .if NARG(__VA_ARGS__) == 1;\ + addi _ARG1(__VA_ARGS__,x0),_BR,offset;\ + .endif;\ + .set offset,0; + + + +//------------------------------ BORROWED FROM ANDREW's RISC-V TEST MACROS -----------------------// +#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1)) + +#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11)) + +#define TEST_JALR_OP(tempreg, rd, rs1, imm, swreg, offset,adj) \ +5: ;\ + LA(rd,5b ) ;\ + .if adj & 1 == 1 ;\ + LA(rs1, 3f-imm+adj-1 ) ;\ + jalr rd, imm+1(rs1) ;\ + .else ;\ + LA(rs1, 3f-imm+adj) ;\ + jalr rd, imm(rs1) ;\ + .endif ;\ + nop ;\ + nop ;\ + xori rd,rd, 0x2 ;\ + j 4f ;\ + ;\ +3: .if adj & 2 == 2 ;\ + .fill 2,1,0x00 ;\ + .endif ;\ + xori rd,rd, 0x3 ;\ + j 4f ;\ + .if adj&2 == 2 ;\ + .fill 2,1,0x00 ;\ + .endif ;\ + ;\ +4: LA(tempreg, 5b ) ;\ + andi tempreg,tempreg,~(3) ;\ + sub rd,rd,tempreg ;\ + RVTEST_SIGUPD(swreg,rd,offset) +//SREG rd, offset(swreg); + +#define TEST_JAL_OP(tempreg, rd, imm, label, swreg, offset, adj)\ +5: ;\ + LA(tempreg, 2f ) ;\ + jalr x0,0(tempreg) ;\ +6: LA(tempreg, 4f ) ;\ + jalr x0,0(tempreg) ;\ +1: .if (adj & 2 == 2) && (label == 1b) ;\ + .fill 2,1,0x00 ;\ + .endif ;\ + xori rd,rd, 0x1 ;\ + beq x0,x0,6b ;\ + .if (adj & 2 == 2) && (label == 1b) ;\ + .fill 2,1,0x00 ;\ + .endif ;\ + .if (imm/2) - 2 >= 0 ;\ + .set num,(imm/2)-2 ;\ + .else ;\ + .set num,0 ;\ + .endif ;\ + .ifc label, 3f ;\ + .set num,0 ;\ + .endif ;\ + .rept num ;\ + nop ;\ + .endr ;\ + ;\ +2: jal rd, label+(adj) ;\ + .if adj & 2 == 2 ;\ + nop ;\ + nop ;\ + .endif ;\ + xori rd,rd, 0x2 ;\ + j 4f ;\ + .if (imm/2) - 3 >= 0 ;\ + .set num,(imm/2)-3 ;\ + .else ;\ + .set num,0 ;\ + .endif ;\ + .ifc label, 1b ;\ + .set num,0 ;\ + .endif ;\ + .rept num ;\ + nop ;\ + .endr ;\ +3: .if (adj & 2 == 2) && (label == 3f) ;\ + .fill 2,1,0x00 ;\ + .endif ;\ + xori rd,rd, 0x3 ;\ + LA(tempreg, 4f ) ;\ + jalr x0,0(tempreg) ;\ + .if (adj&2 == 2) && (label == 3f) ;\ + .fill 2,1,0x00 ;\ + .endif ;\ +4: LA(tempreg, 5b ) ;\ + andi tempreg,tempreg,~(3) ;\ + sub rd,rd,tempreg ;\ + RVTEST_SIGUPD(swreg,rd,offset) +//SREG rd, offset(swreg); + +#define TEST_BRANCH_OP(inst, tempreg, reg1, reg2, val1, val2, imm, label, swreg, offset,adj) \ + LI(reg1, MASK_XLEN(val1)) ;\ + LI(reg2, MASK_XLEN(val2)) ;\ + addi tempreg,x0,0 ;\ + j 2f ;\ + ;\ +1: .if adj & 2 == 2 ;\ + .fill 2,1,0x00 ;\ + .endif ;\ + addi tempreg,tempreg, 0x1 ;\ + j 4f ;\ + .if adj & 2 == 2 ;\ + .fill 2,1,0x00 ;\ + .endif ;\ + .if (imm/2) - 2 >= 0 ;\ + .set num,(imm/2)-2 ;\ + .else ;\ + .set num,0 ;\ + .endif ;\ + .ifc label, 3f ;\ + .set num,0 ;\ + .endif ;\ + .rept num ;\ + nop ;\ + .endr ;\ + ;\ +2: inst reg1, reg2, label+adj ;\ + addi tempreg, tempreg,0x2 ;\ + j 4f ;\ + .if (imm/4) - 3 >= 0 ;\ + .set num,(imm/4)-3 ;\ + .else ;\ + .set num,0 ;\ + .endif ;\ + .ifc label, 1b ;\ + .set num,0 ;\ + .endif ;\ + .rept num ;\ + nop ;\ + .endr ;\ + ;\ +3: .if adj & 2 == 2 ;\ + .fill 2,1,0x00 ;\ + .endif ;\ + addi tempreg, tempreg,0x3 ;\ + j 4f ;\ + .if adj&2 == 2 ;\ + .fill 2,1,0x00 ;\ + .endif ;\ + ;\ +4: RVTEST_SIGUPD(swreg,tempreg,offset) +//SREG tempreg, offset(swreg); + +#define TEST_STORE(swreg,testreg,index,rs1,rs2,rs2_val,imm_val,offset,inst,adj) ;\ +LI(rs2,rs2_val) ;\ +addi rs1,swreg,offset+adj ;\ +LI(testreg,imm_val) ;\ +sub rs1,rs1,testreg ;\ +inst rs2, imm_val(rs1) ;\ +nop ;\ +nop + +#define TEST_LOAD(swreg,testreg,index,rs1,destreg,imm_val,offset,inst,adj) ;\ +LA(rs1,rvtest_data+(index*4)+adj-imm_val) ;\ +inst destreg, imm_val(rs1) ;\ +nop ;\ +nop ;\ +RVTEST_SIGUPD(swreg,destreg,offset) +//SREG destreg, offset(swreg); + +#define TEST_STORE_F(swreg,testreg,fcsr_val,rs1,rs2,imm_val,offset,inst,adj,flagreg,valaddr_reg, val_offset);\ +LOAD_MEM_VAL(FLREG, valaddr_reg, rs2, val_offset, testreg); \ +addi rs1,swreg,offset+adj ;\ +LI(testreg,imm_val) ;\ +sub rs1,rs1,testreg ;\ +inst rs2, imm_val(rs1) ;\ +nop ;\ +nop ;\ +csrr flagreg, fcsr ;\ +RVTEST_SIGUPD(swreg,flagreg,offset+SIGALIGN) + +#define TEST_LOAD_F(swreg,testreg,fcsr_val,rs1,destreg,imm_val,inst,adj,flagreg) ;\ +LA(rs1,rvtest_data+adj-imm_val) ;\ +LI(testreg, fcsr_val); csrw fcsr, testreg ;\ +inst destreg, imm_val(rs1) ;\ +nop ;\ +nop ;\ +csrr flagreg, fcsr ;\ +RVTEST_SIGUPD_F(swreg,destreg,flagreg) + +#define TEST_CSR_FIELD(ADDRESS,TEMP_REG,MASK_REG,NEG_MASK_REG,VAL,DEST_REG,OFFSET,BASE_REG) \ + LI(TEMP_REG,VAL);\ + and TEMP_REG,TEMP_REG,MASK_REG;\ + csrr DEST_REG,ADDRESS;\ + and DEST_REG,DEST_REG,NEG_MASK_REG;\ + or TEMP_REG,TEMP_REG,DEST_REG;\ + csrw ADDRESS,TEMP_REG;\ + csrr DEST_REG,ADDRESS;\ + RVTEST_SIGUPD(BASE_REG,DEST_REG,OFFSET) + +#define WRITE_TO_CSR_FIELD_W_MASK(ADDRESS,RESTORE_REG,TEMP_REG1,TEMP_REG2,MASK_VAL,VAL) \ + LI(TEMP_REG1,VAL);\ + LI(TEMP_REG2,MASK_VAL);\ + and TEMP_REG1,TEMP_REG1,TEMP_REG2;\ + csrr RESTORE_REG,ADDRESS;\ + not TEMP_REG2,TEMP_REG2;\ + and RESTORE_REG,RESTORE_REG,TEMP_REG2;\ + or TEMP_REG1,TEMP_REG1,RESTORE_REG;\ + csrrw RESTORE_REG,ADDRESS,TEMP_REG1;\ + +#define READ_CSR_REG_AND_UPD_SIG(ADDRESS,DEST_REG,OFFSET,BASE_REG) \ + csrr DEST_REG,ADDRESS;\ + RVTEST_SIGUPD(BASE_REG,DEST_REG,OFFSET) + +#define RESTORE_CSR_REG(ADDRESS,RESTORE_REG) \ + csrw ADDRESS,RESTORE_REG; + + +#define TEST_CASE(testreg, destreg, correctval, swreg, offset, code... ) \ + code; \ + RVTEST_SIGUPD(swreg,destreg,offset); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval) + +#define TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, code... ) \ + code; \ + RVTEST_SIGUPD_F(swreg,destreg,flagreg); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval) + +#define TEST_CASE_FID(testreg, destreg, correctval, swreg, flagreg, code... ) \ + code; \ + RVTEST_SIGUPD_FID(swreg,destreg,flagreg); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval) + +#define TEST_AUIPC(inst, destreg, correctval, imm, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + LA testreg, 1f; \ + 1: \ + inst destreg, imm; \ + sub destreg, destreg, testreg; \ + ) + +//Tests for instructions with register-immediate operand +#define TEST_IMM_OP( inst, destreg, reg, correctval, val, imm, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + LI(reg, MASK_XLEN(val)); \ + inst destreg, reg, SEXT_IMM(imm); \ + ) + +//Tests for floating-point instructions with a single register operand +#define TEST_FPSR_OP( inst, destreg, freg, rm, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \ + TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \ + LOAD_MEM_VAL(FLREG, valaddr_reg, freg, val_offset, testreg); \ + LI(testreg, fcsr_val); csrw fcsr, testreg; \ + inst destreg, freg, rm; \ + csrr flagreg, fcsr ; \ + ) + +//Tests for floating-point instructions with a single register operand +//This variant does not take the rm field and set it while writing the instruction +#define TEST_FPSR_OP_NRM( inst, destreg, freg, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \ + TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \ + LOAD_MEM_VAL(FLREG, valaddr_reg, freg, val_offset, testreg); \ + LI(testreg, fcsr_val); csrw fcsr, testreg; \ + inst destreg, freg; \ + csrr flagreg, fcsr ; \ + ) + +//Tests for floating-point instructions with a single register operand and integer destination register +#define TEST_FPID_OP( inst, destreg, freg, rm, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg,load_instr) \ + TEST_CASE_FID(testreg, destreg, correctval, swreg, flagreg, \ + LOAD_MEM_VAL(load_instr, valaddr_reg, freg, val_offset, testreg); \ + LI(testreg, fcsr_val); csrw fcsr, testreg; \ + inst destreg, freg, rm; \ + csrr flagreg, fcsr ; \ + ) + +//Tests for floating-point instructions with a single register operand and integer operand register +#define TEST_FPIO_OP( inst, destreg, freg, rm, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg, load_instr) \ + TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \ + LOAD_MEM_VAL(load_instr, valaddr_reg, freg, val_offset, testreg); \ + LI(testreg, fcsr_val); csrw fcsr, testreg; \ + inst destreg, freg, rm; \ + csrr flagreg, fcsr; \ + ) + +//Tests for floating-point instructions with a single register operand and integer destination register +//This variant does not take the rm field and set it while writing the instruction +#define TEST_FPID_OP_NRM( inst, destreg, freg, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \ + TEST_CASE_FID(testreg, destreg, correctval, swreg, flagreg, \ + LOAD_MEM_VAL(FLREG, valaddr_reg, freg, val_offset, testreg); \ + LI(testreg, fcsr_val); csrw fcsr, testreg; \ + inst destreg, freg; \ + csrr flagreg, fcsr ; \ + ) + +//Tests for floating-point instructions with one GPR operand and a single FPR result +//This variant does not take the rm field and set it while writing the instruction +#define TEST_FPIO_OP_NRM( inst, destreg, freg, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg, load_instr) \ + TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \ + LOAD_MEM_VAL(load_instr, valaddr_reg, freg, val_offset, testreg); \ + LI(testreg, fcsr_val); csrw fcsr, testreg; \ + inst destreg, freg; \ + csrr flagreg, fcsr; \ + ) + +//Tests for floating-point instructions with two GPR operands and a single FPR result +//This variant does not take the rm field and set it while writing the instruction +#define TEST_FPIOIO_OP_NRM(inst, destreg, freg1, freg2, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg, load_instr) \ + TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \ + LOAD_MEM_VAL(load_instr, valaddr_reg, freg1, val_offset, testreg); \ + LOAD_MEM_VAL(load_instr, valaddr_reg, freg2, (val_offset+FREGWIDTH), testreg); \ + LI(testreg, fcsr_val); csrw fcsr, testreg; \ + inst destreg, freg; \ + csrr flagreg, fcsr; \ + ) + +//Tests for instructions with register-register-immediate operands +#define TEST_RRI_OP(inst, destreg, reg1, reg2, imm, correctval, val1, val2, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + LI(reg1, MASK_XLEN(val1)); \ + LI(reg2, MASK_XLEN(val2)); \ + inst destreg, reg1, reg2, imm; \ + ) + +//Tests for a instructions with register-register operand +#define TEST_RI_OP(inst, destreg, reg2, imm, correctval, val1, val2, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + LI(destreg, MASK_XLEN(val1)); \ + LI(reg2, MASK_XLEN(val2)); \ + inst destreg, reg2, imm; \ + ) + +//Tests for a instructions with register-register operand +#define TEST_RR_OP(inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + LI(reg1, MASK_XLEN(val1)); \ + LI(reg2, MASK_XLEN(val2)); \ + inst destreg, reg1, reg2; \ + ) +//Tests for floating-point instructions with register-register operand +//This variant does not take the rm field and set it while writing the instruction +#define TEST_FPRR_OP_NRM(inst, destreg, freg1, freg2, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \ + TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \ + LOAD_MEM_VAL(FLREG, valaddr_reg, freg1, val_offset, testreg); \ + LOAD_MEM_VAL(FLREG, valaddr_reg, freg2, (val_offset+FREGWIDTH), testreg); \ + LI(testreg, fcsr_val); csrw fcsr, testreg; \ + inst destreg, freg1, freg2; \ + csrr flagreg, fcsr; \ + ) + +//Tests for floating-point instructions with register-register operand +#define TEST_FPRR_OP(inst, destreg, freg1, freg2, rm, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \ + TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \ + LOAD_MEM_VAL(FLREG, valaddr_reg, freg1, val_offset, testreg); \ + LOAD_MEM_VAL(FLREG, valaddr_reg, freg2, (val_offset+FREGWIDTH), testreg); \ + LI(testreg, fcsr_val); csrw fcsr, testreg; \ + inst destreg, freg1, freg2, rm; \ + csrr flagreg, fcsr; \ + ) + +//Tests for floating-point CMP instructions with register-register operand +#define TEST_FCMP_OP(inst, destreg, freg1, freg2, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \ + TEST_CASE_FID(testreg, destreg, correctval, swreg, flagreg, \ + LOAD_MEM_VAL(FLREG, valaddr_reg, freg1, val_offset, testreg); \ + LOAD_MEM_VAL(FLREG, valaddr_reg, freg2, (val_offset+FREGWIDTH), testreg); \ + LI(testreg, fcsr_val); csrw fcsr, testreg; \ + inst destreg, freg1, freg2; \ + csrr flagreg, fcsr ; \ + ) + +//Tests for floating-point R4 type instructions +#define TEST_FPR4_OP(inst, destreg, freg1, freg2, freg3, rm , fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \ + TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \ + LOAD_MEM_VAL(FLREG, valaddr_reg, freg1, val_offset, testreg); \ + LOAD_MEM_VAL(FLREG, valaddr_reg, freg2, (val_offset+FREGWIDTH), testreg); \ + LOAD_MEM_VAL(FLREG, valaddr_reg, freg3, (val_offset+2*FREGWIDTH), testreg); \ + LI(testreg, fcsr_val); csrw fcsr, testreg; \ + inst destreg, freg1, freg2, freg3, rm; \ + csrr flagreg, fcsr ; \ + ) + +#define TEST_CNOP_OP( inst, testreg, imm_val, swreg, offset) \ + TEST_CASE(testreg, x0, 0, swreg, offset, \ + inst imm_val; \ + ) + +//Tests for instructions with register-immediate operand and update the saturation flag +#define TEST_PKIMM_OP( inst, destreg, reg, correctval, val, imm, flagreg, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + LI(reg, MASK_XLEN(val)); \ + inst destreg, reg, SEXT_IMM(imm); \ + rdov flagreg; \ + ) + +//Tests for instructions with register-register operand and update the saturation flag +#define TEST_PKRR_OP(inst, destreg, reg1, reg2, correctval, val1, val2, flagreg, swreg, offset, testreg) \ + LI(reg1, MASK_XLEN(val1)); \ + LI(reg2, MASK_XLEN(val2)); \ + inst destreg, reg1, reg2; \ + rdov flagreg; \ + RVTEST_SIGUPD_PK(swreg, destreg, flagreg, offset); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval) + +//Tests for instructions with a single register operand and update the saturation flag +#define TEST_PKR_OP( inst, destreg, reg, correctval, val, flagreg, swreg, offset, testreg) \ + TEST_CASE_FID(testreg, destreg, correctval, swreg, flagreg, offset, \ + LI(reg, MASK_XLEN(val)); \ + inst destreg, reg; \ + rdov flagreg; \ + ) + +#if __riscv_xlen == 32 +//Tests for a instruction with register pair operands for all its three operands +#define TEST_P64_PPP_OP_32(inst, destreg, destreg_hi, reg1, reg1_hi, reg2, reg2_hi, correctval, correctval_hi, val1, val1_hi, val2, val2_hi, swreg, offset, testreg) \ + LI(reg1, MASK_XLEN(val1)); \ + LI(reg1_hi, MASK_XLEN(val1_hi)); \ + LI(reg2, MASK_XLEN(val2)); \ + LI(reg2_hi, MASK_XLEN(val2_hi)); \ + inst destreg, reg1, reg2; \ + RVTEST_SIGUPD_P64(swreg,destreg, destreg_hi, offset); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg_hi, correctval_hi) + +#define TEST_PK64_PPP_OP_32(inst, destreg, destreg_hi, reg1, reg1_hi, reg2, reg2_hi, correctval, correctval_hi, val1, val1_hi, val2, val2_hi, flagreg, swreg, offset, testreg) \ + LI(reg1, MASK_XLEN(val1)); \ + LI(reg1_hi, MASK_XLEN(val1_hi)); \ + LI(reg2, MASK_XLEN(val2)); \ + LI(reg2_hi, MASK_XLEN(val2_hi)); \ + inst destreg, reg1, reg2; \ + RVTEST_SIGUPD_PK64(swreg,destreg, destreg_hi, flagreg, offset); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg_hi, correctval_hi) + +#define TEST_P64_PPN_OP_32(inst, destreg, destreg_hi, reg1, reg1_hi, reg2, correctval, correctval_hi, val1, val1_hi, val2, swreg, offset, testreg) \ + LI(reg1, MASK_XLEN(val1)); \ + LI(reg1_hi, MASK_XLEN(val1_hi)); \ + LI(reg2, MASK_XLEN(val2)); \ + inst destreg, reg1, reg2; \ + RVTEST_SIGUPD_P64(swreg, destreg, destreg_hi, offset); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg_hi, correctval_hi) + +#define TEST_P64_PNN_OP_32(inst, destreg, destreg_hi, reg1, reg2, correctval, correctval_hi, val1, val2, swreg, offset, testreg) \ + LI(reg1, MASK_XLEN(val1)); \ + LI(reg2, MASK_XLEN(val2)); \ + inst destreg, reg1, reg2; \ + RVTEST_SIGUPD_P64(swreg, destreg, destreg_hi, offset); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg_hi, correctval_hi) + +#define TEST_PK64_PNN_OP_32(inst, destreg, destreg_hi, reg1, reg2, correctval, correctval_hi, val1, val2, flagreg, swreg, offset, testreg) \ + LI(reg1, MASK_XLEN(val1)); \ + LI(reg2, MASK_XLEN(val2)); \ + inst destreg, reg1, reg2; \ + RVTEST_SIGUPD_PK64(swreg, destreg, destreg_hi, flagreg, offset); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg_hi, correctval_hi) + +#define TEST_P64_NPN_OP_32(inst, destreg, reg1, reg1_hi, reg2, correctval, val1, val1_hi, val2, swreg, offset, testreg) \ + LI(reg1, MASK_XLEN(val1)); \ + LI(reg1_hi, MASK_XLEN(val1_hi)); \ + LI(reg2, MASK_XLEN(val2)); \ + inst destreg, reg1, reg2; \ + RVTEST_SIGUPD(swreg,destreg,offset); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval); + +#define TEST_P64_NP_OP_32(inst, destreg, reg1, reg1_hi, correctval, val1, val1_hi, imm_val, swreg, offset, testreg) \ + LI(reg1, MASK_XLEN(val1)); \ + LI(reg1_hi, MASK_XLEN(val1_hi)); \ + inst destreg, reg1, imm_val; \ + RVTEST_SIGUPD(swreg,destreg,offset); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval); + +//Tests for a instruction with pair register rd, pair register rs1 and pair register rs2 +#define TEST_P64_PPP_OP(inst, rd, rd_hi, rs1, rs1_hi, rs2, rs2_hi, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, rs2_val_hi, swreg, offset, testreg) \ + TEST_P64_PPP_OP_32(inst, rd, rd_hi, rs1, rs1_hi, rs2, rs2_hi, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, rs2_val_hi, swreg, offset, testreg) +#define TEST_PK64_PPP_OP(inst, rd, rd_hi, rs1, rs1_hi, rs2, rs2_hi, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, rs2_val_hi, flagreg, swreg, offset, testreg) \ + TEST_PK64_PPP_OP_32(inst, rd, rd_hi, rs1, rs1_hi, rs2, rs2_hi, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, rs2_val_hi, flagreg, swreg, offset, testreg) +//Tests for a instruction with pair register rd, pair register rs1 and normal register rs2 +#define TEST_P64_PPN_OP(inst, rd, rd_hi, rs1, rs1_hi, rs2, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, swreg, offset, testreg) \ + TEST_P64_PPN_OP_32(inst, rd, rd_hi, rs1, rs1_hi, rs2, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, swreg, offset, testreg) +//Tests for a instruction with pair register rd, normal register rs1 and normal register rs2 +#define TEST_P64_PNN_OP(inst, rd, rd_hi, rs1, rs2, correctval, correctval_hi, rs1_val, rs2_val, swreg, offset, testreg) \ + TEST_P64_PNN_OP_32(inst, rd, rd_hi, rs1, rs2, correctval, correctval_hi, rs1_val, rs2_val, swreg, offset, testreg) +//Tests for a instruction with pair register rd, normal register rs1 and normal register rs2 +#define TEST_PK64_PNN_OP(inst, rd, rd_hi, rs1, rs2, correctval, correctval_hi, rs1_val, rs2_val, flagreg, swreg, offset, testreg) \ + TEST_PK64_PNN_OP_32(inst, rd, rd_hi, rs1, rs2, correctval, correctval_hi, rs1_val, rs2_val, flagreg, swreg, offset, testreg) +//Tests for a instruction with normal register rd, pair register rs1 and normal register rs2 +#define TEST_P64_NPN_OP(inst, rd, rs1, rs1_hi, rs2, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, swreg, offset, testreg) \ + TEST_P64_NPN_OP_32(inst, rd, rs1, rs1_hi, rs2, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, swreg, offset, testreg) +//Tests for a instruction with normal register rd, pair register rs1 +#define TEST_P64_NP_OP(inst, rd, rs1, rs1_hi, correctval, correctval_hi, rs1_val, rs1_val_hi, imm_val, swreg, offset, testreg) \ + TEST_P64_NP_OP_32(inst, rd, rs1, rs1_hi, correctval, correctval_hi, rs1_val, rs1_val_hi, imm_val, swreg, offset, testreg) + +#else + +// When in rv64, there are no instructions with pair operand, so Macro is redefined to normal TEST_RR_OP +#define TEST_P64_PPP_OP(inst, rd, rd_hi, rs1, rs1_hi, rs2, rs2_hi, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, rs2_val_hi, swreg, offset, testreg) \ + TEST_RR_OP(inst, rd, rs1, rs2, correctval, rs1_val, rs2_val, swreg, offset, testreg) +#define TEST_PK64_PPP_OP(inst, rd, rd_hi, rs1, rs1_hi, rs2, rs2_hi, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, rs2_val_hi, flagreg, swreg, offset, testreg) \ + TEST_PKRR_OP(inst, rd, rs1, rs2, correctval, rs1_val, rs2_val, flagreg, swreg, offset, testreg) +#define TEST_P64_PPN_OP(inst, rd, rd_hi, rs1, rs1_hi, rs2, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, swreg, offset, testreg) \ + TEST_RR_OP(inst, rd, rs1, rs2, correctval, rs1_val, rs2_val, swreg, offset, testreg) +#define TEST_P64_PNN_OP(inst, rd, rd_hi, rs1, rs2, correctval, correctval_hi, rs1_val, rs2_val, swreg, offset, testreg) \ + TEST_RR_OP(inst, rd, rs1, rs2, correctval, rs1_val, rs2_val, swreg, offset, testreg) +#define TEST_PK64_PNN_OP(inst, rd, rd_hi, rs1, rs2, correctval, correctval_hi, rs1_val, rs2_val, flagreg, swreg, offset, testreg) \ + TEST_PKRR_OP(inst, rd, rs1, rs2, correctval, rs1_val, rs2_val, flagreg, swreg, offset, testreg) +#define TEST_P64_NPN_OP(inst, rd, rs1, rs1_hi, rs2, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, swreg, offset, testreg) \ + TEST_RR_OP(inst, rd, rs1, rs2, correctval, rs1_val, rs2_val, swreg, offset, testreg) +#define TEST_P64_NP_OP(inst, rd, rs1, rs1_hi, correctval, correctval_hi, rs1_val, rs1_val_hi, imm_val, swreg, offset, testreg) \ + TEST_IMM_OP(inst, rd, rs1, correctval, rs1_val, imm_val, swreg, offset, testreg) + +#endif + + + + +#define TEST_CMV_OP( inst, destreg, reg, correctval, val2, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + LI(reg, MASK_XLEN(val2)); \ + inst destreg, reg; \ + ) + +#define TEST_CR_OP( inst, destreg, reg, correctval, val1, val2, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + LI(reg, MASK_XLEN(val2)); \ + LI(destreg, MASK_XLEN(val1)); \ + inst destreg, reg; \ + ) + +#define TEST_CI_OP( inst, destreg, correctval, val, imm, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + LI(destreg, MASK_XLEN(val)); \ + inst destreg, imm; \ + ) + +#define TEST_CADDI4SPN_OP( inst, destreg, correctval, imm, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + LI(x2, 0); \ + inst destreg, x2,imm; \ + ) + +//Tests for instructions with a single register operand +#define TEST_RD_OP(inst, destreg, reg1, correctval, val1, swreg, offset, testreg) \ + TEST_CMV_OP(inst, destreg, reg1, correctval, val1, swreg, offset, testreg) + +#define TEST_CBRANCH_OP(inst, tempreg, reg2, val2, imm, label, swreg, offset) \ + LI(reg2, MASK_XLEN(val2)) ;\ + j 2f ;\ + addi tempreg, x0,0 ;\ + .option push ;\ + .option norvc ;\ +1: addi tempreg, tempreg,0x1 ;\ + j 4f ;\ + .option pop ;\ + .if (imm/2) - 4 >= 0 ;\ + .set num,(imm/2)-4 ;\ + .else ;\ + .set num,0 ;\ + .endif ;\ + .ifc label, 3f ;\ + .set num,0 ;\ + .endif ;\ + .rept num ;\ + c.nop ;\ + .endr ;\ +2: inst reg2, label ;\ + .option push ;\ + .option norvc ;\ + addi tempreg, tempreg, 0x2 ;\ + j 4f ;\ + .option pop ;\ + .if (imm/2) - 5 >= 0 ;\ + .set num,(imm/2)-5 ;\ + .else ;\ + .set num,0 ;\ + .endif ;\ + .ifc label, 1b ;\ + .set num,0 ;\ + .endif ;\ + .rept num ;\ + c.nop ;\ + .endr ;\ + ;\ +3: addi tempreg, tempreg ,0x3 ;\ + ;\ +4: RVTEST_SIGUPD(swreg,tempreg,offset) +//SREG tempreg, offset(swreg); + + +#define TEST_CJ_OP(inst, tempreg, imm, label, swreg, offset) \ + .option push ;\ + .option norvc ;\ + j 2f ;\ + addi tempreg,x0,0 ;\ +1: addi tempreg, tempreg,0x1 ;\ + j 4f ;\ + .option pop ;\ + .if (imm/2) - 4 >= 0 ;\ + .set num,(imm/2)-4 ;\ + .else ;\ + .set num,0 ;\ + .endif ;\ + .ifc label, 3f ;\ + .set num,0 ;\ + .endif ;\ + .rept num ;\ + c.nop ;\ + .endr ;\ +2: inst label ;\ + .option push ;\ + .option norvc ;\ + addi tempreg, tempreg, 0x2 ;\ + j 4f ;\ + .option pop ;\ + .if (imm/2) - 5 >= 0 ;\ + .set num,(imm/2)-5 ;\ + .else ;\ + .set num,0 ;\ + .endif ;\ + .ifc label, 1b ;\ + .set num,0 ;\ + .endif ;\ + .rept num ;\ + c.nop ;\ + .endr ;\ + ;\ +3: addi tempreg, tempreg, 0x3 ;\ + ;\ +4: RVTEST_SIGUPD(swreg,tempreg,offset) +//SREG tempreg, offset(swreg); + +#define TEST_CJAL_OP(inst, tempreg, imm, label, swreg, offset) \ +5: ;\ + j 2f ;\ + ;\ + .option push ;\ + .option norvc ;\ +1: xori x1,x1, 0x1 ;\ + j 4f ;\ + .option pop ;\ + .if (imm/2) - 4 >= 0 ;\ + .set num,(imm/2)-4 ;\ + .else ;\ + .set num,0 ;\ + .endif ;\ + .ifc label, 3f ;\ + .set num,0 ;\ + .endif ;\ + .rept num ;\ + c.nop ;\ + .endr ;\ +2: inst label ;\ + .option push ;\ + .option norvc ;\ + xori x1,x1, 0x2 ;\ + j 4f ;\ + .option pop ;\ + .if (imm/2) - 5 >= 0 ;\ + .set num,(imm/2)-5 ;\ + .else ;\ + .set num,0 ;\ + .endif ;\ + .ifc label, 1b ;\ + .set num,0 ;\ + .endif ;\ + .rept num ;\ + c.nop ;\ + .endr ;\ + ;\ +3: xori x1,x1, 0x3 ;\ + ;\ +4: LA(tempreg, 5b) ;\ + andi tempreg,tempreg,~(3) ;\ + sub x1,x1,tempreg ;\ + RVTEST_SIGUPD(swreg,x1,offset) +//SREG x1, offset(swreg); + +#define TEST_CJR_OP(tempreg, rs1, swreg, offset) \ +5: ;\ + LA(rs1, 3f) ;\ + ;\ +2: c.jr rs1 ;\ + xori rs1,rs1, 0x2 ;\ + j 4f ;\ + ;\ +3: xori rs1,rs1, 0x3 ;\ + ;\ +4: LA(tempreg, 5b) ;\ + andi tempreg,tempreg,~(3) ;\ + sub rs1,rs1,tempreg ;\ + RVTEST_SIGUPD(swreg,rs1,offset) +//SREG rs1, offset(swreg); + +#define TEST_CJALR_OP(tempreg, rs1, swreg, offset) \ +5: ;\ + LA(rs1, 3f ) ;\ + ;\ +2: c.jalr rs1 ;\ + xori x1,x1, 0x2 ;\ + j 4f ;\ + ;\ +3: xori x1,x1, 0x3 ;\ + ;\ +4: LA(tempreg, 5b ) ;\ + andi tempreg,tempreg,~(3) ;\ + sub x1,x1,tempreg ;\ + RVTEST_SIGUPD(swreg,x1,offset) +//SREG x1, offset(swreg); + + +//--------------------------------- Migration aliases ------------------------------------------ +#ifdef RV_COMPLIANCE_RV32M + #warning "RV_COMPLIANCE_RV32M macro will be deprecated." + #define RVMODEL_BOOT \ + RVTEST_IO_INIT; \ + RV_COMPLIANCE_RV32M ; \ + RV_COMPLIANCE_CODE_BEGIN +#endif + +#define SWSIG(a, b) + +#ifdef RV_COMPLIANCE_DATA_BEGIN + #warning "RV_COMPLIANCE_DATA_BEGIN macro deprecated in v0.2. Please use RVMODEL_DATA_BEGIN instead" + #define RVMODEL_DATA_BEGIN \ + RV_COMPLIANCE_DATA_BEGIN +#endif + +#ifdef RV_COMPLIANCE_DATA_END + #warning "RV_COMPLIANCE_DATA_END macro deprecated in v0.2. Please use RVMODEL_DATA_END instead" + #define RVMODEL_DATA_END \ + RV_COMPLIANCE_DATA_END +#endif + +#ifdef RV_COMPLIANCE_HALT + #warning "RV_COMPLIANCE_HALT macro deprecated in v0.2. Please use RVMODEL_HALT instead" + #define RVMODEL_HALT \ + RV_COMPLIANCE_HALT +#endif + +#ifdef RVTEST_IO_ASSERT_GPR_EQ + #warning "RVTEST_IO_ASSERT_GPR_EQ macro deprecated in v0.2. Please use RVMODEL_IO_ASSERT_GPR_EQ instead" + #define RVMODEL_IO_ASSERT_GPR_EQ(_SP, _R, _I) \ + RVTEST_IO_ASSERT_GPR_EQ(_SP,_R, _I) +#endif + +#ifdef RVTEST_IO_WRITE_STR + #warning "RVTEST_IO_WRITE_STR macro deprecated in v0.2. Please use RVMODEL_IO_WRITE_STR instead" + #define RVMODEL_IO_WRITE_STR(_SP, _STR) \ + RVTEST_IO_WRITE_STR(_SP, _STR) +#endif + +#ifdef RVTEST_IO_INIT + #warning "RVTEST_IO_INIT is deprecated in v0.2. Please use RVMODEL_BOOT for initialization" +#endif + +#ifdef RVTEST_IO_CHECK + #warning "RVTEST_IO_CHECK is deprecated in v0.2. +#endif diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/env/encoding.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/env/encoding.h new file mode 100644 index 000000000..9d6d8f180 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/env/encoding.h @@ -0,0 +1,1496 @@ +/* +* Copyright (c) 2012-2015, The Regents of the University of California (Regents). +* All Rights Reserved. +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. Neither the name of the Regents nor the +* names of its contributors may be used to endorse or promote products +* derived from this software without specific prior written permission. +* IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, +* SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING +* OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +* PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED +* HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE +* MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + +*/ +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_HPP 0x00000600 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_VS 0x00000600 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_SUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_TVM 0x00100000 +#define MSTATUS_TW 0x00200000 +#define MSTATUS_TSR 0x00400000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS_UXL 0x0000000300000000 +#define MSTATUS_SXL 0x0000000C00000000 +#define MSTATUS64_SD 0x8000000000000000 + +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_SUM 0x00040000 +#define SSTATUS_MXR 0x00080000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS_UXL 0x0000000300000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define DCSR_XDEBUGVER (3U<<30) +#define DCSR_NDRESET (1<<29) +#define DCSR_FULLRESET (1<<28) +#define DCSR_EBREAKM (1<<15) +#define DCSR_EBREAKH (1<<14) +#define DCSR_EBREAKS (1<<13) +#define DCSR_EBREAKU (1<<12) +#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STOPTIME (1<<9) +#define DCSR_CAUSE (7<<6) +#define DCSR_DEBUGINT (1<<5) +#define DCSR_HALT (1<<3) +#define DCSR_STEP (1<<2) +#define DCSR_PRV (3<<0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 + +#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) + +#define MCONTROL_SELECT (1<<19) +#define MCONTROL_TIMING (1<<18) +#define MCONTROL_ACTION (0x3f<<12) +#define MCONTROL_CHAIN (1<<11) +#define MCONTROL_MATCH (0xf<<7) +#define MCONTROL_M (1<<6) +#define MCONTROL_H (1<<5) +#define MCONTROL_S (1<<4) +#define MCONTROL_U (1<<3) +#define MCONTROL_EXECUTE (1<<2) +#define MCONTROL_STORE (1<<1) +#define MCONTROL_LOAD (1<<0) + +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define SATP32_MODE 0x80000000 +#define SATP32_ASID 0x7FC00000 +#define SATP32_PPN 0x003FFFFF +#define SATP64_MODE 0xF000000000000000 +#define SATP64_ASID 0x0FFFF00000000000 +#define SATP64_PPN 0x00000FFFFFFFFFFF + +#define SATP_MODE_OFF 0 +#define SATP_MODE_SV32 1 +#define SATP_MODE_SV39 8 +#define SATP_MODE_SV48 9 +#define SATP_MODE_SV57 10 +#define SATP_MODE_SV64 11 + +#define PMP_R 0x01 +#define PMP_W 0x02 +#define PMP_X 0x04 +#define PMP_A 0x18 +#define PMP_L 0x80 +#define PMP_SHIFT 2 + +#define PMP_TOR 0x08 +#define PMP_NA4 0x10 +#define PMP_NAPOT 0x18 + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#define DEFAULT_RSTVEC 0x00001000 +#define CLINT_BASE 0x02000000 +#define CLINT_SIZE 0x000c0000 +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 + +// page table entry (PTE) fields +#define PTE_V 0x001 // Valid +#define PTE_R 0x002 // Read +#define PTE_W 0x004 // Write +#define PTE_X 0x008 // Execute +#define PTE_U 0x010 // User +#define PTE_G 0x020 // Global +#define PTE_A 0x040 // Accessed +#define PTE_D 0x080 // Dirty +#define PTE_SOFT 0x300 // Reserved for Software + +#define PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#ifdef __riscv + +#if __riscv_xlen == 64 +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD +# define RISCV_PGLEVEL_BITS 9 +# define SATP_MODE SATP64_MODE +#else +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD +# define RISCV_PGLEVEL_BITS 10 +# define SATP_MODE SATP32_MODE +#endif +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +#ifdef __GNUC__ + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ + asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) + +#define swap_csr(reg, val) ({ unsigned long __tmp; \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ + __tmp; }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) + +#define rdtime() read_csr(time) +#define rdcycle() read_csr(cycle) +#define rdinstret() read_csr(instret) + +#endif + +#endif + +#endif + +#endif +/* Automatically generated by parse-opcodes. */ +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +#define MATCH_BEQ 0x63 +#define MASK_BEQ 0x707f +#define MATCH_BNE 0x1063 +#define MASK_BNE 0x707f +#define MATCH_BLT 0x4063 +#define MASK_BLT 0x707f +#define MATCH_BGE 0x5063 +#define MASK_BGE 0x707f +#define MATCH_BLTU 0x6063 +#define MASK_BLTU 0x707f +#define MATCH_BGEU 0x7063 +#define MASK_BGEU 0x707f +#define MATCH_JALR 0x67 +#define MASK_JALR 0x707f +#define MATCH_JAL 0x6f +#define MASK_JAL 0x7f +#define MATCH_LUI 0x37 +#define MASK_LUI 0x7f +#define MATCH_AUIPC 0x17 +#define MASK_AUIPC 0x7f +#define MATCH_ADDI 0x13 +#define MASK_ADDI 0x707f +#define MATCH_SLLI 0x1013 +#define MASK_SLLI 0xfc00707f +#define MATCH_SLTI 0x2013 +#define MASK_SLTI 0x707f +#define MATCH_SLTIU 0x3013 +#define MASK_SLTIU 0x707f +#define MATCH_XORI 0x4013 +#define MASK_XORI 0x707f +#define MATCH_SRLI 0x5013 +#define MASK_SRLI 0xfc00707f +#define MATCH_SRAI 0x40005013 +#define MASK_SRAI 0xfc00707f +#define MATCH_ORI 0x6013 +#define MASK_ORI 0x707f +#define MATCH_ANDI 0x7013 +#define MASK_ANDI 0x707f +#define MATCH_ADD 0x33 +#define MASK_ADD 0xfe00707f +#define MATCH_SUB 0x40000033 +#define MASK_SUB 0xfe00707f +#define MATCH_SLL 0x1033 +#define MASK_SLL 0xfe00707f +#define MATCH_SLT 0x2033 +#define MASK_SLT 0xfe00707f +#define MATCH_SLTU 0x3033 +#define MASK_SLTU 0xfe00707f +#define MATCH_XOR 0x4033 +#define MASK_XOR 0xfe00707f +#define MATCH_SRL 0x5033 +#define MASK_SRL 0xfe00707f +#define MATCH_SRA 0x40005033 +#define MASK_SRA 0xfe00707f +#define MATCH_OR 0x6033 +#define MASK_OR 0xfe00707f +#define MATCH_AND 0x7033 +#define MASK_AND 0xfe00707f +#define MATCH_ADDIW 0x1b +#define MASK_ADDIW 0x707f +#define MATCH_SLLIW 0x101b +#define MASK_SLLIW 0xfe00707f +#define MATCH_SRLIW 0x501b +#define MASK_SRLIW 0xfe00707f +#define MATCH_SRAIW 0x4000501b +#define MASK_SRAIW 0xfe00707f +#define MATCH_ADDW 0x3b +#define MASK_ADDW 0xfe00707f +#define MATCH_SUBW 0x4000003b +#define MASK_SUBW 0xfe00707f +#define MATCH_SLLW 0x103b +#define MASK_SLLW 0xfe00707f +#define MATCH_SRLW 0x503b +#define MASK_SRLW 0xfe00707f +#define MATCH_SRAW 0x4000503b +#define MASK_SRAW 0xfe00707f +#define MATCH_LB 0x3 +#define MASK_LB 0x707f +#define MATCH_LH 0x1003 +#define MASK_LH 0x707f +#define MATCH_LW 0x2003 +#define MASK_LW 0x707f +#define MATCH_LD 0x3003 +#define MASK_LD 0x707f +#define MATCH_LBU 0x4003 +#define MASK_LBU 0x707f +#define MATCH_LHU 0x5003 +#define MASK_LHU 0x707f +#define MATCH_LWU 0x6003 +#define MASK_LWU 0x707f +#define MATCH_SB 0x23 +#define MASK_SB 0x707f +#define MATCH_SH 0x1023 +#define MASK_SH 0x707f +#define MATCH_SW 0x2023 +#define MASK_SW 0x707f +#define MATCH_SD 0x3023 +#define MASK_SD 0x707f +#define MATCH_FENCE 0xf +#define MASK_FENCE 0x707f +#define MATCH_FENCE_I 0x100f +#define MASK_FENCE_I 0x707f +#define MATCH_MUL 0x2000033 +#define MASK_MUL 0xfe00707f +#define MATCH_MULH 0x2001033 +#define MASK_MULH 0xfe00707f +#define MATCH_MULHSU 0x2002033 +#define MASK_MULHSU 0xfe00707f +#define MATCH_MULHU 0x2003033 +#define MASK_MULHU 0xfe00707f +#define MATCH_DIV 0x2004033 +#define MASK_DIV 0xfe00707f +#define MATCH_DIVU 0x2005033 +#define MASK_DIVU 0xfe00707f +#define MATCH_REM 0x2006033 +#define MASK_REM 0xfe00707f +#define MATCH_REMU 0x2007033 +#define MASK_REMU 0xfe00707f +#define MATCH_MULW 0x200003b +#define MASK_MULW 0xfe00707f +#define MATCH_DIVW 0x200403b +#define MASK_DIVW 0xfe00707f +#define MATCH_DIVUW 0x200503b +#define MASK_DIVUW 0xfe00707f +#define MATCH_REMW 0x200603b +#define MASK_REMW 0xfe00707f +#define MATCH_REMUW 0x200703b +#define MASK_REMUW 0xfe00707f +#define MATCH_AMOADD_W 0x202f +#define MASK_AMOADD_W 0xf800707f +#define MATCH_AMOXOR_W 0x2000202f +#define MASK_AMOXOR_W 0xf800707f +#define MATCH_AMOOR_W 0x4000202f +#define MASK_AMOOR_W 0xf800707f +#define MATCH_AMOAND_W 0x6000202f +#define MASK_AMOAND_W 0xf800707f +#define MATCH_AMOMIN_W 0x8000202f +#define MASK_AMOMIN_W 0xf800707f +#define MATCH_AMOMAX_W 0xa000202f +#define MASK_AMOMAX_W 0xf800707f +#define MATCH_AMOMINU_W 0xc000202f +#define MASK_AMOMINU_W 0xf800707f +#define MATCH_AMOMAXU_W 0xe000202f +#define MASK_AMOMAXU_W 0xf800707f +#define MATCH_AMOSWAP_W 0x800202f +#define MASK_AMOSWAP_W 0xf800707f +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_SC_W 0x1800202f +#define MASK_SC_W 0xf800707f +#define MATCH_AMOADD_D 0x302f +#define MASK_AMOADD_D 0xf800707f +#define MATCH_AMOXOR_D 0x2000302f +#define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOOR_D 0x4000302f +#define MASK_AMOOR_D 0xf800707f +#define MATCH_AMOAND_D 0x6000302f +#define MASK_AMOAND_D 0xf800707f +#define MATCH_AMOMIN_D 0x8000302f +#define MASK_AMOMIN_D 0xf800707f +#define MATCH_AMOMAX_D 0xa000302f +#define MASK_AMOMAX_D 0xf800707f +#define MATCH_AMOMINU_D 0xc000302f +#define MASK_AMOMINU_D 0xf800707f +#define MATCH_AMOMAXU_D 0xe000302f +#define MASK_AMOMAXU_D 0xf800707f +#define MATCH_AMOSWAP_D 0x800302f +#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_LR_D 0x1000302f +#define MASK_LR_D 0xf9f0707f +#define MATCH_SC_D 0x1800302f +#define MASK_SC_D 0xf800707f +#define MATCH_ECALL 0x73 +#define MASK_ECALL 0xffffffff +#define MATCH_EBREAK 0x100073 +#define MASK_EBREAK 0xffffffff +#define MATCH_URET 0x200073 +#define MASK_URET 0xffffffff +#define MATCH_SRET 0x10200073 +#define MASK_SRET 0xffffffff +#define MATCH_MRET 0x30200073 +#define MASK_MRET 0xffffffff +#define MATCH_DRET 0x7b200073 +#define MASK_DRET 0xffffffff +#define MATCH_SFENCE_VMA 0x12000073 +#define MASK_SFENCE_VMA 0xfe007fff +#define MATCH_WFI 0x10500073 +#define MASK_WFI 0xffffffff +#define MATCH_CSRRW 0x1073 +#define MASK_CSRRW 0x707f +#define MATCH_CSRRS 0x2073 +#define MASK_CSRRS 0x707f +#define MATCH_CSRRC 0x3073 +#define MASK_CSRRC 0x707f +#define MATCH_CSRRWI 0x5073 +#define MASK_CSRRWI 0x707f +#define MATCH_CSRRSI 0x6073 +#define MASK_CSRRSI 0x707f +#define MATCH_CSRRCI 0x7073 +#define MASK_CSRRCI 0x707f +#define MATCH_FADD_S 0x53 +#define MASK_FADD_S 0xfe00007f +#define MATCH_FSUB_S 0x8000053 +#define MASK_FSUB_S 0xfe00007f +#define MATCH_FMUL_S 0x10000053 +#define MASK_FMUL_S 0xfe00007f +#define MATCH_FDIV_S 0x18000053 +#define MASK_FDIV_S 0xfe00007f +#define MATCH_FSGNJ_S 0x20000053 +#define MASK_FSGNJ_S 0xfe00707f +#define MATCH_FSGNJN_S 0x20001053 +#define MASK_FSGNJN_S 0xfe00707f +#define MATCH_FSGNJX_S 0x20002053 +#define MASK_FSGNJX_S 0xfe00707f +#define MATCH_FMIN_S 0x28000053 +#define MASK_FMIN_S 0xfe00707f +#define MATCH_FMAX_S 0x28001053 +#define MASK_FMAX_S 0xfe00707f +#define MATCH_FSQRT_S 0x58000053 +#define MASK_FSQRT_S 0xfff0007f +#define MATCH_FADD_D 0x2000053 +#define MASK_FADD_D 0xfe00007f +#define MATCH_FSUB_D 0xa000053 +#define MASK_FSUB_D 0xfe00007f +#define MATCH_FMUL_D 0x12000053 +#define MASK_FMUL_D 0xfe00007f +#define MATCH_FDIV_D 0x1a000053 +#define MASK_FDIV_D 0xfe00007f +#define MATCH_FSGNJ_D 0x22000053 +#define MASK_FSGNJ_D 0xfe00707f +#define MATCH_FSGNJN_D 0x22001053 +#define MASK_FSGNJN_D 0xfe00707f +#define MATCH_FSGNJX_D 0x22002053 +#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_FMIN_D 0x2a000053 +#define MASK_FMIN_D 0xfe00707f +#define MATCH_FMAX_D 0x2a001053 +#define MASK_FMAX_D 0xfe00707f +#define MATCH_FCVT_S_D 0x40100053 +#define MASK_FCVT_S_D 0xfff0007f +#define MATCH_FCVT_D_S 0x42000053 +#define MASK_FCVT_D_S 0xfff0007f +#define MATCH_FSQRT_D 0x5a000053 +#define MASK_FSQRT_D 0xfff0007f +#define MATCH_FADD_Q 0x6000053 +#define MASK_FADD_Q 0xfe00007f +#define MATCH_FSUB_Q 0xe000053 +#define MASK_FSUB_Q 0xfe00007f +#define MATCH_FMUL_Q 0x16000053 +#define MASK_FMUL_Q 0xfe00007f +#define MATCH_FDIV_Q 0x1e000053 +#define MASK_FDIV_Q 0xfe00007f +#define MATCH_FSGNJ_Q 0x26000053 +#define MASK_FSGNJ_Q 0xfe00707f +#define MATCH_FSGNJN_Q 0x26001053 +#define MASK_FSGNJN_Q 0xfe00707f +#define MATCH_FSGNJX_Q 0x26002053 +#define MASK_FSGNJX_Q 0xfe00707f +#define MATCH_FMIN_Q 0x2e000053 +#define MASK_FMIN_Q 0xfe00707f +#define MATCH_FMAX_Q 0x2e001053 +#define MASK_FMAX_Q 0xfe00707f +#define MATCH_FCVT_S_Q 0x40300053 +#define MASK_FCVT_S_Q 0xfff0007f +#define MATCH_FCVT_Q_S 0x46000053 +#define MASK_FCVT_Q_S 0xfff0007f +#define MATCH_FCVT_D_Q 0x42300053 +#define MASK_FCVT_D_Q 0xfff0007f +#define MATCH_FCVT_Q_D 0x46100053 +#define MASK_FCVT_Q_D 0xfff0007f +#define MATCH_FSQRT_Q 0x5e000053 +#define MASK_FSQRT_Q 0xfff0007f +#define MATCH_FLE_S 0xa0000053 +#define MASK_FLE_S 0xfe00707f +#define MATCH_FLT_S 0xa0001053 +#define MASK_FLT_S 0xfe00707f +#define MATCH_FEQ_S 0xa0002053 +#define MASK_FEQ_S 0xfe00707f +#define MATCH_FLE_D 0xa2000053 +#define MASK_FLE_D 0xfe00707f +#define MATCH_FLT_D 0xa2001053 +#define MASK_FLT_D 0xfe00707f +#define MATCH_FEQ_D 0xa2002053 +#define MASK_FEQ_D 0xfe00707f +#define MATCH_FLE_Q 0xa6000053 +#define MASK_FLE_Q 0xfe00707f +#define MATCH_FLT_Q 0xa6001053 +#define MASK_FLT_Q 0xfe00707f +#define MATCH_FEQ_Q 0xa6002053 +#define MASK_FEQ_Q 0xfe00707f +#define MATCH_FCVT_W_S 0xc0000053 +#define MASK_FCVT_W_S 0xfff0007f +#define MATCH_FCVT_WU_S 0xc0100053 +#define MASK_FCVT_WU_S 0xfff0007f +#define MATCH_FCVT_L_S 0xc0200053 +#define MASK_FCVT_L_S 0xfff0007f +#define MATCH_FCVT_LU_S 0xc0300053 +#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_FMV_X_W 0xe0000053 +#define MASK_FMV_X_W 0xfff0707f +#define MATCH_FCLASS_S 0xe0001053 +#define MASK_FCLASS_S 0xfff0707f +#define MATCH_FCVT_W_D 0xc2000053 +#define MASK_FCVT_W_D 0xfff0007f +#define MATCH_FCVT_WU_D 0xc2100053 +#define MASK_FCVT_WU_D 0xfff0007f +#define MATCH_FCVT_L_D 0xc2200053 +#define MASK_FCVT_L_D 0xfff0007f +#define MATCH_FCVT_LU_D 0xc2300053 +#define MASK_FCVT_LU_D 0xfff0007f +#define MATCH_FMV_X_D 0xe2000053 +#define MASK_FMV_X_D 0xfff0707f +#define MATCH_FCLASS_D 0xe2001053 +#define MASK_FCLASS_D 0xfff0707f +#define MATCH_FCVT_W_Q 0xc6000053 +#define MASK_FCVT_W_Q 0xfff0007f +#define MATCH_FCVT_WU_Q 0xc6100053 +#define MASK_FCVT_WU_Q 0xfff0007f +#define MATCH_FCVT_L_Q 0xc6200053 +#define MASK_FCVT_L_Q 0xfff0007f +#define MATCH_FCVT_LU_Q 0xc6300053 +#define MASK_FCVT_LU_Q 0xfff0007f +#define MATCH_FMV_X_Q 0xe6000053 +#define MASK_FMV_X_Q 0xfff0707f +#define MATCH_FCLASS_Q 0xe6001053 +#define MASK_FCLASS_Q 0xfff0707f +#define MATCH_FCVT_S_W 0xd0000053 +#define MASK_FCVT_S_W 0xfff0007f +#define MATCH_FCVT_S_WU 0xd0100053 +#define MASK_FCVT_S_WU 0xfff0007f +#define MATCH_FCVT_S_L 0xd0200053 +#define MASK_FCVT_S_L 0xfff0007f +#define MATCH_FCVT_S_LU 0xd0300053 +#define MASK_FCVT_S_LU 0xfff0007f +#define MATCH_FMV_W_X 0xf0000053 +#define MASK_FMV_W_X 0xfff0707f +#define MATCH_FCVT_D_W 0xd2000053 +#define MASK_FCVT_D_W 0xfff0007f +#define MATCH_FCVT_D_WU 0xd2100053 +#define MASK_FCVT_D_WU 0xfff0007f +#define MATCH_FCVT_D_L 0xd2200053 +#define MASK_FCVT_D_L 0xfff0007f +#define MATCH_FCVT_D_LU 0xd2300053 +#define MASK_FCVT_D_LU 0xfff0007f +#define MATCH_FMV_D_X 0xf2000053 +#define MASK_FMV_D_X 0xfff0707f +#define MATCH_FCVT_Q_W 0xd6000053 +#define MASK_FCVT_Q_W 0xfff0007f +#define MATCH_FCVT_Q_WU 0xd6100053 +#define MASK_FCVT_Q_WU 0xfff0007f +#define MATCH_FCVT_Q_L 0xd6200053 +#define MASK_FCVT_Q_L 0xfff0007f +#define MATCH_FCVT_Q_LU 0xd6300053 +#define MASK_FCVT_Q_LU 0xfff0007f +#define MATCH_FMV_Q_X 0xf6000053 +#define MASK_FMV_Q_X 0xfff0707f +#define MATCH_FLW 0x2007 +#define MASK_FLW 0x707f +#define MATCH_FLD 0x3007 +#define MASK_FLD 0x707f +#define MATCH_FLQ 0x4007 +#define MASK_FLQ 0x707f +#define MATCH_FSW 0x2027 +#define MASK_FSW 0x707f +#define MATCH_FSD 0x3027 +#define MASK_FSD 0x707f +#define MATCH_FSQ 0x4027 +#define MASK_FSQ 0x707f +#define MATCH_FMADD_S 0x43 +#define MASK_FMADD_S 0x600007f +#define MATCH_FMSUB_S 0x47 +#define MASK_FMSUB_S 0x600007f +#define MATCH_FNMSUB_S 0x4b +#define MASK_FNMSUB_S 0x600007f +#define MATCH_FNMADD_S 0x4f +#define MASK_FNMADD_S 0x600007f +#define MATCH_FMADD_D 0x2000043 +#define MASK_FMADD_D 0x600007f +#define MATCH_FMSUB_D 0x2000047 +#define MASK_FMSUB_D 0x600007f +#define MATCH_FNMSUB_D 0x200004b +#define MASK_FNMSUB_D 0x600007f +#define MATCH_FNMADD_D 0x200004f +#define MASK_FNMADD_D 0x600007f +#define MATCH_FMADD_Q 0x6000043 +#define MASK_FMADD_Q 0x600007f +#define MATCH_FMSUB_Q 0x6000047 +#define MASK_FMSUB_Q 0x600007f +#define MATCH_FNMSUB_Q 0x600004b +#define MASK_FNMSUB_Q 0x600007f +#define MATCH_FNMADD_Q 0x600004f +#define MASK_FNMADD_Q 0x600007f +#define MATCH_C_NOP 0x1 +#define MASK_C_NOP 0xffff +#define MATCH_C_ADDI16SP 0x6101 +#define MASK_C_ADDI16SP 0xef83 +#define MATCH_C_JR 0x8002 +#define MASK_C_JR 0xf07f +#define MATCH_C_JALR 0x9002 +#define MASK_C_JALR 0xf07f +#define MATCH_C_EBREAK 0x9002 +#define MASK_C_EBREAK 0xffff +#define MATCH_C_LD 0x6000 +#define MASK_C_LD 0xe003 +#define MATCH_C_SD 0xe000 +#define MASK_C_SD 0xe003 +#define MATCH_C_ADDIW 0x2001 +#define MASK_C_ADDIW 0xe003 +#define MATCH_C_LDSP 0x6002 +#define MASK_C_LDSP 0xe003 +#define MATCH_C_SDSP 0xe002 +#define MASK_C_SDSP 0xe003 +#define MATCH_C_ADDI4SPN 0x0 +#define MASK_C_ADDI4SPN 0xe003 +#define MATCH_C_FLD 0x2000 +#define MASK_C_FLD 0xe003 +#define MATCH_C_LW 0x4000 +#define MASK_C_LW 0xe003 +#define MATCH_C_FLW 0x6000 +#define MASK_C_FLW 0xe003 +#define MATCH_C_FSD 0xa000 +#define MASK_C_FSD 0xe003 +#define MATCH_C_SW 0xc000 +#define MASK_C_SW 0xe003 +#define MATCH_C_FSW 0xe000 +#define MASK_C_FSW 0xe003 +#define MATCH_C_ADDI 0x1 +#define MASK_C_ADDI 0xe003 +#define MATCH_C_JAL 0x2001 +#define MASK_C_JAL 0xe003 +#define MATCH_C_LI 0x4001 +#define MASK_C_LI 0xe003 +#define MATCH_C_LUI 0x6001 +#define MASK_C_LUI 0xe003 +#define MATCH_C_SRLI 0x8001 +#define MASK_C_SRLI 0xec03 +#define MATCH_C_SRAI 0x8401 +#define MASK_C_SRAI 0xec03 +#define MATCH_C_ANDI 0x8801 +#define MASK_C_ANDI 0xec03 +#define MATCH_C_SUB 0x8c01 +#define MASK_C_SUB 0xfc63 +#define MATCH_C_XOR 0x8c21 +#define MASK_C_XOR 0xfc63 +#define MATCH_C_OR 0x8c41 +#define MASK_C_OR 0xfc63 +#define MATCH_C_AND 0x8c61 +#define MASK_C_AND 0xfc63 +#define MATCH_C_SUBW 0x9c01 +#define MASK_C_SUBW 0xfc63 +#define MATCH_C_ADDW 0x9c21 +#define MASK_C_ADDW 0xfc63 +#define MATCH_C_J 0xa001 +#define MASK_C_J 0xe003 +#define MATCH_C_BEQZ 0xc001 +#define MASK_C_BEQZ 0xe003 +#define MATCH_C_BNEZ 0xe001 +#define MASK_C_BNEZ 0xe003 +#define MATCH_C_SLLI 0x2 +#define MASK_C_SLLI 0xe003 +#define MATCH_C_FLDSP 0x2002 +#define MASK_C_FLDSP 0xe003 +#define MATCH_C_LWSP 0x4002 +#define MASK_C_LWSP 0xe003 +#define MATCH_C_FLWSP 0x6002 +#define MASK_C_FLWSP 0xe003 +#define MATCH_C_MV 0x8002 +#define MASK_C_MV 0xf003 +#define MATCH_C_ADD 0x9002 +#define MASK_C_ADD 0xf003 +#define MATCH_C_FSDSP 0xa002 +#define MASK_C_FSDSP 0xe003 +#define MATCH_C_SWSP 0xc002 +#define MASK_C_SWSP 0xe003 +#define MATCH_C_FSWSP 0xe002 +#define MASK_C_FSWSP 0xe003 +#define MATCH_CUSTOM0 0xb +#define MASK_CUSTOM0 0x707f +#define MATCH_CUSTOM0_RS1 0x200b +#define MASK_CUSTOM0_RS1 0x707f +#define MATCH_CUSTOM0_RS1_RS2 0x300b +#define MASK_CUSTOM0_RS1_RS2 0x707f +#define MATCH_CUSTOM0_RD 0x400b +#define MASK_CUSTOM0_RD 0x707f +#define MATCH_CUSTOM0_RD_RS1 0x600b +#define MASK_CUSTOM0_RD_RS1 0x707f +#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b +#define MASK_CUSTOM0_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM1 0x2b +#define MASK_CUSTOM1 0x707f +#define MATCH_CUSTOM1_RS1 0x202b +#define MASK_CUSTOM1_RS1 0x707f +#define MATCH_CUSTOM1_RS1_RS2 0x302b +#define MASK_CUSTOM1_RS1_RS2 0x707f +#define MATCH_CUSTOM1_RD 0x402b +#define MASK_CUSTOM1_RD 0x707f +#define MATCH_CUSTOM1_RD_RS1 0x602b +#define MASK_CUSTOM1_RD_RS1 0x707f +#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b +#define MASK_CUSTOM1_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM2 0x5b +#define MASK_CUSTOM2 0x707f +#define MATCH_CUSTOM2_RS1 0x205b +#define MASK_CUSTOM2_RS1 0x707f +#define MATCH_CUSTOM2_RS1_RS2 0x305b +#define MASK_CUSTOM2_RS1_RS2 0x707f +#define MATCH_CUSTOM2_RD 0x405b +#define MASK_CUSTOM2_RD 0x707f +#define MATCH_CUSTOM2_RD_RS1 0x605b +#define MASK_CUSTOM2_RD_RS1 0x707f +#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b +#define MASK_CUSTOM2_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM3 0x7b +#define MASK_CUSTOM3 0x707f +#define MATCH_CUSTOM3_RS1 0x207b +#define MASK_CUSTOM3_RS1 0x707f +#define MATCH_CUSTOM3_RS1_RS2 0x307b +#define MASK_CUSTOM3_RS1_RS2 0x707f +#define MATCH_CUSTOM3_RD 0x407b +#define MASK_CUSTOM3_RD 0x707f +#define MATCH_CUSTOM3_RD_RS1 0x607b +#define MASK_CUSTOM3_RD_RS1 0x707f +#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b +#define MASK_CUSTOM3_RD_RS1_RS2 0x707f +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 +#define CSR_SATP 0x180 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MTVAL 0x343 +#define CSR_MIP 0x344 +#define CSR_PMPCFG0 0x3a0 +#define CSR_PMPCFG1 0x3a1 +#define CSR_PMPCFG2 0x3a2 +#define CSR_PMPCFG3 0x3a3 +#define CSR_PMPADDR0 0x3b0 +#define CSR_PMPADDR1 0x3b1 +#define CSR_PMPADDR2 0x3b2 +#define CSR_PMPADDR3 0x3b3 +#define CSR_PMPADDR4 0x3b4 +#define CSR_PMPADDR5 0x3b5 +#define CSR_PMPADDR6 0x3b6 +#define CSR_PMPADDR7 0x3b7 +#define CSR_PMPADDR8 0x3b8 +#define CSR_PMPADDR9 0x3b9 +#define CSR_PMPADDR10 0x3ba +#define CSR_PMPADDR11 0x3bb +#define CSR_PMPADDR12 0x3bc +#define CSR_PMPADDR13 0x3bd +#define CSR_PMPADDR14 0x3be +#define CSR_PMPADDR15 0x3bf +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FETCH_ACCESS 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_LOAD_ACCESS 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_STORE_ACCESS 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#define CAUSE_FETCH_PAGE_FAULT 0xc +#define CAUSE_LOAD_PAGE_FAULT 0xd +#define CAUSE_STORE_PAGE_FAULT 0xf +#define CSR_MENTROPY 0xF15 +#define CSR_MNOISE 0x7A9 +#endif +#ifdef DECLARE_INSN +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(uret, MATCH_URET, MASK_URET) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) +DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) +DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) +DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) +DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) +DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) +DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) +DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) +DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) +DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) +DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) +DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) +DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) +DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) +DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) +DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) +DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) +DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) +DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) +DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q) +DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) +DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) +DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) +DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) +DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) +DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) +DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) +DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) +DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) +DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) +DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) +DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) +DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) +DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) +DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) +DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) +DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) +DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) +DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) +DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) +DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) +DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) +DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) +DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) +DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) +DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) +DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) +DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) +DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) +DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) +DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) +DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) +DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) +DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) +DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) +DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) +DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) +DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) +DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) +DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) +DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) +DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) +DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) +DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) +DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) +#endif +#ifdef DECLARE_CSR +DECLARE_CSR(fflags, CSR_FFLAGS) +DECLARE_CSR(frm, CSR_FRM) +DECLARE_CSR(fcsr, CSR_FCSR) +DECLARE_CSR(cycle, CSR_CYCLE) +DECLARE_CSR(time, CSR_TIME) +DECLARE_CSR(instret, CSR_INSTRET) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) +DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(sie, CSR_SIE) +DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(scounteren, CSR_SCOUNTEREN) +DECLARE_CSR(sscratch, CSR_SSCRATCH) +DECLARE_CSR(sepc, CSR_SEPC) +DECLARE_CSR(scause, CSR_SCAUSE) +DECLARE_CSR(stval, CSR_STVAL) +DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(satp, CSR_SATP) +DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(misa, CSR_MISA) +DECLARE_CSR(medeleg, CSR_MEDELEG) +DECLARE_CSR(mideleg, CSR_MIDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) +DECLARE_CSR(mscratch, CSR_MSCRATCH) +DECLARE_CSR(mepc, CSR_MEPC) +DECLARE_CSR(mcause, CSR_MCAUSE) +DECLARE_CSR(mtval, CSR_MTVAL) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) +DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) +DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) +DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) +DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) +DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) +DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) +DECLARE_CSR(pmpaddr3, CSR_PMPADDR3) +DECLARE_CSR(pmpaddr4, CSR_PMPADDR4) +DECLARE_CSR(pmpaddr5, CSR_PMPADDR5) +DECLARE_CSR(pmpaddr6, CSR_PMPADDR6) +DECLARE_CSR(pmpaddr7, CSR_PMPADDR7) +DECLARE_CSR(pmpaddr8, CSR_PMPADDR8) +DECLARE_CSR(pmpaddr9, CSR_PMPADDR9) +DECLARE_CSR(pmpaddr10, CSR_PMPADDR10) +DECLARE_CSR(pmpaddr11, CSR_PMPADDR11) +DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) +DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) +DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) +DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) +DECLARE_CSR(tselect, CSR_TSELECT) +DECLARE_CSR(tdata1, CSR_TDATA1) +DECLARE_CSR(tdata2, CSR_TDATA2) +DECLARE_CSR(tdata3, CSR_TDATA3) +DECLARE_CSR(dcsr, CSR_DCSR) +DECLARE_CSR(dpc, CSR_DPC) +DECLARE_CSR(dscratch, CSR_DSCRATCH) +DECLARE_CSR(mcycle, CSR_MCYCLE) +DECLARE_CSR(minstret, CSR_MINSTRET) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) +DECLARE_CSR(mvendorid, CSR_MVENDORID) +DECLARE_CSR(marchid, CSR_MARCHID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(cycleh, CSR_CYCLEH) +DECLARE_CSR(timeh, CSR_TIMEH) +DECLARE_CSR(instreth, CSR_INSTRETH) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) +DECLARE_CSR(mcycleh, CSR_MCYCLEH) +DECLARE_CSR(minstreth, CSR_MINSTRETH) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) +#endif +#ifdef DECLARE_CAUSE +DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) +DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS) +DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) +DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) +DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) +DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS) +DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) +DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS) +DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) +DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) +DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) +DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) +DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) +DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) +DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT) +#endif diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/env/riscv-isac.code-workspace b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/env/riscv-isac.code-workspace new file mode 100644 index 000000000..edb2dc3e8 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/env/riscv-isac.code-workspace @@ -0,0 +1,20 @@ +{ + "folders": [ + { + "path": "../../../riscv-isac" + }, + { + "path": "../../../cvw" + }, + { + "path": "../.." + }, + { + "path": "../../../riscv-arch-test" + }, + { + "path": "../../../riscof" + } + ], + "settings": {} +} \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/function_generators.py b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/function_generators.py new file mode 100644 index 000000000..4bdecd668 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/function_generators.py @@ -0,0 +1,368 @@ +def get_cond_generator(opcode,fmt,val_vars,xlen,flen): + def fr128_generator(req_val_comb): + def condition(*argv): + rs1_val = argv[0] + rs2_val = argv[1] + rm = argv[2] + bin_val = '{:0128b}'.format(rs1_val) + fs1 = int(bin_val[0],2) + fe1 = int(bin_val[1:16],2) + fm1 = int(bin_val[16:],2) + bin_val = '{:064b}'.format(rs2_val) + fs2 = int(bin_val[0],2) + fe2 = int(bin_val[1:16],2) + fm2 = int(bin_val[16:],2) + return eval(req_val_comb) + return condition + def fr64_generator(req_val_comb): + def condition(*argv): + rs1_val = argv[0] + rs2_val = argv[1] + rm = argv[2] + bin_val = '{:064b}'.format(rs1_val) + fs1 = int(bin_val[0],2) + fe1 = int(bin_val[1:12],2) + fm1 = int(bin_val[12:],2) + bin_val = '{:064b}'.format(rs2_val) + fs2 = int(bin_val[0],2) + fe2 = int(bin_val[1:12],2) + fm2 = int(bin_val[12:],2) + return eval(req_val_comb) + return condition + + def fr32_generator(req_val_comb): + def condition(*argv): + rs1_val = argv[0] + rs2_val = argv[1] + rm = argv[2] + bin_val = '{:032b}'.format(rs1_val) + fs1 = int(bin_val[0],2) + fe1 = int(bin_val[1:9],2) + fm1 = int(bin_val[9:],2) + bin_val = '{:032b}'.format(rs2_val) + fs2 = int(bin_val[0],2) + fe2 = int(bin_val[1:9],2) + fm2 = int(bin_val[9:],2) + return eval(req_val_comb) + return condition + def fsr128_generator(req_val_comb): + def condition(*argv): + rs1_val = argv[0] + rm = argv[1] + bin_val = '{:0128b}'.format(rs1_val) + fs1 = int(bin_val[0],2) + fe1 = int(bin_val[1:16],2) + fm1 = int(bin_val[16:],2) + return eval(req_val_comb) + return condition + def fsr64_generator(req_val_comb): + def condition(*argv): + rs1_val = argv[0] + rm = argv[1] + bin_val = '{:064b}'.format(rs1_val) + fs1 = int(bin_val[0],2) + fe1 = int(bin_val[1:12],2) + fm1 = int(bin_val[12:],2) + return eval(req_val_comb) + return condition + + def fsr32_generator(req_val_comb): + def condition(*argv): + rs1_val = argv[0] + rm = argv[1] + bin_val = '{:032b}'.format(rs1_val) + fs1 = int(bin_val[0],2) + fe1 = int(bin_val[1:9],2) + fm1 = int(bin_val[9:],2) + return eval(req_val_comb) + return condition + def fr4_128_generator(req_val_comb): + def condition(*argv): + rs1_val = argv[0] + rs2_val = argv[1] + rs3_val = argv[2] + rm = argv[3] + bin_val = '{:0128b}'.format(rs1_val) + fs1 = int(bin_val[0],2) + fe1 = int(bin_val[1:16],2) + fm1 = int(bin_val[16:],2) + bin_val = '{:0128b}'.format(rs2_val) + fs2 = int(bin_val[0],2) + fe2 = int(bin_val[1:16],2) + fm2 = int(bin_val[16:],2) + bin_val = '{:0128b}'.format(rs3_val) + fs3 = int(bin_val[0],2) + fe3 = int(bin_val[1:16],2) + fm3 = int(bin_val[16:],2) + return eval(req_val_comb) + return condition + + def fr4_64_generator(req_val_comb): + def condition(*argv): + rs1_val = argv[0] + rs2_val = argv[1] + rs3_val = argv[2] + rm = argv[3] + bin_val = '{:064b}'.format(rs1_val) + fs1 = int(bin_val[0],2) + fe1 = int(bin_val[1:12],2) + fm1 = int(bin_val[12:],2) + bin_val = '{:064b}'.format(rs2_val) + fs2 = int(bin_val[0],2) + fe2 = int(bin_val[1:12],2) + fm2 = int(bin_val[12:],2) + bin_val = '{:064b}'.format(rs3_val) + fs3 = int(bin_val[0],2) + fe3 = int(bin_val[1:12],2) + fm3 = int(bin_val[12:],2) + return eval(req_val_comb) + return condition + + def fr4_32_generator(req_val_comb): + def condition(*argv): + rs1_val = argv[0] + rs2_val = argv[1] + rs3_val = argv[2] + rm = argv[3] + bin_val = '{:032b}'.format(rs1_val) + fs1 = int(bin_val[0],2) + fe1 = int(bin_val[1:9],2) + fm1 = int(bin_val[9:],2) + bin_val = '{:032b}'.format(rs2_val) + fs2 = int(bin_val[0],2) + fe2 = int(bin_val[1:9],2) + fm2 = int(bin_val[9:],2) + bin_val = '{:032b}'.format(rs3_val) + fs3 = int(bin_val[0],2) + fe3 = int(bin_val[1:9],2) + fm3 = int(bin_val[9:],2) + return eval(req_val_comb) + return condition + + def i_generator(req_val_comb): + def condition(*argv): + for var,val in zip(val_vars,argv): + locals()[var]=val + return eval(req_val_comb) + return condition + + if opcode[0] == 'f' and 'fence' not in opcode: + if fmt == 'frformat': + if flen == 32: + return fr32_generator + elif flen == 64: + return fr64_generator + else: + return fr128_generator + elif fmt == 'fsrformat': + if flen == 32: + return fsr32_generator + elif flen == 64: + return fsr64_generator + else: + return fsr128_generator + elif fmt == 'fr4format': + if flen == 32: + return fr4_32_generator + elif flen == 64: + return fr4_64_generator + else: + return fr4_128_generator + else: + return i_generator + +def get_filter_generator(opcode,fmt,val_vars,xlen,flen): + def fr128_generator(argv): + bin_val1 = '{:0128b}'.format(argv[0]) + bin_val2 = '{:0128b}'.format(argv[1]) + local = { + 'rs1_val': argv[0] + ,'rs2_val': argv[1] + ,'rm': argv[2] + ,'fs1': int(bin_val1[0],2) + ,'fe1': int(bin_val1[1:16],2) + ,'fm1': int(bin_val1[16:],2) + ,'fs2': int(bin_val2[0],2) + ,'fe2': int(bin_val2[1:16],2) + ,'fm2': int(bin_val2[16:],2) + } + def filter_func(cond): + return eval(cond,{},local) + return filter_func + def fr64_generator(argv): + bin_val1 = '{:064b}'.format(argv[0]) + bin_val2 = '{:064b}'.format(argv[1]) + local = { + 'rs1_val': argv[0] + ,'rs2_val': argv[1] + ,'rm': argv[2] + ,'fs1': int(bin_val1[0],2) + ,'fe1': int(bin_val1[1:12],2) + ,'fm1': int(bin_val1[12:],2) + ,'fs2': int(bin_val2[0],2) + ,'fe2': int(bin_val2[1:12],2) + ,'fm2': int(bin_val2[12:],2) + } + def filter_func(cond): + return eval(cond,{},local) + return filter_func + + def fr32_generator(argv): + bin_val1 = '{:032b}'.format(argv[0]) + bin_val2 = '{:032b}'.format(argv[1]) + local = { + 'rs1_val': argv[0] + ,'rs2_val': argv[1] + ,'rm': argv[2] + ,'fs1': int(bin_val1[0],2) + ,'fe1': int(bin_val1[1:9],2) + ,'fm1': int(bin_val1[9:],2) + ,'fs2': int(bin_val2[0],2) + ,'fe2': int(bin_val2[1:9],2) + ,'fm2': int(bin_val2[9:],2) + } + def filter_func(cond): + return eval(cond,{},local) + return filter_func + + def fsr128_generator(argv): + bin_val1 = '{:0128b}'.format(argv[0]) + local = { + 'rs1_val': argv[0] + ,'rm': argv[1] + ,'fs1': int(bin_val1[0],2) + ,'fe1': int(bin_val1[1:16],2) + ,'fm1': int(bin_val1[16:],2) + } + def filter_func(cond): + return eval(cond,{},local) + return filter_func + + def fsr64_generator(argv): + bin_val1 = '{:064b}'.format(argv[0]) + local = { + 'rs1_val': argv[0] + ,'rm': argv[1] + ,'fs1': int(bin_val1[0],2) + ,'fe1': int(bin_val1[1:12],2) + ,'fm1': int(bin_val1[12:],2) + } + def filter_func(cond): + return eval(cond,{},local) + return filter_func + + def fsr32_generator(argv): + bin_val1 = '{:032b}'.format(argv[0]) + local = { + 'rs1_val': argv[0] + ,'rm': argv[1] + ,'fs1': int(bin_val1[0],2) + ,'fe1': int(bin_val1[1:9],2) + ,'fm1': int(bin_val1[9:],2) + } + def filter_func(cond): + return eval(cond,{},local) + return filter_func + + def fr4_128_generator(argv): + bin_val1 = '{:0128b}'.format(argv[0]) + bin_val2 = '{:0128b}'.format(argv[1]) + bin_val3 = '{:0128b}'.format(argv[2]) + local = { + 'rs1_val': argv[0] + ,'rs2_val': argv[1] + ,'rs3_val': argv[2] + ,'rm': argv[3] + ,'fs1': int(bin_val1[0],2) + ,'fe1': int(bin_val1[1:16],2) + ,'fm1': int(bin_val1[16:],2) + ,'fs2': int(bin_val2[0],2) + ,'fe2': int(bin_val2[1:16],2) + ,'fm2': int(bin_val2[16:],2) + ,'fs3': int(bin_val3[0],2) + ,'fe3': int(bin_val3[1:16],2) + ,'fm3': int(bin_val3[16:],2) + } + def filter_func(cond): + return eval(cond,{},local) + return filter_func + def fr4_64_generator(argv): + bin_val1 = '{:064b}'.format(argv[0]) + bin_val2 = '{:064b}'.format(argv[1]) + bin_val3 = '{:064b}'.format(argv[2]) + local = { + 'rs1_val': argv[0] + ,'rs2_val': argv[1] + ,'rs3_val': argv[2] + ,'rm': argv[3] + ,'fs1': int(bin_val1[0],2) + ,'fe1': int(bin_val1[1:12],2) + ,'fm1': int(bin_val1[12:],2) + ,'fs2': int(bin_val2[0],2) + ,'fe2': int(bin_val2[1:12],2) + ,'fm2': int(bin_val2[12:],2) + ,'fs3': int(bin_val3[0],2) + ,'fe3': int(bin_val3[1:12],2) + ,'fm3': int(bin_val3[12:],2) + } + def filter_func(cond): + return eval(cond,{},local) + return filter_func + + def fr4_32_generator(argv): + bin_val1 = '{:032b}'.format(argv[0]) + bin_val2 = '{:032b}'.format(argv[1]) + bin_val3 = '{:032b}'.format(argv[2]) + local = { + 'rs1_val': argv[0] + ,'rs2_val': argv[1] + ,'rs3_val': argv[2] + ,'rm': argv[3] + ,'fs1': int(bin_val1[0],2) + ,'fe1': int(bin_val1[1:9],2) + ,'fm1': int(bin_val1[9:],2) + ,'fs2': int(bin_val2[0],2) + ,'fe2': int(bin_val2[1:9],2) + ,'fm2': int(bin_val2[9:],2) + ,'fs3': int(bin_val3[0],2) + ,'fe3': int(bin_val3[1:9],2) + ,'fm3': int(bin_val3[9:],2) + } + def filter_func(cond): + return eval(cond,{},local) + return filter_func + + + def i_generator(argv): + local = {} + for var,val in zip(val_vars,argv): + local[var]=val + def condition(req_val_comb): + return eval(req_val_comb,{},local) + return condition + + if opcode[0] == 'f' and 'fence' not in opcode: + if fmt == 'frformat': + if flen == 32: + return fr32_generator + elif flen == 64: + return fr64_generator + else: + return fr128_generator + elif fmt == 'fsrformat': + if flen == 32: + return fsr32_generator + elif flen == 64: + return fsr64_generator + else: + return fsr128_generator + elif fmt == 'fr4format': + if flen == 32: + return fr4_32_generator + elif flen == 64: + return fr4_64_generator + else: + return fr4_128_generator + else: + return i_generator + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/generator.py b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/generator.py new file mode 100644 index 000000000..0e3216e7e --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/generator.py @@ -0,0 +1,1424 @@ +# See LICENSE.incore for details +import random +from collections import defaultdict +from constraint import * +import re +from riscv_ctg.constants import * +from riscv_ctg.log import logger +from riscv_ctg.helpers import * +from riscv_isac.InstructionObject import instructionObject +import time +from math import * +import struct +import sys +import itertools +import re + +# F +one_operand_finstructions = ["fsqrt.s","fmv.x.w","fcvt.wu.s","fcvt.w.s","fclass.s","fcvt.l.s","fcvt.lu.s","fcvt.s.l","fcvt.s.lu"] +two_operand_finstructions = ["fadd.s","fsub.s","fmul.s","fdiv.s","fmax.s","fmin.s","feq.s","flt.s","fle.s","fsgnj.s","fsgnjn.s","fsgnjx.s"] +three_operand_finstructions = ["fmadd.s","fmsub.s","fnmadd.s","fnmsub.s"] +# Zfa/F: +one_operand_finstructions += ["fround.s", "froundnx.s", "fcvtmod.w.d","fmvh.x.d"] +two_operand_finstructions += ["fmaxm.s", "fminm.s", "fmvp.d.x", "fleq.s", "fltq.s"] + +# D +one_operand_dinstructions = ["fsqrt.d","fclass.d","fcvt.w.d","fcvt.wu.d","fcvt.d.w","fcvt.d.wu","fcvt.d.s","fcvt.s.d"] +two_operand_dinstructions = ["fadd.d","fsub.d","fmul.d","fdiv.d","fmax.d","fmin.d","feq.d","flt.d","fle.d","fsgnj.d","fsgnjn.d","fsgnjx.d"] +three_operand_dinstructions = ["fmadd.d","fmsub.d","fnmadd.d","fnmsub.d"] +# Q +one_operand_qinstructions = ["fsqrt.q","fclass.q","fcvt.w.q","fcvt.wu.q","fcvt.q.w","fcvt.q.wu","fcvt.q.d","fcvt.d.q","fcvt.q.s","fcvt.s.q"] +two_operand_qinstructions = ["fadd.q","fsub.q","fmul.q","fdiv.q","fmax.q","fmin.q","feq.q","flt.q","fle.q","fsgnj.q","fsgnjn.q","fsgnjx.q"] +three_operand_qinstructions = ["fmadd.q","fmsub.q","fnmadd.q","fnmsub.q"] +# Zfa/D: +one_operand_dinstructions += ["fround.d", "froundnx.d"] +two_operand_dinstructions += ["fmaxm.d", "fminm.d", "fleq.d", "fltq.d"] + + +def is_fp_instruction(insn): + ''' + Takes an instruction string (e.g. 'fadd.s') and returns True if it is a FP instruction. + The function is compatible with all existing and future RISC-V ISA extensions. + + :param insn: String representing an instruction (e.g. 'fadd.s', 'lw') + ''' + return type(insn) == str and insn.lower()[0] == 'f' + +from riscv_ctg.dsp_function import * + +twos_xlen = lambda x: twos(x,xlen) + +def toint(x: str): + if '0x' in x: + return int(x,16) + else: + return int(x) + +def get_rm(opcode): + insns = ['fsgnj','fle','flt','feq','fclass','fmv','flw','fsw','fld','fsd','fmin','fmax', + 'fcvt.d.s', 'fcvt.d.w','fcvt.d.wu'] + insns += ['fminm', 'fmaxm'] + if any([x in opcode for x in insns]): + return [] + else: + return ['rm_val'] + +OPS = { + 'rformat': ['rs1', 'rs2', 'rd'], + 'r4format': ['rs1', 'rs2', 'rs3', 'rd'], + 'iformat': ['rs1', 'rd'], + 'sformat': ['rs1', 'rs2'], + 'bsformat': ['rs1', 'rs2', 'rd'], + 'bformat': ['rs1', 'rs2'], + 'uformat': ['rd'], + 'jformat': ['rd'], + 'crformat': ['rs1', 'rs2'], + 'cmvformat': ['rd', 'rs2'], + 'ciformat': ['rd'], + 'cssformat': ['rs2'], + 'ciwformat': ['rd'], + 'clformat': ['rd', 'rs1'], + 'csformat': ['rs1', 'rs2'], + 'caformat': ['rs1', 'rs2'], + 'cbformat': ['rs1'], + 'cjformat': [], + 'kformat': ['rs1','rd'], + 'ckformat': ['rs1'], + # 'frformat': ['rs1', 'rs2', 'rd'], + 'fsrformat': ['rs1', 'rd'], + # 'fr4format': ['rs1', 'rs2', 'rs3', 'rd'], + 'pbrrformat': ['rs1', 'rs2', 'rd'], + 'phrrformat': ['rs1', 'rs2', 'rd'], + 'pbrformat': ['rs1', 'rd'], + 'phrformat': ['rs1', 'rd'], + 'pbriformat': ['rs1', 'rd'], + 'phriformat': ['rs1', 'rd'], + 'psbrrformat': ['rs1', 'rs2', 'rd'], + 'pshrrformat': ['rs1', 'rs2', 'rd'], + 'pwrrformat': ['rs1', 'rs2', 'rd'], + 'pwriformat': ['rs1', 'rd'], + 'pwrformat': ['rs1', 'rd'], + 'pswrrformat': ['rs1', 'rs2', 'rd'], + 'pwhrrformat': ['rs1', 'rs2', 'rd'], + 'pphrrformat': ['rs1', 'rs2', 'rd'], + 'ppbrrformat': ['rs1', 'rs2', 'rd'], + 'prrformat': ['rs1', 'rs2', 'rd'], + 'prrrformat': ['rs1', 'rs2', 'rs3', 'rd'], + 'dcasrformat': ['rs1', 'rs2', 'rd'] +} +''' Dictionary mapping instruction formats to operands used by those formats ''' + +VALS = { + 'rformat': "['rs1_val', 'rs2_val'] + ((get_rm(opcode)+['fcsr']) if is_fext else []) + \ + ([] if not is_nan_box else ['rs{0}_nan_prefix'.format(x) for x in range(1,3)])", + 'r4format': "['rs1_val', 'rs2_val', 'rs3_val'] + (['rm_val','fcsr'] if is_fext else []) + \ + ([] if not is_nan_box else ['rs{0}_nan_prefix'.format(x) for x in range(1,4)])", + 'iformat': "['rs1_val', 'imm_val'] + ([] if not is_fext else ['fcsr'])", + 'sformat': "['rs1_val', 'rs2_val', 'imm_val'] + ([] if not is_fext else ['fcsr'])", + 'bsformat': "['rs1_val', 'rs2_val', 'imm_val']", + 'bformat': "['rs1_val', 'rs2_val', 'imm_val']", + 'uformat': "['imm_val']", + 'jformat': "['imm_val']", + 'crformat': "['rs1_val', 'rs2_val']", + 'cmvformat': "['rs2_val']", + 'ciformat': "['rs1_val', 'imm_val']", + 'cssformat': "['rs2_val', 'imm_val']", + 'ciwformat': "['imm_val']", + 'clformat': "['rs1_val', 'imm_val']", + 'csformat': "['rs1_val', 'rs2_val', 'imm_val']", + 'caformat': "['rs1_val', 'rs2_val']", + 'cbformat': "['rs1_val', 'imm_val']", + 'cjformat': "['imm_val']", + 'kformat': "['rs1_val']", + 'ckformat': "['rs1_val']", + # 'frformat': "['rs1_val', 'rs2_val', 'rm_val', 'fcsr']", + 'fsrformat': "['rs1_val', 'fcsr'] + get_rm(opcode) + \ + ([] if not is_nan_box else ['rs1_nan_prefix'])", + # 'fr4format': "['rs1_val', 'rs2_val', 'rs3_val', 'rm_val', 'fcsr']", + 'pbrrformat': 'simd_val_vars("rs1", xlen, 8) + simd_val_vars("rs2", xlen, 8)', + 'phrrformat': 'simd_val_vars("rs1", xlen, 16) + simd_val_vars("rs2", xlen, 16)', + 'pbrformat': 'simd_val_vars("rs1", xlen, 8)', + 'phrformat': 'simd_val_vars("rs1", xlen, 16)', + 'pbriformat': 'simd_val_vars("rs1", xlen, 8) + ["imm_val"]', + 'phriformat': 'simd_val_vars("rs1", xlen, 16) + ["imm_val"]', + 'psbrrformat': 'simd_val_vars("rs1", xlen, 8) + ["rs2_val"]', + 'pshrrformat': 'simd_val_vars("rs1", xlen, 16) + ["rs2_val"]', + 'pwrrformat': 'simd_val_vars("rs1", xlen, 32) + simd_val_vars("rs2", xlen, 32)', + 'pwriformat': 'simd_val_vars("rs1", xlen, 32) + ["imm_val"]', + 'pwrformat': 'simd_val_vars("rs1", xlen, 32)', + 'pswrrformat': 'simd_val_vars("rs1", xlen, 32) + ["rs2_val"]', + 'pwhrrformat': 'simd_val_vars("rs1", xlen, 32) + simd_val_vars("rs2", xlen, 16)', + 'pphrrformat': '["rs1_val"] + simd_val_vars("rs2", xlen, 16)', + 'ppbrrformat': '["rs1_val"] + simd_val_vars("rs2", xlen, 8)', + 'prrformat': '["rs1_val", "rs2_val"]', + 'prrrformat': "['rs1_val', 'rs2_val' , 'rs3_val']", + 'dcasrformat': '["rs1_val", "rs2_val"]' +} +''' Dictionary mapping instruction formats to operand value variables used by those formats ''' + + + + +def isInt(s): + ''' + Utility function to check if the variable is an int type. Returns False if + not. + ''' + try: + int(s) + return True + except ValueError: + return False + +def get_default_registers(ops, datasets): + problem = Problem() + not_x0 = lambda x: x not in ['x0'] + + for op in ops: + dataset = datasets[op] + # problem.addVariable(op,list(random.sample(dataset, len(dataset)))) + problem.addVariable(op,dataset) + problem.addConstraint(not_x0,tuple([op])) + if len(ops) > 1: + cond = " and ".join(["!=".join(x) for x in itertools.combinations(ops,2) if x[0]!=x[1]]) + else: + cond = 'True' + def unique_constraint(*args): + for var,val in zip(ops,args): + locals()[var] = val + return eval(cond) + problem.addConstraint(unique_constraint,tuple(ops)) + solution = None + count = 0 + while solution is None and count < 5: + solution = problem.getSolution() + count += 1 + if count == 5: + return [] + else: + return solution + +class Generator(): + ''' + A generator class to generate RISC-V assembly tests for a given instruction + format, opcode and a set of coverpoints. + + :param fmt: the RISC-V instruction format type to be used for the test generation. + :param opnode: dictionary node from the attributes YAML that is to be used in the test generation. + :param opcode: name of the instruction opcode. + :param randomization: a boolean variable indicating if the random constraint solvers must be employed. + :param xl: an integer indicating the XLEN value to be used. + :param base_isa_str: The base isa to be used for the tests. One of [rv32e,rv32i,rv64i] + + :type fmt: str + :type opnode: dict + :type opcode: str + :type randomization: bool + :type xl: int + :type base_isa_str: str + ''' + def __init__(self,fmt,opnode,opcode,randomization, xl, fl, ifl ,base_isa_str): + ''' + This is a Constructor function which initializes various class variables + depending on the arguments. + + The function also creates a dictionary of datasets for each operand. The + dictionary basically indicates what registers from the register file are to be used + when generating solutions for coverpoints. The datasets are limited to + to reduce the time taken by solvers to arrive at a solution. + + A similar dictionary is created for the values to be used by the operand + registers. + + ''' + global xlen + global flen + global iflen + global base_isa + xlen = xl + flen = fl + iflen = ifl + base_isa = base_isa_str + + + is_nan_box = False + is_fext = any(['F' in x or 'D' in x for x in opnode['isa']]) + + if is_fext: + if fl>ifl: + is_int_src = any([opcode.endswith(x) for x in ['.x','.w','.l','.wu','.lu']]) + is_nan_box = not is_int_src + + self.xlen = xl + self.flen = fl + self.iflen = ifl + self.base_isa = base_isa_str + self.fmt = fmt + self.opcode = opcode + self.op_vars = OPS[fmt] + self.val_vars = eval(VALS[fmt]) + self.is_fext = is_fext + self.is_nan_box = is_nan_box + + if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","flw","fsw","fld","fsd"]: + self.val_vars = self.val_vars + ['ea_align'] + self.template = opnode['template'] + self.opnode = opnode + # self.stride = opnode['stride'] + if 'operation' in opnode: + self.operation = opnode['operation'] + else: + self.operation = None + datasets = {} + i=10 + for entry in self.op_vars: + key = entry+"_op_data" + if key in opnode: + datasets[entry] = eval(opnode[key]) + else: + datasets[entry] = ['x'+str(i)] + i+=1 + for entry in self.val_vars: + key = entry+"_data" + if key in opnode: + datasets[entry] = eval(opnode[key]) + else: + logger.warning("{0} not defined for {1}. Defaulting to [0].".format(key,self.opcode)) + datasets[entry] = [0] + + self.datasets = datasets + self.random=randomization + self.default_regs = get_default_registers(self.op_vars, self.datasets) + + def opcomb(self, cgf): + ''' + This function finds the solutions for the various operand combinations + defined by the coverpoints in the CGF under the "op_comb" node of the + covergroup. + + Depending on the registers chosen in the datasets, a contraint is created + to ensure that all those registers occur atleast once in the respective + operand/destination location in the instruction. These contraints are + then supplied to the solver for solutions + + If randomization is enabled we use the ``MinConflictsSolver`` solver to + find solutions. + + If harcoded registers are given in the cgf file, then for the conditions other + than the first one, there will be No Solution. To solve that problem, some code + is written which will find the required register in the condition and generate the + solution normally. + + :param cgf: a covergroup in cgf format containing the set of coverpoints to be satisfied. + + :type cgf: dict + + :return: a dictionary of solutions for the various operand combinations specified in the CGF file. + ''' + logger.debug(self.opcode + ' : Generating OpComb') + solutions = [] + op_conds = {} + opcomb_value = cgf.get("op_comb") + if "op_comb" in cgf: + op_comb = set(cgf["op_comb"]) + else: + op_comb = set([]) + for op in self.op_vars: + if op in cgf: + op_conds[op] = set(cgf[op]) + else: + op_conds[op] = set([]) + individual = False + nodiff = False + construct_constraint = lambda val: (lambda x: bool(x in val)) + while any([len(op_conds[x])!=0 for x in op_conds]+[len(op_comb)!=0]): + cond_str = '' + cond_vars = [] + if self.random: + problem = Problem(MinConflictsSolver()) + else: + problem = Problem() + + done = False + for var in self.op_vars: + problem.addVariable(var, list(self.datasets[var])) + if op_conds[var] and not(individual and done): + cond_vars.append(var) + problem.addConstraint(construct_constraint(op_conds[var]),tuple([var])) + done = True + if op_comb: + cond = op_comb.pop() + cond_str += cond+", " + def comb_constraint(*args): + for var,val in zip(self.op_vars,args): + locals()[var] = val + return eval(cond) + problem.addConstraint(comb_constraint,tuple(self.op_vars)) + elif not nodiff: + problem.addConstraint(AllDifferentConstraint()) + count = 0 + solution = problem.getSolution() + while solution is None and count < 5: + if opcomb_value: + for i in opcomb_value: + opcomb_match = re.search(r'x\d{1,2}', i) + if opcomb_match is not None: + pattern = r'(?:rs1|rs2|rd) == "(x\d+)"' + matches = re.findall(pattern, cond) + if not matches or any(int(match[1:]) > 31 for match in matches): + result = None + else: + result = matches + for match in result: + op_conds['rs1'].add(match) + op_conds['rs2'].add(match) + op_conds['rd'].add(match) + op_comb.add(cond) + break + solution = problem.getSolution() + count = count + 1 + + if solution is None: + if individual: + if nodiff: + logger.warn(self.opcode + " : Cannot find solution for Op combination") + break + else: + nodiff = True + else: + individual = True + continue + op_tuple = [] + for key in self.op_vars: + op_tuple.append(solution[key]) + op_conds[key].discard(solution[key]) + + def eval_func(cond): + for var,val in zip(self.op_vars,op_tuple): + locals()[var] = val + return eval(cond) + sat_set = set(filter(eval_func,op_comb)) + cond_str += ", ".join([var+"=="+solution[var] for var in cond_vars]+list(sat_set)) + op_tuple.append(cond_str) + problem.reset() + solutions.append( tuple(op_tuple) ) + + return solutions + + def valcomb(self, cgf): + ''' + This function finds the solutions for the various value combinations + defined by the coverpoints in the CGF under the "val_comb" node of the + covergroup. + + The constraints here are quite simply taken as `eval` strings from the CGF val_comb + nodes itself. + + If randomization is enabled we use the ``MinConflictsSolver`` solver to + find solutions. + + :param cgf: a covergroup in cgf format containing the set of coverpoints to be satisfied. + + :type cgf: dict + + :return: a dictionary of solutions for the various value combinations specified in the CGF file. + ''' + logger.debug(self.opcode + ' : Generating ValComb') + if 'val_comb' not in cgf: + return [] + val_comb = [] + + conds = list(cgf['val_comb'].keys()) + inds = set(range(len(conds))) + merge = True + if 'fcvt' in self.opcode or 'fmv' in self.opcode: + if self.opcode.split(".")[-1] in ['x','w','wu','l','lu']: + merge = "fmv.x.w" in self.opcode + while inds: + req_val_comb = conds[inds.pop()] + if("#nosat" in req_val_comb): + d={} + soln = [] + req_val_comb_minus_comm = req_val_comb.split("#")[0] + x = req_val_comb_minus_comm.split(" and ") + + if self.is_fext: + # fs + fe + fm -> Combiner Script + try: + d = merge_fields_f(self.val_vars,req_val_comb,self.flen,self.iflen,merge) + except ExtractException as e: + logger.warning("Valcomb skip: "+str(e)) + continue + else: + for i in self.val_vars: + for j in x: + if i in j: + if(d.get(i,"None") == "None"): + d[i] = j.split("==")[1] + else: + logger.error("Invalid Coverpoint: More than one value of "+ i +" found!") + sys.exit(1) + if(set(d.keys()) != set(self.val_vars)): + logger.warning( + "Valcomb skip: Cannot bypass SAT Solver for partially defined coverpoints!"\ + + str(req_val_comb)) + continue + for y in self.val_vars: + soln.append(d[y]) + + soln.append(req_val_comb_minus_comm) + val_tuple = soln + else: + if self.random: + problem = Problem(MinConflictsSolver()) + else: + problem = Problem() + + for var in self.val_vars: + if var == 'ea_align' and var not in req_val_comb: + problem.addVariable(var, [0]) + else: + problem.addVariable(var, self.datasets[var]) + + def condition(*argv): + for var,val in zip(self.val_vars,argv): + locals()[var]=val + return eval(req_val_comb) + + problem.addConstraint(condition,tuple(self.val_vars)) + # if boundconstraint: + # problem.addConstraint(boundconstraint,tuple(['rs1_val', 'imm_val'])) + solution = problem.getSolution() + count = 0 + while (solution is None and count < 5): + solution = problem.getSolution() + count+=1 + if solution is None: + logger.warn(self.opcode + " : Cannot find solution for Val condition "+str(req_val_comb)) + continue + val_tuple = [] + for i,key in enumerate(self.val_vars): + val_tuple.append(solution[key]) + + def eval_func(cond): + for var,val in zip(self.val_vars,val_tuple): + locals()[var] = val + return eval(cond) + sat_set=set(filter(lambda x: eval_func(conds[x]),inds)) + inds = inds - sat_set + val_tuple.append(req_val_comb+', '+', '.join([conds[i] for i in sat_set])) + problem.reset() + val_comb.append( tuple(val_tuple) ) + return val_comb + + def __jfmt_instr__(self,op=None,val=None): + cond_str = '' + if op: + cond_str += op[-1]+', ' + if val: + cond_str += val[-1] + instr = {'inst':self.opcode,'index':'0', 'comment':cond_str} + labelize = lambda x: (str((-x)%2**21),'1b') if x < 0 else (str((x%2**21)),'3f') + if op: + for var,reg in zip(self.op_vars,op): + instr[var] = str(reg) + else: + for i,var in enumerate(self.op_vars): + if self.opcode[0] == 'f' and 'fence' not in self.opcode: + if self.opnode[var+'_op_data'][2] == 'f': + instr[var] = 'f'+str(i+10) + else: + instr[var] = 'x'+str(i+10) + else: + instr[var] = 'x'+str(i+10) + if val: + for i,var in enumerate(self.val_vars): + if var == "imm_val": + instr[var],instr['label'] = labelize(val[i]) + else: + instr[var] = str(val[i]) + else: + for var in self.val_vars: + if var == "imm_val": + instr[var],instr['label'] = '0', '3f' + else: + instr[var] = '0' + return instr + + def __bfmt_instr__(self,op=None,val=None): + cond_str = '' + if op: + cond_str += op[-1]+', ' + if val: + cond_str += val[-1] + instr = {'inst':self.opcode,'index':'0', 'comment':cond_str} + + + labelize = lambda x: (str((-x)%2048),'1b') if x < 0 else (str((x%2048)),'3f') + + if op: + for var,reg in zip(self.op_vars,op): + instr[var] = str(reg) + else: + for i,var in enumerate(self.op_vars): + instr[var] = 'x'+str(i+10) + if val: + for i,var in enumerate(self.val_vars): + if var == "imm_val": + instr[var],instr['label'] = labelize(val[i]) + else: + instr[var] = str(val[i]) + else: + for var in self.val_vars: + if var == "imm_val": + instr[var],instr['label'] = '0', '3f' + else: + instr[var] = '0' + return instr + + def __cb_instr__(self,op=None,val=None): + cond_str = '' + if op: + cond_str += op[-1]+', ' + if val: + cond_str += val[-1] + instr = {'inst':self.opcode,'index':'0', 'comment':cond_str} + + + labelize = lambda x: (str((-x)%257),'1b') if x < 0 else (str((x%257)),'3f') + + if op: + for var,reg in zip(self.op_vars,op): + instr[var] = str(reg) + else: + for i,var in enumerate(self.op_vars): + instr[var] = 'x'+str(i+10) + if val: + for i,var in enumerate(self.val_vars): + if var == "imm_val": + instr[var],instr['label'] = labelize(val[i]) + else: + instr[var] = str(val[i]) + else: + for var in self.val_vars: + if var == "imm_val": + instr[var],instr['label'] = '0', '3f' + else: + instr[var] = '0' + return instr + + def __cj_instr__(self,op=None,val=None): + cond_str = '' + if op: + cond_str += op[-1]+', ' + if val: + cond_str += val[-1] + instr = {'inst':self.opcode,'index':'0', 'comment':cond_str} + + + labelize = lambda x: (str((-x)%2048),'1b') if x < 0 else (str((x%2048)),'3f') + + if op: + for var,reg in zip(self.op_vars,op): + instr[var] = str(reg) + else: + for i,var in enumerate(self.op_vars): + instr[var] = 'x'+str(i+10) + if val: + for i,var in enumerate(self.val_vars): + if var == "imm_val": + instr[var],instr['label'] = labelize(val[i]) + else: + instr[var] = str(val[i]) + else: + for var in self.val_vars: + if var == "imm_val": + instr[var],instr['label'] = '0', '3f' + else: + instr[var] = '0' + instr['rs2'] = 'x1' + return instr + + def __clui_instr__(self,op=None,val=None): + cond_str = '' + if op: + cond_str += op[-1]+', ' + if val: + cond_str += val[-1] + instr = {'inst':self.opcode,'index':'0', 'comment':cond_str} + + if op: + for var,reg in zip(self.op_vars,op): + instr[var] = str(reg) + else: + for i,var in enumerate(self.op_vars): + instr[var] = 'x'+str(i+10) + if val: + for i,var in enumerate(self.val_vars): + if var == "imm_val": + instr[var] = str(val[i]) if val[i] < 32 else str(val[i]+1048512) + else: + instr[var] = str(val[i]) + else: + for var in self.val_vars: + if var == "imm_val": + instr[var] = '16' + else: + instr[var] = '0' + return instr + + def __cmemsp_instr__(self, op=None, val=None): + cond_str = '' + if op: + cond_str += op[-1]+', ' + if val: + cond_str += val[-1] + instr = {'inst':self.opcode,'index':'0', 'comment':cond_str} + if op: + for var,reg in zip(self.op_vars,op): + instr[var] = str(reg) + else: + for i,var in enumerate(self.op_vars): + instr[var] = 'x'+str(i+10) + if val: + for i,var in enumerate(self.val_vars): + instr[var] = str(val[i]) + else: + for var in self.val_vars: + instr[var] = str(self.datasets[var][0]) + instr['rs1'] = 'x2' + return instr + + def __instr__(self, op=None, val=None): + cond_str = '' + if op: + cond_str += op[-1]+', ' + if val: + cond_str += val[-1] + instr = {'inst':self.opcode,'index':'0', 'comment':cond_str} + if op: + for var,reg in zip(self.op_vars,op): + instr[var] = str(reg) + else: + for i,var in enumerate(self.op_vars): + instr[var]=self.default_regs[var] + if val: + for i,var in enumerate(self.val_vars): + instr[var] = str(val[i]) + else: + for var in self.val_vars: + instr[var] = str(self.datasets[var][0]) + return instr + + def __fext_instr__(self,op=None,val=None): + rm_dict = { + 0: 'rne', + 1: 'rtz', + 2: 'rdn', + 3: 'rup', + 4: 'rmm', + 7: 'dyn'} + cond_str = '' + if op: + cond_str += op[-1]+',' + if val: + cond_str += val[-1] + instr = {'inst':self.opcode,'comment':cond_str,'index':'0'} + if op: + for var,reg in zip(self.op_vars,op): + instr[var] = str(reg) + else: + for i,var in enumerate(self.op_vars): + instr[var]=self.default_regs[var] + if val: + for i,var in enumerate(self.val_vars): + if var == 'rm_val': + instr[var] = str(rm_dict[val[i]]) + else: + instr[var] = str(val[i]) + else: + for var in self.val_vars: + if var == 'rm_val': + instr[var] = 'dyn' + else: + instr[var] = str(self.datasets[var][0]) + return instr + + def gen_inst(self,op_comb, val_comb, cgf): + ''' + This function combines the op_comb and val_comb solution dictionaries + to create a complete set of arguments of the instruction. + + Depending on the instruction opcode other subfunctions are called to + create the final merged dictionary of op_comb and val_comb. + + Note however, that using the integer register x0 as either source or + destination does not contribute to the coverage. Hence the respective + val_combs are repeated again with non-x0 registers. + + :param op_comb: list containing the operand combination solutions + :param val_comb: list containing the value combination solutions + :param cgf: a covergroup in cgf format containing the set of coverpoints to be satisfied. + + :type cgf: dict + :type op_comb: list + :type val_comb: list + + :return: list of dictionaries containing the various values necessary for the macro. + ''' + instr_dict = [] + cont = [] + if len(op_comb) < len(val_comb): + op_comb = list(op_comb) + [[]] * (len(val_comb) - len(op_comb)) + elif len(val_comb) < len(op_comb): + val_comb = list(val_comb) + [[self.datasets[var][0] for var in self.val_vars] + [""]] * (len(op_comb) - len(val_comb)) + + x = dict([(y,x) for x,y in enumerate(self.val_vars)]) + + ind_dict = {} + for ind,var in enumerate(self.op_vars): + if var+"_val" in x: + ind_dict[ind] = x[var+"_val"] + + for op,val_soln in zip(op_comb,val_comb): + val = [x for x in val_soln] + if any([x=='x0' for x in op]) or not (len(op) == len(set(op))): + cont.append(val_soln) + op_inds = list(ind_dict.keys()) + for i,x in enumerate(op_inds): + if op[x] == 'x0': + val[ind_dict[x]] = 0 + for y in op_inds[i:]: + if op[y] == op[x]: + val[ind_dict[y]] = val[ind_dict[x]] + if self.is_fext: + instr_dict.append(self.__fext_instr__(op,val)) + elif self.opcode == 'c.lui': + instr_dict.append(self.__clui_instr__(op,val)) + elif self.opcode in ['c.beqz', 'c.bnez']: + instr_dict.append(self.__cb_instr__(op,val)) + elif self.opcode in ['c.lwsp', 'c.swsp', 'c.ldsp', 'c.sdsp']: + if any([x == 'x2' for x in op]): + cont.append(val) + instr_dict.append(self.__cmemsp_instr__(op,val)) + elif self.fmt == 'bformat' or self.opcode in ['c.j']: + instr_dict.append(self.__bfmt_instr__(op,val)) + elif self.opcode in ['c.jal', 'c.jalr']: + instr_dict.append(self.__cj_instr__(op,val)) + elif self.fmt == 'jformat' or self.fmt == 'cjformat': + instr_dict.append(self.__jfmt_instr__(op,val)) + else: + instr_dict.append(self.__instr__(op,val)) + op = None + for val in cont: + if self.is_fext: + instr_dict.append(self.__fext_instr__(op,val)) + elif self.opcode == 'c.lui': + instr_dict.append(self.__clui_instr__(op,val)) + elif self.opcode in ['c.beqz', 'c.bnez']: + instr_dict.append(self.__cb_instr__(op,val)) + elif self.opcode in ['c.lwsp', 'c.swsp', 'c.ldsp', 'c.sdsp']: + instr_dict.append(self.__cmemsp_instr__(op,val)) + elif self.fmt == 'bformat' or self.opcode in ['c.j']: + instr_dict.append(self.__bfmt_instr__(op,val)) + elif self.opcode in ['c.jal', 'c.jalr']: + instr_dict.append(self.__cj_instr__(op,val)) + elif self.fmt == 'jformat': + instr_dict.append(self.__jfmt_instr__(op,val)) + else: + instr_dict.append(self.__instr__(op,val)) + + hits = defaultdict(lambda:set([])) + final_instr = [] + + rm_dict = { + 'rne': 0, + 'rtz': 1, + 'rdn': 2, + 'rup': 3, + 'rmm': 4, + 'dyn': 7} + + def eval_inst_coverage(coverpoints,instr): + cover_hits = {} + var_dict = {} + for key in self.val_vars: + if key == 'imm_val': + if self.fmt in ['jformat','bformat'] or instr['inst'] in \ + ['c.beqz','c.bnez','c.jal','c.j','c.jalr']: + var_dict['imm_val'] = \ + (-1 if instr['label'] == '1b' else 1) * toint(instr['imm_val']) + else: + var_dict['imm_val'] = toint(instr['imm_val']) + elif key == 'rm_val': + var_dict['rm_val'] = rm_dict[instr['rm_val']] + else: + var_dict[key] = toint(instr[key]) + for key in self.op_vars: + var_dict[key] = instr[key] + + insn = instr['inst'] + # instructionObject() has an outdated list of instructions. + # Let's make it support all FP instructions until this is fixed. + # See https://github.com/riscv-software-src/riscv-isac/issues/69 + if (is_fp_instruction(insn)): + insn = "fadd.s" + instr_obj = instructionObject(None, insn, None) + ext_specific_vars = instr_obj.evaluate_instr_var("ext_specific_vars", {**var_dict, 'flen': self.flen, 'iflen': self.iflen}, None, {'fcsr': hex(var_dict.get('fcsr', 0))}) + if ext_specific_vars is not None: + var_dict.update(ext_specific_vars) + + if 'val_comb' in coverpoints: + valcomb_hits = set([]) + for coverpoint in coverpoints['val_comb']: + if eval(coverpoint,globals(),var_dict): + valcomb_hits.add(coverpoint) + cover_hits['val_comb']=valcomb_hits + if 'op_comb' in coverpoints: + opcomb_hits = set([]) + for coverpoint in coverpoints['op_comb']: + if eval(coverpoint,globals(),var_dict): + opcomb_hits.add(coverpoint) + cover_hits['op_comb']=opcomb_hits + if 'rs1' in coverpoints: + if var_dict['rs1'] in coverpoints['rs1']: + cover_hits['rs1'] = set([var_dict['rs1']]) + if 'rs2' in coverpoints: + if var_dict['rs2'] in coverpoints['rs2']: + cover_hits['rs2'] = set([var_dict['rs2']]) + if 'rs3' in coverpoints: + if var_dict['rs3'] in coverpoints['rs3']: + cover_hits['rs3'] = set([var_dict['rs3']]) + if 'rd' in coverpoints: + if var_dict['rd'] in coverpoints['rd']: + cover_hits['rd'] = set([var_dict['rd']]) + return cover_hits + i = 0 + + for instr in instr_dict: + unique = False + skip_val = False + if instr['inst'] in cgf['mnemonics']: + if 'rs1' in instr and 'rs2' in instr: + if instr['rs1'] == instr['rs2']: + skip_val = True + if 'rs1' in instr: + if instr['rs1'] == 'x0' or instr['rs1'] == 'f0': + skip_val = True + if 'rs2' in instr: + if instr['rs2'] == 'x0' or instr['rs2'] == 'f0': + skip_val = True + if 'rd' in instr: + if instr['rd'] == 'x0' or instr['rd'] == 'f0': + skip_val = True + cover_hits = eval_inst_coverage(cgf,instr) + for entry in cover_hits: + if entry=='val_comb' and skip_val: + continue + over = hits[entry] & cover_hits[entry] + if over != cover_hits[entry]: + unique = unique or True + hits[entry] |= cover_hits[entry] + if unique: + final_instr.append(instr) + else: + i+=1 + + if any('IP' in isa for isa in self.opnode['isa']): + if 'p64_profile' in self.opnode: + gen_pair_reg_data(final_instr, self.xlen, self.opnode['bit_width'], self.opnode['p64_profile']) + elif 'bit_width' in self.opnode: + concat_simd_data(final_instr, self.xlen, self.opnode['bit_width']) + + ''' + Zacas introduces double xlen cas operations that need paired source and destination registers + ''' + if any('Zacas' in isa for isa in self.opnode['isa']): + if 'dcas_profile' in self.opnode: + gen_pair_reg_data(final_instr, self.xlen, self.opnode['bit_width'], self.opnode['dcas_profile']) + + + return final_instr + + def valreg(self,instr_dict): + ''' + This function is responsible for identifying which register can be used to store addresses + to load values from memory. + + This register is calculated by traversing the dictionary of solutions + created so far and removing all the registers which are used as either + operands or destination. When 3 or less registers are pending, one of + those registers is used as signature pointer for all the solutions + traversed so far. + + Along with the register the offset is also assigned in this function. + The offset is incremented by the amount specified in the template node bytes always. + + Care is taken to never use 'x0' as signature pointer. + :param instr_dict: list of dictionaries containing the various values necessary for the macro + :type instr_dict: list + :return: list of dictionaries containing the various values necessary for the macro + ''' + # TODO: Move flagreg allocation to separate function. Preferable to club all anxilliary + # register allocations to a generalised function and club both swreg and valreg to it too. + if 'val' in self.opnode: + paired_regs=0 + if self.xlen == 32 and 'p64_profile' in self.opnode: + p64_profile = self.opnode['p64_profile'] + paired_regs = self.opnode['p64_profile'].count('p') + if 'dcas_profile' in self.opnode: + dcas_profile = self.opnode['dcas_profile'] + paired_regs = self.opnode['dcas_profile'].count('p') + + regset = e_regset if 'e' in self.base_isa else default_regset + total_instr = len(instr_dict) + available_reg = regset.copy() + available_reg.remove('x0') + count = 0 + assigned = 0 + offset = 0 + stride = self.opnode['val']['stride'] + num_vars = len(self.op_vars)-1 if 'rd' in self.op_vars else len(self.op_vars) + suffix = self.opnode['val']['sz'] + if flen in self.opnode: + FLEN = max(self.opnode['flen']) + else: + FLEN = 0 + XLEN = max(self.opnode['xlen']) + SIGALIGN = max(XLEN,FLEN)/8 + stride_sz = eval(suffix) + template = Template(eval(self.opnode['val']['val_template'])) + width = self.iflen if self.is_fext else self.xlen + for instr in instr_dict: + if 'rs1' in instr and instr['rs1'] in available_reg: + available_reg.remove(instr['rs1']) + if 'rs2' in instr and instr['rs2'] in available_reg: + available_reg.remove(instr['rs2']) + if 'rd' in instr and instr['rd'] in available_reg: + available_reg.remove(instr['rd']) + if 'rs1_hi' in instr and instr['rs1_hi'] in available_reg: + available_reg.remove(instr['rs1_hi']) + if 'rs2_hi' in instr and instr['rs2_hi'] in available_reg: + available_reg.remove(instr['rs2_hi']) + if 'rd_hi' in instr and instr['rd_hi'] in available_reg: + available_reg.remove(instr['rd_hi']) + if 'swreg' in instr and instr['swreg'] in available_reg: + available_reg.remove(instr['swreg']) + if 'testreg' in instr and instr['testreg'] in available_reg: + available_reg.remove(instr['testreg']) + if len(available_reg) <= 3+len(self.op_vars)+paired_regs: + curr_reg = available_reg[0] + offset = 0 + for i in range(assigned, count+1): + if 'valaddr_reg' not in instr_dict[i]: + instr_dict[i]['valaddr_reg'] = curr_reg + instr_dict[i]['val_offset'] = str(offset) + '*' + suffix + offset += stride + if offset*stride_sz > 2047: + offset = 0 + assigned += 1 + instr_dict[i]['val_section'] = [] + for j in range(1,num_vars+1): + dval = () + if self.is_nan_box: + dval = nan_box(instr_dict[i]['rs{0}_nan_prefix'.format(j)], + instr_dict[i]['rs{0}_val'.format(j)],self.flen,self.iflen) + else: + dval = (instr_dict[i]['rs{0}_val'.format(j)],width) + if self.is_fext: + instr_dict[i]['flagreg'] = available_reg[1] + instr_dict[i]['val_section'].append( + template.substitute(val=dval[0],width=dval[1])) + instr_dict[i]['load_instr'] = self.opnode['val']['load_instr'] + available_reg = regset.copy() + available_reg.remove('x0') + count += 1 + if assigned != total_instr and len(available_reg) != 0: + curr_reg = available_reg[0] + offset = 0 + for i in range(len(instr_dict)): + if 'valaddr_reg' not in instr_dict[i]: + instr_dict[i]['valaddr_reg'] = curr_reg + instr_dict[i]['val_offset'] = str(offset) + '*' + suffix + offset += stride + if offset*stride_sz > 2047: + offset = 0 + assigned += 1 + instr_dict[i]['val_section'] = [] + for j in range(1,num_vars+1): + dval = () + if self.is_nan_box: + dval = nan_box(instr_dict[i]['rs{0}_nan_prefix'.format(j)], + instr_dict[i]['rs{0}_val'.format(j)],self.flen,self.iflen) + else: + dval = (instr_dict[i]['rs{0}_val'.format(j)],width) + if self.is_fext: + instr_dict[i]['flagreg'] = available_reg[1] + instr_dict[i]['val_section'].append( + template.substitute(val=dval[0],width=dval[1])) + instr_dict[i]['load_instr'] = self.opnode['val']['load_instr'] + return instr_dict + else: + return instr_dict + + + + def swreg(self, instr_dict): + ''' + This function is responsible for identifying which register can be used + as a signature pointer for each instruction. + + This register is calculated by traversing the dictionary of solutions + created so far and removing all the registers which are used as either + operands or destination. When 3 or less registers are pending, one of + those registers is used as signature pointer for all the solutions + traversed so far. + + Along with the register the offset is also assigned in this function. + The offset is incremented by the amount specified in the template node bytes always. + + Care is taken to never use 'x0' as signature pointer. + :param instr_dict: list of dictionaries containing the various values necessary for the macro + :type instr_dict: list + :return: list of dictionaries containing the various values necessary for the macro + ''' + # TODO: Clean this up and merge it with the code below to generalise adding val bases to + # generic macro templates. + + paired_regs=0 + if self.xlen == 32 and 'p64_profile' in self.opnode: + p64_profile = self.opnode['p64_profile'] + paired_regs = self.opnode['p64_profile'].count('p') + if 'dcas_profile' in self.opnode: + dcas_profile = self.opnode['dcas_profile'] + paired_regs = self.opnode['dcas_profile'].count('p') + + regset = e_regset if 'e' in self.base_isa else default_regset + total_instr = len(instr_dict) + available_reg = regset.copy() + available_reg.remove('x0') + count = 0 + assigned = 0 + offset = 0 + stride = self.opnode['sig']['stride'] + suffix = self.opnode['sig']['sz'] + if flen in self.opnode: + FLEN = max(self.opnode['flen']) + else: + FLEN = 0 + XLEN = max(self.opnode['xlen']) + SIGALIGN = max(XLEN,FLEN)/8 + stride_sz = eval(suffix) + for instr in instr_dict: + if 'rs1' in instr and instr['rs1'] in available_reg: + available_reg.remove(instr['rs1']) + if 'rs2' in instr and instr['rs2'] in available_reg: + available_reg.remove(instr['rs2']) + if 'rd' in instr and instr['rd'] in available_reg: + available_reg.remove(instr['rd']) + if 'rs1_hi' in instr and instr['rs1_hi'] in available_reg: + available_reg.remove(instr['rs1_hi']) + if 'rs2_hi' in instr and instr['rs2_hi'] in available_reg: + available_reg.remove(instr['rs2_hi']) + if 'rd_hi' in instr and instr['rd_hi'] in available_reg: + available_reg.remove(instr['rd_hi']) + if 'testreg' in instr and instr['testreg'] in available_reg: + available_reg.remove(instr['testreg']) + + if len(available_reg) <= 2+len(self.op_vars)+paired_regs: + curr_swreg = available_reg[0] + offset = 0 + for i in range(assigned, count+1): + if 'swreg' not in instr_dict[i]: + instr_dict[i]['offset'] = str(offset) + '*' + suffix + offset += stride + if offset*stride_sz > 2047: + offset = 0 + instr_dict[i]['swreg'] = curr_swreg + assigned += 1 + available_reg = regset.copy() + available_reg.remove('x0') + count += 1 + if assigned != total_instr and len(available_reg) != 0: + curr_swreg = available_reg[0] + offset = 0 + for i in range(len(instr_dict)): + if 'swreg' not in instr_dict[i]: + instr_dict[i]['offset'] = str(offset) + '*' + suffix + offset += stride + if offset*stride_sz > 2047: + offset = 0 + instr_dict[i]['swreg'] = curr_swreg + return instr_dict + + def testreg(self, instr_dict): + ''' + This function is responsible for identifying which register can be used + as a test register for each instruction. + + This register is calculated by traversing the dictionary of solutions + created so far and removing all the registers which are used as either + operands or destination or signature. When 3 or less registers are pending, one of + those registers is used as test register for all the solutions + traversed so far. + + Care is taken to never use 'x0' as test register. + :param instr_dict: list of dictionaries containing the various values necessary for the macro + :type instr_dict: list + :return: list of dictionaries containing the various values necessary for the macro + ''' + regset = e_regset if 'e' in self.base_isa else default_regset + total_instr = len(instr_dict) + available_reg = regset.copy() + available_reg.remove('x0') + count = 0 + assigned = 0 + + paired_regs=0 + if self.xlen == 32 and 'p64_profile' in self.opnode: + p64_profile = self.opnode['p64_profile'] + paired_regs = p64_profile.count('p') + if 'dcas_profile' in self.opnode: + dcas_profile = self.opnode['dcas_profile'] + paired_regs = dcas_profile.count('p') + + for instr in instr_dict: + if 'rs1' in instr and instr['rs1'] in available_reg: + available_reg.remove(instr['rs1']) + if 'rs1_hi' in instr and instr['rs1_hi'] in available_reg: + available_reg.remove(instr['rs1_hi']) + if 'rs2' in instr and instr['rs2'] in available_reg: + available_reg.remove(instr['rs2']) + if 'rs2_hi' in instr and instr['rs2_hi'] in available_reg: + available_reg.remove(instr['rs2_hi']) + if 'rd' in instr and instr['rd'] in available_reg: + available_reg.remove(instr['rd']) + if 'rd_hi' in instr and instr['rd_hi'] in available_reg: + available_reg.remove(instr['rd_hi']) + if 'swreg' in instr and instr['swreg'] in available_reg: + available_reg.remove(instr['swreg']) + + if len(available_reg) <= 2+len(self.op_vars)+paired_regs: + curr_testreg = available_reg[0] + for i in range(assigned, count+1): + if 'testreg' not in instr_dict[i]: + instr_dict[i]['testreg'] = curr_testreg + assigned += 1 + available_reg = regset.copy() + available_reg.remove('x0') + count += 1 + if assigned != total_instr and len(available_reg) != 0: + curr_testreg = available_reg[0] + for i in range(len(instr_dict)): + if 'testreg' not in instr_dict[i]: + instr_dict[i]['testreg'] = curr_testreg + return instr_dict + + def correct_val(self,instr_dict): + ''' + this function is responsible for assigning the correct-vals for all instructions. + The correctvals are calculated based on the `operation` field of the node + in the attributes YAML. If the operation field is empty, then a value of + 0 is assigned to the correctval. + :param instr_dict: list of dictionaries containing the various values necessary for the macro + :type instr_dict: list + :return: list of dictionaries containing the various values necessary for the macro + ''' + if self.opcode[0] == 'f' and 'fence' not in self.opcode: + for i in range(len(instr_dict)): + instr_dict[i]['correctval'] = '0' + return instr_dict + if self.xlen == 32 and 'p64_profile' in self.opnode: + p64_profile = self.opnode['p64_profile'] + if len(p64_profile) >= 3 and p64_profile[0]=='p': + for i in range(len(instr_dict)): + instr_dict[i]['correctval_hi'] = '0' + if 'dcas_profile' in self.opnode: + dcas_profile = self.opnode['dcas_profile'] + if len(dcas_profile) >= 3 and dcas_profile[0]=='p': + for i in range(len(instr_dict)): + instr_dict[i]['correctval_hi'] = '0' + if self.fmt in ['caformat','crformat']: + normalise = lambda x,y: 0 if y['rs1']=='x0' else x + else: + normalise = (lambda x,y: x) if 'rd' not in self.op_vars else (lambda x,y: 0 if y['rd']=='x0' else x) + if self.operation: + for i in range(len(instr_dict)): + for var in self.val_vars: + locals()[var]=toint(instr_dict[i][var]) + correctval = eval(self.operation) + instr_dict[i]['correctval'] = str(normalise(correctval,instr_dict[i])) + else: + for i in range(len(instr_dict)): + instr_dict[i]['correctval'] = '0x' + '0'.zfill(int(self.xlen/4)) + return instr_dict + + def reformat_instr(self, instr_dict): + ''' + This function basically sanitizes the integer values to a readable + hex values + :param instr_dict: list of dictionaries containing the various values necessary for the macro + :type instr_dict: list + :return: list of dictionaries containing the various values necessary for the macro + ''' + if any('IP' in isa for isa in self.opnode['isa']): + # instr_dict is already in the desired format for instructions that perform SIMD operations, or Zpsfoperand instructions in RV32. + if 'bit_width' in self.opnode or (self.xlen == 32 and 'p64_profile' in self.opnode): + return instr_dict + if any('Zacas' in isa for isa in self.opnode['isa']): + # instr_dict is already in the desired format for Zacas dcas instructions + if 'bit_width' in self.opnode or 'dcas_profile' in self.opnode: + return instr_dict + + # Fix all K instructions to be unsigned to output unsigned hex values into the test. Its + # only a cosmetic difference and has no impact on coverage + is_unsigned = any('IZk' in isa for isa in self.opnode['isa']) + + for i in range(len(instr_dict)): + for field in instr_dict[i]: + if xlen == 32: + if instr_dict[i]['inst'] in ['sltu', 'sltiu', 'bgeu', 'bltu'] or is_unsigned: + size = '>I' + else: + size = '>i' + else: + if instr_dict[i]['inst'] in ['sltu', 'sltiu', 'bgeu', 'bltu'] or is_unsigned: + size = '>Q' + else: + size = '>q' + if 'val' in field and field != 'correctval' and field != 'valaddr_reg' and \ + field != 'val_section' and field != 'val_offset' and field != 'rm_val': + value = (instr_dict[i][field]).strip() + #print(value) + if '0x' in value: + value = '0x' + value[2:].zfill(int(self.xlen/4)) + value = struct.unpack(size, bytes.fromhex(value[2:]))[0] + else: + value = int(value) +# value = '0x' + struct.pack(size,value).hex() + #print("test",hex(value)) + instr_dict[i][field] = hex(value) + return instr_dict + + def write_test(self, fprefix, node, label, instr_dict, op_node, usage_str,max_inst): + start = 0 + total = len(instr_dict) + end = len(instr_dict) + if max_inst: + end = max_inst + else: + max_inst = total + i = 1 + while end <= total and start=max_inst: + end += max_inst + else: + end = total + + + def __write_test__(self, file_name,node,label,instr_dict, op_node, usage_str): + ''' + This function generates the test using various templates. + + :param file_name: path of the output file + :param node: a covergroup in cgf format containing the set of coverpoints to be satisfied + :param label: the label for the covergroup in the input cgf file + :param instr_dict: list of dictionaries containing the various values necessary for the macro + :param op_node: dictionary node from the attributes YAML that is to be used in the test generation + :param usage_str: Banner string for the test + + :type file_name: str + :type node: dict + :type label: str + :type instr_dict: list + :type op_node: dict + :type usage_str: str + ''' + regs = defaultdict(lambda: 0) + sreg = instr_dict[0]['swreg'] + vreg = None + code = [] + sign = [""] + data = [".align 4","rvtest_data:",".word 0xbabecafe", \ + ".word 0xabecafeb", ".word 0xbecafeba", ".word 0xecafebab"] + stride = self.opnode['sig']['stride'] + if self.is_fext: + code.append("RVTEST_FP_ENABLE()") + + if any('IP' in isa for isa in self.opnode['isa']): + code.append("RVTEST_VXSAT_ENABLE()") + if self.xlen == 32 and 'p64_profile' in self.opnode: + p64_profile = self.opnode['p64_profile'] + if 'dcas_profile' in self.opnode: + dcas_profile = self.opnode['dcas_profile'] + + n = 0 + is_int_src = any([self.opcode.endswith(x) for x in ['.x','.w','.l','.wu','.lu']]) + src_len = xlen if self.opcode.endswith('.x') else (32 if 'w' in self.opcode else 64) + sz = 'word' if src_len == 32 else 'dword' + opcode = instr_dict[0]['inst'] + op_node_isa = "" + extension = "" + xlens = [self.xlen] + \ + (list(filter(lambda x: x>self.xlen,self.opnode['xlen'])) if self.is_fext else []) + for val in xlens: + rvxlen = "RV"+str(val) + op_node_isa += (("," if op_node_isa else "") \ + + ",".join([rvxlen + isa for isa in op_node['isa']])) + op_node_isa = op_node_isa.replace("I","E") if 'e' in self.base_isa else op_node_isa + extension = op_node_isa.replace('I',"").replace('E',"") + count = 0 + neg_offset = 0 + width = self.iflen if not self.is_nan_box else self.flen + dset_n = 0 + sig_sz = '(({0})/4)'.format(self.opnode['sig']['sz']) + cond_prefix = '' if self.is_fext else 'check ISA:=regex(.*{0}.*);'.format(self.xlen) + for instr in instr_dict: + switch = False + res = '\ninst_{0}:'.format(str(count)) + res += Template(op_node['template']).safe_substitute(instr) + if 'val' in self.opnode: + if eval(instr['val_offset'],{}, + {'FLEN':width,'XLEN':self.xlen,'SIGALIGN':max(self.xlen,self.flen)/8} + ) == 0 or instr['valaddr_reg'] != vreg: + dlabel = 'test_dataset_'+str(dset_n) + dset_n += 1 + data.append(dlabel+":") + vreg = instr['valaddr_reg'] + code.append("RVTEST_VALBASEUPD("+vreg+","+dlabel+")") + # for i in range(1,num_vars+1): + # dval = () + # if self.is_nan_box: + # dval = nan_box(instr['rs{0}_nan_prefix'.format(i)], + # instr['rs{0}_val'.format(i)],self.flen,self.iflen) + # else: + # dval = (instr['rs{0}_val'.format(i)],self.iflen) + data.extend(instr['val_section']) + if instr['swreg'] != sreg or eval(instr['offset'],{}, + {'FLEN':width,'XLEN':self.xlen,'SIGALIGN':max(self.xlen,self.flen)/8}) == 0: + sign.append(signode_template.substitute( + {'n':n,'label':"signature_"+sreg+"_"+str(regs[sreg]),'sz':sig_sz})) + n = stride + regs[sreg]+=1 + sreg = instr['swreg'] + code.append("RVTEST_SIGBASE("+sreg+",signature_"+sreg+"_"+str(regs[sreg])+")") + else: + n+=stride + code.append(res) + count = count + 1 + case_str = ''.join([case_template.safe_substitute(xlen=self.xlen,num=i,cond=cond,cov_label=label) for i,cond in enumerate(node['config'])]) + sign.append(signode_template.substitute({'n':n, + 'label':"signature_"+sreg+"_"+str(regs[sreg]),'sz':sig_sz})) + test = part_template.safe_substitute(case_str=case_str,code='\n'.join(code)) + sign.append("#ifdef rvtest_mtrap_routine\ntsig_begin_canary:\nCANARY;\n"+signode_template.substitute( + {'n':64,'label':"mtrap_sigptr",'sz':'XLEN/32'})+"\ntsig_end_canary:\nCANARY;\n#endif\n") + sign.append("#ifdef rvtest_gpr_save\n"+signode_template.substitute( + {'n':32,'label':"gpr_save",'sz':'XLEN/32'})+"\n#endif\n") + with open(file_name,"w") as fd: + fd.write(usage_str + test_template.safe_substitute(data='\n'.join(data),test=test,sig='\n'.join(sign),isa=op_node_isa,opcode=opcode,extension=extension,label=label)) \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/helpers.py b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/helpers.py new file mode 100644 index 000000000..c9c8a9efc --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/helpers.py @@ -0,0 +1,79 @@ +import re + +class ExtractException(Exception): + pass + +num_dict = { + 'rs1_val': '1', + 'rs2_val': '2', + 'rs3_val': '3', +} +fsub_vars = ['fe','fm','fs'] + +val_regex = "{0}\s*==\s*(?P<{1}>[0-9abcdefx+\-\*/\|\&]*)\s*" + +def to_int(x): + if '0x' in x: + return int(x,16) + else: + return int(x) + +def nan_box(prefix,rs,flen,iflen): + if int(prefix) == ((2**(flen-iflen))-1): + return (rs,iflen) + else: + return (str(to_int(rs)|(to_int(prefix)< iflen: + nan_box = True + fdict = {} + for var in val_vars: + if var in num_dict and merge: + fdict[var] = extract_frs_fields(num_dict[var],cvp,iflen) + if nan_box: + nan_var = 'rs{0}_nan_prefix'.format(num_dict[var]) + regex = val_regex.format(nan_var.replace("_","\\_"),nan_var) + match_obj = re.search(regex,cvp) + if match_obj is not None: + fdict[nan_var] = eval(match_obj.group(nan_var)) + else: + fdict[nan_var] = (2**(flen-iflen))-1 + else: + regex = val_regex.format(var.replace("_","\\_"),var) + match_obj = re.search(regex,cvp) + if match_obj is not None: + fdict[var] = eval(match_obj.group(var)) + elif 'nan_prefix' not in var: + raise ExtractException("{0} not defined in coverpoint:{1}".format(var,cvp)) + return fdict + + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/log.py b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/log.py new file mode 100644 index 000000000..f4d2312b5 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/log.py @@ -0,0 +1,92 @@ +# See LICENSE.incore for details + +import logging +import colorlog + +class Log: + """ + this class holds all the logic; see the end of the script to + see how it's instantiated in order to have the line + "from zenlog import log" work + """ + + aliases = { + logging.CRITICAL: ("critical", "crit", "fatal"), + logging.ERROR: ("error", "err"), + logging.WARNING: ("warning", "warn"), + logging.INFO: ("info", "inf"), + logging.DEBUG: ("debug", "dbg") + } + + def __init__(self, format=None): + if not format: + format = "%(log_color)s%(levelname)8s%(reset)s | %(log_color)s%(message)s%(reset)s" + self.format = format + self.colors = { + 'DEBUG': 'purple', + 'INFO': 'green', + 'WARNING': 'red', + 'ERROR': 'bold_red', + 'CRITICAL': 'bold_red', + } + self.logger = logging.getLogger() + + + # the magic happens here: we use the "extra" argument documented in + # https://docs.python.org/2/library/logging.html#logging.Logger.debug + # to inject new items into the logging.LogRecord objects + # we also create our convenience methods here + def critical(self, message, *args, **kwargs): + for line in str(message).splitlines(): + self.logger.critical(line, + *args, **kwargs) + crit = c = fatal = critical + + def error(self, message, *args, **kwargs): + for line in str(message).splitlines(): + self.logger.error(line, + *args, **kwargs) + err = e = error + + def warn(self, message, *args, **kwargs): + for line in str(message).splitlines(): + self.logger.warning(line, + *args, **kwargs) + warning = w = warn + + def info(self, message, *args, **kwargs): + for line in str(message).splitlines(): + self.logger.info(line, + *args, **kwargs) + inf = nfo = i = info + + def debug(self, message, *args, **kwargs): + for line in str(message).splitlines(): + self.logger.debug(line, + *args, **kwargs) + dbg = d = debug + + # other convenience functions to set the global logging level + def _parse_level(self, lvl): + for log_level in self.aliases: + if lvl == log_level or lvl in self.aliases[log_level]: + return log_level + print('Invalid log level passed. Please select from debug | info | warning | error') + raise ValueError("{}-Invalid log level.".format(lvl)) + + def level(self, lvl=logging.CRITICAL): + '''Setup the Logger.''' + + self._lvl = self._parse_level(lvl) + + self.stream = logging.StreamHandler() + self.stream.setLevel(self._lvl) + + self.stream.setLevel(self._lvl) + + self.stream.setFormatter(colorlog.ColoredFormatter(self.format,log_colors=self.colors)) + self.logger.setLevel(self._lvl) + + self.logger.addHandler(self.stream) + logging.root.setLevel(self._lvl) +logger = Log() diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/main.py b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/main.py new file mode 100644 index 000000000..e23b80263 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/main.py @@ -0,0 +1,29 @@ +# See LICENSE.incore for details +"""Console script for riscv_ctg.""" + +import click,os + +from riscv_ctg.log import logger +from riscv_ctg.ctg import ctg +from riscv_ctg.__init__ import __version__ +from riscv_ctg.constants import env,gen_sign_dataset,gen_usign_dataset +from riscv_isac.cgf_normalize import expand_cgf +@click.command() +@click.version_option(prog_name="RISC-V Compliance Test Generator",version=__version__) +@click.option('--verbose', '-v', default='error', help='Set verbose level', type=click.Choice(['info','error','debug','warning'],case_sensitive=False)) +@click.option('--out-dir', '-d', default='./', type=click.Path(resolve_path=True,writable=True), help='Output directory path') +@click.option('--randomize','-r', default=False , is_flag='True', help='Randomize Outputs.') +@click.option('--cgf','-cf',multiple=True,type=click.Path(exists=True,resolve_path=True,readable=True),help="Path to the cgf file(s). Multiple allowed.") +@click.option('--procs','-p',type=int,default=1,help='Max number of processes to spawn') +@click.option('--base-isa','-bi',type=click.Choice(['rv32e','rv32i','rv64i']),help="Base ISA string for the tests.") +@click.option('--flen','-fl',type=click.Choice(['32','64','128','0']),help="Value of FLEN in\ + hardware.",default='0') +@click.option("--inst",type=int,help="Maximum number of Macro Instances per test.") +def cli(verbose, out_dir, randomize , cgf,procs,base_isa, flen,inst): + if not os.path.exists(out_dir): + os.mkdir(out_dir) + if '32' in base_isa: + xlen = 32 + elif '64' in base_isa: + xlen = 64 + ctg(verbose, out_dir, randomize ,xlen, int(flen), cgf,procs,base_isa,inst) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/misc/bitmanip_real_world.py b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/misc/bitmanip_real_world.py new file mode 100644 index 000000000..5109f2395 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/misc/bitmanip_real_world.py @@ -0,0 +1,442 @@ +import random +import os + +#---------------------------------------------------Start String-------------------------------------------------- + +start_str = ''' +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV$xlenIK") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*$xlen.*);check ISA:=regex(.*RV$xlen.*I.*K.*);def TEST_CASE_1=True;",$inst) + +RVTEST_CASE(1,"//check ISA:=regex(.*$xlen.*);check ISA:=regex(.*RV$xlen.*I.*$config.*);def TEST_CASE_1=True;",$inst) + +RVTEST_SIGBASE( $swreg1,signature_$swreg1_1)''' + +#---------------------------------------------Assembly String: aes64*---------------------------------------------- + +string1 = '''// $comment +// opcode: $inst; op1:$rs1; op2:$rs2; dest1:$rd1; dest2:$rd2; dest3:$rd3; op1val:$r1_val; op2val:$r2_val +li $rs1, $r1_val; +li $rs2, $r2_val; +xor $rs1, $rs1, $rs2; +$inst $rd1, $rs1, $rs2; +$inst $rd2, $rs2, $rs1; +xor $rd3, $rd2, $rs2; +RVTEST_SIGUPD($swreg1,$rd1,$offset1); +RVTEST_SIGUPD($swreg1,$rd2,$offset2); +RVTEST_SIGUPD($swreg1,$rd3,$offset3);''' + +#---------------------------------Assembly String: SHA2, SM3 & aes64im - Pattern 1--------------------------------- + +string2 = '''// $comment +// opcode: $inst2; op1:$rs3; dest1:$rs1; op1val:$r1_val; op2val:$r2_val +li $rs1, $r1_val; +li $rs2, $r2_val; +$inst1 $rs3, $rs1, $rs2; +$inst2 $rs1, $rs3; +$inst1 $rs4, $rs1, $rs2; +RVTEST_SIGUPD($swreg1,$rs3,$offset1); +RVTEST_SIGUPD($swreg1,$rs1,$offset2); +RVTEST_SIGUPD($swreg1,$rs4,$offset3);''' + +string2_not = '''// $comment +// opcode: $inst2; op1:$rs3; dest1:$rs1; op1val:$r1_val; op2val:$r2_val +li $rs1, $r1_val; +li $rs2, $r2_val; +$inst1 $rs3, $rs2; +$inst2 $rs1, $rs3; +$inst1 $rs4, $rs1; +RVTEST_SIGUPD($swreg1,$rs3,$offset1); +RVTEST_SIGUPD($swreg1,$rs1,$offset2); +RVTEST_SIGUPD($swreg1,$rs4,$offset3);''' + +#---------------------------------Assembly String: SHA2, SM3 & aes64im - Pattern 2--------------------------------- + +string3 = '''// $comment +// opcode: $inst; op1:$rs1; dest1:$rs2; +LREG $rs1, $offset1($rs0); +$inst $rs2, $rs1; +RVTEST_SIGUPD($swreg1,$rs1,$offset2); +RVTEST_SIGUPD($swreg1,$rs2,$offset3);''' + +#---------------------------------------Assembly String: SHA2-512 - Pattern 1-------------------------------------- + +string5 = '''// $comment +// opcode: $inst2; op1:$rs3; op2:$rs2; dest1:$rs1; op1val:$r1_val; op2val:$r2_val +li $rs1, $r1_val; +li $rs2, $r2_val; +$inst1 $rs3, $rs1, $rs2; +$inst2 $rs1, $rs3, $rs2; +$inst1 $rs4, $rs1, $rs2; +RVTEST_SIGUPD($swreg1,$rs3,$offset1); +RVTEST_SIGUPD($swreg1,$rs1,$offset2); +RVTEST_SIGUPD($swreg1,$rs4,$offset3);''' + +string5_not = '''// $comment +// opcode: $inst2; op1:$rs3; op2:$rs2; dest1:$rs1; op1val:$r1_val; op2val:$r2_val +li $rs1, $r1_val; +li $rs2, $r2_val; +$inst1 $rs3, $rs2; +$inst2 $rs1, $rs3, $rs2; +$inst1 $rs4, $rs1; +RVTEST_SIGUPD($swreg1,$rs3,$offset1); +RVTEST_SIGUPD($swreg1,$rs1,$offset2); +RVTEST_SIGUPD($swreg1,$rs4,$offset3);''' + +#---------------------------------------Assembly String: SHA2-512 - Pattern 2-------------------------------------- + +string6 = '''// $comment +// opcode: $inst; op1:$rs1; op2:$rs2; dest1:$rs3; +LREG $rs1, $offset1($rs0); +LREG $rs2, $offset2($rs0); +$inst $rs3, $rs1, $rs2; +RVTEST_SIGUPD($swreg1,$rs1,$offset3); +RVTEST_SIGUPD($swreg1,$rs3,$offset4);''' + +#----------------------------------------------Assembly String: aes32*--------------------------------------------- + +string4 = '''// $comment +// opcode: $inst; op1:$rs1; op1:$rs2; op1:$rs3; op1:$rs4; dest:$rs5; +li $rs1, $r1_val; +li $rs2, $r2_val; +li $rs3, $r3_val; +li $rs4, $r4_val; +li $rs5, $r5_val; +$inst $rs5, $rs1, 0; +$inst $rs5, $rs2, 1; +$inst $rs5, $rs3, 2; +$inst $rs5, $rs4, 3; +RVTEST_SIGUPD($swreg1,$rs5,$offset1);''' + +#----------------------------------------------Assembly String: sm4ed, sm4ks --------------------------------------------- + +string7 = '''// $comment +// opcode: $inst; $op1: $rs6; op2:$rs1; op2:$rs2; op2:$rs3; op2:$rs4; dest:$rs5; +li $rs1, $r1_val; +li $rs2, $r2_val; +li $rs3, $r3_val; +li $rs4, $r4_val; +li $rs5, $r5_val; +li $rs6, $r6_val; +$inst $rs5, $rs6, $rs1, 0; +$inst $rs5, $rs6, $rs2, 1; +$inst $rs5, $rs6, $rs3, 2; +$inst $rs5, $rs6, $rs4, 3; +RVTEST_SIGUPD($swreg1,$rs5,$offset1);''' + +#----------------------------------------------------End String---------------------------------------------------- + +end_str = '''#endif + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN + + +signature_$swreg1_1: + .fill $fill_val*(XLEN/32),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine + +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef + +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef + +#endif + +RVMODEL_DATA_END''' + +#-------------------------------------------------End String 1 & 2------------------------------------------------ + +end_str1 = '''#endif + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data:''' + +end_str2 = '''RVTEST_DATA_END + +RVMODEL_DATA_BEGIN + + +signature_$swreg1_1: + .fill $fill_val*(XLEN/32),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine + +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef + +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef + +#endif + +RVMODEL_DATA_END''' + +#----------------------------------------------------User Inputs--------------------------------------------------- + +instr_dict = { + 1: ["aes64ds","aes64dsm","aes64es","aes64esm","sm4ed","sm4ks"], + 2: ["sha256sig0","sha256sig1","sha256sum0","sha256sum1","sha512sig0",\ + "sha512sig1","sha512sum0","sha512sum1","sm3p0","sm3p1","aes64im"], + 3: ["aes32dsi","aes32dsmi","aes32esi","aes32esmi"], + 4: ["sha256sig0","sha256sig1","sha256sum0","sha256sum1","sm3p0","sm3p1"], + 5: ["sha512sig0h","sha512sig0l","sha512sig1h","sha512sig1l","sha512sum0r","sha512sum1r"], + 6: ["sm4ed","sm4ks"], + 7: ["sm4ed","sm4ks"]} + +instr_f = { + 1: ["xor"], + 2: ["xor","not","add"], + 3: ["none"], + 4: ["xor","not","add"], + 5: ["xor","not","add"], + 6: ["none"], + 7: ["none"] + } + +xlen = { + 1: 64, + 2: 64, + 3: 32, + 4: 32, + 5: 32, + 6: 64, + 7: 32} + +comment_dict = { + 1: ["1st Instruction => rs1 = $rs1; rs2 = $rs2 | 2nd Instruction => rs1 = $rs2; rs2 = $rs1\ + | Result of xor goes into $inst & vice versa"], + 2: ["Forwarded $inst1 into $inst2 & the result back into $inst1","Checking load-to-use hazard!"], + 3: ["Expected use-case sequence -> Aims to test things like pipeline forwarding"], + 4: ["Forwarded $inst1 into $inst2 & the result back into $inst1","Checking load-to-use hazard!"], + 5: ["Forwarded $inst1 into $inst2 & the result back into $inst1","Checking load-to-use hazard!"], + 6: ["Expected use-case sequence -> Aims to test things like pipeline forwarding"], + 7: ["Expected use-case sequence -> Aims to test things like pipeline forwarding"]} + +n_i = { + 1: [27,3], + 2: [28,30,3], + 3: [27,1], + 4: [28,30,3], + 5: [28,29,3], + 6: [27,1], + 7: [27,1] + } + +swreg1 = "x31" + +seed = 10 + +#------------------------------------------------------------------------------------------------------------------ + +config_ZKn = ['aes64ds','aes64dsm','aes64es','aes64esm','sha256sig0','sha256sig1','sha256sum0','sha256sum1',\ + 'sha512sig0','sha512sig1','sha512sum0','sha512sum1','aes64im','aes32esi','aes32esmi','aes32dsi',\ + 'aes32dsmi','sha512sig0h','sha512sig0l','sha512sig1h','sha512sig1l','sha512sum0r','sha512sum1r'] + +config_ZKs = ['sm3p0','sm3p1','sm4ed','sm4ks'] + +if os.path.isdir(os.getcwd()+"/real_world_tests") == False: + os.mkdir(os.getcwd()+"/real_world_tests") + os.mkdir(os.getcwd()+"/real_world_tests/RV32IK") + os.mkdir(os.getcwd()+"/real_world_tests/RV64IK") + +for key in instr_dict: + for z in instr_dict[key]: + with open(os.getcwd()+'/real_world_tests/RV'+str(xlen[key])+'IK/'+z+'-rwp1.S','w') as out: + offset_val = 0 + if z in config_ZKn: + config = "ZKn" + elif z in config_ZKs: + config = "ZKs" + sp = start_str.replace("$inst",z).replace("$swreg1",swreg1).replace("$xlen",str(xlen[key])).replace("$config",config) + out.write(sp) + out.write('\n\n') + random.seed(seed) + for i in range(1,n_i[key][0]): + out.write("inst_"+str(i-1)+":\n") + + r1 = random.randint(0,2**xlen[key]-1) + r2 = random.randint(0,2**xlen[key]-1) + r3 = random.randint(0,2**xlen[key]-1) + r4 = random.randint(0,2**xlen[key]-1) + r5 = random.randint(0,2**xlen[key]-1) + r6 = random.randint(0,2**xlen[key]-1) + r1_str = '{0:#0{1}x}'.format(r1,int(xlen[key]/4)+2) + r2_str = '{0:#0{1}x}'.format(r2,int(xlen[key]/4)+2) + r3_str = '{0:#0{1}x}'.format(r3,int(xlen[key]/4)+2) + r4_str = '{0:#0{1}x}'.format(r4,int(xlen[key]/4)+2) + r5_str = '{0:#0{1}x}'.format(r5,int(xlen[key]/4)+2) + r6_str = '{0:#0{1}x}'.format(r6,int(xlen[key]/4)+2) + + if key == 1: + comment_str = comment_dict[key][0].replace("$rs1","x"+str(i)).replace("$rs2","x"+str(i+1)).replace("$inst",z) + + sp = string1.replace("$rs1","x"+str(i)).replace("$rs2","x"+str(i+1))\ + .replace("$rd1","x"+str(i+2)).replace("$rd2","x"+str(i+3)).replace("$rd3","x"+str(i+4))\ + .replace("$inst",z).replace("$swreg1",swreg1).replace("$offset1",str(offset_val))\ + .replace("$offset2",str(int(offset_val+xlen[key]/8)))\ + .replace("$offset3",str(int(offset_val+xlen[key]/4)))\ + .replace("$r1_val",r1_str).replace("$r2_val",r2_str).replace("$comment",comment_str) + + offset_val = int(offset_val + (xlen[key]*6)/16) + out.write(sp) + out.write('\n\n') + + elif key == 2 or key == 4 or key == 5: + for j in instr_f[key]: + comment_str = comment_dict[key][0].replace("$inst1",j).replace("$inst2",z) + + if key == 2 or key == 4: + if j == 'not': + sp = string2_not.replace("$rs1","x"+str(i)).replace("$rs2","x"+str(i+1))\ + .replace("$rs3","x"+str(i+2)).replace("$rs4","x"+str(i+3)).replace("$inst1",j)\ + .replace("$inst2",z).replace("$swreg1",swreg1).replace("$offset1",str(offset_val))\ + .replace("$offset2",str(int(offset_val+xlen[key]/8)))\ + .replace("$offset3",str(int(offset_val+xlen[key]/4)))\ + .replace("$r1_val",r1_str).replace("$r2_val",r2_str).replace("$comment",comment_str) + else: + sp = string2.replace("$rs1","x"+str(i)).replace("$rs2","x"+str(i+1))\ + .replace("$rs3","x"+str(i+2)).replace("$rs4","x"+str(i+3)).replace("$inst1",j)\ + .replace("$inst2",z).replace("$swreg1",swreg1).replace("$offset1",str(offset_val))\ + .replace("$offset2",str(int(offset_val+xlen[key]/8)))\ + .replace("$offset3",str(int(offset_val+xlen[key]/4)))\ + .replace("$r1_val",r1_str).replace("$r2_val",r2_str).replace("$comment",comment_str) + elif key == 5: + if j == 'not': + sp = string5_not.replace("$rs1","x"+str(i)).replace("$rs2","x"+str(i+1))\ + .replace("$rs3","x"+str(i+2)).replace("$rs4","x"+str(i+3)).replace("$inst1",j)\ + .replace("$inst2",z).replace("$swreg1",swreg1).replace("$offset1",str(offset_val))\ + .replace("$offset2",str(int(offset_val+xlen[key]/8)))\ + .replace("$offset3",str(int(offset_val+xlen[key]/4)))\ + .replace("$r1_val",r1_str).replace("$r2_val",r2_str).replace("$comment",comment_str) + else : + sp = string5.replace("$rs1","x"+str(i)).replace("$rs2","x"+str(i+1))\ + .replace("$rs3","x"+str(i+2)).replace("$rs4","x"+str(i+3)).replace("$inst1",j)\ + .replace("$inst2",z).replace("$swreg1",swreg1).replace("$offset1",str(offset_val))\ + .replace("$offset2",str(int(offset_val+xlen[key]/8)))\ + .replace("$offset3",str(int(offset_val+xlen[key]/4)))\ + .replace("$r1_val",r1_str).replace("$r2_val",r2_str).replace("$comment",comment_str) + + offset_val = int(offset_val + (xlen[key]*6)/16) + out.write(sp) + out.write('\n\n') + + elif key == 3: + comment_str = comment_dict[key][0] + + sp = string4.replace("$rs1","x"+str(i)).replace("$rs2","x"+str(i+1))\ + .replace("$rs3","x"+str(i+2)).replace("$rs4","x"+str(i+3)).replace("$rs5","x"+str(i+4))\ + .replace("$inst",z).replace("$swreg1",swreg1).replace("$offset1",str(offset_val))\ + .replace("$r1_val",r1_str).replace("$r2_val",r2_str).replace("$r3_val",r3_str)\ + .replace("$r4_val",r4_str).replace("$r5_val",r5_str)\ + .replace("$comment",comment_str) + + offset_val = offset_val + int(xlen[key]/8) + out.write(sp) + out.write('\n\n') + elif key == 6 or key == 7: + comment_str = comment_dict[key][0] + + sp = string7.replace("$rs1","x"+str(i)).replace("$rs2","x"+str(i+1))\ + .replace("$rs3","x"+str(i+2)).replace("$rs4","x"+str(i+3)).replace("$rs5","x"+str(i+4))\ + .replace("$rs6","x"+str(i+5))\ + .replace("$inst",z).replace("$swreg1",swreg1).replace("$offset1",str(offset_val))\ + .replace("$r1_val",r1_str).replace("$r2_val",r2_str).replace("$r3_val",r3_str)\ + .replace("$r4_val",r4_str).replace("$r5_val",r5_str)\ + .replace("$r6_val",r6_str)\ + .replace("$comment",comment_str) + + offset_val = offset_val + int(xlen[key]/8) + out.write(sp) + out.write('\n\n') + + ed = end_str.replace("$swreg1",swreg1)\ + .replace("$fill_val",str(((n_i[key][0])-1)*n_i[key][len(n_i[key])-1]*len(instr_f[key]))) + out.write(ed) + out.write('\n') + out.close() + print("Test File Generated for "+str(xlen[key])+"-bit "+z+"-Test Pattern 1!") + + if key == 2 or key == 4 or key == 5: + with open(os.getcwd()+'/real_world_tests/RV'+str(xlen[key])+'IK/'+z+'-rwp2.S','w') as out: + offset_val1 = 0 + offset_val2 = 0 + if z in config_ZKn: + config = "ZKn" + elif z in config_ZKs: + config = "ZKs" + sp = start_str.replace("$inst",z).replace("$swreg1",swreg1).replace("$xlen",str(xlen[key])).replace("$config",config) + out.write(sp) + out.write('\n\n') + out.write("la x1, rvtest_data") + out.write('\n\n') + random.seed(seed) + for i in range(2,n_i[key][1]): + out.write("inst_"+str(i-2)+":\n") + + comment_str = comment_dict[key][1] + + if key == 2 or key ==4: + sp = string3.replace("$rs0","x1").replace("$rs1","x"+str(i))\ + .replace("$rs2","x"+str(i+1)).replace("$inst",z).replace("$swreg1",swreg1)\ + .replace("$offset1",str(offset_val1)).replace("$offset2",str(offset_val2))\ + .replace("$offset3",str(int(offset_val2+xlen[key]/8))).replace("$comment",comment_str) + elif key == 5: + sp = string6.replace("$rs0","x1").replace("$rs1","x"+str(i))\ + .replace("$rs2","x"+str(i+1)).replace("$rs3","x"+str(i+2))\ + .replace("$inst",z).replace("$swreg1",swreg1).replace("$offset1",str(offset_val1))\ + .replace("$offset2",str(int(offset_val1+xlen[key]/8))).replace("$offset3",str(offset_val2))\ + .replace("$offset4",str(int(offset_val2+xlen[key]/8))).replace("$comment",comment_str) + + offset_val1 = int(offset_val1 + xlen[key]/8) + offset_val2 = int(offset_val2 + xlen[key]/4) + out.write(sp) + out.write('\n\n') + + out.write(end_str1) + out.write('\n') + for j in range(2,30): + x = random.randint(0,2**xlen[key]-1) + x_str = '{0:#0{1}x}'.format(x,int(xlen[key]/4)+2) + if xlen[key] == 64: + out.write(".dword "+x_str+"\n") + else: + out.write(".word "+x_str+"\n") + + ed = end_str2.replace("$swreg1",swreg1).replace("$fill_val",str((n_i[key][1]-2)*2)) + out.write(ed) + out.write('\n') + out.close() + print("Test File Generated for "+str(xlen[key])+"-bit "+z+"-Test Pattern 2!") diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/requirements.txt b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/requirements.txt new file mode 100644 index 000000000..af94a163f --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/requirements.txt @@ -0,0 +1,5 @@ +click +ruamel.yaml>=0.16.0 +colorlog +python-constraint +riscv_isac>=0.14.0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/utils.py b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/utils.py new file mode 100644 index 000000000..d3dd53127 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/riscv_ctg/utils.py @@ -0,0 +1,359 @@ +# See LICENSE.incore for details + +"""Common Utils """ +import sys +import os +import subprocess +import shlex +from riscv_ctg.log import logger +import ruamel +from ruamel.yaml import YAML +from collections import defaultdict +import riscv_ctg.constants as const +from riscv_isac.utils import combineReader + +yaml = YAML(typ="rt") +yaml.default_flow_style = False +yaml.allow_unicode = True + +def load_yaml(foo): + try: + with open(foo, "r") as file: + return dict(yaml.load(file)) + except ruamel.yaml.constructor.DuplicateKeyError as msg: + logger = logging.getLogger(__name__) + error = "\n".join(str(msg).split("\n")[2:-7]) + logger.error(error) + raise SystemExit + +def gen_format_data(): + ''' + Generate dictionary from template.yaml file with the structure: + Format: + - ISA + - Mnemonics + ''' + op_template = load_yaml(const.template_file) + + # Initialize nested dictionary + nested_dict = lambda: defaultdict(nested_dict) + format_dict = nested_dict() + + for mnemonic, data in op_template.items(): + if mnemonic not in ['metadata']: + format_type = data['formattype'] + isa = data['isa'] + + for each in isa: + format_dict[format_type][each][mnemonic] = None + + return format_dict + +def get_instr_list(): + ''' + Get list of all instructions defined in template file + ''' + op_template = load_yaml(const.template_file) + + instr_lst = list(op_template.keys()) + instr_lst.remove('metadata') + + return instr_lst + +def load_yamls(foo): + with combineReader(foo) as fp: + return dict(yaml.load(fp)) + +class makeUtil(): + """ + Utility for ease of use of make commands like `make` and `pmake`. + Supports automatic addition and execution of targets. Uses the class + :py:class:`shellCommand` to execute commands. + """ + def __init__(self,makeCommand='make',makefilePath="./Makefile"): + """ Constructor. + + :param makeCommand: The variant of make to be used with optional arguments. + Ex - `pmake -j 8` + + :type makeCommand: str + + :param makefilePath: The path to the makefile to be used. + + :type makefilePath: str + + """ + self.makeCommand=makeCommand + self.makefilePath = makefilePath + self.targets = [] + def add_target(self,command,tname=""): + """ + Function to add a target to the makefile. + + :param command: The command to be executed when the target is run. + + :type command: str + + :param tname: The name of the target to be used. If not specified, TARGET is used as the name. + + :type tname: str + """ + if tname == "": + tname = "TARGET"+str(len(self.targets)) + with open(self.makefilePath,"a") as makefile: + makefile.write("\n\n.PHONY : " + tname + "\n" + tname + " :\n\t"+command.replace("\n","\n\t")) + self.targets.append(tname) + def execute_target(self,tname,cwd="./"): + """ + Function to execute a particular target only. + + :param tname: Name of the target to execute. + + :type tname: str + + :param cwd: The working directory to be set while executing the make command. + + :type cwd: str + + :raise AssertionError: If target name is not present in the list of defined targets. + + """ + assert tname in self.targets, "Target does not exist." + shellCommand(self.makeCommand+" -f "+self.makefilePath+" "+tname).run(cwd=cwd) + def execute_all(self,cwd): + """ + Function to execute all the defined targets. + + :param cwd: The working directory to be set while executing the make command. + + :type cwd: str + + """ + shellCommand(self.makeCommand+" -f "+self.makefilePath+" "+" ".join(self.targets)).run(cwd=cwd) + + +class Command(): + """ + Class for command build which is supported + by :py:mod:`suprocess` module. Supports automatic + conversion of :py:class:`pathlib.Path` instances to + valid format for :py:mod:`subprocess` functions. + """ + + def __init__(self, *args, pathstyle='auto', ensure_absolute_paths=False): + """Constructor. + + :param pathstyle: Determine the path style when adding instance of + :py:class:`pathlib.Path`. Path style determines the slash type + which separates the path components. If pathstyle is `auto`, then + on Windows backslashes are used and on Linux forward slashes are used. + When backslashes should be prevented on all systems, the pathstyle + should be `posix`. No other values are allowed. + + :param ensure_absolute_paths: If true, then any passed path will be + converted to absolute path. + + :param args: Initial command. + + :type pathstyle: str + + :type ensure_absolute_paths: bool + """ + self.ensure_absolute_paths = ensure_absolute_paths + self.pathstyle = pathstyle + self.args = [] + + for arg in args: + self.append(arg) + + def append(self, arg): + """Add new argument to command. + + :param arg: Argument to be added. It may be list, tuple, + :py:class:`Command` instance or any instance which + supports :py:func:`str`. + """ + to_add = [] + if type(arg) is list: + to_add = arg + elif type(arg) is tuple: + to_add = list(arg) + elif isinstance(arg, type(self)): + to_add = arg.args + elif isinstance(arg, str) and not self._is_shell_command(): + to_add = shlex.split(arg) + else: + # any object which will be converted into str. + to_add.append(arg) + + # Convert all arguments to its string representation. + # pathlib.Path instances + to_add = [ + self._path2str(el) if isinstance(el, pathlib.Path) else str(el) + for el in to_add + ] + self.args.extend(to_add) + + def clear(self): + """Clear arguments.""" + self.args = [] + + def run(self, **kwargs): + """Execute the current command. + + Uses :py:class:`subprocess.Popen` to execute the command. + + :return: The return code of the process . + :raise subprocess.CalledProcessError: If `check` is set + to true in `kwargs` and the process returns + non-zero value. + """ + kwargs.setdefault('shell', self._is_shell_command()) + cwd = self._path2str(kwargs.get( + 'cwd')) if not kwargs.get('cwd') is None else self._path2str( + os.getcwd()) + kwargs.update({'cwd': cwd}) + logger.debug(cwd) + # When running as shell command, subprocess expects + # The arguments to be string. + logger.debug(str(self)) + cmd = str(self) if kwargs['shell'] else self + x = subprocess.Popen(cmd, + stdout=subprocess.PIPE, + stderr=subprocess.PIPE, + **kwargs) + out, err = x.communicate() + out = out.rstrip() + err = err.rstrip() + if x.returncode != 0: + if out: + logger.error(out.decode("ascii")) + if err: + logger.error(err.decode("ascii")) + else: + if out: + logger.warning(out.decode("ascii")) + if err: + logger.warning(err.decode("ascii")) + return x.returncode + + def _is_shell_command(self): + """ + Return true if current command is supposed to be executed + as shell script otherwise false. + """ + return any('|' in arg for arg in self.args) + + def _path2str(self, path): + """Convert :py:class:`pathlib.Path` to string. + + The final form of the string is determined by the + configuration of `Command` instance. + + :param path: Path-like object which will be converted + into string. + :return: String representation of `path` + """ + path = pathlib.Path(path) + if self.ensure_absolute_paths and not path.is_absolute(): + path = path.resolve() + + if self.pathstyle == 'posix': + return path.as_posix() + elif self.pathstyle == 'auto': + return str(path) + else: + raise ValueError(f"Invalid pathstyle {self.pathstyle}") + + def __add__(self, other): + cmd = Command(self, + pathstyle=self.pathstyle, + ensure_absolute_paths=self.ensure_absolute_paths) + cmd += other + return cmd + + def __iadd__(self, other): + self.append(other) + return self + + def __iter__(self): + """ + Support iteration so functions from :py:mod:`subprocess` module + support `Command` instance. + """ + return iter(self.args) + + def __repr__(self): + return f'<{self.__class__.__name__} args={self.args}>' + + def __str__(self): + return ' '.join(self.args) + + +class shellCommand(Command): + """ + Sub Class of the command class which always executes commands as shell commands. + """ + + def __init__(self, *args, pathstyle='auto', ensure_absolute_paths=False): + """ + :param pathstyle: Determine the path style when adding instance of + :py:class:`pathlib.Path`. Path style determines the slash type + which separates the path components. If pathstyle is `auto`, then + on Windows backslashes are used and on Linux forward slashes are used. + When backslashes should be prevented on all systems, the pathstyle + should be `posix`. No other values are allowed. + + :param ensure_absolute_paths: If true, then any passed path will be + converted to absolute path. + + :param args: Initial command. + + :type pathstyle: str + + :type ensure_absolute_paths: bool + + """ + return super().__init__(*args, + pathstyle=pathstyle, + ensure_absolute_paths=ensure_absolute_paths) + + def _is_shell_command(self): + return True + +def sys_command(command): + logger.warning('$ {0} '.format(' '.join(shlex.split(command)))) + x = subprocess.Popen(shlex.split(command), + stdout=subprocess.PIPE, + stderr=subprocess.PIPE, + ) + try: + out, err = x.communicate(timeout=5) + except subprocess.TimeoutExpired: + x.kill() + out, err = x.communicate() + + out = out.rstrip() + err = err.rstrip() + if x.returncode != 0: + if out: + logger.error(out.decode("ascii")) + if err: + logger.error(err.decode("ascii")) + else: + if out: + logger.debug(out.decode("ascii")) + if err: + logger.debug(err.decode("ascii")) + return out.decode("ascii") + +def sys_command_file(command, filename): + cmd = command.split(' ') + cmd = [x.strip(' ') for x in cmd] + cmd = [i for i in cmd if i] + logger.debug('{0} > {1}'.format(' '.join(cmd), filename)) + fp = open(filename, 'w') + out = subprocess.Popen(cmd, stdout=fp, stderr=fp) + stdout, stderr = out.communicate() + fp.close() + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/README.md b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/README.md new file mode 100644 index 000000000..ea1e47ae8 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/README.md @@ -0,0 +1,13 @@ +## CGF: Cover Group Format + +- Uses a simple to use and a human readable YAML format to define cover groups and cover-points for the RISC-V ISA. +- Declares datasets separately which can be used across coverpoints: + - Operand Addresses for a single instruction + - Operand Value for a single instruction + - Abstract functions like walking1s and walking0s which get unrolled by the extraction tool +- Covergroups include multiple datasets + - Each coverpoint is defined as a boolean expression which can to be evaluated by the "eval" + tool of python. + - Coverpoints to use a standard set of keywords like: rs1, rs2, rd, rs1_val, rs2_val, etc +- Uses Anchors and Aliases to keep the size of the YAML file small + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/cgf.yaml b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/cgf.yaml new file mode 100644 index 000000000..ab8e8101d --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/cgf.yaml @@ -0,0 +1,2239 @@ +# For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore + +datasets: + all_regs: &all_regs + x0: 0 + x1: 0 + x2: 0 + x3: 0 + x4: 0 + x5: 0 + x6: 0 + x7: 0 + x8: 0 + x9: 0 + x10: 0 + x11: 0 + x12: 0 + x13: 0 + x14: 0 + x15: 0 + x16: 0 + x17: 0 + x18: 0 + x19: 0 + x20: 0 + x21: 0 + x22: 0 + x23: 0 + x24: 0 + x25: 0 + x26: 0 + x27: 0 + x28: 0 + x29: 0 + x30: 0 + x31: 0 + + pair_regs: &pair_regs + x0: 0 + x2: 0 + x4: 0 + x6: 0 + x8: 0 + x10: 0 + x12: 0 + x14: 0 + x16: 0 + x18: 0 + x20: 0 + x22: 0 + x24: 0 + x26: 0 + x28: 0 + x30: 0 + + + c_regs: &c_regs + x8: 0 + x9: 0 + x10: 0 + x11: 0 + x12: 0 + x13: 0 + x14: 0 + x15: 0 + + all_regs_mx0: &all_regs_mx0 + x1: 0 + x2: 0 + x3: 0 + x4: 0 + x5: 0 + x6: 0 + x7: 0 + x8: 0 + x9: 0 + x10: 0 + x11: 0 + x12: 0 + x13: 0 + x14: 0 + x15: 0 + x16: 0 + x17: 0 + x18: 0 + x19: 0 + x20: 0 + x21: 0 + x22: 0 + x23: 0 + x24: 0 + x25: 0 + x26: 0 + x27: 0 + x28: 0 + x29: 0 + x30: 0 + x31: 0 + + cbfmt_immval_sgn: &cbfmt_immval_sgn + 'imm_val == (-2**(6-1))': 0 + 'imm_val == 0': 0 + 'imm_val == (2**(6-1)-1)': 0 + 'imm_val == 1': 0 + + rfmt_op_comb: &rfmt_op_comb + 'rs1 == rs2 != rd': 0 + 'rs1 == rd != rs2': 0 + 'rs2 == rd != rs1': 0 + 'rs1 == rs2 == rd': 0 + 'rs1 != rs2 and rs1 != rd and rs2 != rd': 0 + + ifmt_op_comb: &ifmt_op_comb + 'rs1 == rd': 0 + 'rs1 != rd': 0 + + sfmt_op_comb: &sfmt_op_comb + 'rs1 == rs2': 0 + 'rs1 != rs2': 0 + + base_rs1val_sgn: &base_rs1val_sgn + 'rs1_val == (-2**(xlen-1))': 0 + 'rs1_val == 0': 0 + 'rs1_val == (2**(xlen-1)-1)': 0 + 'rs1_val == 1': 0 + + base_rs2val_sgn: &base_rs2val_sgn + 'rs2_val == (-2**(xlen-1))': 0 + 'rs2_val == 0': 0 + 'rs2_val == (2**(xlen-1)-1)': 0 + 'rs2_val == 1': 0 + + base_rs1val_unsgn: &base_rs1val_unsgn + 'rs1_val == 0': 0 + 'rs1_val == (2**(xlen)-1)': 0 + 'rs1_val == 1': 0 + + base_rs2val_unsgn: &base_rs2val_unsgn + 'rs2_val == 0': 0 + 'rs2_val == (2**(xlen)-1)': 0 + 'rs2_val == 1': 0 + + base_rs3val_unsgn: &base_rs3val_unsgn + 'rs3_val == 0': 0 + 'rs3_val == (2**(xlen)-1)': 0 + 'rs3_val == 1': 0 + + + rfmt_val_comb_sgn: &rfmt_val_comb_sgn + 'rs1_val > 0 and rs2_val > 0': 0 + 'rs1_val > 0 and rs2_val < 0': 0 + 'rs1_val < 0 and rs2_val < 0': 0 + 'rs1_val < 0 and rs2_val > 0': 0 + 'rs1_val == rs2_val': 0 + 'rs1_val != rs2_val': 0 + + rfmt_val_comb_unsgn: &rfmt_val_comb_unsgn + 'rs1_val > 0 and rs2_val > 0': 0 + 'rs1_val == rs2_val and rs1_val > 0 and rs2_val > 0': 0 + 'rs1_val != rs2_val and rs1_val > 0 and rs2_val > 0': 0 + + ifmt_val_comb_sgn: &ifmt_val_comb_sgn + 'rs1_val == imm_val': 0 + 'rs1_val != imm_val': 0 + 'rs1_val > 0 and imm_val > 0': 0 + 'rs1_val > 0 and imm_val < 0': 0 + 'rs1_val < 0 and imm_val > 0': 0 + 'rs1_val < 0 and imm_val < 0': 0 + + ifmt_val_comb_unsgn: &ifmt_val_comb_unsgn + 'rs1_val == imm_val and rs1_val > 0 and imm_val > 0': 0 + 'rs1_val != imm_val and rs1_val > 0 and imm_val > 0': 0 + + ifmt_base_immval_sgn: &ifmt_base_immval_sgn + 'imm_val == (-2**(12-1))': 0 + 'imm_val == 0': 0 + 'imm_val == (2**(12-1)-1)': 0 + 'imm_val == 1': 0 + + ifmt_base_immval_unsgn: &ifmt_base_immval_unsgn + 'imm_val == 0': 0 + 'imm_val == (2**(12)-1)': 0 + 'imm_val == 1': 0 + + ifmt_base_shift: &ifmt_base_shift + 'rs1_val < 0 and imm_val > 0 and imm_val < xlen': 0 + 'rs1_val > 0 and imm_val > 0 and imm_val < xlen': 0 + 'rs1_val < 0 and imm_val == 0': 0 + 'rs1_val > 0 and imm_val == 0': 0 + 'rs1_val < 0 and imm_val == (xlen-1)': 0 + 'rs1_val > 0 and imm_val == (xlen-1)': 0 + 'rs1_val == imm_val and imm_val > 0 and imm_val < xlen': 0 + 'rs1_val == (-2**(xlen-1)) and imm_val >= 0 and imm_val < xlen': 0 + 'rs1_val == 0 and imm_val >= 0 and imm_val < xlen': 0 + 'rs1_val == (2**(xlen-1)-1) and imm_val >= 0 and imm_val < xlen': 0 + 'rs1_val == 1 and imm_val >= 0 and imm_val < xlen': 0 + + ifmt_base_shift_32w: &ifmt_base_shift_32w + 'rs1_val < 0 and imm_val > 0 and imm_val < 32': 0 + 'rs1_val > 0 and imm_val > 0 and imm_val < 32': 0 + 'rs1_val < 0 and imm_val == 0': 0 + 'rs1_val > 0 and imm_val == 0': 0 + 'rs1_val < 0 and imm_val == 31': 0 + 'rs1_val > 0 and imm_val == 31': 0 + 'rs1_val == imm_val and imm_val > 0 and imm_val < 32': 0 + 'rs1_val == (-2**(xlen-1)) and imm_val >= 0 and imm_val < 32': 0 + 'rs1_val == 0 and imm_val >= 0 and imm_val < 32': 0 + 'rs1_val == (2**(xlen-1)-1) and imm_val >= 0 and imm_val < 32': 0 + 'rs1_val == 1 and imm_val >= 0 and imm_val < 32': 0 + + + rfmt_base_shift: &rfmt_base_shift + 'rs1_val < 0 and rs2_val > 0 and rs2_val < xlen': 0 + 'rs1_val > 0 and rs2_val > 0 and rs2_val < xlen': 0 + 'rs1_val < 0 and rs2_val == 0': 0 + 'rs1_val > 0 and rs2_val == 0': 0 + 'rs1_val == rs2_val and rs2_val > 0 and rs2_val < xlen': 0 + 'rs1_val == (-2**(xlen-1)) and rs2_val >= 0 and rs2_val < xlen': 0 + 'rs1_val == 0 and rs2_val >= 0 and rs2_val < xlen': 0 + 'rs1_val == (2**(xlen-1)-1) and rs2_val >= 0 and rs2_val < xlen': 0 + 'rs1_val == 1 and rs2_val >= 0 and rs2_val < xlen': 0 + + bfmt_base_branch_val_align_sgn: &bfmt_base_branch_val_align_sgn + 'rs1_val > 0 and rs2_val > 0 and imm_val & 0x03 == 0': 0 + 'rs1_val > 0 and rs2_val < 0 and imm_val & 0x03 == 0': 0 + 'rs1_val < 0 and rs2_val < 0 and imm_val & 0x03 == 0': 0 + 'rs1_val < 0 and rs2_val > 0 and imm_val & 0x03 == 0': 0 + 'rs1_val == rs2_val and imm_val > 0 and imm_val & 0x03 == 0': 0 + 'rs1_val == rs2_val and imm_val < 0 and imm_val & 0x03 == 0': 0 + 'rs1_val > rs2_val and imm_val > 0 and imm_val & 0x03 == 0': 0 + 'rs1_val > rs2_val and imm_val < 0 and imm_val & 0x03 == 0': 0 + 'rs1_val < rs2_val and imm_val > 0 and imm_val & 0x03 == 0': 0 + 'rs1_val < rs2_val and imm_val < 0 and imm_val & 0x03 == 0': 0 + + bfmt_base_branch_val_align_unsgn: &bfmt_base_branch_val_align_unsgn + 'rs1_val > 0 and rs2_val > 0': 0 + 'rs1_val > 0 and rs2_val > 0 and rs1_val == rs2_val and imm_val > 0': 0 + 'rs1_val > 0 and rs2_val > 0 and rs1_val == rs2_val and imm_val < 0': 0 + 'rs1_val > 0 and rs2_val > 0 and rs1_val > rs2_val and imm_val > 0 ': 0 + 'rs1_val > 0 and rs2_val > 0 and rs1_val > rs2_val and imm_val < 0 ': 0 + 'rs1_val > 0 and rs2_val > 0 and rs1_val < rs2_val and imm_val > 0 ': 0 + 'rs1_val > 0 and rs2_val > 0 and rs1_val < rs2_val and imm_val < 0 ': 0 + + rs1val_walking: &rs1val_walking + 'walking_ones("rs1_val", xlen)': 0 + 'walking_zeros("rs1_val", xlen)': 0 + 'alternate("rs1_val",xlen)': 0 + + rs2val_walking: &rs2val_walking + 'walking_ones("rs2_val", xlen)': 0 + 'walking_zeros("rs2_val", xlen)': 0 + 'alternate("rs2_val",xlen)': 0 + + rs3val_walking: &rs3val_walking + 'walking_ones("rs3_val", xlen)': 0 + 'walking_zeros("rs3_val", xlen)': 0 + 'alternate("rs3_val",xlen)': 0 + + ifmt_immval_walking: &ifmt_immval_walking + 'walking_ones("imm_val", 12)': 0 + 'walking_zeros("imm_val", 12)': 0 + 'alternate("imm_val",12)': 0 + + rs1val_walking_unsgn: &rs1val_walking_unsgn + 'walking_ones("rs1_val", xlen,False)': 0 + 'walking_zeros("rs1_val", xlen,False)': 0 + 'alternate("rs1_val",xlen,False)': 0 + + rs2val_walking_unsgn: &rs2val_walking_unsgn + 'walking_ones("rs2_val", xlen,False)': 0 + 'walking_zeros("rs2_val", xlen,False)': 0 + 'alternate("rs2_val",xlen,False)': 0 + + crfmt_val_comb_sgn: &crfmt_val_comb_sgn + 'rs2_val > 0': 0 + 'rs2_val < 0': 0 + + cbimm_val_walking: &cbimm_val_walking + 'walking_ones("imm_val", 6)': 0 + 'walking_zeros("imm_val", 6)': 0 + 'alternate("imm_val",6)': 0 + + ifmt_immval_walking_unsgn: &ifmt_immval_walking_unsgn + 'walking_ones("imm_val", 12,False)': 0 + 'walking_zeros("imm_val", 12,False)': 0 + 'alternate("imm_val",12,False)': 0 + +ecall: + config: + - check ISA:=regex(.*I.*); def rvtest_mtrap_routine=True + opcode: + ecall: 0 + +ebreak: + config: + - check ISA:=regex(.*I.*); def rvtest_mtrap_routine=True + opcode: + ebreak: 0 + +fencei: + config: + - check ISA:=regex(.*I.*Zifencei.*) + opcode: + fence.i: 0 + +misalign-lh: + cond: check ISA:=regex(.*I.*Zicsr.*) + config: + - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True + - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True + opcode: + lh: 0 + val_comb: + 'ea_align == 1': 0 + +misalign-lhu: + config: + - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True + - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*I.*Zicsr.*) + opcode: + lhu: 0 + val_comb: + 'ea_align == 1': 0 + +misalign-lwu: + config: + - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True + - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*64.*I.*Zicsr.*) + opcode: + lwu: 0 + val_comb: + 'ea_align == 1': 0 + 'ea_align == 2': 0 + 'ea_align == 3': 0 + +misalign-sd: + config: + - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True + - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*64.*I.*Zicsr.*) + opcode: + sd: 0 + val_comb: + 'ea_align == 1': 0 + 'ea_align == 2': 0 + 'ea_align == 3': 0 + 'ea_align == 4': 0 + 'ea_align == 5': 0 + 'ea_align == 6': 0 + 'ea_align == 7': 0 + +misalign-ld: + config: + - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True + - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*64.*I.*) + opcode: + ld: 0 + val_comb: + 'ea_align == 1': 0 + 'ea_align == 2': 0 + 'ea_align == 3': 0 + 'ea_align == 4': 0 + 'ea_align == 5': 0 + 'ea_align == 6': 0 + 'ea_align == 7': 0 + +misalign-lw: + config: + - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True + - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*I.*Zicsr.*) + opcode: + lw: 0 + val_comb: + 'ea_align == 1': 0 + 'ea_align == 2': 0 + 'ea_align == 3': 0 + +misalign-sh: + config: + - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True + - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*I.*Zicsr.*) + opcode: + sh: 0 + val_comb: + 'ea_align == 1': 0 + +misalign-sw: + config: + - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True + - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*I.*Zicsr.*) + opcode: + sw: 0 + val_comb: + 'ea_align == 1': 0 + 'ea_align == 2': 0 + 'ea_align == 3': 0 + +misalign2-jalr: + config: + - check ISA:=regex(.*I.*C.*) + - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*I.*) + opcode: + jalr: 0 + val_comb: + 'ea_align == 2': 0 + +misalign1-jalr: + config: + - check ISA:=regex(.*I.*); def rvtest_mtrap_routine=True + opcode: + jalr: 0 + val_comb: + 'ea_align == 1': 0 + +misalign-jal: + config: + - check ISA:=regex(.*I.*C.*) + - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*I.*) + opcode: + jal: 0 + val_comb: + 'ea_align == 2': 0 + +misalign-bge: + config: + - check ISA:=regex(.*I.*C.*) + - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*I.*) + opcode: + bge: 0 + val_comb: + ' rs1_val>rs2_val and ea_align == 2': 0 + +misalign-bgeu: + config: + - check ISA:=regex(.*I.*C.*) + - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*I.*) + opcode: + bgeu: 0 + val_comb: + ' rs1_val>rs2_val and ea_align == 2': 0 + +misalign-blt: + config: + - check ISA:=regex(.*I.*C.*) + - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*I.*) + opcode: + blt: 0 + val_comb: + ' rs1_val 0' : 0 + 'imm_val == 1020': 0 + abstract_comb: + 'walking_ones("imm_val", 8,False,scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val", 8,False,scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",8,False,scale_func = lambda x: x*4)': 0 + +clw: + config: + - check ISA:=regex(.*I.*C.*) + opcode: + c.lw: 0 + rs1: + <<: *c_regs + rd: + <<: *c_regs + op_comb: + 'rs1 == rd': 0 + 'rs1 != rd': 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0 + +cld: + config: + - check ISA:=regex(.*RV64.*I.*C.*) + opcode: + c.ld: 0 + rs1: + <<: *c_regs + rd: + <<: *c_regs + op_comb: + 'rs1 == rd': 0 + 'rs1 != rd': 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 + +csw: + config: + - check ISA:=regex(.*I.*C.*) + opcode: + c.sw: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0 + +csd: + config: + - check ISA:=regex(.*RV64.*I.*C.*) + opcode: + c.sd: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 + +cnop: + config: + - check ISA:=regex(.*I.*C.*) + opcode: + c.nop: 0 + val_comb: + abstract_comb: + <<: *cbimm_val_walking + +caddi: + config: + - check ISA:=regex(.*I.*C.*) + opcode: + c.addi: 0 + rd: + <<: *all_regs_mx0 + val_comb: + <<: [*base_rs1val_sgn, *cbfmt_immval_sgn, *ifmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *cbimm_val_walking] + +cjal: + config: + - check ISA:=regex(.*RV32.*I.*C.*) + opcode: + c.jal: 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val < 0': 0 + abstract_comb: + 'walking_ones("imm_val", 11,fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030),scale_func = lambda x: x*2)': 0 + 'walking_zeros("imm_val", 11,fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030),scale_func = lambda x: x*2)': 0 + 'alternate("imm_val",11, fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030) ,scale_func = lambda x: x*2)': 0 + +caddiw: + config: + - check ISA:=regex(.*RV64.*I.*C.*) + opcode: + c.addiw: 0 + rd: + <<: *all_regs_mx0 + val_comb: + 'rs1_val == (-2**(xlen-1))': 0 + 'rs1_val == 0': 0 + 'rs1_val == (2**(xlen-1)-1)': 0 + 'rs1_val == 1': 0 + <<: [*cbfmt_immval_sgn, *ifmt_val_comb_sgn] + abstract_comb: + 'walking_ones("rs1_val", xlen)': 0 + 'walking_zeros("rs1_val", xlen)': 0 + 'alternate("rs1_val",xlen)': 0 + <<: [*cbimm_val_walking] + +cli: + config: + - check ISA:=regex(.*I.*C.*) + opcode: + c.li: 0 + rd: + <<: *all_regs + val_comb: + <<: [*cbfmt_immval_sgn] + abstract_comb: + 'walking_ones("imm_val", 6)': 0 + 'walking_zeros("imm_val", 6)': 0 + 'alternate("imm_val", 6)': 0 + +caddi16sp: + config: + - check ISA:=regex(.*I.*C.*) + opcode: + c.addi16sp: 0 + rd: + x2: 0 + val_comb: + <<: [*base_rs1val_sgn,*ifmt_val_comb_sgn] + 'imm_val == -512': 0 + 'imm_val == 496': 0 + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("imm_val", 6,True,scale_func = lambda x: x*16)': 0 + 'walking_zeros("imm_val", 6,True,scale_func = lambda x: x*16)': 0 + 'alternate("imm_val",6,True,scale_func = lambda x: x*16)': 0 + +clui: + config: + - check ISA:=regex(.*I.*C.*) + opcode: + c.lui: 0 + rd: + x0: 0 + x1: 0 + x3: 0 + x4: 0 + x5: 0 + x6: 0 + x7: 0 + x8: 0 + x9: 0 + x10: 0 + x11: 0 + x12: 0 + x13: 0 + x14: 0 + x15: 0 + x16: 0 + x17: 0 + x18: 0 + x19: 0 + x20: 0 + x21: 0 + x22: 0 + x23: 0 + x24: 0 + x25: 0 + x26: 0 + x27: 0 + x28: 0 + x29: 0 + x30: 0 + x31: 0 + + val_comb: + 'rs1_val > 0 and imm_val > 32': 0 + 'rs1_val > 0 and imm_val < 32 and imm_val !=0 ': 0 + 'rs1_val < 0 and imm_val > 32': 0 + 'rs1_val < 0 and imm_val < 32 and imm_val !=0 ': 0 + abstract_comb: + 'walking_ones("imm_val", 6, False)': 0 + 'walking_zeros("imm_val", 6, False)': 0 + 'alternate("imm_val", 6, False)': 0 + +csrli: + config: + - check ISA:=regex(.*I.*C.*) + opcode: + c.srli: 0 + rs1: + <<: *c_regs + val_comb: + 'rs1_val < 0 and imm_val < xlen': 0 + 'rs1_val > 0 and imm_val < xlen': 0 + 'rs1_val == imm_val and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == 0 and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == 1 and imm_val != 0 and imm_val < xlen': 0 + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 + 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 + +csrai: + config: + - check ISA:=regex(.*I.*C.*) + opcode: + c.srai: 0 + rs1: + <<: *c_regs + val_comb: + 'rs1_val < 0 and imm_val < xlen': 0 + 'rs1_val > 0 and imm_val < xlen': 0 + 'rs1_val == imm_val and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == 0 and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == 1 and imm_val != 0 and imm_val < xlen': 0 + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 + 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 + +candi: + config: + - check ISA:=regex(.*I.*C.*) + opcode: + c.andi: 0 + rs1: + <<: *c_regs + val_comb: + <<: [*base_rs1val_sgn,*cbfmt_immval_sgn,*ifmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *cbimm_val_walking] + +csub: + config: + - check ISA:=regex(.*I.*C.*) + opcode: + c.sub: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn, *base_rs2val_sgn] + abstract_comb: + <<: [*rs1val_walking,*rs2val_walking] + +cxor: + config: + - check ISA:=regex(.*I.*C.*) + opcode: + c.xor: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn, *base_rs2val_sgn] + abstract_comb: + <<: [*rs1val_walking,*rs2val_walking] + +cor: + config: + - check ISA:=regex(.*I.*C.*) + opcode: + c.or: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn,*base_rs2val_sgn] + abstract_comb: + <<: [*rs1val_walking,*rs2val_walking] + +cand: + config: + - check ISA:=regex(.*I.*C.*) + opcode: + c.and: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn,*base_rs2val_sgn] + abstract_comb: + <<: [*rs1val_walking,*rs2val_walking] + +csubw: + config: + - check ISA:=regex(.*RV64.*I.*C.*) + opcode: + c.subw: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn, *base_rs2val_sgn] + abstract_comb: + <<: [*rs1val_walking,*rs2val_walking] + +caddw: + config: + - check ISA:=regex(.*RV64.*I.*C.*) + opcode: + c.addw: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn, *base_rs2val_sgn] + abstract_comb: + <<: [*rs1val_walking,*rs2val_walking] + +cj: + config: + - check ISA:=regex(.*I.*C.*) + opcode: + c.j: 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val < 0': 0 + abstract_comb: + 'walking_ones("imm_val", 11,fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030),scale_func = lambda x: x*2)': 0 + 'walking_zeros("imm_val", 11,fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030),scale_func = lambda x: x*2)': 0 + 'alternate("imm_val",11, fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030) ,scale_func = lambda x: x*2)': 0 + +cbeqz: + config: + - check ISA:=regex(.*I.*C.*) + opcode: + c.beqz: 0 + rs1: + <<: *c_regs + val_comb: + 'rs1_val > 0 and imm_val > 0': 0 + 'rs1_val < 0 and imm_val > 0': 0 + 'rs1_val == 0 and imm_val > 0': 0 + 'rs1_val > 0 and imm_val < 0': 0 + 'rs1_val < 0 and imm_val < 0': 0 + 'rs1_val == 0 and imm_val < 0': 0 + <<: [*base_rs1val_sgn] + abstract_comb: + <<: [*rs1val_walking] + +cbnez: + config: + - check ISA:=regex(.*I.*C.*) + opcode: + c.bnez: 0 + rs1: + <<: *c_regs + val_comb: + 'rs1_val > 0 and imm_val > 0': 0 + 'rs1_val < 0 and imm_val > 0': 0 + 'rs1_val == 0 and imm_val > 0': 0 + 'rs1_val > 0 and imm_val < 0': 0 + 'rs1_val < 0 and imm_val < 0': 0 + 'rs1_val == 0 and imm_val < 0': 0 + <<: [*base_rs1val_sgn] + abstract_comb: + <<: [*rs1val_walking] + +cslli: + config: + - check ISA:=regex(.*I.*C.*) + opcode: + c.slli: 0 + rd: + <<: *c_regs + val_comb: + 'rs1_val < 0 and imm_val < xlen': 0 + 'rs1_val > 0 and imm_val < xlen': 0 + 'rs1_val == imm_val and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == 0 and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == 1 and imm_val != 0 and imm_val < xlen': 0 + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 + 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 + +clwsp: + config: + - check ISA:=regex(.*I.*C.*) + opcode: + c.lwsp: 0 + rd: + <<: *all_regs_mx0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0 + +cldsp: + config: + - check ISA:=regex(.*RV64.*I.*C.*) + opcode: + c.ldsp: 0 + rd: + <<: *all_regs_mx0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 + +cjr: + config: + - check ISA:=regex(.*I.*C.*) + opcode: + c.jr: 0 + rs1: + <<: *all_regs_mx0 + +cmv: + config: + - check ISA:=regex(.*I.*C.*) + opcode: + c.mv: 0 + rs2: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +cadd: + config: + - check ISA:=regex(.*I.*C.*) + opcode: + c.add: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs_mx0 + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn,*base_rs2val_sgn] + abstract_comb: + <<: [*rs1val_walking,*rs2val_walking] + +cjalr: + config: + - check ISA:=regex(.*I.*C.*) + opcode: + c.jalr: 0 + rs1: + <<: *all_regs_mx0 + +cswsp: + config: + - check ISA:=regex(.*I.*C.*) + opcode: + c.swsp: 0 + rs2: + <<: *all_regs + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0 + +csdsp: + config: + - check ISA:=regex(.*RV64.*I.*C.*) + opcode: + c.sdsp: 0 + rs2: + <<: *all_regs + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 + +addi: + config: + - check ISA:=regex(.*I.*) + opcode: + addi: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + <<: [*rs1val_walking, *ifmt_immval_walking] + +slti: + config: + - check ISA:=regex(.*I.*) + opcode: + slti: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] + abstract_comb: + <<: [*rs1val_walking, *ifmt_immval_walking] + +sltiu: + config: + - check ISA:=regex(.*I.*) + opcode: + sltiu: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [*ifmt_val_comb_unsgn , *base_rs1val_unsgn , *ifmt_base_immval_unsgn] + abstract_comb: + <<: [*rs1val_walking_unsgn, *ifmt_immval_walking_unsgn] + +andi: + config: + - check ISA:=regex(.*I.*) + opcode: + andi: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] + abstract_comb: + <<: [*rs1val_walking, *ifmt_immval_walking] + +ori: + config: + - check ISA:=regex(.*I.*) + opcode: + ori: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] + abstract_comb: + <<: [*rs1val_walking, *ifmt_immval_walking] + +xori: + config: + - check ISA:=regex(.*I.*) + opcode: + xori: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] + abstract_comb: + <<: [*rs1val_walking, *ifmt_immval_walking] + +slli: + config: + - check ISA:=regex(.*I.*) + opcode: + slli: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: *ifmt_base_shift + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 + 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 + +srai: + config: + - check ISA:=regex(.*I.*) + opcode: + srai: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: *ifmt_base_shift + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 + 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 + +srli: + config: + - check ISA:=regex(.*I.*) + opcode: + srli: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: *ifmt_base_shift + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 + 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 + +add: + config: + - check ISA:=regex(.*I.*) + opcode: + add: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +sub: + config: + - check ISA:=regex(.*I.*) + opcode: + sub: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +slt: + config: + - check ISA:=regex(.*I.*) + opcode: + slt: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +sltu: + config: + - check ISA:=regex(.*I.*) + opcode: + sltu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + +and: + config: + - check ISA:=regex(.*I.*) + opcode: + and: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +or: + config: + - check ISA:=regex(.*I.*) + opcode: + or: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +xor: + config: + - check ISA:=regex(.*I.*) + opcode: + xor: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +sll: + config: + - check ISA:=regex(.*I.*) + opcode: + sll: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: *rfmt_base_shift + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("rs2_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(xlen,2)), False)': 0 + 'alternate("rs2_val", ceil(log(xlen,2)), False)': 0 + +srl: + config: + - check ISA:=regex(.*I.*) + opcode: + srl: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: *rfmt_base_shift + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("rs2_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(xlen,2)), False)': 0 + 'alternate("rs2_val", ceil(log(xlen,2)), False)': 0 + +sra: + config: + - check ISA:=regex(.*I.*) + opcode: + sra: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: *rfmt_base_shift + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("rs2_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(xlen,2)), False)': 0 + 'alternate("rs2_val", ceil(log(xlen,2)), False)': 0 + +beq: + config: + - check ISA:=regex(.*I.*) + opcode: + beq: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *bfmt_base_branch_val_align_sgn + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +bge: + config: + - check ISA:=regex(.*I.*) + opcode: + bge: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *bfmt_base_branch_val_align_sgn + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +bgeu: + config: + - check ISA:=regex(.*I.*) + opcode: + bgeu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *bfmt_base_branch_val_align_unsgn + abstract_comb: + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + +blt: + config: + - check ISA:=regex(.*I.*) + opcode: + blt: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *bfmt_base_branch_val_align_sgn + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +bltu: + config: + - check ISA:=regex(.*I.*) + opcode: + bltu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *bfmt_base_branch_val_align_unsgn + abstract_comb: + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + +bne: + config: + - check ISA:=regex(.*I.*) + opcode: + bne: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *bfmt_base_branch_val_align_sgn + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +lhu-align: + config: + - check ISA:=regex(.*I.*) + opcode: + lhu: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'ea_align == 2 and (imm_val % 4) == 0': 0 + 'ea_align == 2 and (imm_val % 4) == 1': 0 + 'ea_align == 2 and (imm_val % 4) == 2': 0 + 'ea_align == 2 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + +lh-align: + config: + - check ISA:=regex(.*I.*) + opcode: + lh: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'ea_align == 2 and (imm_val % 4) == 0': 0 + 'ea_align == 2 and (imm_val % 4) == 1': 0 + 'ea_align == 2 and (imm_val % 4) == 2': 0 + 'ea_align == 2 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + +lbu-align: + config: + - check ISA:=regex(.*I.*) + opcode: + lbu: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'ea_align == 2 and (imm_val % 4) == 0': 0 + 'ea_align == 2 and (imm_val % 4) == 1': 0 + 'ea_align == 2 and (imm_val % 4) == 2': 0 + 'ea_align == 2 and (imm_val % 4) == 3': 0 + 'ea_align == 1 and (imm_val % 4) == 0': 0 + 'ea_align == 1 and (imm_val % 4) == 1': 0 + 'ea_align == 1 and (imm_val % 4) == 2': 0 + 'ea_align == 1 and (imm_val % 4) == 3': 0 + 'ea_align == 3 and (imm_val % 4) == 0': 0 + 'ea_align == 3 and (imm_val % 4) == 1': 0 + 'ea_align == 3 and (imm_val % 4) == 2': 0 + 'ea_align == 3 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + +lb-align: + config: + - check ISA:=regex(.*I.*) + opcode: + lb: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'ea_align == 2 and (imm_val % 4) == 0': 0 + 'ea_align == 2 and (imm_val % 4) == 1': 0 + 'ea_align == 2 and (imm_val % 4) == 2': 0 + 'ea_align == 2 and (imm_val % 4) == 3': 0 + 'ea_align == 1 and (imm_val % 4) == 0': 0 + 'ea_align == 1 and (imm_val % 4) == 1': 0 + 'ea_align == 1 and (imm_val % 4) == 2': 0 + 'ea_align == 1 and (imm_val % 4) == 3': 0 + 'ea_align == 3 and (imm_val % 4) == 0': 0 + 'ea_align == 3 and (imm_val % 4) == 1': 0 + 'ea_align == 3 and (imm_val % 4) == 2': 0 + 'ea_align == 3 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + +lw-align: + config: + - check ISA:=regex(.*I.*) + opcode: + lw: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + + +sh-align: + config: + - check ISA:=regex(.*I.*) + opcode: + sh: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + op_comb: + 'rs1 != rs2': 0 + val_comb: + <<: [ *base_rs2val_sgn] + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'ea_align == 2 and (imm_val % 4) == 0': 0 + 'ea_align == 2 and (imm_val % 4) == 1': 0 + 'ea_align == 2 and (imm_val % 4) == 2': 0 + 'ea_align == 2 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + abstract_comb: + <<: [*rs2val_walking] + +sb-align: + config: + - check ISA:=regex(.*I.*) + opcode: + sb: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'ea_align == 2 and (imm_val % 4) == 0': 0 + 'ea_align == 2 and (imm_val % 4) == 1': 0 + 'ea_align == 2 and (imm_val % 4) == 2': 0 + 'ea_align == 2 and (imm_val % 4) == 3': 0 + 'ea_align == 1 and (imm_val % 4) == 0': 0 + 'ea_align == 1 and (imm_val % 4) == 1': 0 + 'ea_align == 1 and (imm_val % 4) == 2': 0 + 'ea_align == 1 and (imm_val % 4) == 3': 0 + 'ea_align == 3 and (imm_val % 4) == 0': 0 + 'ea_align == 3 and (imm_val % 4) == 1': 0 + 'ea_align == 3 and (imm_val % 4) == 2': 0 + 'ea_align == 3 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +sw-align: + config: + - check ISA:=regex(.*I.*) + opcode: + sw: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +auipc: + config: + - check ISA:=regex(.*I.*) + opcode: + auipc: 0 + rd: + <<: *all_regs + val_comb: + 'imm_val == 0': 0 + 'imm_val > 0': 0 + 'imm_val == ((2**20)-1)': 0 + +lui: + config: + - check ISA:=regex(.*I.*) + opcode: + lui: 0 + rd: + <<: *all_regs + val_comb: + 'imm_val == 0': 0 + 'imm_val > 0': 0 + 'imm_val == ((2**20)-1)': 0 + +jal: + config: + - check ISA:=regex(.*I.*) + opcode: + jal: 0 + rd: + <<: *all_regs + val_comb: + 'imm_val < 0' : 0 + 'imm_val > 0': 0 + 'imm_val == (-(2**(18)))': 0 + 'imm_val == ((2**(18)))': 0 + +jalr: + config: + - check ISA:=regex(.*I.*) + opcode: + jalr: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'imm_val > 0': 0 + 'imm_val < 0': 0 + abstract_comb: + <<: *ifmt_immval_walking + +mul: + config: + - check ISA:=regex(.*I.*M.*) + opcode: + mul: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +mulh: + config: + - check ISA:=regex(.*I.*M.*) + opcode: + mulh: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +mulhu: + config: + - check ISA:=regex(.*I.*M.*) + opcode: + mulhu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +mulhsu: + config: + - check ISA:=regex(.*I.*M.*) + opcode: + mulhsu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +div: + config: + - check ISA:=regex(.*I.*M.*) + opcode: + div: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +divu: + config: + - check ISA:=regex(.*I.*M.*) + opcode: + divu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +rem: + config: + - check ISA:=regex(.*I.*M.*) + opcode: + rem: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +remu: + config: + - check ISA:=regex(.*I.*M.*) + opcode: + remu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +lwu-align: + config: + - check ISA:=regex(.*RV64.*I.*) + opcode: + lwu: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + +ld-align: + config: + - check ISA:=regex(.*RV64.*I.*) + opcode: + ld: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 8) == 0': 0 + 'ea_align == 0 and (imm_val % 8) == 1': 0 + 'ea_align == 0 and (imm_val % 8) == 2': 0 + 'ea_align == 0 and (imm_val % 8) == 3': 0 + 'ea_align == 0 and (imm_val % 8) == 4': 0 + 'ea_align == 0 and (imm_val % 8) == 5': 0 + 'ea_align == 0 and (imm_val % 8) == 6': 0 + 'ea_align == 0 and (imm_val % 8) == 7': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + +sd-align: + config: + - check ISA:=regex(.*RV64.*I.*) + opcode: + sd: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'ea_align == 0 and (imm_val % 8) == 0': 0 + 'ea_align == 0 and (imm_val % 8) == 1': 0 + 'ea_align == 0 and (imm_val % 8) == 2': 0 + 'ea_align == 0 and (imm_val % 8) == 3': 0 + 'ea_align == 0 and (imm_val % 8) == 4': 0 + 'ea_align == 0 and (imm_val % 8) == 5': 0 + 'ea_align == 0 and (imm_val % 8) == 6': 0 + 'ea_align == 0 and (imm_val % 8) == 7': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +addiw: + config: + - check ISA:=regex(.*RV64.*I.*) + opcode: + addiw: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + <<: [*rs1val_walking, *ifmt_immval_walking] + +slliw: + config: + - check ISA:=regex(.*RV64.*I.*) + opcode: + slliw: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: *ifmt_base_shift_32w + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("imm_val", 5, False)': 0 + 'walking_zeros("imm_val", 5, False)': 0 + 'alternate("imm_val", 5, False)': 0 + +srliw: + config: + - check ISA:=regex(.*RV64.*I.*) + opcode: + srliw: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: *ifmt_base_shift_32w + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("imm_val", 5, False)': 0 + 'walking_zeros("imm_val", 5, False)': 0 + 'alternate("imm_val", 5, False)': 0 + +sraiw: + config: + - check ISA:=regex(.*RV64.*I.*) + opcode: + sraiw: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: *ifmt_base_shift_32w + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("imm_val", 5, False)': 0 + 'walking_zeros("imm_val", 5, False)': 0 + 'alternate("imm_val", 5, False)': 0 + +addw: + config: + - check ISA:=regex(.*RV64.*I.*) + opcode: + addw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +subw: + config: + - check ISA:=regex(.*RV64.*I.*) + opcode: + subw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +sllw: + config: + - check ISA:=regex(.*RV64.*I.*) + opcode: + sllw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: *rfmt_base_shift + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("rs2_val", 5, False)': 0 + 'walking_zeros("rs2_val", 5, False)': 0 + 'alternate("rs2_val", 5, False)': 0 + +srlw: + config: + - check ISA:=regex(.*RV64.*I.*) + opcode: + srlw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: *rfmt_base_shift + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("rs2_val", 5, False)': 0 + 'walking_zeros("rs2_val", 5, False)': 0 + 'alternate("rs2_val", 5, False)': 0 +sraw: + config: + - check ISA:=regex(.*RV64.*I.*) + opcode: + sraw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: *rfmt_base_shift + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("rs2_val", 5, False)': 0 + 'walking_zeros("rs2_val", 5, False)': 0 + 'alternate("rs2_val", 5, False)': 0 + +mulw: + config: + - check ISA:=regex(.*RV64.*I.*M.*) + opcode: + mulw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +divw: + config: + - check ISA:=regex(.*RV64.*I.*M.*) + opcode: + divw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +divuw: + config: + - check ISA:=regex(.*RV64.*I.*M.*) + opcode: + divuw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +remw: + config: + - check ISA:=regex(.*RV64.*I.*M.*) + opcode: + remw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +remuw: + config: + - check ISA:=regex(.*RV64.*I.*M.*) + opcode: + remuw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/coverpoints.yaml b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/coverpoints.yaml new file mode 100644 index 000000000..6472b78d8 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/coverpoints.yaml @@ -0,0 +1,1915 @@ +# For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore + +datasets: + all_regs: &all_regs + x0: 0 + x1: 0 + x2: 0 + x3: 0 + x4: 0 + x5: 0 + x6: 0 + x7: 0 + x8: 0 + x9: 0 + x10: 0 + x11: 0 + x12: 0 + x13: 0 + x14: 0 + x15: 0 + x16: 0 + x17: 0 + x18: 0 + x19: 0 + x20: 0 + x21: 0 + x22: 0 + x23: 0 + x24: 0 + x25: 0 + x26: 0 + x27: 0 + x28: 0 + x29: 0 + x30: 0 + x31: 0 + + c_regs: &c_regs + x8: 0 + x9: 0 + x10: 0 + x11: 0 + x12: 0 + x13: 0 + x14: 0 + x15: 0 + + all_regs_mx0: &all_regs_mx0 + x1: 0 + x2: 0 + x3: 0 + x4: 0 + x5: 0 + x6: 0 + x7: 0 + x8: 0 + x9: 0 + x10: 0 + x11: 0 + x12: 0 + x13: 0 + x14: 0 + x15: 0 + x16: 0 + x17: 0 + x18: 0 + x19: 0 + x20: 0 + x21: 0 + x22: 0 + x23: 0 + x24: 0 + x25: 0 + x26: 0 + x27: 0 + x28: 0 + x29: 0 + x30: 0 + x31: 0 + + cbfmt_immval_sgn: &cbfmt_immval_sgn + 'imm_val == (-2**(6-1))': 0 + 'imm_val == 0': 0 + 'imm_val == (2**(6-1)-1)': 0 + 'imm_val == 1': 0 + + rfmt_op_comb: &rfmt_op_comb + 'rs1 == rs2 != rd': 0 + 'rs1 == rd != rs2': 0 + 'rs2 == rd != rs1': 0 + 'rs1 == rs2 == rd': 0 + 'rs1 != rs2 and rs1 != rd and rs2 != rd': 0 + + ifmt_op_comb: &ifmt_op_comb + 'rs1 == rd': 0 + 'rs1 != rd': 0 + + sfmt_op_comb: &sfmt_op_comb + 'rs1 == rs2': 0 + 'rs1 != rs2': 0 + + base_rs1val_sgn: &base_rs1val_sgn + 'rs1_val == (-2**(xlen-1))': 0 + 'rs1_val == 0': 0 + 'rs1_val == (2**(xlen-1)-1)': 0 + 'rs1_val == 1': 0 + + base_rs2val_sgn: &base_rs2val_sgn + 'rs2_val == (-2**(xlen-1))': 0 + 'rs2_val == 0': 0 + 'rs2_val == (2**(xlen-1)-1)': 0 + 'rs2_val == 1': 0 + + base_rs1val_unsgn: &base_rs1val_unsgn + 'rs1_val == 0': 0 + 'rs1_val == (2**(xlen)-1)': 0 + 'rs1_val == 1': 0 + + base_rs2val_unsgn: &base_rs2val_unsgn + 'rs2_val == 0': 0 + 'rs2_val == (2**(xlen)-1)': 0 + 'rs2_val == 1': 0 + + rfmt_val_comb_sgn: &rfmt_val_comb_sgn + 'rs1_val > 0 and rs2_val > 0': 0 + 'rs1_val > 0 and rs2_val < 0': 0 + 'rs1_val < 0 and rs2_val < 0': 0 + 'rs1_val < 0 and rs2_val > 0': 0 + 'rs1_val == rs2_val': 0 + 'rs1_val != rs2_val': 0 + + rfmt_val_comb_unsgn: &rfmt_val_comb_unsgn + 'rs1_val > 0 and rs2_val > 0': 0 + 'rs1_val == rs2_val and rs1_val > 0 and rs2_val > 0': 0 + 'rs1_val != rs2_val and rs1_val > 0 and rs2_val > 0': 0 + + ifmt_val_comb_sgn: &ifmt_val_comb_sgn + 'rs1_val == imm_val': 0 + 'rs1_val != imm_val': 0 + 'rs1_val > 0 and imm_val > 0': 0 + 'rs1_val > 0 and imm_val < 0': 0 + 'rs1_val < 0 and imm_val > 0': 0 + 'rs1_val < 0 and imm_val < 0': 0 + + ifmt_val_comb_unsgn: &ifmt_val_comb_unsgn + 'rs1_val == imm_val and rs1_val > 0 and imm_val > 0': 0 + 'rs1_val != imm_val and rs1_val > 0 and imm_val > 0': 0 + + ifmt_base_immval_sgn: &ifmt_base_immval_sgn + 'imm_val == (-2**(12-1))': 0 + 'imm_val == 0': 0 + 'imm_val == (2**(12-1)-1)': 0 + 'imm_val == 1': 0 + + ifmt_base_immval_unsgn: &ifmt_base_immval_unsgn + 'imm_val == 0': 0 + 'imm_val == (2**(12)-1)': 0 + 'imm_val == 1': 0 + + ifmt_base_shift: &ifmt_base_shift + 'rs1_val < 0 and imm_val > 0 and imm_val < xlen': 0 + 'rs1_val > 0 and imm_val > 0 and imm_val < xlen': 0 + 'rs1_val < 0 and imm_val == 0': 0 + 'rs1_val > 0 and imm_val == 0': 0 + 'rs1_val < 0 and imm_val == (xlen-1)': 0 + 'rs1_val > 0 and imm_val == (xlen-1)': 0 + 'rs1_val == imm_val and imm_val > 0 and imm_val < xlen': 0 + 'rs1_val == (-2**(xlen-1)) and imm_val >= 0 and imm_val < xlen': 0 + 'rs1_val == 0 and imm_val >= 0 and imm_val < xlen': 0 + 'rs1_val == (2**(xlen-1)-1) and imm_val >= 0 and imm_val < xlen': 0 + 'rs1_val == 1 and imm_val >= 0 and imm_val < xlen': 0 + + ifmt_base_shift_32w: &ifmt_base_shift_32w + 'rs1_val < 0 and imm_val > 0 and imm_val < 32': 0 + 'rs1_val > 0 and imm_val > 0 and imm_val < 32': 0 + 'rs1_val < 0 and imm_val == 0': 0 + 'rs1_val > 0 and imm_val == 0': 0 + 'rs1_val < 0 and imm_val == 31': 0 + 'rs1_val > 0 and imm_val == 31': 0 + 'rs1_val == imm_val and imm_val > 0 and imm_val < 32': 0 + 'rs1_val == (-2**(xlen-1)) and imm_val >= 0 and imm_val < 32': 0 + 'rs1_val == 0 and imm_val >= 0 and imm_val < 32': 0 + 'rs1_val == (2**(xlen-1)-1) and imm_val >= 0 and imm_val < 32': 0 + 'rs1_val == 1 and imm_val >= 0 and imm_val < 32': 0 + + + rfmt_base_shift: &rfmt_base_shift + 'rs1_val < 0 and rs2_val > 0 and rs2_val < xlen': 0 + 'rs1_val > 0 and rs2_val > 0 and rs2_val < xlen': 0 + 'rs1_val < 0 and rs2_val == 0': 0 + 'rs1_val > 0 and rs2_val == 0': 0 + 'rs1_val == rs2_val and rs2_val > 0 and rs2_val < xlen': 0 + 'rs1_val == (-2**(xlen-1)) and rs2_val >= 0 and rs2_val < xlen': 0 + 'rs1_val == 0 and rs2_val >= 0 and rs2_val < xlen': 0 + 'rs1_val == (2**(xlen-1)-1) and rs2_val >= 0 and rs2_val < xlen': 0 + 'rs1_val == 1 and rs2_val >= 0 and rs2_val < xlen': 0 + + bfmt_base_branch_val_align_sgn: &bfmt_base_branch_val_align_sgn + 'rs1_val > 0 and rs2_val > 0 and imm_val & 0x03 == 0': 0 + 'rs1_val > 0 and rs2_val < 0 and imm_val & 0x03 == 0': 0 + 'rs1_val < 0 and rs2_val < 0 and imm_val & 0x03 == 0': 0 + 'rs1_val < 0 and rs2_val > 0 and imm_val & 0x03 == 0': 0 + 'rs1_val == rs2_val and imm_val > 0 and imm_val & 0x03 == 0': 0 + 'rs1_val == rs2_val and imm_val < 0 and imm_val & 0x03 == 0': 0 + 'rs1_val > rs2_val and imm_val > 0 and imm_val & 0x03 == 0': 0 + 'rs1_val > rs2_val and imm_val < 0 and imm_val & 0x03 == 0': 0 + 'rs1_val < rs2_val and imm_val > 0 and imm_val & 0x03 == 0': 0 + 'rs1_val < rs2_val and imm_val < 0 and imm_val & 0x03 == 0': 0 + + bfmt_base_branch_val_align_unsgn: &bfmt_base_branch_val_align_unsgn + 'rs1_val > 0 and rs2_val > 0': 0 + 'rs1_val > 0 and rs2_val > 0 and rs1_val == rs2_val and imm_val > 0': 0 + 'rs1_val > 0 and rs2_val > 0 and rs1_val == rs2_val and imm_val < 0': 0 + 'rs1_val > 0 and rs2_val > 0 and rs1_val > rs2_val and imm_val > 0 ': 0 + 'rs1_val > 0 and rs2_val > 0 and rs1_val > rs2_val and imm_val < 0 ': 0 + 'rs1_val > 0 and rs2_val > 0 and rs1_val < rs2_val and imm_val > 0 ': 0 + 'rs1_val > 0 and rs2_val > 0 and rs1_val < rs2_val and imm_val < 0 ': 0 + + rs1val_walking: &rs1val_walking + 'walking_ones("rs1_val", xlen)': 0 + 'walking_zeros("rs1_val", xlen)': 0 + 'alternate("rs1_val",xlen)': 0 + + rs2val_walking: &rs2val_walking + 'walking_ones("rs2_val", xlen)': 0 + 'walking_zeros("rs2_val", xlen)': 0 + 'alternate("rs2_val",xlen)': 0 + + rs3val_walking: &rs3val_walking + 'walking_ones("rs3_val", xlen)': 0 + 'walking_zeros("rs3_val", xlen)': 0 + 'alternate("rs3_val",xlen)': 0 + + ifmt_immval_walking: &ifmt_immval_walking + 'walking_ones("imm_val", 12)': 0 + 'walking_zeros("imm_val", 12)': 0 + 'alternate("imm_val",12)': 0 + + rs1val_walking_unsgn: &rs1val_walking_unsgn + 'walking_ones("rs1_val", xlen,False)': 0 + 'walking_zeros("rs1_val", xlen,False)': 0 + 'alternate("rs1_val",xlen,False)': 0 + + rs2val_walking_unsgn: &rs2val_walking_unsgn + 'walking_ones("rs2_val", xlen,False)': 0 + 'walking_zeros("rs2_val", xlen,False)': 0 + 'alternate("rs2_val",xlen,False)': 0 + + crfmt_val_comb_sgn: &crfmt_val_comb_sgn + 'rs2_val > 0': 0 + 'rs2_val < 0': 0 + + cbimm_val_walking: &cbimm_val_walking + 'walking_ones("imm_val", 6)': 0 + 'walking_zeros("imm_val", 6)': 0 + 'alternate("imm_val",6)': 0 + + ifmt_immval_walking_unsgn: &ifmt_immval_walking_unsgn + 'walking_ones("imm_val", 12,False)': 0 + 'walking_zeros("imm_val", 12,False)': 0 + 'alternate("imm_val",12,False)': 0 + +caddi4spn: + config: check ISA:=regex(.*I.*C.*) + opcode: + c.addi4spn: 0 + rd: + <<: *c_regs + val_comb: + 'imm_val > 0' : 0 + 'imm_val == 1020': 0 + abstract_comb: + 'walking_ones("imm_val", 8,False,scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val", 8,False,scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",8,False,scale_func = lambda x: x*4)': 0 + +clw: + config: check ISA:=regex(.*I.*C.*) + opcode: + c.lw: 0 + rs1: + <<: *c_regs + rd: + <<: *c_regs + op_comb: + 'rs1 == rd': 0 + 'rs1 != rd': 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0 + +cld: + config: check ISA:=regex(.*RV64.*I.*C.*) + opcode: + c.ld: 0 + rs1: + <<: *c_regs + rd: + <<: *c_regs + op_comb: + 'rs1 == rd': 0 + 'rs1 != rd': 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 + +csw: + config: check ISA:=regex(.*I.*C.*) + opcode: + c.sw: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0 + +csd: + config: check ISA:=regex(.*RV64.*I.*C.*) + opcode: + c.sd: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 + +cnop: + config: check ISA:=regex(.*I.*C.*) + opcode: + c.nop: 0 + val_comb: + abstract_comb: + <<: *cbimm_val_walking + +caddi: + config: check ISA:=regex(.*I.*C.*) + opcode: + c.addi: 0 + rd: + <<: *all_regs_mx0 + val_comb: + <<: [*base_rs1val_sgn, *cbfmt_immval_sgn, *ifmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *cbimm_val_walking] + +cjal: + config: check ISA:=regex(.*RV32.*I.*C.*) + opcode: + c.jal: 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val < 0': 0 + abstract_comb: + 'walking_ones("imm_val", 11,fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030),scale_func = lambda x: x*2)': 0 + 'walking_zeros("imm_val", 11,fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030),scale_func = lambda x: x*2)': 0 + 'alternate("imm_val",11, fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030) ,scale_func = lambda x: x*2)': 0 + +caddiw: + config: check ISA:=regex(.*RV64.*I.*C.*) + opcode: + c.addiw: 0 + rd: + <<: *all_regs_mx0 + val_comb: + 'rs1_val == (-2**(xlen-1))': 0 + 'rs1_val == 0': 0 + 'rs1_val == (2**(xlen-1)-1)': 0 + 'rs1_val == 1': 0 + <<: [*cbfmt_immval_sgn, *ifmt_val_comb_sgn] + abstract_comb: + 'walking_ones("rs1_val", xlen)': 0 + 'walking_zeros("rs1_val", xlen)': 0 + 'alternate("rs1_val",xlen)': 0 + <<: [*cbimm_val_walking] + +cli: + config: check ISA:=regex(.*I.*C.*) + opcode: + c.li: 0 + rd: + <<: *all_regs + val_comb: + <<: [*cbfmt_immval_sgn] + abstract_comb: + 'walking_ones("imm_val", 6)': 0 + 'walking_zeros("imm_val", 6)': 0 + 'alternate("imm_val", 6)': 0 + +caddi16sp: + config: check ISA:=regex(.*I.*C.*) + opcode: + c.addi16sp: 0 + rd: + x2: 0 + val_comb: + <<: [*base_rs1val_sgn,*ifmt_val_comb_sgn] + 'imm_val == -512': 0 + 'imm_val == 496': 0 + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("imm_val", 6,True,scale_func = lambda x: x*16)': 0 + 'walking_zeros("imm_val", 6,True,scale_func = lambda x: x*16)': 0 + 'alternate("imm_val",6,True,scale_func = lambda x: x*16)': 0 + +clui: + config: check ISA:=regex(.*I.*C.*) + opcode: + c.lui: 0 + rd: + x0: 0 + x1: 0 + x3: 0 + x4: 0 + x5: 0 + x6: 0 + x7: 0 + x8: 0 + x9: 0 + x10: 0 + x11: 0 + x12: 0 + x13: 0 + x14: 0 + x15: 0 + x16: 0 + x17: 0 + x18: 0 + x19: 0 + x20: 0 + x21: 0 + x22: 0 + x23: 0 + x24: 0 + x25: 0 + x26: 0 + x27: 0 + x28: 0 + x29: 0 + x30: 0 + x31: 0 + + val_comb: + 'rs1_val > 0 and imm_val > 32': 0 + 'rs1_val > 0 and imm_val < 32 and imm_val !=0 ': 0 + 'rs1_val < 0 and imm_val > 32': 0 + 'rs1_val < 0 and imm_val < 32 and imm_val !=0 ': 0 + abstract_comb: + 'walking_ones("imm_val", 6, False)': 0 + 'walking_zeros("imm_val", 6, False)': 0 + 'alternate("imm_val", 6, False)': 0 + +csrli: + config: check ISA:=regex(.*I.*C.*) + opcode: + c.srli: 0 + rs1: + <<: *c_regs + val_comb: + 'rs1_val < 0 and imm_val < xlen': 0 + 'rs1_val > 0 and imm_val < xlen': 0 + 'rs1_val == imm_val and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == 0 and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == 1 and imm_val != 0 and imm_val < xlen': 0 + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 + 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 + +csrai: + config: check ISA:=regex(.*I.*C.*) + opcode: + c.srai: 0 + rs1: + <<: *c_regs + val_comb: + 'rs1_val < 0 and imm_val < xlen': 0 + 'rs1_val > 0 and imm_val < xlen': 0 + 'rs1_val == imm_val and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == 0 and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == 1 and imm_val != 0 and imm_val < xlen': 0 + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 + 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 + +candi: + config: check ISA:=regex(.*I.*C.*) + opcode: + c.andi: 0 + rs1: + <<: *c_regs + val_comb: + <<: [*base_rs1val_sgn,*cbfmt_immval_sgn,*ifmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *cbimm_val_walking] + +csub: + config: check ISA:=regex(.*I.*C.*) + opcode: + c.sub: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn, *base_rs2val_sgn] + abstract_comb: + <<: [*rs1val_walking,*rs2val_walking] + +cxor: + config: check ISA:=regex(.*I.*C.*) + opcode: + c.xor: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn, *base_rs2val_sgn] + abstract_comb: + <<: [*rs1val_walking,*rs2val_walking] + +cor: + config: check ISA:=regex(.*I.*C.*) + opcode: + c.or: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn,*base_rs2val_sgn] + abstract_comb: + <<: [*rs1val_walking,*rs2val_walking] + +cand: + config: check ISA:=regex(.*I.*C.*) + opcode: + c.and: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn,*base_rs2val_sgn] + abstract_comb: + <<: [*rs1val_walking,*rs2val_walking] + +csubw: + config: check ISA:=regex(.*RV64.*I.*C.*) + opcode: + c.subw: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn, *base_rs2val_sgn] + abstract_comb: + <<: [*rs1val_walking,*rs2val_walking] + +caddw: + config: check ISA:=regex(.*RV64.*I.*C.*) + opcode: + c.addw: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn, *base_rs2val_sgn] + abstract_comb: + <<: [*rs1val_walking,*rs2val_walking] + +cj: + config: check ISA:=regex(.*I.*C.*) + opcode: + c.j: 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val < 0': 0 + abstract_comb: + 'walking_ones("imm_val", 11,fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030),scale_func = lambda x: x*2)': 0 + 'walking_zeros("imm_val", 11,fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030),scale_func = lambda x: x*2)': 0 + 'alternate("imm_val",11, fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030) ,scale_func = lambda x: x*2)': 0 + +cbeqz: + config: check ISA:=regex(.*I.*C.*) + opcode: + c.beqz: 0 + rs1: + <<: *c_regs + val_comb: + 'rs1_val > 0 and imm_val > 0': 0 + 'rs1_val < 0 and imm_val > 0': 0 + 'rs1_val == 0 and imm_val > 0': 0 + 'rs1_val > 0 and imm_val < 0': 0 + 'rs1_val < 0 and imm_val < 0': 0 + 'rs1_val == 0 and imm_val < 0': 0 + <<: [*base_rs1val_sgn] + abstract_comb: + <<: [*rs1val_walking] + +cbnez: + config: check ISA:=regex(.*I.*C.*) + opcode: + c.bnez: 0 + rs1: + <<: *c_regs + val_comb: + 'rs1_val > 0 and imm_val > 0': 0 + 'rs1_val < 0 and imm_val > 0': 0 + 'rs1_val == 0 and imm_val > 0': 0 + 'rs1_val > 0 and imm_val < 0': 0 + 'rs1_val < 0 and imm_val < 0': 0 + 'rs1_val == 0 and imm_val < 0': 0 + <<: [*base_rs1val_sgn] + abstract_comb: + <<: [*rs1val_walking] + +cslli: + config: check ISA:=regex(.*I.*C.*) + opcode: + c.slli: 0 + rd: + <<: *c_regs + val_comb: + 'rs1_val < 0 and imm_val < xlen': 0 + 'rs1_val > 0 and imm_val < xlen': 0 + 'rs1_val == imm_val and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == 0 and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == 1 and imm_val != 0 and imm_val < xlen': 0 + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 + 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 + +clwsp: + config: check ISA:=regex(.*I.*C.*) + opcode: + c.lwsp: 0 + rd: + <<: *all_regs_mx0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0 + +cldsp: + config: check ISA:=regex(.*RV64.*I.*C.*) + opcode: + c.ldsp: 0 + rd: + <<: *all_regs_mx0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 + +cjr: + config: check ISA:=regex(.*I.*C.*) + opcode: + c.jr: 0 + rs1: + <<: *all_regs_mx0 + +cmv: + config: check ISA:=regex(.*I.*C.*) + opcode: + c.mv: 0 + rs2: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +cadd: + config: check ISA:=regex(.*I.*C.*) + opcode: + c.add: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs_mx0 + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn,*base_rs2val_sgn] + abstract_comb: + <<: [*rs1val_walking,*rs2val_walking] + +cjalr: + config: check ISA:=regex(.*I.*C.*) + opcode: + c.jalr: 0 + rs1: + <<: *all_regs_mx0 + +cswsp: + config: check ISA:=regex(.*I.*C.*) + opcode: + c.swsp: 0 + rs2: + <<: *all_regs + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0 + +csdsp: + config: check ISA:=regex(.*RV64.*I.*C.*) + opcode: + c.sdsp: 0 + rs2: + <<: *all_regs + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 + +addi: + config: check ISA:=regex(.*I.*) + opcode: + addi: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + <<: [*rs1val_walking, *ifmt_immval_walking] + +slti: + config: check ISA:=regex(.*I.*) + opcode: + slti: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] + abstract_comb: + <<: [*rs1val_walking, *ifmt_immval_walking] + +sltiu: + config: check ISA:=regex(.*I.*) + opcode: + sltiu: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [*ifmt_val_comb_unsgn , *base_rs1val_unsgn , *ifmt_base_immval_unsgn] + abstract_comb: + <<: [*rs1val_walking_unsgn, *ifmt_immval_walking_unsgn] + +andi: + config: check ISA:=regex(.*I.*) + opcode: + andi: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] + abstract_comb: + <<: [*rs1val_walking, *ifmt_immval_walking] + +ori: + config: check ISA:=regex(.*I.*) + opcode: + ori: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] + abstract_comb: + <<: [*rs1val_walking, *ifmt_immval_walking] + +xori: + config: check ISA:=regex(.*I.*) + opcode: + xori: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] + abstract_comb: + <<: [*rs1val_walking, *ifmt_immval_walking] + +slli: + config: check ISA:=regex(.*I.*) + opcode: + slli: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: *ifmt_base_shift + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 + 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 + +srai: + config: check ISA:=regex(.*I.*) + opcode: + srai: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: *ifmt_base_shift + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 + 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 + +srli: + config: check ISA:=regex(.*I.*) + opcode: + srli: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: *ifmt_base_shift + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 + 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 + +add: + config: check ISA:=regex(.*I.*) + opcode: + add: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +sub: + config: check ISA:=regex(.*I.*) + opcode: + sub: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +slt: + config: check ISA:=regex(.*I.*) + opcode: + slt: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +sltu: + config: check ISA:=regex(.*I.*) + opcode: + sltu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + +and: + config: check ISA:=regex(.*I.*) + opcode: + and: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +or: + config: check ISA:=regex(.*I.*) + opcode: + or: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +xor: + config: check ISA:=regex(.*I.*) + opcode: + xor: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +sll: + config: check ISA:=regex(.*I.*) + opcode: + sll: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: *rfmt_base_shift + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("rs2_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(xlen,2)), False)': 0 + 'alternate("rs2_val", ceil(log(xlen,2)), False)': 0 + +srl: + config: check ISA:=regex(.*I.*) + opcode: + srl: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: *rfmt_base_shift + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("rs2_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(xlen,2)), False)': 0 + 'alternate("rs2_val", ceil(log(xlen,2)), False)': 0 + +sra: + config: check ISA:=regex(.*I.*) + opcode: + sra: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: *rfmt_base_shift + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("rs2_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(xlen,2)), False)': 0 + 'alternate("rs2_val", ceil(log(xlen,2)), False)': 0 + +beq: + config: check ISA:=regex(.*I.*) + opcode: + beq: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *bfmt_base_branch_val_align_sgn + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +bge: + config: check ISA:=regex(.*I.*) + opcode: + bge: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *bfmt_base_branch_val_align_sgn + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +bgeu: + config: check ISA:=regex(.*I.*) + opcode: + bgeu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *bfmt_base_branch_val_align_unsgn + abstract_comb: + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + +blt: + config: check ISA:=regex(.*I.*) + opcode: + blt: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *bfmt_base_branch_val_align_sgn + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +bltu: + config: check ISA:=regex(.*I.*) + opcode: + bltu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *bfmt_base_branch_val_align_unsgn + abstract_comb: + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + +bne: + config: check ISA:=regex(.*I.*) + opcode: + bne: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *bfmt_base_branch_val_align_sgn + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +lhu-align: + config: check ISA:=regex(.*I.*) + opcode: + lhu: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'ea_align == 2 and (imm_val % 4) == 0': 0 + 'ea_align == 2 and (imm_val % 4) == 1': 0 + 'ea_align == 2 and (imm_val % 4) == 2': 0 + 'ea_align == 2 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + +lh-align: + config: check ISA:=regex(.*I.*) + opcode: + lh: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'ea_align == 2 and (imm_val % 4) == 0': 0 + 'ea_align == 2 and (imm_val % 4) == 1': 0 + 'ea_align == 2 and (imm_val % 4) == 2': 0 + 'ea_align == 2 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + +lbu-align: + config: check ISA:=regex(.*I.*) + opcode: + lbu: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'ea_align == 2 and (imm_val % 4) == 0': 0 + 'ea_align == 2 and (imm_val % 4) == 1': 0 + 'ea_align == 2 and (imm_val % 4) == 2': 0 + 'ea_align == 2 and (imm_val % 4) == 3': 0 + 'ea_align == 1 and (imm_val % 4) == 0': 0 + 'ea_align == 1 and (imm_val % 4) == 1': 0 + 'ea_align == 1 and (imm_val % 4) == 2': 0 + 'ea_align == 1 and (imm_val % 4) == 3': 0 + 'ea_align == 3 and (imm_val % 4) == 0': 0 + 'ea_align == 3 and (imm_val % 4) == 1': 0 + 'ea_align == 3 and (imm_val % 4) == 2': 0 + 'ea_align == 3 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + +lb-align: + config: check ISA:=regex(.*I.*) + opcode: + lb: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'ea_align == 2 and (imm_val % 4) == 0': 0 + 'ea_align == 2 and (imm_val % 4) == 1': 0 + 'ea_align == 2 and (imm_val % 4) == 2': 0 + 'ea_align == 2 and (imm_val % 4) == 3': 0 + 'ea_align == 1 and (imm_val % 4) == 0': 0 + 'ea_align == 1 and (imm_val % 4) == 1': 0 + 'ea_align == 1 and (imm_val % 4) == 2': 0 + 'ea_align == 1 and (imm_val % 4) == 3': 0 + 'ea_align == 3 and (imm_val % 4) == 0': 0 + 'ea_align == 3 and (imm_val % 4) == 1': 0 + 'ea_align == 3 and (imm_val % 4) == 2': 0 + 'ea_align == 3 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + +lw-align: + config: check ISA:=regex(.*I.*) + opcode: + lw: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + + +sh-align: + config: check ISA:=regex(.*I.*) + opcode: + sh: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + op_comb: + 'rs1 != rs2': 0 + val_comb: + <<: [ *base_rs2val_sgn] + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'ea_align == 2 and (imm_val % 4) == 0': 0 + 'ea_align == 2 and (imm_val % 4) == 1': 0 + 'ea_align == 2 and (imm_val % 4) == 2': 0 + 'ea_align == 2 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + abstract_comb: + <<: [*rs2val_walking] + +sb-align: + config: check ISA:=regex(.*I.*) + opcode: + sb: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'ea_align == 2 and (imm_val % 4) == 0': 0 + 'ea_align == 2 and (imm_val % 4) == 1': 0 + 'ea_align == 2 and (imm_val % 4) == 2': 0 + 'ea_align == 2 and (imm_val % 4) == 3': 0 + 'ea_align == 1 and (imm_val % 4) == 0': 0 + 'ea_align == 1 and (imm_val % 4) == 1': 0 + 'ea_align == 1 and (imm_val % 4) == 2': 0 + 'ea_align == 1 and (imm_val % 4) == 3': 0 + 'ea_align == 3 and (imm_val % 4) == 0': 0 + 'ea_align == 3 and (imm_val % 4) == 1': 0 + 'ea_align == 3 and (imm_val % 4) == 2': 0 + 'ea_align == 3 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +sw-align: + config: check ISA:=regex(.*I.*) + opcode: + sw: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +auipc: + config: check ISA:=regex(.*I.*) + opcode: + auipc: 0 + rd: + <<: *all_regs + val_comb: + 'imm_val == 0': 0 + 'imm_val > 0': 0 + 'imm_val == ((2**20)-1)': 0 + +lui: + config: check ISA:=regex(.*I.*) + opcode: + lui: 0 + rd: + <<: *all_regs + val_comb: + 'imm_val == 0': 0 + 'imm_val > 0': 0 + 'imm_val == ((2**20)-1)': 0 + +jal: + config: check ISA:=regex(.*I.*) + opcode: + jal: 0 + rd: + <<: *all_regs + val_comb: + 'imm_val < 0' : 0 + 'imm_val > 0': 0 + 'imm_val == (-(2**(18)))': 0 + 'imm_val == ((2**(18)))': 0 + +jalr: + config: check ISA:=regex(.*I.*) + opcode: + jalr: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'imm_val > 0': 0 + 'imm_val < 0': 0 + abstract_comb: + <<: *ifmt_immval_walking + +mul: + config: check ISA:=regex(.*I.*M.*) + opcode: + mul: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +mulh: + config: check ISA:=regex(.*I.*M.*) + opcode: + mulh: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +mulhu: + config: check ISA:=regex(.*I.*M.*) + opcode: + mulhu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +mulhsu: + config: check ISA:=regex(.*I.*M.*) + opcode: + mulhsu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +div: + config: check ISA:=regex(.*I.*M.*) + opcode: + div: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +divu: + config: check ISA:=regex(.*I.*M.*) + opcode: + divu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +rem: + config: check ISA:=regex(.*I.*M.*) + opcode: + rem: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +remu: + config: check ISA:=regex(.*I.*M.*) + opcode: + remu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +lwu-align: + config: check ISA:=regex(.*RV64.*I.*) + opcode: + lwu: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + +ld-align: + config: check ISA:=regex(.*RV64.*I.*) + opcode: + ld: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 8) == 0': 0 + 'ea_align == 0 and (imm_val % 8) == 1': 0 + 'ea_align == 0 and (imm_val % 8) == 2': 0 + 'ea_align == 0 and (imm_val % 8) == 3': 0 + 'ea_align == 0 and (imm_val % 8) == 4': 0 + 'ea_align == 0 and (imm_val % 8) == 5': 0 + 'ea_align == 0 and (imm_val % 8) == 6': 0 + 'ea_align == 0 and (imm_val % 8) == 7': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + +sd-align: + config: check ISA:=regex(.*RV64.*I.*) + opcode: + sd: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'ea_align == 0 and (imm_val % 8) == 0': 0 + 'ea_align == 0 and (imm_val % 8) == 1': 0 + 'ea_align == 0 and (imm_val % 8) == 2': 0 + 'ea_align == 0 and (imm_val % 8) == 3': 0 + 'ea_align == 0 and (imm_val % 8) == 4': 0 + 'ea_align == 0 and (imm_val % 8) == 5': 0 + 'ea_align == 0 and (imm_val % 8) == 6': 0 + 'ea_align == 0 and (imm_val % 8) == 7': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +addiw: + config: check ISA:=regex(.*RV64.*I.*) + opcode: + addiw: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + <<: [*rs1val_walking, *ifmt_immval_walking] + +slliw: + config: check ISA:=regex(.*RV64.*I.*) + opcode: + slliw: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: *ifmt_base_shift_32w + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("imm_val", 5, False)': 0 + 'walking_zeros("imm_val", 5, False)': 0 + 'alternate("imm_val", 5, False)': 0 + +srliw: + config: check ISA:=regex(.*RV64.*I.*) + opcode: + srliw: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: *ifmt_base_shift_32w + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("imm_val", 5, False)': 0 + 'walking_zeros("imm_val", 5, False)': 0 + 'alternate("imm_val", 5, False)': 0 + +sraiw: + config: check ISA:=regex(.*RV64.*I.*) + opcode: + sraiw: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: *ifmt_base_shift_32w + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("imm_val", 5, False)': 0 + 'walking_zeros("imm_val", 5, False)': 0 + 'alternate("imm_val", 5, False)': 0 + +addw: + config: check ISA:=regex(.*RV64.*I.*) + opcode: + addw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +subw: + config: check ISA:=regex(.*RV64.*I.*) + opcode: + subw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +sllw: + config: check ISA:=regex(.*RV64.*I.*) + opcode: + sllw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: *rfmt_base_shift + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("rs2_val", 5, False)': 0 + 'walking_zeros("rs2_val", 5, False)': 0 + 'alternate("rs2_val", 5, False)': 0 + +srlw: + config: check ISA:=regex(.*RV64.*I.*) + opcode: + srlw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: *rfmt_base_shift + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("rs2_val", 5, False)': 0 + 'walking_zeros("rs2_val", 5, False)': 0 + 'alternate("rs2_val", 5, False)': 0 +sraw: + config: check ISA:=regex(.*RV64.*I.*) + opcode: + sraw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: *rfmt_base_shift + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("rs2_val", 5, False)': 0 + 'walking_zeros("rs2_val", 5, False)': 0 + 'alternate("rs2_val", 5, False)': 0 + +mulw: + config: check ISA:=regex(.*RV64.*I.*M.*) + opcode: + mulw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +divw: + config: check ISA:=regex(.*RV64.*I.*M.*) + opcode: + divw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +divuw: + config: check ISA:=regex(.*RV64.*I.*M.*) + opcode: + divuw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +remw: + config: check ISA:=regex(.*RV64.*I.*M.*) + opcode: + remw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +remuw: + config: check ISA:=regex(.*RV64.*I.*M.*) + opcode: + remuw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/dataset.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/dataset.cgf new file mode 100644 index 000000000..2d3565eaf --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/dataset.cgf @@ -0,0 +1,563 @@ +# For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore + +datasets: + rv32e_regs_mx0: &rv32e_regs_mx0 + x1: 0 + x2: 0 + x3: 0 + x4: 0 + x5: 0 + x6: 0 + x7: 0 + x8: 0 + x9: 0 + x10: 0 + x11: 0 + x12: 0 + x13: 0 + x14: 0 + x15: 0 + + rv32e_regs_mx2: &rv32e_regs_mx2 + x1: 0 + x3: 0 + x4: 0 + x5: 0 + x6: 0 + x7: 0 + x8: 0 + x9: 0 + x10: 0 + x11: 0 + x12: 0 + x13: 0 + x14: 0 + x15: 0 + + rv32e_regs: &rv32e_regs + x0: 0 + x1: 0 + x2: 0 + x3: 0 + x4: 0 + x5: 0 + x6: 0 + x7: 0 + x8: 0 + x9: 0 + x10: 0 + x11: 0 + x12: 0 + x13: 0 + x14: 0 + x15: 0 + + all_regs: &all_regs + x0: 0 + x1: 0 + x2: 0 + x3: 0 + x4: 0 + x5: 0 + x6: 0 + x7: 0 + x8: 0 + x9: 0 + x10: 0 + x11: 0 + x12: 0 + x13: 0 + x14: 0 + x15: 0 + x16: 0 + x17: 0 + x18: 0 + x19: 0 + x20: 0 + x21: 0 + x22: 0 + x23: 0 + x24: 0 + x25: 0 + x26: 0 + x27: 0 + x28: 0 + x29: 0 + x30: 0 + x31: 0 + + all_fregs: &all_fregs + f0: 0 + f1: 0 + f2: 0 + f3: 0 + f4: 0 + f5: 0 + f6: 0 + f7: 0 + f8: 0 + f9: 0 + f10: 0 + f11: 0 + f12: 0 + f13: 0 + f14: 0 + f15: 0 + f16: 0 + f17: 0 + f18: 0 + f19: 0 + f20: 0 + f21: 0 + f22: 0 + f23: 0 + f24: 0 + f25: 0 + f26: 0 + f27: 0 + f28: 0 + f29: 0 + f30: 0 + f31: 0 + + pair_regs: &pair_regs + x2: 0 + x4: 0 + x6: 0 + x8: 0 + x10: 0 + x12: 0 + x14: 0 + x16: 0 + x18: 0 + x20: 0 + x22: 0 + x24: 0 + x26: 0 + x28: 0 + x30: 0 + + c_regs: &c_regs + x8: 0 + x9: 0 + x10: 0 + x11: 0 + x12: 0 + x13: 0 + x14: 0 + x15: 0 + + all_regs_mx2: &all_regs_mx2 + x1: 0 + x3: 0 + x4: 0 + x5: 0 + x6: 0 + x7: 0 + x8: 0 + x9: 0 + x10: 0 + x11: 0 + x12: 0 + x13: 0 + x14: 0 + x15: 0 + x16: 0 + x17: 0 + x18: 0 + x19: 0 + x20: 0 + x21: 0 + x22: 0 + x23: 0 + x24: 0 + x25: 0 + x26: 0 + x27: 0 + x28: 0 + x29: 0 + x30: 0 + x31: 0 + + all_regs_mx0: &all_regs_mx0 + x1: 0 + x2: 0 + x3: 0 + x4: 0 + x5: 0 + x6: 0 + x7: 0 + x8: 0 + x9: 0 + x10: 0 + x11: 0 + x12: 0 + x13: 0 + x14: 0 + x15: 0 + x16: 0 + x17: 0 + x18: 0 + x19: 0 + x20: 0 + x21: 0 + x22: 0 + x23: 0 + x24: 0 + x25: 0 + x26: 0 + x27: 0 + x28: 0 + x29: 0 + x30: 0 + x31: 0 + + cbfmt_immval_sgn: &cbfmt_immval_sgn + 'imm_val == (-2**(6-1))': 0 + 'imm_val == 0': 0 + 'imm_val == (2**(6-1)-1)': 0 + 'imm_val == 1': 0 + + rfmt_op_comb: &rfmt_op_comb + 'rs1 == rs2 != rd': 0 + 'rs1 == rd != rs2': 0 + 'rs2 == rd != rs1': 0 + 'rs1 == rs2 == rd': 0 + 'rs1 != rs2 and rs1 != rd and rs2 != rd': 0 + + div_hardcoded_opcomb: &div_hardcoded_opcomb + 'rs1 == rd != rs2 and rd != "x0"': 0 + 'rs1 == rd != rs2 and rd == "x0"': 0 + 'rs1 == "x0" != rd': 0 + 'rd == "x0" != rs1': 0 + + ramofmt_op_comb: &ramofmt_op_comb + 'rs1 == rd != rs2': 0 + 'rs2 == rd != rs1': 0 + 'rs1 != rs2 and rs1 != rd and rs2 != rd': 0 + + r4fmt_op_comb: &r4fmt_op_comb + 'rs1 == rs2 == rs3 == rd': 0 + 'rs1 == rs2 == rs3 != rd': 0 + 'rs1 == rs2 == rd != rs3': 0 + 'rs1 == rd == rs3 != rs2': 0 + 'rd == rs2 == rs3 != rs1': 0 + 'rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1': 0 + 'rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1': 0 + 'rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1': 0 + 'rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2': 0 + 'rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2': 0 + 'rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3': 0 + 'rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd': 0 + + ifmt_op_comb: &ifmt_op_comb + 'rs1 == rd': 0 + 'rs1 != rd': 0 + + sfmt_op_comb: &sfmt_op_comb + 'rs1 == rs2': 0 + 'rs1 != rs2': 0 + + r0fmt_op_comb: &r0fmt_op_comb + 'rs1 == 0': 0 + 'rs1 != 0': 0 + + base_rs1val_sgn: &base_rs1val_sgn + 'rs1_val == (-2**(xlen-1))': 0 + 'rs1_val == 0': 0 + 'rs1_val == (2**(xlen-1)-1)': 0 + 'rs1_val == 1': 0 + + base_rs1val_sgn_rs2val_zero: &base_rs1val_sgn_rs2val_zero + 'rs1_val == (-2**(xlen-1)) and rs2_val == 0': 0 + 'rs1_val == 0 and rs2_val == 0': 0 + 'rs1_val == (2**(xlen-1)-1) and rs2_val == 0': 0 + 'rs1_val == 1 and rs2_val == 0': 0 + + base_rs2val_sgn: &base_rs2val_sgn + 'rs2_val == (-2**(xlen-1))': 0 + 'rs2_val == 0': 0 + 'rs2_val == (2**(xlen-1)-1)': 0 + 'rs2_val == 1': 0 + + base_rs3val_sgn: &base_rs3val_sgn + 'rs3_val == (-2**(xlen-1))': 0 + 'rs3_val == 0': 0 + 'rs3_val == (2**(xlen-1)-1)': 0 + 'rs3_val == 1': 0 + + + base_rs1val_unsgn: &base_rs1val_unsgn + 'rs1_val == 0': 0 + 'rs1_val == (2**(xlen)-1)': 0 + 'rs1_val == 1': 0 + + base_rs2val_unsgn: &base_rs2val_unsgn + 'rs2_val == 0': 0 + 'rs2_val == (2**(xlen)-1)': 0 + 'rs2_val == 1': 0 + + base_rs3val_unsgn: &base_rs3val_unsgn + 'rs3_val == 0': 0 + 'rs3_val == (2**(xlen)-1)': 0 + 'rs3_val == 1': 0 + + rfmt_val_comb_sgn: &rfmt_val_comb_sgn + 'rs1_val > 0 and rs2_val > 0': 0 + 'rs1_val > 0 and rs2_val < 0': 0 + 'rs1_val < 0 and rs2_val < 0': 0 + 'rs1_val < 0 and rs2_val > 0': 0 + 'rs1_val == rs2_val': 0 + 'rs1_val != rs2_val': 0 + + div_corner_case: &div_corner_case + 'rs1_val == -(2**(xlen-1)) and rs2_val == -0x01': 0 + + rfmt_val_comb_unsgn: &rfmt_val_comb_unsgn + 'rs1_val > 0 and rs2_val > 0': 0 + 'rs1_val == rs2_val and rs1_val > 0 and rs2_val > 0': 0 + 'rs1_val != rs2_val and rs1_val > 0 and rs2_val > 0': 0 + + ifmt_val_comb_sgn: &ifmt_val_comb_sgn + 'rs1_val == imm_val': 0 + 'rs1_val != imm_val': 0 + 'rs1_val > 0 and imm_val > 0': 0 + 'rs1_val > 0 and imm_val < 0': 0 + 'rs1_val < 0 and imm_val > 0': 0 + 'rs1_val < 0 and imm_val < 0': 0 + + ifmt_val_comb_unsgn: &ifmt_val_comb_unsgn + 'rs1_val == imm_val and rs1_val > 0 and imm_val > 0': 0 + 'rs1_val != imm_val and rs1_val > 0 and imm_val > 0': 0 + + ifmt_base_immval_sgn: &ifmt_base_immval_sgn + 'imm_val == (-2**(12-1))': 0 + 'imm_val == 0': 0 + 'imm_val == (2**(12-1)-1)': 0 + 'imm_val == 1': 0 + + ifmt_base_immval_sgn_len: &ifmt_base_immval_sgn_len + 'imm_val == (-2**(ceil(log(xlen,2))-1))': 0 + 'imm_val == 0': 0 + 'imm_val == (2**(ceil(log(xlen,2))-1)-1)': 0 + 'imm_val == 1': 0 + + ifmt_base_immval_unsgn_len_sub_3: &ifmt_base_immval_unsgn_len_sub_3 + 'imm_val == 0': 0 + 'imm_val == (2**(ceil(log(xlen,2))-3)-1)': 0 + 'imm_val == 1': 0 + + ifmt_base_immval_unsgn: &ifmt_base_immval_unsgn + 'imm_val == 0': 0 + 'imm_val == (2**(12)-1)': 0 + 'imm_val == 1': 0 + + ifmt_base_shift: &ifmt_base_shift + 'rs1_val < 0 and imm_val > 0 and imm_val < xlen': 0 + 'rs1_val > 0 and imm_val > 0 and imm_val < xlen': 0 + 'rs1_val < 0 and imm_val == 0': 0 + 'rs1_val > 0 and imm_val == 0': 0 + 'rs1_val < 0 and imm_val == (xlen-1)': 0 + 'rs1_val > 0 and imm_val == (xlen-1)': 0 + 'rs1_val == imm_val and imm_val > 0 and imm_val < xlen': 0 + 'rs1_val == (-2**(xlen-1)) and imm_val >= 0 and imm_val < xlen': 0 + 'rs1_val == 0 and imm_val >= 0 and imm_val < xlen': 0 + 'rs1_val == (2**(xlen-1)-1) and imm_val >= 0 and imm_val < xlen': 0 + 'rs1_val == 1 and imm_val >= 0 and imm_val < xlen': 0 + + ifmt_base_shift_32w: &ifmt_base_shift_32w + 'rs1_val < 0 and imm_val > 0 and imm_val < 32': 0 + 'rs1_val > 0 and imm_val > 0 and imm_val < 32': 0 + 'rs1_val < 0 and imm_val == 0': 0 + 'rs1_val > 0 and imm_val == 0': 0 + 'rs1_val < 0 and imm_val == 31': 0 + 'rs1_val > 0 and imm_val == 31': 0 + 'rs1_val == imm_val and imm_val > 0 and imm_val < 32': 0 + 'rs1_val == (-2**(xlen-1)) and imm_val >= 0 and imm_val < 32': 0 + 'rs1_val == 0 and imm_val >= 0 and imm_val < 32': 0 + 'rs1_val == (2**(xlen-1)-1) and imm_val >= 0 and imm_val < 32': 0 + 'rs1_val == 1 and imm_val >= 0 and imm_val < 32': 0 + + + rfmt_base_shift: &rfmt_base_shift + 'rs1_val < 0 and rs2_val > 0 and rs2_val < xlen': 0 + 'rs1_val > 0 and rs2_val > 0 and rs2_val < xlen': 0 + 'rs1_val < 0 and rs2_val == 0': 0 + 'rs1_val > 0 and rs2_val == 0': 0 + 'rs1_val == rs2_val and rs2_val > 0 and rs2_val < xlen': 0 + 'rs1_val == (-2**(xlen-1)) and rs2_val >= 0 and rs2_val < xlen': 0 + 'rs1_val == 0 and rs2_val >= 0 and rs2_val < xlen': 0 + 'rs1_val == (2**(xlen-1)-1) and rs2_val >= 0 and rs2_val < xlen': 0 + 'rs1_val == 1 and rs2_val >= 0 and rs2_val < xlen': 0 + + bfmt_base_branch_val_align_sgn: &bfmt_base_branch_val_align_sgn + 'rs1_val > 0 and rs2_val > 0 and imm_val & 0x03 == 0': 0 + 'rs1_val > 0 and rs2_val < 0 and imm_val & 0x03 == 0': 0 + 'rs1_val < 0 and rs2_val < 0 and imm_val & 0x03 == 0': 0 + 'rs1_val < 0 and rs2_val > 0 and imm_val & 0x03 == 0': 0 + 'rs1_val == rs2_val and imm_val > 0 and imm_val & 0x03 == 0': 0 + 'rs1_val == rs2_val and imm_val < 0 and imm_val & 0x03 == 0': 0 + 'rs1_val > rs2_val and imm_val > 0 and imm_val & 0x03 == 0': 0 + 'rs1_val > rs2_val and imm_val < 0 and imm_val & 0x03 == 0': 0 + 'rs1_val < rs2_val and imm_val > 0 and imm_val & 0x03 == 0': 0 + 'rs1_val < rs2_val and imm_val < 0 and imm_val & 0x03 == 0': 0 + + bfmt_base_branch_val_align_unsgn: &bfmt_base_branch_val_align_unsgn + 'rs1_val > 0 and rs2_val > 0': 0 + 'rs1_val > 0 and rs2_val > 0 and rs1_val == rs2_val and imm_val > 0': 0 + 'rs1_val > 0 and rs2_val > 0 and rs1_val == rs2_val and imm_val < 0': 0 + 'rs1_val > 0 and rs2_val > 0 and rs1_val > rs2_val and imm_val > 0 ': 0 + 'rs1_val > 0 and rs2_val > 0 and rs1_val > rs2_val and imm_val < 0 ': 0 + 'rs1_val > 0 and rs2_val > 0 and rs1_val < rs2_val and imm_val > 0 ': 0 + 'rs1_val > 0 and rs2_val > 0 and rs1_val < rs2_val and imm_val < 0 ': 0 + + rs1val_walking: &rs1val_walking + 'walking_ones("rs1_val", xlen)': 0 + 'walking_zeros("rs1_val", xlen)': 0 + 'alternate("rs1_val",xlen)': 0 + + rs2val_walking: &rs2val_walking + 'walking_ones("rs2_val", xlen)': 0 + 'walking_zeros("rs2_val", xlen)': 0 + 'alternate("rs2_val",xlen)': 0 + + rs3val_walking: &rs3val_walking + 'walking_ones("rs3_val", xlen)': 0 + 'walking_zeros("rs3_val", xlen)': 0 + 'alternate("rs3_val",xlen)': 0 + + ifmt_immval_walking: &ifmt_immval_walking + 'walking_ones("imm_val", 12)': 0 + 'walking_zeros("imm_val", 12)': 0 + 'alternate("imm_val",12)': 0 + + ifmt_immval_walking_len: &ifmt_immval_walking_len + 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 + 'alternate("imm_val",ceil(log(xlen,2)), False)': 0 + + ifmt_immval_walking_len_sub_3: &ifmt_immval_walking_len_sub_3 + 'walking_ones("imm_val", ceil(log(xlen,2))-3, False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2))-3, False)': 0 + 'alternate("imm_val", ceil(log(xlen,2))-3, False)': 0 + + + ifmt_immval_walking_5u: &ifmt_immval_walking_5u + 'walking_ones("imm_val", 5, False)': 0 + 'walking_zeros("imm_val", 5, False)': 0 + 'alternate("imm_val", 5, False)': 0 + + rs1val_walking_unsgn: &rs1val_walking_unsgn + 'walking_ones("rs1_val", xlen,False)': 0 + 'walking_zeros("rs1_val", xlen,False)': 0 + 'alternate("rs1_val",xlen,False)': 0 + + rs2val_walking_unsgn: &rs2val_walking_unsgn + 'walking_ones("rs2_val", xlen,False)': 0 + 'walking_zeros("rs2_val", xlen,False)': 0 + 'alternate("rs2_val",xlen,False)': 0 + + crfmt_val_comb_sgn: &crfmt_val_comb_sgn + 'rs2_val > 0': 0 + 'rs2_val < 0': 0 + + cbimm_val_walking: &cbimm_val_walking + 'walking_ones("imm_val", 6)': 0 + 'walking_zeros("imm_val", 6)': 0 + 'alternate("imm_val",6)': 0 + + ifmt_immval_walking_unsgn: &ifmt_immval_walking_unsgn + 'walking_ones("imm_val", 12,False)': 0 + 'walking_zeros("imm_val", 12,False)': 0 + 'alternate("imm_val",12,False)': 0 + + rvp64_rs1val_sgn: &rvp64_rs1val_sgn + 'rs1_val == (-2**63)': 0 + 'rs1_val == 0': 0 + 'rs1_val == (2**63-1)': 0 + 'rs1_val == 1': 0 + + rvp64_rs2val_sgn: &rvp64_rs2val_sgn + 'rs2_val == (-2**63)': 0 + 'rs2_val == 0': 0 + 'rs2_val == (2**63-1)': 0 + 'rs2_val == 1': 0 + + rvp64_rs1val_unsgn: &rvp64_rs1val_unsgn + 'rs1_val == 0': 0 + 'rs1_val == (2**64-1)': 0 + 'rs1_val == 1': 0 + + rvp64_rs2val_unsgn: &rvp64_rs2val_unsgn + 'rs2_val == 0': 0 + 'rs2_val == (2**64-1)': 0 + 'rs2_val == 1': 0 + + rvp64_rs1val_walking_sgn: &rvp64_rs1val_walking_sgn + 'walking_ones("rs1_val", 64)': 0 + 'walking_zeros("rs1_val", 64)': 0 + 'alternate("rs1_val",64)': 0 + + rvp64_rs2val_walking_sgn: &rvp64_rs2val_walking_sgn + 'walking_ones("rs2_val", 64)': 0 + 'walking_zeros("rs2_val", 64)': 0 + 'alternate("rs2_val",64)': 0 + + rvp64_rs1val_walking_unsgn: &rvp64_rs1val_walking_unsgn + 'walking_ones("rs1_val", 64, signed=False)': 0 + 'walking_zeros("rs1_val", 64, signed=False)': 0 + 'alternate("rs1_val",64, signed=False)': 0 + + rvp64_rs2val_walking_unsgn: &rvp64_rs2val_walking_unsgn + 'walking_ones("rs2_val", 64, signed=False)': 0 + 'walking_zeros("rs2_val", 64, signed=False)': 0 + 'alternate("rs2_val",64, signed=False)': 0 + + rvp128_rs1val_sgn: &rvp128_rs1val_sgn + 'rs1_val == 0': 0 + 'rs1_val == 1': 0 + + rvp128_rs2val_sgn: &rvp128_rs2val_sgn + 'rs2_val == 0': 0 + 'rs2_val == 1': 0 + + rvp128_rs1val_walking_sgn: &rvp128_rs1val_walking_sgn + 'walking_ones("rs1_val", 128)': 0 + 'walking_zeros("rs1_val", 128)': 0 + 'alternate("rs1_val",128)': 0 + + rvp128_rs2val_walking_sgn: &rvp128_rs2val_walking_sgn + 'walking_ones("rs2_val", 128)': 0 + 'walking_zeros("rs2_val", 128)': 0 + 'alternate("rs2_val",128)': 0 + + zacas_op_comb: &zacas_op_comb + 'rs1 != rs2 and rs1 != rd and rs2 != rd': 0 + + zacas_dcas_rs1val_sgn: &zacas_dcas_rs1val_sgn + 'rs1_val == 0': 0 + 'rs1_val == 1': 0 + + zacas_dcas_rs2val_sgn: &zacas_dcas_rs2val_sgn + 'rs2_val == 0': 0 + 'rs2_val == 1': 0 + + zacas128_rs1val_walking_sgn: &zacas128_rs1val_walking_sgn + 'walking_ones("rs1_val", 128)': 0 + 'walking_zeros("rs1_val", 128)': 0 + 'alternate("rs1_val",128)': 0 + + zacas128_rs2val_walking_sgn: &zacas128_rs2val_walking_sgn + 'walking_ones("rs2_val", 128)': 0 + 'walking_zeros("rs2_val", 128)': 0 + 'alternate("rs2_val",128)': 0 + + zacas64_rs1val_walking_sgn: &zacas64_rs1val_walking_sgn + 'walking_ones("rs1_val", 64)': 0 + 'walking_zeros("rs1_val", 64)': 0 + 'alternate("rs1_val",64)': 0 + + zacas64_rs2val_walking_sgn: &zacas64_rs2val_walking_sgn + 'walking_ones("rs2_val", 64)': 0 + 'walking_zeros("rs2_val", 64)': 0 + 'alternate("rs2_val",64)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32e.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32e.cgf new file mode 100644 index 000000000..31b4c8af7 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32e.cgf @@ -0,0 +1,752 @@ +# For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore + +fence: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + fence: 0 + +addi: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + addi: 0 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +slti: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + slti: 0 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +sltiu: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + sltiu: 0 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [*ifmt_val_comb_unsgn , *base_rs1val_unsgn , *ifmt_base_immval_unsgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)],signed=False)': 0 + <<: [*rs1val_walking_unsgn, *ifmt_immval_walking_unsgn] + +andi: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + andi: 0 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +ori: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + ori: 0 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +xori: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + xori: 0 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +slli: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + slli: 0 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: *ifmt_base_shift + abstract_comb: + 'sp_dataset(xlen,["rs1_val"])': 0 + <<: [*rs1val_walking] + 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 + 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 + +srai: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + srai: 0 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: *ifmt_base_shift + abstract_comb: + 'sp_dataset(xlen,["rs1_val"])': 0 + <<: [*rs1val_walking] + 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 + 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 + +srli: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + srli: 0 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: *ifmt_base_shift + abstract_comb: + 'sp_dataset(xlen,["rs1_val"])': 0 + <<: [*rs1val_walking] + 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 + 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 + +add: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + add: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +sub: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + sub: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +slt: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + slt: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +sltu: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + sltu: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'sp_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + +and: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + and: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +or: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + or: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +xor: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + xor: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +sll: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + sll: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: *rfmt_base_shift + abstract_comb: + <<: [*rs1val_walking] + 'sp_dataset(xlen,var_lst=["rs1_val"])': 0 + 'walking_ones("rs2_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(xlen,2)), False)': 0 + 'alternate("rs2_val", ceil(log(xlen,2)), False)': 0 + +srl: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + srl: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: *rfmt_base_shift + abstract_comb: + <<: [*rs1val_walking] + 'sp_dataset(xlen,var_lst=["rs1_val"])': 0 + 'walking_ones("rs2_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(xlen,2)), False)': 0 + 'alternate("rs2_val", ceil(log(xlen,2)), False)': 0 + +sra: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + sra: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: *rfmt_base_shift + abstract_comb: + <<: [*rs1val_walking] + 'sp_dataset(xlen,var_lst=["rs1_val"])': 0 + 'walking_ones("rs2_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(xlen,2)), False)': 0 + 'alternate("rs2_val", ceil(log(xlen,2)), False)': 0 + +beq: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + beq: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *bfmt_base_branch_val_align_sgn + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + 'sp_dataset(xlen)': 0 + +bge: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + bge: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *bfmt_base_branch_val_align_sgn + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + 'sp_dataset(xlen)': 0 + +bgeu: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + bgeu: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *bfmt_base_branch_val_align_unsgn + abstract_comb: + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + 'sp_dataset(xlen,signed=False)': 0 + +blt: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + blt: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *bfmt_base_branch_val_align_sgn + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + 'sp_dataset(xlen)': 0 + +bltu: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + bltu: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *bfmt_base_branch_val_align_unsgn + abstract_comb: + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + 'sp_dataset(xlen,signed=False)': 0 + +bne: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + bne: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *bfmt_base_branch_val_align_sgn + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + 'sp_dataset(xlen)': 0 + +lhu-align: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + lhu: 0 + rs1: + <<: *rv32e_regs_mx0 + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'ea_align == 2 and (imm_val % 4) == 0': 0 + 'ea_align == 2 and (imm_val % 4) == 1': 0 + 'ea_align == 2 and (imm_val % 4) == 2': 0 + 'ea_align == 2 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + +lh-align: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + lh: 0 + rs1: + <<: *rv32e_regs_mx0 + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'ea_align == 2 and (imm_val % 4) == 0': 0 + 'ea_align == 2 and (imm_val % 4) == 1': 0 + 'ea_align == 2 and (imm_val % 4) == 2': 0 + 'ea_align == 2 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + +lbu-align: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + lbu: 0 + rs1: + <<: *rv32e_regs_mx0 + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'ea_align == 2 and (imm_val % 4) == 0': 0 + 'ea_align == 2 and (imm_val % 4) == 1': 0 + 'ea_align == 2 and (imm_val % 4) == 2': 0 + 'ea_align == 2 and (imm_val % 4) == 3': 0 + 'ea_align == 1 and (imm_val % 4) == 0': 0 + 'ea_align == 1 and (imm_val % 4) == 1': 0 + 'ea_align == 1 and (imm_val % 4) == 2': 0 + 'ea_align == 1 and (imm_val % 4) == 3': 0 + 'ea_align == 3 and (imm_val % 4) == 0': 0 + 'ea_align == 3 and (imm_val % 4) == 1': 0 + 'ea_align == 3 and (imm_val % 4) == 2': 0 + 'ea_align == 3 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + +lb-align: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + lb: 0 + rs1: + <<: *rv32e_regs_mx0 + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'ea_align == 2 and (imm_val % 4) == 0': 0 + 'ea_align == 2 and (imm_val % 4) == 1': 0 + 'ea_align == 2 and (imm_val % 4) == 2': 0 + 'ea_align == 2 and (imm_val % 4) == 3': 0 + 'ea_align == 1 and (imm_val % 4) == 0': 0 + 'ea_align == 1 and (imm_val % 4) == 1': 0 + 'ea_align == 1 and (imm_val % 4) == 2': 0 + 'ea_align == 1 and (imm_val % 4) == 3': 0 + 'ea_align == 3 and (imm_val % 4) == 0': 0 + 'ea_align == 3 and (imm_val % 4) == 1': 0 + 'ea_align == 3 and (imm_val % 4) == 2': 0 + 'ea_align == 3 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + +lw-align: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + lw: 0 + rs1: + <<: *rv32e_regs_mx0 + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + + +sh-align: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + sh: 0 + rs1: + <<: *rv32e_regs_mx0 + rs2: + <<: *rv32e_regs + op_comb: + 'rs1 != rs2': 0 + val_comb: + <<: [ *base_rs2val_sgn] + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'ea_align == 2 and (imm_val % 4) == 0': 0 + 'ea_align == 2 and (imm_val % 4) == 1': 0 + 'ea_align == 2 and (imm_val % 4) == 2': 0 + 'ea_align == 2 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + abstract_comb: + <<: [*rs2val_walking] + +sb-align: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + sb: 0 + rs1: + <<: *rv32e_regs_mx0 + rs2: + <<: *rv32e_regs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'ea_align == 2 and (imm_val % 4) == 0': 0 + 'ea_align == 2 and (imm_val % 4) == 1': 0 + 'ea_align == 2 and (imm_val % 4) == 2': 0 + 'ea_align == 2 and (imm_val % 4) == 3': 0 + 'ea_align == 1 and (imm_val % 4) == 0': 0 + 'ea_align == 1 and (imm_val % 4) == 1': 0 + 'ea_align == 1 and (imm_val % 4) == 2': 0 + 'ea_align == 1 and (imm_val % 4) == 3': 0 + 'ea_align == 3 and (imm_val % 4) == 0': 0 + 'ea_align == 3 and (imm_val % 4) == 1': 0 + 'ea_align == 3 and (imm_val % 4) == 2': 0 + 'ea_align == 3 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +sw-align: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + sw: 0 + rs1: + <<: *rv32e_regs_mx0 + rs2: + <<: *rv32e_regs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +auipc: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + auipc: 0 + rd: + <<: *rv32e_regs + val_comb: + 'imm_val == 0': 0 + 'imm_val > 0': 0 + 'imm_val == ((2**20)-1)': 0 + abstract_comb: + 'sp_dataset(20,["imm_val"],signed=False)': 0 + 'walking_ones("imm_val", 20, False)': 0 + 'walking_zeros("imm_val", 20, False)': 0 + 'alternate("imm_val", 20, False)': 0 + +lui: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + lui: 0 + rd: + <<: *rv32e_regs + val_comb: + 'imm_val == 0': 0 + 'imm_val > 0': 0 + 'imm_val == ((2**20)-1)': 0 + abstract_comb: + 'sp_dataset(20,["imm_val"],signed=False)': 0 + 'walking_ones("imm_val", 20, False)': 0 + 'walking_zeros("imm_val", 20, False)': 0 + 'alternate("imm_val", 20, False)': 0 + +jal: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + jal: 0 + rd: + <<: *rv32e_regs + val_comb: + 'imm_val < 0' : 0 + 'imm_val > 0': 0 + 'imm_val == (-(2**(18)))': 0 + 'imm_val == ((2**(18)))': 0 + +jalr: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + jalr: 0 + rs1: + <<: *rv32e_regs_mx0 + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'imm_val > 0': 0 + 'imm_val < 0': 0 + abstract_comb: + <<: *ifmt_immval_walking diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32e_b.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32e_b.cgf new file mode 100644 index 000000000..6ab80eb1f --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32e_b.cgf @@ -0,0 +1,705 @@ +sh1add: + config: + - check ISA:=regex(.*E.*Zba.*) ;def RVTEST_E = True + mnemonics: + sh1add: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'bitmanip_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +sh2add: + config: + - check ISA:=regex(.*E.*Zba.*) ;def RVTEST_E = True + mnemonics: + sh2add: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'bitmanip_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +sh3add: + config: + - check ISA:=regex(.*E.*Zba.*) ;def RVTEST_E = True + mnemonics: + sh3add: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'bitmanip_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +xnor: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zbkb.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zk.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zkn.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zks.*) ;def RVTEST_E = True + mnemonics: + xnor: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'bitmanip_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + +zext.h_32: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + mnemonics: + zext.h: 0 + base_op: pack + p_op_cond: rs2 == x0 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'rs1_val == 0': 0 + 'rs1_val == 0x80': 0 + 'rs1_val == 0xFF80': 0 + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 + 'uniform_random(20, 100, ["rs1_val"], [xlen])': 0 +andn: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zbkb.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zk.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zkn.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zks.*) ;def RVTEST_E = True + mnemonics: + andn: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + 'bitmanip_dataset(xlen,["rs1_val","rs2_val"],False)': 0 + +clz: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + mnemonics: + clz: 0 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + <<: [*rs1val_walking_unsgn] + 'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0 + 'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0 + 'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0 + 'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0 + +ctz: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + mnemonics: + ctz: 0 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + <<: [*rs1val_walking_unsgn] + 'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0 + 'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0 + 'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0 + 'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0 + +cpop: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + mnemonics: + cpop: 0 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + <<: [*rs1val_walking_unsgn] + 'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0 + 'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0 + 'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0 + 'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0 + +max: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + mnemonics: + max: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'bitmanip_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +maxu: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + mnemonics: + maxu: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'bitmanip_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + +min: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + mnemonics: + min: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'bitmanip_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +minu: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + mnemonics: + minu: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'bitmanip_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + +orcb_32: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + mnemonics: + orc.b: 0 + base_op: gorci + p_op_cond: imm_val == 7 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'rs1_val == 0x1020408': 0 + 'rs1_val == 0x2040801': 0 + 'rs1_val == 0x4080102': 0 + 'rs1_val == 0x8010204': 0 + abstract_comb: + <<: [*rs1val_walking_unsgn] + + +orn: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zbkb.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zk.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zkn.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zks.*) ;def RVTEST_E = True + mnemonics: + orn: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'bitmanip_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + +rev8_32: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zbkb.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zk.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zkn.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zks.*) ;def RVTEST_E = True + mnemonics: + rev8: 0 + base_op: grevi + p_op_cond: imm_val == 24 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'rs1_val == 0x1020408': 0 + 'rs1_val == 0x2040801': 0 + 'rs1_val == 0x4080102': 0 + 'rs1_val == 0x8010204': 0 + abstract_comb: + 'leading_ones(32, ["rs1_val"], [32])': 0 + 'trailing_ones(32, ["rs1_val"], [32])': 0 + 'leading_zeros(32, ["rs1_val"], [32])': 0 + 'trailing_zeros(32, ["rs1_val"], [32])': 0 + 'bitmanip_dataset(xlen,["rs1_val"],signed=False)': 0 + +rol: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zbkb.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zk.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zkn.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zks.*) ;def RVTEST_E = True + mnemonics: + rol: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'leading_ones(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'trailing_ones(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'leading_zeros(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'trailing_zeros(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + +ror: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + - check ISA:=regex(.*I.*Zbkb.*) ;def RVTEST_E = True + - check ISA:=regex(.*I.*Zk.*) ;def RVTEST_E = True + - check ISA:=regex(.*I.*Zkn.*) ;def RVTEST_E = True + - check ISA:=regex(.*I.*Zks.*) ;def RVTEST_E = True + mnemonics: + ror: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'leading_ones(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'trailing_ones(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'leading_zeros(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'trailing_zeros(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + +rori: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zbkb.*) ;def RVTEST_E = True + - check ISA:=regex(.*.*Zk.*) ;def RVTEST_E = True + - check ISA:=regex(.*I.*Zkn.*) ;def RVTEST_E = True + - check ISA:=regex(.*I.*Zks.*) ;def RVTEST_E = True + mnemonics: + rori: 0 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'leading_ones(32, ["rs1_val","imm_val"],[32,5])': 0 + 'trailing_ones(32, ["rs1_val","imm_val"],[32,5])': 0 + 'leading_zeros(32, ["rs1_val","imm_val"],[32,5])': 0 + 'trailing_zeros(32, ["rs1_val","imm_val"],[32,5])': 0 + +sext.b: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + mnemonics: + sext.b: 0 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'rs1_val == 0': 0 + 'rs1_val == 0x8000': 0 + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 + 'uniform_random(20, 100, ["rs1_val"], [xlen])': 0 + +sext.h: + config: + - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True + mnemonics: + sext.h: 0 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'rs1_val == 0': 0 + 'rs1_val == 0x80': 0 + 'rs1_val == 0xff80': 0 + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 + 'uniform_random(20, 100, ["rs1_val"], [xlen])': 0 + +clmul: + config: + - check ISA:=regex(.*E.*Zbc.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zbkc.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zk.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zks.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zkn.*) ;def RVTEST_E = True + mnemonics: + clmul: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + 'rs1_val==1 and rs2_val==1': 0 + 'rs1_val==1 and rs2_val==0': 0 + 'rs1_val==1 and rs2_val==0x1000': 0 + 'rs1_val==0 and rs2_val==1': 0 + 'rs1_val==0 and rs2_val==0': 0 + 'rs1_val==0 and rs2_val==0x1000': 0 + abstract_comb: + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + +clmulh: + config: + - check ISA:=regex(.*E.*Zbc.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zbkc.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zk.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zkn.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zks.*) ;def RVTEST_E = True + mnemonics: + clmulh: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + 'rs1_val==1 and rs2_val==1': 0 + 'rs1_val==1 and rs2_val==0': 0 + 'rs1_val==1 and rs2_val==0x1000': 0 + 'rs1_val==0 and rs2_val==1': 0 + 'rs1_val==0 and rs2_val==0': 0 + 'rs1_val==0 and rs2_val==0x1000': 0 + abstract_comb: + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + + +clmulr: + config: + - check ISA:=regex(.*E.*Zbc.*) ;def RVTEST_E = True + mnemonics: + clmulr: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + 'rs1_val==1 and rs2_val==1': 0 + 'rs1_val==1 and rs2_val==0': 0 + 'rs1_val==1 and rs2_val==0x1000': 0 + 'rs1_val==0 and rs2_val==1': 0 + 'rs1_val==0 and rs2_val==0': 0 + 'rs1_val==0 and rs2_val==0x1000': 0 + abstract_comb: + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + +bclr: + config: + - check ISA:=regex(.*E.*Zbs.*) ;def RVTEST_E = True + mnemonics: + bclr: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: +# 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs2_val", xlen )': 0 + 'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0 + 'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0 + 'leading_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'leading_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0 + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + + +bclri: + config: + - check ISA:=regex(.*E.*Zbs.*) ;def RVTEST_E = True + mnemonics: + bclri: 0 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: +# 'xlenlim("rs1_val", xlen)': 0 + 'leading_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'leading_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 + + +bext: + config: + - check ISA:=regex(.*E.*Zbs.*) ;def RVTEST_E = True + mnemonics: + bext: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: +# 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs2_val", xlen )': 0 + 'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0 + 'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0 + 'leading_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'leading_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0 + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + + +bexti: + config: + - check ISA:=regex(.*E.*Zbs.*) ;def RVTEST_E = True + mnemonics: + bexti: 0 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: +# 'xlenlim("rs1_val", xlen)': 0 + 'leading_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'leading_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 + + +binv: + config: + - check ISA:=regex(.*E.*Zbs.*) ;def RVTEST_E = True + mnemonics: + binv: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: +# 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs2_val", xlen )': 0 + 'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0 + 'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0 + 'leading_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'leading_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0 + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + + +binvi: + config: + - check ISA:=regex(.*E.*Zbs.*) ;def RVTEST_E = True + mnemonics: + binvi: 0 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: +# 'xlenlim("rs1_val", xlen)': 0 + 'leading_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'leading_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 + +bset: + config: + - check ISA:=regex(.*E.*Zbs.*) ;def RVTEST_E = True + mnemonics: + bset: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: +# 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs2_val", xlen )': 0 + 'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0 + 'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0 + 'leading_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'leading_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0 + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + + +bseti: + config: + - check ISA:=regex(.*E.*Zbs.*) ;def RVTEST_E = True + mnemonics: + bseti: 0 + rs1: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: +# 'xlenlim("rs1_val", xlen)': 0 + 'leading_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'leading_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32e_fencei.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32e_fencei.cgf new file mode 100644 index 000000000..0339821ee --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32e_fencei.cgf @@ -0,0 +1,6 @@ +fencei: + config: + - check ISA:=regex(.*E.*Zifencei.*) ;def RVTEST_E = True + mnemonics: + fence.i: 0 + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32e_priv.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32e_priv.cgf new file mode 100644 index 000000000..129677f1a --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32e_priv.cgf @@ -0,0 +1,146 @@ +misalign-lh: + cond: check ISA:=regex(.*E.*Zicsr.*) ;def RVTEST_E = True + config: + - check ISA:=regex(.*E.*); check hw_data_misaligned_support:=True ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True ;def RVTEST_E = True + mnemonics: + lh: 0 + val_comb: + 'ea_align == 1': 0 + +misalign-lhu: + config: + - check ISA:=regex(.*E.*); check hw_data_misaligned_support:=True ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True ;def RVTEST_E = True + cond: check ISA:=regex(.*E.*Zicsr.*) ;def RVTEST_E = True + mnemonics: + lhu: 0 + val_comb: + 'ea_align == 1': 0 + + +misalign-lw: + config: + - check ISA:=regex(.*E.*); check hw_data_misaligned_support:=True ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True ;def RVTEST_E = True + cond: check ISA:=regex(.*E.*Zicsr.*) ;def RVTEST_E = True + mnemonics: + lw: 0 + val_comb: + 'ea_align == 1': 0 + 'ea_align == 2': 0 + 'ea_align == 3': 0 + +misalign-sh: + config: + - check ISA:=regex(.*E.*); check hw_data_misaligned_support:=True ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True ;def RVTEST_E = True + cond: check ISA:=regex(.*E.*Zicsr.*) ;def RVTEST_E = True + mnemonics: + sh: 0 + val_comb: + 'ea_align == 1': 0 + +misalign-sw: + config: + - check ISA:=regex(.*E.*); check hw_data_misaligned_support:=True ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True ;def RVTEST_E = True + cond: check ISA:=regex(.*E.*Zicsr.*) ;def RVTEST_E = True + mnemonics: + sw: 0 + val_comb: + 'ea_align == 1': 0 + 'ea_align == 2': 0 + 'ea_align == 3': 0 + +misalign2-jalr: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True ;def RVTEST_E = True + cond: check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + jalr: 0 + val_comb: + 'imm_val%2 == 1 and ea_align == 2': 0 + 'imm_val%2 == 0 and ea_align == 2': 0 + +misalign1-jalr: + config: + - check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + jalr: 0 + val_comb: + 'imm_val%2 == 1 and ea_align == 1': 0 + 'imm_val%2 == 0 and ea_align == 1': 0 + +misalign-jal: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True ;def RVTEST_E = True + cond: check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + jal: 0 + val_comb: + 'ea_align == 2': 0 + +misalign-bge: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True ;def RVTEST_E = True + cond: check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + bge: 0 + val_comb: + ' rs1_val>rs2_val and ea_align == 2': 0 + +misalign-bgeu: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True ;def RVTEST_E = True + cond: check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + bgeu: 0 + val_comb: + ' rs1_val>rs2_val and ea_align == 2': 0 + +misalign-blt: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + - check ISA:=regex(.*E.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True ;def RVTEST_E = True + cond: check ISA:=regex(.*E.*) ;def RVTEST_E = True + mnemonics: + blt: 0 + val_comb: + ' rs1_val 0' : 0 + 'imm_val == 1020': 0 + abstract_comb: + 'walking_ones("imm_val", 8,False,scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val", 8,False,scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",8,False,scale_func = lambda x: x*4)': 0 + +clw: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + mnemonics: + c.lw: 0 + rs1: + <<: *c_regs + rd: + <<: *c_regs + op_comb: + 'rs1 == rd': 0 + 'rs1 != rd': 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0 + + +csw: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + mnemonics: + c.sw: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0 + + +cnop: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + mnemonics: + c.nop: 0 + val_comb: + abstract_comb: + <<: *cbimm_val_walking + +caddi: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + mnemonics: + c.addi: 0 + rd: + <<: *rv32e_regs_mx0 + val_comb: + <<: [*base_rs1val_sgn, *cbfmt_immval_sgn, *ifmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",6)])': 0 + <<: [*rs1val_walking, *cbimm_val_walking] + +cjal: + config: + - check ISA:=regex(.*RV32.*E.*C.*) ;def RVTEST_E = True + mnemonics: + c.jal: 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val < 0': 0 + abstract_comb: + 'walking_ones("imm_val", 11,fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030),scale_func = lambda x: x*2)': 0 + 'walking_zeros("imm_val", 11,fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030),scale_func = lambda x: x*2)': 0 + 'alternate("imm_val",11, fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030) ,scale_func = lambda x: x*2)': 0 + +cli: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + mnemonics: + c.li: 0 + rd: + <<: *rv32e_regs + val_comb: + <<: [*cbfmt_immval_sgn] + abstract_comb: + 'walking_ones("imm_val", 6)': 0 + 'walking_zeros("imm_val", 6)': 0 + 'alternate("imm_val", 6)': 0 + +caddi16sp: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + mnemonics: + c.addi16sp: 0 + rd: + x2: 0 + val_comb: + <<: [*base_rs1val_sgn,*ifmt_val_comb_sgn] + 'imm_val == -512': 0 + 'imm_val == 496': 0 + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("imm_val", 6,True,scale_func = lambda x: x*16)': 0 + 'walking_zeros("imm_val", 6,True,scale_func = lambda x: x*16)': 0 + 'alternate("imm_val",6,True,scale_func = lambda x: x*16)': 0 + +clui: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + mnemonics: + c.lui: 0 + rd: + <<: *rv32e_regs_mx2 + val_comb: + 'rs1_val > 0 and imm_val > 32': 0 + 'rs1_val > 0 and imm_val < 32 and imm_val !=0 ': 0 + 'rs1_val < 0 and imm_val > 32': 0 + 'rs1_val < 0 and imm_val < 32 and imm_val !=0 ': 0 + abstract_comb: + 'walking_ones("imm_val", 6, False)': 0 + 'walking_zeros("imm_val", 6, False)': 0 + 'alternate("imm_val", 6, False)': 0 + +csrli: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + mnemonics: + c.srli: 0 + rs1: + <<: *c_regs + val_comb: + 'rs1_val < 0 and imm_val < xlen': 0 + 'rs1_val > 0 and imm_val < xlen': 0 + 'rs1_val == imm_val and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == 0 and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == 1 and imm_val != 0 and imm_val < xlen': 0 + abstract_comb: + 'sp_dataset(xlen,["rs1_val"])': 0 + <<: [*rs1val_walking] + 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 + 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 + +csrai: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + mnemonics: + c.srai: 0 + rs1: + <<: *c_regs + val_comb: + 'rs1_val < 0 and imm_val < xlen': 0 + 'rs1_val > 0 and imm_val < xlen': 0 + 'rs1_val == imm_val and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == 0 and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == 1 and imm_val != 0 and imm_val < xlen': 0 + abstract_comb: + 'sp_dataset(xlen,["rs1_val"])': 0 + <<: [*rs1val_walking] + 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 + 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 + +candi: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + mnemonics: + c.andi: 0 + rs1: + <<: *c_regs + val_comb: + <<: [*base_rs1val_sgn,*cbfmt_immval_sgn,*ifmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",6)])': 0 + <<: [*rs1val_walking, *cbimm_val_walking] + +csub: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + mnemonics: + c.sub: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn, *base_rs2val_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking,*rs2val_walking] + +cxor: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + mnemonics: + c.xor: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn, *base_rs2val_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking,*rs2val_walking] + +cor: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + mnemonics: + c.or: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn,*base_rs2val_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking,*rs2val_walking] + +cand: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + mnemonics: + c.and: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn,*base_rs2val_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking,*rs2val_walking] + + + +cj: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + mnemonics: + c.j: 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val < 0': 0 + abstract_comb: + 'walking_ones("imm_val", 11,fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030),scale_func = lambda x: x*2)': 0 + 'walking_zeros("imm_val", 11,fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030),scale_func = lambda x: x*2)': 0 + 'alternate("imm_val",11, fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030) ,scale_func = lambda x: x*2)': 0 + +cbeqz: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + mnemonics: + c.beqz: 0 + rs1: + <<: *c_regs + val_comb: + 'rs1_val > 0 and imm_val > 0': 0 + 'rs1_val < 0 and imm_val > 0': 0 + 'rs1_val == 0 and imm_val > 0': 0 + 'rs1_val > 0 and imm_val < 0': 0 + 'rs1_val < 0 and imm_val < 0': 0 + 'rs1_val == 0 and imm_val < 0': 0 + <<: [*base_rs1val_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val"])': 0 + <<: [*rs1val_walking] + +cbnez: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + mnemonics: + c.bnez: 0 + rs1: + <<: *c_regs + val_comb: + 'rs1_val > 0 and imm_val > 0': 0 + 'rs1_val < 0 and imm_val > 0': 0 + 'rs1_val == 0 and imm_val > 0': 0 + 'rs1_val > 0 and imm_val < 0': 0 + 'rs1_val < 0 and imm_val < 0': 0 + 'rs1_val == 0 and imm_val < 0': 0 + <<: [*base_rs1val_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val"])': 0 + <<: [*rs1val_walking] + +cslli: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + mnemonics: + c.slli: 0 + rd: + <<: *c_regs + val_comb: + 'rs1_val < 0 and imm_val < xlen': 0 + 'rs1_val > 0 and imm_val < xlen': 0 + 'rs1_val == imm_val and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == 0 and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == 1 and imm_val != 0 and imm_val < xlen': 0 + abstract_comb: + 'sp_dataset(xlen,["rs1_val"])': 0 + <<: [*rs1val_walking] + 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 + 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 + +clwsp: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + mnemonics: + c.lwsp: 0 + rd: + <<: *rv32e_regs_mx0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0 + + +cjr: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + mnemonics: + c.jr: 0 + rs1: + <<: *rv32e_regs_mx0 + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *base_rs1val_sgn_rs2val_zero + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: *rs1val_walking + +cmv: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + mnemonics: + c.mv: 0 + rs2: + <<: *rv32e_regs_mx0 + rd: + <<: *rv32e_regs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs2_val"])': 0 + <<: [*rs2val_walking] + +cadd: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + mnemonics: + c.add: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs_mx0 + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn,*base_rs2val_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking,*rs2val_walking] + +cjalr: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + mnemonics: + c.jalr: 0 + rs1: + <<: *rv32e_regs_mx0 + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *base_rs1val_sgn_rs2val_zero + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: *rs1val_walking + +cswsp: + config: + - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True + mnemonics: + c.swsp: 0 + rs2: + <<: *rv32e_regs_mx2 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32em.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32em.cgf new file mode 100644 index 000000000..0bee96553 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32em.cgf @@ -0,0 +1,154 @@ +# For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore + +mul: + config: + - check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True + mnemonics: + mul: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +mulh: + config: + - check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True + mnemonics: + mulh: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +mulhu: + config: + - check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True + mnemonics: + mulhu: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'sp_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + +mulhsu: + config: + - check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True + mnemonics: + mulhsu: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_unsgn, *rfmt_val_comb_unsgn] + 'rs1_val > 0 and rs2_val > 0': 0 + abstract_comb: + 'sp_dataset(xlen,[("rs1_val",xlen),("rs2_val",xlen,False)])': 0 + <<: [*rs1val_walking, *rs2val_walking_unsgn] + +div: + config: + - check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True + mnemonics: + div: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +divu: + config: + - check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True + mnemonics: + divu: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'sp_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + +rem: + config: + - check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True + mnemonics: + rem: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +remu: + config: + - check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True + mnemonics: + remu: 0 + rs1: + <<: *rv32e_regs + rs2: + <<: *rv32e_regs + rd: + <<: *rv32e_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'sp_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32i.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32i.cgf new file mode 100644 index 000000000..54ce07fb9 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32i.cgf @@ -0,0 +1,752 @@ +# For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore + +fence: + config: + - check ISA:=regex(.*I.*) + mnemonics: + fence: 0 + +addi: + config: + - check ISA:=regex(.*I.*) + mnemonics: + addi: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +slti: + config: + - check ISA:=regex(.*I.*) + mnemonics: + slti: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +sltiu: + config: + - check ISA:=regex(.*I.*) + mnemonics: + sltiu: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [*ifmt_val_comb_unsgn , *base_rs1val_unsgn , *ifmt_base_immval_unsgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)],signed=False)': 0 + <<: [*rs1val_walking_unsgn, *ifmt_immval_walking_unsgn] + +andi: + config: + - check ISA:=regex(.*I.*) + mnemonics: + andi: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +ori: + config: + - check ISA:=regex(.*I.*) + mnemonics: + ori: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +xori: + config: + - check ISA:=regex(.*I.*) + mnemonics: + xori: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +slli: + config: + - check ISA:=regex(.*I.*) + mnemonics: + slli: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: *ifmt_base_shift + abstract_comb: + 'sp_dataset(xlen,["rs1_val"])': 0 + <<: [*rs1val_walking] + 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 + 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 + +srai: + config: + - check ISA:=regex(.*I.*) + mnemonics: + srai: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: *ifmt_base_shift + abstract_comb: + 'sp_dataset(xlen,["rs1_val"])': 0 + <<: [*rs1val_walking] + 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 + 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 + +srli: + config: + - check ISA:=regex(.*I.*) + mnemonics: + srli: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: *ifmt_base_shift + abstract_comb: + 'sp_dataset(xlen,["rs1_val"])': 0 + <<: [*rs1val_walking] + 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 + 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 + +add: + config: + - check ISA:=regex(.*I.*) + mnemonics: + add: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +sub: + config: + - check ISA:=regex(.*I.*) + mnemonics: + sub: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +slt: + config: + - check ISA:=regex(.*I.*) + mnemonics: + slt: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +sltu: + config: + - check ISA:=regex(.*I.*) + mnemonics: + sltu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'sp_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + +and: + config: + - check ISA:=regex(.*I.*) + mnemonics: + and: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +or: + config: + - check ISA:=regex(.*I.*) + mnemonics: + or: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +xor: + config: + - check ISA:=regex(.*I.*) + mnemonics: + xor: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +sll: + config: + - check ISA:=regex(.*I.*) + mnemonics: + sll: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: *rfmt_base_shift + abstract_comb: + <<: [*rs1val_walking] + 'sp_dataset(xlen,var_lst=["rs1_val"])': 0 + 'walking_ones("rs2_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(xlen,2)), False)': 0 + 'alternate("rs2_val", ceil(log(xlen,2)), False)': 0 + +srl: + config: + - check ISA:=regex(.*I.*) + mnemonics: + srl: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: *rfmt_base_shift + abstract_comb: + <<: [*rs1val_walking] + 'sp_dataset(xlen,var_lst=["rs1_val"])': 0 + 'walking_ones("rs2_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(xlen,2)), False)': 0 + 'alternate("rs2_val", ceil(log(xlen,2)), False)': 0 + +sra: + config: + - check ISA:=regex(.*I.*) + mnemonics: + sra: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: *rfmt_base_shift + abstract_comb: + <<: [*rs1val_walking] + 'sp_dataset(xlen,var_lst=["rs1_val"])': 0 + 'walking_ones("rs2_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(xlen,2)), False)': 0 + 'alternate("rs2_val", ceil(log(xlen,2)), False)': 0 + +beq: + config: + - check ISA:=regex(.*I.*) + mnemonics: + beq: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *bfmt_base_branch_val_align_sgn + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + 'sp_dataset(xlen)': 0 + +bge: + config: + - check ISA:=regex(.*I.*) + mnemonics: + bge: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *bfmt_base_branch_val_align_sgn + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + 'sp_dataset(xlen)': 0 + +bgeu: + config: + - check ISA:=regex(.*I.*) + mnemonics: + bgeu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *bfmt_base_branch_val_align_unsgn + abstract_comb: + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + 'sp_dataset(xlen,signed=False)': 0 + +blt: + config: + - check ISA:=regex(.*I.*) + mnemonics: + blt: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *bfmt_base_branch_val_align_sgn + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + 'sp_dataset(xlen)': 0 + +bltu: + config: + - check ISA:=regex(.*I.*) + mnemonics: + bltu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *bfmt_base_branch_val_align_unsgn + abstract_comb: + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + 'sp_dataset(xlen,signed=False)': 0 + +bne: + config: + - check ISA:=regex(.*I.*) + mnemonics: + bne: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *bfmt_base_branch_val_align_sgn + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + 'sp_dataset(xlen)': 0 + +lhu-align: + config: + - check ISA:=regex(.*I.*) + mnemonics: + lhu: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'ea_align == 2 and (imm_val % 4) == 0': 0 + 'ea_align == 2 and (imm_val % 4) == 1': 0 + 'ea_align == 2 and (imm_val % 4) == 2': 0 + 'ea_align == 2 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + +lh-align: + config: + - check ISA:=regex(.*I.*) + mnemonics: + lh: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'ea_align == 2 and (imm_val % 4) == 0': 0 + 'ea_align == 2 and (imm_val % 4) == 1': 0 + 'ea_align == 2 and (imm_val % 4) == 2': 0 + 'ea_align == 2 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + +lbu-align: + config: + - check ISA:=regex(.*I.*) + mnemonics: + lbu: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'ea_align == 2 and (imm_val % 4) == 0': 0 + 'ea_align == 2 and (imm_val % 4) == 1': 0 + 'ea_align == 2 and (imm_val % 4) == 2': 0 + 'ea_align == 2 and (imm_val % 4) == 3': 0 + 'ea_align == 1 and (imm_val % 4) == 0': 0 + 'ea_align == 1 and (imm_val % 4) == 1': 0 + 'ea_align == 1 and (imm_val % 4) == 2': 0 + 'ea_align == 1 and (imm_val % 4) == 3': 0 + 'ea_align == 3 and (imm_val % 4) == 0': 0 + 'ea_align == 3 and (imm_val % 4) == 1': 0 + 'ea_align == 3 and (imm_val % 4) == 2': 0 + 'ea_align == 3 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + +lb-align: + config: + - check ISA:=regex(.*I.*) + mnemonics: + lb: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'ea_align == 2 and (imm_val % 4) == 0': 0 + 'ea_align == 2 and (imm_val % 4) == 1': 0 + 'ea_align == 2 and (imm_val % 4) == 2': 0 + 'ea_align == 2 and (imm_val % 4) == 3': 0 + 'ea_align == 1 and (imm_val % 4) == 0': 0 + 'ea_align == 1 and (imm_val % 4) == 1': 0 + 'ea_align == 1 and (imm_val % 4) == 2': 0 + 'ea_align == 1 and (imm_val % 4) == 3': 0 + 'ea_align == 3 and (imm_val % 4) == 0': 0 + 'ea_align == 3 and (imm_val % 4) == 1': 0 + 'ea_align == 3 and (imm_val % 4) == 2': 0 + 'ea_align == 3 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + +lw-align: + config: + - check ISA:=regex(.*I.*) + mnemonics: + lw: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + + +sh-align: + config: + - check ISA:=regex(.*I.*) + mnemonics: + sh: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + op_comb: + 'rs1 != rs2': 0 + val_comb: + <<: [ *base_rs2val_sgn] + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'ea_align == 2 and (imm_val % 4) == 0': 0 + 'ea_align == 2 and (imm_val % 4) == 1': 0 + 'ea_align == 2 and (imm_val % 4) == 2': 0 + 'ea_align == 2 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + abstract_comb: + <<: [*rs2val_walking] + +sb-align: + config: + - check ISA:=regex(.*I.*) + mnemonics: + sb: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'ea_align == 2 and (imm_val % 4) == 0': 0 + 'ea_align == 2 and (imm_val % 4) == 1': 0 + 'ea_align == 2 and (imm_val % 4) == 2': 0 + 'ea_align == 2 and (imm_val % 4) == 3': 0 + 'ea_align == 1 and (imm_val % 4) == 0': 0 + 'ea_align == 1 and (imm_val % 4) == 1': 0 + 'ea_align == 1 and (imm_val % 4) == 2': 0 + 'ea_align == 1 and (imm_val % 4) == 3': 0 + 'ea_align == 3 and (imm_val % 4) == 0': 0 + 'ea_align == 3 and (imm_val % 4) == 1': 0 + 'ea_align == 3 and (imm_val % 4) == 2': 0 + 'ea_align == 3 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +sw-align: + config: + - check ISA:=regex(.*I.*) + mnemonics: + sw: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +auipc: + config: + - check ISA:=regex(.*I.*) + mnemonics: + auipc: 0 + rd: + <<: *all_regs + val_comb: + 'imm_val == 0': 0 + 'imm_val > 0': 0 + 'imm_val == ((2**20)-1)': 0 + abstract_comb: + 'sp_dataset(20,["imm_val"],signed=False)': 0 + 'walking_ones("imm_val", 20, False)': 0 + 'walking_zeros("imm_val", 20, False)': 0 + 'alternate("imm_val", 20, False)': 0 + +lui: + config: + - check ISA:=regex(.*I.*) + mnemonics: + lui: 0 + rd: + <<: *all_regs + val_comb: + 'imm_val == 0': 0 + 'imm_val > 0': 0 + 'imm_val == ((2**20)-1)': 0 + abstract_comb: + 'sp_dataset(20,["imm_val"],signed=False)': 0 + 'walking_ones("imm_val", 20, False)': 0 + 'walking_zeros("imm_val", 20, False)': 0 + 'alternate("imm_val", 20, False)': 0 + +jal: + config: + - check ISA:=regex(.*I.*) + mnemonics: + jal: 0 + rd: + <<: *all_regs + val_comb: + 'imm_val < 0' : 0 + 'imm_val > 0': 0 + 'imm_val == (-(2**(18)))': 0 + 'imm_val == ((2**(18)))': 0 + +jalr: + config: + - check ISA:=regex(.*I.*) + mnemonics: + jalr: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'imm_val > 0': 0 + 'imm_val < 0': 0 + abstract_comb: + <<: *ifmt_immval_walking diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32i_b.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32i_b.cgf new file mode 100644 index 000000000..14fe4a017 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32i_b.cgf @@ -0,0 +1,734 @@ +sh1add: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zba.*) + mnemonics: + sh1add: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'bitmanip_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +sh2add: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zba.*) + mnemonics: + sh2add: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'bitmanip_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +sh3add: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zba.*) + mnemonics: + sh3add: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'bitmanip_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +xnor: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + - check ISA:=regex(.*I.*Zbkb.*) + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zks.*) + mnemonics: + xnor: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'bitmanip_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + +zext.h_32: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + mnemonics: + zext.h: 0 + base_op: pack + p_op_cond: rs2 == x0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'rs1_val == 0': 0 + 'rs1_val == 0x80': 0 + 'rs1_val == 0xFF80': 0 + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 + 'uniform_random(20, 100, ["rs1_val"], [xlen])': 0 +andn: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + - check ISA:=regex(.*I.*Zbkb.*) + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zks.*) + mnemonics: + andn: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + 'bitmanip_dataset(xlen,["rs1_val","rs2_val"],False)': 0 + +clz: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + mnemonics: + clz: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + <<: [*rs1val_walking_unsgn] + 'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0 + 'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0 + 'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0 + 'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0 + +ctz: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + mnemonics: + ctz: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + <<: [*rs1val_walking_unsgn] + 'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0 + 'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0 + 'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0 + 'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0 + +cpop: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + mnemonics: + cpop: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + <<: [*rs1val_walking_unsgn] + 'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0 + 'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0 + 'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0 + 'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0 + +max: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + mnemonics: + max: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'bitmanip_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +maxu: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + mnemonics: + maxu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'bitmanip_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + +min: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + mnemonics: + min: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'bitmanip_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +minu: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + mnemonics: + minu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'bitmanip_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + +orcb_32: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + mnemonics: + orc.b: 0 + base_op: gorci + p_op_cond: imm_val == 7 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'rs1_val == 0x1020408': 0 + 'rs1_val == 0x2040801': 0 + 'rs1_val == 0x4080102': 0 + 'rs1_val == 0x8010204': 0 + abstract_comb: + <<: [*rs1val_walking_unsgn] + + +orn: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + - check ISA:=regex(.*I.*Zbkb.*) + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zks.*) + mnemonics: + orn: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'bitmanip_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + +rev8_32: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + - check ISA:=regex(.*I.*Zbkb.*) + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zks.*) + mnemonics: + rev8: 0 + base_op: grevi + p_op_cond: imm_val == 24 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'rs1_val == 0x1020408': 0 + 'rs1_val == 0x2040801': 0 + 'rs1_val == 0x4080102': 0 + 'rs1_val == 0x8010204': 0 + abstract_comb: + 'leading_ones(32, ["rs1_val"], [32])': 0 + 'trailing_ones(32, ["rs1_val"], [32])': 0 + 'leading_zeros(32, ["rs1_val"], [32])': 0 + 'trailing_zeros(32, ["rs1_val"], [32])': 0 + 'bitmanip_dataset(xlen,["rs1_val"],signed=False)': 0 + +rol: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + - check ISA:=regex(.*I.*Zbkb.*) + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zks.*) + mnemonics: + rol: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'leading_ones(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'trailing_ones(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'leading_zeros(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'trailing_zeros(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + +ror: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + - check ISA:=regex(.*I.*Zbkb.*) + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zks.*) + mnemonics: + ror: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'leading_ones(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'trailing_ones(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'leading_zeros(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'trailing_zeros(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + +rori: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + - check ISA:=regex(.*I.*Zbkb.*) + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zks.*) + mnemonics: + rori: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'leading_ones(32, ["rs1_val","imm_val"],[32,5])': 0 + 'trailing_ones(32, ["rs1_val","imm_val"],[32,5])': 0 + 'leading_zeros(32, ["rs1_val","imm_val"],[32,5])': 0 + 'trailing_zeros(32, ["rs1_val","imm_val"],[32,5])': 0 + +sext.b: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + mnemonics: + sext.b: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'rs1_val == 0': 0 + 'rs1_val == 0x8000': 0 + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 + 'uniform_random(20, 100, ["rs1_val"], [xlen])': 0 + +sext.h: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + mnemonics: + sext.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'rs1_val == 0': 0 + 'rs1_val == 0x80': 0 + 'rs1_val == 0xff80': 0 + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 + 'uniform_random(20, 100, ["rs1_val"], [xlen])': 0 + +clmul: + config: + - check ISA:=regex(.*I.*Zbc.*) + - check ISA:=regex(.*I.*Zbkc.*) + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zks.*) + - check ISA:=regex(.*I.*Zkn.*) + mnemonics: + clmul: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + 'rs1_val==1 and rs2_val==1': 0 + 'rs1_val==1 and rs2_val==0': 0 + 'rs1_val==1 and rs2_val==0x1000': 0 + 'rs1_val==0 and rs2_val==1': 0 + 'rs1_val==0 and rs2_val==0': 0 + 'rs1_val==0 and rs2_val==0x1000': 0 + abstract_comb: + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + +clmulh: + config: + - check ISA:=regex(.*I.*Zbc.*) + - check ISA:=regex(.*I.*Zbkc.*) + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zks.*) + mnemonics: + clmulh: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + 'rs1_val==1 and rs2_val==1': 0 + 'rs1_val==1 and rs2_val==0': 0 + 'rs1_val==1 and rs2_val==0x1000': 0 + 'rs1_val==0 and rs2_val==1': 0 + 'rs1_val==0 and rs2_val==0': 0 + 'rs1_val==0 and rs2_val==0x1000': 0 + abstract_comb: + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + + +clmulr: + config: + - check ISA:=regex(.*I.*Zbc.*) + mnemonics: + clmulr: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + 'rs1_val==1 and rs2_val==1': 0 + 'rs1_val==1 and rs2_val==0': 0 + 'rs1_val==1 and rs2_val==0x1000': 0 + 'rs1_val==0 and rs2_val==1': 0 + 'rs1_val==0 and rs2_val==0': 0 + 'rs1_val==0 and rs2_val==0x1000': 0 + abstract_comb: + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + +bclr: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbs.*) + mnemonics: + bclr: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: +# 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs2_val", xlen )': 0 + 'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0 + 'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0 + 'leading_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'leading_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0 + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + + +bclri: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbs.*) + mnemonics: + bclri: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: +# 'xlenlim("rs1_val", xlen)': 0 + 'leading_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'leading_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 + + +bext: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbs.*) + mnemonics: + bext: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: +# 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs2_val", xlen )': 0 + 'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0 + 'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0 + 'leading_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'leading_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0 + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + + +bexti: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbs.*) + mnemonics: + bexti: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: +# 'xlenlim("rs1_val", xlen)': 0 + 'leading_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'leading_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 + + +binv: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbs.*) + mnemonics: + binv: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: +# 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs2_val", xlen )': 0 + 'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0 + 'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0 + 'leading_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'leading_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0 + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + + +binvi: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbs.*) + mnemonics: + binvi: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: +# 'xlenlim("rs1_val", xlen)': 0 + 'leading_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'leading_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 + +bset: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbs.*) + mnemonics: + bset: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: +# 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs2_val", xlen )': 0 + 'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0 + 'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0 + 'leading_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'leading_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0 + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + + +bseti: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbs.*) + mnemonics: + bseti: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: +# 'xlenlim("rs1_val", xlen)': 0 + 'leading_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_ones(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'leading_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32i_fencei.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32i_fencei.cgf new file mode 100644 index 000000000..7699d7c47 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32i_fencei.cgf @@ -0,0 +1,6 @@ +fencei: + config: + - check ISA:=regex(.*I.*Zifencei.*) + mnemonics: + fence.i: 0 + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32i_k.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32i_k.cgf new file mode 100644 index 000000000..d75c7dc79 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32i_k.cgf @@ -0,0 +1,537 @@ +aes32dsi: + config: + - check ISA:=regex(.*RV32.*I.*Zk.*) + - check ISA:=regex(.*RV32.*I.*Zkn.*) + - check ISA:=regex(.*RV32.*I.*Zknd.*) + mnemonics: + aes32dsi: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'byte_count(32,["rs1_val","rs2_val","imm_val"])': 0 + 'uniform_random(20, 100, ["rs1_val","rs2_val","imm_val"], [32, 32, 2])': 0 + +aes32dsmi: + config: + - check ISA:=regex(.*RV32.*I.*Zk.*) + - check ISA:=regex(.*RV32.*I.*Zkn.*) + - check ISA:=regex(.*RV32.*I.*Zknd.*) + mnemonics: + aes32dsmi: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'byte_count(32,["rs1_val","rs2_val","imm_val"])': 0 + 'uniform_random(20, 100, ["rs1_val","rs2_val","imm_val"], [32, 32, 2])': 0 + +aes32esi: + config: + - check ISA:=regex(.*RV32.*I.*Zk.*) + - check ISA:=regex(.*RV32.*I.*Zkn.*) + - check ISA:=regex(.*RV32.*I.*Zkne.*) + mnemonics: + aes32esi: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'byte_count(32,["rs1_val","rs2_val","imm_val"])': 0 + 'uniform_random(20, 100, ["rs1_val","rs2_val","imm_val"], [32, 32, 2])': 0 + +aes32esmi: + config: + - check ISA:=regex(.*RV32.*I.*Zk.*) + - check ISA:=regex(.*RV32.*I.*Zkn.*) + - check ISA:=regex(.*RV32.*I.*Zkne.*) + mnemonics: + aes32esmi: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'byte_count(32,["rs1_val","rs2_val","imm_val"])': 0 + 'uniform_random(20, 100, ["rs1_val","rs2_val","imm_val"], [32, 32, 2])': 0 + +sm4ed: + config: + - check ISA:=regex(.*I.*Zks.*) + - check ISA:=regex(.*I.*Zksed.*) + mnemonics: + sm4ed: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'byte_count(32,["rs1_val","rs2_val","imm_val"])': 0 + 'uniform_random(20, 100, ["rs1_val","rs2_val","imm_val"], [32, 32, 2])': 0 + +sm4ks: + config: + - check ISA:=regex(.*I.*Zks.*) + - check ISA:=regex(.*I.*Zksed.*) + mnemonics: + sm4ks: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'byte_count(32,["rs1_val","rs2_val","imm_val"])': 0 + 'uniform_random(20, 100, ["rs1_val","rs2_val","imm_val"], [32, 32, 2])': 0 + +sha256sig0: + config: + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zknh.*) + mnemonics: + sha256sig0: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 + 'uniform_random(20, 100, ["rs1_val"], [xlen])': 0 + +sha256sig1: + config: + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zknh.*) + mnemonics: + sha256sig1: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 + 'uniform_random(20, 100, ["rs1_val"], [xlen])': 0 + +sha256sum0: + config: + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zknh.*) + mnemonics: + sha256sum0: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 + 'uniform_random(20, 100, ["rs1_val"], [xlen])': 0 + +sha256sum1: + config: + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zknh.*) + mnemonics: + sha256sum1: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 + 'uniform_random(20, 100, ["rs1_val"], [xlen])': 0 + +sm3p0: + config: + - check ISA:=regex(.*I.*Zks.*) + - check ISA:=regex(.*I.*Zksh.*) + mnemonics: + sm3p0: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 + 'uniform_random(20, 100, ["rs1_val"], [xlen])': 0 + +sm3p1: + config: + - check ISA:=regex(.*I.*Zks.*) + - check ISA:=regex(.*I.*Zksh.*) + mnemonics: + sm3p1: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 + 'uniform_random(20, 100, ["rs1_val"], [xlen])': 0 + +sha512sig0h: + config: + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*RV32.*I.*Zkn.*) + - check ISA:=regex(.*RV32.*I.*Zknh.*) + mnemonics: + sha512sig0h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_ones("rs2_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 + 'walking_zeros("rs2_val", xlen, False)': 0 + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + +sha512sig0l: + config: + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*RV32.*I.*Zkn.*) + - check ISA:=regex(.*RV32.*I.*Zknh.*) + mnemonics: + sha512sig0l: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_ones("rs2_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 + 'walking_zeros("rs2_val", xlen, False)': 0 + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + +sha512sig1h: + config: + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*RV32.*I.*Zkn.*) + - check ISA:=regex(.*RV32.*I.*Zknh.*) + mnemonics: + sha512sig1h: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_ones("rs2_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 + 'walking_zeros("rs2_val", xlen, False)': 0 + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + +sha512sig1l: + config: + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*RV32.*I.*Zkn.*) + - check ISA:=regex(.*RV32.*I.*Zknh.*) + mnemonics: + sha512sig1l: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_ones("rs2_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 + 'walking_zeros("rs2_val", xlen, False)': 0 + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + +sha512sum0r: + config: + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*RV32.*I.*Zkn.*) + - check ISA:=regex(.*RV32.*I.*Zknh.*) + mnemonics: + sha512sum0r: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_ones("rs2_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 + 'walking_zeros("rs2_val", xlen, False)': 0 + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + +sha512sum1r: + config: + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*RV32.*I.*Zkn.*) + - check ISA:=regex(.*RV32.*I.*Zknh.*) + mnemonics: + sha512sum1r: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_ones("rs2_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 + 'walking_zeros("rs2_val", xlen, False)': 0 + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + + + +brev8_32: + config: + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zks.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zbkb.*) + mnemonics: + brev8: 0 + base_op: grevi + p_op_cond: imm_val == 7 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'rs1_val == 0x1020408': 0 + 'rs1_val == 0x2040801': 0 + 'rs1_val == 0x4080102': 0 + 'rs1_val == 0x8010204': 0 + abstract_comb: + 'leading_ones(64, ["rs1_val"], [32])': 0 + 'trailing_ones(64, ["rs1_val"], [32])': 0 + 'leading_zeros(64, ["rs1_val"], [32])': 0 + 'trailing_zeros(64, ["rs1_val"], [32])': 0 + 'bitmanip_dataset(xlen,["rs1_val"],signed=False)': 0 + +zip: + config: + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zks.*) + - check ISA:=regex(.*I.*Zbkb.*) + mnemonics: + zip: 0 + base_op: shfli + p_op_cond: imm_val == 15 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'leading_ones(32, ["rs1_val"],[xlen])': 0 + 'trailing_ones(32, ["rs1_val"],[xlen])': 0 + 'leading_zeros(32, ["rs1_val"],[xlen])': 0 + 'trailing_zeros(32, ["rs1_val"],[xlen])': 0 + +unzip: + config: + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zks.*) + - check ISA:=regex(.*I.*Zbkb.*) + mnemonics: + unzip: 0 + base_op: unshfli + p_op_cond: imm_val == 15 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'leading_ones(32, ["rs1_val"],[xlen])': 0 + 'trailing_ones(32, ["rs1_val"],[xlen])': 0 + 'leading_zeros(32, ["rs1_val"],[xlen])': 0 + 'trailing_zeros(32, ["rs1_val"],[xlen])': 0 + +pack: + config: + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zks.*) + - check ISA:=regex(.*I.*Zbkb.*) + mnemonics: + pack: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'leading_ones(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'trailing_ones(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'leading_zeros(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'trailing_zeros(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + +packh: + config: + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zks.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zbkb.*) + mnemonics: + packh: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'leading_ones(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'trailing_ones(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'leading_zeros(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'trailing_zeros(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + +xperm8: + config: + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zks.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zbkx.*) + mnemonics: + xperm8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + 'leading_ones(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'trailing_ones(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'leading_zeros(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'trailing_zeros(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + +xperm4: + config: + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zks.*) + - check ISA:=regex(.*I.*Zbkx.*) + mnemonics: + xperm4: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + 'leading_ones(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'trailing_ones(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'leading_zeros(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'trailing_zeros(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32i_priv.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32i_priv.cgf new file mode 100644 index 000000000..94131f0a5 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32i_priv.cgf @@ -0,0 +1,158 @@ +ecall: + config: + - check ISA:=regex(.*I.*); def rvtest_mtrap_routine=True + mnemonics: + ecall: 0 + +ebreak: + config: + - check ISA:=regex(.*I.*); def rvtest_mtrap_routine=True + mnemonics: + ebreak: 0 + +misalign-lh: + cond: check ISA:=regex(.*I.*Zicsr.*) + config: + - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True + - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True + mnemonics: + lh: 0 + val_comb: + 'ea_align == 1': 0 + +misalign-lhu: + config: + - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True + - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*I.*Zicsr.*) + mnemonics: + lhu: 0 + val_comb: + 'ea_align == 1': 0 + + +misalign-lw: + config: + - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True + - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*I.*Zicsr.*) + mnemonics: + lw: 0 + val_comb: + 'ea_align == 1': 0 + 'ea_align == 2': 0 + 'ea_align == 3': 0 + +misalign-sh: + config: + - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True + - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*I.*Zicsr.*) + mnemonics: + sh: 0 + val_comb: + 'ea_align == 1': 0 + +misalign-sw: + config: + - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True + - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*I.*Zicsr.*) + mnemonics: + sw: 0 + val_comb: + 'ea_align == 1': 0 + 'ea_align == 2': 0 + 'ea_align == 3': 0 + +misalign2-jalr: + config: + - check ISA:=regex(.*I.*C.*) + - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*I.*) + mnemonics: + jalr: 0 + val_comb: + 'imm_val%2 == 1 and ea_align == 2': 0 + 'imm_val%2 == 0 and ea_align == 2': 0 + +misalign1-jalr: + config: + - check ISA:=regex(.*I.*) + mnemonics: + jalr: 0 + val_comb: + 'imm_val%2 == 1 and ea_align == 1': 0 + 'imm_val%2 == 0 and ea_align == 1': 0 + +misalign-jal: + config: + - check ISA:=regex(.*I.*C.*) + - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*I.*) + mnemonics: + jal: 0 + val_comb: + 'ea_align == 2': 0 + +misalign-bge: + config: + - check ISA:=regex(.*I.*C.*) + - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*I.*) + mnemonics: + bge: 0 + val_comb: + ' rs1_val>rs2_val and ea_align == 2': 0 + +misalign-bgeu: + config: + - check ISA:=regex(.*I.*C.*) + - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*I.*) + mnemonics: + bgeu: 0 + val_comb: + ' rs1_val>rs2_val and ea_align == 2': 0 + +misalign-blt: + config: + - check ISA:=regex(.*I.*C.*) + - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*I.*) + mnemonics: + blt: 0 + val_comb: + ' rs1_val 0' : 0 + 'imm_val == 1020': 0 + abstract_comb: + 'walking_ones("imm_val", 8,False,scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val", 8,False,scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",8,False,scale_func = lambda x: x*4)': 0 + +clw: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.lw: 0 + rs1: + <<: *c_regs + rd: + <<: *c_regs + op_comb: + 'rs1 == rd': 0 + 'rs1 != rd': 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0 + + +csw: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.sw: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0 + + +cnop: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.nop: 0 + val_comb: + abstract_comb: + <<: *cbimm_val_walking + +caddi: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.addi: 0 + rd: + <<: *all_regs_mx0 + val_comb: + <<: [*base_rs1val_sgn, *cbfmt_immval_sgn, *ifmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",6)])': 0 + <<: [*rs1val_walking, *cbimm_val_walking] + +cjal: + config: + - check ISA:=regex(.*RV32.*I.*C.*) + mnemonics: + c.jal: 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val < 0': 0 + abstract_comb: + 'walking_ones("imm_val", 11,fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030),scale_func = lambda x: x*2)': 0 + 'walking_zeros("imm_val", 11,fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030),scale_func = lambda x: x*2)': 0 + 'alternate("imm_val",11, fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030) ,scale_func = lambda x: x*2)': 0 + +cli: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.li: 0 + rd: + <<: *all_regs + val_comb: + <<: [*cbfmt_immval_sgn] + abstract_comb: + 'walking_ones("imm_val", 6)': 0 + 'walking_zeros("imm_val", 6)': 0 + 'alternate("imm_val", 6)': 0 + +caddi16sp: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.addi16sp: 0 + rd: + x2: 0 + val_comb: + <<: [*base_rs1val_sgn,*ifmt_val_comb_sgn] + 'imm_val == -512': 0 + 'imm_val == 496': 0 + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("imm_val", 6,True,scale_func = lambda x: x*16)': 0 + 'walking_zeros("imm_val", 6,True,scale_func = lambda x: x*16)': 0 + 'alternate("imm_val",6,True,scale_func = lambda x: x*16)': 0 + +clui: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.lui: 0 + rd: + x0: 0 + x1: 0 + x3: 0 + x4: 0 + x5: 0 + x6: 0 + x7: 0 + x8: 0 + x9: 0 + x10: 0 + x11: 0 + x12: 0 + x13: 0 + x14: 0 + x15: 0 + x16: 0 + x17: 0 + x18: 0 + x19: 0 + x20: 0 + x21: 0 + x22: 0 + x23: 0 + x24: 0 + x25: 0 + x26: 0 + x27: 0 + x28: 0 + x29: 0 + x30: 0 + x31: 0 + + val_comb: + 'rs1_val > 0 and imm_val > 32': 0 + 'rs1_val > 0 and imm_val < 32 and imm_val !=0 ': 0 + 'rs1_val < 0 and imm_val > 32': 0 + 'rs1_val < 0 and imm_val < 32 and imm_val !=0 ': 0 + abstract_comb: + 'walking_ones("imm_val", 6, False)': 0 + 'walking_zeros("imm_val", 6, False)': 0 + 'alternate("imm_val", 6, False)': 0 + +csrli: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.srli: 0 + rs1: + <<: *c_regs + val_comb: + 'rs1_val < 0 and imm_val < xlen': 0 + 'rs1_val > 0 and imm_val < xlen': 0 + 'rs1_val == imm_val and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == 0 and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == 1 and imm_val != 0 and imm_val < xlen': 0 + abstract_comb: + 'sp_dataset(xlen,["rs1_val"])': 0 + <<: [*rs1val_walking] + 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 + 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 + +csrai: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.srai: 0 + rs1: + <<: *c_regs + val_comb: + 'rs1_val < 0 and imm_val < xlen': 0 + 'rs1_val > 0 and imm_val < xlen': 0 + 'rs1_val == imm_val and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == 0 and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == 1 and imm_val != 0 and imm_val < xlen': 0 + abstract_comb: + 'sp_dataset(xlen,["rs1_val"])': 0 + <<: [*rs1val_walking] + 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 + 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 + +candi: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.andi: 0 + rs1: + <<: *c_regs + val_comb: + <<: [*base_rs1val_sgn,*cbfmt_immval_sgn,*ifmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",6)])': 0 + <<: [*rs1val_walking, *cbimm_val_walking] + +csub: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.sub: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn, *base_rs2val_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking,*rs2val_walking] + +cxor: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.xor: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn, *base_rs2val_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking,*rs2val_walking] + +cor: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.or: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn,*base_rs2val_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking,*rs2val_walking] + +cand: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.and: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn,*base_rs2val_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking,*rs2val_walking] + + + +cj: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.j: 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val < 0': 0 + abstract_comb: + 'walking_ones("imm_val", 11,fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030),scale_func = lambda x: x*2)': 0 + 'walking_zeros("imm_val", 11,fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030),scale_func = lambda x: x*2)': 0 + 'alternate("imm_val",11, fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030) ,scale_func = lambda x: x*2)': 0 + +cbeqz: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.beqz: 0 + rs1: + <<: *c_regs + val_comb: + 'rs1_val > 0 and imm_val > 0': 0 + 'rs1_val < 0 and imm_val > 0': 0 + 'rs1_val == 0 and imm_val > 0': 0 + 'rs1_val > 0 and imm_val < 0': 0 + 'rs1_val < 0 and imm_val < 0': 0 + 'rs1_val == 0 and imm_val < 0': 0 + <<: [*base_rs1val_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val"])': 0 + <<: [*rs1val_walking] + +cbnez: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.bnez: 0 + rs1: + <<: *c_regs + val_comb: + 'rs1_val > 0 and imm_val > 0': 0 + 'rs1_val < 0 and imm_val > 0': 0 + 'rs1_val == 0 and imm_val > 0': 0 + 'rs1_val > 0 and imm_val < 0': 0 + 'rs1_val < 0 and imm_val < 0': 0 + 'rs1_val == 0 and imm_val < 0': 0 + <<: [*base_rs1val_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val"])': 0 + <<: [*rs1val_walking] + +cslli: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.slli: 0 + rd: + <<: *c_regs + val_comb: + 'rs1_val < 0 and imm_val < xlen': 0 + 'rs1_val > 0 and imm_val < xlen': 0 + 'rs1_val == imm_val and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == 0 and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == 1 and imm_val != 0 and imm_val < xlen': 0 + abstract_comb: + 'sp_dataset(xlen,["rs1_val"])': 0 + <<: [*rs1val_walking] + 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 + 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 + +clwsp: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.lwsp: 0 + rd: + <<: *all_regs_mx0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0 + + +cjr: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.jr: 0 + rs1: + <<: *all_regs_mx0 + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *base_rs1val_sgn_rs2val_zero + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: *rs1val_walking + +cmv: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.mv: 0 + rs2: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs2_val"])': 0 + <<: [*rs2val_walking] + +cadd: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.add: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs_mx0 + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn,*base_rs2val_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking,*rs2val_walking] + +cjalr: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.jalr: 0 + rs1: + <<: *all_regs_mx0 + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *base_rs1val_sgn_rs2val_zero + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: *rs1val_walking + +cswsp: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.swsp: 0 + rs2: + <<: *all_regs_mx2 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0 + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32im.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32im.cgf new file mode 100644 index 000000000..d69131e4d --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32im.cgf @@ -0,0 +1,154 @@ +# For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore + +mul: + config: + - check ISA:=regex(.*I.*M.*) + mnemonics: + mul: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +mulh: + config: + - check ISA:=regex(.*I.*M.*) + mnemonics: + mulh: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +mulhu: + config: + - check ISA:=regex(.*I.*M.*) + mnemonics: + mulhu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'sp_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + +mulhsu: + config: + - check ISA:=regex(.*I.*M.*) + mnemonics: + mulhsu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_unsgn, *rfmt_val_comb_unsgn] + 'rs1_val > 0 and rs2_val > 0': 0 + abstract_comb: + 'sp_dataset(xlen,[("rs1_val",xlen),("rs2_val",xlen,False)])': 0 + <<: [*rs1val_walking, *rs2val_walking_unsgn] + +div: + config: + - check ISA:=regex(.*I.*M.*) + mnemonics: + div: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*rfmt_op_comb , *div_hardcoded_opcomb] + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn, *div_corner_case] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +divu: + config: + - check ISA:=regex(.*I.*M.*) + mnemonics: + divu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*rfmt_op_comb , *div_hardcoded_opcomb] + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'sp_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + +rem: + config: + - check ISA:=regex(.*I.*M.*) + mnemonics: + rem: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*rfmt_op_comb , *div_hardcoded_opcomb] + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn, *div_corner_case] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +remu: + config: + - check ISA:=regex(.*I.*M.*) + mnemonics: + remu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*rfmt_op_comb , *div_hardcoded_opcomb] + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'sp_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32ip.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32ip.cgf new file mode 100644 index 000000000..3fa586ed5 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32ip.cgf @@ -0,0 +1,4419 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +add16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + add16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +radd16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + radd16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +uradd16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + uradd16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'simd_base_val("rs2", xlen, 16, signed=False)': 0 + 'simd_val_comb(xlen, 16, signed=False)': 0 + +kadd16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kadd16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +ukadd16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ukadd16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'simd_base_val("rs2", xlen, 16, signed=False)': 0 + 'simd_val_comb(xlen, 16, signed=False)': 0 + +sub16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + sub16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +rsub16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + rsub16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + + +ursub16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ursub16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'simd_base_val("rs2", xlen, 16, signed=False)': 0 + 'simd_val_comb(xlen, 16, signed=False)': 0 + +ksub16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ksub16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +uksub16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + uksub16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'simd_base_val("rs2", xlen, 16, signed=False)': 0 + 'simd_val_comb(xlen, 16, signed=False)': 0 + +cras16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + cras16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +rcras16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + rcras16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +urcras16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + urcras16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'simd_base_val("rs2", xlen, 16, signed=False)': 0 + 'simd_val_comb(xlen, 16, signed=False)': 0 + +kcras16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kcras16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +ukcras16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ukcras16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'simd_base_val("rs2", xlen, 16, signed=False)': 0 + 'simd_val_comb(xlen, 16, signed=False)': 0 + +crsa16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + crsa16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +rcrsa16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + rcrsa16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +urcrsa16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + urcrsa16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'simd_base_val("rs2", xlen, 16, signed=False)': 0 + 'simd_val_comb(xlen, 16, signed=False)': 0 + +kcrsa16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kcrsa16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +ukcrsa16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ukcrsa16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'simd_base_val("rs2", xlen, 16, signed=False)': 0 + 'simd_val_comb(xlen, 16, signed=False)': 0 + +stas16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + stas16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +rstas16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + rstas16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +urstas16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + urstas16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'simd_base_val("rs2", xlen, 16, signed=False)': 0 + 'simd_val_comb(xlen, 16, signed=False)': 0 + +kstas16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kstas16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +ukstas16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ukstas16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'simd_base_val("rs2", xlen, 16, signed=False)': 0 + 'simd_val_comb(xlen, 16, signed=False)': 0 + +stsa16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + stsa16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +rstsa16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + rstsa16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +urstsa16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + urstsa16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'simd_base_val("rs2", xlen, 16, signed=False)': 0 + 'simd_val_comb(xlen, 16, signed=False)': 0 + +kstsa16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kstsa16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +ukstsa16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ukstsa16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'simd_base_val("rs2", xlen, 16, signed=False)': 0 + 'simd_val_comb(xlen, 16, signed=False)': 0 + +add8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + add8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + 'simd_base_val("rs2", xlen, 8, signed=True)': 0 + 'simd_val_comb(xlen, 8, signed=True)': 0 + +radd8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + radd8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + 'simd_base_val("rs2", xlen, 8, signed=True)': 0 + 'simd_val_comb(xlen, 8, signed=True)': 0 + +uradd8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + uradd8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=False)': 0 + 'simd_base_val("rs2", xlen, 8, signed=False)': 0 + 'simd_val_comb(xlen, 8, signed=False)': 0 + +kadd8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kadd8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + 'simd_base_val("rs2", xlen, 8, signed=True)': 0 + 'simd_val_comb(xlen, 8, signed=True)': 0 + +ukadd8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ukadd8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=False)': 0 + 'simd_base_val("rs2", xlen, 8, signed=False)': 0 + 'simd_val_comb(xlen, 8, signed=False)': 0 + +sub8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + sub8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + 'simd_base_val("rs2", xlen, 8, signed=True)': 0 + 'simd_val_comb(xlen, 8, signed=True)': 0 + +rsub8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + rsub8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + 'simd_base_val("rs2", xlen, 8, signed=True)': 0 + 'simd_val_comb(xlen, 8, signed=True)': 0 + +ursub8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ursub8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=False)': 0 + 'simd_base_val("rs2", xlen, 8, signed=False)': 0 + 'simd_val_comb(xlen, 8, signed=False)': 0 + +ksub8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ksub8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + 'simd_base_val("rs2", xlen, 8, signed=True)': 0 + 'simd_val_comb(xlen, 8, signed=True)': 0 + +uksub8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + uksub8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=False)': 0 + 'simd_base_val("rs2", xlen, 8, signed=False)': 0 + 'simd_val_comb(xlen, 8, signed=False)': 0 + +sra16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + sra16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'walking_ones("rs2_val", ceil(log(16, 2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(16, 2)), False)': 0 + 'alternate("rs2_val", ceil(log(16, 2)), False)': 0 + +srai16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + srai16: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_imm_val("imm_val", 4)': 0 + +sra16.u: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + sra16.u: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'walking_ones("rs2_val", ceil(log(16, 2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(16, 2)), False)': 0 + 'alternate("rs2_val", ceil(log(16, 2)), False)': 0 + +srai16.u: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + srai16.u: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_imm_val("imm_val", 4)': 0 + +srl16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + srl16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'walking_ones("rs2_val", ceil(log(16, 2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(16, 2)), False)': 0 + 'alternate("rs2_val", ceil(log(16, 2)), False)': 0 + +srli16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + srli16: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'simd_imm_val("imm_val", 4)': 0 + +srl16.u: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + srl16.u: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'walking_ones("rs2_val", ceil(log(16, 2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(16, 2)), False)': 0 + 'alternate("rs2_val", ceil(log(16, 2)), False)': 0 + +srli16.u: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + srli16.u: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'simd_imm_val("imm_val", 4)': 0 + +sll16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + sll16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'walking_ones("rs2_val", ceil(log(16, 2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(16, 2)), False)': 0 + 'alternate("rs2_val", ceil(log(16, 2)), False)': 0 + +slli16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + slli16: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'simd_imm_val("imm_val", 4)': 0 + +ksll16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ksll16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'walking_ones("rs2_val", ceil(log(16, 2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(16, 2)), False)': 0 + 'alternate("rs2_val", ceil(log(16, 2)), False)': 0 + +kslli16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kslli16: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_imm_val("imm_val", 4)': 0 + +kslra16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kslra16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'walking_ones("rs2_val", xlen, True)': 0 + 'walking_zeros("rs2_val", xlen, True)': 0 + 'alternate("rs2_val", xlen, True)': 0 + +kslra16.u: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kslra16.u: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'walking_ones("rs2_val", xlen, True)': 0 + 'walking_zeros("rs2_val", xlen, True)': 0 + 'alternate("rs2_val", xlen, True)': 0 + +sra8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + sra8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + 'walking_ones("rs2_val", ceil(log(8, 2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(8, 2)), False)': 0 + 'alternate("rs2_val", ceil(log(8, 2)), False)': 0 + +srai8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + srai8: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + 'simd_imm_val("imm_val", 3)': 0 + +sra8.u: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + sra8.u: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + 'walking_ones("rs2_val", ceil(log(8, 2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(8, 2)), False)': 0 + 'alternate("rs2_val", ceil(log(8, 2)), False)': 0 + +srai8.u: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + srai8.u: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + 'simd_imm_val("imm_val", 3)': 0 + +srl8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + srl8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=False)': 0 + 'walking_ones("rs2_val", ceil(log(8, 2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(8, 2)), False)': 0 + 'alternate("rs2_val", ceil(log(8, 2)), False)': 0 + +srli8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + srli8: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=False)': 0 + 'simd_imm_val("imm_val", 3)': 0 + +srl8.u: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + srl8.u: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=False)': 0 + 'walking_ones("rs2_val", ceil(log(8, 2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(8, 2)), False)': 0 + 'alternate("rs2_val", ceil(log(8, 2)), False)': 0 + +srli8.u: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + srli8.u: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=False)': 0 + 'simd_imm_val("imm_val", 3)': 0 + +sll8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + sll8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=False)': 0 + 'walking_ones("rs2_val", ceil(log(8, 2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(8, 2)), False)': 0 + 'alternate("rs2_val", ceil(log(8, 2)), False)': 0 + +slli8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + slli8: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=False)': 0 + 'simd_imm_val("imm_val", 3)': 0 + +ksll8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ksll8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + 'walking_ones("rs2_val", ceil(log(8, 2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(8, 2)), False)': 0 + 'alternate("rs2_val", ceil(log(8, 2)), False)': 0 + +kslli8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kslli8: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + 'simd_imm_val("imm_val", 3)': 0 + +kslra8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kslra8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + 'walking_ones("rs2_val", xlen, True)': 0 + 'walking_zeros("rs2_val", xlen, True)': 0 + 'alternate("rs2_val", xlen, True)': 0 + +kslra8.u: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kslra8.u: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=False)': 0 + 'walking_ones("rs2_val", xlen, True)': 0 + 'walking_zeros("rs2_val", xlen, True)': 0 + 'alternate("rs2_val", xlen, True)': 0 + +cmpeq16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + cmpeq16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +scmplt16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + scmplt16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +scmple16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + scmple16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +ucmplt16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ucmplt16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'simd_base_val("rs2", xlen, 16, signed=False)': 0 + 'simd_val_comb(xlen, 16, signed=False)': 0 + +ucmple16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ucmple16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'simd_base_val("rs2", xlen, 16, signed=False)': 0 + 'simd_val_comb(xlen, 16, signed=False)': 0 + +cmpeq8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + cmpeq8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + 'simd_base_val("rs2", xlen, 8, signed=True)': 0 + 'simd_val_comb(xlen, 8, signed=True)': 0 + +scmplt8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + scmplt8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + 'simd_base_val("rs2", xlen, 8, signed=True)': 0 + 'simd_val_comb(xlen, 8, signed=True)': 0 + +scmple8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + scmple8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + 'simd_base_val("rs2", xlen, 8, signed=True)': 0 + 'simd_val_comb(xlen, 8, signed=True)': 0 + +ucmplt8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ucmplt8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=False)': 0 + 'simd_base_val("rs2", xlen, 8, signed=False)': 0 + 'simd_val_comb(xlen, 8, signed=False)': 0 + +ucmple8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ucmple8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=False)': 0 + 'simd_base_val("rs2", xlen, 8, signed=False)': 0 + 'simd_val_comb(xlen, 8, signed=False)': 0 + +smul16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smul16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +smulx16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smulx16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +umul16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + umul16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'simd_base_val("rs2", xlen, 16, signed=False)': 0 + 'simd_val_comb(xlen, 16, signed=False)': 0 + +umulx16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + umulx16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'simd_base_val("rs2", xlen, 16, signed=False)': 0 + 'simd_val_comb(xlen, 16, signed=False)': 0 + +khm16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + khm16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +khmx16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + khmx16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +smul8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smul8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + 'simd_base_val("rs2", xlen, 8, signed=True)': 0 + 'simd_val_comb(xlen, 8, signed=True)': 0 + +smulx8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smulx8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + 'simd_base_val("rs2", xlen, 8, signed=True)': 0 + 'simd_val_comb(xlen, 8, signed=True)': 0 + +umul8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + umul8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=False)': 0 + 'simd_base_val("rs2", xlen, 8, signed=False)': 0 + 'simd_val_comb(xlen, 8, signed=False)': 0 + +umulx8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + umulx8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=False)': 0 + 'simd_base_val("rs2", xlen, 8, signed=False)': 0 + 'simd_val_comb(xlen, 8, signed=False)': 0 + +khm8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + khm8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + 'simd_base_val("rs2", xlen, 8, signed=True)': 0 + 'simd_val_comb(xlen, 8, signed=True)': 0 + +khmx8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + khmx8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + 'simd_base_val("rs2", xlen, 8, signed=True)': 0 + 'simd_val_comb(xlen, 8, signed=True)': 0 + +smin16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smin16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +umin16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + umin16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'simd_base_val("rs2", xlen, 16, signed=False)': 0 + 'simd_val_comb(xlen, 16, signed=False)': 0 + +smax16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smax16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +umax16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + umax16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'simd_base_val("rs2", xlen, 16, signed=False)': 0 + 'simd_val_comb(xlen, 16, signed=False)': 0 + +sclip16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + sclip16: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_imm_val("imm_val", 4)': 0 + +uclip16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + uclip16: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'simd_imm_val("imm_val", 4)': 0 + +kabs16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kabs16: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + +clrs16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + clrs16: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + +clz16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + clz16: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + +# alias of pkbt16 +# swap16: +# config: +# - check ISA:=regex(.*I.*P.*Zicsr.*) +# mnemonics: +# swap16: 0 +# rs1: +# <<: *all_regs +# rd: +# <<: *all_regs +# val_comb: +# abstract_comb: +# 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + +smin8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smin8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + 'simd_base_val("rs2", xlen, 8, signed=True)': 0 + 'simd_val_comb(xlen, 8, signed=True)': 0 + +umin8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + umin8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=False)': 0 + 'simd_base_val("rs2", xlen, 8, signed=False)': 0 + 'simd_val_comb(xlen, 8, signed=False)': 0 + +smax8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smax8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + 'simd_base_val("rs2", xlen, 8, signed=True)': 0 + 'simd_val_comb(xlen, 8, signed=True)': 0 + +umax8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + umax8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=False)': 0 + 'simd_base_val("rs2", xlen, 8, signed=False)': 0 + 'simd_val_comb(xlen, 8, signed=False)': 0 + +kabs8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kabs8: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + +sclip8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + sclip8: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + 'simd_imm_val("imm_val", 3)': 0 + +uclip8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + uclip8: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=False)': 0 + 'simd_imm_val("imm_val", 3)': 0 + +clrs8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + clrs8: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + +clz8: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + clz8: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=False)': 0 + +# instructions overlapping with those in the B extension in RV32/RV64 configuration (Zbpbo) +# swap8: +# config: +# - check ISA:=regex(.*I.*P.*Zicsr.*) +# mnemonics: +# swap8: 0 +# rs1: +# <<: *all_regs +# rd: +# <<: *all_regs +# val_comb: +# abstract_comb: +# 'simd_base_val("rs1", xlen, 8, signed=False)': 0 + +sunpkd810: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + sunpkd810: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + +sunpkd820: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + sunpkd820: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + +sunpkd830: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + sunpkd830: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + +sunpkd831: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + sunpkd831: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + +sunpkd832: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + sunpkd832: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + +zunpkd810: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + zunpkd810: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=False)': 0 + +zunpkd820: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + zunpkd820: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=False)': 0 + +zunpkd830: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + zunpkd830: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=False)': 0 + +zunpkd831: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + zunpkd831: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=False)': 0 + +zunpkd832: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + zunpkd832: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=False)': 0 + +# instructions overlapping with those in the B extension in RV32 configuration (Zbpbo) +# pkbb16: +# config: +# - check ISA:=regex(.*I.*P.*Zicsr.*) +# mnemonics: +# pkbb16: 0 +# rs1: +# <<: *all_regs +# rs2: +# <<: *all_regs +# rd: +# <<: *all_regs +# op_comb: +# <<: *rfmt_op_comb +# val_comb: +# abstract_comb: +# 'simd_base_val("rs1", xlen, 16, signed=False)': 0 +# 'simd_base_val("rs2", xlen, 16, signed=False)': 0 +# 'simd_val_comb(xlen, 16, signed=False)': 0 + +pkbt16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + pkbt16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'simd_base_val("rs2", xlen, 16, signed=False)': 0 + 'simd_val_comb(xlen, 16, signed=False)': 0 + +pktb16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + pktb16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'simd_base_val("rs2", xlen, 16, signed=False)': 0 + 'simd_val_comb(xlen, 16, signed=False)': 0 + +# instructions overlapping with those in the B extension in RV32 configuration (Zbpbo) +# pktt16: +# config: +# - check ISA:=regex(.*I.*P.*Zicsr.*) +# mnemonics: +# pktt16: 0 +# rs1: +# <<: *all_regs +# rs2: +# <<: *all_regs +# rd: +# <<: *all_regs +# op_comb: +# <<: *rfmt_op_comb +# val_comb: +# abstract_comb: +# 'simd_base_val("rs1", xlen, 16, signed=False)': 0 +# 'simd_base_val("rs2", xlen, 16, signed=False)': 0 +# 'simd_val_comb(xlen, 16, signed=False)': 0 + +# 2.3.2. +smmul: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smmul: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + +smmul.u: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smmul.u: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + +kmmac: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmmac: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + +kmmac.u: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmmac.u: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + +kmmsb: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmmsb: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + +kmmsb.u: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmmsb.u: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + +kwmmul: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kwmmul: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + +kwmmul.u: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kwmmul.u: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + + +# 2.3.3 Most Significant Word 32x32 Multiply & Add Instructions + +smmwb: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smmwb: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + +smmwb.u: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smmwb.u: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + +smmwt: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smmwt: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + +smmwt.u: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smmwt.u: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + + +kmmawb: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmmawb: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + +kmmawb.u: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmmawb.u: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + +kmmawt: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmmawt: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + +kmmawt.u: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmmawt.u: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + + +kmmwb2: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmmwb2: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + +kmmwb2.u: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmmwb2.u: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + +kmmwt2: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmmwt2: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + +kmmwt2.u: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmmwt2.u: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + + +kmmawb2: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmmawb2: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + +kmmawb2.u: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmmawb2.u: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + +kmmawt2: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmmawt2: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + +kmmawt2.u: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmmawt2.u: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + +# 2.3.4 + +smbb16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smbb16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +smbt16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smbt16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +smtt16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smtt16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +kmda: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmda: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +kmxda: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmxda: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 +smds: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smds: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +smdrs: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smdrs: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +smxds: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smxds: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +kmabb: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmabb: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +kmabt: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmabt: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +kmatt: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmatt: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +kmada: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmada: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +kmaxda: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmaxda: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +kmads: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmads: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +kmadrs: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmadrs: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +kmaxds: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmaxds: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +kmsda: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmsda: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +kmsxda: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmsxda: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +# 2.3.5 +smal: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smal: 0 + rs1: + <<: *pair_regs + rs2: + <<: *all_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*rvp64_rs1val_sgn] + abstract_comb: + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + +# 2.3.6 Miscellaneous Instructions + +sclip32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + sclip32: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_imm_val("imm_val", 5)': 0 + +uclip32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + uclip32: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'simd_imm_val("imm_val", 5)': 0 + +clrs32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + clrs32: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + +# instructions overlapping with those in the B extension in RV32 configuration (Zbpbo) +# clz32: +# config: +# - check ISA:=regex(.*I.*P.*Zicsr.*) +# mnemonics: +# clz32: 0 +# rs1: +# <<: *all_regs +# rd: +# <<: *all_regs +# val_comb: +# abstract_comb: +# 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + +pbsad: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + pbsad: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=False)': 0 + 'simd_base_val("rs2", xlen, 8, signed=False)': 0 + 'simd_val_comb(xlen, 8, signed=False)': 0 + +pbsada: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + pbsada: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=False)': 0 + 'simd_base_val("rs2", xlen, 8, signed=False)': 0 + 'simd_val_comb(xlen, 8, signed=False)': 0 + +smaqa: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smaqa: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + 'simd_base_val("rs2", xlen, 8, signed=True)': 0 + 'simd_val_comb(xlen, 8, signed=True)': 0 + +umaqa: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + umaqa: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=False)': 0 + 'simd_base_val("rs2", xlen, 8, signed=False)': 0 + 'simd_val_comb(xlen, 8, signed=False)': 0 + +smaqa.su: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smaqa.su: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 8, signed=True)': 0 + 'simd_base_val("rs2", xlen, 8, signed=True)': 0 + 'simd_val_comb(xlen, 8, signed=True)': 0 + +# 2.4.1 +add64: + config: + - check ISA:=regex(.*32.*I.*P.*Zicsr.*) + mnemonics: + add64: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*rvp64_rs1val_sgn, *rvp64_rs2val_sgn, *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rvp64_rs1val_walking_sgn, *rvp64_rs2val_walking_sgn] + +radd64: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + radd64: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*rvp64_rs1val_sgn, *rvp64_rs2val_sgn, *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rvp64_rs1val_walking_sgn, *rvp64_rs2val_walking_sgn] + +uradd64: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + uradd64: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*rvp64_rs1val_unsgn, *rvp64_rs2val_unsgn, *rfmt_val_comb_unsgn] + abstract_comb: + <<: [*rvp64_rs1val_walking_unsgn, *rvp64_rs2val_walking_unsgn] + +kadd64: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kadd64: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*rvp64_rs1val_sgn, *rvp64_rs2val_sgn, *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rvp64_rs1val_walking_sgn, *rvp64_rs2val_walking_sgn] + +ukadd64: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ukadd64: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*rvp64_rs1val_unsgn, *rvp64_rs2val_unsgn, *rfmt_val_comb_unsgn] + abstract_comb: + <<: [*rvp64_rs1val_walking_unsgn, *rvp64_rs2val_walking_unsgn] + +sub64: + config: + - check ISA:=regex(.*32.*I.*P.*Zicsr.*) + mnemonics: + sub64: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*rvp64_rs1val_sgn, *rvp64_rs2val_sgn, *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rvp64_rs1val_walking_sgn, *rvp64_rs2val_walking_sgn] + +rsub64: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + rsub64: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*rvp64_rs1val_sgn, *rvp64_rs2val_sgn, *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rvp64_rs1val_walking_sgn, *rvp64_rs2val_walking_sgn] + +ursub64: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ursub64: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*rvp64_rs1val_unsgn, *rvp64_rs2val_unsgn, *rfmt_val_comb_unsgn] + abstract_comb: + <<: [*rvp64_rs1val_walking_unsgn, *rvp64_rs2val_walking_unsgn] + +ksub64: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ksub64: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*rvp64_rs1val_sgn, *rvp64_rs2val_sgn, *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rvp64_rs1val_walking_sgn, *rvp64_rs2val_walking_sgn] + +uksub64: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + uksub64: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*rvp64_rs1val_unsgn, *rvp64_rs2val_unsgn, *rfmt_val_comb_unsgn] + abstract_comb: + <<: [*rvp64_rs1val_walking_unsgn, *rvp64_rs2val_walking_unsgn] + +# 2.4.2 +smar64: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smar64: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +smsr64: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smsr64: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +umar64: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + umar64: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'simd_base_val("rs2", xlen, 32, signed=False)': 0 + 'simd_val_comb(xlen, 32, signed=False)': 0 + +umsr64: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + umsr64: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'simd_base_val("rs2", xlen, 32, signed=False)': 0 + 'simd_val_comb(xlen, 32, signed=False)': 0 + +kmar64: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmar64: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +kmsr64: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmsr64: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +ukmar64: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ukmar64: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'simd_base_val("rs2", xlen, 32, signed=False)': 0 + 'simd_val_comb(xlen, 32, signed=False)': 0 + +ukmsr64: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ukmsr64: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'simd_base_val("rs2", xlen, 32, signed=False)': 0 + 'simd_val_comb(xlen, 32, signed=False)': 0 + +# 2.4.3 +smalbb: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smalbb: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +smalbt: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smalbt: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +smaltt: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smaltt: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +smalda: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smalda: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +smalxda: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smalxda: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +smalds: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smalds: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +smaldrs: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smaldrs: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +smalxds: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smalxds: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +smslda: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smslda: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +smslxda: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smslxda: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +# 2.5 Non-SIMD Instructions + +kaddh: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kaddh: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +ksubh: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ksubh: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +khmbb: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + khmbb: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +khmbt: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + khmbt: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +khmtt: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + khmtt: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +ukaddh: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ukaddh: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'simd_base_val("rs2", xlen, 16, signed=False)': 0 + 'simd_val_comb(xlen, 16, signed=False)': 0 + +uksubh: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + uksubh: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'simd_base_val("rs2", xlen, 16, signed=False)': 0 + 'simd_val_comb(xlen, 16, signed=False)': 0 + +kaddw: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kaddw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +ukaddw: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ukaddw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'simd_base_val("rs2", xlen, 32, signed=False)': 0 + 'simd_val_comb(xlen, 32, signed=False)': 0 + +ksubw: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ksubw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +uksubw: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + uksubw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'simd_base_val("rs2", xlen, 32, signed=False)': 0 + 'simd_val_comb(xlen, 32, signed=False)': 0 + +kdmbb: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kdmbb: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +kdmbt: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kdmbt: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +kdmtt: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kdmtt: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +kslraw: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kslraw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +kslraw.u: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kslraw.u: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + 'rs1_w0_val == rs2_w0_val': 0 + 'rs1_w0_val != rs2_w0_val': 0 + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + +ksllw: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ksllw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'walking_ones("rs2_val", ceil(log(32, 2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(32, 2)), False)': 0 + 'alternate("rs2_val", ceil(log(32, 2)), False)': 0 + +kslliw: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kslliw: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_imm_val("imm_val", 5)': 0 + +kdmabb: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kdmabb: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +kdmabt: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kdmabt: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +kdmatt: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kdmatt: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +kabsw: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kabsw: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + +# 2.5.3. +raddw: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + raddw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + +uraddw: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + uraddw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'simd_base_val("rs2", xlen, 32, signed=False)': 0 + +rsubw: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + rsubw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + +ursubw: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ursubw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'simd_base_val("rs2", xlen, 32, signed=False)': 0 + +mulr64: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + mulr64: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'simd_base_val("rs2", xlen, 32, signed=False)': 0 +mulsr64: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + mulsr64: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + +maddr32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + maddr32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + +msubr32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + msubr32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + +# 2.5.4 +# alias of csr operations +# rdov: +# config: +# - check ISA:=regex(.*I.*P.*Zicsr.*) +# mnemonics: +# rdov: 0 +# rd: +# <<: *all_regs +# +# +# clrov: +# config: +# - check ISA:=regex(.*I.*P.*Zicsr.*) +# mnemonics: +# clrov: 0 +# rd: +# <<: *all_regs + +# 2.5.5. +ave: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ave: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn, *base_rs2val_sgn, *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +sra.u: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + sra.u: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn, *base_rs2val_sgn, *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +srai.u: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + srai.u: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + <<: [*rs1val_walking, *ifmt_immval_walking_len] + + +# instructions overlapping with those in the B extension in RV32/RV64 configuration (Zbpbo) +# bitrev: +# config: +# - check ISA:=regex(.*I.*P.*Zicsr.*) +# mnemonics: +# bitrev: 0 +# rs1: +# <<: *all_regs +# rs2: +# <<: *all_regs +# rd: +# <<: *all_regs +# op_comb: +# <<: *rfmt_op_comb +# val_comb: +# <<: [*base_rs1val_sgn, *base_rs2val_sgn, *rfmt_val_comb_sgn] +# abstract_comb: +# <<: [*rs1val_walking, *rs2val_walking] +# +# +# bitrevi: +# config: +# - check ISA:=regex(.*I.*P.*Zicsr.*) +# mnemonics: +# bitrevi: 0 +# rs1: +# <<: *all_regs +# rd: +# <<: *all_regs +# op_comb: +# <<: *ifmt_op_comb +# val_comb: +# abstract_comb: +# <<: [*rs1val_walking, *ifmt_immval_walking_len] + +# instructions overlapping with those in the B extension in RV32/RV64 configuration (Zbpbo) +# wext: +# config: +# - check ISA:=regex(.*I.*P.*Zicsr.*) +# mnemonics: +# wext: 0 +# rs1: +# <<: *pair_regs +# rs2: +# <<: *all_regs +# rd: +# <<: *all_regs +# op_comb: +# <<: *rfmt_op_comb +# val_comb: +# <<: [*rvp64_rs1val_sgn] +# abstract_comb: +# 'simd_base_val("rs2", xlen, 8, signed=False)': 0 +# +# wexti: +# config: +# - check ISA:=regex(.*I.*P.*Zicsr.*) +# mnemonics: +# wexti: 0 +# rs1: +# <<: *pair_regs +# rd: +# <<: *all_regs +# op_comb: +# <<: *ifmt_op_comb +# val_comb: +# <<: [*rvp64_rs1val_sgn] +# abstract_comb: +# 'simd_imm_val("imm_val", 5)': 0 + +insb: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + insb: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [*base_rs1val_sgn] + abstract_comb: + 'simd_imm_val("imm_val", ceil(log(xlen,2))-3)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32zabha.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32zabha.cgf new file mode 100644 index 000000000..754130dfd --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32zabha.cgf @@ -0,0 +1,362 @@ +amoadd.b: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amoadd.b: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amoand.b: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amoand.b: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amoswap.b: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amoswap.b: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amoxor.b: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amoxor.b: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amoor.b: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amoor.b: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amomin.b: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amomin.b: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amominu.b: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amominu.b: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amomax.b: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amomax.b: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amomaxu.b: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amomaxu.b: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amocas.b: + config: + - check ISA:=regex(.*I.*A.*Zabha.*Zacas.*) + mnemonics: + amocas.b: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *zacas_op_comb + val_comb: + <<: [*base_rs1val_sgn, *base_rs2val_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + + +amoadd.h: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amoadd.h: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amoand.h: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amoand.h: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amoswap.h: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amoswap.h: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amoxor.h: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amoxor.h: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amoor.h: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amoor.h: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amomin.h: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amomin.h: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amominu.h: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amominu.h: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amomax.h: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amomax.h: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amomaxu.h: + config: + - check ISA:=regex(.*I.*A.*Zabha.*) + mnemonics: + amomaxu.h: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +amocas.h: + config: + - check ISA:=regex(.*I.*A.*Zabha.*Zacas.*) + mnemonics: + amocas.h: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *zacas_op_comb + val_comb: + <<: [*base_rs1val_sgn, *base_rs2val_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32zacas.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32zacas.cgf new file mode 100644 index 000000000..70935c46f --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv32zacas.cgf @@ -0,0 +1,36 @@ +# cover group format file for Zacas extension +amocas.w: + config: + - check ISA:=regex(.*Zacas.*) + mnemonics: + amocas.w: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *zacas_op_comb + val_comb: + <<: [*base_rs1val_sgn, *base_rs2val_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +amocas.d_32: + config: + - check ISA:=regex(.*Zacas.*) + mnemonics: + amocas.d_32: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *zacas_op_comb + val_comb: + <<: [*zacas_dcas_rs1val_sgn, *zacas_dcas_rs2val_sgn, *rfmt_val_comb_sgn] + abstract_comb: + <<: [*zacas64_rs1val_walking_sgn, *zacas64_rs2val_walking_sgn] diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv64i.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv64i.cgf new file mode 100644 index 000000000..0a4a816dc --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv64i.cgf @@ -0,0 +1,1003 @@ +# For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore + +fence: + config: + - check ISA:=regex(.*I.*) + mnemonics: + fence: 0 + +addi: + config: + - check ISA:=regex(.*I.*) + mnemonics: + addi: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +slti: + config: + - check ISA:=regex(.*I.*) + mnemonics: + slti: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +sltiu: + config: + - check ISA:=regex(.*I.*) + mnemonics: + sltiu: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [*ifmt_val_comb_unsgn , *base_rs1val_unsgn , *ifmt_base_immval_unsgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)],signed=False)': 0 + <<: [*rs1val_walking_unsgn, *ifmt_immval_walking_unsgn] + +andi: + config: + - check ISA:=regex(.*I.*) + mnemonics: + andi: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +ori: + config: + - check ISA:=regex(.*I.*) + mnemonics: + ori: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +xori: + config: + - check ISA:=regex(.*I.*) + mnemonics: + xori: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [*ifmt_val_comb_sgn , *base_rs1val_sgn , *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +slli: + config: + - check ISA:=regex(.*I.*) + mnemonics: + slli: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: *ifmt_base_shift + abstract_comb: + 'sp_dataset(xlen,["rs1_val"])': 0 + <<: [*rs1val_walking] + 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 + 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 + +srai: + config: + - check ISA:=regex(.*I.*) + mnemonics: + srai: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: *ifmt_base_shift + abstract_comb: + 'sp_dataset(xlen,["rs1_val"])': 0 + <<: [*rs1val_walking] + 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 + 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 + +srli: + config: + - check ISA:=regex(.*I.*) + mnemonics: + srli: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: *ifmt_base_shift + abstract_comb: + 'sp_dataset(xlen,["rs1_val"])': 0 + <<: [*rs1val_walking] + 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 + 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 + +add: + config: + - check ISA:=regex(.*I.*) + mnemonics: + add: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +sub: + config: + - check ISA:=regex(.*I.*) + mnemonics: + sub: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +slt: + config: + - check ISA:=regex(.*I.*) + mnemonics: + slt: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +sltu: + config: + - check ISA:=regex(.*I.*) + mnemonics: + sltu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'sp_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + +and: + config: + - check ISA:=regex(.*I.*) + mnemonics: + and: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +or: + config: + - check ISA:=regex(.*I.*) + mnemonics: + or: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +xor: + config: + - check ISA:=regex(.*I.*) + mnemonics: + xor: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +sll: + config: + - check ISA:=regex(.*I.*) + mnemonics: + sll: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: *rfmt_base_shift + abstract_comb: + <<: [*rs1val_walking] + 'sp_dataset(xlen,var_lst=["rs1_val"])': 0 + 'walking_ones("rs2_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(xlen,2)), False)': 0 + 'alternate("rs2_val", ceil(log(xlen,2)), False)': 0 + +srl: + config: + - check ISA:=regex(.*I.*) + mnemonics: + srl: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: *rfmt_base_shift + abstract_comb: + <<: [*rs1val_walking] + 'sp_dataset(xlen,var_lst=["rs1_val"])': 0 + 'walking_ones("rs2_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(xlen,2)), False)': 0 + 'alternate("rs2_val", ceil(log(xlen,2)), False)': 0 + +sra: + config: + - check ISA:=regex(.*I.*) + mnemonics: + sra: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: *rfmt_base_shift + abstract_comb: + <<: [*rs1val_walking] + 'sp_dataset(xlen,var_lst=["rs1_val"])': 0 + 'walking_ones("rs2_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(xlen,2)), False)': 0 + 'alternate("rs2_val", ceil(log(xlen,2)), False)': 0 + +beq: + config: + - check ISA:=regex(.*I.*) + mnemonics: + beq: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *bfmt_base_branch_val_align_sgn + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + 'sp_dataset(xlen)': 0 + +bge: + config: + - check ISA:=regex(.*I.*) + mnemonics: + bge: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *bfmt_base_branch_val_align_sgn + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + 'sp_dataset(xlen)': 0 + +bgeu: + config: + - check ISA:=regex(.*I.*) + mnemonics: + bgeu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *bfmt_base_branch_val_align_unsgn + abstract_comb: + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + 'sp_dataset(xlen,signed=False)': 0 + +blt: + config: + - check ISA:=regex(.*I.*) + mnemonics: + blt: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *bfmt_base_branch_val_align_sgn + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + 'sp_dataset(xlen)': 0 + +bltu: + config: + - check ISA:=regex(.*I.*) + mnemonics: + bltu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *bfmt_base_branch_val_align_unsgn + abstract_comb: + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + 'sp_dataset(xlen,signed=False)': 0 + +bne: + config: + - check ISA:=regex(.*I.*) + mnemonics: + bne: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *bfmt_base_branch_val_align_sgn + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + 'sp_dataset(xlen)': 0 + +lhu-align: + config: + - check ISA:=regex(.*I.*) + mnemonics: + lhu: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'ea_align == 2 and (imm_val % 4) == 0': 0 + 'ea_align == 2 and (imm_val % 4) == 1': 0 + 'ea_align == 2 and (imm_val % 4) == 2': 0 + 'ea_align == 2 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + +lh-align: + config: + - check ISA:=regex(.*I.*) + mnemonics: + lh: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'ea_align == 2 and (imm_val % 4) == 0': 0 + 'ea_align == 2 and (imm_val % 4) == 1': 0 + 'ea_align == 2 and (imm_val % 4) == 2': 0 + 'ea_align == 2 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + +lbu-align: + config: + - check ISA:=regex(.*I.*) + mnemonics: + lbu: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'ea_align == 2 and (imm_val % 4) == 0': 0 + 'ea_align == 2 and (imm_val % 4) == 1': 0 + 'ea_align == 2 and (imm_val % 4) == 2': 0 + 'ea_align == 2 and (imm_val % 4) == 3': 0 + 'ea_align == 1 and (imm_val % 4) == 0': 0 + 'ea_align == 1 and (imm_val % 4) == 1': 0 + 'ea_align == 1 and (imm_val % 4) == 2': 0 + 'ea_align == 1 and (imm_val % 4) == 3': 0 + 'ea_align == 3 and (imm_val % 4) == 0': 0 + 'ea_align == 3 and (imm_val % 4) == 1': 0 + 'ea_align == 3 and (imm_val % 4) == 2': 0 + 'ea_align == 3 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + +lb-align: + config: + - check ISA:=regex(.*I.*) + mnemonics: + lb: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'ea_align == 2 and (imm_val % 4) == 0': 0 + 'ea_align == 2 and (imm_val % 4) == 1': 0 + 'ea_align == 2 and (imm_val % 4) == 2': 0 + 'ea_align == 2 and (imm_val % 4) == 3': 0 + 'ea_align == 1 and (imm_val % 4) == 0': 0 + 'ea_align == 1 and (imm_val % 4) == 1': 0 + 'ea_align == 1 and (imm_val % 4) == 2': 0 + 'ea_align == 1 and (imm_val % 4) == 3': 0 + 'ea_align == 3 and (imm_val % 4) == 0': 0 + 'ea_align == 3 and (imm_val % 4) == 1': 0 + 'ea_align == 3 and (imm_val % 4) == 2': 0 + 'ea_align == 3 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + +lw-align: + config: + - check ISA:=regex(.*I.*) + mnemonics: + lw: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + + +sh-align: + config: + - check ISA:=regex(.*I.*) + mnemonics: + sh: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + op_comb: + 'rs1 != rs2': 0 + val_comb: + <<: [ *base_rs2val_sgn] + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'ea_align == 2 and (imm_val % 4) == 0': 0 + 'ea_align == 2 and (imm_val % 4) == 1': 0 + 'ea_align == 2 and (imm_val % 4) == 2': 0 + 'ea_align == 2 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + abstract_comb: + <<: [*rs2val_walking] + +sb-align: + config: + - check ISA:=regex(.*I.*) + mnemonics: + sb: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'ea_align == 2 and (imm_val % 4) == 0': 0 + 'ea_align == 2 and (imm_val % 4) == 1': 0 + 'ea_align == 2 and (imm_val % 4) == 2': 0 + 'ea_align == 2 and (imm_val % 4) == 3': 0 + 'ea_align == 1 and (imm_val % 4) == 0': 0 + 'ea_align == 1 and (imm_val % 4) == 1': 0 + 'ea_align == 1 and (imm_val % 4) == 2': 0 + 'ea_align == 1 and (imm_val % 4) == 3': 0 + 'ea_align == 3 and (imm_val % 4) == 0': 0 + 'ea_align == 3 and (imm_val % 4) == 1': 0 + 'ea_align == 3 and (imm_val % 4) == 2': 0 + 'ea_align == 3 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +sw-align: + config: + - check ISA:=regex(.*I.*) + mnemonics: + sw: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +auipc: + config: + - check ISA:=regex(.*I.*) + mnemonics: + auipc: 0 + rd: + <<: *all_regs + val_comb: + 'imm_val == 0': 0 + 'imm_val > 0': 0 + 'imm_val == ((2**20)-1)': 0 + abstract_comb: + 'sp_dataset(20,["imm_val"],signed=False)': 0 + 'walking_ones("imm_val", 20, False)': 0 + 'walking_zeros("imm_val", 20, False)': 0 + 'alternate("imm_val", 20, False)': 0 + +lui: + config: + - check ISA:=regex(.*I.*) + mnemonics: + lui: 0 + rd: + <<: *all_regs + val_comb: + 'imm_val == 0': 0 + 'imm_val > 0': 0 + 'imm_val == ((2**20)-1)': 0 + abstract_comb: + 'sp_dataset(20,["imm_val"],signed=False)': 0 + 'walking_ones("imm_val", 20, False)': 0 + 'walking_zeros("imm_val", 20, False)': 0 + 'alternate("imm_val", 20, False)': 0 + +jal: + config: + - check ISA:=regex(.*I.*) + mnemonics: + jal: 0 + rd: + <<: *all_regs + val_comb: + 'imm_val < 0' : 0 + 'imm_val > 0': 0 + 'imm_val == (-(2**(18)))': 0 + 'imm_val == ((2**(18)))': 0 + +jalr: + config: + - check ISA:=regex(.*I.*) + mnemonics: + jalr: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'imm_val > 0': 0 + 'imm_val < 0': 0 + abstract_comb: + <<: *ifmt_immval_walking + +lwu-align: + config: + - check ISA:=regex(.*RV64.*I.*) + mnemonics: + lwu: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1': 0 + 'ea_align == 0 and (imm_val % 4) == 2': 0 + 'ea_align == 0 and (imm_val % 4) == 3': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + +ld-align: + config: + - check ISA:=regex(.*RV64.*I.*) + mnemonics: + ld: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 8) == 0': 0 + 'ea_align == 0 and (imm_val % 8) == 1': 0 + 'ea_align == 0 and (imm_val % 8) == 2': 0 + 'ea_align == 0 and (imm_val % 8) == 3': 0 + 'ea_align == 0 and (imm_val % 8) == 4': 0 + 'ea_align == 0 and (imm_val % 8) == 5': 0 + 'ea_align == 0 and (imm_val % 8) == 6': 0 + 'ea_align == 0 and (imm_val % 8) == 7': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + +sd-align: + config: + - check ISA:=regex(.*RV64.*I.*) + mnemonics: + sd: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'ea_align == 0 and (imm_val % 8) == 0': 0 + 'ea_align == 0 and (imm_val % 8) == 1': 0 + 'ea_align == 0 and (imm_val % 8) == 2': 0 + 'ea_align == 0 and (imm_val % 8) == 3': 0 + 'ea_align == 0 and (imm_val % 8) == 4': 0 + 'ea_align == 0 and (imm_val % 8) == 5': 0 + 'ea_align == 0 and (imm_val % 8) == 6': 0 + 'ea_align == 0 and (imm_val % 8) == 7': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +addiw: + config: + - check ISA:=regex(.*RV64.*I.*) + mnemonics: + addiw: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +slliw: + config: + - check ISA:=regex(.*RV64.*I.*) + mnemonics: + slliw: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: *ifmt_base_shift_32w + abstract_comb: + 'sp_dataset(xlen,["rs1_val"])': 0 + <<: [*rs1val_walking] + 'walking_ones("imm_val", 5, False)': 0 + 'walking_zeros("imm_val", 5, False)': 0 + 'alternate("imm_val", 5, False)': 0 + +srliw: + config: + - check ISA:=regex(.*RV64.*I.*) + mnemonics: + srliw: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: *ifmt_base_shift_32w + abstract_comb: + 'sp_dataset(xlen,["rs1_val"])': 0 + <<: [*rs1val_walking] + 'walking_ones("imm_val", 5, False)': 0 + 'walking_zeros("imm_val", 5, False)': 0 + 'alternate("imm_val", 5, False)': 0 + +sraiw: + config: + - check ISA:=regex(.*RV64.*I.*) + mnemonics: + sraiw: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: *ifmt_base_shift_32w + abstract_comb: + 'sp_dataset(xlen,["rs1_val"])': 0 + <<: [*rs1val_walking] + 'walking_ones("imm_val", 5, False)': 0 + 'walking_zeros("imm_val", 5, False)': 0 + 'alternate("imm_val", 5, False)': 0 + +addw: + config: + - check ISA:=regex(.*RV64.*I.*) + mnemonics: + addw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +subw: + config: + - check ISA:=regex(.*RV64.*I.*) + mnemonics: + subw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +sllw: + config: + - check ISA:=regex(.*RV64.*I.*) + mnemonics: + sllw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: *rfmt_base_shift + abstract_comb: + <<: [*rs1val_walking] + 'sp_dataset(xlen,var_lst=["rs1_val"])': 0 + 'walking_ones("rs2_val", 5, False)': 0 + 'walking_zeros("rs2_val", 5, False)': 0 + 'alternate("rs2_val", 5, False)': 0 + +srlw: + config: + - check ISA:=regex(.*RV64.*I.*) + mnemonics: + srlw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: *rfmt_base_shift + abstract_comb: + <<: [*rs1val_walking] + 'sp_dataset(xlen,var_lst=["rs1_val"])': 0 + 'walking_ones("rs2_val", 5, False)': 0 + 'walking_zeros("rs2_val", 5, False)': 0 + 'alternate("rs2_val", 5, False)': 0 +sraw: + config: + - check ISA:=regex(.*RV64.*I.*) + mnemonics: + sraw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: *rfmt_base_shift + abstract_comb: + <<: [*rs1val_walking] + 'sp_dataset(xlen,var_lst=["rs1_val"])': 0 + 'walking_ones("rs2_val", 5, False)': 0 + 'walking_zeros("rs2_val", 5, False)': 0 + 'alternate("rs2_val", 5, False)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv64i_b.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv64i_b.cgf new file mode 100644 index 000000000..5cd7cca4c --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv64i_b.cgf @@ -0,0 +1,973 @@ +add.uw: + config: + - check ISA:=regex(.*RV64.*I.*B.*) + - check ISA:=regex(.*RV64.*I.*Zba.*) + mnemonics: + add.uw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'bitmanip_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + +sh1add: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zba.*) + mnemonics: + sh1add: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'bitmanip_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + + +sh1add.uw: + config: + - check ISA:=regex(.*RV64.*I.*B.*) + - check ISA:=regex(.*RV64.*I.*Zba.*) + mnemonics: + sh1add.uw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'bitmanip_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + +sh2add: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zba.*) + mnemonics: + sh2add: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'bitmanip_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +sh2add.uw: + config: + - check ISA:=regex(.*RV64.*I.*B.*) + - check ISA:=regex(.*RV64.*I.*Zba.*) + mnemonics: + sh2add.uw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'bitmanip_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + +sh3add: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zba.*) + mnemonics: + sh3add: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'bitmanip_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +sh3add.uw: + config: + - check ISA:=regex(.*RV64.*I.*B.*) + - check ISA:=regex(.*RV64.*I.*Zba.*) + mnemonics: + sh3add.uw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'bitmanip_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + +slli.uw: + config: + - check ISA:=regex(.*RV64.*I.*B.*) + - check ISA:=regex(.*RV64.*I.*Zba.*) + mnemonics: + slli.uw: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'bitmanip_dataset(xlen,["rs1_val"],signed=False)': 0 + <<: [*rs1val_walking_unsgn] + 'walking_ones("imm_val", 5, False)': 0 + 'walking_zeros("imm_val", 5, False)': 0 + 'alternate("imm_val", 5, False)': 0 + +xnor: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + - check ISA:=regex(.*I.*Zbkb.*) + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zks.*) + mnemonics: + xnor: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'bitmanip_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + +zext.h_64: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + mnemonics: + zext.h: 0 + base_op: packw + p_op_cond: rs2 == x0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'rs1_val == 0': 0 + 'rs1_val == 0x80': 0 + 'rs1_val == 0xFF80': 0 + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 + 'uniform_random(20, 100, ["rs1_val"], [xlen])': 0 +andn: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + - check ISA:=regex(.*I.*Zbkb.*) + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zks.*) + mnemonics: + andn: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + 'uniform_random(5, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + 'bitmanip_dataset(xlen,["rs1_val","rs2_val"],False)': 0 + +clz: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + mnemonics: + clz: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + <<: [*rs1val_walking_unsgn] + 'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0 + 'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0 + 'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0 + 'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0 + + +clzw: + config: + - check ISA:=regex(.*RV64.*I.*B.*) + - check ISA:=regex(.*RV64.*I.*Zbb.*) + mnemonics: + clzw: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + <<: [*rs1val_walking_unsgn] + 'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0 + 'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0 + 'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0 + 'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0 + +ctz: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + mnemonics: + ctz: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + <<: [*rs1val_walking_unsgn] + 'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0 + 'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0 + 'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0 + 'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0 + +ctzw: + config: + - check ISA:=regex(.*RV64.*I.*B.*) + - check ISA:=regex(.*RV64.*I.*Zbb.*) + mnemonics: + ctzw: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + <<: [*rs1val_walking_unsgn] + 'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0 + 'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0 + 'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0 + 'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0 + + +cpop: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + mnemonics: + cpop: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + <<: [*rs1val_walking_unsgn] + 'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0 + 'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0 + 'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0 + 'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0 + +cpopw: + config: + - check ISA:=regex(.*RV64.*I.*B.*) + - check ISA:=regex(.*RV64.*I.*Zbb.*) + mnemonics: + cpopw: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + <<: [*rs1val_walking_unsgn] + 'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0 + 'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0 + 'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0 + 'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0 + +max: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + mnemonics: + max: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'bitmanip_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +maxu: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + mnemonics: + maxu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'bitmanip_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + +min: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + mnemonics: + min: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'bitmanip_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +minu: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + mnemonics: + minu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'bitmanip_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + +orcb_64: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + mnemonics: + orc.b: 0 + base_op: gorci + p_op_cond: imm_val == 7 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'rs1_val == 0x102040801020408': 0 + 'rs1_val == 0x204080102040801': 0 + 'rs1_val == 0x408010204080102': 0 + 'rs1_val == 0x801020408010204': 0 + abstract_comb: + <<: [*rs1val_walking_unsgn] + + +orn: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + - check ISA:=regex(.*I.*Zbkb.*) + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zks.*) + mnemonics: + orn: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'bitmanip_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + +rev8: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + - check ISA:=regex(.*I.*Zbkb.*) + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zks.*) + mnemonics: + rev8: 0 + base_op: grevi + p_op_cond: imm_val == 56 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'rs1_val == 0x102040801020408': 0 + 'rs1_val == 0x204080102040801': 0 + 'rs1_val == 0x408010204080102': 0 + 'rs1_val == 0x801020408010204': 0 + abstract_comb: + 'leading_ones(64, ["rs1_val"], [32])': 0 + 'trailing_ones(64, ["rs1_val"], [32])': 0 + 'leading_zeros(64, ["rs1_val"], [32])': 0 + 'trailing_zeros(64, ["rs1_val"], [32])': 0 + 'bitmanip_dataset(xlen,["rs1_val"],signed=False)': 0 + +rol: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + - check ISA:=regex(.*I.*Zbkb.*) + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zks.*) + mnemonics: + rol: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'leading_ones(64, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'trailing_ones(64, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'leading_zeros(64, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'trailing_zeros(64, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + +rolw: + config: + - check ISA:=regex(.*RV64.*I.*B.*) + - check ISA:=regex(.*RV64.*I.*Zbb.*) + - check ISA:=regex(.*RV64.*I.*Zbkb.*) + - check ISA:=regex(.*RV64.*I.*Zk.*) + - check ISA:=regex(.*RV64.*I.*Zkn.*) + - check ISA:=regex(.*RV64.*I.*Zks.*) + mnemonics: + rolw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'leading_ones(64, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'trailing_ones(64, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'leading_zeros(64, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'trailing_zeros(64, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + +ror: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + - check ISA:=regex(.*I.*Zbkb.*) + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zks.*) + mnemonics: + ror: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'leading_ones(64, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'trailing_ones(64, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'leading_zeros(64, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'trailing_zeros(64, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + +rori: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + - check ISA:=regex(.*I.*Zbkb.*) + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zks.*) + mnemonics: + rori: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'leading_ones(64, ["rs1_val","imm_val"],[32,5])': 0 + 'trailing_ones(64, ["rs1_val","imm_val"],[32,5])': 0 + 'leading_zeros(64, ["rs1_val","imm_val"],[32,5])': 0 + 'trailing_zeros(64, ["rs1_val","imm_val"],[32,5])': 0 + + +roriw: + config: + - check ISA:=regex(.*RV64.*I.*B.*) + - check ISA:=regex(.*RV64.*I.*Zbb.*) + - check ISA:=regex(.*RV64.*I.*Zbkb.*) + - check ISA:=regex(.*RV64.*I.*Zk.*) + - check ISA:=regex(.*RV64.*I.*Zkn.*) + - check ISA:=regex(.*RV64.*I.*Zks.*) + mnemonics: + roriw: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'leading_ones(64, ["rs1_val","imm_val"],[32,5])': 0 + 'trailing_ones(64, ["rs1_val","imm_val"],[32,5])': 0 + 'leading_zeros(64, ["rs1_val","imm_val"],[32,5])': 0 + 'trailing_zeros(64, ["rs1_val","imm_val"],[32,5])': 0 + +rorw: + config: + - check ISA:=regex(.*RV64.*I.*B.*) + - check ISA:=regex(.*RV64.*I.*Zbb.*) + - check ISA:=regex(.*RV64.*I.*Zbkb.*) + - check ISA:=regex(.*RV64.*I.*Zk.*) + - check ISA:=regex(.*RV64.*I.*Zkn.*) + - check ISA:=regex(.*RV64.*I.*Zks.*) + mnemonics: + rorw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'leading_ones(64, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'trailing_ones(64, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'leading_zeros(64, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + 'trailing_zeros(64, ["rs1_val","rs2_val"],[xlen,xlen])': 0 + + +sext.b: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + mnemonics: + sext.b: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'rs1_val == 0': 0 + 'rs1_val == 0x8000': 0 + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 + 'uniform_random(20, 100, ["rs1_val"], [xlen])': 0 + +sext.h: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbb.*) + mnemonics: + sext.h: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'rs1_val == 0': 0 + 'rs1_val == 0x80': 0 + 'rs1_val == 0xff80': 0 + abstract_comb: + 'walking_ones("rs1_val", xlen, False)': 0 + 'walking_zeros("rs1_val", xlen, False)': 0 + 'uniform_random(20, 100, ["rs1_val"], [xlen])': 0 + +clmul: + config: + - check ISA:=regex(.*I.*Zbc.*) + - check ISA:=regex(.*I.*Zbkc.*) + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zks.*) + mnemonics: + clmul: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + 'rs1_val==1 and rs2_val==1': 0 + 'rs1_val==1 and rs2_val==0': 0 + 'rs1_val==1 and rs2_val==0x1000': 0 + 'rs1_val==0 and rs2_val==1': 0 + 'rs1_val==0 and rs2_val==0': 0 + 'rs1_val==0 and rs2_val==0x1000': 0 + abstract_comb: + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + +clmulh: + config: + - check ISA:=regex(.*I.*Zbc.*) + - check ISA:=regex(.*I.*Zbkc.*) + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zks.*) + mnemonics: + clmulh: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + 'rs1_val==1 and rs2_val==1': 0 + 'rs1_val==1 and rs2_val==0': 0 + 'rs1_val==1 and rs2_val==0x1000': 0 + 'rs1_val==0 and rs2_val==1': 0 + 'rs1_val==0 and rs2_val==0': 0 + 'rs1_val==0 and rs2_val==0x1000': 0 + abstract_comb: + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + + +clmulr: + config: + - check ISA:=regex(.*I.*Zbc.*) + mnemonics: + clmulr: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + 'rs1_val==1 and rs2_val==1': 0 + 'rs1_val==1 and rs2_val==0': 0 + 'rs1_val==1 and rs2_val==0x1000': 0 + 'rs1_val==0 and rs2_val==1': 0 + 'rs1_val==0 and rs2_val==0': 0 + 'rs1_val==0 and rs2_val==0x1000': 0 + abstract_comb: + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0 + +bclr: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbs.*) + mnemonics: + bclr: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: +# 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs2_val", xlen )': 0 + 'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0 + 'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0 + 'leading_ones(64, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_ones(64, ["rs1_val", "rs2_val"], [32,5])': 0 + 'leading_zeros(64, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_zeros(64, ["rs1_val", "rs2_val"], [32,5])': 0 + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + + +bclri: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbs.*) + mnemonics: + bclri: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: +# 'xlenlim("rs1_val", xlen)': 0 + 'leading_ones(64, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_ones(64, ["rs1_val", "imm_val"], [32,5])': 0 + 'leading_zeros(64, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_zeros(64, ["rs1_val", "imm_val"], [32,5])': 0 + + +bext: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbs.*) + mnemonics: + bext: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: +# 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs2_val", xlen )': 0 + 'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0 + 'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0 + 'leading_ones(64, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_ones(64, ["rs1_val", "rs2_val"], [32,5])': 0 + 'leading_zeros(64, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_zeros(64, ["rs1_val", "rs2_val"], [32,5])': 0 + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + + +bexti: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbs.*) + mnemonics: + bexti: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: +# 'xlenlim("rs1_val", xlen)': 0 + 'leading_ones(64, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_ones(64, ["rs1_val", "imm_val"], [32,5])': 0 + 'leading_zeros(64, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_zeros(64, ["rs1_val", "imm_val"], [32,5])': 0 + + +binv: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbs.*) + mnemonics: + binv: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: +# 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs2_val", xlen )': 0 + 'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0 + 'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0 + 'leading_ones(64, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_ones(64, ["rs1_val", "rs2_val"], [32,5])': 0 + 'leading_zeros(64, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_zeros(64, ["rs1_val", "rs2_val"], [32,5])': 0 + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + + +binvi: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbs.*) + mnemonics: + binvi: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: +# 'xlenlim("rs1_val", xlen)': 0 + 'leading_ones(64, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_ones(64, ["rs1_val", "imm_val"], [32,5])': 0 + 'leading_zeros(64, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_zeros(64, ["rs1_val", "imm_val"], [32,5])': 0 + +bset: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbs.*) + mnemonics: + bset: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: +# 'xlenlim("rs1_val", xlen)': 0 +# 'xlenlim("rs2_val", xlen )': 0 + 'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0 + 'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0 + 'leading_ones(64, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_ones(64, ["rs1_val", "rs2_val"], [32,5])': 0 + 'leading_zeros(64, ["rs1_val", "rs2_val"], [32,5])': 0 + 'trailing_zeros(64, ["rs1_val", "rs2_val"], [32,5])': 0 + <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn] + + + +bseti: + config: + - check ISA:=regex(.*I.*B.*) + - check ISA:=regex(.*I.*Zbs.*) + mnemonics: + bseti: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: +# 'xlenlim("rs1_val", xlen)': 0 + 'leading_ones(64, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_ones(64, ["rs1_val", "imm_val"], [32,5])': 0 + 'leading_zeros(64, ["rs1_val", "imm_val"], [32,5])': 0 + 'trailing_zeros(64, ["rs1_val", "imm_val"], [32,5])': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv64i_fencei.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv64i_fencei.cgf new file mode 100644 index 000000000..3397e5a00 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv64i_fencei.cgf @@ -0,0 +1,8 @@ + +fencei: + config: + - check ISA:=regex(.*I.*Zifencei.*) + mnemonics: + fence.i: 0 + + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv64i_k.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv64i_k.cgf new file mode 100644 index 000000000..87d34b960 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv64i_k.cgf @@ -0,0 +1,517 @@ +# For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore + + +brev8: + config: + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zks.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zbkb.*) + mnemonics: + brev8: 0 + base_op: grevi + p_op_cond: imm_val == 7 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + 'rs1_val == 0x102040801020408': 0 + 'rs1_val == 0x204080102040801': 0 + 'rs1_val == 0x408010204080102': 0 + 'rs1_val == 0x801020408010204': 0 + abstract_comb: + 'leading_ones(64, ["rs1_val"], [32])': 0 + 'trailing_ones(64, ["rs1_val"], [32])': 0 + 'leading_zeros(64, ["rs1_val"], [32])': 0 + 'trailing_zeros(64, ["rs1_val"], [32])': 0 + + +pack: + config: + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zks.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zbkb.*) + mnemonics: + pack: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'leading_ones(64, ["rs1_val","rs2_val"], [64,64])': 0 + 'trailing_ones(64, ["rs1_val","rs2_val"], [64,64])': 0 + 'leading_zeros(64, ["rs1_val","rs2_val"], [64,64])': 0 + 'trailing_zeros(64, ["rs1_val","rs2_val"], [64,64])': 0 + +packh: + config: + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zks.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zbkb.*) + mnemonics: + packh: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'leading_ones(64, ["rs1_val","rs2_val"], [64,64])': 0 + 'trailing_ones(64, ["rs1_val","rs2_val"], [64,64])': 0 + 'leading_zeros(64, ["rs1_val","rs2_val"], [64,64])': 0 + 'trailing_zeros(64, ["rs1_val","rs2_val"], [64,64])': 0 + +packw: + config: + - check ISA:=regex(.*RV64.*I.*Zk.*) + - check ISA:=regex(.*RV64.*I.*Zks.*) + - check ISA:=regex(.*RV64.*I.*Zkn.*) + - check ISA:=regex(.*RV64.*I.*Zbkb.*) + mnemonics: + packw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'leading_ones(64, ["rs1_val","rs2_val"], [64,64])': 0 + 'trailing_ones(64, ["rs1_val","rs2_val"], [64,64])': 0 + 'leading_zeros(64, ["rs1_val","rs2_val"], [64,64])': 0 + 'trailing_zeros(64, ["rs1_val","rs2_val"], [64,64])': 0 + +xperm4: + config: + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zks.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zbkx.*) + mnemonics: + xperm4: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [64, 64])': 0 + 'leading_ones(64, ["rs1_val","rs2_val"], [64,64])': 0 + 'trailing_ones(64, ["rs1_val","rs2_val"], [64,64])': 0 + 'leading_zeros(64, ["rs1_val","rs2_val"], [64,64])': 0 + 'trailing_zeros(64, ["rs1_val","rs2_val"], [64,64])': 0 + +xperm8: + config: + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zks.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zbkx.*) + mnemonics: + xperm8: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [64, 64])': 0 + 'walking_ones("rs1_val", 64, False)': 0 + 'walking_ones("rs2_val", 64, False)': 0 + 'trailing_ones(64, ["rs1_val","rs2_val"], [64,64],False)': 0 + 'leading_zeros(64, ["rs1_val","rs2_val"], [64,64],False)': 0 + 'trailing_zeros(64, ["rs1_val","rs2_val"], [64,64],False)': 0 + + +aes64ds: + config: + - check ISA:=regex(.*RV64.*I.*Zk.*) + - check ISA:=regex(.*RV64.*I.*Zkn.*) + - check ISA:=regex(.*RV64.*I.*Zknd.*) + mnemonics: + aes64ds: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'byte_count(64, ["rs1_val","rs2_val"])': 0 + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [64, 64])': 0 + +aes64dsm: + config: + - check ISA:=regex(.*RV64.*I.*Zk.*) + - check ISA:=regex(.*RV64.*I.*Zkn.*) + - check ISA:=regex(.*RV64.*I.*Zknd.*) + mnemonics: + aes64dsm: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'byte_count(64, ["rs1_val","rs2_val"])': 0 + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [64, 64])': 0 + +aes64es: + config: + - check ISA:=regex(.*RV64.*I.*Zk.*) + - check ISA:=regex(.*RV64.*I.*Zkn.*) + - check ISA:=regex(.*RV64.*I.*Zkne.*) + mnemonics: + aes64es: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'byte_count(64, ["rs1_val","rs2_val"])': 0 + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [64, 64])': 0 + +aes64esm: + config: + - check ISA:=regex(.*RV64.*I.*Zk.*) + - check ISA:=regex(.*RV64.*I.*Zkn.*) + - check ISA:=regex(.*RV64.*I.*Zkne.*) + mnemonics: + aes64esm: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'byte_count(64, ["rs1_val","rs2_val"])': 0 + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [64, 64])': 0 + +aes64im: + config: + - check ISA:=regex(.*RV64.*I.*Zk.*) + - check ISA:=regex(.*RV64.*I.*Zkn.*) + - check ISA:=regex(.*RV64.*I.*Zknd.*) + mnemonics: + aes64im: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'walking_ones("rs1_val", 64, False)': 0 + 'walking_zeros("rs1_val", 64, False)': 0 + 'uniform_random(20, 100, ["rs1_val"], [64])': 0 + +aes64ks1i: + config: + - check ISA:=regex(.*RV64.*I.*Zk.*) + - check ISA:=regex(.*RV64.*I.*Zkn.*) + - check ISA:=regex(.*RV64.*I.*Zknd.*) + - check ISA:=regex(.*RV64.*I.*Zkne.*) + mnemonics: + aes64ks1i: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'byte_count(64, ["rs1_val", "imm_val"], "Y")': 0 + 'uniform_random(20, 100, ["rs1_val","imm_val"], [64, log(10,2)])': 0 + +aes64ks2: + config: + - check ISA:=regex(.*RV64.*I.*Zk.*) + - check ISA:=regex(.*RV64.*I.*Zkn.*) + - check ISA:=regex(.*RV64.*I.*Zknd.*) + - check ISA:=regex(.*RV64.*I.*Zkne.*) + mnemonics: + aes64ks2: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'walking_ones("rs1_val", 64, False)': 0 + 'walking_ones("rs2_val", 64, False)': 0 + 'walking_zeros("rs1_val", 64, False)': 0 + 'walking_zeros("rs2_val", 64, False)': 0 + 'uniform_random(20, 100, ["rs1_val","rs2_val"], [64, 64])': 0 + +sha256sig0: + config: + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zknh.*) + mnemonics: + sha256sig0: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'walking_ones("rs1_val", 64, False)': 0 + 'walking_zeros("rs1_val", 64, False)': 0 + 'uniform_random(20, 100, ["rs1_val"], [64])': 0 + +sha256sig1: + config: + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zknh.*) + mnemonics: + sha256sig1: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'walking_ones("rs1_val", 64, False)': 0 + 'walking_zeros("rs1_val", 64, False)': 0 + 'uniform_random(20, 100, ["rs1_val"], [64])': 0 + +sha256sum0: + config: + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zknh.*) + mnemonics: + sha256sum0: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'walking_ones("rs1_val", 64, False)': 0 + 'walking_zeros("rs1_val", 64, False)': 0 + 'uniform_random(20, 100, ["rs1_val"], [64])': 0 + +sha256sum1: + config: + - check ISA:=regex(.*I.*Zk.*) + - check ISA:=regex(.*I.*Zkn.*) + - check ISA:=regex(.*I.*Zknh.*) + mnemonics: + sha256sum1: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'walking_ones("rs1_val", 64, False)': 0 + 'walking_zeros("rs1_val", 64, False)': 0 + 'uniform_random(20, 100, ["rs1_val"], [64])': 0 + +sha512sig0: + config: + - check ISA:=regex(.*RV64.*I.*Zk.*) + - check ISA:=regex(.*RV64.*I.*Zkn.*) + - check ISA:=regex(.*RV64.*I.*Zknh.*) + mnemonics: + sha512sig0: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'walking_ones("rs1_val", 64, False)': 0 + 'walking_zeros("rs1_val", 64, False)': 0 + 'uniform_random(20, 100, ["rs1_val"], [64])': 0 + +sha512sig1: + config: + - check ISA:=regex(.*RV64.*I.*Zk.*) + - check ISA:=regex(.*RV64.*I.*Zkn.*) + - check ISA:=regex(.*RV64.*I.*Zknh.*) + mnemonics: + sha512sig1: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'walking_ones("rs1_val", 64, False)': 0 + 'walking_zeros("rs1_val", 64, False)': 0 + 'uniform_random(20, 100, ["rs1_val"], [64])': 0 + +sha512sum0: + config: + - check ISA:=regex(.*RV64.*I.*Zk.*) + - check ISA:=regex(.*RV64.*I.*Zkn.*) + - check ISA:=regex(.*RV64.*I.*Zknh.*) + mnemonics: + sha512sum0: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'walking_ones("rs1_val", 64, False)': 0 + 'walking_zeros("rs1_val", 64, False)': 0 + 'uniform_random(20, 100, ["rs1_val"], [64])': 0 + +sha512sum1: + config: + - check ISA:=regex(.*RV64.*I.*Zk.*) + - check ISA:=regex(.*RV64.*I.*Zkn.*) + - check ISA:=regex(.*RV64.*I.*Zknh.*) + mnemonics: + sha512sum1: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'walking_ones("rs1_val", 64, False)': 0 + 'walking_zeros("rs1_val", 64, False)': 0 + 'uniform_random(20, 100, ["rs1_val"], [64])': 0 + +sm3p0: + config: + - check ISA:=regex(.*I.*Zks.*) + - check ISA:=regex(.*I.*Zksh.*) + mnemonics: + sm3p0: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'walking_ones("rs1_val", 64, False)': 0 + 'walking_zeros("rs1_val", 64, False)': 0 + 'uniform_random(20, 100, ["rs1_val"], [64])': 0 + +sm3p1: + config: + - check ISA:=regex(.*I.*Zks.*) + - check ISA:=regex(.*I.*Zksh.*) + mnemonics: + sm3p1: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'walking_ones("rs1_val", 64, False)': 0 + 'walking_zeros("rs1_val", 64, False)': 0 + 'uniform_random(20, 100, ["rs1_val"], [64])': 0 + +sm4ed: + config: + - check ISA:=regex(.*I.*Zks.*) + - check ISA:=regex(.*I.*Zksed.*) + mnemonics: + sm4ed: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'byte_count(64, ["rs1_val","rs2_val","imm_val"], "Y")': 0 + 'uniform_random(20, 100, ["rs1_val","rs2_val","imm_val"], [64, 64, 2])': 0 + +sm4ks: + config: + - check ISA:=regex(.*I.*Zks.*) + - check ISA:=regex(.*I.*Zksed.*) + mnemonics: + sm4ks: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'byte_count(64, ["rs1_val","rs2_val","imm_val"], "Y")': 0 + 'uniform_random(20, 100, ["rs1_val","rs2_val","imm_val"], [64, 64, 2])': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv64i_priv.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv64i_priv.cgf new file mode 100644 index 000000000..8babd6440 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv64i_priv.cgf @@ -0,0 +1,199 @@ +ecall: + config: + - check ISA:=regex(.*I.*); def rvtest_mtrap_routine=True + mnemonics: + ecall: 0 + +ebreak: + config: + - check ISA:=regex(.*I.*); def rvtest_mtrap_routine=True + mnemonics: + ebreak: 0 + +misalign-lh: + cond: check ISA:=regex(.*I.*Zicsr.*) + config: + - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True + - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True + mnemonics: + lh: 0 + val_comb: + 'ea_align == 1': 0 + +misalign-lhu: + config: + - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True + - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*I.*Zicsr.*) + mnemonics: + lhu: 0 + val_comb: + 'ea_align == 1': 0 + +misalign-lwu: + config: + - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True + - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*64.*I.*Zicsr.*) + mnemonics: + lwu: 0 + val_comb: + 'ea_align == 1': 0 + 'ea_align == 2': 0 + 'ea_align == 3': 0 + +misalign-sd: + config: + - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True + - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*64.*I.*Zicsr.*) + mnemonics: + sd: 0 + val_comb: + 'ea_align == 1': 0 + 'ea_align == 2': 0 + 'ea_align == 3': 0 + 'ea_align == 4': 0 + 'ea_align == 5': 0 + 'ea_align == 6': 0 + 'ea_align == 7': 0 + +misalign-ld: + config: + - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True + - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*64.*I.*) + mnemonics: + ld: 0 + val_comb: + 'ea_align == 1': 0 + 'ea_align == 2': 0 + 'ea_align == 3': 0 + 'ea_align == 4': 0 + 'ea_align == 5': 0 + 'ea_align == 6': 0 + 'ea_align == 7': 0 + +misalign-lw: + config: + - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True + - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*I.*Zicsr.*) + mnemonics: + lw: 0 + val_comb: + 'ea_align == 1': 0 + 'ea_align == 2': 0 + 'ea_align == 3': 0 + +misalign-sh: + config: + - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True + - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*I.*Zicsr.*) + mnemonics: + sh: 0 + val_comb: + 'ea_align == 1': 0 + +misalign-sw: + config: + - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True + - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*I.*Zicsr.*) + mnemonics: + sw: 0 + val_comb: + 'ea_align == 1': 0 + 'ea_align == 2': 0 + 'ea_align == 3': 0 + +misalign2-jalr: + config: + - check ISA:=regex(.*I.*C.*) + - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*I.*) + mnemonics: + jalr: 0 + val_comb: + 'ea_align == 2': 0 + +misalign1-jalr: + config: + - check ISA:=regex(.*I.*); def rvtest_mtrap_routine=True + mnemonics: + jalr: 0 + val_comb: + 'ea_align == 1': 0 + +misalign-jal: + config: + - check ISA:=regex(.*I.*C.*) + - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*I.*) + mnemonics: + jal: 0 + val_comb: + 'ea_align == 2': 0 + +misalign-bge: + config: + - check ISA:=regex(.*I.*C.*) + - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*I.*) + mnemonics: + bge: 0 + val_comb: + ' rs1_val>rs2_val and ea_align == 2': 0 + +misalign-bgeu: + config: + - check ISA:=regex(.*I.*C.*) + - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*I.*) + mnemonics: + bgeu: 0 + val_comb: + ' rs1_val>rs2_val and ea_align == 2': 0 + +misalign-blt: + config: + - check ISA:=regex(.*I.*C.*) + - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*I.*) + mnemonics: + blt: 0 + val_comb: + ' rs1_val 0' : 0 + 'imm_val == 1020': 0 + abstract_comb: + 'walking_ones("imm_val", 8,False,scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val", 8,False,scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",8,False,scale_func = lambda x: x*4)': 0 + +clw: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.lw: 0 + rs1: + <<: *c_regs + rd: + <<: *c_regs + op_comb: + 'rs1 == rd': 0 + 'rs1 != rd': 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0 + +cld: + config: + - check ISA:=regex(.*RV64.*I.*C.*) + mnemonics: + c.ld: 0 + rs1: + <<: *c_regs + rd: + <<: *c_regs + op_comb: + 'rs1 == rd': 0 + 'rs1 != rd': 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 + +csw: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.sw: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0 + +csd: + config: + - check ISA:=regex(.*RV64.*I.*C.*) + mnemonics: + c.sd: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 + +cnop: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.nop: 0 + val_comb: + abstract_comb: + <<: *cbimm_val_walking + +caddi: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.addi: 0 + rd: + <<: *all_regs_mx0 + val_comb: + <<: [*base_rs1val_sgn, *cbfmt_immval_sgn, *ifmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",6)])': 0 + <<: [*rs1val_walking, *cbimm_val_walking] + +caddiw: + config: + - check ISA:=regex(.*RV64.*I.*C.*) + mnemonics: + c.addiw: 0 + rd: + <<: *all_regs_mx0 + val_comb: + 'rs1_val == (-2**(xlen-1))': 0 + 'rs1_val == 0': 0 + 'rs1_val == (2**(xlen-1)-1)': 0 + 'rs1_val == 1': 0 + <<: [*cbfmt_immval_sgn, *ifmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",6)])': 0 + 'walking_ones("rs1_val", xlen)': 0 + 'walking_zeros("rs1_val", xlen)': 0 + 'alternate("rs1_val",xlen)': 0 + <<: [*cbimm_val_walking] + +cli: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.li: 0 + rd: + <<: *all_regs + val_comb: + <<: [*cbfmt_immval_sgn] + abstract_comb: + 'walking_ones("imm_val", 6)': 0 + 'walking_zeros("imm_val", 6)': 0 + 'alternate("imm_val", 6)': 0 + +caddi16sp: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.addi16sp: 0 + rd: + x2: 0 + val_comb: + <<: [*base_rs1val_sgn,*ifmt_val_comb_sgn] + 'imm_val == -512': 0 + 'imm_val == 496': 0 + abstract_comb: + <<: [*rs1val_walking] + 'walking_ones("imm_val", 6,True,scale_func = lambda x: x*16)': 0 + 'walking_zeros("imm_val", 6,True,scale_func = lambda x: x*16)': 0 + 'alternate("imm_val",6,True,scale_func = lambda x: x*16)': 0 + +clui: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.lui: 0 + rd: + x0: 0 + x1: 0 + x3: 0 + x4: 0 + x5: 0 + x6: 0 + x7: 0 + x8: 0 + x9: 0 + x10: 0 + x11: 0 + x12: 0 + x13: 0 + x14: 0 + x15: 0 + x16: 0 + x17: 0 + x18: 0 + x19: 0 + x20: 0 + x21: 0 + x22: 0 + x23: 0 + x24: 0 + x25: 0 + x26: 0 + x27: 0 + x28: 0 + x29: 0 + x30: 0 + x31: 0 + + val_comb: + 'rs1_val > 0 and imm_val > 32': 0 + 'rs1_val > 0 and imm_val < 32 and imm_val !=0 ': 0 + 'rs1_val < 0 and imm_val > 32': 0 + 'rs1_val < 0 and imm_val < 32 and imm_val !=0 ': 0 + abstract_comb: + 'walking_ones("imm_val", 6, False)': 0 + 'walking_zeros("imm_val", 6, False)': 0 + 'alternate("imm_val", 6, False)': 0 + +csrli: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.srli: 0 + rs1: + <<: *c_regs + val_comb: + 'rs1_val < 0 and imm_val < xlen': 0 + 'rs1_val > 0 and imm_val < xlen': 0 + 'rs1_val == imm_val and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == 0 and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == 1 and imm_val != 0 and imm_val < xlen': 0 + abstract_comb: + 'sp_dataset(xlen,["rs1_val"])': 0 + <<: [*rs1val_walking] + 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 + 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 + +csrai: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.srai: 0 + rs1: + <<: *c_regs + val_comb: + 'rs1_val < 0 and imm_val < xlen': 0 + 'rs1_val > 0 and imm_val < xlen': 0 + 'rs1_val == imm_val and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == 0 and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == 1 and imm_val != 0 and imm_val < xlen': 0 + abstract_comb: + 'sp_dataset(xlen,["rs1_val"])': 0 + <<: [*rs1val_walking] + 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 + 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 + +candi: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.andi: 0 + rs1: + <<: *c_regs + val_comb: + <<: [*base_rs1val_sgn,*cbfmt_immval_sgn,*ifmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",6)])': 0 + <<: [*rs1val_walking, *cbimm_val_walking] + +csub: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.sub: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn, *base_rs2val_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking,*rs2val_walking] + +cxor: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.xor: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn, *base_rs2val_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking,*rs2val_walking] + +cor: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.or: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn,*base_rs2val_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking,*rs2val_walking] + +cand: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.and: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn,*base_rs2val_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking,*rs2val_walking] + +csubw: + config: + - check ISA:=regex(.*RV64.*I.*C.*) + mnemonics: + c.subw: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn, *base_rs2val_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking,*rs2val_walking] + +caddw: + config: + - check ISA:=regex(.*RV64.*I.*C.*) + mnemonics: + c.addw: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn, *base_rs2val_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking,*rs2val_walking] + +cj: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.j: 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val < 0': 0 + abstract_comb: + 'walking_ones("imm_val", 11,fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030),scale_func = lambda x: x*2)': 0 + 'walking_zeros("imm_val", 11,fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030),scale_func = lambda x: x*2)': 0 + 'alternate("imm_val",11, fltr_func =lambda x: (x>=10 and x<2030) or (x<=-8 and x>-2030) ,scale_func = lambda x: x*2)': 0 + +cbeqz: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.beqz: 0 + rs1: + <<: *c_regs + val_comb: + 'rs1_val > 0 and imm_val > 0': 0 + 'rs1_val < 0 and imm_val > 0': 0 + 'rs1_val == 0 and imm_val > 0': 0 + 'rs1_val > 0 and imm_val < 0': 0 + 'rs1_val < 0 and imm_val < 0': 0 + 'rs1_val == 0 and imm_val < 0': 0 + <<: [*base_rs1val_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val"])': 0 + <<: [*rs1val_walking] + +cbnez: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.bnez: 0 + rs1: + <<: *c_regs + val_comb: + 'rs1_val > 0 and imm_val > 0': 0 + 'rs1_val < 0 and imm_val > 0': 0 + 'rs1_val == 0 and imm_val > 0': 0 + 'rs1_val > 0 and imm_val < 0': 0 + 'rs1_val < 0 and imm_val < 0': 0 + 'rs1_val == 0 and imm_val < 0': 0 + <<: [*base_rs1val_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val"])': 0 + <<: [*rs1val_walking] + +cslli: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.slli: 0 + rd: + <<: *c_regs + val_comb: + 'rs1_val < 0 and imm_val < xlen': 0 + 'rs1_val > 0 and imm_val < xlen': 0 + 'rs1_val == imm_val and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == (-2**(xlen-1)) and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == 0 and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == (2**(xlen-1)-1) and imm_val != 0 and imm_val < xlen': 0 + 'rs1_val == 1 and imm_val != 0 and imm_val < xlen': 0 + abstract_comb: + 'sp_dataset(xlen,["rs1_val"])': 0 + <<: [*rs1val_walking] + 'walking_ones("imm_val", ceil(log(xlen,2)), False)': 0 + 'walking_zeros("imm_val", ceil(log(xlen,2)), False)': 0 + 'alternate("imm_val", ceil(log(xlen,2)), False)': 0 + +clwsp: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.lwsp: 0 + rd: + <<: *all_regs_mx0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0 + +cldsp: + config: + - check ISA:=regex(.*RV64.*I.*C.*) + mnemonics: + c.ldsp: 0 + rd: + <<: *all_regs_mx0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 + +cjr: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.jr: 0 + rs1: + <<: *all_regs_mx0 + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *base_rs1val_sgn_rs2val_zero + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: *rs1val_walking + +cmv: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.mv: 0 + rs2: + <<: *all_regs_mx0 + rd: + <<: *all_regs + op_comb: + 'rs2 == rd and rs2 != 0': 0 + 'rs2 != rd and rs2 != 0': 0 + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs2_val"])': 0 + <<: [*rs2val_walking] + +cadd: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.add: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs_mx0 + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: [*crfmt_val_comb_sgn, *base_rs1val_sgn,*base_rs2val_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking,*rs2val_walking] + +cjalr: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.jalr: 0 + rs1: + <<: *all_regs_mx0 + op_comb: + <<: *sfmt_op_comb + val_comb: + <<: *base_rs1val_sgn_rs2val_zero + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: *rs1val_walking + +cswsp: + config: + - check ISA:=regex(.*I.*C.*) + mnemonics: + c.swsp: 0 + rs2: + <<: *all_regs_mx2 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0 + +csdsp: + config: + - check ISA:=regex(.*RV64.*I.*C.*) + mnemonics: + c.sdsp: 0 + rs2: + <<: *all_regs_mx2 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv64im.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv64im.cgf new file mode 100644 index 000000000..92ac8c096 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv64im.cgf @@ -0,0 +1,250 @@ +# For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore + +mul: + config: + - check ISA:=regex(.*I.*M.*) + mnemonics: + mul: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +mulh: + config: + - check ISA:=regex(.*I.*M.*) + mnemonics: + mulh: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +mulhu: + config: + - check ISA:=regex(.*I.*M.*) + mnemonics: + mulhu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'sp_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + +mulhsu: + config: + - check ISA:=regex(.*I.*M.*) + mnemonics: + mulhsu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_unsgn, *rfmt_val_comb_unsgn] + 'rs1_val < 0 and rs2_val > 0': 0 + abstract_comb: + 'sp_dataset(xlen,[("rs1_val",xlen),("rs2_val",xlen,False)])': 0 + <<: [*rs1val_walking, *rs2val_walking_unsgn] + +div: + config: + - check ISA:=regex(.*I.*M.*) + mnemonics: + div: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn, *div_corner_case] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +divu: + config: + - check ISA:=regex(.*I.*M.*) + mnemonics: + divu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'sp_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + +rem: + config: + - check ISA:=regex(.*I.*M.*) + mnemonics: + rem: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn, *div_corner_case] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +remu: + config: + - check ISA:=regex(.*I.*M.*) + mnemonics: + remu: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'sp_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + +mulw: + config: + - check ISA:=regex(.*RV64.*I.*M.*) + mnemonics: + mulw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +divw: + config: + - check ISA:=regex(.*RV64.*I.*M.*) + mnemonics: + divw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn, *div_corner_case] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +divuw: + config: + - check ISA:=regex(.*RV64.*I.*M.*) + mnemonics: + divuw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'sp_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + +remw: + config: + - check ISA:=regex(.*RV64.*I.*M.*) + mnemonics: + remw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn, *div_corner_case] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +remuw: + config: + - check ISA:=regex(.*RV64.*I.*M.*) + mnemonics: + remuw: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn] + abstract_comb: + 'sp_dataset(xlen,signed=False)': 0 + <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn] + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv64ip.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv64ip.cgf new file mode 100644 index 000000000..cf0ca4bab --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv64ip.cgf @@ -0,0 +1,1578 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +add32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + add32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +radd32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + radd32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +uradd32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + uradd32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'simd_base_val("rs2", xlen, 32, signed=False)': 0 + 'simd_val_comb(xlen, 32, signed=False)': 0 + +kadd32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kadd32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +ukadd32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ukadd32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'simd_base_val("rs2", xlen, 32, signed=False)': 0 + 'simd_val_comb(xlen, 32, signed=False)': 0 + +sub32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + sub32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +rsub32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + rsub32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + + +ursub32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ursub32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'simd_base_val("rs2", xlen, 32, signed=False)': 0 + 'simd_val_comb(xlen, 32, signed=False)': 0 + +ksub32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ksub32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +uksub32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + uksub32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'simd_base_val("rs2", xlen, 32, signed=False)': 0 + 'simd_val_comb(xlen, 32, signed=False)': 0 + +cras32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + cras32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +rcras32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + rcras32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +urcras32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + urcras32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'simd_base_val("rs2", xlen, 32, signed=False)': 0 + 'simd_val_comb(xlen, 32, signed=False)': 0 + +kcras32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kcras32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +ukcras32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ukcras32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'simd_base_val("rs2", xlen, 32, signed=False)': 0 + 'simd_val_comb(xlen, 32, signed=False)': 0 + +crsa32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + crsa32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +rcrsa32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + rcrsa32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +urcrsa32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + urcrsa32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'simd_base_val("rs2", xlen, 32, signed=False)': 0 + 'simd_val_comb(xlen, 32, signed=False)': 0 + +kcrsa32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kcrsa32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +ukcrsa32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ukcrsa32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'simd_base_val("rs2", xlen, 32, signed=False)': 0 + 'simd_val_comb(xlen, 32, signed=False)': 0 + +stas32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + stas32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +rstas32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + rstas32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +urstas32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + urstas32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'simd_base_val("rs2", xlen, 32, signed=False)': 0 + 'simd_val_comb(xlen, 32, signed=False)': 0 + +kstas32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kstas32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +ukstas32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ukstas32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'simd_base_val("rs2", xlen, 32, signed=False)': 0 + 'simd_val_comb(xlen, 32, signed=False)': 0 + +stsa32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + stsa32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +rstsa32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + rstsa32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +urstsa32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + urstsa32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'simd_base_val("rs2", xlen, 32, signed=False)': 0 + 'simd_val_comb(xlen, 32, signed=False)': 0 + +kstsa32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kstsa32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +ukstsa32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ukstsa32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'simd_base_val("rs2", xlen, 32, signed=False)': 0 + 'simd_val_comb(xlen, 32, signed=False)': 0 + +sra32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + sra32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'walking_ones("rs2_val", ceil(log(32, 2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(32, 2)), False)': 0 + 'alternate("rs2_val", ceil(log(32, 2)), False)': 0 + +srai32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + srai32: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_imm_val("imm_val", 5)': 0 + +sra32.u: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + sra32.u: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'walking_ones("rs2_val", ceil(log(32, 2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(32, 2)), False)': 0 + 'alternate("rs2_val", ceil(log(32, 2)), False)': 0 + +srai32.u: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + srai32.u: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_imm_val("imm_val", 5)': 0 + +srl32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + srl32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'walking_ones("rs2_val", ceil(log(32, 2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(32, 2)), False)': 0 + 'alternate("rs2_val", ceil(log(32, 2)), False)': 0 + +srli32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + srli32: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'simd_imm_val("imm_val", 5)': 0 + +srl32.u: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + srl32.u: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'walking_ones("rs2_val", ceil(log(32, 2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(32, 2)), False)': 0 + 'alternate("rs2_val", ceil(log(32, 2)), False)': 0 + +srli32.u: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + srli32.u: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'simd_imm_val("imm_val", 5)': 0 + +sll32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + sll32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'walking_ones("rs2_val", ceil(log(32, 2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(32, 2)), False)': 0 + 'alternate("rs2_val", ceil(log(32, 2)), False)': 0 + +slli32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + slli32: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'simd_imm_val("imm_val", 5)': 0 + +ksll32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + ksll32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'walking_ones("rs2_val", ceil(log(32, 2)), False)': 0 + 'walking_zeros("rs2_val", ceil(log(32, 2)), False)': 0 + 'alternate("rs2_val", ceil(log(32, 2)), False)': 0 + +kslli32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kslli32: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_imm_val("imm_val", 5)': 0 + +kslra32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kslra32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'walking_ones("rs2_val", xlen, True)': 0 + 'walking_zeros("rs2_val", xlen, True)': 0 + 'alternate("rs2_val", xlen, True)': 0 + +kslra32.u: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kslra32.u: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'walking_ones("rs2_val", xlen, True)': 0 + 'walking_zeros("rs2_val", xlen, True)': 0 + 'alternate("rs2_val", xlen, True)': 0 + +smin32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smin32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +umin32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + umin32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'simd_base_val("rs2", xlen, 32, signed=False)': 0 + 'simd_val_comb(xlen, 32, signed=False)': 0 + +smax32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smax32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +umax32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + umax32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'simd_base_val("rs2", xlen, 32, signed=False)': 0 + 'simd_val_comb(xlen, 32, signed=False)': 0 + +kabs32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kabs32: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + +khmbb16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + khmbb16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +khmbt16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + khmbt16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +khmtt16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + khmtt16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +kdmbb16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kdmbb16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +kdmbt16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kdmbt16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +kdmtt16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kdmtt16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +kdmabb16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kdmabb16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +kdmabt16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kdmabt16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +kdmatt16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kdmatt16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=True)': 0 + 'simd_base_val("rs2", xlen, 16, signed=True)': 0 + 'simd_val_comb(xlen, 16, signed=True)': 0 + +# alias of mulsr64 +# smbb32: +# config: +# - check ISA:=regex(.*I.*P.*Zicsr.*) +# mnemonics: +# smbb32: 0 +# rs1: +# <<: *all_regs +# rs2: +# <<: *all_regs +# rd: +# <<: *all_regs +# op_comb: +# <<: *rfmt_op_comb +# val_comb: +# abstract_comb: +# 'simd_base_val("rs1", xlen, 32, signed=True)': 0 +# 'simd_base_val("rs2", xlen, 32, signed=True)': 0 +# 'simd_val_comb(xlen, 32, signed=True)': 0 + +smbt32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smbt32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +smtt32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smtt32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +kmabb32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmabb32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +kmabt32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmabt32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +kmatt32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmatt32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +kmda32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmda32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +kmxda32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmxda32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +# alias of kmar64 +# kmada32: +# config: +# - check ISA:=regex(.*I.*P.*Zicsr.*) +# mnemonics: +# kmada32: 0 +# rs1: +# <<: *all_regs +# rs2: +# <<: *all_regs +# rd: +# <<: *all_regs +# op_comb: +# <<: *rfmt_op_comb +# val_comb: +# abstract_comb: +# 'simd_base_val("rs1", xlen, 32, signed=True)': 0 +# 'simd_base_val("rs2", xlen, 32, signed=True)': 0 +# 'simd_val_comb(xlen, 32, signed=True)': 0 + +kmaxda32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmaxda32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +kmads32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmads32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +kmadrs32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmadrs32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +kmaxds32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmaxds32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +kmsda32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmsda32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +kmsxda32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + kmsxda32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +smds32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smds32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +smdrs32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smdrs32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +smxds32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + smxds32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_base_val("rs2", xlen, 32, signed=True)': 0 + 'simd_val_comb(xlen, 32, signed=True)': 0 + +sraiw.u: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + sraiw.u: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=True)': 0 + 'simd_imm_val("imm_val", 5)': 0 + +# instructions overlapping with those in the B extension in RV64 configuration (Zbpbo) +# pkbb32: +# config: +# - check ISA:=regex(.*I.*P.*Zicsr.*) +# mnemonics: +# pkbb32: 0 +# rs1: +# <<: *all_regs +# rs2: +# <<: *all_regs +# rd: +# <<: *all_regs +# op_comb: +# <<: *rfmt_op_comb +# val_comb: +# abstract_comb: +# 'simd_base_val("rs1", xlen, 32, signed=False)': 0 +# 'simd_base_val("rs2", xlen, 32, signed=False)': 0 +# 'simd_val_comb(xlen, 32, signed=False)': 0 + +pkbt32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + pkbt32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'simd_base_val("rs2", xlen, 32, signed=False)': 0 + 'simd_val_comb(xlen, 32, signed=False)': 0 + +pktb32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + pktb32: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + 'simd_base_val("rs2", xlen, 32, signed=False)': 0 + 'simd_val_comb(xlen, 32, signed=False)': 0 + +# instructions overlapping with those in the B extension in RV64 configuration (Zbpbo) +# pktt32: +# config: +# - check ISA:=regex(.*I.*P.*Zicsr.*) +# mnemonics: +# pktt32: 0 +# rs1: +# <<: *all_regs +# rs2: +# <<: *all_regs +# rd: +# <<: *all_regs +# op_comb: +# <<: *rfmt_op_comb +# val_comb: +# abstract_comb: +# 'simd_base_val("rs1", xlen, 32, signed=False)': 0 +# 'simd_base_val("rs2", xlen, 32, signed=False)': 0 +# 'simd_val_comb(xlen, 32, signed=False)': 0 + +# instructions overlapping with those in the B extension in RV32 configuration (Zbpbo) +clz32: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + clz32: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 32, signed=False)': 0 + +pkbb16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + pkbb16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'simd_base_val("rs2", xlen, 16, signed=False)': 0 + 'simd_val_comb(xlen, 16, signed=False)': 0 + +pktt16: + config: + - check ISA:=regex(.*I.*P.*Zicsr.*) + mnemonics: + pktt16: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'simd_base_val("rs1", xlen, 16, signed=False)': 0 + 'simd_base_val("rs2", xlen, 16, signed=False)': 0 + 'simd_val_comb(xlen, 16, signed=False)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv64zacas.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv64zacas.cgf new file mode 100644 index 000000000..6d4db482e --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/rv64zacas.cgf @@ -0,0 +1,54 @@ +# cover group format file for Zacas extension +amocas.w: + config: + - check ISA:=regex(.*Zacas.*) + mnemonics: + amocas.w: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *zacas_op_comb + val_comb: + <<: [*base_rs1val_sgn, *base_rs2val_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +amocas.d_64: + config: + - check ISA:=regex(.*Zacas.*) + mnemonics: + amocas.d_64: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *zacas_op_comb + val_comb: + <<: [*base_rs1val_sgn, *base_rs2val_sgn, *rfmt_val_comb_sgn] + abstract_comb: + <<: [*rs1val_walking, *rs2val_walking] + +amocas.q: + config: + - check ISA:=regex(.*Zacas.*) + mnemonics: + amocas.q: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *zacas_op_comb + val_comb: + <<: [*zacas_dcas_rs1val_sgn, *zacas_dcas_rs2val_sgn, *rfmt_val_comb_sgn] + abstract_comb: + <<: [*zacas128_rs1val_walking_sgn, *zacas128_rs2val_walking_sgn] diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fadd.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fadd.d.cgf new file mode 100644 index 000000000..fd1092a36 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fadd.d.cgf @@ -0,0 +1,188 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fadd.d_b1: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fadd.d", 2)': 0 + +fadd.d_b2: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,64, "fadd.d", 2)': 0 + +fadd.d_b3: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,64, "fadd.d", 2)': 0 + +fadd.d_b4: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,64, "fadd.d", 2)': 0 + +fadd.d_b5: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,64, "fadd.d", 2)': 0 + +fadd.d_b7: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,64, "fadd.d", 2)': 0 + +fadd.d_b8: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,64, "fadd.d", 2)': 0 + +fadd.d_b10: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b10(flen,64, "fadd.d", 2)': 0 + +fadd.d_b11: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b11(flen,64, "fadd.d", 2)': 0 + +fadd.d_b12: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b12(flen,64, "fadd.d", 2)': 0 + +fadd.d_b13: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b13(flen,64, "fadd.d", 2)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fadd.q.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fadd.q.cgf new file mode 100644 index 000000000..4ea09a546 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fadd.q.cgf @@ -0,0 +1,16 @@ +fadd.q_b1: + config: + - check ISA:=regex(.*I.*D.*Q.*) + mnemonics: + fadd.q: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,128, "fadd.q", 2)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fclass.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fclass.d.cgf new file mode 100644 index 000000000..a400d6d81 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fclass.d.cgf @@ -0,0 +1,15 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fclass.d_b1: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fclass.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fclass.d", 1)': 0 + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fcvt.d.s.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fcvt.d.s.cgf new file mode 100644 index 000000000..def774ab4 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fcvt.d.s.cgf @@ -0,0 +1,106 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.d.s_b1: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.d.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fcvt.d.s", 1)': 0 + +fcvt.d.s_b22: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.d.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b22(flen,32, "fcvt.d.s", 1)': 0 + +fcvt.d.s_b23: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.d.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b23(flen,32, "fcvt.d.s", 1)': 0 + +fcvt.d.s_b24: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.d.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b24(flen,32, "fcvt.d.s", 1)': 0 + +fcvt.d.s_b27: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.d.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b27(flen,32, "fcvt.d.s", 1)': 0 + +fcvt.d.s_b28: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.d.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b28(flen,32, "fcvt.d.s", 1)': 0 + +fcvt.d.s_b29: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.d.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b29(flen,32, "fcvt.d.s", 1)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fcvt.d.w.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fcvt.d.w.cgf new file mode 100644 index 000000000..2dcf295fb --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fcvt.d.w.cgf @@ -0,0 +1,28 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.d.w_b25: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.d.w: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b25(flen,32, "fcvt.d.w", 1)': 0 + +fcvt.d.w_b26: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.d.w: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b26(32, "fcvt.d.w", 1)': 0 + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fcvt.d.wu.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fcvt.d.wu.cgf new file mode 100644 index 000000000..0f9ed15c3 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fcvt.d.wu.cgf @@ -0,0 +1,28 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.d.wu_b25: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.d.wu: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b25(flen,32, "fcvt.d.wu", 1)': 0 + +fcvt.d.wu_b26: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.d.wu: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b26(32, "fcvt.d.wu", 1)': 0 + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fcvt.s.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fcvt.s.d.cgf new file mode 100644 index 000000000..9d87ab7b9 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fcvt.s.d.cgf @@ -0,0 +1,106 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.s.d_b1: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.s.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fcvt.s.d", 1)': 0 + +fcvt.s.d_b22: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.s.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b22(flen,64, "fcvt.s.d", 1)': 0 + +fcvt.s.d_b23: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.s.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b23(flen,64, "fcvt.s.d", 1)': 0 + +fcvt.s.d_b24: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.s.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b24(flen,64, "fcvt.s.d", 1)': 0 + +fcvt.s.d_b27: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.s.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b27(flen,64, "fcvt.s.d", 1)': 0 + +fcvt.s.d_b28: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.s.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b28(flen,64, "fcvt.s.d", 1)': 0 + +fcvt.s.d_b29: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.s.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b29(flen,64, "fcvt.s.d", 1)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fcvt.w.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fcvt.w.d.cgf new file mode 100644 index 000000000..dc81adfa9 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fcvt.w.d.cgf @@ -0,0 +1,92 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.w.d_b1: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.w.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fcvt.w.d", 1)': 0 + +fcvt.w.d_b22: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.w.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b22(flen,64, "fcvt.w.d", 1)': 0 + +fcvt.w.d_b23: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.w.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b23(flen,64, "fcvt.w.d", 1)': 0 + +fcvt.w.d_b24: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.w.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b24(flen,64, "fcvt.w.d", 1)': 0 + +fcvt.w.d_b27: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.w.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b27(flen,64, "fcvt.w.d", 1)': 0 + +fcvt.w.d_b28: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.w.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b28(flen,64, "fcvt.w.d", 1)': 0 + +fcvt.w.d_b29: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.w.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b29(flen,64, "fcvt.w.d", 1)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fcvt.wu.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fcvt.wu.d.cgf new file mode 100644 index 000000000..dacb2e398 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fcvt.wu.d.cgf @@ -0,0 +1,92 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.wu.d_b1: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.wu.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fcvt.wu.d", 1)': 0 + +fcvt.wu.d_b22: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.wu.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b22(flen,64, "fcvt.wu.d", 1)': 0 + +fcvt.wu.d_b23: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.wu.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b23(flen,64, "fcvt.wu.d", 1)': 0 + +fcvt.wu.d_b24: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.wu.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b24(flen,64, "fcvt.wu.d", 1)': 0 + +fcvt.wu.d_b27: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.wu.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b27(flen,64, "fcvt.wu.d", 1)': 0 + +fcvt.wu.d_b28: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.wu.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b28(flen,64, "fcvt.wu.d", 1)': 0 + +fcvt.wu.d_b29: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fcvt.wu.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b29(flen,64, "fcvt.wu.d", 1)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fdiv.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fdiv.d.cgf new file mode 100644 index 000000000..d1e37d833 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fdiv.d.cgf @@ -0,0 +1,188 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fdiv.d_b1: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fdiv.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fdiv.d", 2)': 0 + +fdiv.d_b2: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fdiv.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,64, "fdiv.d", 2)': 0 + +fdiv.d_b3: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fdiv.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,64, "fdiv.d", 2)': 0 + +fdiv.d_b4: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fdiv.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,64, "fdiv.d", 2)': 0 + +fdiv.d_b5: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fdiv.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,64, "fdiv.d", 2)': 0 + +fdiv.d_b6: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fdiv.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,64, "fdiv.d", 2)': 0 + +fdiv.d_b7: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fdiv.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,64, "fdiv.d", 2)': 0 + +fdiv.d_b8: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fdiv.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,64, "fdiv.d", 2)': 0 + +fdiv.d_b9: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fdiv.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b9(flen,64, "fdiv.d", 2)': 0 + +fdiv.d_b20: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fdiv.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b20(flen,64, "fdiv.d", 2)': 0 + +fdiv.d_b21: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fdiv.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b21(flen,64, "fdiv.d", 2)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/feq.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/feq.d.cgf new file mode 100644 index 000000000..9d86e46f6 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/feq.d.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +feq.d_b1: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + feq.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "feq.d", 2)': 0 + +feq.d_b19: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + feq.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,64, "feq.d", 2)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fld-align.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fld-align.cgf new file mode 100644 index 000000000..8ddbe6339 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fld-align.cgf @@ -0,0 +1,23 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fld-align: + config: + - check ISA:=regex(.*D.*) + mnemonics: + fld: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_fregs + val_comb: + 'ea_align == 0 and (imm_val % 8) == 0 and fcsr == 0': 0 + 'ea_align == 0 and (imm_val % 8) == 1 and fcsr == 0': 0 + 'ea_align == 0 and (imm_val % 8) == 2 and fcsr == 0': 0 + 'ea_align == 0 and (imm_val % 8) == 3 and fcsr == 0': 0 + 'ea_align == 0 and (imm_val % 8) == 4 and fcsr == 0': 0 + 'ea_align == 0 and (imm_val % 8) == 5 and fcsr == 0': 0 + 'ea_align == 0 and (imm_val % 8) == 6 and fcsr == 0': 0 + 'ea_align == 0 and (imm_val % 8) == 7 and fcsr == 0': 0 + 'imm_val > 0 and fcsr == 0': 0 + 'imm_val < 0 and fcsr == 0': 0 + 'imm_val == 0 and fcsr == 0': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fle.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fle.d.cgf new file mode 100644 index 000000000..d5a6e7642 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fle.d.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fle.d_b1: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fle.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fle.d", 2)': 0 + +fle.d_b19: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fle.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,64, "fle.d", 2)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/flt.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/flt.d.cgf new file mode 100644 index 000000000..f350b32e3 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/flt.d.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +flt.d_b1: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + flt.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "flt.d", 2)': 0 + +flt.d_b19: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + flt.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,64, "flt.d", 2)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fmadd.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fmadd.d.cgf new file mode 100644 index 000000000..a9a49cfbb --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fmadd.d.cgf @@ -0,0 +1,248 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmadd.d_b1: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fmadd.d", 3)': 0 + +fmadd.d_b2: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,64, "fmadd.d", 3)': 0 + +fmadd.d_b3: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,64, "fmadd.d", 3)': 0 + +fmadd.d_b4: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,64, "fmadd.d", 3)': 0 + +fmadd.d_b5: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,64, "fmadd.d", 3)': 0 + +fmadd.d_b6: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,64, "fmadd.d", 3)': 0 + +fmadd.d_b7: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,64, "fmadd.d", 3)': 0 + +fmadd.d_b8: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,64, "fmadd.d", 3)': 0 + +fmadd.d_b14: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b14(flen,64, "fmadd.d", 3)': 0 + +fmadd.d_b15: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b15(flen,64, "fmadd.d", 3)': 0 + +fmadd.d_b16: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b16(flen,64, "fmadd.d", 3)': 0 + +fmadd.d_b17: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b17(flen,64, "fmadd.d", 3)': 0 + +fmadd.d_b18: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b18(flen,64, "fmadd.d", 3)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fmax.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fmax.d.cgf new file mode 100644 index 000000000..73633a2fc --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fmax.d.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmax.d_b1: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmax.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fmax.d", 2)': 0 + +fmax.d_b19: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmax.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,64, "fmax.d", 2)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fmin.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fmin.d.cgf new file mode 100644 index 000000000..df0a710ef --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fmin.d.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmin.d_b1: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmin.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fmin.d", 2)': 0 + +fmin.d_b19: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmin.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,64, "fmin.d", 2)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fmsub.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fmsub.d.cgf new file mode 100644 index 000000000..7f734f8f9 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fmsub.d.cgf @@ -0,0 +1,248 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmsub.d_b1: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fmsub.d", 3)': 0 + +fmsub.d_b2: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,64, "fmsub.d", 3)': 0 + +fmsub.d_b3: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,64, "fmsub.d", 3)': 0 + +fmsub.d_b4: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,64, "fmsub.d", 3)': 0 + +fmsub.d_b5: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,64, "fmsub.d", 3)': 0 + +fmsub.d_b6: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,64, "fmsub.d", 3)': 0 + +fmsub.d_b7: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,64, "fmsub.d", 3)': 0 + +fmsub.d_b8: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,64, "fmsub.d", 3)': 0 + +fmsub.d_b14: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b14(flen,64, "fmsub.d", 3)': 0 + +fmsub.d_b15: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b15(flen,64, "fmsub.d", 3)': 0 + +fmsub.d_b16: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b16(flen,64, "fmsub.d", 3)': 0 + +fmsub.d_b17: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b17(flen,64, "fmsub.d", 3)': 0 + +fmsub.d_b18: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b18(flen,64, "fmsub.d", 3)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fmul.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fmul.d.cgf new file mode 100644 index 000000000..48db171f3 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fmul.d.cgf @@ -0,0 +1,155 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmul.d_b1: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmul.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fmul.d", 2)': 0 + +fmul.d_b2: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmul.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,64, "fmul.d", 2)': 0 + +fmul.d_b3: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmul.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,64, "fmul.d", 2)': 0 + +fmul.d_b4: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmul.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,64, "fmul.d", 2)': 0 + +fmul.d_b5: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmul.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,64, "fmul.d", 2)': 0 + +fmul.d_b6: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmul.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,64, "fmul.d", 2)': 0 + +fmul.d_b7: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmul.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,64, "fmul.d", 2)': 0 + +fmul.d_b8: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmul.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,64, "fmul.d", 2)': 0 + +fmul.d_b9: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fmul.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b9(flen,64, "fmul.d", 2)': 0 + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fnmadd.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fnmadd.d.cgf new file mode 100644 index 000000000..192d998c5 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fnmadd.d.cgf @@ -0,0 +1,248 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fnmadd.d_b1: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fnmadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fnmadd.d", 3)': 0 + +fnmadd.d_b2: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fnmadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,64, "fnmadd.d", 3)': 0 + +fnmadd.d_b3: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fnmadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,64, "fnmadd.d", 3)': 0 + +fnmadd.d_b4: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fnmadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,64, "fnmadd.d", 3)': 0 + +fnmadd.d_b5: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fnmadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,64, "fnmadd.d", 3)': 0 + +fnmadd.d_b6: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fnmadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,64, "fnmadd.d", 3)': 0 + +fnmadd.d_b7: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fnmadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,64, "fnmadd.d", 3)': 0 + +fnmadd.d_b8: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fnmadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,64, "fnmadd.d", 3)': 0 + +fnmadd.d_b14: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fnmadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b14(flen,64, "fnmadd.d", 3)': 0 + +fnmadd.d_b15: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fnmadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b15(flen,64, "fnmadd.d", 3)': 0 + +fnmadd.d_b16: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fnmadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b16(flen,64, "fnmadd.d", 3)': 0 + +fnmadd.d_b17: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fnmadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b17(flen,64, "fnmadd.d", 3)': 0 + +fnmadd.d_b18: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fnmadd.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b18(flen,64, "fnmadd.d", 3)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fnmsub.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fnmsub.d.cgf new file mode 100644 index 000000000..5c8c2b6d9 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fnmsub.d.cgf @@ -0,0 +1,248 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fnmsub.d_b1: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fnmsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fnmsub.d", 3)': 0 + +fnmsub.d_b2: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fnmsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,64, "fnmsub.d", 3)': 0 + +fnmsub.d_b3: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fnmsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,64, "fnmsub.d", 3)': 0 + +fnmsub.d_b4: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fnmsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,64, "fnmsub.d", 3)': 0 + +fnmsub.d_b5: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fnmsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,64, "fnmsub.d", 3)': 0 + +fnmsub.d_b6: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fnmsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,64, "fnmsub.d", 3)': 0 + +fnmsub.d_b7: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fnmsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,64, "fnmsub.d", 3)': 0 + +fnmsub.d_b8: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fnmsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,64, "fnmsub.d", 3)': 0 + +fnmsub.d_b14: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fnmsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b14(flen,64, "fnmsub.d", 3)': 0 + +fnmsub.d_b15: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fnmsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b15(flen,64, "fnmsub.d", 3)': 0 + +fnmsub.d_b16: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fnmsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b16(flen,64, "fnmsub.d", 3)': 0 + +fnmsub.d_b17: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fnmsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b17(flen,64, "fnmsub.d", 3)': 0 + +fnmsub.d_b18: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fnmsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b18(flen,64, "fnmsub.d", 3)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fsd-align.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fsd-align.cgf new file mode 100644 index 000000000..4897723b2 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fsd-align.cgf @@ -0,0 +1,23 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsd-align: + config: + - check ISA:=regex(.*D.*) + mnemonics: + fsd: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_fregs + val_comb: + 'ea_align == 0 and (imm_val % 8) == 0 and fcsr == 0': 0 + 'ea_align == 0 and (imm_val % 8) == 1 and fcsr == 0': 0 + 'ea_align == 0 and (imm_val % 8) == 2 and fcsr == 0': 0 + 'ea_align == 0 and (imm_val % 8) == 3 and fcsr == 0': 0 + 'ea_align == 0 and (imm_val % 8) == 4 and fcsr == 0': 0 + 'ea_align == 0 and (imm_val % 8) == 5 and fcsr == 0': 0 + 'ea_align == 0 and (imm_val % 8) == 6 and fcsr == 0': 0 + 'ea_align == 0 and (imm_val % 8) == 7 and fcsr == 0': 0 + 'imm_val > 0 and fcsr == 0': 0 + 'imm_val < 0 and fcsr == 0': 0 + 'imm_val == 0 and fcsr == 0': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fsgnj.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fsgnj.d.cgf new file mode 100644 index 000000000..c92ce150e --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fsgnj.d.cgf @@ -0,0 +1,19 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsgnj.d_b1: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fsgnj.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fsgnj.d", 2)': 0 + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fsgnjn.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fsgnjn.d.cgf new file mode 100644 index 000000000..7eab86eca --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fsgnjn.d.cgf @@ -0,0 +1,19 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsgnjn.d_b1: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fsgnjn.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fsgnjn.d", 2)': 0 + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fsgnjx.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fsgnjx.d.cgf new file mode 100644 index 000000000..ba00bff1f --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fsgnjx.d.cgf @@ -0,0 +1,19 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsgnjx.d_b1: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fsgnjx.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fsgnjx.d", 2)': 0 + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fsqrt.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fsqrt.d.cgf new file mode 100644 index 000000000..4c12d7bba --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fsqrt.d.cgf @@ -0,0 +1,137 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsqrt.d_b1: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fsqrt.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fsqrt.d", 1)': 0 + +fsqrt.d_b2: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fsqrt.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,64, "fsqrt.d", 1)': 0 + +fsqrt.d_b3: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fsqrt.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,64, "fsqrt.d", 1)': 0 + +fsqrt.d_b4: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fsqrt.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,64, "fsqrt.d", 1)': 0 + +fsqrt.d_b5: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fsqrt.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,64, "fsqrt.d", 1)': 0 + +fsqrt.d_b7: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fsqrt.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,64, "fsqrt.d", 1)': 0 + +fsqrt.d_b8: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fsqrt.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,64, "fsqrt.d", 1)': 0 + +fsqrt.d_b9: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fsqrt.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b9(flen,64, "fsqrt.d", 1)': 0 + +fsqrt.d_b20: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fsqrt.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b20(flen,64, "fsqrt.d", 1)': 0 + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fsub.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fsub.d.cgf new file mode 100644 index 000000000..df8a6f946 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fsub.d.cgf @@ -0,0 +1,188 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fssub.d_b1: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fsub.d", 2)': 0 + +fssub.d_b2: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,64, "fsub.d", 2)': 0 + +fssub.d_b3: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,64, "fsub.d", 2)': 0 + +fssub.d_b4: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,64, "fsub.d", 2)': 0 + +fssub.d_b5: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,64, "fsub.d", 2)': 0 + +fssub.d_b7: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,64, "fsub.d", 2)': 0 + +fssub.d_b8: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,64, "fsub.d", 2)': 0 + +fssub.d_b10: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b10(flen,64, "fsub.d", 2)': 0 + +fssub.d_b11: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b11(flen,64, "fsub.d", 2)': 0 + +fssub.d_b12: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b12(flen,64, "fsub.d", 2)': 0 + +fssub.d_b13: + config: + - check ISA:=regex(.*I.*D.*) + mnemonics: + fsub.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b13(flen,64, "fsub.d", 2)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fadd.s.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fadd.s.cgf new file mode 100644 index 000000000..01fc5104f --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fadd.s.cgf @@ -0,0 +1,188 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fadd_b1: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fadd.s", 2)': 0 + +fadd_b2: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,32, "fadd.s", 2)': 0 + +fadd_b3: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,32, "fadd.s", 2)': 0 + +fadd_b4: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,32, "fadd.s", 2)': 0 + +fadd_b5: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,32, "fadd.s", 2)': 0 + +fadd_b7: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,32, "fadd.s", 2)': 0 + +fadd_b8: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,32, "fadd.s", 2)': 0 + +fadd_b10: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b10(flen,32, "fadd.s", 2)': 0 + +fadd_b11: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b11(flen,32, "fadd.s", 2)': 0 + +fadd_b12: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b12(flen,32, "fadd.s", 2)': 0 + +fadd_b13: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b13(flen,32, "fadd.s", 2)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fclass.s.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fclass.s.cgf new file mode 100644 index 000000000..cf7cd1dbc --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fclass.s.cgf @@ -0,0 +1,15 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fclass_b1: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fclass.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fclass.s", 1)': 0 + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fcvt.s.w.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fcvt.s.w.cgf new file mode 100644 index 000000000..49dc0f9c5 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fcvt.s.w.cgf @@ -0,0 +1,28 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.s.w_b25: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fcvt.s.w: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b25(flen,32, "fcvt.s.w", 1)': 0 + +fcvt.s.w_b26: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fcvt.s.w: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b26(32, "fcvt.s.w", 1)': 0 + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fcvt.s.wu.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fcvt.s.wu.cgf new file mode 100644 index 000000000..eff472660 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fcvt.s.wu.cgf @@ -0,0 +1,28 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.s.wu_b25: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fcvt.s.wu: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b25(flen,32, "fcvt.s.wu", 1)': 0 + +fcvt.s.wu_b26: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fcvt.s.wu: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b26(32, "fcvt.s.wu", 1)': 0 + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fcvt.w.s.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fcvt.w.s.cgf new file mode 100644 index 000000000..1950bc326 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fcvt.w.s.cgf @@ -0,0 +1,92 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.w.s_b1: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fcvt.w.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fcvt.w.s", 1)': 0 + +fcvt.w.s_b22: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fcvt.w.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b22(flen,32, "fcvt.w.s", 1)': 0 + +fcvt.w.s_b23: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fcvt.w.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b23(flen,32, "fcvt.w.s", 1)': 0 + +fcvt.w.s_b24: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fcvt.w.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b24(flen,32, "fcvt.w.s", 1)': 0 + +fcvt.w.s_b27: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fcvt.w.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b27(flen,32, "fcvt.w.s", 1)': 0 + +fcvt.w.s_b28: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fcvt.w.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b28(flen,32, "fcvt.w.s", 1)': 0 + +fcvt.w.s_b29: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fcvt.w.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b29(flen,32, "fcvt.w.s", 1)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fcvt.wu.s.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fcvt.wu.s.cgf new file mode 100644 index 000000000..4ab625dd6 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fcvt.wu.s.cgf @@ -0,0 +1,92 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.wu.s_b1: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fcvt.wu.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fcvt.wu.s", 1)': 0 + +fcvt.wu.s_b22: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fcvt.wu.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b22(flen,32, "fcvt.wu.s", 1)': 0 + +fcvt.wu.s_b23: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fcvt.wu.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b23(flen,32, "fcvt.wu.s", 1)': 0 + +fcvt.wu.s_b24: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fcvt.wu.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b24(flen,32, "fcvt.wu.s", 1)': 0 + +fcvt.wu.s_b27: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fcvt.wu.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b27(flen,32, "fcvt.wu.s", 1)': 0 + +fcvt.wu.s_b28: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fcvt.wu.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b28(flen,32, "fcvt.wu.s", 1)': 0 + +fcvt.wu.s_b29: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fcvt.wu.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b29(flen,32, "fcvt.wu.s", 1)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fdiv.s.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fdiv.s.cgf new file mode 100644 index 000000000..f4b3e143b --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fdiv.s.cgf @@ -0,0 +1,188 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fdiv_b1: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fdiv.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fdiv.s", 2)': 0 + +fdiv_b2: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fdiv.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,32, "fdiv.s", 2)': 0 + +fdiv_b3: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fdiv.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,32, "fdiv.s", 2)': 0 + +fdiv_b4: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fdiv.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,32, "fdiv.s", 2)': 0 + +fdiv_b5: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fdiv.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,32, "fdiv.s", 2)': 0 + +fdiv_b6: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fdiv.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,32, "fdiv.s", 2)': 0 + +fdiv_b7: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fdiv.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,32, "fdiv.s", 2)': 0 + +fdiv_b8: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fdiv.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,32, "fdiv.s", 2)': 0 + +fdiv_b9: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fdiv.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b9(flen,32, "fdiv.s", 2)': 0 + +fdiv_b20: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fdiv.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b20(flen,32, "fdiv.s", 2)': 0 + +fdiv_b21: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fdiv.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b21(flen,32, "fdiv.s", 2)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/feq.s.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/feq.s.cgf new file mode 100644 index 000000000..7cf20e824 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/feq.s.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +feq_b1: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + feq.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "feq.s", 2)': 0 + +feq_b19: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + feq.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,32, "feq.s", 2)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fle.s.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fle.s.cgf new file mode 100644 index 000000000..0e743cfb2 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fle.s.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fle_b1: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fle.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fle.s", 2)': 0 + +fle_b19: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fle.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,32, "fle.s", 2)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/flt.s.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/flt.s.cgf new file mode 100644 index 000000000..0cbfc4966 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/flt.s.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +flt_b1: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + flt.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "flt.s", 2)': 0 + +flt_b19: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + flt.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,32, "flt.s", 2)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/flw-align.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/flw-align.cgf new file mode 100644 index 000000000..62ed7d1bb --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/flw-align.cgf @@ -0,0 +1,19 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +flw-align: + config: + - check ISA:=regex(.*F.*) + mnemonics: + flw: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *all_fregs + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0 and fcsr == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1 and fcsr == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 2 and fcsr == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 3 and fcsr == 0': 0 + 'imm_val > 0 and fcsr == 0': 0 + 'imm_val < 0 and fcsr == 0': 0 + 'imm_val == 0 and fcsr == 0': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fmadd.s.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fmadd.s.cgf new file mode 100644 index 000000000..b5f3c9a85 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fmadd.s.cgf @@ -0,0 +1,248 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmadd_b1: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fmadd.s", 3)': 0 + +fmadd_b2: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,32, "fmadd.s", 3)': 0 + +fmadd_b3: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,32, "fmadd.s", 3)': 0 + +fmadd_b4: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,32, "fmadd.s", 3)': 0 + +fmadd_b5: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,32, "fmadd.s", 3)': 0 + +fmadd_b6: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,32, "fmadd.s", 3)': 0 + +fmadd_b7: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,32, "fmadd.s", 3)': 0 + +fmadd_b8: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,32, "fmadd.s", 3)': 0 + +fmadd_b14: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b14(flen,32, "fmadd.s", 3)': 0 + +fmadd_b15: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b15(flen,32, "fmadd.s", 3)': 0 + +fmadd_b16: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b16(flen,32, "fmadd.s", 3)': 0 + +fmadd_b17: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b17(flen,32, "fmadd.s", 3)': 0 + +fmadd_b18: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b18(flen,32, "fmadd.s", 3)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fmax.s.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fmax.s.cgf new file mode 100644 index 000000000..6652fcbf9 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fmax.s.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmax_b1: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmax.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fmax.s", 2)': 0 + +fmax_b19: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmax.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,32, "fmax.s", 2)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fmin.s.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fmin.s.cgf new file mode 100644 index 000000000..81d4ba06e --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fmin.s.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmin_b1: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmin.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fmin.s", 2)': 0 + +fmin_b19: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmin.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,32, "fmin.s", 2)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fmsub.s.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fmsub.s.cgf new file mode 100644 index 000000000..ff6b74642 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fmsub.s.cgf @@ -0,0 +1,248 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmsub_b1: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fmsub.s", 3)': 0 + +fmsub_b2: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,32, "fmsub.s", 3)': 0 + +fmsub_b3: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,32, "fmsub.s", 3)': 0 + +fmsub_b4: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,32, "fmsub.s", 3)': 0 + +fmsub_b5: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,32, "fmsub.s", 3)': 0 + +fmsub_b6: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,32, "fmsub.s", 3)': 0 + +fmsub_b7: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,32, "fmsub.s", 3)': 0 + +fmsub_b8: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,32, "fmsub.s", 3)': 0 + +fmsub_b14: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b14(flen,32, "fmsub.s", 3)': 0 + +fmsub_b15: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b15(flen,32, "fmsub.s", 3)': 0 + +fmsub_b16: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b16(flen,32, "fmsub.s", 3)': 0 + +fmsub_b17: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b17(flen,32, "fmsub.s", 3)': 0 + +fmsub_b18: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b18(flen,32, "fmsub.s", 3)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fmul.s.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fmul.s.cgf new file mode 100644 index 000000000..5d09eba25 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fmul.s.cgf @@ -0,0 +1,155 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmul_b1: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmul.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fmul.s", 2)': 0 + +fmul_b2: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmul.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,32, "fmul.s", 2)': 0 + +fmul_b3: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmul.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,32, "fmul.s", 2)': 0 + +fmul_b4: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmul.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,32, "fmul.s", 2)': 0 + +fmul_b5: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmul.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,32, "fmul.s", 2)': 0 + +fmul_b6: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmul.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,32, "fmul.s", 2)': 0 + +fmul_b7: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmul.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,32, "fmul.s", 2)': 0 + +fmul_b8: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmul.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,32, "fmul.s", 2)': 0 + +fmul_b9: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmul.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b9(flen,32, "fmul.s", 2)': 0 + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fmv.w.x.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fmv.w.x.cgf new file mode 100644 index 000000000..fae501eae --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fmv.w.x.cgf @@ -0,0 +1,28 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmv.w.x_b25: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmv.w.x: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b25(flen,32, "fmv.w.x", 1)': 0 + +fmv.w.x_b26: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmv.w.x: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b26(32, "fmv.w.x", 1)': 0 + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fmv.x.w.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fmv.x.w.cgf new file mode 100644 index 000000000..e58bacec0 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fmv.x.w.cgf @@ -0,0 +1,92 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmv.x.w_b1: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmv.x.w: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fmv.x.w", 1)': 0 + +fmv.x.w_b22: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmv.x.w: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b22(flen,32, "fmv.x.w", 1)': 0 + +fmv.x.w_b23: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmv.x.w: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b23(flen,32, "fmv.x.w", 1)': 0 + +fmv.x.w_b24: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmv.x.w: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b24(flen,32, "fmv.x.w", 1)': 0 + +fmv.x.w_b27: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmv.x.w: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b27(flen,32, "fmv.x.w", 1)': 0 + +fmv.x.w_b28: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmv.x.w: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b28(flen,32, "fmv.x.w", 1)': 0 + +fmv.x.w_b29: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fmv.x.w: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b29(flen,32, "fmv.x.w", 1)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fnmadd.s.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fnmadd.s.cgf new file mode 100644 index 000000000..f8834ff4c --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fnmadd.s.cgf @@ -0,0 +1,248 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fnmadd_b1: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fnmadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fnmadd.s", 3)': 0 + +fnmadd_b2: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fnmadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,32, "fnmadd.s", 3)': 0 + +fnmadd_b3: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fnmadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,32, "fnmadd.s", 3)': 0 + +fnmadd_b4: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fnmadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,32, "fnmadd.s", 3)': 0 + +fnmadd_b5: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fnmadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,32, "fnmadd.s", 3)': 0 + +fnmadd_b6: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fnmadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,32, "fnmadd.s", 3)': 0 + +fnmadd_b7: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fnmadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,32, "fnmadd.s", 3)': 0 + +fnmadd_b8: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fnmadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,32, "fnmadd.s", 3)': 0 + +fnmadd_b14: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fnmadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b14(flen,32, "fnmadd.s", 3)': 0 + +fnmadd_b15: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fnmadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b15(flen,32, "fnmadd.s", 3)': 0 + +fnmadd_b16: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fnmadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b16(flen,32, "fnmadd.s", 3)': 0 + +fnmadd_b17: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fnmadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b17(flen,32, "fnmadd.s", 3)': 0 + +fnmadd_b18: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fnmadd.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b18(flen,32, "fnmadd.s", 3)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fnmsub.s.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fnmsub.s.cgf new file mode 100644 index 000000000..f163e3ce4 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fnmsub.s.cgf @@ -0,0 +1,248 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fnmsub_b1: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fnmsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fnmsub.s", 3)': 0 + +fnmsub_b2: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fnmsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,32, "fnmsub.s", 3)': 0 + +fnmsub_b3: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fnmsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,32, "fnmsub.s", 3)': 0 + +fnmsub_b4: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fnmsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,32, "fnmsub.s", 3)': 0 + +fnmsub_b5: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fnmsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,32, "fnmsub.s", 3)': 0 + +fnmsub_b6: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fnmsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,32, "fnmsub.s", 3)': 0 + +fnmsub_b7: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fnmsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,32, "fnmsub.s", 3)': 0 + +fnmsub_b8: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fnmsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,32, "fnmsub.s", 3)': 0 + +fnmsub_b14: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fnmsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b14(flen,32, "fnmsub.s", 3)': 0 + +fnmsub_b15: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fnmsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b15(flen,32, "fnmsub.s", 3)': 0 + +fnmsub_b16: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fnmsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b16(flen,32, "fnmsub.s", 3)': 0 + +fnmsub_b17: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fnmsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b17(flen,32, "fnmsub.s", 3)': 0 + +fnmsub_b18: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fnmsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rs3: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *r4fmt_op_comb + val_comb: + abstract_comb: + 'ibm_b18(flen,32, "fnmsub.s", 3)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fsgnj.s.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fsgnj.s.cgf new file mode 100644 index 000000000..cd04be5fe --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fsgnj.s.cgf @@ -0,0 +1,19 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsgnj_b1: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fsgnj.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fsgnj.s", 2)': 0 + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fsgnjn.s.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fsgnjn.s.cgf new file mode 100644 index 000000000..9b115f283 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fsgnjn.s.cgf @@ -0,0 +1,19 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsgnjn_b1: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fsgnjn.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fsgnjn.s", 2)': 0 + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fsgnjx.s.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fsgnjx.s.cgf new file mode 100644 index 000000000..f157bf009 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fsgnjx.s.cgf @@ -0,0 +1,19 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsgnjx_b1: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fsgnjx.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fsgnjx.s", 2)': 0 + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fsqrt.s.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fsqrt.s.cgf new file mode 100644 index 000000000..0595ee6ab --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fsqrt.s.cgf @@ -0,0 +1,137 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsqrt_b1: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fsqrt.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fsqrt.s", 1)': 0 + +fsqrt_b2: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fsqrt.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,32, "fsqrt.s", 1)': 0 + +fsqrt_b3: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fsqrt.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,32, "fsqrt.s", 1)': 0 + +fsqrt_b4: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fsqrt.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,32, "fsqrt.s", 1)': 0 + +fsqrt_b5: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fsqrt.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,32, "fsqrt.s", 1)': 0 + +fsqrt_b7: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fsqrt.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,32, "fsqrt.s", 1)': 0 + +fsqrt_b8: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fsqrt.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,32, "fsqrt.s", 1)': 0 + +fsqrt_b9: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fsqrt.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b9(flen,32, "fsqrt.s", 1)': 0 + +fsqrt_b20: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fsqrt.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b20(flen,32, "fsqrt.s", 1)': 0 + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fsub.s.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fsub.s.cgf new file mode 100644 index 000000000..30eba0362 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fsub.s.cgf @@ -0,0 +1,188 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsub_b1: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fsub.s", 2)': 0 + +fsub_b2: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,32, "fsub.s", 2)': 0 + +fsub_b3: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,32, "fsub.s", 2)': 0 + +fsub_b4: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,32, "fsub.s", 2)': 0 + +fsub_b5: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,32, "fsub.s", 2)': 0 + +fsub_b7: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,32, "fsub.s", 2)': 0 + +fsub_b8: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,32, "fsub.s", 2)': 0 + +fsub_b10: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b10(flen,32, "fsub.s", 2)': 0 + +fsub_b11: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b11(flen,32, "fsub.s", 2)': 0 + +fsub_b12: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b12(flen,32, "fsub.s", 2)': 0 + +fsub_b13: + config: + - check ISA:=regex(.*I.*F.*) + mnemonics: + fsub.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b13(flen,32, "fsub.s", 2)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fsw-align.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fsw-align.cgf new file mode 100644 index 000000000..3188c369d --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fsw-align.cgf @@ -0,0 +1,19 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsw-align: + config: + - check ISA:=regex(.*F.*) + mnemonics: + fsw: 0 + rs2: + <<: *all_fregs + rs1: + <<: *all_regs_mx0 + val_comb: + 'ea_align == 0 and (imm_val % 4) == 0 and fcsr == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 1 and fcsr == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 2 and fcsr == 0': 0 + 'ea_align == 0 and (imm_val % 4) == 3 and fcsr == 0': 0 + 'imm_val > 0 and fcsr == 0': 0 + 'imm_val < 0 and fcsr == 0': 0 + 'imm_val == 0 and fcsr == 0': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64D/fcvt.d.l.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64D/fcvt.d.l.cgf new file mode 100644 index 000000000..7db8eeb9c --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64D/fcvt.d.l.cgf @@ -0,0 +1,28 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.d.l_b25: + config: + - check ISA:=regex(.*RV64.*I.*D.*) + mnemonics: + fcvt.d.l: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b25(flen,64, "fcvt.d.l", 1)': 0 + +fcvt.d.l_b26: + config: + - check ISA:=regex(.*RV64.*I.*D.*) + mnemonics: + fcvt.d.l: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b26(64, "fcvt.d.l", 1)': 0 + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64D/fcvt.d.lu.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64D/fcvt.d.lu.cgf new file mode 100644 index 000000000..a2dac71c7 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64D/fcvt.d.lu.cgf @@ -0,0 +1,28 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.d.lu_b25: + config: + - check ISA:=regex(.*RV64.*I.*D.*) + mnemonics: + fcvt.d.lu: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b25(flen,64, "fcvt.d.lu", 1)': 0 + +fcvt.d.lu_b26: + config: + - check ISA:=regex(.*RV64.*I.*D.*) + mnemonics: + fcvt.d.lu: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b26(64, "fcvt.d.lu", 1)': 0 + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64D/fcvt.l.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64D/fcvt.l.d.cgf new file mode 100644 index 000000000..a5079b4d6 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64D/fcvt.l.d.cgf @@ -0,0 +1,92 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.l.d_b1: + config: + - check ISA:=regex(.*RV64.*I.*D.*) + mnemonics: + fcvt.l.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fcvt.l.d", 1)': 0 + +fcvt.l.d_b22: + config: + - check ISA:=regex(.*RV64.*I.*D.*) + mnemonics: + fcvt.l.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b22(flen,64, "fcvt.l.d", 1)': 0 + +fcvt.l.d_b23: + config: + - check ISA:=regex(.*RV64.*I.*D.*) + mnemonics: + fcvt.l.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b23(flen,64, "fcvt.l.d", 1)': 0 + +fcvt.l.d_b24: + config: + - check ISA:=regex(.*RV64.*I.*D.*) + mnemonics: + fcvt.l.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b24(flen,64, "fcvt.l.d", 1)': 0 + +fcvt.l.d_b27: + config: + - check ISA:=regex(.*RV64.*I.*D.*) + mnemonics: + fcvt.l.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b27(flen,64, "fcvt.l.d", 1)': 0 + +fcvt.l.d_b28: + config: + - check ISA:=regex(.*RV64.*I.*D.*) + mnemonics: + fcvt.l.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b28(flen,64, "fcvt.l.d", 1)': 0 + +fcvt.l.d_b29: + config: + - check ISA:=regex(.*RV64.*I.*D.*) + mnemonics: + fcvt.l.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b29(flen,64, "fcvt.l.d", 1)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64D/fcvt.lu.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64D/fcvt.lu.d.cgf new file mode 100644 index 000000000..7402e4520 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64D/fcvt.lu.d.cgf @@ -0,0 +1,92 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.lu.d_b1: + config: + - check ISA:=regex(.*RV64.*I.*D.*) + mnemonics: + fcvt.lu.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fcvt.lu.d", 1)': 0 + +fcvt.lu.d_b22: + config: + - check ISA:=regex(.*RV64.*I.*D.*) + mnemonics: + fcvt.lu.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b22(flen,64, "fcvt.lu.d", 1)': 0 + +fcvt.lu.d_b23: + config: + - check ISA:=regex(.*RV64.*I.*D.*) + mnemonics: + fcvt.lu.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b23(flen,64, "fcvt.lu.d", 1)': 0 + +fcvt.lu.d_b24: + config: + - check ISA:=regex(.*RV64.*I.*D.*) + mnemonics: + fcvt.lu.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b24(flen,64, "fcvt.lu.d", 1)': 0 + +fcvt.lu.d_b27: + config: + - check ISA:=regex(.*RV64.*I.*D.*) + mnemonics: + fcvt.lu.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b27(flen,64, "fcvt.lu.d", 1)': 0 + +fcvt.lu.d_b28: + config: + - check ISA:=regex(.*RV64.*I.*D.*) + mnemonics: + fcvt.lu.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b28(flen,64, "fcvt.lu.d", 1)': 0 + +fcvt.lu.d_b29: + config: + - check ISA:=regex(.*RV64.*I.*D.*) + mnemonics: + fcvt.lu.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b29(flen,64, "fcvt.lu.d", 1)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64D/fmv.d.x.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64D/fmv.d.x.cgf new file mode 100644 index 000000000..05d67690e --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64D/fmv.d.x.cgf @@ -0,0 +1,28 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmv.d.x_b25: + config: + - check ISA:=regex(.*RV64.*I.*D.*) + mnemonics: + fmv.d.x: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b25(flen,64, "fmv.d.x", 1)': 0 + +fmv.d.x_b26: + config: + - check ISA:=regex(.*RV64.*I.*D.*) + mnemonics: + fmv.d.x: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b26(64, "fmv.d.x", 1)': 0 + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64D/fmv.x.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64D/fmv.x.d.cgf new file mode 100644 index 000000000..2cc96bdc2 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64D/fmv.x.d.cgf @@ -0,0 +1,92 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmv.x.d_b1: + config: + - check ISA:=regex(.*RV64.*I.*D.*) + mnemonics: + fmv.x.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fmv.x.d", 1)': 0 + +fmv.x.d_b22: + config: + - check ISA:=regex(.*RV64.*I.*D.*) + mnemonics: + fmv.x.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b22(flen,64, "fmv.x.d", 1)': 0 + +fmv.x.d_b23: + config: + - check ISA:=regex(.*RV64.*I.*D.*) + mnemonics: + fmv.x.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b23(flen,64, "fmv.x.d", 1)': 0 + +fmv.x.d_b24: + config: + - check ISA:=regex(.*RV64.*I.*D.*) + mnemonics: + fmv.x.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b24(flen,64, "fmv.x.d", 1)': 0 + +fmv.x.d_b27: + config: + - check ISA:=regex(.*RV64.*I.*D.*) + mnemonics: + fmv.x.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b27(flen,64, "fmv.x.d", 1)': 0 + +fmv.x.d_b28: + config: + - check ISA:=regex(.*RV64.*I.*D.*) + mnemonics: + fmv.x.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b28(flen,64, "fmv.x.d", 1)': 0 + +fmv.x.d_b29: + config: + - check ISA:=regex(.*RV64.*I.*D.*) + mnemonics: + fmv.x.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b29(flen,64, "fmv.x.d", 1)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64F/fcvt.l.s.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64F/fcvt.l.s.cgf new file mode 100644 index 000000000..152ad7539 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64F/fcvt.l.s.cgf @@ -0,0 +1,92 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.l.s_b1: + config: + - check ISA:=regex(.*RV64.*I.*F.*) + mnemonics: + fcvt.l.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fcvt.l.s", 1)': 0 + +fcvt.l.s_b22: + config: + - check ISA:=regex(.*RV64.*I.*F.*) + mnemonics: + fcvt.l.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b22(flen,32, "fcvt.l.s", 1)': 0 + +fcvt.l.s_b23: + config: + - check ISA:=regex(.*RV64.*I.*F.*) + mnemonics: + fcvt.l.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b23(flen,32, "fcvt.l.s", 1)': 0 + +fcvt.l.s_b24: + config: + - check ISA:=regex(.*RV64.*I.*F.*) + mnemonics: + fcvt.l.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b24(flen,32, "fcvt.l.s", 1)': 0 + +fcvt.l.s_b27: + config: + - check ISA:=regex(.*RV64.*I.*F.*) + mnemonics: + fcvt.l.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b27(flen,32, "fcvt.l.s", 1)': 0 + +fcvt.l.s_b28: + config: + - check ISA:=regex(.*RV64.*I.*F.*) + mnemonics: + fcvt.l.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b28(flen,32, "fcvt.l.s", 1)': 0 + +fcvt.l.s_b29: + config: + - check ISA:=regex(.*RV64.*I.*F.*) + mnemonics: + fcvt.l.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b29(flen,32, "fcvt.l.s", 1)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64F/fcvt.lu.s.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64F/fcvt.lu.s.cgf new file mode 100644 index 000000000..544a79664 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64F/fcvt.lu.s.cgf @@ -0,0 +1,92 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.lu.s_b1: + config: + - check ISA:=regex(.*RV64.*I.*F.*) + mnemonics: + fcvt.lu.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,32, "fcvt.lu.s", 1)': 0 + +fcvt.lu.s_b22: + config: + - check ISA:=regex(.*RV64.*I.*F.*) + mnemonics: + fcvt.lu.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b22(flen,32, "fcvt.lu.s", 1)': 0 + +fcvt.lu.s_b23: + config: + - check ISA:=regex(.*RV64.*I.*F.*) + mnemonics: + fcvt.lu.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b23(flen,32, "fcvt.lu.s", 1)': 0 + +fcvt.lu.s_b24: + config: + - check ISA:=regex(.*RV64.*I.*F.*) + mnemonics: + fcvt.lu.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b24(flen,32, "fcvt.lu.s", 1)': 0 + +fcvt.lu.s_b27: + config: + - check ISA:=regex(.*RV64.*I.*F.*) + mnemonics: + fcvt.lu.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b27(flen,32, "fcvt.lu.s", 1)': 0 + +fcvt.lu.s_b28: + config: + - check ISA:=regex(.*RV64.*I.*F.*) + mnemonics: + fcvt.lu.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b28(flen,32, "fcvt.lu.s", 1)': 0 + +fcvt.lu.s_b29: + config: + - check ISA:=regex(.*RV64.*I.*F.*) + mnemonics: + fcvt.lu.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b29(flen,32, "fcvt.lu.s", 1)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64F/fcvt.s.l.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64F/fcvt.s.l.cgf new file mode 100644 index 000000000..e6eeebcee --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64F/fcvt.s.l.cgf @@ -0,0 +1,28 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.s.l_b25: + config: + - check ISA:=regex(.*RV64.*I.*F.*) + mnemonics: + fcvt.s.l: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b25(flen,64, "fcvt.s.l", 1)': 0 + +fcvt.s.l_b26: + config: + - check ISA:=regex(.*RV64.*I.*F.*) + mnemonics: + fcvt.s.l: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b26(64, "fcvt.s.l", 1)': 0 + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64F/fcvt.s.lu.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64F/fcvt.s.lu.cgf new file mode 100644 index 000000000..4a23073de --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV64F/fcvt.s.lu.cgf @@ -0,0 +1,28 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.s.lu_b25: + config: + - check ISA:=regex(.*RV64.*I.*F.*) + mnemonics: + fcvt.s.lu: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b25(flen,64, "fcvt.s.lu", 1)': 0 + +fcvt.s.lu_b26: + config: + - check ISA:=regex(.*RV64.*I.*F.*) + mnemonics: + fcvt.s.lu: 0 + rs1: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b26(64, "fcvt.s.lu", 1)': 0 + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/srmcfg.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/srmcfg.cgf new file mode 100644 index 000000000..411d05434 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/srmcfg.cgf @@ -0,0 +1,77 @@ +srmcfg: + config: + - check ISA:=regex(.*I.*Zicsr.*Ssqosid.*); def rvtest_mtrap_routine=True + isa: + - I_Zicsr_Ssqosid + csr_comb: + 'CSR_SRMCFG & 0x0FFF0FFF == 0x00000001': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x00000003': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x00000007': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0000000F': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0000001F': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0000003F': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0000007F': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x000000FF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x000001FF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x000003FF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x000007FF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x00000FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x00010FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x00030FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x00070FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x000F0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x001F0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x003F0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x007F0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x00FF0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x01FF0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x03FF0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FFE': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FFC': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FF8': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FF0': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FE0': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FC0': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0F80': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0F00': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0E00': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0C00': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0800': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0000': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFE0000': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFC0000': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FF80000': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FF00000': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FE00000': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FC00000': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0F800000': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0F000000': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0E000000': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0C000000': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x08000000': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x00000000': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FFD': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FFB': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FF7': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FEF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FDF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FBF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0F7F': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0EFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0DFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0BFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF07FF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFE0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFD0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFB0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FF70FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FEF0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FDF0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FBF0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0F7F0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0EFF0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0DFF0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0BFF0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x07FF0FFF': 0 + 'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FFF': 0 + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zcmop.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zcmop.cgf new file mode 100644 index 000000000..8af2caa00 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zcmop.cgf @@ -0,0 +1,71 @@ +c.mop.1: + config: + - check ISA:=regex(.*C.*Zcmop.*) + mnemonics: + c.mop.1: + val_comb: + abstract_comb: + <<: *cbimm_val_walking + +c.mop.3: + config: + - check ISA:=regex(.*C.*Zcmop.*) + mnemonics: + c.mop.3: + val_comb: + abstract_comb: + <<: *cbimm_val_walking + +c.mop.5: + config: + - check ISA:=regex(.*C.*Zcmop.*) + mnemonics: + c.mop.5: + val_comb: + abstract_comb: + <<: *cbimm_val_walking + +c.mop.7: + config: + - check ISA:=regex(.*C.*Zcmop.*) + mnemonics: + c.mop.7: + val_comb: + abstract_comb: + <<: *cbimm_val_walking + +c.mop.9: + config: + - check ISA:=regex(.*C.*Zcmop.*) + mnemonics: + c.mop.9: + val_comb: + abstract_comb: + <<: *cbimm_val_walking + +c.mop.11: + config: + - check ISA:=regex(.*C.*Zcmop.*) + mnemonics: + c.mop.11: + val_comb: + abstract_comb: + <<: *cbimm_val_walking + +c.mop.13: + config: + - check ISA:=regex(.*C.*Zcmop.*) + mnemonics: + c.mop.13: + val_comb: + abstract_comb: + <<: *cbimm_val_walking + +c.mop.15: + config: + - check ISA:=regex(.*C.*Zcmop.*) + mnemonics: + c.mop.15: + val_comb: + abstract_comb: + <<: *cbimm_val_walking diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fcvtmod.w.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fcvtmod.w.d.cgf new file mode 100644 index 000000000..6d83fdca4 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fcvtmod.w.d.cgf @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fcvtmod.w.d_b1: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fcvtmod.w.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen, 64, "fcvt.w.d", 1)': 0 + +fcvtmod.w.d_b22: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fcvtmod.w.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b22(flen, 64, "fcvt.w.d", 1)': 0 + +fcvtmod.w.d_b23: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fcvtmod.w.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b23(flen, 64, "fcvt.w.d", 1)': 0 + +fcvtmod.w.d_b24: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fcvtmod.w.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b24(flen, 64, "fcvt.w.d", 1)': 0 + +fcvtmod.w.d_b27: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fcvtmod.w.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b27(flen, 64, "fcvt.w.d", 1)': 0 + +fcvtmod.w.d_b28: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fcvtmod.w.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b28(flen, 64, "fcvt.w.d", 1)': 0 + +fcvtmod.w.d_b29: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fcvtmod.w.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b29(flen, 64, "fcvt.w.d", 1)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fleq.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fleq.d.cgf new file mode 100644 index 000000000..392b7e311 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fleq.d.cgf @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fleq.d_b1: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fleq.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 64, "fle.d", 2)': 0 + +fleq.d_b19: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fleq.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen, 64, "fle.d", 2)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fleq.s.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fleq.s.cgf new file mode 100644 index 000000000..518ff63dc --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fleq.s.cgf @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fleq_b1: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + fleq.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 32, "fle.s", 2)': 0 + +fleq_b19: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + fleq.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen, 32, "fle.s", 2)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fli.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fli.d.cgf new file mode 100644 index 000000000..dea19ac27 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fli.d.cgf @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fli.d_b1: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fli.d: 0 + rd: + <<: *all_fregs diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fli.s.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fli.s.cgf new file mode 100644 index 000000000..d16cc2c28 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fli.s.cgf @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fli_b1: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + fli.s: 0 + rd: + <<: *all_fregs diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fltq.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fltq.d.cgf new file mode 100644 index 000000000..1bc2c0820 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fltq.d.cgf @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fltq.d_b1: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fltq.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 64, "flt.d", 2)': 0 + +fltq.d_b19: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fltq.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen, 64, "flt.d", 2)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fltq.s.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fltq.s.cgf new file mode 100644 index 000000000..8449a73ae --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fltq.s.cgf @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fltq_b1: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + fltq.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 32, "flt.s", 2)': 0 + +fltq_b19: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + fltq.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen, 32, "flt.s", 2)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fmaxm.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fmaxm.d.cgf new file mode 100644 index 000000000..1538ea4e1 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fmaxm.d.cgf @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fmaxm.d_b1: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fmaxm.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 64, "fmax.d", 2)': 0 + +fmaxm.d_b19: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fmaxm.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen, 64, "fmax.d", 2)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fmaxm.s.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fmaxm.s.cgf new file mode 100644 index 000000000..08d65acc0 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fmaxm.s.cgf @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fmaxm_b1: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + fmaxm.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 32, "fmax.s", 2)': 0 + +fmaxm_b19: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + fmaxm.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen, 32, "fmax.s", 2)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fminm.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fminm.d.cgf new file mode 100644 index 000000000..9f559c812 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fminm.d.cgf @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fminm.d_b1: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fminm.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 64, "fmin.d", 2)': 0 + +fminm.d_b19: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fminm.d: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen, 64, "fmin.d", 2)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fminm.s.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fminm.s.cgf new file mode 100644 index 000000000..0c53416f8 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fminm.s.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fminm_b1: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + fminm.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 32, "fmin.s", 2)': 0 + +fminm_b19: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + fminm.s: 0 + rs1: + <<: *all_fregs + rs2: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen, 32, "fmin.s", 2)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fmvh.x.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fmvh.x.d.cgf new file mode 100644 index 000000000..f3eb4fdf6 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fmvh.x.d.cgf @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fmvh.x.d_b1: + config: + - check ISA:=regex(.*RV32.*I.*D.*Zfa.*) + mnemonics: + fmvh.x.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fmv.x.d", 1)': 0 + +fmvh.x.d_b22: + config: + - check ISA:=regex(.*RV32.*I.*D.*Zfa.*) + mnemonics: + fmvh.x.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b22(flen,64, "fmv.x.d", 1)': 0 + +fmvh.x.d_b23: + config: + - check ISA:=regex(.*RV32.*I.*D.*Zfa.*) + mnemonics: + fmvh.x.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b23(flen,64, "fmv.x.d", 1)': 0 + +fmvh.x.d_b24: + config: + - check ISA:=regex(.*RV32.*I.*D.*Zfa.*) + mnemonics: + fmvh.x.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b24(flen,64, "fmv.x.d", 1)': 0 + +fmvh.x.d_b27: + config: + - check ISA:=regex(.*RV32.*I.*D.*Zfa.*) + mnemonics: + fmvh.x.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b27(flen,64, "fmv.x.d", 1)': 0 + +fmvh.x.d_b28: + config: + - check ISA:=regex(.*RV32.*I.*D.*Zfa.*) + mnemonics: + fmvh.x.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b28(flen,64, "fmv.x.d", 1)': 0 + +fmvh.x.d_b29: + config: + - check ISA:=regex(.*RV32.*I.*D.*Zfa.*) + mnemonics: + fmvh.x.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_regs + val_comb: + abstract_comb: + 'ibm_b29(flen,64, "fmv.x.d", 1)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fmvp.d.x.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fmvp.d.x.cgf new file mode 100644 index 000000000..85633d607 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fmvp.d.x.cgf @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fmvp.d.x_b25: + config: + - check ISA:=regex(.*RV32.*I.*D.*Zfa.*) + mnemonics: + fmvp.d.x: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b25(flen, 64, "fmv.d.x", 2)': 0 + +fmvp.d.x_b26: + config: + - check ISA:=regex(.*RV32.*I.*D.*Zfa.*) + mnemonics: + fmvp.d.x: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_fregs + val_comb: + abstract_comb: + 'ibm_b26(64, "fmv.d.x", 2)': 0 + + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fround.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fround.d.cgf new file mode 100644 index 000000000..671392d15 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fround.d.cgf @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fround.d_b1: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + fround.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 64, "fsqrt.d", 1)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fround.s.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fround.s.cgf new file mode 100644 index 000000000..629fea2cb --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/fround.s.cgf @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: BSD-3-Clause + +fround_b1: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + fround.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 32, "fsqrt.s", 1)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/froundnx.d.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/froundnx.d.cgf new file mode 100644 index 000000000..6fe670b79 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/froundnx.d.cgf @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: BSD-3-Clause + +froundnx.d_b1: + config: + - check ISA:=regex(.*I.*D.*Zfa.*) + mnemonics: + froundnx.d: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 64, "fsqrt.d", 1)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/froundnx.s.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/froundnx.s.cgf new file mode 100644 index 000000000..9bcdef9a5 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zfa/froundnx.s.cgf @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: BSD-3-Clause + +froundnx_b1: + config: + - check ISA:=regex(.*I.*F.*Zfa.*) + mnemonics: + froundnx.s: 0 + rs1: + <<: *all_fregs + rd: + <<: *all_fregs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen, 32, "fsqrt.s", 1)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zicfilp.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zicfilp.cgf new file mode 100644 index 000000000..6ead1de81 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zicfilp.cgf @@ -0,0 +1,44 @@ +lpad-m: + config: + - check ISA:=regex(.*I.*Zicsr.*Zicfilp.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True + mnemonics: + lpad-m: 0 + val_comb: + 'imm_val == 0': 0 + 'imm_val > 0': 0 + 'imm_val == ((2**20)-1)': 0 + abstract_comb: + 'sp_dataset(20,["imm_val"],signed=False)': 0 + 'walking_ones("imm_val", 20, False)': 0 + 'walking_zeros("imm_val", 20, False)': 0 + 'alternate("imm_val", 20, False)': 0 + +lpad-s: + config: + - check ISA:=regex(.*I.*Zicsr.*Zicfilp.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True + mnemonics: + lpad-s: 0 + val_comb: + 'imm_val == 0': 0 + 'imm_val > 0': 0 + 'imm_val == ((2**20)-1)': 0 + abstract_comb: + 'sp_dataset(20,["imm_val"],signed=False)': 0 + 'walking_ones("imm_val", 20, False)': 0 + 'walking_zeros("imm_val", 20, False)': 0 + 'alternate("imm_val", 20, False)': 0 + +lpad-u: + config: + - check ISA:=regex(.*I.*Zicsr.*Zicfilp.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True + mnemonics: + lpad-u: 0 + val_comb: + 'imm_val == 0': 0 + 'imm_val > 0': 0 + 'imm_val == ((2**20)-1)': 0 + abstract_comb: + 'sp_dataset(20,["imm_val"],signed=False)': 0 + 'walking_ones("imm_val", 20, False)': 0 + 'walking_zeros("imm_val", 20, False)': 0 + 'alternate("imm_val", 20, False)': 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zicfiss.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zicfiss.cgf new file mode 100644 index 000000000..b1c1140c9 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zicfiss.cgf @@ -0,0 +1,133 @@ +sspush_popchk_u: + config: + - check ISA:=regex(.*I.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True + mnemonics: + sspushpopchk_u: 0 + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +sspush_popchk_s: + config: + - check ISA:=regex(.*I.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True + mnemonics: + sspushpopchk_s: 0 + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +csspush_popchk_u: + config: + - check ISA:=regex(.*I.*C.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True + mnemonics: + c.sspushpopchk_u: 0 + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +csspush_popchk_s: + config: + - check ISA:=regex(.*I.*C.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True + mnemonics: + c.sspushpopchk_s: 0 + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +ssamoswap.w_s: + config: + - check ISA:=regex(.*I.*A.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True + mnemonics: + ssamoswap.w_s: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +ssamoswap.d_s: + config: + - check ISA:=regex(.*I.*A.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True + mnemonics: + ssamoswap.d_s: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + + +ssamoswap.w_u: + config: + - check ISA:=regex(.*I.*A.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True + mnemonics: + ssamoswap.w_u: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +ssamoswap.d_u: + config: + - check ISA:=regex(.*I.*A.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True + mnemonics: + ssamoswap.d_u: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: [*ramofmt_op_comb] + val_comb: + <<: [*base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + +ssrdp_u: + config: + - check ISA:=regex(.*I.*A.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True + mnemonics: + ssrdp_u: 0 + rd: + <<: *all_regs_mx0 + op_comb: + <<: *rfmt_op_comb + +ssrdp_s: + config: + - check ISA:=regex(.*I.*A.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True + mnemonics: + ssrdp_s: 0 + rd: + <<: *all_regs_mx0 + op_comb: + <<: *rfmt_op_comb + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zicond.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zicond.cgf new file mode 100644 index 000000000..af6c1b824 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zicond.cgf @@ -0,0 +1,37 @@ +czero.eqz: + config: + - check ISA:=regex(.*Zicond.*) + mnemonics: + czero.eqz: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +czero.nez: + config: + - check ISA:=regex(.*Zicond.*) + mnemonics: + czero.nez: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zimop.cgf b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zimop.cgf new file mode 100644 index 000000000..25fb014c0 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/zimop.cgf @@ -0,0 +1,697 @@ +# For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore + +mop.rr.0: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.rr.0: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +mop.rr.1: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.rr.1: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +mop.rr.2: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.rr.2: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +mop.rr.3: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.rr.3: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +mop.rr.4: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.rr.4: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +mop.rr.5: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.rr.5: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +mop.rr.6: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.rr.6: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +mop.rr.7: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.rr.7: 0 + rs1: + <<: *all_regs + rs2: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn] + abstract_comb: + 'sp_dataset(xlen)': 0 + <<: [*rs1val_walking, *rs2val_walking] + +mop.r.0: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.0: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.1: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.1: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.2: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.2: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.3: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.3: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.4: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.4: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.5: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.5: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.6: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.6: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.7: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.7: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.8: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.8: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.9: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.9: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.10: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.10: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.11: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.11: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.12: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.12: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.13: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.13: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.14: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.14: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.15: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.15: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.16: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.16: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.17: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.17: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.18: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.18: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.19: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.19: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.20: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.20: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.21: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.21: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.22: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.22: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.23: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.23: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.24: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.24: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.25: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.25: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.26: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.26: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.27: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.27: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.28: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.28: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.29: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.29: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.30: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.30: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] + +mop.r.31: + config: + - check ISA:=regex(.*Zimop.*) + mnemonics: + mop.r.31: 0 + rs1: + <<: *all_regs + rd: + <<: *all_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn] + abstract_comb: + 'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0 + <<: [*rs1val_walking, *ifmt_immval_walking] diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/setup.cfg b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/setup.cfg new file mode 100644 index 000000000..7b4085942 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/setup.cfg @@ -0,0 +1,16 @@ +[bumpversion] +current_version = 0.12.1 +commit = True +tag = True + +[bumpversion:file:riscv_ctg/__init__.py] +search = __version__ = '{current_version}' +replace = __version__ = '{new_version}' + +[bdist_wheel] +universal = 1 + +[flake8] +exclude = docs + +[aliases] diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/setup.py b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/setup.py new file mode 100644 index 000000000..cfba8937c --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/setup.py @@ -0,0 +1,63 @@ +# See LICENSE.incore.incore for details + +"""The setup script.""" + +from setuptools import setup, find_packages +import os +import riscv_ctg + +# Base directory of package +here = os.path.abspath(os.path.dirname(__file__)) + + +def read(*parts): + with codecs.open(os.path.join(here, *parts), 'r') as fp: + return fp.read() +def read_requires(): + with open(os.path.join(here, "riscv_ctg/requirements.txt"),"r") as reqfile: + return reqfile.read().splitlines() + +#Long Description +with open("README.rst", "r") as fh: + readme = fh.read() + +setup_requirements = [ ] + +test_requirements = [ ] + +setup( + name='riscv_ctg', + version=riscv_ctg.__version__, + description="RISC-V CTG", + long_description=readme + '\n\n', + classifiers=[ + "Programming Language :: Python :: 3.6", + "License :: OSI Approved :: BSD License", + "Development Status :: 4 - Beta" + ], + url='https://github.com/riscv/riscv-ctg', + author="InCore Semiconductors Pvt. Ltd.", + author_email='info@incoresemi.com', + license="BSD-3-Clause", + packages=find_packages(), + package_dir={'riscv_ctg': 'riscv_ctg'}, + package_data={ + 'riscv_ctg': [ + 'requirements.txt', + 'data/*', + 'env/*' + ] + }, + install_requires=read_requires(), + python_requires='>=3.6.0', + entry_points={ + 'console_scripts': [ + 'riscv_ctg=riscv_ctg.main:cli', + ], + }, + include_package_data=True, + keywords='riscv_ctg', + test_suite='tests', + tests_require=test_requirements, + zip_safe=False, +) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/tests/__init__.py b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/tests/__init__.py new file mode 100644 index 000000000..4dbe8ae81 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/tests/__init__.py @@ -0,0 +1,2 @@ +# See LICENSE.incore for details +"""Unit test package for riscv_ctg.""" diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/tests/env/arch_test.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/tests/env/arch_test.h new file mode 100644 index 000000000..eb4cb3e36 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/tests/env/arch_test.h @@ -0,0 +1,1503 @@ +#include "encoding.h" +// TODO the following should come from the YAML. +#ifndef NUM_SPECD_INTCAUSES + #define NUM_SPECD_INTCAUSES 16 +#endif +//#define RVTEST_FIXED_LEN +#ifndef UNROLLSZ + #define UNROLLSZ 5 +#endif +// #ifndef rvtest_gpr_save +// #define rvtest_gpr_save +// #endif + +//----------------------------------------------------------------------- +// RV Arch Test Macros +//----------------------------------------------------------------------- +#ifndef RVMODEL_SET_MSW_INT + #warning "RVMODEL_SET_MSW_INT is not defined by target. Declaring as empty macro" + #define RVMODEL_SET_MSW_INT +#endif + +#ifndef RVMODEL_CLEAR_MSW_INT + #warning "RVMODEL_CLEAR_MSW_INT is not defined by target. Declaring as empty macro" + #define RVMODEL_CLEAR_MSW_INT +#endif + +#ifndef RVMODEL_CLEAR_MTIMER_INT + #warning "RVMODEL_CLEAR_MTIMER_INT is not defined by target. Declaring as empty macro" + #define RVMODEL_CLEAR_MTIMER_INT +#endif + +#ifndef RVMODEL_CLEAR_MEXT_INT + #warning "RVMODEL_CLEAR_MEXT_INT is not defined by target. Declaring as empty macro" + #define RVMODEL_CLEAR_MEXT_INT +#endif + +#ifdef RVTEST_FIXED_LEN + #define LI(reg, val)\ + .option push;\ + .option norvc;\ + .align UNROLLSZ;\ + li reg,val;\ + .align UNROLLSZ;\ + .option pop; + + #define LA(reg, val)\ + .option push;\ + .option norvc;\ + .align UNROLLSZ;\ + la reg,val;\ + .align UNROLLSZ;\ + .option pop; + +#else + #define LI(reg,val);\ + .option push;\ + .option norvc;\ + li reg,val;\ + .option pop; + + #define LA(reg,val);\ + .option push;\ + .option norvc;\ + la reg,val;\ + .option pop; +#endif +#if XLEN==64 + #define SREG sd + #define LREG ld + #define LREGWU lwu + #define REGWIDTH 8 + #define MASK 0xFFFFFFFFFFFFFFFF + +#else + #if XLEN==32 + #define SREG sw + #define LREG lw + #define LREGWU lw + #define REGWIDTH 4 + #define MASK 0xFFFFFFFF + + #endif +#endif + +#if FLEN==64 + #define FLREG fld + #define FSREG fsd + #define FREGWIDTH 8 + #define SIGALIGN 8 +#else + #if FLEN==32 + #define FLREG flw + #define FSREG fsw + #define FREGWIDTH 4 + #endif +#endif + +#if FLEN>XLEN + #define SIGALIGN FREGWIDTH +#else + #define SIGALIGN REGWIDTH +#endif + + +#if SIGALIGN==8 + #define CANARY \ + .dword 0x6F5CA309E7D4B281 +#else + #define CANARY \ + .word 0x6F5CA309 +#endif + +#define MMODE_SIG 3 +#define RLENG (REGWIDTH<<3) + +#define RVTEST_ISA(_STR) + +#ifndef DATA_REL_TVAL_MSK + #define DATA_REL_TVAL_MSK 0x0F05 << (REGWIDTH*8-16) +#endif + +#ifndef CODE_REL_TVAL_MSK + #define CODE_REL_TVAL_MSK 0xD008 << (REGWIDTH*8-16) +#endif + +#define NAN_BOXED(__val__,__width__,__max__) \ + .if __width__ == 32 ;\ + .word __val__ ;\ + .else ;\ + .dword __val__ ;\ + .endif ;\ + .if __max__ > __width__ ;\ + .set pref_bytes,(__max__-__width__)/32 ;\ + .else ;\ + .set pref_bytes, 0 ;\ + .endif ;\ + .rept pref_bytes ;\ + .word 0xffffffff ;\ + .endr ; + + +#define ZERO_EXTEND(__val__,__width__,__max__) \ + .if __max__ > __width__ ;\ + .set pref_bytes,(__max__-__width__)/32 ;\ + .else ;\ + .set pref_bytes, 0 ;\ + .endif ;\ + .rept pref_bytes ;\ + .word 0 ;\ + .endr ;\ + .if __width__ == 32 ;\ + .word __val__ ;\ + .else ;\ + .dword __val__ ;\ + .endif; + +// ----------------------------------- CODE BEGIN w/ TRAP HANDLER START ------------------------ // + +.macro RVTEST_CODE_BEGIN + .align UNROLLSZ + .section .text.init; + .globl rvtest_init; \ + rvtest_init: +#ifdef rvtest_mtrap_routine + LA(x1, rvtest_trap_prolog ); + jalr ra, x1 + rvtest_prolog_done: +#endif + LI (x1, (0xFEEDBEADFEEDBEAD & MASK)); + LI (x2, (0xFF76DF56FF76DF56 & MASK)); + LI (x3, (0x7FBB6FAB7FBB6FAB & MASK)); + LI (x4, (0xBFDDB7D5BFDDB7D5 & MASK)); + LA (x5, rvtest_code_begin); + LA (x6, rvtest_data_begin); + LI (x7, (0xB7FBB6FAB7FBB6FA & MASK)); + LI (x8, (0x5BFDDB7D5BFDDB7D & MASK)); + LI (x9, (0xADFEEDBEADFEEDBE & MASK)); + LI (x10, (0x56FF76DF56FF76DF & MASK)); + LI (x11, (0xAB7FBB6FAB7FBB6F & MASK)); + LI (x12, (0xD5BFDDB7D5BFDDB7 & MASK)); + LI (x13, (0xEADFEEDBEADFEEDB & MASK)); + LI (x14, (0xF56FF76DF56FF76D & MASK)); + LI (x15, (0xFAB7FBB6FAB7FBB6 & MASK)); + #ifndef RVTEST_E + LI (x16, (0x7D5BFDDB7D5BFDDB & MASK)); + LI (x17, (0xBEADFEEDBEADFEED & MASK)); + LI (x18, (0xDF56FF76DF56FF76 & MASK)); + LI (x19, (0x6FAB7FBB6FAB7FBB & MASK)); + LI (x20, (0xB7D5BFDDB7D5BFDD & MASK)); + LI (x21, (0xDBEADFEEDBEADFEE & MASK)); + LI (x22, (0x6DF56FF76DF56FF7 & MASK)); + LI (x23, (0xB6FAB7FBB6FAB7FB & MASK)); + LI (x24, (0xDB7D5BFDDB7D5BFD & MASK)); + LI (x25, (0xEDBEADFEEDBEADFE & MASK)); + LI (x26, (0x76DF56FF76DF56FF & MASK)); + LI (x27, (0xBB6FAB7FBB6FAB7F & MASK)); + LI (x28, (0xDDB7D5BFDDB7D5BF & MASK)); + LI (x29, (0xEEDBEADFEEDBEADF & MASK)); + LI (x30, (0xF76DF56FF76DF56F & MASK)); + LI (x31, (0xFBB6FAB7FBB6FAB7 & MASK)); + #endif + .globl rvtest_code_begin + rvtest_code_begin: +.endm + +// --------------------------------- CODE BEGIN w/ TRAP HANDLER END -----------------------------// + +.macro RVTEST_CODE_END + .align 4; + .global rvtest_code_end + rvtest_code_end: +#ifdef rvtest_mtrap_routine + .option push + .option norvc + j exit_cleanup + + rvtest_trap_prolog: + /******************************************************************************/ + /**** Prolog, to be run before any tests ****/ + /**** #include 1 copy of this per mode in rvmodel_boot code? ****/ + /**** ------------------------------------------------------------------- ****/ + /**** if xTVEC isn't completely RW, then we need to change the code at its ****/ + /**** target. The entire trap trampoline and mtrap handler replaces the ****/ + /**** area pointed to by mtvec, after saving its original contents first. ****/ + /**** If it isn't possible to fully write that area, restore and fail. ****/ + /******************************************************************************/ + + //trap_handler_prolog; enter with t1..t6 available + + init_mscratch: + la t1, trapreg_sv + csrrw t1, CSR_MSCRATCH, t1 // swap old mscratch. mscratch not points to trapreg_sv + la t2, mscratch_save + SREG t1, 0(t2) // save old mscratch in mscratch_save region + csrr t1, CSR_MSCRATCH // read the trapreg_sv address + LA( t2, mtrap_sigptr ) // locate the start of the trap signature + SREG t2, 0(t1) // save mtrap_sigptr at first location of trapreg_sv + init_mtvec: + la t1, mtrampoline + la t4, mtvec_save + csrrw t2, CSR_MTVEC, t1 // swap mtvec and trap_trampoline + SREG t2, 0(t4) // save orig mtvec + csrr t3, CSR_MTVEC // now read new_mtval back + beq t3, t1, rvtest_prolog_done // if mtvec==trap_trampoline, mtvec is writable, continue + + /****************************************************************/ + /**** fixed mtvec, can't move it so move trampoline instead ****/ + /**** t1=trampoline, t2=oldmtvec, t3=save area, t4=save end ****/ + /****************************************************************/ + + // t2 = dut's original mtvec setting + // t1 = mtrampoline address + init_tramp: /**** copy trampoline at mtvec tgt ****/ + + csrw CSR_MTVEC, t2 // restore orig mtvec, will now attemp to copy trampoline to it + la t3, tramptbl_sv // addr of save area + addi t4, t3, NUM_SPECD_INTCAUSES*4 // end of save area + + overwrite_tt: // now build new trampoline table with offsets base from curr mtvec + lw t6, 0(t2) // get original mtvec target + sw t6, 0(t3) // save it + lw t5, 0(t1) // get trampoline src + sw t5, 0(t2) // overwrite mtvec target + lw t6, 0(t2) // rd it back to make sure it was written + bne t6, t5, resto_tramp // table isn't fully writable, restore and give up + addi t1, t1, 4 // next src index + addi t2, t2, 4 // next tgt index + addi t3, t3, 4 // next save index + bne t3, t4, overwrite_tt // not done, loop + j rvtest_prolog_done + + resto_tramp: // vector table not writeable, restore + LREG t1, 16(t4) // load mscratch_SAVE at fixed offset from table end + csrw CSR_MSCRATCH, t1 // restore mscratch + LREG t4, 8(t4) // load mtvec_SAVE (used as end of loop marker) + + + resto_loop: // goes backwards, t2= dest vec tbl ptr, t3=src save area ptr, t4=vec tbl begin + lw t6, 0(t3) // read saved tgt entry + sw t6, 0(t2) // restore original tgt + addi t2, t2, -4 // prev tgt index + addi t3, t3, -4 // prev save index + bne t2, t4, resto_loop // didn't restore to begining yet, loop + + j rvtest_end // failure to replace trampoline + + + #define mhandler \ + csrrw sp, CSR_MSCRATCH, sp; \ + SREG t6, 6*REGWIDTH(sp); \ + jal t6, common_prolog; + + /**********************************************************************/ + /**** This is the entry point for all m-modetraps, vectored or not.****/ + /**** At entry, mscratch will contain a pointer to a scratch area. ****/ + /**** This is an array of branches at 4B intevals that spreads out ****/ + /**** to an array of 32B mhandler macros for specd int causes, and ****/ + /**** to a return for anything above that (which causes a mismatch)****/ + /**********************************************************************/ + mtrampoline: // 64 or 32 entry table + .set value, 0 + .rept NUM_SPECD_INTCAUSES // located at each possible int vectors + j mtrap_handler + 12*(value) //offset < +/- 1MB + .set value, value + 1 + .endr + .rept RLENG-NUM_SPECD_INTCAUSES // fill at each impossible entry + mret + .endr + + mtrap_handler: /* after executing, sp points to temp save area, t4 is PC */ + .rept NUM_SPECD_INTCAUSES + mhandler + .endr + + common_prolog: + la t5, common_mhandler + jr t5 + /*********************************************************************/ + /**** common code for all ints & exceptions, will fork to handle ****/ + /**** each separately. The common handler first stores trap mode+ ****/ + /**** vector, and mcause signatures. All traps have 4wd sigs, but ****/ + /**** sw and timer ints only store 3 of the 4. ****/ + /**** sig offset Exception ExtInt SWInt TimerInt ****/ + /**** 0: tval IntID -1 -1 ****/ + /**** 4: mepc mip mip mip ****/ + /**** 8: <---------------------- mcause -------------> ****/ + /**** 12: <--------------------- Vect+mode ----------> ****/ + /*********************************************************************/ + /* in general, CSRs loaded in t2, addresses into t3 */ + + common_mhandler: /* enter with link in t6 */ + SREG t5, 5*REGWIDTH(sp) + SREG t4, 4*REGWIDTH(sp) + SREG t3, 3*REGWIDTH(sp) + SREG t2, 2*REGWIDTH(sp) + SREG t1, 1*REGWIDTH(sp) /* save other temporaries */ + + LREG t1, 0(sp) /* load trap sig pointer (runs backwards from DATA_END) */ + + LA( t3, mtrampoline) + sub t2, t6, t3 /* reloc “link” to 0..63 to show which int vector was taken */ + addi t2, t2, MMODE_SIG /* insert mode# into 1:0 */ + SREG t2, 0*REGWIDTH(t1) /* save 1st sig value, (vect, trapmode) */ + sv_mcause: + csrr t2, CSR_MCAUSE + SREG t2, 1*REGWIDTH(t1) /* save 2nd sig value, (mcause) */ + + bltz t2, common_mint_handler /* this is a interrupt, not a trap */ + + /********************************************************************/ + /**** This is the exceptions specific code, storing relative mepc****/ + /**** & relative tval signatures. tval is relocated by code or ****/ + /**** data start, or 0 depending on mcause. mepc signature value ****/ + /**** is relocated by code start, and restored adjusted depending****/ + /**** on op alignment so trapped op isn't re-executed. ****/ + /********************************************************************/ + common_mexcpt_handler: + csrr t2, CSR_MEPC + sv_mepc: + LA( t3, rvtest_prolog_done) /* offset to compensate for different loader offsets */ + sub t4, t2, t3 /* convert mepc to rel offset of beginning of test*/ + SREG t4, 2*REGWIDTH(t1) /* save 3rd sig value, (rel mepc) into trap signature area */ + adj_mepc: //adj mepc so there is padding after op, and its 8B aligned + andi t4, t2, 0x2 /* set to 2 if mepc was misaligned */ + sub t2, t2, t4 /* adjust mepc to prev 4B alignment */ + addi t2, t2, 0x8 /* adjust mepc, so it skips past the op, has padding & is 4B aligned */ + csrw CSR_MEPC, t2 /* restore adjusted value, has 1,2, or 3 bytes of padding */ + + + /* calculate relative mtval if it’s an address (by code_begin or data_begin amt) */ + /* note that masks that determine this are implementation specific from YAML */ + + /* masks are bit reversed, so mcause==0 bit is in MSB (so different for RV32 and RV64) */ + + adj_mtval: + csrr t2, CSR_MCAUSE /* code begin adjustment amount already in t3 */ + + LI(t4, CODE_REL_TVAL_MSK) /* trap#s 12, 3,1,0, -- adjust w/ code_begin */ + sll t4, t4, t2 /* put bit# in MSB */ + bltz t4, sv_mtval /* correct adjustment is code_begin in t3 */ + + LA( t3, mtrap_sigptr) /* adjustment assuming access is to signature region */ + LI(t4, DATA_REL_TVAL_MSK) /* trap#s not 14, 11..8, 2 adjust w/ data_begin */ + sll t4, t4, t2 /* put bit# in MSB */ + bgez t4, no_adj /* correct adjustment is data_begin in t3 */ + sigbound_chk: + csrr t4, CSR_MTVAL /* do a bounds check on mtval */ + bge t3, t4, sv_mtval /* if mtval is greater than the rvmodel_data_begin then use that as anchor */ + LA( t3, rvtest_data_begin) /* else change anchor to rvtest_data_begin */ + blt t3, t4, sv_mtval /* before the signature, use data_begin adj */ + mv t4, t3 /* use sig relative adjust */ + no_adj: + LI(t3, 0) /* else zero adjustment amt */ + + // For Illegal op handling + addi t2, t2, -2 /* check if mcause==2 (illegal op) */ + bnez t2, sv_mtval /* not illegal op, no special treatment */ + csrr t2, CSR_MTVAL + bnez t2, sv_mtval /* mtval isn’t zero, no special treatment */ + illop: + LI(t5, 0x20000) /* get mprv mask */ + csrrs t5, CSR_MSTATUS, t5 /* set mprv while saving the old value */ + csrr t3, CSR_MEPC + lhu t2, 0(t3) /* load 1st 16b of opc w/ old priv, endianess*/ + andi t4, t2, 0x3 + addi t4, t4, -0x3 /* does opcode[1:0]==0b11? (Meaning >16b op) */ + bnez t4, sv_mtval /* entire mtval is in tt2, adj amt will be set to zero */ + lhu t4, 2(t3) + sll t4, t4, 16 + or t3, t2, t4 /* get 2nd hwd, align it & insert it into opcode */ + csrw CSR_MSTATUS, t5 /* restore mstatus */ + +/*******FIXME: this will not handle 48 or 64b opcodes in an RV64) ********/ + + sv_mtval: + csrr t2, CSR_MTVAL + sub t2, t2, t3 /* perform mtval adjust by either code or data position or zero*/ + SREG t2, 3*REGWIDTH(t1) /* save 4th sig value, (rel mtval) into trap signature area */ + + resto_rtn: /* restore and return */ + addi t1, t1,4*REGWIDTH /* adjust trap signature ptr (traps always save 4 words) */ + SREG t1, 0*REGWIDTH(sp) /* save updated trap sig pointer (pts to trap_sigptr */ + + LREG t1, 1*REGWIDTH(sp) + LREG t2, 2*REGWIDTH(sp) + LREG t3, 3*REGWIDTH(sp) + LREG t4, 4*REGWIDTH(sp) + LREG t5, 5*REGWIDTH(sp) + LREG t6, 6*REGWIDTH(sp) /* restore temporaries */ + + csrrw sp, CSR_MSCRATCH, sp /* restore sp from scratch */ + mret + + common_mint_handler: /* t1 has sig ptr, t2 has mcause */ + + LI(t3, 1) + sll t3, t3, t2 /* create mask 1<> 1); \ + csrs mstatus, a0; \ + csrwi fcsr, 0 + +#ifdef pext_check_vxsat_ov +#define RVTEST_VXSAT_ENABLE()\ + li a0, MSTATUS_VS & (MSTATUS_VS >> 1); \ + csrs mstatus, a0; \ + clrov +#else +#define RVTEST_VXSAT_ENABLE() +#endif + +#define RVTEST_SIGBASE(_R,_TAG) \ + LA(_R,_TAG);\ + .set offset,0; + +.set offset,0; +#define _ARG5(_1ST,_2ND, _3RD,_4TH,_5TH,...) _5TH +#define _ARG4(_1ST,_2ND, _3RD,_4TH,...) _4TH +#define _ARG3(_1ST,_2ND, _3RD, ...) _3RD +#define _ARG2(_1ST,_2ND, ...) _2ND +#define _ARG1(_1ST,...) _1ST +#define NARG(...) _ARG5(__VA_OPT__(__VA_ARGS__,)4,3,2,1,0) + +#define LOAD_MEM_VAL(_LINST, _AREG, _RD, _OFF, _TREG) \ + .if _OFF >= 2048 ;\ + .set _off, _OFF%2048 ;\ + LI(_TREG, _OFF-_off) ;\ + add _AREG,_AREG,_TREG ;\ + .else ;\ + .set _off, _OFF ;\ + .endif ;\ + _LINST _RD, _off(_AREG) ;\ + .if _OFF >= 2048 ;\ + sub _AREG,_AREG,_TREG ;\ + .endif + + /* use this function to ensure individual signature stores don't exceed offset limits */ + /* if they would, then update the base by offset & reduce offset by -2048 */ + /* there is an option to pre-increment offset if there was a previous signture store */ + +#define CHK_OFFSET(_BREG, _SZ, _PRE_INC) \ + .if (_PRE_INC!=0) ;\ + .set offset, offset+_SZ ;\ + .endif ;\ + .if offset>=2048 ;\ + addi _BREG, _BREG, (2048 - _SZ) ;\ + .set offset, offset -(2048 - _SZ) ;\ + .endif + + + /* automatically adjust base and offset if offset gets too big */ + /* RVTEST_SIGUPD(basereg, sigreg) stores sigreg at offset(basereg) and updates offset by regwidth */ + /* RVTEST_SIGUPD(basereg, sigreg,newoff) stores sigreg at newoff(basereg) and updates offset to regwidth+newoff */ +#define RVTEST_SIGUPD(_BR,_R,...) \ + .if NARG(__VA_ARGS__) == 1 ;\ + .set offset,_ARG1(__VA_OPT__(__VA_ARGS__,0)) ;\ + .endif ;\ + CHK_OFFSET(_BR,REGWIDTH,0);\ + SREG _R,offset(_BR) ;\ + .set offset,offset+REGWIDTH + +#define RVTEST_SIGUPD_F(_BR,_R,_F,...) \ + .if NARG(__VA_ARGS__) == 1 ;\ + .set offset,_ARG1(__VA_OPT__(__VA_ARGS__,0)) ;\ + .endif ;\ + .if (offset & (SIGALIGN-1)) != 0 ;\ + .warning "Incorrect Offset Alignment for Signature.";\ + .err ;\ + .endif ;\ + CHK_OFFSET(_BR,SIGALIGN,0);\ + FSREG _R,offset(_BR) ;\ + CHK_OFFSET(_BR,SIGALIGN,1);\ + SREG _F,offset(_BR) ;\ + .set offset,offset+(SIGALIGN) + + +#define RVTEST_SIGUPD_FID(_BR,_R,_F,...) \ + .if NARG(__VA_ARGS__) == 1 ;\ + .set offset,_ARG1(__VA_OPT__(__VA_ARGS__,0)) ;\ + .endif ;\ + .if (offset & (SIGALIGN-1)) != 0 ;\ + .warning "Incorrect Offset Alignment for Signature.";\ + .err ;\ + .endif ;\ + CHK_OFFSET(_BR,SIGALIGN,0);\ + SREG _R,offset(_BR) ;\ + CHK_OFFSET(_BR,SIGALIGN,1);\ + SREG _F,offset(_BR) ;\ + .set offset,offset+(SIGALIGN) + +// for updating signatures when 'rd' is a paired register (64-bit) in Zpsfoperand extension in RV32. +#define RVTEST_SIGUPD_P64(_BR,_R,_R_HI,...) \ + .if NARG(__VA_ARGS__) == 0 ;\ + RVTEST_SIGUPD_FID(_BR,_R,_R_HI) ;\ + .else ;\ + RVTEST_SIGUPD_FID(_BR,_R,_R_HI,_ARG1(__VA_OPT__(__VA_ARGS__,0)));\ + .endif + +// for reading vxsat.OV flag in P-ext; and only reads the flag when Zicsr extension is present +#ifdef pext_check_vxsat_ov +#define RDOV(_F)\ + rdov _F +#else +#define RDOV(_F)\ + nop +#endif + +// for updating signatures that include flagreg when 'rd' is a paired register (64-bit) in Zpsfoperand extension in RV32. +#define RVTEST_SIGUPD_PK64(_BR,_R,_R_HI,_F,...)\ + .if NARG(__VA_ARGS__) == 1 ;\ + .set offset,_ARG1(__VA_OPT__(__VA_ARGS__,0)) ;\ + .endif ;\ + CHK_OFFSET(_BR,REGWIDTH,0);\ + SREG _R,offset(_BR) ;\ + CHK_OFFSET(_BR,REGWIDTH,1);\ + SREG _R_HI,offset+REGWIDTH(_BR) ;\ + RDOV(_F) ;\ + CHK_OFFSET(_BR,REGWIDTH,1);\ + SREG _F,offset+2*REGWIDTH(_BR) ;\ + .set offset,offset+(3*REGWIDTH) + +// for updating signatures that include flagreg for P-ext saturation instructions (RV32/RV64). +#define RVTEST_SIGUPD_PK(_BR,_R,_F,OFFSET)\ + RVTEST_SIGUPD_FID(_BR,_R,_F,OFFSET) + +#define RVTEST_VALBASEUPD(_BR,...)\ + .if NARG(__VA_ARGS__) == 0;\ + addi _BR,_BR,2040;\ + .endif;\ + .if NARG(__VA_ARGS__) == 1;\ + LA(_BR,_ARG1(__VA_ARGS__,x0));\ + .endif; + +#define RVTEST_VALBASEMOV(_NR,_BR)\ + add _NR, _BR, x0; +/* + * RVTEST_BASEUPD(base reg) - updates the base register the last signature address + REGWIDTH + * RVTEST_BASEUPD(base reg, new reg) - moves value of the next signature region to update into new reg + * The hidden variable offset is reset always +*/ + +#define RVTEST_BASEUPD(_BR,...)\ + .if NARG(__VA_ARGS__) == 0;\ + addi _BR,_BR,offset;\ + .endif;\ + .if NARG(__VA_ARGS__) == 1;\ + addi _ARG1(__VA_ARGS__,x0),_BR,offset;\ + .endif;\ + .set offset,0; + + + +//------------------------------ BORROWED FROM ANDREW's RISC-V TEST MACROS -----------------------// +#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1)) + +#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11)) + +#define TEST_JALR_OP(tempreg, rd, rs1, imm, swreg, offset,adj) \ +5: ;\ + LA(rd,5b ) ;\ + .if adj & 1 == 1 ;\ + LA(rs1, 3f-imm+adj-1 ) ;\ + jalr rd, imm+1(rs1) ;\ + .else ;\ + LA(rs1, 3f-imm+adj) ;\ + jalr rd, imm(rs1) ;\ + .endif ;\ + nop ;\ + nop ;\ + xori rd,rd, 0x2 ;\ + j 4f ;\ + ;\ +3: .if adj & 2 == 2 ;\ + .fill 2,1,0x00 ;\ + .endif ;\ + xori rd,rd, 0x3 ;\ + j 4f ;\ + .if adj&2 == 2 ;\ + .fill 2,1,0x00 ;\ + .endif ;\ + ;\ +4: LA(tempreg, 5b ) ;\ + andi tempreg,tempreg,~(3) ;\ + sub rd,rd,tempreg ;\ + RVTEST_SIGUPD(swreg,rd,offset) +//SREG rd, offset(swreg); + +#define TEST_JAL_OP(tempreg, rd, imm, label, swreg, offset, adj)\ +5: ;\ + LA(tempreg, 2f ) ;\ + jalr x0,0(tempreg) ;\ +6: LA(tempreg, 4f ) ;\ + jalr x0,0(tempreg) ;\ +1: .if (adj & 2 == 2) && (label == 1b) ;\ + .fill 2,1,0x00 ;\ + .endif ;\ + xori rd,rd, 0x1 ;\ + beq x0,x0,6b ;\ + .if (adj & 2 == 2) && (label == 1b) ;\ + .fill 2,1,0x00 ;\ + .endif ;\ + .if (imm/2) - 2 >= 0 ;\ + .set num,(imm/2)-2 ;\ + .else ;\ + .set num,0 ;\ + .endif ;\ + .ifc label, 3f ;\ + .set num,0 ;\ + .endif ;\ + .rept num ;\ + nop ;\ + .endr ;\ + ;\ +2: jal rd, label+(adj) ;\ + .if adj & 2 == 2 ;\ + nop ;\ + nop ;\ + .endif ;\ + xori rd,rd, 0x2 ;\ + j 4f ;\ + .if (imm/2) - 3 >= 0 ;\ + .set num,(imm/2)-3 ;\ + .else ;\ + .set num,0 ;\ + .endif ;\ + .ifc label, 1b ;\ + .set num,0 ;\ + .endif ;\ + .rept num ;\ + nop ;\ + .endr ;\ +3: .if (adj & 2 == 2) && (label == 3f) ;\ + .fill 2,1,0x00 ;\ + .endif ;\ + xori rd,rd, 0x3 ;\ + LA(tempreg, 4f ) ;\ + jalr x0,0(tempreg) ;\ + .if (adj&2 == 2) && (label == 3f) ;\ + .fill 2,1,0x00 ;\ + .endif ;\ +4: LA(tempreg, 5b ) ;\ + andi tempreg,tempreg,~(3) ;\ + sub rd,rd,tempreg ;\ + RVTEST_SIGUPD(swreg,rd,offset) +//SREG rd, offset(swreg); + +#define TEST_BRANCH_OP(inst, tempreg, reg1, reg2, val1, val2, imm, label, swreg, offset,adj) \ + LI(reg1, MASK_XLEN(val1)) ;\ + LI(reg2, MASK_XLEN(val2)) ;\ + addi tempreg,x0,0 ;\ + j 2f ;\ + ;\ +1: .if adj & 2 == 2 ;\ + .fill 2,1,0x00 ;\ + .endif ;\ + addi tempreg,tempreg, 0x1 ;\ + j 4f ;\ + .if adj & 2 == 2 ;\ + .fill 2,1,0x00 ;\ + .endif ;\ + .if (imm/2) - 2 >= 0 ;\ + .set num,(imm/2)-2 ;\ + .else ;\ + .set num,0 ;\ + .endif ;\ + .ifc label, 3f ;\ + .set num,0 ;\ + .endif ;\ + .rept num ;\ + nop ;\ + .endr ;\ + ;\ +2: inst reg1, reg2, label+adj ;\ + addi tempreg, tempreg,0x2 ;\ + j 4f ;\ + .if (imm/4) - 3 >= 0 ;\ + .set num,(imm/4)-3 ;\ + .else ;\ + .set num,0 ;\ + .endif ;\ + .ifc label, 1b ;\ + .set num,0 ;\ + .endif ;\ + .rept num ;\ + nop ;\ + .endr ;\ + ;\ +3: .if adj & 2 == 2 ;\ + .fill 2,1,0x00 ;\ + .endif ;\ + addi tempreg, tempreg,0x3 ;\ + j 4f ;\ + .if adj&2 == 2 ;\ + .fill 2,1,0x00 ;\ + .endif ;\ + ;\ +4: RVTEST_SIGUPD(swreg,tempreg,offset) +//SREG tempreg, offset(swreg); + +#define TEST_STORE(swreg,testreg,index,rs1,rs2,rs2_val,imm_val,offset,inst,adj) ;\ +LI(rs2,rs2_val) ;\ +addi rs1,swreg,offset+adj ;\ +LI(testreg,imm_val) ;\ +sub rs1,rs1,testreg ;\ +inst rs2, imm_val(rs1) ;\ +nop ;\ +nop + +#define TEST_LOAD(swreg,testreg,index,rs1,destreg,imm_val,offset,inst,adj) ;\ +LA(rs1,rvtest_data+(index*4)+adj-imm_val) ;\ +inst destreg, imm_val(rs1) ;\ +nop ;\ +nop ;\ +RVTEST_SIGUPD(swreg,destreg,offset) +//SREG destreg, offset(swreg); + +#define TEST_STORE_F(swreg,testreg,fcsr_val,rs1,rs2,imm_val,offset,inst,adj,flagreg,valaddr_reg, val_offset);\ +LOAD_MEM_VAL(FLREG, valaddr_reg, rs2, val_offset, testreg); \ +addi rs1,swreg,offset+adj ;\ +LI(testreg,imm_val) ;\ +sub rs1,rs1,testreg ;\ +inst rs2, imm_val(rs1) ;\ +nop ;\ +nop ;\ +csrr flagreg, fcsr ;\ +RVTEST_SIGUPD(swreg,flagreg,offset+SIGALIGN) + +#define TEST_LOAD_F(swreg,testreg,fcsr_val,rs1,destreg,imm_val,inst,adj,flagreg) ;\ +LA(rs1,rvtest_data+adj-imm_val) ;\ +LI(testreg, fcsr_val); csrw fcsr, testreg ;\ +inst destreg, imm_val(rs1) ;\ +nop ;\ +nop ;\ +csrr flagreg, fcsr ;\ +RVTEST_SIGUPD_F(swreg,destreg,flagreg) + +#define TEST_CSR_FIELD(ADDRESS,TEMP_REG,MASK_REG,NEG_MASK_REG,VAL,DEST_REG,OFFSET,BASE_REG) \ + LI(TEMP_REG,VAL);\ + and TEMP_REG,TEMP_REG,MASK_REG;\ + csrr DEST_REG,ADDRESS;\ + and DEST_REG,DEST_REG,NEG_MASK_REG;\ + or TEMP_REG,TEMP_REG,DEST_REG;\ + csrw ADDRESS,TEMP_REG;\ + csrr DEST_REG,ADDRESS;\ + RVTEST_SIGUPD(BASE_REG,DEST_REG,OFFSET) + +#define WRITE_TO_CSR_FIELD_W_MASK(ADDRESS,RESTORE_REG,TEMP_REG1,TEMP_REG2,MASK_VAL,VAL) \ + LI(TEMP_REG1,VAL);\ + LI(TEMP_REG2,MASK_VAL);\ + and TEMP_REG1,TEMP_REG1,TEMP_REG2;\ + csrr RESTORE_REG,ADDRESS;\ + not TEMP_REG2,TEMP_REG2;\ + and RESTORE_REG,RESTORE_REG,TEMP_REG2;\ + or TEMP_REG1,TEMP_REG1,RESTORE_REG;\ + csrrw RESTORE_REG,ADDRESS,TEMP_REG1;\ + +#define READ_CSR_REG_AND_UPD_SIG(ADDRESS,DEST_REG,OFFSET,BASE_REG) \ + csrr DEST_REG,ADDRESS;\ + RVTEST_SIGUPD(BASE_REG,DEST_REG,OFFSET) + +#define RESTORE_CSR_REG(ADDRESS,RESTORE_REG) \ + csrw ADDRESS,RESTORE_REG; + + +#define TEST_CASE(testreg, destreg, correctval, swreg, offset, code... ) \ + code; \ + RVTEST_SIGUPD(swreg,destreg,offset); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval) + +#define TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, code... ) \ + code; \ + RVTEST_SIGUPD_F(swreg,destreg,flagreg); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval) + +#define TEST_CASE_FID(testreg, destreg, correctval, swreg, flagreg, code... ) \ + code; \ + RVTEST_SIGUPD_FID(swreg,destreg,flagreg); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval) + +#define TEST_AUIPC(inst, destreg, correctval, imm, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + LA testreg, 1f; \ + 1: \ + inst destreg, imm; \ + sub destreg, destreg, testreg; \ + ) + +//Tests for instructions with register-immediate operand +#define TEST_IMM_OP( inst, destreg, reg, correctval, val, imm, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + LI(reg, MASK_XLEN(val)); \ + inst destreg, reg, SEXT_IMM(imm); \ + ) + +//Tests for floating-point instructions with a single register operand +#define TEST_FPSR_OP( inst, destreg, freg, rm, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \ + TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \ + LOAD_MEM_VAL(FLREG, valaddr_reg, freg, val_offset, testreg); \ + LI(testreg, fcsr_val); csrw fcsr, testreg; \ + inst destreg, freg, rm; \ + csrr flagreg, fcsr ; \ + ) + +//Tests for floating-point instructions with a single register operand +//This variant does not take the rm field and set it while writing the instruction +#define TEST_FPSR_OP_NRM( inst, destreg, freg, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \ + TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \ + LOAD_MEM_VAL(FLREG, valaddr_reg, freg, val_offset, testreg); \ + LI(testreg, fcsr_val); csrw fcsr, testreg; \ + inst destreg, freg; \ + csrr flagreg, fcsr ; \ + ) + +//Tests for floating-point instructions with a single register operand and integer destination register +#define TEST_FPID_OP( inst, destreg, freg, rm, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg,load_instr) \ + TEST_CASE_FID(testreg, destreg, correctval, swreg, flagreg, \ + LOAD_MEM_VAL(load_instr, valaddr_reg, freg, val_offset, testreg); \ + LI(testreg, fcsr_val); csrw fcsr, testreg; \ + inst destreg, freg, rm; \ + csrr flagreg, fcsr ; \ + ) + +//Tests for floating-point instructions with a single register operand and integer operand register +#define TEST_FPIO_OP( inst, destreg, freg, rm, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg, load_instr) \ + TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \ + LOAD_MEM_VAL(load_instr, valaddr_reg, freg, val_offset, testreg); \ + LI(testreg, fcsr_val); csrw fcsr, testreg; \ + inst destreg, freg, rm; \ + csrr flagreg, fcsr; \ + ) + +//Tests for floating-point instructions with a single register operand and integer destination register +//This variant does not take the rm field and set it while writing the instruction +#define TEST_FPID_OP_NRM( inst, destreg, freg, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \ + TEST_CASE_FID(testreg, destreg, correctval, swreg, flagreg, \ + LOAD_MEM_VAL(FLREG, valaddr_reg, freg, val_offset, testreg); \ + LI(testreg, fcsr_val); csrw fcsr, testreg; \ + inst destreg, freg; \ + csrr flagreg, fcsr ; \ + ) + +//Tests for floating-point instructions with one GPR operand and a single FPR result +//This variant does not take the rm field and set it while writing the instruction +#define TEST_FPIO_OP_NRM( inst, destreg, freg, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg, load_instr) \ + TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \ + LOAD_MEM_VAL(load_instr, valaddr_reg, freg, val_offset, testreg); \ + LI(testreg, fcsr_val); csrw fcsr, testreg; \ + inst destreg, freg; \ + csrr flagreg, fcsr; \ + ) + +//Tests for floating-point instructions with two GPR operands and a single FPR result +//This variant does not take the rm field and set it while writing the instruction +#define TEST_FPIOIO_OP_NRM(inst, destreg, freg1, freg2, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg, load_instr) \ + TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \ + LOAD_MEM_VAL(load_instr, valaddr_reg, freg1, val_offset, testreg); \ + LOAD_MEM_VAL(load_instr, valaddr_reg, freg2, (val_offset+FREGWIDTH), testreg); \ + LI(testreg, fcsr_val); csrw fcsr, testreg; \ + inst destreg, freg; \ + csrr flagreg, fcsr; \ + ) + +//Tests for instructions with register-register-immediate operands +#define TEST_RRI_OP(inst, destreg, reg1, reg2, imm, correctval, val1, val2, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + LI(reg1, MASK_XLEN(val1)); \ + LI(reg2, MASK_XLEN(val2)); \ + inst destreg, reg1, reg2, imm; \ + ) + +//Tests for a instructions with register-register operand +#define TEST_RI_OP(inst, destreg, reg2, imm, correctval, val1, val2, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + LI(destreg, MASK_XLEN(val1)); \ + LI(reg2, MASK_XLEN(val2)); \ + inst destreg, reg2, imm; \ + ) + +//Tests for a instructions with register-register operand +#define TEST_RR_OP(inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + LI(reg1, MASK_XLEN(val1)); \ + LI(reg2, MASK_XLEN(val2)); \ + inst destreg, reg1, reg2; \ + ) +//Tests for floating-point instructions with register-register operand +//This variant does not take the rm field and set it while writing the instruction +#define TEST_FPRR_OP_NRM(inst, destreg, freg1, freg2, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \ + TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \ + LOAD_MEM_VAL(FLREG, valaddr_reg, freg1, val_offset, testreg); \ + LOAD_MEM_VAL(FLREG, valaddr_reg, freg2, (val_offset+FREGWIDTH), testreg); \ + LI(testreg, fcsr_val); csrw fcsr, testreg; \ + inst destreg, freg1, freg2; \ + csrr flagreg, fcsr; \ + ) + +//Tests for floating-point instructions with register-register operand +#define TEST_FPRR_OP(inst, destreg, freg1, freg2, rm, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \ + TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \ + LOAD_MEM_VAL(FLREG, valaddr_reg, freg1, val_offset, testreg); \ + LOAD_MEM_VAL(FLREG, valaddr_reg, freg2, (val_offset+FREGWIDTH), testreg); \ + LI(testreg, fcsr_val); csrw fcsr, testreg; \ + inst destreg, freg1, freg2, rm; \ + csrr flagreg, fcsr; \ + ) + +//Tests for floating-point CMP instructions with register-register operand +#define TEST_FCMP_OP(inst, destreg, freg1, freg2, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \ + TEST_CASE_FID(testreg, destreg, correctval, swreg, flagreg, \ + LOAD_MEM_VAL(FLREG, valaddr_reg, freg1, val_offset, testreg); \ + LOAD_MEM_VAL(FLREG, valaddr_reg, freg2, (val_offset+FREGWIDTH), testreg); \ + LI(testreg, fcsr_val); csrw fcsr, testreg; \ + inst destreg, freg1, freg2; \ + csrr flagreg, fcsr ; \ + ) + +//Tests for floating-point R4 type instructions +#define TEST_FPR4_OP(inst, destreg, freg1, freg2, freg3, rm , fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \ + TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \ + LOAD_MEM_VAL(FLREG, valaddr_reg, freg1, val_offset, testreg); \ + LOAD_MEM_VAL(FLREG, valaddr_reg, freg2, (val_offset+FREGWIDTH), testreg); \ + LOAD_MEM_VAL(FLREG, valaddr_reg, freg3, (val_offset+2*FREGWIDTH), testreg); \ + LI(testreg, fcsr_val); csrw fcsr, testreg; \ + inst destreg, freg1, freg2, freg3, rm; \ + csrr flagreg, fcsr ; \ + ) + +#define TEST_CNOP_OP( inst, testreg, imm_val, swreg, offset) \ + TEST_CASE(testreg, x0, 0, swreg, offset, \ + inst imm_val; \ + ) + +//Tests for instructions with register-immediate operand and update the saturation flag +#define TEST_PKIMM_OP( inst, destreg, reg, correctval, val, imm, flagreg, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + LI(reg, MASK_XLEN(val)); \ + inst destreg, reg, SEXT_IMM(imm); \ + rdov flagreg; \ + ) + +//Tests for instructions with register-register operand and update the saturation flag +#define TEST_PKRR_OP(inst, destreg, reg1, reg2, correctval, val1, val2, flagreg, swreg, offset, testreg) \ + LI(reg1, MASK_XLEN(val1)); \ + LI(reg2, MASK_XLEN(val2)); \ + inst destreg, reg1, reg2; \ + rdov flagreg; \ + RVTEST_SIGUPD_PK(swreg, destreg, flagreg, offset); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval) + +//Tests for instructions with a single register operand and update the saturation flag +#define TEST_PKR_OP( inst, destreg, reg, correctval, val, flagreg, swreg, offset, testreg) \ + TEST_CASE_FID(testreg, destreg, correctval, swreg, flagreg, offset, \ + LI(reg, MASK_XLEN(val)); \ + inst destreg, reg; \ + rdov flagreg; \ + ) + +#if __riscv_xlen == 32 +//Tests for a instruction with register pair operands for all its three operands +#define TEST_P64_PPP_OP_32(inst, destreg, destreg_hi, reg1, reg1_hi, reg2, reg2_hi, correctval, correctval_hi, val1, val1_hi, val2, val2_hi, swreg, offset, testreg) \ + LI(reg1, MASK_XLEN(val1)); \ + LI(reg1_hi, MASK_XLEN(val1_hi)); \ + LI(reg2, MASK_XLEN(val2)); \ + LI(reg2_hi, MASK_XLEN(val2_hi)); \ + inst destreg, reg1, reg2; \ + RVTEST_SIGUPD_P64(swreg,destreg, destreg_hi, offset); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg_hi, correctval_hi) + +#define TEST_PK64_PPP_OP_32(inst, destreg, destreg_hi, reg1, reg1_hi, reg2, reg2_hi, correctval, correctval_hi, val1, val1_hi, val2, val2_hi, flagreg, swreg, offset, testreg) \ + LI(reg1, MASK_XLEN(val1)); \ + LI(reg1_hi, MASK_XLEN(val1_hi)); \ + LI(reg2, MASK_XLEN(val2)); \ + LI(reg2_hi, MASK_XLEN(val2_hi)); \ + inst destreg, reg1, reg2; \ + RVTEST_SIGUPD_PK64(swreg,destreg, destreg_hi, flagreg, offset); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg_hi, correctval_hi) + +#define TEST_P64_PPN_OP_32(inst, destreg, destreg_hi, reg1, reg1_hi, reg2, correctval, correctval_hi, val1, val1_hi, val2, swreg, offset, testreg) \ + LI(reg1, MASK_XLEN(val1)); \ + LI(reg1_hi, MASK_XLEN(val1_hi)); \ + LI(reg2, MASK_XLEN(val2)); \ + inst destreg, reg1, reg2; \ + RVTEST_SIGUPD_P64(swreg, destreg, destreg_hi, offset); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg_hi, correctval_hi) + +#define TEST_P64_PNN_OP_32(inst, destreg, destreg_hi, reg1, reg2, correctval, correctval_hi, val1, val2, swreg, offset, testreg) \ + LI(reg1, MASK_XLEN(val1)); \ + LI(reg2, MASK_XLEN(val2)); \ + inst destreg, reg1, reg2; \ + RVTEST_SIGUPD_P64(swreg, destreg, destreg_hi, offset); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg_hi, correctval_hi) + +#define TEST_PK64_PNN_OP_32(inst, destreg, destreg_hi, reg1, reg2, correctval, correctval_hi, val1, val2, flagreg, swreg, offset, testreg) \ + LI(reg1, MASK_XLEN(val1)); \ + LI(reg2, MASK_XLEN(val2)); \ + inst destreg, reg1, reg2; \ + RVTEST_SIGUPD_PK64(swreg, destreg, destreg_hi, flagreg, offset); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg_hi, correctval_hi) + +#define TEST_P64_NPN_OP_32(inst, destreg, reg1, reg1_hi, reg2, correctval, val1, val1_hi, val2, swreg, offset, testreg) \ + LI(reg1, MASK_XLEN(val1)); \ + LI(reg1_hi, MASK_XLEN(val1_hi)); \ + LI(reg2, MASK_XLEN(val2)); \ + inst destreg, reg1, reg2; \ + RVTEST_SIGUPD(swreg,destreg,offset); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval); + +#define TEST_P64_NP_OP_32(inst, destreg, reg1, reg1_hi, correctval, val1, val1_hi, imm_val, swreg, offset, testreg) \ + LI(reg1, MASK_XLEN(val1)); \ + LI(reg1_hi, MASK_XLEN(val1_hi)); \ + inst destreg, reg1, imm_val; \ + RVTEST_SIGUPD(swreg,destreg,offset); \ + RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval); + +//Tests for a instruction with pair register rd, pair register rs1 and pair register rs2 +#define TEST_P64_PPP_OP(inst, rd, rd_hi, rs1, rs1_hi, rs2, rs2_hi, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, rs2_val_hi, swreg, offset, testreg) \ + TEST_P64_PPP_OP_32(inst, rd, rd_hi, rs1, rs1_hi, rs2, rs2_hi, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, rs2_val_hi, swreg, offset, testreg) +#define TEST_PK64_PPP_OP(inst, rd, rd_hi, rs1, rs1_hi, rs2, rs2_hi, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, rs2_val_hi, flagreg, swreg, offset, testreg) \ + TEST_PK64_PPP_OP_32(inst, rd, rd_hi, rs1, rs1_hi, rs2, rs2_hi, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, rs2_val_hi, flagreg, swreg, offset, testreg) +//Tests for a instruction with pair register rd, pair register rs1 and normal register rs2 +#define TEST_P64_PPN_OP(inst, rd, rd_hi, rs1, rs1_hi, rs2, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, swreg, offset, testreg) \ + TEST_P64_PPN_OP_32(inst, rd, rd_hi, rs1, rs1_hi, rs2, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, swreg, offset, testreg) +//Tests for a instruction with pair register rd, normal register rs1 and normal register rs2 +#define TEST_P64_PNN_OP(inst, rd, rd_hi, rs1, rs2, correctval, correctval_hi, rs1_val, rs2_val, swreg, offset, testreg) \ + TEST_P64_PNN_OP_32(inst, rd, rd_hi, rs1, rs2, correctval, correctval_hi, rs1_val, rs2_val, swreg, offset, testreg) +//Tests for a instruction with pair register rd, normal register rs1 and normal register rs2 +#define TEST_PK64_PNN_OP(inst, rd, rd_hi, rs1, rs2, correctval, correctval_hi, rs1_val, rs2_val, flagreg, swreg, offset, testreg) \ + TEST_PK64_PNN_OP_32(inst, rd, rd_hi, rs1, rs2, correctval, correctval_hi, rs1_val, rs2_val, flagreg, swreg, offset, testreg) +//Tests for a instruction with normal register rd, pair register rs1 and normal register rs2 +#define TEST_P64_NPN_OP(inst, rd, rs1, rs1_hi, rs2, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, swreg, offset, testreg) \ + TEST_P64_NPN_OP_32(inst, rd, rs1, rs1_hi, rs2, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, swreg, offset, testreg) +//Tests for a instruction with normal register rd, pair register rs1 +#define TEST_P64_NP_OP(inst, rd, rs1, rs1_hi, correctval, correctval_hi, rs1_val, rs1_val_hi, imm_val, swreg, offset, testreg) \ + TEST_P64_NP_OP_32(inst, rd, rs1, rs1_hi, correctval, correctval_hi, rs1_val, rs1_val_hi, imm_val, swreg, offset, testreg) + +#else + +// When in rv64, there are no instructions with pair operand, so Macro is redefined to normal TEST_RR_OP +#define TEST_P64_PPP_OP(inst, rd, rd_hi, rs1, rs1_hi, rs2, rs2_hi, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, rs2_val_hi, swreg, offset, testreg) \ + TEST_RR_OP(inst, rd, rs1, rs2, correctval, rs1_val, rs2_val, swreg, offset, testreg) +#define TEST_PK64_PPP_OP(inst, rd, rd_hi, rs1, rs1_hi, rs2, rs2_hi, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, rs2_val_hi, flagreg, swreg, offset, testreg) \ + TEST_PKRR_OP(inst, rd, rs1, rs2, correctval, rs1_val, rs2_val, flagreg, swreg, offset, testreg) +#define TEST_P64_PPN_OP(inst, rd, rd_hi, rs1, rs1_hi, rs2, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, swreg, offset, testreg) \ + TEST_RR_OP(inst, rd, rs1, rs2, correctval, rs1_val, rs2_val, swreg, offset, testreg) +#define TEST_P64_PNN_OP(inst, rd, rd_hi, rs1, rs2, correctval, correctval_hi, rs1_val, rs2_val, swreg, offset, testreg) \ + TEST_RR_OP(inst, rd, rs1, rs2, correctval, rs1_val, rs2_val, swreg, offset, testreg) +#define TEST_PK64_PNN_OP(inst, rd, rd_hi, rs1, rs2, correctval, correctval_hi, rs1_val, rs2_val, flagreg, swreg, offset, testreg) \ + TEST_PKRR_OP(inst, rd, rs1, rs2, correctval, rs1_val, rs2_val, flagreg, swreg, offset, testreg) +#define TEST_P64_NPN_OP(inst, rd, rs1, rs1_hi, rs2, correctval, correctval_hi, rs1_val, rs1_val_hi, rs2_val, swreg, offset, testreg) \ + TEST_RR_OP(inst, rd, rs1, rs2, correctval, rs1_val, rs2_val, swreg, offset, testreg) +#define TEST_P64_NP_OP(inst, rd, rs1, rs1_hi, correctval, correctval_hi, rs1_val, rs1_val_hi, imm_val, swreg, offset, testreg) \ + TEST_IMM_OP(inst, rd, rs1, correctval, rs1_val, imm_val, swreg, offset, testreg) + +#endif + + + + +#define TEST_CMV_OP( inst, destreg, reg, correctval, val2, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + LI(reg, MASK_XLEN(val2)); \ + inst destreg, reg; \ + ) + +#define TEST_CR_OP( inst, destreg, reg, correctval, val1, val2, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + LI(reg, MASK_XLEN(val2)); \ + LI(destreg, MASK_XLEN(val1)); \ + inst destreg, reg; \ + ) + +#define TEST_CI_OP( inst, destreg, correctval, val, imm, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + LI(destreg, MASK_XLEN(val)); \ + inst destreg, imm; \ + ) + +#define TEST_CADDI4SPN_OP( inst, destreg, correctval, imm, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + LI(x2, 0); \ + inst destreg, x2,imm; \ + ) + +//Tests for instructions with a single register operand +#define TEST_RD_OP(inst, destreg, reg1, correctval, val1, swreg, offset, testreg) \ + TEST_CMV_OP(inst, destreg, reg1, correctval, val1, swreg, offset, testreg) + +#define TEST_CBRANCH_OP(inst, tempreg, reg2, val2, imm, label, swreg, offset) \ + LI(reg2, MASK_XLEN(val2)) ;\ + j 2f ;\ + addi tempreg, x0,0 ;\ + .option push ;\ + .option norvc ;\ +1: addi tempreg, tempreg,0x1 ;\ + j 4f ;\ + .option pop ;\ + .if (imm/2) - 4 >= 0 ;\ + .set num,(imm/2)-4 ;\ + .else ;\ + .set num,0 ;\ + .endif ;\ + .ifc label, 3f ;\ + .set num,0 ;\ + .endif ;\ + .rept num ;\ + c.nop ;\ + .endr ;\ +2: inst reg2, label ;\ + .option push ;\ + .option norvc ;\ + addi tempreg, tempreg, 0x2 ;\ + j 4f ;\ + .option pop ;\ + .if (imm/2) - 5 >= 0 ;\ + .set num,(imm/2)-5 ;\ + .else ;\ + .set num,0 ;\ + .endif ;\ + .ifc label, 1b ;\ + .set num,0 ;\ + .endif ;\ + .rept num ;\ + c.nop ;\ + .endr ;\ + ;\ +3: addi tempreg, tempreg ,0x3 ;\ + ;\ +4: RVTEST_SIGUPD(swreg,tempreg,offset) +//SREG tempreg, offset(swreg); + + +#define TEST_CJ_OP(inst, tempreg, imm, label, swreg, offset) \ + .option push ;\ + .option norvc ;\ + j 2f ;\ + addi tempreg,x0,0 ;\ +1: addi tempreg, tempreg,0x1 ;\ + j 4f ;\ + .option pop ;\ + .if (imm/2) - 4 >= 0 ;\ + .set num,(imm/2)-4 ;\ + .else ;\ + .set num,0 ;\ + .endif ;\ + .ifc label, 3f ;\ + .set num,0 ;\ + .endif ;\ + .rept num ;\ + c.nop ;\ + .endr ;\ +2: inst label ;\ + .option push ;\ + .option norvc ;\ + addi tempreg, tempreg, 0x2 ;\ + j 4f ;\ + .option pop ;\ + .if (imm/2) - 5 >= 0 ;\ + .set num,(imm/2)-5 ;\ + .else ;\ + .set num,0 ;\ + .endif ;\ + .ifc label, 1b ;\ + .set num,0 ;\ + .endif ;\ + .rept num ;\ + c.nop ;\ + .endr ;\ + ;\ +3: addi tempreg, tempreg, 0x3 ;\ + ;\ +4: RVTEST_SIGUPD(swreg,tempreg,offset) +//SREG tempreg, offset(swreg); + +#define TEST_CJAL_OP(inst, tempreg, imm, label, swreg, offset) \ +5: ;\ + j 2f ;\ + ;\ + .option push ;\ + .option norvc ;\ +1: xori x1,x1, 0x1 ;\ + j 4f ;\ + .option pop ;\ + .if (imm/2) - 4 >= 0 ;\ + .set num,(imm/2)-4 ;\ + .else ;\ + .set num,0 ;\ + .endif ;\ + .ifc label, 3f ;\ + .set num,0 ;\ + .endif ;\ + .rept num ;\ + c.nop ;\ + .endr ;\ +2: inst label ;\ + .option push ;\ + .option norvc ;\ + xori x1,x1, 0x2 ;\ + j 4f ;\ + .option pop ;\ + .if (imm/2) - 5 >= 0 ;\ + .set num,(imm/2)-5 ;\ + .else ;\ + .set num,0 ;\ + .endif ;\ + .ifc label, 1b ;\ + .set num,0 ;\ + .endif ;\ + .rept num ;\ + c.nop ;\ + .endr ;\ + ;\ +3: xori x1,x1, 0x3 ;\ + ;\ +4: LA(tempreg, 5b) ;\ + andi tempreg,tempreg,~(3) ;\ + sub x1,x1,tempreg ;\ + RVTEST_SIGUPD(swreg,x1,offset) +//SREG x1, offset(swreg); + +#define TEST_CJR_OP(tempreg, rs1, swreg, offset) \ +5: ;\ + LA(rs1, 3f) ;\ + ;\ +2: c.jr rs1 ;\ + xori rs1,rs1, 0x2 ;\ + j 4f ;\ + ;\ +3: xori rs1,rs1, 0x3 ;\ + ;\ +4: LA(tempreg, 5b) ;\ + andi tempreg,tempreg,~(3) ;\ + sub rs1,rs1,tempreg ;\ + RVTEST_SIGUPD(swreg,rs1,offset) +//SREG rs1, offset(swreg); + +#define TEST_CJALR_OP(tempreg, rs1, swreg, offset) \ +5: ;\ + LA(rs1, 3f ) ;\ + ;\ +2: c.jalr rs1 ;\ + xori x1,x1, 0x2 ;\ + j 4f ;\ + ;\ +3: xori x1,x1, 0x3 ;\ + ;\ +4: LA(tempreg, 5b ) ;\ + andi tempreg,tempreg,~(3) ;\ + sub x1,x1,tempreg ;\ + RVTEST_SIGUPD(swreg,x1,offset) +//SREG x1, offset(swreg); + + +//--------------------------------- Migration aliases ------------------------------------------ +#ifdef RV_COMPLIANCE_RV32M + #warning "RV_COMPLIANCE_RV32M macro will be deprecated." + #define RVMODEL_BOOT \ + RVTEST_IO_INIT; \ + RV_COMPLIANCE_RV32M ; \ + RV_COMPLIANCE_CODE_BEGIN +#endif + +#define SWSIG(a, b) + +#ifdef RV_COMPLIANCE_DATA_BEGIN + #warning "RV_COMPLIANCE_DATA_BEGIN macro deprecated in v0.2. Please use RVMODEL_DATA_BEGIN instead" + #define RVMODEL_DATA_BEGIN \ + RV_COMPLIANCE_DATA_BEGIN +#endif + +#ifdef RV_COMPLIANCE_DATA_END + #warning "RV_COMPLIANCE_DATA_END macro deprecated in v0.2. Please use RVMODEL_DATA_END instead" + #define RVMODEL_DATA_END \ + RV_COMPLIANCE_DATA_END +#endif + +#ifdef RV_COMPLIANCE_HALT + #warning "RV_COMPLIANCE_HALT macro deprecated in v0.2. Please use RVMODEL_HALT instead" + #define RVMODEL_HALT \ + RV_COMPLIANCE_HALT +#endif + +#ifdef RVTEST_IO_ASSERT_GPR_EQ + #warning "RVTEST_IO_ASSERT_GPR_EQ macro deprecated in v0.2. Please use RVMODEL_IO_ASSERT_GPR_EQ instead" + #define RVMODEL_IO_ASSERT_GPR_EQ(_SP, _R, _I) \ + RVTEST_IO_ASSERT_GPR_EQ(_SP,_R, _I) +#endif + +#ifdef RVTEST_IO_WRITE_STR + #warning "RVTEST_IO_WRITE_STR macro deprecated in v0.2. Please use RVMODEL_IO_WRITE_STR instead" + #define RVMODEL_IO_WRITE_STR(_SP, _STR) \ + RVTEST_IO_WRITE_STR(_SP, _STR) +#endif + +#ifdef RVTEST_IO_INIT + #warning "RVTEST_IO_INIT is deprecated in v0.2. Please use RVMODEL_BOOT for initialization" +#endif + +#ifdef RVTEST_IO_CHECK + #warning "RVTEST_IO_CHECK is deprecated in v0.2. +#endif diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/tests/env/encoding.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/tests/env/encoding.h new file mode 100644 index 000000000..9d6d8f180 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/tests/env/encoding.h @@ -0,0 +1,1496 @@ +/* +* Copyright (c) 2012-2015, The Regents of the University of California (Regents). +* All Rights Reserved. +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* 1. Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* 2. Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* 3. Neither the name of the Regents nor the +* names of its contributors may be used to endorse or promote products +* derived from this software without specific prior written permission. +* IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, +* SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING +* OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +* PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED +* HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE +* MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + +*/ +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_HPP 0x00000600 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_VS 0x00000600 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_SUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_TVM 0x00100000 +#define MSTATUS_TW 0x00200000 +#define MSTATUS_TSR 0x00400000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS_UXL 0x0000000300000000 +#define MSTATUS_SXL 0x0000000C00000000 +#define MSTATUS64_SD 0x8000000000000000 + +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_SUM 0x00040000 +#define SSTATUS_MXR 0x00080000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS_UXL 0x0000000300000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define DCSR_XDEBUGVER (3U<<30) +#define DCSR_NDRESET (1<<29) +#define DCSR_FULLRESET (1<<28) +#define DCSR_EBREAKM (1<<15) +#define DCSR_EBREAKH (1<<14) +#define DCSR_EBREAKS (1<<13) +#define DCSR_EBREAKU (1<<12) +#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STOPTIME (1<<9) +#define DCSR_CAUSE (7<<6) +#define DCSR_DEBUGINT (1<<5) +#define DCSR_HALT (1<<3) +#define DCSR_STEP (1<<2) +#define DCSR_PRV (3<<0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 + +#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) + +#define MCONTROL_SELECT (1<<19) +#define MCONTROL_TIMING (1<<18) +#define MCONTROL_ACTION (0x3f<<12) +#define MCONTROL_CHAIN (1<<11) +#define MCONTROL_MATCH (0xf<<7) +#define MCONTROL_M (1<<6) +#define MCONTROL_H (1<<5) +#define MCONTROL_S (1<<4) +#define MCONTROL_U (1<<3) +#define MCONTROL_EXECUTE (1<<2) +#define MCONTROL_STORE (1<<1) +#define MCONTROL_LOAD (1<<0) + +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define SATP32_MODE 0x80000000 +#define SATP32_ASID 0x7FC00000 +#define SATP32_PPN 0x003FFFFF +#define SATP64_MODE 0xF000000000000000 +#define SATP64_ASID 0x0FFFF00000000000 +#define SATP64_PPN 0x00000FFFFFFFFFFF + +#define SATP_MODE_OFF 0 +#define SATP_MODE_SV32 1 +#define SATP_MODE_SV39 8 +#define SATP_MODE_SV48 9 +#define SATP_MODE_SV57 10 +#define SATP_MODE_SV64 11 + +#define PMP_R 0x01 +#define PMP_W 0x02 +#define PMP_X 0x04 +#define PMP_A 0x18 +#define PMP_L 0x80 +#define PMP_SHIFT 2 + +#define PMP_TOR 0x08 +#define PMP_NA4 0x10 +#define PMP_NAPOT 0x18 + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#define DEFAULT_RSTVEC 0x00001000 +#define CLINT_BASE 0x02000000 +#define CLINT_SIZE 0x000c0000 +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 + +// page table entry (PTE) fields +#define PTE_V 0x001 // Valid +#define PTE_R 0x002 // Read +#define PTE_W 0x004 // Write +#define PTE_X 0x008 // Execute +#define PTE_U 0x010 // User +#define PTE_G 0x020 // Global +#define PTE_A 0x040 // Accessed +#define PTE_D 0x080 // Dirty +#define PTE_SOFT 0x300 // Reserved for Software + +#define PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#ifdef __riscv + +#if __riscv_xlen == 64 +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD +# define RISCV_PGLEVEL_BITS 9 +# define SATP_MODE SATP64_MODE +#else +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD +# define RISCV_PGLEVEL_BITS 10 +# define SATP_MODE SATP32_MODE +#endif +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +#ifdef __GNUC__ + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ + asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) + +#define swap_csr(reg, val) ({ unsigned long __tmp; \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ + __tmp; }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; }) + +#define rdtime() read_csr(time) +#define rdcycle() read_csr(cycle) +#define rdinstret() read_csr(instret) + +#endif + +#endif + +#endif + +#endif +/* Automatically generated by parse-opcodes. */ +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +#define MATCH_BEQ 0x63 +#define MASK_BEQ 0x707f +#define MATCH_BNE 0x1063 +#define MASK_BNE 0x707f +#define MATCH_BLT 0x4063 +#define MASK_BLT 0x707f +#define MATCH_BGE 0x5063 +#define MASK_BGE 0x707f +#define MATCH_BLTU 0x6063 +#define MASK_BLTU 0x707f +#define MATCH_BGEU 0x7063 +#define MASK_BGEU 0x707f +#define MATCH_JALR 0x67 +#define MASK_JALR 0x707f +#define MATCH_JAL 0x6f +#define MASK_JAL 0x7f +#define MATCH_LUI 0x37 +#define MASK_LUI 0x7f +#define MATCH_AUIPC 0x17 +#define MASK_AUIPC 0x7f +#define MATCH_ADDI 0x13 +#define MASK_ADDI 0x707f +#define MATCH_SLLI 0x1013 +#define MASK_SLLI 0xfc00707f +#define MATCH_SLTI 0x2013 +#define MASK_SLTI 0x707f +#define MATCH_SLTIU 0x3013 +#define MASK_SLTIU 0x707f +#define MATCH_XORI 0x4013 +#define MASK_XORI 0x707f +#define MATCH_SRLI 0x5013 +#define MASK_SRLI 0xfc00707f +#define MATCH_SRAI 0x40005013 +#define MASK_SRAI 0xfc00707f +#define MATCH_ORI 0x6013 +#define MASK_ORI 0x707f +#define MATCH_ANDI 0x7013 +#define MASK_ANDI 0x707f +#define MATCH_ADD 0x33 +#define MASK_ADD 0xfe00707f +#define MATCH_SUB 0x40000033 +#define MASK_SUB 0xfe00707f +#define MATCH_SLL 0x1033 +#define MASK_SLL 0xfe00707f +#define MATCH_SLT 0x2033 +#define MASK_SLT 0xfe00707f +#define MATCH_SLTU 0x3033 +#define MASK_SLTU 0xfe00707f +#define MATCH_XOR 0x4033 +#define MASK_XOR 0xfe00707f +#define MATCH_SRL 0x5033 +#define MASK_SRL 0xfe00707f +#define MATCH_SRA 0x40005033 +#define MASK_SRA 0xfe00707f +#define MATCH_OR 0x6033 +#define MASK_OR 0xfe00707f +#define MATCH_AND 0x7033 +#define MASK_AND 0xfe00707f +#define MATCH_ADDIW 0x1b +#define MASK_ADDIW 0x707f +#define MATCH_SLLIW 0x101b +#define MASK_SLLIW 0xfe00707f +#define MATCH_SRLIW 0x501b +#define MASK_SRLIW 0xfe00707f +#define MATCH_SRAIW 0x4000501b +#define MASK_SRAIW 0xfe00707f +#define MATCH_ADDW 0x3b +#define MASK_ADDW 0xfe00707f +#define MATCH_SUBW 0x4000003b +#define MASK_SUBW 0xfe00707f +#define MATCH_SLLW 0x103b +#define MASK_SLLW 0xfe00707f +#define MATCH_SRLW 0x503b +#define MASK_SRLW 0xfe00707f +#define MATCH_SRAW 0x4000503b +#define MASK_SRAW 0xfe00707f +#define MATCH_LB 0x3 +#define MASK_LB 0x707f +#define MATCH_LH 0x1003 +#define MASK_LH 0x707f +#define MATCH_LW 0x2003 +#define MASK_LW 0x707f +#define MATCH_LD 0x3003 +#define MASK_LD 0x707f +#define MATCH_LBU 0x4003 +#define MASK_LBU 0x707f +#define MATCH_LHU 0x5003 +#define MASK_LHU 0x707f +#define MATCH_LWU 0x6003 +#define MASK_LWU 0x707f +#define MATCH_SB 0x23 +#define MASK_SB 0x707f +#define MATCH_SH 0x1023 +#define MASK_SH 0x707f +#define MATCH_SW 0x2023 +#define MASK_SW 0x707f +#define MATCH_SD 0x3023 +#define MASK_SD 0x707f +#define MATCH_FENCE 0xf +#define MASK_FENCE 0x707f +#define MATCH_FENCE_I 0x100f +#define MASK_FENCE_I 0x707f +#define MATCH_MUL 0x2000033 +#define MASK_MUL 0xfe00707f +#define MATCH_MULH 0x2001033 +#define MASK_MULH 0xfe00707f +#define MATCH_MULHSU 0x2002033 +#define MASK_MULHSU 0xfe00707f +#define MATCH_MULHU 0x2003033 +#define MASK_MULHU 0xfe00707f +#define MATCH_DIV 0x2004033 +#define MASK_DIV 0xfe00707f +#define MATCH_DIVU 0x2005033 +#define MASK_DIVU 0xfe00707f +#define MATCH_REM 0x2006033 +#define MASK_REM 0xfe00707f +#define MATCH_REMU 0x2007033 +#define MASK_REMU 0xfe00707f +#define MATCH_MULW 0x200003b +#define MASK_MULW 0xfe00707f +#define MATCH_DIVW 0x200403b +#define MASK_DIVW 0xfe00707f +#define MATCH_DIVUW 0x200503b +#define MASK_DIVUW 0xfe00707f +#define MATCH_REMW 0x200603b +#define MASK_REMW 0xfe00707f +#define MATCH_REMUW 0x200703b +#define MASK_REMUW 0xfe00707f +#define MATCH_AMOADD_W 0x202f +#define MASK_AMOADD_W 0xf800707f +#define MATCH_AMOXOR_W 0x2000202f +#define MASK_AMOXOR_W 0xf800707f +#define MATCH_AMOOR_W 0x4000202f +#define MASK_AMOOR_W 0xf800707f +#define MATCH_AMOAND_W 0x6000202f +#define MASK_AMOAND_W 0xf800707f +#define MATCH_AMOMIN_W 0x8000202f +#define MASK_AMOMIN_W 0xf800707f +#define MATCH_AMOMAX_W 0xa000202f +#define MASK_AMOMAX_W 0xf800707f +#define MATCH_AMOMINU_W 0xc000202f +#define MASK_AMOMINU_W 0xf800707f +#define MATCH_AMOMAXU_W 0xe000202f +#define MASK_AMOMAXU_W 0xf800707f +#define MATCH_AMOSWAP_W 0x800202f +#define MASK_AMOSWAP_W 0xf800707f +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_SC_W 0x1800202f +#define MASK_SC_W 0xf800707f +#define MATCH_AMOADD_D 0x302f +#define MASK_AMOADD_D 0xf800707f +#define MATCH_AMOXOR_D 0x2000302f +#define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOOR_D 0x4000302f +#define MASK_AMOOR_D 0xf800707f +#define MATCH_AMOAND_D 0x6000302f +#define MASK_AMOAND_D 0xf800707f +#define MATCH_AMOMIN_D 0x8000302f +#define MASK_AMOMIN_D 0xf800707f +#define MATCH_AMOMAX_D 0xa000302f +#define MASK_AMOMAX_D 0xf800707f +#define MATCH_AMOMINU_D 0xc000302f +#define MASK_AMOMINU_D 0xf800707f +#define MATCH_AMOMAXU_D 0xe000302f +#define MASK_AMOMAXU_D 0xf800707f +#define MATCH_AMOSWAP_D 0x800302f +#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_LR_D 0x1000302f +#define MASK_LR_D 0xf9f0707f +#define MATCH_SC_D 0x1800302f +#define MASK_SC_D 0xf800707f +#define MATCH_ECALL 0x73 +#define MASK_ECALL 0xffffffff +#define MATCH_EBREAK 0x100073 +#define MASK_EBREAK 0xffffffff +#define MATCH_URET 0x200073 +#define MASK_URET 0xffffffff +#define MATCH_SRET 0x10200073 +#define MASK_SRET 0xffffffff +#define MATCH_MRET 0x30200073 +#define MASK_MRET 0xffffffff +#define MATCH_DRET 0x7b200073 +#define MASK_DRET 0xffffffff +#define MATCH_SFENCE_VMA 0x12000073 +#define MASK_SFENCE_VMA 0xfe007fff +#define MATCH_WFI 0x10500073 +#define MASK_WFI 0xffffffff +#define MATCH_CSRRW 0x1073 +#define MASK_CSRRW 0x707f +#define MATCH_CSRRS 0x2073 +#define MASK_CSRRS 0x707f +#define MATCH_CSRRC 0x3073 +#define MASK_CSRRC 0x707f +#define MATCH_CSRRWI 0x5073 +#define MASK_CSRRWI 0x707f +#define MATCH_CSRRSI 0x6073 +#define MASK_CSRRSI 0x707f +#define MATCH_CSRRCI 0x7073 +#define MASK_CSRRCI 0x707f +#define MATCH_FADD_S 0x53 +#define MASK_FADD_S 0xfe00007f +#define MATCH_FSUB_S 0x8000053 +#define MASK_FSUB_S 0xfe00007f +#define MATCH_FMUL_S 0x10000053 +#define MASK_FMUL_S 0xfe00007f +#define MATCH_FDIV_S 0x18000053 +#define MASK_FDIV_S 0xfe00007f +#define MATCH_FSGNJ_S 0x20000053 +#define MASK_FSGNJ_S 0xfe00707f +#define MATCH_FSGNJN_S 0x20001053 +#define MASK_FSGNJN_S 0xfe00707f +#define MATCH_FSGNJX_S 0x20002053 +#define MASK_FSGNJX_S 0xfe00707f +#define MATCH_FMIN_S 0x28000053 +#define MASK_FMIN_S 0xfe00707f +#define MATCH_FMAX_S 0x28001053 +#define MASK_FMAX_S 0xfe00707f +#define MATCH_FSQRT_S 0x58000053 +#define MASK_FSQRT_S 0xfff0007f +#define MATCH_FADD_D 0x2000053 +#define MASK_FADD_D 0xfe00007f +#define MATCH_FSUB_D 0xa000053 +#define MASK_FSUB_D 0xfe00007f +#define MATCH_FMUL_D 0x12000053 +#define MASK_FMUL_D 0xfe00007f +#define MATCH_FDIV_D 0x1a000053 +#define MASK_FDIV_D 0xfe00007f +#define MATCH_FSGNJ_D 0x22000053 +#define MASK_FSGNJ_D 0xfe00707f +#define MATCH_FSGNJN_D 0x22001053 +#define MASK_FSGNJN_D 0xfe00707f +#define MATCH_FSGNJX_D 0x22002053 +#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_FMIN_D 0x2a000053 +#define MASK_FMIN_D 0xfe00707f +#define MATCH_FMAX_D 0x2a001053 +#define MASK_FMAX_D 0xfe00707f +#define MATCH_FCVT_S_D 0x40100053 +#define MASK_FCVT_S_D 0xfff0007f +#define MATCH_FCVT_D_S 0x42000053 +#define MASK_FCVT_D_S 0xfff0007f +#define MATCH_FSQRT_D 0x5a000053 +#define MASK_FSQRT_D 0xfff0007f +#define MATCH_FADD_Q 0x6000053 +#define MASK_FADD_Q 0xfe00007f +#define MATCH_FSUB_Q 0xe000053 +#define MASK_FSUB_Q 0xfe00007f +#define MATCH_FMUL_Q 0x16000053 +#define MASK_FMUL_Q 0xfe00007f +#define MATCH_FDIV_Q 0x1e000053 +#define MASK_FDIV_Q 0xfe00007f +#define MATCH_FSGNJ_Q 0x26000053 +#define MASK_FSGNJ_Q 0xfe00707f +#define MATCH_FSGNJN_Q 0x26001053 +#define MASK_FSGNJN_Q 0xfe00707f +#define MATCH_FSGNJX_Q 0x26002053 +#define MASK_FSGNJX_Q 0xfe00707f +#define MATCH_FMIN_Q 0x2e000053 +#define MASK_FMIN_Q 0xfe00707f +#define MATCH_FMAX_Q 0x2e001053 +#define MASK_FMAX_Q 0xfe00707f +#define MATCH_FCVT_S_Q 0x40300053 +#define MASK_FCVT_S_Q 0xfff0007f +#define MATCH_FCVT_Q_S 0x46000053 +#define MASK_FCVT_Q_S 0xfff0007f +#define MATCH_FCVT_D_Q 0x42300053 +#define MASK_FCVT_D_Q 0xfff0007f +#define MATCH_FCVT_Q_D 0x46100053 +#define MASK_FCVT_Q_D 0xfff0007f +#define MATCH_FSQRT_Q 0x5e000053 +#define MASK_FSQRT_Q 0xfff0007f +#define MATCH_FLE_S 0xa0000053 +#define MASK_FLE_S 0xfe00707f +#define MATCH_FLT_S 0xa0001053 +#define MASK_FLT_S 0xfe00707f +#define MATCH_FEQ_S 0xa0002053 +#define MASK_FEQ_S 0xfe00707f +#define MATCH_FLE_D 0xa2000053 +#define MASK_FLE_D 0xfe00707f +#define MATCH_FLT_D 0xa2001053 +#define MASK_FLT_D 0xfe00707f +#define MATCH_FEQ_D 0xa2002053 +#define MASK_FEQ_D 0xfe00707f +#define MATCH_FLE_Q 0xa6000053 +#define MASK_FLE_Q 0xfe00707f +#define MATCH_FLT_Q 0xa6001053 +#define MASK_FLT_Q 0xfe00707f +#define MATCH_FEQ_Q 0xa6002053 +#define MASK_FEQ_Q 0xfe00707f +#define MATCH_FCVT_W_S 0xc0000053 +#define MASK_FCVT_W_S 0xfff0007f +#define MATCH_FCVT_WU_S 0xc0100053 +#define MASK_FCVT_WU_S 0xfff0007f +#define MATCH_FCVT_L_S 0xc0200053 +#define MASK_FCVT_L_S 0xfff0007f +#define MATCH_FCVT_LU_S 0xc0300053 +#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_FMV_X_W 0xe0000053 +#define MASK_FMV_X_W 0xfff0707f +#define MATCH_FCLASS_S 0xe0001053 +#define MASK_FCLASS_S 0xfff0707f +#define MATCH_FCVT_W_D 0xc2000053 +#define MASK_FCVT_W_D 0xfff0007f +#define MATCH_FCVT_WU_D 0xc2100053 +#define MASK_FCVT_WU_D 0xfff0007f +#define MATCH_FCVT_L_D 0xc2200053 +#define MASK_FCVT_L_D 0xfff0007f +#define MATCH_FCVT_LU_D 0xc2300053 +#define MASK_FCVT_LU_D 0xfff0007f +#define MATCH_FMV_X_D 0xe2000053 +#define MASK_FMV_X_D 0xfff0707f +#define MATCH_FCLASS_D 0xe2001053 +#define MASK_FCLASS_D 0xfff0707f +#define MATCH_FCVT_W_Q 0xc6000053 +#define MASK_FCVT_W_Q 0xfff0007f +#define MATCH_FCVT_WU_Q 0xc6100053 +#define MASK_FCVT_WU_Q 0xfff0007f +#define MATCH_FCVT_L_Q 0xc6200053 +#define MASK_FCVT_L_Q 0xfff0007f +#define MATCH_FCVT_LU_Q 0xc6300053 +#define MASK_FCVT_LU_Q 0xfff0007f +#define MATCH_FMV_X_Q 0xe6000053 +#define MASK_FMV_X_Q 0xfff0707f +#define MATCH_FCLASS_Q 0xe6001053 +#define MASK_FCLASS_Q 0xfff0707f +#define MATCH_FCVT_S_W 0xd0000053 +#define MASK_FCVT_S_W 0xfff0007f +#define MATCH_FCVT_S_WU 0xd0100053 +#define MASK_FCVT_S_WU 0xfff0007f +#define MATCH_FCVT_S_L 0xd0200053 +#define MASK_FCVT_S_L 0xfff0007f +#define MATCH_FCVT_S_LU 0xd0300053 +#define MASK_FCVT_S_LU 0xfff0007f +#define MATCH_FMV_W_X 0xf0000053 +#define MASK_FMV_W_X 0xfff0707f +#define MATCH_FCVT_D_W 0xd2000053 +#define MASK_FCVT_D_W 0xfff0007f +#define MATCH_FCVT_D_WU 0xd2100053 +#define MASK_FCVT_D_WU 0xfff0007f +#define MATCH_FCVT_D_L 0xd2200053 +#define MASK_FCVT_D_L 0xfff0007f +#define MATCH_FCVT_D_LU 0xd2300053 +#define MASK_FCVT_D_LU 0xfff0007f +#define MATCH_FMV_D_X 0xf2000053 +#define MASK_FMV_D_X 0xfff0707f +#define MATCH_FCVT_Q_W 0xd6000053 +#define MASK_FCVT_Q_W 0xfff0007f +#define MATCH_FCVT_Q_WU 0xd6100053 +#define MASK_FCVT_Q_WU 0xfff0007f +#define MATCH_FCVT_Q_L 0xd6200053 +#define MASK_FCVT_Q_L 0xfff0007f +#define MATCH_FCVT_Q_LU 0xd6300053 +#define MASK_FCVT_Q_LU 0xfff0007f +#define MATCH_FMV_Q_X 0xf6000053 +#define MASK_FMV_Q_X 0xfff0707f +#define MATCH_FLW 0x2007 +#define MASK_FLW 0x707f +#define MATCH_FLD 0x3007 +#define MASK_FLD 0x707f +#define MATCH_FLQ 0x4007 +#define MASK_FLQ 0x707f +#define MATCH_FSW 0x2027 +#define MASK_FSW 0x707f +#define MATCH_FSD 0x3027 +#define MASK_FSD 0x707f +#define MATCH_FSQ 0x4027 +#define MASK_FSQ 0x707f +#define MATCH_FMADD_S 0x43 +#define MASK_FMADD_S 0x600007f +#define MATCH_FMSUB_S 0x47 +#define MASK_FMSUB_S 0x600007f +#define MATCH_FNMSUB_S 0x4b +#define MASK_FNMSUB_S 0x600007f +#define MATCH_FNMADD_S 0x4f +#define MASK_FNMADD_S 0x600007f +#define MATCH_FMADD_D 0x2000043 +#define MASK_FMADD_D 0x600007f +#define MATCH_FMSUB_D 0x2000047 +#define MASK_FMSUB_D 0x600007f +#define MATCH_FNMSUB_D 0x200004b +#define MASK_FNMSUB_D 0x600007f +#define MATCH_FNMADD_D 0x200004f +#define MASK_FNMADD_D 0x600007f +#define MATCH_FMADD_Q 0x6000043 +#define MASK_FMADD_Q 0x600007f +#define MATCH_FMSUB_Q 0x6000047 +#define MASK_FMSUB_Q 0x600007f +#define MATCH_FNMSUB_Q 0x600004b +#define MASK_FNMSUB_Q 0x600007f +#define MATCH_FNMADD_Q 0x600004f +#define MASK_FNMADD_Q 0x600007f +#define MATCH_C_NOP 0x1 +#define MASK_C_NOP 0xffff +#define MATCH_C_ADDI16SP 0x6101 +#define MASK_C_ADDI16SP 0xef83 +#define MATCH_C_JR 0x8002 +#define MASK_C_JR 0xf07f +#define MATCH_C_JALR 0x9002 +#define MASK_C_JALR 0xf07f +#define MATCH_C_EBREAK 0x9002 +#define MASK_C_EBREAK 0xffff +#define MATCH_C_LD 0x6000 +#define MASK_C_LD 0xe003 +#define MATCH_C_SD 0xe000 +#define MASK_C_SD 0xe003 +#define MATCH_C_ADDIW 0x2001 +#define MASK_C_ADDIW 0xe003 +#define MATCH_C_LDSP 0x6002 +#define MASK_C_LDSP 0xe003 +#define MATCH_C_SDSP 0xe002 +#define MASK_C_SDSP 0xe003 +#define MATCH_C_ADDI4SPN 0x0 +#define MASK_C_ADDI4SPN 0xe003 +#define MATCH_C_FLD 0x2000 +#define MASK_C_FLD 0xe003 +#define MATCH_C_LW 0x4000 +#define MASK_C_LW 0xe003 +#define MATCH_C_FLW 0x6000 +#define MASK_C_FLW 0xe003 +#define MATCH_C_FSD 0xa000 +#define MASK_C_FSD 0xe003 +#define MATCH_C_SW 0xc000 +#define MASK_C_SW 0xe003 +#define MATCH_C_FSW 0xe000 +#define MASK_C_FSW 0xe003 +#define MATCH_C_ADDI 0x1 +#define MASK_C_ADDI 0xe003 +#define MATCH_C_JAL 0x2001 +#define MASK_C_JAL 0xe003 +#define MATCH_C_LI 0x4001 +#define MASK_C_LI 0xe003 +#define MATCH_C_LUI 0x6001 +#define MASK_C_LUI 0xe003 +#define MATCH_C_SRLI 0x8001 +#define MASK_C_SRLI 0xec03 +#define MATCH_C_SRAI 0x8401 +#define MASK_C_SRAI 0xec03 +#define MATCH_C_ANDI 0x8801 +#define MASK_C_ANDI 0xec03 +#define MATCH_C_SUB 0x8c01 +#define MASK_C_SUB 0xfc63 +#define MATCH_C_XOR 0x8c21 +#define MASK_C_XOR 0xfc63 +#define MATCH_C_OR 0x8c41 +#define MASK_C_OR 0xfc63 +#define MATCH_C_AND 0x8c61 +#define MASK_C_AND 0xfc63 +#define MATCH_C_SUBW 0x9c01 +#define MASK_C_SUBW 0xfc63 +#define MATCH_C_ADDW 0x9c21 +#define MASK_C_ADDW 0xfc63 +#define MATCH_C_J 0xa001 +#define MASK_C_J 0xe003 +#define MATCH_C_BEQZ 0xc001 +#define MASK_C_BEQZ 0xe003 +#define MATCH_C_BNEZ 0xe001 +#define MASK_C_BNEZ 0xe003 +#define MATCH_C_SLLI 0x2 +#define MASK_C_SLLI 0xe003 +#define MATCH_C_FLDSP 0x2002 +#define MASK_C_FLDSP 0xe003 +#define MATCH_C_LWSP 0x4002 +#define MASK_C_LWSP 0xe003 +#define MATCH_C_FLWSP 0x6002 +#define MASK_C_FLWSP 0xe003 +#define MATCH_C_MV 0x8002 +#define MASK_C_MV 0xf003 +#define MATCH_C_ADD 0x9002 +#define MASK_C_ADD 0xf003 +#define MATCH_C_FSDSP 0xa002 +#define MASK_C_FSDSP 0xe003 +#define MATCH_C_SWSP 0xc002 +#define MASK_C_SWSP 0xe003 +#define MATCH_C_FSWSP 0xe002 +#define MASK_C_FSWSP 0xe003 +#define MATCH_CUSTOM0 0xb +#define MASK_CUSTOM0 0x707f +#define MATCH_CUSTOM0_RS1 0x200b +#define MASK_CUSTOM0_RS1 0x707f +#define MATCH_CUSTOM0_RS1_RS2 0x300b +#define MASK_CUSTOM0_RS1_RS2 0x707f +#define MATCH_CUSTOM0_RD 0x400b +#define MASK_CUSTOM0_RD 0x707f +#define MATCH_CUSTOM0_RD_RS1 0x600b +#define MASK_CUSTOM0_RD_RS1 0x707f +#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b +#define MASK_CUSTOM0_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM1 0x2b +#define MASK_CUSTOM1 0x707f +#define MATCH_CUSTOM1_RS1 0x202b +#define MASK_CUSTOM1_RS1 0x707f +#define MATCH_CUSTOM1_RS1_RS2 0x302b +#define MASK_CUSTOM1_RS1_RS2 0x707f +#define MATCH_CUSTOM1_RD 0x402b +#define MASK_CUSTOM1_RD 0x707f +#define MATCH_CUSTOM1_RD_RS1 0x602b +#define MASK_CUSTOM1_RD_RS1 0x707f +#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b +#define MASK_CUSTOM1_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM2 0x5b +#define MASK_CUSTOM2 0x707f +#define MATCH_CUSTOM2_RS1 0x205b +#define MASK_CUSTOM2_RS1 0x707f +#define MATCH_CUSTOM2_RS1_RS2 0x305b +#define MASK_CUSTOM2_RS1_RS2 0x707f +#define MATCH_CUSTOM2_RD 0x405b +#define MASK_CUSTOM2_RD 0x707f +#define MATCH_CUSTOM2_RD_RS1 0x605b +#define MASK_CUSTOM2_RD_RS1 0x707f +#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b +#define MASK_CUSTOM2_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM3 0x7b +#define MASK_CUSTOM3 0x707f +#define MATCH_CUSTOM3_RS1 0x207b +#define MASK_CUSTOM3_RS1 0x707f +#define MATCH_CUSTOM3_RS1_RS2 0x307b +#define MASK_CUSTOM3_RS1_RS2 0x707f +#define MATCH_CUSTOM3_RD 0x407b +#define MASK_CUSTOM3_RD 0x707f +#define MATCH_CUSTOM3_RD_RS1 0x607b +#define MASK_CUSTOM3_RD_RS1 0x707f +#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b +#define MASK_CUSTOM3_RD_RS1_RS2 0x707f +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 +#define CSR_SATP 0x180 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MTVAL 0x343 +#define CSR_MIP 0x344 +#define CSR_PMPCFG0 0x3a0 +#define CSR_PMPCFG1 0x3a1 +#define CSR_PMPCFG2 0x3a2 +#define CSR_PMPCFG3 0x3a3 +#define CSR_PMPADDR0 0x3b0 +#define CSR_PMPADDR1 0x3b1 +#define CSR_PMPADDR2 0x3b2 +#define CSR_PMPADDR3 0x3b3 +#define CSR_PMPADDR4 0x3b4 +#define CSR_PMPADDR5 0x3b5 +#define CSR_PMPADDR6 0x3b6 +#define CSR_PMPADDR7 0x3b7 +#define CSR_PMPADDR8 0x3b8 +#define CSR_PMPADDR9 0x3b9 +#define CSR_PMPADDR10 0x3ba +#define CSR_PMPADDR11 0x3bb +#define CSR_PMPADDR12 0x3bc +#define CSR_PMPADDR13 0x3bd +#define CSR_PMPADDR14 0x3be +#define CSR_PMPADDR15 0x3bf +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FETCH_ACCESS 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_LOAD_ACCESS 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_STORE_ACCESS 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#define CAUSE_FETCH_PAGE_FAULT 0xc +#define CAUSE_LOAD_PAGE_FAULT 0xd +#define CAUSE_STORE_PAGE_FAULT 0xf +#define CSR_MENTROPY 0xF15 +#define CSR_MNOISE 0x7A9 +#endif +#ifdef DECLARE_INSN +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(uret, MATCH_URET, MASK_URET) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) +DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) +DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) +DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) +DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) +DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) +DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) +DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) +DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) +DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) +DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) +DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) +DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) +DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) +DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) +DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) +DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) +DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) +DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) +DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q) +DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) +DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) +DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) +DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) +DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) +DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) +DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) +DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) +DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) +DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) +DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) +DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) +DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) +DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) +DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) +DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) +DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) +DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) +DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) +DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) +DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) +DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) +DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) +DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) +DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) +DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) +DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) +DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) +DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) +DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) +DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) +DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) +DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) +DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) +DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) +DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) +DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) +DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) +DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) +DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) +DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) +DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) +DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) +DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) +DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) +#endif +#ifdef DECLARE_CSR +DECLARE_CSR(fflags, CSR_FFLAGS) +DECLARE_CSR(frm, CSR_FRM) +DECLARE_CSR(fcsr, CSR_FCSR) +DECLARE_CSR(cycle, CSR_CYCLE) +DECLARE_CSR(time, CSR_TIME) +DECLARE_CSR(instret, CSR_INSTRET) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) +DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(sie, CSR_SIE) +DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(scounteren, CSR_SCOUNTEREN) +DECLARE_CSR(sscratch, CSR_SSCRATCH) +DECLARE_CSR(sepc, CSR_SEPC) +DECLARE_CSR(scause, CSR_SCAUSE) +DECLARE_CSR(stval, CSR_STVAL) +DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(satp, CSR_SATP) +DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(misa, CSR_MISA) +DECLARE_CSR(medeleg, CSR_MEDELEG) +DECLARE_CSR(mideleg, CSR_MIDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) +DECLARE_CSR(mscratch, CSR_MSCRATCH) +DECLARE_CSR(mepc, CSR_MEPC) +DECLARE_CSR(mcause, CSR_MCAUSE) +DECLARE_CSR(mtval, CSR_MTVAL) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) +DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) +DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) +DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) +DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) +DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) +DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) +DECLARE_CSR(pmpaddr3, CSR_PMPADDR3) +DECLARE_CSR(pmpaddr4, CSR_PMPADDR4) +DECLARE_CSR(pmpaddr5, CSR_PMPADDR5) +DECLARE_CSR(pmpaddr6, CSR_PMPADDR6) +DECLARE_CSR(pmpaddr7, CSR_PMPADDR7) +DECLARE_CSR(pmpaddr8, CSR_PMPADDR8) +DECLARE_CSR(pmpaddr9, CSR_PMPADDR9) +DECLARE_CSR(pmpaddr10, CSR_PMPADDR10) +DECLARE_CSR(pmpaddr11, CSR_PMPADDR11) +DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) +DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) +DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) +DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) +DECLARE_CSR(tselect, CSR_TSELECT) +DECLARE_CSR(tdata1, CSR_TDATA1) +DECLARE_CSR(tdata2, CSR_TDATA2) +DECLARE_CSR(tdata3, CSR_TDATA3) +DECLARE_CSR(dcsr, CSR_DCSR) +DECLARE_CSR(dpc, CSR_DPC) +DECLARE_CSR(dscratch, CSR_DSCRATCH) +DECLARE_CSR(mcycle, CSR_MCYCLE) +DECLARE_CSR(minstret, CSR_MINSTRET) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) +DECLARE_CSR(mvendorid, CSR_MVENDORID) +DECLARE_CSR(marchid, CSR_MARCHID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(cycleh, CSR_CYCLEH) +DECLARE_CSR(timeh, CSR_TIMEH) +DECLARE_CSR(instreth, CSR_INSTRETH) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) +DECLARE_CSR(mcycleh, CSR_MCYCLEH) +DECLARE_CSR(minstreth, CSR_MINSTRETH) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) +#endif +#ifdef DECLARE_CAUSE +DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) +DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS) +DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) +DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) +DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) +DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS) +DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) +DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS) +DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) +DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) +DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) +DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) +DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) +DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) +DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT) +#endif diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/tests/fadd.q_b1-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/tests/fadd.q_b1-01.S new file mode 100644 index 000000000..a04e3ab91 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/tests/fadd.q_b1-01.S @@ -0,0 +1,910 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Wed Jun 26 18:18:33 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/skulkarni/cvw/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/skulkarni/cvw/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fadd.q.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fadd.q instruction of the RISC-V RV64FDQ_Zicsr extension for the fadd.q_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64IFDQ_Zicsr") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Q.*);def TEST_CASE_1=True;",fadd.q_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==f25, rs2==f2, rd==f0,fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 0 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f25; op2:f2; dest:f0; op1val:0x0; op2val:0x0; + valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f0, f25, f2, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rs2 == rd, rs1==f3, rs2==f3, rd==f3,fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 1 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f3; op2:f3; dest:f3; op1val:0x0; op2val:0x0; + valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f3, f3, f3, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_2: +// rs2 == rd != rs1, rs1==f9, rs2==f11, rd==f11,fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 0 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f9; op2:f11; dest:f11; op1val:0x0; op2val:0x1; + valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f11, f9, f11, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_3: +// rs1 == rd != rs2, rs1==f7, rs2==f22, rd==f7,fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 1 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f7; op2:f22; dest:f7; op1val:0x0; op2val:0x80000000000000000000000000000001; + valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f7, f7, f22, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_4: +// rs1 == rs2 != rd, rs1==f31, rs2==f31, rd==f25,fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 0 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f31; op2:f31; dest:f25; op1val:0x0; op2val:0x0; + valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f25, f31, f31, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f29, rs2==f30, rd==f5,fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 1 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f29; op2:f30; dest:f5; op1val:0x0; op2val:0x80000000000000000000000000000002; + valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f5, f29, f30, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f21, rs2==f10, rd==f26,fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 0 and fe2 == 0x0000 and fm2 == 0xffffffffffffffffffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f21; op2:f10; dest:f26; op1val:0x0; op2val:0xffffffffffffffffffffffffffff; + valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f26, f21, f10, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f14, rs2==f5, rd==f13,fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 1 and fe2 == 0x0000 and fm2 == 0xffffffffffffffffffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f14; op2:f5; dest:f13; op1val:0x0; op2val:0x8000ffffffffffffffffffffffffffff; + valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f13, f14, f5, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f28, rs2==f1, rd==f18,fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 0 and fe2 == 0x0001 and fm2 == 0x0000000000000000000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f28; op2:f1; dest:f18; op1val:0x0; op2val:0x10000000000000000000000000000; + valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f18, f28, f1, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f16, rs2==f19, rd==f2,fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 1 and fe2 == 0x0001 and fm2 == 0x0000000000000000000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f16; op2:f19; dest:f2; op1val:0x0; op2val:0x80010000000000000000000000000000; + valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f2, f16, f19, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f23, rs2==f28, rd==f8,fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 0 and fe2 == 0x0001 and fm2 == 0x0000000000000000000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f23; op2:f28; dest:f8; op1val:0x0; op2val:0x10000000000000000000000000002; + valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f8, f23, f28, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f1, rs2==f23, rd==f10,fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 1 and fe2 == 0x0001 and fm2 == 0x0000000000000000000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f1; op2:f23; dest:f10; op1val:0x0; op2val:0x80010000000000000000000000000002; + valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f10, f1, f23, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f4, rs2==f18, rd==f1,fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 0 and fe2 == 0x7ffe and fm2 == 0xffffffffffffffffffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f4; op2:f18; dest:f1; op1val:0x0; op2val:0x7ffeffffffffffffffffffffffffffff; + valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f1, f4, f18, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f0, rs2==f12, rd==f28,fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 1 and fe2 == 0x7fff and fm2 == 0xefffffffffffffffffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f0; op2:f12; dest:f28; op1val:0x0; op2val:0xffffefffffffffffffffffffffffffff; + valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f28, f0, f12, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f10, rs2==f13, rd==f27,fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 0 and fe2 == 0x7fff and fm2 == 0x0000000000000000000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f10; op2:f13; dest:f27; op1val:0x0; op2val:0x7fff0000000000000000000000000000; + valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f27, f10, f13, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f22, rs2==f20, rd==f15,fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 1 and fe2 == 0x7fff and fm2 == 0x0000000000000000000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f22; op2:f20; dest:f15; op1val:0x0; op2val:0xffff0000000000000000000000000000; + valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f15, f22, f20, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f19, rs2==f6, rd==f20,fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 0 and fe2 == 0x7fff and fm2 == 0x8000000000000000000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f19; op2:f6; dest:f20; op1val:0x0; op2val:0x7fff8000000000000000000000000000; + valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f20, f19, f6, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f5, rs2==f26, rd==f16,fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 1 and fe2 == 0x7fff and fm2 == 0x8000000000000000000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f5; op2:f26; dest:f16; op1val:0x0; op2val:0xffff8000000000000000000000000000; + valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f16, f5, f26, dyn, 0, 0, x3, 34*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f26, rs2==f0, rd==f19,fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 0 and fe2 == 0x7fff and fm2 == 0x8000000000000000000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f26; op2:f0; dest:f19; op1val:0x0; op2val:0x7fff8000000000000000000000000001; + valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f19, f26, f0, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f12, rs2==f17, rd==f4,fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 1 and fe2 == 0x7fff and fm2 == 0x8000000000000000000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f12; op2:f17; dest:f4; op1val:0x0; op2val:0xffff8000000000000000000000000001; + valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f4, f12, f17, dyn, 0, 0, x3, 38*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f2, rs2==f15, rd==f24,fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 0 and fe2 == 0x7fff and fm2 == 0x0000000000000000000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f2; op2:f15; dest:f24; op1val:0x0; op2val:0x7fff0000000000000000000000000001; + valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f24, f2, f15, dyn, 0, 0, x3, 40*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f11, rs2==f24, rd==f30,fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 1 and fe2 == 0x7fff and fm2 == 0x0000000000000000000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f11; op2:f24; dest:f30; op1val:0x0; op2val:0xffff0000000000000000000000000001; + valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f30, f11, f24, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f27, rs2==f29, rd==f6,fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 0 and fe2 == 0x3fff and fm2 == 0x0000000000000000000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f27; op2:f29; dest:f6; op1val:0x0; op2val:0x3fff0000000000000000000000000000; + valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f6, f27, f29, dyn, 0, 0, x3, 44*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f30, rs2==f27, rd==f17,fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 1 and fe2 == 0x3fff and fm2 == 0x0000000000000000000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f27; dest:f17; op1val:0x0; op2val:0xbfff0000000000000000000000000000; + valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f17, f30, f27, dyn, 0, 0, x3, 46*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f15, rs2==f21, rd==f23,fs1 == 1 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 0 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f15; op2:f21; dest:f23; op1val:0x80000000000000000000000000000000; op2val:0x0; + valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f23, f15, f21, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f20, rs2==f16, rd==f12,fs1 == 1 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 1 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f20; op2:f16; dest:f12; op1val:0x80000000000000000000000000000000; op2val:0x80000000000000000000000000000000; + valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f12, f20, f16, dyn, 0, 0, x3, 50*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rs2==f9, rd==f22,fs1 == 1 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 0 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f6; op2:f9; dest:f22; op1val:0x80000000000000000000000000000000; op2val:0x1; + valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f22, f6, f9, dyn, 0, 0, x3, 52*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f8, rs2==f4, rd==f29,fs1 == 1 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 1 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f8; op2:f4; dest:f29; op1val:0x80000000000000000000000000000000; op2val:0x80000000000000000000000000000001; + valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f29, f8, f4, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f24, rs2==f8, rd==f9,fs1 == 1 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 0 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f24; op2:f8; dest:f9; op1val:0x80000000000000000000000000000000; op2val:0x2; + valaddr_reg:x3; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f9, f24, f8, dyn, 0, 0, x3, 56*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f13, rs2==f7, rd==f31,fs1 == 1 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 1 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f13; op2:f7; dest:f31; op1val:0x80000000000000000000000000000000; op2val:0x80000000000000000000000000000002; + valaddr_reg:x3; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f13, f7, dyn, 0, 0, x3, 58*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f17, rs2==f14, rd==f21,fs1 == 1 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 0 and fe2 == 0x0000 and fm2 == 0xffffffffffffffffffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f17; op2:f14; dest:f21; op1val:0x80000000000000000000000000000000; op2val:0xffffffffffffffffffffffffffff; + valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f21, f17, f14, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f18, rs2==f25, rd==f14,fs1 == 1 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 1 and fe2 == 0x0000 and fm2 == 0xffffffffffffffffffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f18; op2:f25; dest:f14; op1val:0x80000000000000000000000000000000; op2val:0x8000ffffffffffffffffffffffffffff; + valaddr_reg:x3; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f14, f18, f25, dyn, 0, 0, x3, 62*FLEN/8, x4, x1, x2) + +inst_32: +// fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000001 and fs2 == 0 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x0; + valaddr_reg:x3; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 64*FLEN/8, x4, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000001 and fs2 == 1 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x80000000000000000000000000000000; + valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000001 and fs2 == 0 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x1; + valaddr_reg:x3; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 68*FLEN/8, x4, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000001 and fs2 == 1 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x80000000000000000000000000000001; + valaddr_reg:x3; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 70*FLEN/8, x4, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000001 and fs2 == 0 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x2; + valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 72*FLEN/8, x4, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000001 and fs2 == 1 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x80000000000000000000000000000002; + valaddr_reg:x3; val_offset:74*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 74*FLEN/8, x4, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000001 and fs2 == 0 and fe2 == 0x0000 and fm2 == 0xffffffffffffffffffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0xffffffffffffffffffffffffffff; + valaddr_reg:x3; val_offset:76*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 76*FLEN/8, x4, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000001 and fs2 == 1 and fe2 == 0x0000 and fm2 == 0xffffffffffffffffffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x1; op2val:0x8000ffffffffffffffffffffffffffff; + valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 78*FLEN/8, x4, x1, x2) + +inst_40: +// fs1 == 1 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000001 and fs2 == 0 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x80000000000000000000000000000001; op2val:0x0; + valaddr_reg:x3; val_offset:80*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 80*FLEN/8, x4, x1, x2) + +inst_41: +// fs1 == 1 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000001 and fs2 == 1 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x80000000000000000000000000000001; op2val:0x80000000000000000000000000000000; + valaddr_reg:x3; val_offset:82*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 82*FLEN/8, x4, x1, x2) + +inst_42: +// fs1 == 1 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000001 and fs2 == 0 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x80000000000000000000000000000001; op2val:0x1; + valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 84*FLEN/8, x4, x1, x2) + +inst_43: +// fs1 == 1 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000001 and fs2 == 1 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x80000000000000000000000000000001; op2val:0x80000000000000000000000000000001; + valaddr_reg:x3; val_offset:86*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 86*FLEN/8, x4, x1, x2) + +inst_44: +// fs1 == 1 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000001 and fs2 == 0 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x80000000000000000000000000000001; op2val:0x2; + valaddr_reg:x3; val_offset:88*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 88*FLEN/8, x4, x1, x2) + +inst_45: +// fs1 == 1 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000001 and fs2 == 1 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x80000000000000000000000000000001; op2val:0x80000000000000000000000000000002; + valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2) + +inst_46: +// fs1 == 1 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000001 and fs2 == 0 and fe2 == 0x0000 and fm2 == 0xffffffffffffffffffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x80000000000000000000000000000001; op2val:0xffffffffffffffffffffffffffff; + valaddr_reg:x3; val_offset:92*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 92*FLEN/8, x4, x1, x2) + +inst_47: +// fs1 == 1 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000001 and fs2 == 1 and fe2 == 0x0000 and fm2 == 0xffffffffffffffffffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x80000000000000000000000000000001; op2val:0x8000ffffffffffffffffffffffffffff; + valaddr_reg:x3; val_offset:94*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 94*FLEN/8, x4, x1, x2) + +inst_48: +// fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000002 and fs2 == 0 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x0; + valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 96*FLEN/8, x4, x1, x2) + +inst_49: +// fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000002 and fs2 == 1 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x80000000000000000000000000000000; + valaddr_reg:x3; val_offset:98*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 98*FLEN/8, x4, x1, x2) + +inst_50: +// fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000002 and fs2 == 0 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x1; + valaddr_reg:x3; val_offset:100*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 100*FLEN/8, x4, x1, x2) + +inst_51: +// fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000002 and fs2 == 1 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x80000000000000000000000000000001; + valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 102*FLEN/8, x4, x1, x2) + +inst_52: +// fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000002 and fs2 == 0 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x2; + valaddr_reg:x3; val_offset:104*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 104*FLEN/8, x4, x1, x2) + +inst_53: +// fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000002 and fs2 == 1 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x80000000000000000000000000000002; + valaddr_reg:x3; val_offset:106*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 106*FLEN/8, x4, x1, x2) + +inst_54: +// fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000002 and fs2 == 0 and fe2 == 0x0000 and fm2 == 0xffffffffffffffffffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0xffffffffffffffffffffffffffff; + valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 108*FLEN/8, x4, x1, x2) + +inst_55: +// fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000002 and fs2 == 1 and fe2 == 0x0000 and fm2 == 0xffffffffffffffffffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x2; op2val:0x8000ffffffffffffffffffffffffffff; + valaddr_reg:x3; val_offset:110*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 110*FLEN/8, x4, x1, x2) + +inst_56: +// fs1 == 1 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000002 and fs2 == 0 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x80000000000000000000000000000002; op2val:0x0; + valaddr_reg:x3; val_offset:112*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 112*FLEN/8, x4, x1, x2) + +inst_57: +// fs1 == 1 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000002 and fs2 == 1 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x80000000000000000000000000000002; op2val:0x80000000000000000000000000000000; + valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 114*FLEN/8, x4, x1, x2) + +inst_58: +// fs1 == 1 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000002 and fs2 == 0 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x80000000000000000000000000000002; op2val:0x1; + valaddr_reg:x3; val_offset:116*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 116*FLEN/8, x4, x1, x2) + +inst_59: +// fs1 == 1 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000002 and fs2 == 1 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x80000000000000000000000000000002; op2val:0x80000000000000000000000000000001; + valaddr_reg:x3; val_offset:118*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 118*FLEN/8, x4, x1, x2) + +inst_60: +// fs1 == 1 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000002 and fs2 == 0 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x80000000000000000000000000000002; op2val:0x2; + valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 120*FLEN/8, x4, x1, x2) + +inst_61: +// fs1 == 1 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000002 and fs2 == 1 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x80000000000000000000000000000002; op2val:0x80000000000000000000000000000002; + valaddr_reg:x3; val_offset:122*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 122*FLEN/8, x4, x1, x2) + +inst_62: +// fs1 == 1 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000002 and fs2 == 0 and fe2 == 0x0000 and fm2 == 0xffffffffffffffffffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x80000000000000000000000000000002; op2val:0xffffffffffffffffffffffffffff; + valaddr_reg:x3; val_offset:124*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 124*FLEN/8, x4, x1, x2) + +inst_63: +// fs1 == 1 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000002 and fs2 == 1 and fe2 == 0x0000 and fm2 == 0xffffffffffffffffffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x80000000000000000000000000000002; op2val:0x8000ffffffffffffffffffffffffffff; + valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 126*FLEN/8, x4, x1, x2) + +inst_64: +// fs1 == 0 and fe1 == 0x0000 and fm1 == 0xffffffffffffffffffffffffffff and fs2 == 0 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0xffffffffffffffffffffffffffff; op2val:0x0; + valaddr_reg:x3; val_offset:128*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 128*FLEN/8, x4, x1, x2) + +inst_65: +// fs1 == 0 and fe1 == 0x0000 and fm1 == 0xffffffffffffffffffffffffffff and fs2 == 1 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0xffffffffffffffffffffffffffff; op2val:0x80000000000000000000000000000000; + valaddr_reg:x3; val_offset:130*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 130*FLEN/8, x4, x1, x2) + +inst_66: +// fs1 == 0 and fe1 == 0x0000 and fm1 == 0xffffffffffffffffffffffffffff and fs2 == 0 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0xffffffffffffffffffffffffffff; op2val:0x1; + valaddr_reg:x3; val_offset:132*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 132*FLEN/8, x4, x1, x2) + +inst_67: +// fs1 == 0 and fe1 == 0x0000 and fm1 == 0xffffffffffffffffffffffffffff and fs2 == 1 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0xffffffffffffffffffffffffffff; op2val:0x80000000000000000000000000000001; + valaddr_reg:x3; val_offset:134*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 134*FLEN/8, x4, x1, x2) + +inst_68: +// fs1 == 0 and fe1 == 0x0000 and fm1 == 0xffffffffffffffffffffffffffff and fs2 == 0 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0xffffffffffffffffffffffffffff; op2val:0x2; + valaddr_reg:x3; val_offset:136*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 136*FLEN/8, x4, x1, x2) + +inst_69: +// fs1 == 0 and fe1 == 0x0000 and fm1 == 0xffffffffffffffffffffffffffff and fs2 == 1 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0xffffffffffffffffffffffffffff; op2val:0x80000000000000000000000000000002; + valaddr_reg:x3; val_offset:138*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 138*FLEN/8, x4, x1, x2) + +inst_70: +// fs1 == 0 and fe1 == 0x0000 and fm1 == 0xffffffffffffffffffffffffffff and fs2 == 0 and fe2 == 0x0000 and fm2 == 0xffffffffffffffffffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0xffffffffffffffffffffffffffff; op2val:0xffffffffffffffffffffffffffff; + valaddr_reg:x3; val_offset:140*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 140*FLEN/8, x4, x1, x2) + +inst_71: +// fs1 == 0 and fe1 == 0x0000 and fm1 == 0xffffffffffffffffffffffffffff and fs2 == 1 and fe2 == 0x0000 and fm2 == 0xffffffffffffffffffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0xffffffffffffffffffffffffffff; op2val:0x8000ffffffffffffffffffffffffffff; + valaddr_reg:x3; val_offset:142*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 142*FLEN/8, x4, x1, x2) + +inst_72: +// fs1 == 1 and fe1 == 0x0000 and fm1 == 0xffffffffffffffffffffffffffff and fs2 == 0 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x8000ffffffffffffffffffffffffffff; op2val:0x0; + valaddr_reg:x3; val_offset:144*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 144*FLEN/8, x4, x1, x2) + +inst_73: +// fs1 == 1 and fe1 == 0x0000 and fm1 == 0xffffffffffffffffffffffffffff and fs2 == 1 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x8000ffffffffffffffffffffffffffff; op2val:0x80000000000000000000000000000000; + valaddr_reg:x3; val_offset:146*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 146*FLEN/8, x4, x1, x2) + +inst_74: +// fs1 == 1 and fe1 == 0x0000 and fm1 == 0xffffffffffffffffffffffffffff and fs2 == 0 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x8000ffffffffffffffffffffffffffff; op2val:0x1; + valaddr_reg:x3; val_offset:148*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 148*FLEN/8, x4, x1, x2) + +inst_75: +// fs1 == 1 and fe1 == 0x0000 and fm1 == 0xffffffffffffffffffffffffffff and fs2 == 1 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x8000ffffffffffffffffffffffffffff; op2val:0x80000000000000000000000000000001; + valaddr_reg:x3; val_offset:150*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 150*FLEN/8, x4, x1, x2) + +inst_76: +// fs1 == 1 and fe1 == 0x0000 and fm1 == 0xffffffffffffffffffffffffffff and fs2 == 0 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x8000ffffffffffffffffffffffffffff; op2val:0x2; + valaddr_reg:x3; val_offset:152*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 152*FLEN/8, x4, x1, x2) + +inst_77: +// fs1 == 1 and fe1 == 0x0000 and fm1 == 0xffffffffffffffffffffffffffff and fs2 == 1 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x8000ffffffffffffffffffffffffffff; op2val:0x80000000000000000000000000000002; + valaddr_reg:x3; val_offset:154*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 154*FLEN/8, x4, x1, x2) + +inst_78: +// fs1 == 1 and fe1 == 0x0000 and fm1 == 0xffffffffffffffffffffffffffff and fs2 == 0 and fe2 == 0x0000 and fm2 == 0xffffffffffffffffffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x8000ffffffffffffffffffffffffffff; op2val:0xffffffffffffffffffffffffffff; + valaddr_reg:x3; val_offset:156*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 156*FLEN/8, x4, x1, x2) + +inst_79: +// fs1 == 1 and fe1 == 0x0000 and fm1 == 0xffffffffffffffffffffffffffff and fs2 == 1 and fe2 == 0x0000 and fm2 == 0xffffffffffffffffffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x8000ffffffffffffffffffffffffffff; op2val:0x8000ffffffffffffffffffffffffffff; + valaddr_reg:x3; val_offset:158*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 158*FLEN/8, x4, x1, x2) + +inst_80: +// fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 1 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x80000000000000000000000000000000; + valaddr_reg:x3; val_offset:160*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 160*FLEN/8, x4, x1, x2) + +inst_81: +// fs1 == 0 and fe1 == 0x0000 and fm1 == 0x0000000000000000000000000000 and fs2 == 0 and fe2 == 0x0000 and fm2 == 0x0000000000000000000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fadd.q ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x2; + valaddr_reg:x3; val_offset:162*FLEN/8; rmval:dyn; fcsr: 0; + correctval:??; testreg:x2 +*/ +TEST_FPRR_OP(fadd.q, f31, f30, f29, dyn, 0, 0, x3, 162*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(1,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105729,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105730,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(5192296858534827628530496329220095,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(170146375757327766559315834212213325823,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(5192296858534827628530496329220096,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(170146375757327766559315834212213325824,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(5192296858534827628530496329220098,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(170146375757327766559315834212213325826,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(170135991163610696904058773219554885631,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(340282042402384805036647824275747635199,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(170135991163610696904058773219554885632,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(340277174624079928635746076935438991360,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(170138587312039964317873038467719495680,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(340279770772509196049560342183603601408,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(170138587312039964317873038467719495681,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(340279770772509196049560342183603601409,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(170135991163610696904058773219554885633,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(340277174624079928635746076935438991361,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(85065399433376081038215121361612832768,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(255206582893845312769902425077496938496,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105728,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105728,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105728,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105728,128,FLEN) +NAN_BOXED(1,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105728,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105729,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105728,128,FLEN) +NAN_BOXED(2,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105728,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105730,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105728,128,FLEN) +NAN_BOXED(5192296858534827628530496329220095,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105728,128,FLEN) +NAN_BOXED(170146375757327766559315834212213325823,128,FLEN) +NAN_BOXED(1,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(1,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105728,128,FLEN) +NAN_BOXED(1,128,FLEN) +NAN_BOXED(1,128,FLEN) +NAN_BOXED(1,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105729,128,FLEN) +NAN_BOXED(1,128,FLEN) +NAN_BOXED(2,128,FLEN) +NAN_BOXED(1,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105730,128,FLEN) +NAN_BOXED(1,128,FLEN) +NAN_BOXED(5192296858534827628530496329220095,128,FLEN) +NAN_BOXED(1,128,FLEN) +NAN_BOXED(170146375757327766559315834212213325823,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105729,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105729,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105728,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105729,128,FLEN) +NAN_BOXED(1,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105729,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105729,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105729,128,FLEN) +NAN_BOXED(2,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105729,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105730,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105729,128,FLEN) +NAN_BOXED(5192296858534827628530496329220095,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105729,128,FLEN) +NAN_BOXED(170146375757327766559315834212213325823,128,FLEN) +NAN_BOXED(2,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(2,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105728,128,FLEN) +NAN_BOXED(2,128,FLEN) +NAN_BOXED(1,128,FLEN) +NAN_BOXED(2,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105729,128,FLEN) +NAN_BOXED(2,128,FLEN) +NAN_BOXED(2,128,FLEN) +NAN_BOXED(2,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105730,128,FLEN) +NAN_BOXED(2,128,FLEN) +NAN_BOXED(5192296858534827628530496329220095,128,FLEN) +NAN_BOXED(2,128,FLEN) +NAN_BOXED(170146375757327766559315834212213325823,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105730,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105730,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105728,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105730,128,FLEN) +NAN_BOXED(1,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105730,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105729,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105730,128,FLEN) +NAN_BOXED(2,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105730,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105730,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105730,128,FLEN) +NAN_BOXED(5192296858534827628530496329220095,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105730,128,FLEN) +NAN_BOXED(170146375757327766559315834212213325823,128,FLEN) +NAN_BOXED(5192296858534827628530496329220095,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(5192296858534827628530496329220095,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105728,128,FLEN) +NAN_BOXED(5192296858534827628530496329220095,128,FLEN) +NAN_BOXED(1,128,FLEN) +NAN_BOXED(5192296858534827628530496329220095,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105729,128,FLEN) +NAN_BOXED(5192296858534827628530496329220095,128,FLEN) +NAN_BOXED(2,128,FLEN) +NAN_BOXED(5192296858534827628530496329220095,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105730,128,FLEN) +NAN_BOXED(5192296858534827628530496329220095,128,FLEN) +NAN_BOXED(5192296858534827628530496329220095,128,FLEN) +NAN_BOXED(5192296858534827628530496329220095,128,FLEN) +NAN_BOXED(170146375757327766559315834212213325823,128,FLEN) +NAN_BOXED(170146375757327766559315834212213325823,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(170146375757327766559315834212213325823,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105728,128,FLEN) +NAN_BOXED(170146375757327766559315834212213325823,128,FLEN) +NAN_BOXED(1,128,FLEN) +NAN_BOXED(170146375757327766559315834212213325823,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105729,128,FLEN) +NAN_BOXED(170146375757327766559315834212213325823,128,FLEN) +NAN_BOXED(2,128,FLEN) +NAN_BOXED(170146375757327766559315834212213325823,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105730,128,FLEN) +NAN_BOXED(170146375757327766559315834212213325823,128,FLEN) +NAN_BOXED(5192296858534827628530496329220095,128,FLEN) +NAN_BOXED(170146375757327766559315834212213325823,128,FLEN) +NAN_BOXED(170146375757327766559315834212213325823,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(170141183460469231731687303715884105728,128,FLEN) +NAN_BOXED(0,128,FLEN) +NAN_BOXED(2,128,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 164*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/tests/test_riscv_ctg.py b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/tests/test_riscv_ctg.py new file mode 100644 index 000000000..d457e7eb1 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-ctg/tests/test_riscv_ctg.py @@ -0,0 +1,21 @@ +# See Licence.incore for details. +from click.testing import CliRunner +from riscv_ctg.main import cli +from riscv_ctg.ctg import ctg +import pytest + +@pytest.fixture +def runner(): + return CliRunner() + +def test_version(runner): + '''Testing version option''' + result = runner.invoke(cli, ['--version']) + assert result.exit_code == 0 + +# -r -d temp1 -x 32 -cf sample_cgfs/rv32i.cgf -v debu +def test_rv32i(runner): + ''' Testing rv32 runs ''' + result = runner.invoke(cli, ['--randomize', '--out-dir', 'rv32i', '-cf', + '../sample_cgfs/rv32i.cgf', '-v', 'debug']) + assert result.exit_code == 0 or result.exit_code == 1 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/CHANGELOG.md b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/CHANGELOG.md new file mode 100644 index 000000000..094aae462 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/CHANGELOG.md @@ -0,0 +1,159 @@ +# CHANGELOG + +This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html). + +## [0.18.1] - 2024-03-07 +- Fix hex representation of most negative value in floatingPoint_tohex() + +## [0.18.0] - 2023-07-26 +- Add support to decode compressed instructions + +## [0.17.0] - 2022-10-25 +- Improve data propagation reports to capture multiple signature updates per coverpoint +- Add a CLI flag to explicitly log the redundant coverpoints while normalizing the CGF files + +## [0.16.1] - 2022-10-20 +- Fix length of commitval to 32 bits if flen is 32 for f registers in sail parser. + +## [0.16.0] - 2022-09-28 +- Refactored the instruction object class + +## [0.15.0] - 2022-08-25 +- Added support for instruction aliases + +## [0.14.0] - 2022-08-08 +- Add fields to instruction object +- Enable generic coverage evaluation mechanisms for floating point instructions +- Fix coverpoint generation to account for nan boxing of fp instructions. +- Add fields(frm, fcsr, nan_prefix) for fp instructions + +## [0.13.2] - 2022-05-23 +- Error reporting for missing coverlabel in cgf file + +## [0.13.1] - 2022-05-07 +- Fix mistune version for doc builds. + +## [0.13.0] - 2022-05-02 +- Covergroup format revised. +- Added support for Pseudoinstructions for coverage computation. + +## [0.12.0] - 2022-04-15 +- Parallelized coverage computation. +- Added feature to remove coverpoints when hit. +- Added CLI option to specify number of processes to be spawned. +- Added CLI option to turn on/off feature to remove hit coverpoints. + +## [0.11.0] - 2022-04-03 +- Added plugins to use new rvopcode format +- Added CLI option to setup rvopcode plugin + +## [0.10.2] - 2022-03-15 +- Added method to generate data patterns for bitmanip instructions + +## [0.10.1] - 2022-02-10 +- Added vxsat to supported csr_regs +- Added comments to coverpoint functions for P-ext +- Removed unused tuple type for bit_width parameters in P-ext coverpoint functions + +## [0.10.0] - 2022-01-27 +- Added support for instructions from B extension. +- Bug fix for bgeu instruction. + +## [0.9.0] - 2022-01-07 +- Added support for P extension cover point generation and instruction decoding. +- Allowed an instruction to generate results in multiple registers. + +## [0.8.0] - 2021-10-30 +- Added cross combination coverage support. + +## [0.7.3] - 2021-09-02 +- Updated logger to enable logging for API calls. + +## [0.7.2] - 2021-08-18 +- Added decoding support for K extension instructions based on latest spec + +## [0.7.1] - 2021-08-12 +- Bug fix for error while using byte_count with overlap = Y. + +## [0.7.0] - 2021-08-11 +- Adding support for floating point extension coverpoints +- Bug fixes for instruction decoder and improved pretty printing. +- fix for uninitialized total_categories variable in coverage. +- fixed CONTRIBUTING.rst file + +## [0.6.6] - 2021-08-03 +- Bug fix for error while decoding instruction name + +## [0.6.5] - 2021-07-14 +- Bug fix for error while generating Data Propagation Report. + +## [0.6.4] - 2021-07-08 +- Added support for CSR coverage and its architectural state +- Updated the merge function to support multiprocessing +- Added a parameter '-p' ( number of processes ) in merge command +- Documentation update for CSR coverpoints +- Return value of parsers changed from 5 independent values (hexcode, addr, reg commmit, csr commit, mnemonics) to instruction object updated with these values +- Argument of decode and all decoding functions (in internaldecoder) changed from hexcode and addr to instruction object + +## [0.6.3] - 2021-06-24 +- Documentation updates to reflect plugin usage. +- Minor bug fixes in coverage reporting. +- Improved CLI help messages. + +## [0.6.2] - 2021-06-15 +- Added parser plugins for sail and spike +- Added decoder plugin +- Added arguments in main.py for custom plugin paths and names. + +## [0.6.1] - 2021-06-11 +- Added initial support for F extension coverpoints based on IBM models. +- Added support for F extension architectural state +- Fixed author information and repo link in setup.py + +## [0.6.0] - 2021-05-27 +- added support in parsers for K-scalar crypto instructions +- added support for abstract functions: uniform random, byte-count, leading-ones, leading-zeros, + trailing-ones, trailing-zeros +- now maintain a separate list of instructions which require unsigned interpretation of rs1 and rs2. +- restructured coverage report handling to preserve comments throughout processing and merging. +- switched yaml to a round-trip parser for preserving comments + +## [0.5.2] - 2021-02-23 +- Moved ci to github actions +- fixed links in docs + +## [0.5.1] - 2020-12-14 +- Fixed operand signedness for m ext ops. + +## [0.5.0] - 2020-11-18 +- added support to take multiple cgf files as input. The order matters +- added support for abstract function of special dataset + +## [0.4.0] - 2020-11-10 +- added special data set for r-type instructions +- fixed data propagation report generation and templates +- using classes to manage architectural state and statistics +- updated docs + +## [0.3.1] - 2020-10-26 + - use logger instead of log in coverage.py + + +## [0.3.0] - 2020-10-26 +- Adding support for Data propagation report generation +- Added 'sig-label' as the new cli option under coverage to capture DP reports +- Added support in sail parsers to extract mnemonics also from the trace file +- added pytablewriter as part of the requirements + +## [0.2.0] - 2020-10-23 +- Added documentation for CGF and usage +- Added normalization routine as cli +- Added abstract functions +- using click for cli +- adding parsers for sail and spike +- added support for filtering based on labels +- added merge-reports cli command + + +## [0.1.0] - 2020-06-25 +- initial draft diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/CONTRIBUTING.rst b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/CONTRIBUTING.rst new file mode 100644 index 000000000..97af244ec --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/CONTRIBUTING.rst @@ -0,0 +1,97 @@ +.. See LICENSE.incore for details + +.. highlight:: shell + +============ +Contributing +============ + +Your inputs are welcome and greatly appreciated! We want to make contributing to this project as easy and transparent as possible, whether it's: + +- Reporting a bug +- Discussing the current state of the code +- Submitting a fix +- Proposing new features +- Becoming a maintainer + +We develop with Github +---------------------- + +We use github to host code, to track issues and feature requests, as well as accept pull requests. + +All changes happen through Pull Requests +---------------------------------------- + +Pull requests are the best way to propose changes to the codebase. We actively welcome your pull requests: + +1. Fork the repo and create your branch from `master`. +2. If you have updated the docs, ensure that they render correctly in the respective format. +3. Make sure to create an entry in the CHANGELOG.md. Please refer to the section on versioning below + to choose an appropriate version number. +4. Ensure the existing framework is not broken and still passes the basic checks. +5. Please include a comment with the SPDX license identifier in all source files, for example: + ``` + // SPDX-License-Identifier: BSD-3-Clause + ``` +6. Bump the version of the tool to patch/minor/major as per the entry made in the CHANGELOG.md +7. Issue that pull request! + +Checks for a PR +--------------- + +Make sure your PR meets all the following requirements: + +1. You have made an entry in the CHANGELOG.md. +2. You have bumped the version of the tool using bumpversion utility described below. +3. The commit messages are verbose. +4. You PR doesn't break existing framework. + +Versioning +---------- + +When issuing pull requests, an entry in the CHANGELOG.md is mandatory. The arch-test-repo adheres to +the [`Semantic Versioning`](https://semver.org/spec/v2.0.0.html) scheme. Following guidelines must +be followed while assigning a new version number : + +- Patch-updates: all doc updates (like typos, more clarification,etc) will be patches. Beautification enhancements will also be treated as patch updates. Certain bug fixes to existing code may be treated as patches as well. +- Minor-updates: Updates to code with new extensions, features, run time optimizations can be + treated as minor updates. +- Major-updates: Changes to the framework flow (backward compatible or incompatible) will be treated + as major updates. + +Note: You can have either a patch or minor or major update. +Note: In case of a conflict, the maintainers will decide the final version to be assigned. + +All contributions will be under the permissive open-source License +------------------------------------------------------------------ + +In short, when you submit code changes, your submissions are understood to be under a permissive open source license like BSD-3, Apache-2.0 and CC, etc that covers the project. Feel free to contact the maintainers if that's a concern. + +Report bugs using Github's `issues `_ +------------------------------------------------------------------------------------ + +We use GitHub issues to track public bugs. Report a bug by `opening a new issue `_ it's that easy! + +Write bug reports with detail, background, and sample code +---------------------------------------------------------- + +**Great Bug Reports** tend to have: + +- A quick summary and/or background +- Steps to reproduce + - Be specific! + - Give sample code if you can. +- What you expected would happen +- What actually happens +- Notes (possibly including why you think this might be happening, or stuff you tried that didn't work) + + +Version Bumping made simple +--------------------------- + +Each PR will require the tools version to be bumped. This can be achieved using the following +commands:: + + $ bumpversion --allow-dirty --no-tag --config-file setup.cfg patch #options: major / minor / patch + + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/LICENSE.incore b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/LICENSE.incore new file mode 100644 index 000000000..c1c837a28 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/LICENSE.incore @@ -0,0 +1,30 @@ +BSD 3-Clause License + +Copyright (c) 2020, InCore Semiconductors Pvt. Ltd. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +* Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/MANIFEST.in b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/MANIFEST.in new file mode 100644 index 000000000..b888a5a6d --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/MANIFEST.in @@ -0,0 +1,7 @@ +include LICENSE.incore +include README.rst +include riscv_isac/requirements.txt +recursive-include riscv_isac/data/* + +recursive-exclude * __pycache__ +recursive-exclude * *.py[co] diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/README.rst b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/README.rst new file mode 100644 index 000000000..819738270 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/README.rst @@ -0,0 +1,5 @@ +##################################### +**RISC-V ISA Coverage** : RISC-V ISAC +##################################### + +Latest documentation of riscv_isac can be found on readthedocs `here `_ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/Makefile new file mode 100644 index 000000000..9dcaa1136 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/Makefile @@ -0,0 +1,26 @@ +# See LICENSE.incore for details + +# Minimal makefile for Sphinx documentation +# + +# You can set these variables from the command line. +SPHINXOPTS = +SPHINXBUILD = sphinx-build +SPHINXPROJ = riscv_isac +SOURCEDIR = source +BUILDDIR = build + +# Put it first so that "make" without argument is like "make help". +help: + @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) + +.PHONY: help Makefile + +# Catch-all target: route all unknown targets to Sphinx using the new +# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). +%: Makefile + @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) + +clean: + @$(SPHINXBUILD) -M clean "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/README.md b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/README.md new file mode 100644 index 000000000..50c16d0d6 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/README.md @@ -0,0 +1,15 @@ +# Build the docs + +## For PDF +``` +pip install -r requirements.txt +make latexpdf +evince build/latex/*.pdf +``` + +## HTML +``` +pip install -r requirements.txt +make html +firefox build/html/index.html +``` diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/requirements.txt b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/requirements.txt new file mode 100644 index 000000000..2a1d69448 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/requirements.txt @@ -0,0 +1,40 @@ +alabaster==0.7.12 +Babel==2.7.0 +Cerberus==1.3.1 +certifi==2019.6.16 +chardet==3.0.4 +doc8==0.8.0 +docutils==0.14 +gitdb2==2.0.5 +idna==2.8 +imagesize==1.1.0 +Jinja2==2.10.1 +MarkupSafe==1.1.1 +oyaml==0.9 +packaging==19.0 +pbr==5.3.1 +Pygments==2.4.2 +pyparsing==2.4.0 +python-dateutil==2.8.0 +pytz==2019.1 +PyYAML==5.1.1 +requests==2.22.0 +restructuredtext-lint==1.3.0 +ruamel.yaml==0.15.97 +six==1.12.0 +smmap2==2.0.5 +snowballstemmer==1.2.1 +Sphinx==3.0.4 +sphinx-rtd-theme==0.4.3 +sphinxcontrib-autoyaml==0.5.0 +sphinxcontrib-mermaid +sphinxcontrib-websupport==1.1.2 +sphinxcontrib-bibtex==1.0.0 +stevedore==1.30.1 +urllib3==1.25.3 +twine==1.13.0 +sphinx_tabs +m2r2==0.2.7 +mistune==0.8.4 +colorlog==4.1.0 +pyelftools==0.26 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/Cross_coverage.rst b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/Cross_coverage.rst new file mode 100644 index 000000000..ae4f9be97 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/Cross_coverage.rst @@ -0,0 +1,134 @@ +############### +Cross Coverage +############### + +ISAC supports extraction of data dependencies across different instructions in the log file. It can check for possible data hazards (RAW, WAW, WAR) between instructions. +The hazards are checked for instructions belonging to the same window. The window size of the instruction is a parameter (by default taken as 32). +The coverpoints are updated whenever the conditions mentioned in them are matched for a given instruction. + +Syntax for the coverpoints +=========================== + +Each coverpoint is a string constituting of three sections - opcode list, assign list and condition list separated by ``::`` symbol. In each of these lists symbol +``?`` signifies a don't care condition. The delimiter for elements of the list is ``:`` symbol. The template of a generic coverpoint is shown below: + +``[list of opcodes]::[list of assignment statements]::[list of condition statements]`` + +Opcode List: +-------------- +This is the list of instruction names against which we check the name of the current instruction in the queue. Here ``?`` signifies that we needn't check the name +for that instruction as that won't affect the conditions of that coverpoint. Opcode list is a list of tuples and don't care conditions. + +An example of a opcode list : ``[(add,sub):?:?:(mul,mulh):?]`` + +Assign List: +------------- +This list contains the assigning statements for registers. These statements are evaluated using ``exec`` command. The register numbers are assigned to variables. +Under don't care conditions, no assignment is done. + +An example of assign list: ``[a=rd:?:?]`` + +Here a is any variable which is assigned the destination register number of the first instruction. + +Condition List: +---------------- +This contains the evaluation statements to check the data dependencies. In case of don't care conditions, we don't check for data dependecies for that +particular instruction. It conatins conditions for both source as well as destination registers. We can check for both consuming and non-consuming instructions. + +Example of condition list: ``[?:rs1==a or rs2==a]`` + +Here let a be the destination register of the first instruction (assigned by assign list). Then this checks whether any of the source registers are equal to the +destination register of the previous instruction. It basically checks for read after write hazard. + +Cross Coverage Queue +===================== + +This is list of instruction objects in which the data is pushed in the sequence they are parsed. Whenever the queue size becomes equal to the window size, we check for all potential data hazards between the front element of the queue and the rest of the instructions according to the coverpoint and then pop the first element. + +Cross Coverage Class +===================== + +def __init__(self,label,coverpoint): +--------------------------------------- + +The cross coverage class ``cross`` is initialized with the ``label`` and ``coverpoint``. ``result`` stores the coverage for that coverpoint. + +* Arguments: ``self`` instance of the class, ``label`` the instruction name, ``coverpoint`` the coverpoint to be evaluated. + + +.. code-block:: python + + def __init__(self,label,coverpoint): + self.label = label + self.coverpoint = coverpoint + self.result = 0 + +An instance of a class is created for each ``(label,coverpoint)`` pair present in the CGF and all the relevant information about the coverpoint - opcode list, assign list and condition list are extracted. + +def process(self, queue, window_size, addr_pairs): +---------------------------------------------------- + +The ``process`` function of ``cross`` evaluates each coverpoint and updates ``result`` if there is a hit. The data in the coverpoint is evaluated against their corresponding instruction in the queue i.e. if the index of an instruction is i, then it will check and assign statments at index i of the three lists of the coverpoints. If the instruction address doesn't belong to any list of addresses in ``addr_pairs`` we treat is as a don't care. These coverpoints are checked in three steps. + + - First, the name of the first instruction is checked against the corresponding entry in the opcode list. + - If the instruction is present, we assign its register value to a variable using ``exec`` command on the assign list elements. + - Then we check for the conditions in the condition list using ``eval`` command. + The above steps are repeated until the entire coverpoint is evaluated and it's a hit or the conditions are not satisfied and the loop breaks. + +* Arguments: ``self`` instance of the class, ``queue`` the list containing the instructions to be evaluated, ``window_size`` maximum number of instructions to be checked for any coverpoint, ``addr_pairs`` the addresses to be considered while evaluating an instruction +* Returns: None + +def get_metric(self): +---------------------- + +It returns the coverage for that instance. + +* Arguments: ``self`` instance of the class +* Returns: ``result`` the final coverage for that coverpoint + +Updating the CGF +======================== + + - An object dictionary ``obj_dict`` contains an instance of ``cross`` for each ``(label,coverpoint)`` pair. + - As the instrcutions are parsed, they are appended to the ``cross_cover_queue`` which is the list of instructions to be checked. + - When the size of queue becomes equal to the window size, for each entry in ``obj_dict``, the coverpoints are evaluated in ``process`` + - The first element of the queue is popped and the process is repeated. + - After all the instrcutions are parsed, all the instructions in the queue are again evaluated in the above manner till there is nothing to evaluate. + - The final metric for each ``(label,coverpoint)`` instance is updated for each node in the CGF. + +**Examples of coverpoints** + The window size is fixed and equal to 5. + + 1. RAW for an add instruction followed immediately by a subtract instruction. + + .. code-block:: python + + [(add,sub) : (add,sub) ] :: [a=rd : ? ] :: [? : rs1==a or rs2==a ] + + 2. RAW on x10 register for an add instruction followed by a subtract instruction with one non-consuming/non-updating instruction in between. + No update happens to the rd register in between. + + .. code-block:: python + + [(add,sub) : ? : (add,sub) ] :: [a=rd : ? : ? ] :: [rd==x10 : rd!=a and rs1!=a and rs2!=a : rs1==a or rs2==a ] + + 3. WAW for an add instruction followed by a subtract instruction with 3 non-consuming instructions in between. + + .. code-block:: python + + [add : ? : ? : ? : sub] :: [a=rd : ? : ? : ? : ?] :: [? : ? : ? : ? : rd==a] + + 4. WAW for add followed by subtract with 3 consuming instructions in between. + + .. code-block:: python + + [(add,sub) : ? : ? : ? : (add,sub)] :: [a=rd : ? : ? : ? : ?] :: [? : rs1==a or rs2==a : rs1==a or rs2==a : rs1==a or rs2==a : rd==a] + + 5. WAR for an add instruction followed immediately by a subtract instruction. + + .. code-block:: python + + [(add,sub) : (add,sub) ] :: [a=rs1; b=rs2 : ? ] :: [? : rd==a or rd==b ] + + + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/_static/custom.css b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/_static/custom.css new file mode 100644 index 000000000..3f7e16db1 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/_static/custom.css @@ -0,0 +1,309 @@ +/* -- Extra CSS styles for Zephyr content (RTD theme) ----------------------- */ + +/* make the page width fill the window */ +.wy-nav-content { + max-width: none; +} + +/* pygments tweak for white-on-black console */ +/* hold off on this change for now + +.highlight-console .highlight { + background-color: black; +} +.highlight-console .highlight .go, .highlight-console .highlight .gp { + color: white; +} +.highlight-console .highlight .hll { + background-color: white; +} +.highlight-console .highlight .hll .go, .highlight-console .highlight .hll .gp { + color: black; + font-weight: bold; +} +*/ + +/* tweak doc version selection */ +.rst-versions { + position: static !important; +} + + +.rst-versions .rst-current-version { + padding: 5px; + background-color: #2980B9; + color: #80FF80; +} + +.rst-versions .rst-other-versions { + padding: 5px; +} + +div.rst-other-versions dl { + margin-bottom: 0; +} + +/* tweak spacing after a toctree, fixing issue from sphinx-tabs */ +.toctree-wrapper ul, ul.simple ol.simple { + margin-bottom: 24px !important; +} + +/* code block highlight color in rtd changed to lime green, no no no */ + +.rst-content tt.literal, .rst-content code.literal, .highlight { + background: #f0f0f0; +} +.rst-content tt.literal, .rst-content code.literal { + color: #000000; +} + +/* code literal links should be blue, and purple after visiting */ +a.internal code.literal { + color: #2980B9; +} +a.internal:visited code.literal { + color: #9B59B9; +} + +/* Make the version number more visible */ +.wy-side-nav-search>div.version { + color: rgba(255,255,255,1); +} + +/* squish the space between a paragraph before a list */ +div > p + ul, div > p + ol { + margin-top: -20px; +} + +/* squish space before an hlist in a list */ +li table.hlist { + margin-top: -10px; + margin-bottom: 5px; +} + +/* add some space before the figure caption */ +p.caption { +# border-top: 1px solid; + margin-top: 1em; +} + +/* decrease line leading a bit, 24px is too wide */ + +p { + line-height: 22px; +} + +/* add a colon after the figure/table number (before the caption) */ +span.caption-number::after { + content: ": "; +} + +p.extrafooter { + text-align: right; + margin-top: -36px; +} + +table.align-center { + display: table !important; +} + +/* put the table caption at the bottom, as done for figures */ +table { + caption-side: bottom; +} + +.code-block-caption { + color: #000; + font: italic 85%/1 arial,sans-serif; + padding: 1em 0; + text-align: center; +} + +/* make .. hlist:: tables fill the page */ +table.hlist { + width: 95% !important; + table-layout: fixed; +} + +/* override rtd theme white-space no-wrap in table heading and content */ +th,td { + white-space: normal !important; +} + +/* dbk tweak for doxygen-generated API headings (for RTD theme) */ +.rst-content dl.group>dt, .rst-content dl.group>dd>p { + display:none !important; +} +.rst-content dl.group { + margin: 0 0 12px 0px; +} +.rst-content dl.group>dd { + margin-left: 0 !important; +} +.rst-content p.breathe-sectiondef-title { + text-decoration: underline; /* dbk for API sub-headings */ + font-size: 1.25rem; + font-weight: bold; + margin-bottom: 12px; +} +.rst-content div.breathe-sectiondef { + padding-left: 0 !important; +} + +/* doxygenXX item color tweaks, light blue background with dark blue top border */ +.rst-content dl:not(.docutils) dl dt, dl:not(.docutils,.rst-other-versions) dt { + background: #e7f2fa !important; + border-top: none !important; + border-left: none !important; */ +} + + +/* tweak display of option tables to make first column wider */ +col.option { + width: 25%; +} + +/* tweak format for (:kbd:`F10`) */ +kbd +{ + -moz-border-radius:3px; + -moz-box-shadow:0 1px 0 rgba(0,0,0,0.2),0 0 0 2px #fff inset; + -webkit-border-radius:3px; + -webkit-box-shadow:0 1px 0 rgba(0,0,0,0.2),0 0 0 2px #fff inset; + background-color:#f7f7f7; + border:1px solid #ccc; + border-radius:3px; + box-shadow:0 1px 0 rgba(0,0,0,0.2),0 0 0 2px #fff inset; + color:#333; + display:inline-block; + font-family:Arial,Helvetica,sans-serif; + font-size:11px; + line-height:1.4; + margin:0 .1em; + padding:.1em .6em; + text-shadow:0 1px 0 #fff; +} + +/* home page grid display */ + +.grid { + list-style-type: none !important; + display: -webkit-box; + display: -ms-flexbox; + display: flex; + -ms-flex-wrap: wrap; + flex-wrap: wrap; + -webkit-box-pack: center; + -ms-flex-pack: center; + justify-content: center; + margin: 1rem auto; + max-width: calc((250px + 2rem) * 4); +} + +.grid-item { + list-style-type: none !important; + -webkit-box-flex: 0; + -ms-flex: 0 0 auto; + flex: 0 0 auto; + width: 200px; + text-align: center; + margin: 1rem; +} + +.grid-item a { + display: block; + width: 200px; + height: 200px; + padding: 20px; + display: -webkit-box; + display: -ms-flexbox; + display: flex; + -webkit-box-orient: vertical; + -webkit-box-direction: normal; + -ms-flex-direction: column; + flex-direction: column; + -webkit-box-pack: center; + -ms-flex-pack: center; + justify-content: center; + -webkit-box-align: center; + -ms-flex-align: center; + align-items: center; + border: 1px solid #c6cbce; + background-color: #1ab4e7; + color: white; +} + +.grid-item h2 { + font-size: 1.1rem; +} + +.grid-item img { + margin-bottom: 1.1rem; + max-width: 75%; +} + + +.grid-item a:hover { + background-color: #1892BA; + color: white; +} + + +.grid-item p { + margin-top: 0.5rem; + color: #333e48; +} + +.grid-icon { + line-height: 1.8; + font-size: 4rem; + color: white; +} + +/* add a class for multi-column support + * in docs to replace use of .hlist with + * a .. rst-class:: rst-columns + */ + +.rst-columns { + column-width: 18em; +} + +/* numbered "h2" steps */ + +body { + counter-reset: step-count; +} + +div.numbered-step h2::before { + counter-increment: step-count; + content: counter(step-count); + background: #cccccc; + border-radius: 0.8em; + -moz-border-radius: 0.8em; + -webkit-border-radius: 0.8em; + color: #ffffff; + display: inline-block; + font-weight: bold; + line-height: 1.6em; + margin-right: 5px; + text-align: center; + width: 1.6em; +} + +/* tweak bottom margin of a code block in a list */ + +.tab div[class^='highlight']:last-child { + margin-bottom: 1em; +} + +/* force table content font-size in responsive tables to be 100% + * fixing larger font size for paragraphs in the kconfig tables */ + +.wy-table-responsive td p { + font-size:100%; +} +.section #basic-2-flip-flop-synchronizer{ + text-align:justify; +} + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/_static/incore_logo.png b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/_static/incore_logo.png new file mode 100644 index 000000000..dfbf6c43d Binary files /dev/null and b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/_static/incore_logo.png differ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/_static/l1cache.png b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/_static/l1cache.png new file mode 100644 index 000000000..08d980f20 Binary files /dev/null and b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/_static/l1cache.png differ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/_static/onlyC.png b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/_static/onlyC.png new file mode 100644 index 000000000..2c80aa79f Binary files /dev/null and b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/_static/onlyC.png differ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/_static/riscv-isac.png b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/_static/riscv-isac.png new file mode 100644 index 000000000..153504df7 Binary files /dev/null and b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/_static/riscv-isac.png differ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/_static/theme_overrides.css b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/_static/theme_overrides.css new file mode 100644 index 000000000..03c2bc22f --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/_static/theme_overrides.css @@ -0,0 +1,18 @@ +/* override table width restrictions */ + +@media screen and (min-width: 767px) { + + .wy-table-responsive table td { + /* !important prevents the common CSS stylesheets from overriding + this as on RTD they are loaded after this stylesheet */ + white-space: normal !important; + } + + .wy-table-responsive { + overflow: visible !important; + } +} + +.section #basic-2-flip-flop-synchronizer{ + text-align:justify; +} diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/_templates/breadcrumbs.html b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/_templates/breadcrumbs.html new file mode 100644 index 000000000..6c6493a1c --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/_templates/breadcrumbs.html @@ -0,0 +1,14 @@ +{% extends "!breadcrumbs.html" %} +{% block breadcrumbs %} + + {# parameterize default name "Docs" in breadcrumb via docs_title in conf.py #} + {% if not docs_title %} + {% set docs_title = "Docs" %} + {% endif %} + +
  • {{ docs_title }} »
    • + {% for doc in parents %} +
  • {{ doc.title }} »
    • + {% endfor %} +
  • {{ title }}
    • +{% endblock %} diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/_templates/layout.html b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/_templates/layout.html new file mode 100644 index 000000000..24c127eb4 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/_templates/layout.html @@ -0,0 +1,14 @@ +{% extends "!layout.html" %} +{% block document %} + {% if is_release %} +
    + The latest development version + of this page may be more current than this released {{ version }} version. +
    + {% endif %} + {{ super() }} +{% endblock %} +{% block menu %} + {% include "versions.html" %} + {{ super() }} +{% endblock %} diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/_templates/versions.html b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/_templates/versions.html new file mode 100644 index 000000000..e66fba251 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/_templates/versions.html @@ -0,0 +1,25 @@ +{# Add rst-badge after rst-versions for small badge style. #} +
    + + RISC-V ISA Coverage + v: {{ current_version }} + + +
    +
    +
    {{ _('Release Versions') }}
    + {% for slug, url in versions %} +
    {{ slug }}
    + {% endfor %} +
    +
    +
    {{ _('Quick Links') }}
    +
    + Project Home +
    +
    + Releases +
    +
    +
    +
    diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/add_instr.rst b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/add_instr.rst new file mode 100644 index 000000000..f4781a73e --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/add_instr.rst @@ -0,0 +1,40 @@ +.. _add_instr: + +################################### +Adding Support for new Instructions +################################### + +This section details the steps for adding support for new instructions in the native python plugins +of RISCV-ISAC. + +.. note:: An alternative is to add support for the new instructions using the ``riscv/riscv-opcodes`` repository. Refer :here:`rvopcodes` for further information. + +Update the Parser-Module +======================== + +The first step is to update the parser-module to be able to deduce the relevant fields of the new +instruction and create the required :meth:`~riscv_isac.parsers.instructionObject`. + +As part of this phase, the contributor will first have to add a function(s) which will decode the +instruction hexadecimal encoding and extract the parameters of the :meth:`~riscv_isac.parsers.instructionObject`. +Make sure to follow the same code structure as used by other functions in module. + +Currently the top level function that get's called by the coverage module is the +:meth:`~riscv_isac.parsers.parseInstruction` function. This function based on the `instruction length +encoding` scheme defined by the RISC-V ISA spec identifies the length of the instruction. If the +instruction is compressed then the :meth:`~riscv_isac.parsers.parseCompressedInstruction` function +is called, else the :meth:`~riscv_isac.parsers.parseInstruction` function is called. + +If the new instruction(s) being added belong to the non-compressed opcodes, then the particular +entry in :meth:`~riscv_isac.parsers.OPCODES` needs to be updated to point to the new function(s) +defined earlier. If there are instructions falling into the compressed op-code space then the +functions :meth:`~riscv_isac.parsers.quad0`, :meth:`~riscv_isac.parsers.quad1` or :meth:`~riscv_isac.parsers.quad2` +will need to be updated accordingly. + +Update the Architectural +======================== + +The coverage module maintains its own architectural state : integer register file, program counter, +floating point register file, etc. If the new instruction(s) requires an additional architectural +state, then that needs to be added in :meth:`~riscv_isac.coverage.archStats` and the usage needs to +be updated in :meth:`~riscv_isac.coverage.compute_per_line`. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/cgf.rst b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/cgf.rst new file mode 100644 index 000000000..e49c53849 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/docs/source/cgf.rst @@ -0,0 +1,438 @@ +.. See LICENSE.incore for details + +.. _cgf: + +================= +CGF Specification +================= + +A cgf file is a file which is written in the *yaml* format. The higher level node type in a cgf file is a dictionary. + +Covergroup +========== +A covergroup is a dictionary based on the following template. These dictionaries constitute the nodes in a cgf file. Each cover group contains the following type of coverpoints: + +* Mnemonics (Used in conjunction with a `base_op` and a condtion `p_op_cond` node to describe a pseudo-instruction) +* Register +* Register Operand Combinations +* Register/Immediate Value Combinations +* Control and Status Registers Value Combinations +* Cross coverage nodes + +Template +-------- + +The template for defining a non pseudo-op covergroup is as follows: + +.. code-block:: yaml + +