From 6b7ff50a849919e776c51b7ec18c9c43908de6a3 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Mon, 13 Nov 2023 16:44:02 -0600
Subject: [PATCH] Reduced Arty A7 clock speed to 20Mhz to support Zicclsm.

---
 fpga/generator/xlnx_mmcm.tcl      |  2 +-
 linux/devicetree/wally-artya7.dts | 10 +++++-----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/fpga/generator/xlnx_mmcm.tcl b/fpga/generator/xlnx_mmcm.tcl
index a8a2fe568..2f003e7a5 100644
--- a/fpga/generator/xlnx_mmcm.tcl
+++ b/fpga/generator/xlnx_mmcm.tcl
@@ -15,7 +15,7 @@ set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \
                         CONFIG.CLKOUT4_USED {false} \
                         CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \
                         CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \
-                        CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {23} \
+                        CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20} \
                         CONFIG.CLKIN1_JITTER_PS {10.0} \
                        ] [get_ips $ipName]
 
diff --git a/linux/devicetree/wally-artya7.dts b/linux/devicetree/wally-artya7.dts
index 4206c7804..6dab66c7b 100644
--- a/linux/devicetree/wally-artya7.dts
+++ b/linux/devicetree/wally-artya7.dts
@@ -21,8 +21,8 @@
 	cpus {
 		#address-cells = <0x01>;
 		#size-cells = <0x00>;
-		clock-frequency = <0x15EF3C0>;
-		timebase-frequency = <0x15EF3C0>;
+		clock-frequency = <0x1312D00>;
+		timebase-frequency = <0x1312D00>;
 
 		cpu@0 {
 			phandle = <0x01>;
@@ -51,7 +51,7 @@
 		uart@10000000 {
 			interrupts = <0x0a>;
 			interrupt-parent = <0x03>;
-			clock-frequency = <0x15EF3C0>;
+			clock-frequency = <0x1312D00>;
 			reg = <0x00 0x10000000 0x00 0x100>;
 			compatible = "ns16550a";
 		};
@@ -74,8 +74,8 @@
 			fifo-depth = <256>;
 			bus-width = <4>;
 			interrupt-parent = <0x03>;
-			clock = <0x15EF3C0>;
-			max-frequency = <0x15EF3C0>;
+			clock = <0x1312D00>;
+			max-frequency = <0x1312D00>;
 			cap-sd-highspeed;
 			cap-mmc-highspeed;
 			no-sdio;