diff --git a/testbench/tests.vh b/testbench/tests.vh
index 45605b5dc..7d60cb0c1 100644
--- a/testbench/tests.vh
+++ b/testbench/tests.vh
@@ -259,9 +259,7 @@ string arch64priv[] = '{
   "rv64i_m/privilege/src/misalign-blt-01.S",
   "rv64i_m/privilege/src/misalign-bltu-01.S",
   "rv64i_m/privilege/src/misalign-bne-01.S",
-  "rv64i_m/privilege/src/misalign-jal-01.S"
-  // commented out for now because rv64gc supports Zicclsm, but Sail does not yet.  Restore when Sail supports Zicclsm.
-  /* -----\/----- EXCLUDED -----\/-----
+  "rv64i_m/privilege/src/misalign-jal-01.S",
   "rv64i_m/privilege/src/misalign-ld-01.S",
   "rv64i_m/privilege/src/misalign-lh-01.S",
   "rv64i_m/privilege/src/misalign-lhu-01.S",
@@ -270,7 +268,6 @@ string arch64priv[] = '{
   "rv64i_m/privilege/src/misalign-sd-01.S",
   "rv64i_m/privilege/src/misalign-sh-01.S",
   "rv64i_m/privilege/src/misalign-sw-01.S"
-  -----/\----- EXCLUDED -----/\----- */
 };
 
 string arch64zifencei[] = '{
diff --git a/tests/riscof/sail_cSim/riscof_sail_cSim.py b/tests/riscof/sail_cSim/riscof_sail_cSim.py
index 720bc91f0..e4150cb2f 100644
--- a/tests/riscof/sail_cSim/riscof_sail_cSim.py
+++ b/tests/riscof/sail_cSim/riscof_sail_cSim.py
@@ -114,7 +114,7 @@ class sail_cSim(pluginTemplate):
                 reference_output = re.sub("/src/","/references/", re.sub(".S",".reference_output", test))
                 execute += f'cut -c-{8:g} {reference_output} > {sig_file}' #use cut to remove comments when copying
             else:
-                execute += self.sail_exe[self.xlen] + f' --trace=step --test-signature={sig_file} {elf} > {test_name}.log 2>&1;'
+                execute += self.sail_exe[self.xlen] + f' --config {self.pluginpath}/{"rv64gc.json" if self.xlen == 64 else "rv32gc.json"} --trace=step --test-signature={sig_file} {elf} > {test_name}.log 2>&1;'
 
                 # Coverage
                 # Generate trace from sail log
diff --git a/tests/riscof/sail_cSim/rv32gc.json b/tests/riscof/sail_cSim/rv32gc.json
new file mode 100644
index 000000000..b457b4f70
--- /dev/null
+++ b/tests/riscof/sail_cSim/rv32gc.json
@@ -0,0 +1,221 @@
+{
+  "base": {
+    "writable_misa": false,
+    "writable_fiom": true,
+    "writable_hpm_counters": {
+      "len": 32,
+      "value": "0xFFFF_FFFF"
+    },
+    "mtval_has_illegal_instruction_bits": true
+  },
+  "memory": {
+    "pmp": {
+      "grain": 0,
+      "count": 16
+    },
+    "misaligned": {
+      "supported": false,
+      "byte_by_byte": false,
+      "order_decreasing": false,
+      "allowed_within_exp": 0
+    },
+    "translation": {
+      "dirty_update": false
+    }
+  },
+  "platform": {
+    "vendorid": 0,
+    "archid": 0,
+    "impid": 0,
+    "hartid": 0,
+    "reset_vector": 4096,
+    "cache_block_size_exp": 6,
+    "ram": {
+      "base": 2147483648,
+      "size": 2147483648
+    },
+    "rom": {
+      "base": 4096,
+      "size": 4096
+    },
+    "clint": {
+      "base": 33554432,
+      "size": 786432
+    },
+    "instructions_per_tick": 2,
+    "wfi_is_nop": true
+  },
+  "extensions": {
+    "M": {
+      "supported": true
+    },
+    "A": {
+      "supported": true
+    },
+    "FD": {
+      "supported": true
+    },
+    "V": {
+      "supported": true,
+      "vlen_exp": 9,
+      "elen_exp": 6,
+      "vl_use_ceil": false
+    },
+    "B": {
+      "supported": true
+    },
+    "S": {
+      "supported": true
+    },
+    "U": {
+      "supported": true
+    },
+    "Zicbom": {
+      "supported": true
+    },
+    "Zicboz": {
+      "supported": true
+    },
+    "Zicond": {
+      "supported": true
+    },
+    "Zicntr": {
+      "supported": true
+    },
+    "Zifencei": {
+      "supported": true
+    },
+    "Zihpm": {
+      "supported": true
+    },
+    "Zimop": {
+      "supported": true
+    },
+    "Zmmul": {
+      "supported": false
+    },
+    "Zaamo": {
+      "supported": false
+    },
+    "Zabha": {
+      "supported": true
+    },
+    "Zalrsc": {
+      "supported": false
+    },
+    "Zfa": {
+      "supported": true
+    },
+    "Zfh": {
+      "supported": true
+    },
+    "Zfhmin": {
+      "supported": false
+    },
+    "Zfinx": {
+      "supported": false
+    },
+    "Zca": {
+      "supported": true
+    },
+    "Zcf": {
+      "supported": true
+    },
+    "Zcd": {
+      "supported": true
+    },
+    "Zcb": {
+      "supported": true
+    },
+    "Zcmop": {
+      "supported": true
+    },
+    "Zba": {
+      "supported": false
+    },
+    "Zbb": {
+      "supported": false
+    },
+    "Zbs": {
+      "supported": false
+    },
+    "Zbc": {
+      "supported": true
+    },
+    "Zbkb": {
+      "supported": true
+    },
+    "Zbkc": {
+      "supported": true
+    },
+    "Zbkx": {
+      "supported": true
+    },
+    "Zknd": {
+      "supported": true
+    },
+    "Zkne": {
+      "supported": true
+    },
+    "Zknh": {
+      "supported": true
+    },
+    "Zkr": {
+      "supported": true
+    },
+    "Zksed": {
+      "supported": true
+    },
+    "Zksh": {
+      "supported": true
+    },
+    "Zhinx": {
+      "supported": false
+    },
+    "Zvbb": {
+      "supported": true
+    },
+    "Zvkb": {
+      "supported": false
+    },
+    "Zvbc": {
+      "supported": true
+    },
+    "Zvknha": {
+      "supported": true
+    },
+    "Zvknhb": {
+      "supported": true
+    },
+    "Zvksh": {
+      "supported": true
+    },
+    "Sscofpmf": {
+      "supported": true
+    },
+    "Smcntrpmf": {
+      "supported": true
+    },
+    "Sstc": {
+      "supported": true
+    },
+    "Svinval": {
+      "supported": true
+    },
+    "Svbare": {
+      "supported": true
+    },
+    "Sv32": {
+      "supported": true
+    },
+    "Sv39": {
+      "supported": true
+    },
+    "Sv48": {
+      "supported": true
+    },
+    "Sv57": {
+      "supported": true
+    }
+  }
+}
diff --git a/tests/riscof/sail_cSim/rv64gc.json b/tests/riscof/sail_cSim/rv64gc.json
new file mode 100644
index 000000000..dc176b97e
--- /dev/null
+++ b/tests/riscof/sail_cSim/rv64gc.json
@@ -0,0 +1,221 @@
+{
+  "base": {
+    "writable_misa": false,
+    "writable_fiom": true,
+    "writable_hpm_counters": {
+      "len": 32,
+      "value": "0xFFFF_FFFF"
+    },
+    "mtval_has_illegal_instruction_bits": true
+  },
+  "memory": {
+    "pmp": {
+      "grain": 0,
+      "count": 16
+    },
+    "misaligned": {
+      "supported": true,
+      "byte_by_byte": false,
+      "order_decreasing": false,
+      "allowed_within_exp": 0
+    },
+    "translation": {
+      "dirty_update": false
+    }
+  },
+  "platform": {
+    "vendorid": 0,
+    "archid": 0,
+    "impid": 0,
+    "hartid": 0,
+    "reset_vector": 4096,
+    "cache_block_size_exp": 6,
+    "ram": {
+      "base": 2147483648,
+      "size": 2147483648
+    },
+    "rom": {
+      "base": 4096,
+      "size": 4096
+    },
+    "clint": {
+      "base": 33554432,
+      "size": 786432
+    },
+    "instructions_per_tick": 2,
+    "wfi_is_nop": true
+  },
+  "extensions": {
+    "M": {
+      "supported": true
+    },
+    "A": {
+      "supported": true
+    },
+    "FD": {
+      "supported": true
+    },
+    "V": {
+      "supported": true,
+      "vlen_exp": 9,
+      "elen_exp": 6,
+      "vl_use_ceil": false
+    },
+    "B": {
+      "supported": true
+    },
+    "S": {
+      "supported": true
+    },
+    "U": {
+      "supported": true
+    },
+    "Zicbom": {
+      "supported": true
+    },
+    "Zicboz": {
+      "supported": true
+    },
+    "Zicond": {
+      "supported": true
+    },
+    "Zicntr": {
+      "supported": true
+    },
+    "Zifencei": {
+      "supported": true
+    },
+    "Zihpm": {
+      "supported": true
+    },
+    "Zimop": {
+      "supported": true
+    },
+    "Zmmul": {
+      "supported": false
+    },
+    "Zaamo": {
+      "supported": false
+    },
+    "Zabha": {
+      "supported": true
+    },
+    "Zalrsc": {
+      "supported": false
+    },
+    "Zfa": {
+      "supported": true
+    },
+    "Zfh": {
+      "supported": true
+    },
+    "Zfhmin": {
+      "supported": false
+    },
+    "Zfinx": {
+      "supported": false
+    },
+    "Zca": {
+      "supported": true
+    },
+    "Zcf": {
+      "supported": true
+    },
+    "Zcd": {
+      "supported": true
+    },
+    "Zcb": {
+      "supported": true
+    },
+    "Zcmop": {
+      "supported": true
+    },
+    "Zba": {
+      "supported": false
+    },
+    "Zbb": {
+      "supported": false
+    },
+    "Zbs": {
+      "supported": false
+    },
+    "Zbc": {
+      "supported": true
+    },
+    "Zbkb": {
+      "supported": true
+    },
+    "Zbkc": {
+      "supported": true
+    },
+    "Zbkx": {
+      "supported": true
+    },
+    "Zknd": {
+      "supported": true
+    },
+    "Zkne": {
+      "supported": true
+    },
+    "Zknh": {
+      "supported": true
+    },
+    "Zkr": {
+      "supported": true
+    },
+    "Zksed": {
+      "supported": true
+    },
+    "Zksh": {
+      "supported": true
+    },
+    "Zhinx": {
+      "supported": false
+    },
+    "Zvbb": {
+      "supported": true
+    },
+    "Zvkb": {
+      "supported": false
+    },
+    "Zvbc": {
+      "supported": true
+    },
+    "Zvknha": {
+      "supported": true
+    },
+    "Zvknhb": {
+      "supported": true
+    },
+    "Zvksh": {
+      "supported": true
+    },
+    "Sscofpmf": {
+      "supported": true
+    },
+    "Smcntrpmf": {
+      "supported": true
+    },
+    "Sstc": {
+      "supported": true
+    },
+    "Svinval": {
+      "supported": true
+    },
+    "Svbare": {
+      "supported": true
+    },
+    "Sv32": {
+      "supported": true
+    },
+    "Sv39": {
+      "supported": true
+    },
+    "Sv48": {
+      "supported": true
+    },
+    "Sv57": {
+      "supported": true
+    }
+  }
+}
diff --git a/tests/riscof/spike/riscof_spike.py b/tests/riscof/spike/riscof_spike.py
index 43d1339a1..703fddc69 100644
--- a/tests/riscof/spike/riscof_spike.py
+++ b/tests/riscof/spike/riscof_spike.py
@@ -196,7 +196,7 @@ class spike(pluginTemplate):
                 reference_output = re.sub("/src/","/references/", re.sub(".S",".reference_output", test))
                 simcmd = f'cut -c-{8:g} {reference_output} > {sig_file}' #use cut to remove comments when copying
             else:
-                simcmd = self.dut_exe + f' --isa={self.isa} +signature={sig_file} +signature-granularity=4 {elf}'
+                simcmd = self.dut_exe + f' {"--misaligned" if self.xlen == 64 else ""} --isa={self.isa} +signature={sig_file} +signature-granularity=4 {elf}'
           else:
             simcmd = 'echo "NO RUN"'