From 7244ca1e7b66c168bea591b7d49da8afa73e6eeb Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 24 Oct 2022 13:48:47 -0500 Subject: [PATCH] Bit width error. --- pipelined/src/uncore/uartPC16550D.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/uncore/uartPC16550D.sv b/pipelined/src/uncore/uartPC16550D.sv index e312eeb4d..ddc5e3826 100644 --- a/pipelined/src/uncore/uartPC16550D.sv +++ b/pipelined/src/uncore/uartPC16550D.sv @@ -99,7 +99,7 @@ module uartPC16550D( // receive data (* mark_debug = "true" *) logic [10:0] RXBR; - (* mark_debug = "true" *) logic [6:0] rxtimeoutcnt; + (* mark_debug = "true" *) logic [9:0] rxtimeoutcnt; logic rxcentered; logic rxparity, rxparitybit, rxstopbit; (* mark_debug = "true" *) logic rxparityerr, rxoverrunerr, rxframingerr, rxbreak, rxfifohaserr;