From 7411d50a78e1a5961c0013ed5e65cb5d453364b9 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Mon, 5 Dec 2022 11:37:14 -0800 Subject: [PATCH] added all 32 bit tests to 64 bit periph tests except gpio --- .../WALLY-clint-01.reference_output | 18 + .../references/WALLY-plic-01.reference_output | 498 +++++++++ .../WALLY-plic-s-01.reference_output | 79 ++ .../references/WALLY-uart-01.reference_output | 150 +++ .../rv64i_m/privilege/src/WALLY-TEST-LIB-64.h | 133 ++- .../rv64i_m/privilege/src/WALLY-clint-01.S | 95 ++ .../rv64i_m/privilege/src/WALLY-plic-01.S | 954 ++++++++++++++++++ .../rv64i_m/privilege/src/WALLY-plic-s-01.S | 230 +++++ .../rv64i_m/privilege/src/WALLY-uart-01.S | 248 +++++ 9 files changed, 2399 insertions(+), 6 deletions(-) create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-clint-01.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-plic-01.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-plic-s-01.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-uart-01.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-clint-01.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-uart-01.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-clint-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-clint-01.reference_output new file mode 100644 index 000000000..723617745 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-clint-01.reference_output @@ -0,0 +1,18 @@ +00000000 # msip zero on reset +00000000 +00000000 # mip is zero +00000000 +00000008 # mip msip bit is set +00000000 +00000000 # mip msip bit is reset +00000000 +00000000 # mip mtip bit is reset +00000000 +FFFFFFFF # mtimecmp is same as written value +FFFFFFFF +A5A5A5A5 # mtimecmph is same as written value +FFFFFFFF +00000000 # mip mtip is zero +00000000 +00000080 # mip mtip is set +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-plic-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-plic-01.reference_output new file mode 100644 index 000000000..c6c6fa7f9 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-plic-01.reference_output @@ -0,0 +1,498 @@ +00000000 # read empty MIP (1.0.0) +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000000 # Claim gives no interrupt due to zero priority +00000000 +00000008 # interrupt still pending due to no claim +00000000 +00000000 # check no interrupts pending +00000000 +00000800 # MEIP set due to PLIC priority (1.0.1) +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # read empty MIP (1.0.2) +00000000 +00000000 # check GPIO interrupt pending on intPending0 +00000000 +00000000 # claim gives no interrupt due to no intPending +00000000 +00000000 # no interrupts pending after clear +00000000 +00000000 # still no interrupts after clear +00000000 +00000000 # read empty MIP (1.1.0) +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # Claim gives 3 for ID of GPIO +00000000 +00000000 # interrupt still pending due to no claim +00000000 +00000000 # check no interrupts pending +00000000 +00000800 # MEIP set due to PLIC priority (1.1.1) +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # read empty MIP (1.2.0) +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # Claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000800 # MEIP set due to PLIC priority (1.2.1) +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # read empty MIP (1.3.0) +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # Claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000800 # MEIP set due to PLIC priority (1.3.1) +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # read empty MIP (1.4.0) +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # Claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000800 # MEIP set due to PLIC priority (1.4.1) +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # read empty MIP (1.5.0) +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # Claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000800 # MEIP set due to PLIC priority (1.5.1) +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # read empty MIP (1.6.0) +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # Claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000800 # MEIP set due to PLIC priority (1.6.1) +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # read empty MIP (1.7.0) +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # Claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000800 # MEIP set (2.0) +00000000 +00000408 # gpio and uart pending +00000000 +00000003 # claim gpio +00000000 +00000400 # gpio no longer pending +00000000 +00000000 # no interrupts pending +00000000 +00000800 # MEIP set (2.1) +00000000 +00000408 # gpio and uart pending +00000000 +00000003 # claim gpio +00000000 +00000400 # gpio no longer pending +00000000 +00000000 # no interrupts pending +00000000 +00000800 # MEIP set (2.2) +00000000 +00000408 # gpio and uart pending +00000000 +0000000A # claim uart +00000000 +00000008 # uart no longer pending +00000000 +00000000 # no interrupts pending +00000000 +00000800 # MEIP set (2.3) +00000000 +00000408 # gpio and uart pending +00000000 +0000000A # claim uart +00000000 +00000008 # uart no longer pending +00000000 +00000000 # no interrupts pending +00000000 +00000000 # MEIP empty (2.4) +00000000 +00000408 # gpio and uart pending +00000000 +0000000A # claim none +00000000 +00000008 # gpio and uart still pending +00000000 +00000000 # no interrupts pending +00000000 +00000A00 # MEIP and SEIP set (3.0) +00000000 +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000400 # check GPIO interrupt pending cleared after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000200 # SEIP set (3.1) +00000000 +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000400 # check GPIO interrupt pending cleared after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000200 # SEIP set (3.2) +00000000 +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 +0000000A # claim UART +00000000 +00000008 # GPIO interrupt pending after UART claimcomp +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # read empty MIP (3.3) +00000000 +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 +0000000A # claim UART +00000000 +00000008 # check UART interrupt pending cleared after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000A00 # MEIP and SEIP set (4.0) +00000000 +00000400 # UART interrupt pending +00000000 +0000000A # claim UART +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # check no interrupts pending +00000000 +00000200 # SEIP set (4.1) +00000000 +00000400 # UART interrupt pending +00000000 +00000000 # nothing in claim register +00000000 +00000400 # UART interrupt pending +00000000 +00000000 # check no interrupts pending +00000000 +00000A00 # MEIP and SEIP set (4.2) +00000000 +00000400 # UART interrupt pending +00000000 +0000000A # claim UART +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # check no interrupts pending +00000000 +00000800 # MEIP set (4.3) +00000000 +00000400 # UART interrupt pending +00000000 +0000000A # claim UART +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # check no interrupts pending +00000000 +00000800 # MEIP set (4.4) +00000000 +00000400 # UART interrupt pending +00000000 +0000000A # claim UART +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # check no interrupts pending +00000000 +00000200 # SEIP set (4.5) +00000000 +00000400 # UART interrupt pending +00000000 +00000000 # nothing in claim register +00000000 +00000400 # UART interrupt pending +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # All disabled (4.6) +00000000 +00000400 # UART interrupt pending +00000000 +00000000 # nothing in claim register +00000000 +00000400 # UART interrupt pending +00000000 +00000000 # check no interrupts pending +00000000 +00000200 # SEIP set (5.0) +00000000 +00000008 # GPIO interrupt pending +00000000 +00000000 # nothing in claim register +00000000 +00000008 # GPIO interrupt pending +00000000 +00000000 # check no interrupts pending +00000000 +00000A00 # MEIP and SEIP set (5.1) +00000000 +00000008 # GPIO interrupt pending +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # check no interrupts pending +00000000 +00000800 # MEIP set (5.2) +00000000 +00000008 # GPIO interrupt pending +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # check no interrupts pending +00000000 +00000A00 # MEIP and SEIP set (5.3) +00000000 +00000008 # GPIO interrupt pending +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # check no interrupts pending +00000000 +00000800 # MEIP set (5.4) +00000000 +00000008 # GPIO interrupt pending +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # check no interrupts pending +00000000 +00000200 # SEIP set (5.5) +00000000 +00000008 # GPIO interrupt pending +00000000 +00000000 # nothing in claim register +00000000 +00000008 # GPIO interrupt pending +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # read empty MIP (5.6) +00000000 +00000008 # GPIO interrupt pending +00000000 +00000000 # nothing in claim register +00000000 +00000008 # GPIO interrupt pending +00000000 +00000000 # check no interrupts pending +00000000 +0000000b # written due to goto_s_mode +00000000 +00000200 # read sip (7.0) +00000000 +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000400 # check GPIO interrupt pending cleared after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000200 # read sip (7.1) +00000000 +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000400 # check GPIO interrupt pending cleared after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000200 # read sip (7.2) +00000000 +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 +0000000A # claim UART +00000000 +00000008 # GPIO interrupt pending after UART claimcomp +00000000 +00000000 # check no interrupts pending +00000000 +00000200 # read sip (7.3) +00000000 +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000400 # check GPIO interrupt pending cleared after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # read sip (7.4) +00000000 +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 +00000000 # nothing in claim register +00000000 +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 +00000000 # check no interrupts pending +00000000 +00000200 # read sip (7.5) +00000000 +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000400 # check GPIO interrupt pending cleared after claim +00000000 +00000000 # check no interrupts pending +00000000 +00000000 # read sip (7.6) +00000000 +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 +00000000 # nothing in claim register +00000000 +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 +00000000 # check no interrupts pending +00000000 +00000009 # output from ecall in supervisor mode +00000000 +00000800 # MEIP set (8.0) +00000000 +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 +0000000A # claim UART +00000000 +00000008 # GPIO interrupt pending after UART claimcomp +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000000 # read empty MIP # no interrupts, meip is low +00000000 +00000000 # check no interrupts pending +00000000 +00000800 # MEIP set +00000000 +00000008 # GPIO interrupt pending after complete +00000000 +00000003 # claim gives 3 for ID of GPIO +00000000 +00000000 # read empty MIP # meip is zeroed +00000000 +00000000 # check no interrupts pending +00000000 +00000800 # MEIP set +00000000 +00000400 # check GPIO interrupt pending cleared after claim +00000000 +00000800 # MEIP set +00000000 +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 +0000000A # claim UART +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-plic-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-plic-s-01.reference_output new file mode 100644 index 000000000..da4f81fab --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-plic-s-01.reference_output @@ -0,0 +1,79 @@ +0000000b # ecall for change to supervisor mode +00000000 + +00000200 # 1.1: read SIP with supervisor interrupt +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # Claim GPIO in supervisor context +00000000 +00000000 # No interrupts pending +00000000 +00000000 # No interrupts pending +00000000 + +00000200 # 1.2: read SIP with supervisor interrupt +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # Claim GPIO in supervisor context +00000000 +00000000 # No interrupts pending +00000000 +00000000 # No interrupts pending +00000000 + +00000000 # 1.3: read SIP with supervisor interrupt +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000000 # No claim +00000000 +00000008 # Interrupt unclaimed and still pending +00000000 +00000000 # No interrupts pending +00000000 + +00000000 # 1.4: read SIP with supervisor interrupt +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000000 # No claim +00000000 +00000008 # Interrupt unclaimed and still pending +00000000 +00000000 # No interrupts pending +00000000 + +00000000 # 1.5: read SIP with supervisor interrupt +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # Claim GPIO in supervisor context even though it is masked by priority +00000000 +00000000 # No interrupts pending +00000000 +00000000 # No interrupts pending +00000000 + +00000200 # 1.6: read SIP with supervisor interrupt +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # Claim GPIO in supervisor context +00000000 +00000000 # No interrupts pending +00000000 +00000000 # No interrupts pending +00000000 + +00000000 # 1.7: read SIP with supervisor interrupt +00000000 +00000008 # check GPIO interrupt pending on intPending0 +00000000 +00000003 # Glaim GPIO in supervisor conxtex even though it is masked by priority +00000000 +00000000 # No interrupts pending +00000000 +00000000 # No interrupts pending +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-uart-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-uart-01.reference_output new file mode 100644 index 000000000..ebac64f92 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-uart-01.reference_output @@ -0,0 +1,150 @@ +00000000 # Reset tests +00000000 +00000001 # 00000000 *** commented because LCR should reset to zero but resets to 3 due to the FPGA +00000000 +00000000 +00000000 +00000060 +00000000 +00000000 +00000000 +00000060 # read-write test +00000000 +00000020 # transmitter register empty but shift register not +00000000 +00000101 # transmitter is not empty when done transmitting 5 bits +00000000 +00000000 +00000000 +00000060 +00000000 +00000101 # Multi-bit transmission: 5 bits +00000000 +00000015 +00000000 +00000101 # Transmit 6 bits +00000000 +0000002A +00000000 +00000101 # Transmit 7 bits +00000000 +0000007F +00000000 +00000101 # Transmit 8 bits +00000000 +ffffff80 +ffffffff +00000101 # Odd parity +00000000 +00000079 +00000000 +00000101 # Even parity +00000000 +0000006A +00000000 +00000101 # Extra stop bit +00000000 +0000005B +00000000 +00000002 # Transmission interrupt tests +00000000 +00000401 # Interrupt generated by finished transmission +00000000 +00000004 +00000000 +00000006 # IIR return LSR intr and LSR has an overflow error +00000000 +00000063 +00000000 +00000004 +00000000 +00000001 +00000000 +00000001 # MODEM interrupt tests +00000000 +00000000 +00000000 +00000011 +00000000 +00000001 +00000000 +00000000 # DSR Test +00000000 +00000032 +00000000 +00000001 +00000000 +00000000 # RI Test +00000000 +00000034 +00000000 +00000001 +00000000 +00000000 # DCD Test +00000000 +ffffffB8 +ffffffff +00000001 +00000000 +ffffffC2 # FIFO interrupt +ffffffff +0000C101 +00000000 +00000000 +00000000 +ffffffC1 +ffffffff +0000C401 +00000000 +ffffffA5 +ffffffff +ffffffC1 +ffffffff +00000001 +00000000 +00000002 +00000000 +00000061 +00000000 +00000003 +00000000 +00000060 +00000000 +0000C101 +00000000 +ffffffC1 +ffffffff +00000060 +00000000 +ffffffC1 # FIFO filling/overrun test +ffffffff +0000C401 # Threshold = 1 +00000000 +ffffffC1 # Threshold = 4 +ffffffff +0000C101 +00000000 +0000C401 +00000000 +ffffffC1 # Threshold = 8 +ffffffff +0000C101 +00000000 +0000C401 +00000000 +ffffffC1 # Threshold = 14 +ffffffff +0000C101 +00000000 +0000C401 +00000000 +0000C101 +00000000 +00000061 # FIFO has data, no overrun +00000000 +00000006 # wait for interrupt +00000000 +ffffffA3 # FIFO overrun error +ffffffff +0000000b # ecall from test termination +00000000 \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index 60872449e..cdc11c7b8 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -1008,20 +1008,141 @@ read08_test: addi a6, a6, 8 j test_loop // go to next test case + +read04_test: + // address to read in t3, expected 8 bit value in t4 (unused, but there for your perusal). + li t2, 0xBAD // bad value that will be overwritten on good reads. + lb t2, 0(t3) + andi t2, t2, 0xF // mask lower 4 bits + sd t2, 0(t1) + addi t1, t1, 8 + addi a6, a6, 8 + j test_loop // go to next test case + readmip_test: // read the MIP into the signature csrr t2, mip - sw t2, 0(t1) - addi t1, t1, 4 - addi a6, a6, 4 + sd t2, 0(t1) + addi t1, t1, 8 + addi a6, a6, 8 j test_loop // go to next test case readsip_test: // read the MIP into the signature csrr t2, sip - sw t2, 0(t1) - addi t1, t1, 4 - addi a6, a6, 4 + sd t2, 0(t1) + addi t1, t1, 8 + addi a6, a6, 8 j test_loop // go to next test case +claim_m_plic_interrupts: // clears one non-pending PLIC interrupt + li t2, 0x0C00000C // GPIO priority + li t3, 7 + lw t4, 0(t2) + sw t3, 0(t2) + sw t4, -4(sp) + addi sp, sp, -4 + li t2, 0x0C000028 // UART priority + li t3, 7 + lw t4, 0(t2) + sw t3, 0(t2) + sw t4, -4(sp) + addi sp, sp, -4 + li t2, 0x0C002000 + li t3, 0x0C200004 + li t4, 0xFFF + lw t6, 0(t2) // save current enable status + sw t4, 0(t2) // enable all relevant interrupts on PLIC + lw t5, 0(t3) // make PLIC claim + sw t5, 0(t3) // complete claim made + sw t6, 0(t2) // restore saved enable status + li t2, 0x0C00000C // GPIO priority + li t3, 0x0C000028 // UART priority + lw t4, 4(sp) // load stored GPIO and UART priority + lw t5, 0(sp) + addi sp, sp, 8 // restore stack pointer + sw t4, 0(t2) + sw t5, 0(t3) + j test_loop + +claim_s_plic_interrupts: // clears one non-pending PLIC interrupt + li t2, 0x0C00000C // GPIO priority + li t3, 7 + lw t4, 0(t2) + sw t3, 0(t2) + sw t4, -4(sp) + addi sp, sp, -4 + li t2, 0x0C000028 // UART priority + li t3, 7 + lw t4, 0(t2) + sw t3, 0(t2) + sw t4, -4(sp) + addi sp, sp, -4 + li t2, 0x0C002080 + li t3, 0x0C201004 + li t4, 0xFFF + lw t6, 0(t2) // save current enable status + sw t4, 0(t2) // enable all relevant interrupts on PLIC + lw t5, 0(t3) // make PLIC claim + sw t5, 0(t3) // complete claim made + sw t6, 0(t2) // restore saved enable status + li t2, 0x0C00000C // GPIO priority + li t3, 0x0C000028 // UART priority + lw t4, 4(sp) // load stored GPIO and UART priority + lw t5, 0(sp) + addi sp, sp, 8 // restore stack pointer + sw t4, 0(t2) + sw t5, 0(t3) + j test_loop + +uart_lsr_intr_wait: // waits for interrupts to be ready + li t2, 0x10000002 // IIR + li t4, 0x6 +uart_lsr_intr_loop: + lb t3, 0(t2) + andi t3, t3, 0x7 + bne t3, t4, uart_lsr_intr_loop +uart_save_iir_status: + sd t3, 0(t1) + addi t1, t1, 8 + addi a6, a6, 8 + j test_loop + +uart_data_wait: + li t2, 0x10000005 // LSR + li t3, 0x10000002 // IIR + li a4, 0x61 +uart_read_LSR_IIR: + lbu t4, 0(t3) // save IIR before reading LSR might clear it + // check if IIR is the rxfifotimeout interrupt. if it is, then read the fifo then go back and repeat this. + li t5, 0xCC // Value in IIR for Fifo Enabled, with timeout interrupt pending + beq t4, t5, uart_rxfifo_timout + lb t5, 0(t2) // read LSR + andi t6, t5, 0x61 // wait until all transmissions are done and data is ready + bne a4, t6, uart_read_LSR_IIR + j uart_data_ready +uart_rxfifo_timout: + li t4, 0x10000000 // read from the fifo to clear the rx timeout error + lb t5, 0(t4) + sb t5, 0(t4) // write back to the fifo to make sure we have the same data so expected future overrun errors still occur. + //read the fifo until empty + j uart_read_LSR_IIR + + +uart_data_ready: + li t2, 0 + sd t2, 0(t1) // clear entry deadbeef from memory + lbu t4, 0(t3) // re read IIR + andi t5, t5, 0x9F // mask THRE and TEMT from signature + sb t4, 1(t1) // IIR + sb t5, 0(t1) // LSR + addi t1, t1, 8 + addi a6, a6, 8 + j test_loop + +uart_clearmodemintr: + li t2, 0x10000006 + lb t2, 0(t2) + j test_loop + goto_s_mode: // return to address in t3, li a0, 3 // Trap handler behavior (go to supervisor mode) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-clint-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-clint-01.S new file mode 100644 index 000000000..838e4654d --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-clint-01.S @@ -0,0 +1,95 @@ +/////////////////////////////////////////// +// +// WALLY-gpio +// +// Author: David_Harris@hmc.edu and Nicholas Lucio +// +// Created 2022-06-16 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-64.h" +RVTEST_ISA("RV64I") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",clint) + +INIT_TESTS + +TRAP_HANDLER m + +j run_test_loop // begin test loop/table tests instead of executing inline code. + +INIT_TEST_TABLE + +END_TESTS + +TEST_STACK_AND_DATA + +.align 3 +test_cases: +# --------------------------------------------------------------------------------------------- +# Test Contents +# +# Here is where the actual tests are held, or rather, what the actual tests do. +# each entry consists of 3 values that will be read in as follows: +# +# '.8byte [x28 Value], [x29 Value], [x30 value]' +# or +# '.8byte [address], [value], [test type]' +# +# The encoding for x30 test type values can be found in the test handler in the framework file +# +# --------------------------------------------------------------------------------------------- + +# =========== Define CLINT registers =========== + +.equ CLINT, 0x02000000 +.equ msip, (CLINT+0x00) +.equ mtimecmp, (CLINT+0x4000) # doesn't necessarily reset to zero +.equ mtimecmph,(CLINT+0x4004) +.equ mtime, (CLINT+0xBFF8) # resets to zero but cannot be easily tested +.equ mtimeh, (CLINT+0xBFFC) + +# =========== Verify verifiable registers reset to zero =========== + +.8byte msip, 0x00000000, read32_test # msip reset to zero + +# =========== msip tests =========== + +.8byte msip, 0xFFFFFFFE, write32_test # write to invalid bits of msip +.8byte 0x0, 0x00000000, readmip_test # msip bit should be zero +.8byte msip, 0x00000001, write32_test # set msip to one +.8byte 0x0, 0x00000008, readmip_test # msip bit is set +.8byte msip, 0x00000000, write32_test # set msip to zero +.8byte 0x0, 0x00000000, readmip_test # msip bit is released + +# =========== mtime write tests =========== + +.8byte mtime, 0x00000000, write32_test # test we can write to mtime +.8byte mtimeh, 0x00000000, write32_test # test we can write to mtimeh +.8byte 0x0,0x00000000, readmip_test # mtip bit should be zero + +# =========== mtimecmp tests =========== + +.8byte mtimecmp, 0xFFFFFFFF, write32_test # verify mtimecmp is writable +.8byte mtimecmph, 0xA5A5A5A5, write32_test # verify mtimecmph is writable +.8byte mtimecmp, 0xFFFFFFFF, read32_test # read back value written to mtimecmp +.8byte mtimecmph, 0xA5A5A5A5, read32_test # read back value written to mtimecmph +.8byte mtime, 0xFFFFFFFF, write32_test # write to mtime +.8byte 0x0, 0x00000000, readmip_test # mtip should still be zero +.8byte mtimeh, 0xA5A5A5A6, write32_test # cause mtip to go high by making mtime > mtimecmp +.8byte 0x0, 0x00000080, readmip_test # mtip should be set + +.8byte 0x0, 0x0, terminate_test # terminate tests diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S new file mode 100644 index 000000000..43ceabfcf --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S @@ -0,0 +1,954 @@ +/////////////////////////////////////////// +// +// WALLY-plic +// +// Author: Nicholas Lucio +// +// Created 2022-06-16 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-64.h" + +RVTEST_ISA("RV64I") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic) + +INIT_TESTS + +TRAP_HANDLER m + +j run_test_loop // begin test loop/table tests instead of executing inline code. + +INIT_TEST_TABLE + +END_TESTS + +TEST_STACK_AND_DATA + +.align 2 +test_cases: +# --------------------------------------------------------------------------------------------- +# Test Contents +# +# Here is where the actual tests are held, or rather, what the actual tests do. +# each entry consists of 3 values that will be read in as follows: +# +# '.8byte [x28 Value], [x29 Value], [x30 value]' +# or +# '.8byte [address], [value], [test type]' +# +# The encoding for x30 test type values can be found in the test handler in the framework file +# +# --------------------------------------------------------------------------------------------- + +# =========== Define PLIC registers =========== + +.equ PLIC, 0x0C000000 +.equ PLIC_INTPRI_GPIO, (PLIC+0x00000C) # GPIO is interrupt 3 +.equ PLIC_INTPRI_UART, (PLIC+0x000028) # UART is interrupt 10 +.equ PLIC_INTPENDING0, (PLIC+0x001000) # intPending0 register +.equ PLIC_INTEN00, (PLIC+0x002000) # interrupt enables for context 0 (machine mode) sources 31:1 +.equ PLIC_INTEN10, (PLIC+0x002080) # interrupt enables for context 1 (supervisor mode) sources 31:1 +.equ PLIC_THRESH0, (PLIC+0x200000) # Priority threshold for context 0 (machine mode) +.equ PLIC_CLAIM0, (PLIC+0x200004) # Claim/Complete register for context 0 +.equ PLIC_THRESH1, (PLIC+0x201000) # Priority threshold for context 1 (supervisor mode) +.equ PLIC_CLAIM1, (PLIC+0x201004) # Claim/Complete register for context 1 + +# =========== Define GPIO registers =========== + +.equ GPIO, 0x10060000 +.equ input_val, (GPIO+0x00) +.equ input_en, (GPIO+0x04) +.equ output_en, (GPIO+0x08) +.equ output_val, (GPIO+0x0C) +.equ rise_ie, (GPIO+0x18) +.equ rise_ip, (GPIO+0x1C) +.equ fall_ie, (GPIO+0x20) +.equ fall_ip, (GPIO+0x24) +.equ high_ie, (GPIO+0x28) +.equ high_ip, (GPIO+0x2C) +.equ low_ie, (GPIO+0x30) +.equ low_ip, (GPIO+0x34) +.equ iof_en, (GPIO+0x38) +.equ iof_sel, (GPIO+0x3C) +.equ out_xor, (GPIO+0x40) + +# =========== Define UART registers =========== + +.equ UART, 0x10000000 +.equ UART_IER, (UART+0x01) +.equ UART_MCR, (UART+0x04) +.equ UART_MSR, (UART+0x06) + +# =========== Initialize UART and GPIO =========== + +# GPIO Initialization +.8byte input_en, 0x00000001, write32_test # enable bit 0 of input_en +.8byte output_en, 0x00000001, write32_test # enable bit 0 of output_en +.8byte output_val, 0x00000000, write32_test # make sure output_val is 0 +.8byte rise_ie, 0x00000001, write32_test # enable rise interrupts + +# =========== Initialize relevant PLIC registers =========== + +.8byte PLIC_INTPRI_GPIO, 0x00000000, write32_test # set GPIO priority to zero +.8byte PLIC_INTPRI_UART, 0x00000000, write32_test # set UART priority to zero +.8byte PLIC_INTEN00, 0x00000408, write32_test # enable m-mode interrupts +.8byte PLIC_INTEN10, 0x00000408, write32_test # enable s-mode interrupts +.8byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.8byte PLIC_THRESH1, 0x00000007, write32_test # set s-mode threshold to max + +# =========== Machine-Mode Priority Testing (1.T.X) =========== + +# Test 1.0.0: GPIO int lacks priority (0 = 0) +.8byte PLIC_THRESH0, 0x00000000, write32_test # change threshold +.8byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.8byte 0x0, 0x00000000, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.8byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +#.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.0.1: GPIO int has priority (1 > 0) +.8byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # let GPIO cause interrupts +.8byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.0.2: meip and c/c clear without interrupt pending +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte 0x0, 0x00000000, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # expect no interrupt pending +.8byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.1.0: GPIO lacks priority (1 = 1) +.8byte PLIC_THRESH0, 0x00000001, write32_test # change threshold +.8byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.8byte 0x0, 0x00000000, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.1.1: GPIO int has priority (2 > 1) +.8byte PLIC_INTPRI_GPIO, 0x00000002, write32_test # let GPIO cause interrupts +.8byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.2.0: GPIO int lacks priority (2 = 2) +.8byte PLIC_THRESH0, 0x00000002, write32_test # change threshold +.8byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.8byte 0x0, 0x00000000, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.2.1: GPIO int has priority (3 > 2) +.8byte PLIC_INTPRI_GPIO, 0x00000003, write32_test # let GPIO cause interrupts +.8byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.3.0: GPIO int lacks priority (3 = 3) +.8byte PLIC_THRESH0, 0x00000003, write32_test # change threshold +.8byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.8byte 0x0, 0x00000000, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.3.1: GPIO int has priority (4 > 3) +.8byte PLIC_INTPRI_GPIO, 0x00000004, write32_test # let GPIO cause interrupts +.8byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.4.0: GPIO int lacks priority (4 = 4) +.8byte PLIC_THRESH0, 0x00000004, write32_test # change threshold +.8byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.8byte 0x0, 0x00000000, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.4.1: GPIO int has priority (5 > 4) +.8byte PLIC_INTPRI_GPIO, 0x00000005, write32_test # let GPIO cause interrupts +.8byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.5.0: GPIO int lacks priority (5 = 5) +.8byte PLIC_THRESH0, 0x00000005, write32_test # change threshold +.8byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.8byte 0x0, 0x00000000, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.5.1: GPIO int has priority (6 > 5) +.8byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # let GPIO cause interrupts +.8byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.6.0: GPIO int lacks priority (6 = 6) +.8byte PLIC_THRESH0, 0x00000006, write32_test # change threshold +.8byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.8byte 0x0, 0x00000000, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.6.1: GPIO int has priority (7 > 6) +.8byte PLIC_INTPRI_GPIO, 0x00000007, write32_test # let GPIO cause interrupts +.8byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.7.0: GPIO int lacks priority (7 = 7) +.8byte PLIC_THRESH0, 0x00000007, write32_test # change threshold +.8byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.8byte 0x0, 0x00000000, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier +.8byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# =========== UART vs GPIO priority (2.X) =========== + +.8byte PLIC_INTEN00, 0x00000408, write32_test # enable m-mode interrupts +.8byte PLIC_INTEN10, 0x00000408, write32_test # enable s-mode interrupts +.8byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.8byte PLIC_THRESH1, 0x00000007, write32_test # set s-mode threshold to max +# UART Initialization +.8byte UART_IER, 0x08, write08_test # enable modem status interrupts from CTS +.8byte UART_MCR, 0x10, write08_test # enable loopback mode, RTS = 0 +.8byte UART_MSR, 0x00, write08_test # disable UART interrupt + +# Test 2.0: GPIO Priority = UART Priority + +.8byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.8byte PLIC_INTPRI_UART, 0x00000001, write32_test # UARTPriority = 1 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 2.1: GPIO Priority > UART Priority + +.8byte PLIC_INTPRI_GPIO, 0x00000003, write32_test # GPIOPriority = 3 +.8byte PLIC_INTPRI_UART, 0x00000002, write32_test # UARTPriority = 2 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 2.2: GPIO Priority < UART Priority + +.8byte PLIC_INTPRI_GPIO, 0x00000004, write32_test # GPIOPriority = 4 +.8byte PLIC_INTPRI_UART, 0x00000005, write32_test # UARTPriority = 5 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for UART +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 2.3: GPIO Priority < UART Priority + +.8byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # GPIOPriority = 6 +.8byte PLIC_INTPRI_UART, 0x00000007, write32_test # UARTPriority = 7 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for UART +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 2.4: Interrupts don't have enough priority + +.8byte PLIC_INTPRI_GPIO, 0x00000004, write32_test # GPIOPriority = 4 +.8byte PLIC_INTPRI_UART, 0x00000005, write32_test # UARTPriority = 5 +.8byte PLIC_THRESH0, 0x00000006, write32_test # set m-mode threshold to 6 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000000, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# =========== SEIP tests (3.X) =========== + +.8byte PLIC_INTEN00, 0x00000408, write32_test # enable m-mode interrupts +.8byte PLIC_INTEN10, 0x00000408, write32_test # enable s-mode interrupts +.8byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.8byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 + +# Test 3.0: Cause machine and supervisor interrupts + +.8byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.8byte PLIC_INTPRI_UART, 0x00000001, write32_test # UARTPriority = 1 +.8byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.8byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000A00, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 3.1: Suppress machine mode interrupts + +.8byte PLIC_INTPRI_GPIO, 0x00000003, write32_test # GPIOPriority = 3 +.8byte PLIC_INTPRI_UART, 0x00000002, write32_test # UARTPriority = 2 +.8byte PLIC_THRESH0, 0x00000007, write32_test # set m-mode threshold to 7 +.8byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000200, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 3.2: Cause SEIP with UART first + +.8byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # GPIOPriority = 6 +.8byte PLIC_INTPRI_UART, 0x00000007, write32_test # UARTPriority = 7 +.8byte PLIC_THRESH0, 0x00000007, write32_test # set m-mode threshold to 7 +.8byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000200, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 3.3: Low SEIP due to insufficient priority + +.8byte PLIC_INTPRI_GPIO, 0x00000002, write32_test # GPIOPriority = 2 +.8byte PLIC_INTPRI_UART, 0x00000003, write32_test # UARTPriority = 3 +.8byte PLIC_THRESH0, 0x00000004, write32_test # set m-mode threshold to 4 +.8byte PLIC_THRESH1, 0x00000005, write32_test # set s-mode threshold to 5 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000000, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# =========== UART interrupt enable tests (4.X) =========== + +.8byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.8byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.8byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIO Priority = 1 +.8byte PLIC_INTPRI_UART, 0x00000001, write32_test # UART Priority = 1 + +# Test 4.0: GPIO m-mode disabled + +.8byte PLIC_INTEN00, 0x00000400, write32_test # disable GPIO m-mode interrupts +.8byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000A00, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 4.1: UART m-mode disabled + +.8byte PLIC_INTEN00, 0x00000008, write32_test # disable UART m-mode interrupts +.8byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000200, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 4.2: GPIO s-mode disabled + +.8byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts +.8byte PLIC_INTEN10, 0x00000400, write32_test # enable all s-mode interrupts +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000A00, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 4.3: UART s-mode disabled + +.8byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts +.8byte PLIC_INTEN10, 0x00000008, write32_test # enable all s-mode interrupts +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 4.4: GPIO and UART s-mode disabled + +.8byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts +.8byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 4.5: GPIO and UART m-mode disabled + +.8byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts +.8byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000200, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 4.6: GPIO and UART fully disabled + +.8byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts +.8byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000200, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# =========== GPIO interrupt enable tests (5.X) =========== + +.8byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.8byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.8byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIO Priority = 1 +.8byte PLIC_INTPRI_UART, 0x00000001, write32_test # UART Priority = 1 + +# Test 5.0: GPIO m-mode disabled + +.8byte PLIC_INTEN00, 0x00000400, write32_test # disable GPIO m-mode interrupts +.8byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte 0x0, 0x00000200, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 5.1: UART m-mode disabled + +.8byte PLIC_INTEN00, 0x00000008, write32_test # disable UART m-mode interrupts +.8byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte 0x0, 0x00000A00, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 5.2: GPIO s-mode disabled + +.8byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts +.8byte PLIC_INTEN10, 0x00000400, write32_test # enable all s-mode interrupts +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 5.3: UART s-mode disabled + +.8byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts +.8byte PLIC_INTEN10, 0x00000008, write32_test # enable all s-mode interrupts +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte 0x0, 0x00000A00, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 5.4: GPIO and UART s-mode disabled + +.8byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts +.8byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 5.5: GPIO and UART m-mode disabled + +.8byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts +.8byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte 0x0, 0x00000200, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 5.6: GPIO and UART fully disabled + +.8byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts +.8byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte 0x0, 0x00000000, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# =========== S-mode enable tests (7.X) =========== + +.8byte 0x0, 0x0, goto_s_mode # go to s-mode. 0xb written to output +.8byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.8byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.8byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIO Priority = 1 +.8byte PLIC_INTPRI_UART, 0x00000001, write32_test # UART Priority = 1 + +# Test 7.0: GPIO m-mode disabled + +.8byte PLIC_INTEN00, 0x00000400, write32_test # disable GPIO m-mode interrupts +.8byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000200, readsip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 7.1: UART m-mode disabled + +.8byte PLIC_INTEN00, 0x00000008, write32_test # disable UART m-mode interrupts +.8byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000200, readsip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 7.2: GPIO s-mode disabled + +.8byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts +.8byte PLIC_INTEN10, 0x00000400, write32_test # enable all s-mode interrupts +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000200, readsip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM1, 0x0000000A, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM1, 0x0000000A, write32_test # complete claim made earlier +.8byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 7.3: UART s-mode disabled + +.8byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts +.8byte PLIC_INTEN10, 0x00000008, write32_test # enable all s-mode interrupts +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000200, readsip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 7.4: GPIO and UART s-mode disabled + +.8byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts +.8byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000000, readsip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM1, 0x00000000, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM1, 0x00000000, write32_test # complete claim made earlier +.8byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 7.5: GPIO and UART m-mode disabled + +.8byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts +.8byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000200, readsip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 7.6: GPIO and UART fully disabled + +.8byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts +.8byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000000, readsip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.8byte PLIC_CLAIM1, 0x00000000, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.8byte PLIC_CLAIM1, 0x00000000, write32_test # complete claim made earlier +.8byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one +.8byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# =========== Special claim tests (8) =========== + +.8byte 0x0, 0x0, goto_m_mode # write 0x9 to output + +.8byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # GPIO Priority = 6 +.8byte PLIC_INTPRI_UART, 0x00000007, write32_test # UART Priority = 7 +.8byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts +.8byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts +.8byte PLIC_THRESH0, 0x00000005, write32_test # set m-mode threshold to 5 + +# Test 8 + +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # read interrupt pending +.8byte PLIC_CLAIM0, 0x0000000A, read32_test # claim UART +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # UART interrupt cleared +.8byte PLIC_CLAIM0, 0x00000003, read32_test # claim GPIO +.8byte 0x0, 0x00000000, readmip_test # no interrupts, meip is low +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # both interrupts claimed +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete GPIO +.8byte 0x0, 0x00000800, readmip_test # GPIO interrupt sets MEIP +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # GPIO bit is set +.8byte PLIC_CLAIM0, 0x00000003, read32_test # claim GPIO again +.8byte 0x0, 0x00000000, readmip_test # meip is zeroed +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # both interrupts claimed +.8byte PLIC_CLAIM0, 0x0000000A, write32_test # complete UART claim +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000400, read32_test # UART pending +.8byte PLIC_CLAIM0, 0x00000003, write32_test # complete GPIO claim +.8byte 0x0, 0x00000800, readmip_test # read mip +.8byte PLIC_INTPENDING0, 0x00000408, read32_test # GPIO and UART pending +.8byte PLIC_CLAIM0, 0x0000000A, read32_test # claim UART + +.8byte 0x0, 0x0, terminate_test # terminate tests diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S new file mode 100644 index 000000000..ed5063e86 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S @@ -0,0 +1,230 @@ +/////////////////////////////////////////// +// +// WALLY-plic-s +// +// Author: David_Harris@hmc.edu and Nicholas Lucio +// Test PLIC supervisor context interrupts and claim/complete +// +// Created 2022-07-29 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-64.h" + +RVTEST_ISA("RV64I") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic-s) + +INIT_TESTS + +TRAP_HANDLER m + +j run_test_loop // begin test loop/table tests instead of executing inline code. + +INIT_TEST_TABLE + +END_TESTS + +TEST_STACK_AND_DATA + +.align 2 +test_cases: +# --------------------------------------------------------------------------------------------- +# Test Contents +# +# Here is where the actual tests are held, or rather, what the actual tests do. +# each entry consists of 3 values that will be read in as follows: +# +# '.8byte [x28 Value], [x29 Value], [x30 value]' +# or +# '.8byte [address], [value], [test type]' +# +# The encoding for x30 test type values can be found in the test handler in the framework file +# +# --------------------------------------------------------------------------------------------- + +# =========== Define PLIC registers =========== + +.equ PLIC, 0x0C000000 +.equ PLIC_INTPRI_GPIO, (PLIC+0x00000C) # GPIO is interrupt 3 +.equ PLIC_INTPRI_UART, (PLIC+0x000028) # UART is interrupt 10 +.equ PLIC_INTPENDING0, (PLIC+0x001000) # intPending0 register +.equ PLIC_INTPENDING1, (PLIC+0x001004) # intPending0 register +.equ PLIC_INTEN00, (PLIC+0x002000) # interrupt enables for context 0 (machine mode) sources 31:1 +.equ PLIC_INTEN10, (PLIC+0x002080) # interrupt enables for context 1 (supervisor mode) sources 31:1 +.equ PLIC_THRESH0, (PLIC+0x200000) # Priority threshold for context 0 (machine mode) +.equ PLIC_CLAIM0, (PLIC+0x200004) # Claim/Complete register for context 0 +.equ PLIC_THRESH1, (PLIC+0x201000) # Priority threshold for context 1 (supervisor mode) +.equ PLIC_CLAIM1, (PLIC+0x201004) # Claim/Complete register for context 1 + +# =========== Define GPIO registers =========== + +.equ GPIO, 0x10060000 +.equ input_val, (GPIO+0x00) +.equ input_en, (GPIO+0x04) +.equ output_en, (GPIO+0x08) +.equ output_val, (GPIO+0x0C) +.equ rise_ie, (GPIO+0x18) +.equ rise_ip, (GPIO+0x1C) +.equ fall_ie, (GPIO+0x20) +.equ fall_ip, (GPIO+0x24) +.equ high_ie, (GPIO+0x28) +.equ high_ip, (GPIO+0x2C) +.equ low_ie, (GPIO+0x30) +.equ low_ip, (GPIO+0x34) +.equ iof_en, (GPIO+0x38) +.equ iof_sel, (GPIO+0x3C) +.equ out_xor, (GPIO+0x40) + +# =========== Initialize GPIO =========== + +# GPIO Initialization +.8byte input_en, 0x00000001, write32_test # enable bit 0 of input_en +.8byte output_en, 0x00000001, write32_test # enable bit 0 of output_en +.8byte output_val, 0x00000000, write32_test # make sure output_val is 0 +.8byte rise_ie, 0x00000001, write32_test # enable rise interrupts + +# =========== Initialize relevant PLIC registers =========== + +.8byte PLIC_INTPRI_UART, 0x00000000, write32_test # set UART priority to 0 to never interrupt + +# =========== Enter Supervisor Mode =========== + +.8byte 0x0, 0x0, goto_s_mode # Enter supervisor mode + +# =========== Test interrupt enables and priorities =========== + +# Case 1.1: +.8byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.8byte PLIC_INTEN00, 0x00000008, write32_test # enable GPIO m-mode interrupts +.8byte PLIC_INTEN10, 0x00000008, write32_test # enable GPIO s-mode interrupts +.8byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.8byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte 0x0, 0x00000200, readsip_test # read sip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO +.8byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt from PLIC +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Case 1.2: +.8byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.8byte PLIC_INTEN00, 0x00000000, write32_test # enable GPIO m-mode interrupts +.8byte PLIC_INTEN10, 0x00000008, write32_test # enable GPIO s-mode interrupts +.8byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.8byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte 0x0, 0x00000200, readsip_test # read sip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO +.8byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt from PLIC +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Case 1.3: +.8byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.8byte PLIC_INTEN00, 0x00000008, write32_test # enable GPIO m-mode interrupts +.8byte PLIC_INTEN10, 0x00000000, write32_test # enable GPIO s-mode interrupts +.8byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.8byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte 0x0, 0x00000000, readsip_test # read sip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO +.8byte PLIC_CLAIM1, 0x00000000, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt from PLIC +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Case 1.4: +.8byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.8byte PLIC_INTEN00, 0x00000000, write32_test # enable GPIO m-mode interrupts +.8byte PLIC_INTEN10, 0x00000000, write32_test # enable GPIO s-mode interrupts +.8byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.8byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte 0x0, 0x00000000, readsip_test # read sip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO +.8byte PLIC_CLAIM1, 0x00000000, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt from PLIC +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Case 1.5: +.8byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.8byte PLIC_INTEN00, 0x00000008, write32_test # enable GPIO m-mode interrupts +.8byte PLIC_INTEN10, 0x00000008, write32_test # enable GPIO s-mode interrupts +.8byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.8byte PLIC_THRESH1, 0x00000005, write32_test # set s-mode threshold to 5 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte 0x0, 0x00000000, readsip_test # read sip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO +.8byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt from PLIC +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Case 1.6: +.8byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.8byte PLIC_INTEN00, 0x00000008, write32_test # enable GPIO m-mode interrupts +.8byte PLIC_INTEN10, 0x00000008, write32_test # enable GPIO s-mode interrupts +.8byte PLIC_THRESH0, 0x00000005, write32_test # set m-mode threshold to 5 +.8byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte 0x0, 0x00000200, readsip_test # read sip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO +.8byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt from PLIC +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Case 1.7: +.8byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.8byte PLIC_INTEN00, 0x00000008, write32_test # enable GPIO m-mode interrupts +.8byte PLIC_INTEN10, 0x00000008, write32_test # enable GPIO s-mode interrupts +.8byte PLIC_THRESH0, 0x00000005, write32_test # set m-mode threshold to 5 +.8byte PLIC_THRESH1, 0x00000005, write32_test # set s-mode threshold to 5 +.8byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.8byte 0x0, 0x00000000, readsip_test # read sip +.8byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO +.8byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.8byte output_val, 0x00000000, write32_test # clear output_val +.8byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.8byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.8byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt from PLIC +.8byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# All done + +.8byte 0x0, 0x0, terminate_test # terminate tests diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-uart-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-uart-01.S new file mode 100644 index 000000000..3cbf3591b --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-uart-01.S @@ -0,0 +1,248 @@ +/////////////////////////////////////////// +// +// WALLY-uart +// +// Author: David_Harris@hmc.edu and Nicholas Lucio +// +// Created 2022-06-16 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-64.h" + +RVTEST_ISA("RV64I") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",uart) + +INIT_TESTS + +TRAP_HANDLER m + +j run_test_loop // begin test loop/table tests instead of executing inline code. + +INIT_TEST_TABLE + +END_TESTS + +TEST_STACK_AND_DATA + +.align 2 + +.equ UART, 0x10000000 +.equ UART_RBR, (UART) +.equ UART_THR, (UART) +.equ UART_IER, (UART+0x01) +.equ UART_IIR, (UART+0x02) +.equ UART_FCR, (UART+0x02) +.equ UART_LCR, (UART+0x03) +.equ UART_MCR, (UART+0x04) +.equ UART_LSR, (UART+0x05) +.equ UART_MSR, (UART+0x06) +.equ UART_Scr, (UART+0x07) + +test_cases: +# --------------------------------------------------------------------------------------------- +# Test Contents +# +# Here is where the actual tests are held, or rather, what the actual tests do. +# each entry consists of 3 values that will be read in as follows: +# +# '.8byte [x28 Value], [x29 Value], [x30 value]' +# or +# '.8byte [address], [value], [test type]' +# +# The encoding for x30 test type values can be found in the test handler in the framework file +# +# --------------------------------------------------------------------------------------------- + +# =========== UART resets to correct values on master reset =========== + +.8byte UART_IER, 0x00, read08_test +.8byte UART_IIR, 0x01, read08_test # IIR resets to 1 +# .8byte UART_LCR, 0x00, read08_test *** commented out because LCR should reset to zero but resets to 3 to help Linux boot +.8byte UART_MCR, 0x00, read08_test +.8byte UART_LSR, 0x60, read08_test # LSR resets with transmit status bits set +.8byte UART_MSR, 0x00, read04_test + +# =========== Basic read-write =========== + +.8byte UART_LCR, 0x00, write08_test # set LCR to initial value +.8byte UART_MCR, 0x10, write08_test # put UART into loopback for MSR test +.8byte UART_LSR, 0x60, read08_test +.8byte UART_THR, 0x00, write08_test # write value to UART +.8byte UART_LSR, 0x00, read08_test # data not ready and transmitter is not empty +.8byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and LSR +.8byte UART_RBR, 0x00, read08_test # read written value +.8byte UART_LSR, 0x60, read08_test # read LSR + +# =========== Different size read-write =========== + +# Transmit 5 bits + +.8byte UART_LCR, 0x00, write08_test # set LCR to transmit 5 bits +.8byte UART_THR, 0x55, write08_test # write value to UART +.8byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and then LSR +.8byte UART_RBR, 0x15, read08_test # read written value without bits 5-7 + +# Transmit 6 bits + +.8byte UART_LCR, 0x01, write08_test # set LCR to transmit six bits +.8byte UART_THR, 0xAA, write08_test # write value to UART +.8byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and then LSR +.8byte UART_RBR, 0x2A, read08_test # read written value without bits 6 & 7 + +# Transmit 7 bits + +.8byte UART_LCR, 0x02, write08_test # set LCR to transmit seven bits +.8byte UART_THR, 0xFF, write08_test # write value to UART +.8byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and then LSR +.8byte UART_RBR, 0x7F, read08_test # read written value without bit 7 + +# Transmit 8 bits + +.8byte UART_LCR, 0x03, write08_test # set LCR to transmit eight bits +.8byte UART_THR, 0x80, write08_test # write value to UART +.8byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and then LSR +.8byte UART_RBR, 0x80, read08_test # read full written value + sign extension + +# Check function with odd parity + +.8byte UART_LCR, 0x0B, write08_test # set LCR to transmit 8 bits + odd partiy +.8byte UART_THR, 0x79, write08_test # write value to UART +.8byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and then LSR +.8byte UART_RBR, 0x79, read08_test # read full written value + +# Check function with even parity + +.8byte UART_LCR, 0x1B, write08_test # set LCR to transmit 8 bits + even parity +.8byte UART_THR, 0x6A, write08_test # write value to UART +.8byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and then LSR +.8byte UART_RBR, 0x6A, read08_test # read full written value + +# Check function with extra stop bit + +.8byte UART_LCR, 0x07, write08_test # set LCR to transmit 8 bits + extra stop +.8byte UART_THR, 0x5B, write08_test # write value to UART +.8byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and then LSR +.8byte UART_RBR, 0x5B, read08_test # read full written value +.8byte UART_LCR, 0x03, write08_test # set LCR to transmit 8 bits + no extra stop bit + +# =========== Transmit-related interrupts =========== + +.8byte UART_IER, 0x07, write08_test # enable data available, buffer empty, and line status interrupts +.8byte UART_IIR, 0x02, read08_test # buffer should be empty, causing interrupt +.8byte UART_THR, 0x00, write08_test # write zeroes to transmitter +.8byte 0x0, 0x0401, uart_data_wait # IIR should have data ready interrupt +.8byte UART_THR, 0x01, write08_test # write 1 to transmitter buffer +.8byte UART_IIR, 0x04, read08_test # data interrupt should still be high +.8byte 0x0, 0x06, uart_lsr_intr_wait # wait for transmission to complete, IIR should throw error due to overrun error. +.8byte UART_LSR, 0x23, read08_test # read overrun error from LSR +.8byte UART_IIR, 0x04, read08_test # check that LSR interrupt was cleared +.8byte UART_RBR, 0x01, read08_test # read previous value from UART + +# =========== MODEM interrupts =========== + +.8byte UART_MSR, 0x00, write08_test # clear MSR +.8byte UART_IER, 0x08, write08_test # enable MODEM Status interrupts +.8byte UART_IIR, 0x01, read08_test # no interrupts pending +.8byte UART_MCR, 0x12, write08_test # Cause DCTS interrupt +.8byte UART_IIR, 0x00, read08_test # MODEM interrupt +.8byte UART_MSR, 0x11, read08_test # Read MSR to clear interrupt +.8byte UART_IIR, 0x01, read08_test # interrupt cleared by reading MSR +.8byte UART_MCR, 0x13, write08_test # Set DSR high +.8byte UART_IIR, 0x00, read08_test # MODEM interrupt +.8byte UART_MSR, 0x32, read08_test # Read MSR to clear interrupt +.8byte UART_IIR, 0x01, read08_test # Interrupt cleared by reading MSR +.8byte UART_MCR, 0x17, write08_test # Set RIb low and keep CTS and DSR +.8byte UART_MCR, 0x13, write08_test # Set RIb high and keep CTS and DSR +.8byte UART_IIR, 0x00, read08_test # MODEM interrupt +.8byte UART_MSR, 0x34, read08_test # Read MSR to clear interrupt +.8byte UART_IIR, 0x01, read08_test # Interrupt cleared by reading MSR +.8byte UART_MCR, 0x1B, write08_test # Set DCD high and keep CTS and DSR +.8byte UART_IIR, 0x00, read08_test # MODEM interrupt +.8byte UART_MSR, 0xb8, read08_test # Read MSR to clear interrupt +.8byte UART_IIR, 0x01, read08_test # Interrupt cleared by reading MSR +.8byte UART_MCR, 0x10, write08_test # Clear MCR +.8byte UART_MSR, 0x00, write08_test # Clear MSR + +# =========== FIFO interrupts =========== + +.8byte UART_IER, 0x07, write08_test # enable data available, buffer empty, and line status interrupts +.8byte UART_FCR, 0x41, write08_test # Set FIFO threshold to 4 and enable FIFO mode +.8byte UART_IIR, 0xC2, read08_test # Enabling FIFO sets top two bits of IIR +.8byte UART_THR, 0x00, write08_test # write 0 to transmit register +.8byte 0x0, 0xC101, uart_data_wait # no interrupts pending (transmitter interrupt squashed by early read) +.8byte UART_RBR, 0x00, read08_test # read 0 from buffer register +.8byte UART_THR, 0xA5, write08_test # Write A5 to transmit register +.8byte UART_THR, 0x01, write08_test # Write 1 to transmit register +.8byte UART_IIR, 0xC1, read08_test # no interrupts pending +.8byte UART_THR, 0x02, write08_test # Write 2 to transmit register +.8byte UART_THR, 0x03, write08_test # Write 3 to transmit register +.8byte 0x0, 0xC401, uart_data_wait # Interrupt due to data ready +.8byte UART_RBR, 0xA5, read08_test # Read A5 from buffer register +.8byte UART_IIR, 0xC2, read08_test # Data ready interrupt cleared +.8byte UART_RBR, 0x01, read08_test # Read 1 from buffer register +.8byte UART_RBR, 0x02, read08_test # Read 2 from buffer register +.8byte UART_LSR, 0x61, read08_test # Data ready, 1 item left in FIFO +.8byte UART_RBR, 0x03, read08_test # Read 3 from buffer register +.8byte UART_LSR, 0x60, read08_test # No data ready, FIFO is empty +.8byte UART_THR, 0xFF, write08_test # Write FF to transmit register +.8byte UART_THR, 0xFE, write08_test # Write FE to transmit register +.8byte 0x0, 0xC101, uart_data_wait # Interrupt due to data ready +.8byte UART_FCR, 0xC7, write08_test # Clear all bytes in FIFO +.8byte UART_FCR, 0xC1, read08_test # Check that FCR clears bits 1 and 2 when written to 1 +.8byte UART_LSR, 0x60, read08_test # No data ready, FIFO cleared by writing to FCR + +# =========== FIFO receiver/overrun =========== + +.8byte UART_FCR, 0x01, write08_test # Set FIFO trigger threshold to 1 and enable FIFO mode +.8byte UART_IIR, 0xC1, read08_test # FIFO has not reached trigger level +.8byte UART_THR, 0x00, write08_test # Write 0 to transmit register +.8byte 0x0, 0xC401, uart_data_wait # Interrupt due to trigger threshold reached +.8byte UART_FCR, 0x41, write08_test # Set FIFO trigger threshold to 4 +.8byte UART_IIR, 0xC1, read08_test # FIFO has not reached trigger threshold +.8byte UART_THR, 0x01, write08_test # Write 1 to transmit register +.8byte UART_THR, 0x02, write08_test # Write 2 to transmit register +.8byte 0x0, 0xC101, uart_data_wait # FIFO has not reached trigger threshold +.8byte UART_THR, 0x03, write08_test # Write 3 to transmit register +.8byte 0x0, 0xC401, uart_data_wait # Interrupt due to trigger threshold reached +.8byte UART_FCR, 0x81, write08_test # Set FIFO trigger threshold to 8 +.8byte UART_IIR, 0xC1, read08_test # FIFO has not reached trigger threshold +.8byte UART_THR, 0x04, write08_test # Write 4 to transmit register +.8byte UART_THR, 0x05, write08_test # Write 5 to transmit register +.8byte UART_THR, 0x06, write08_test # Write 6 to transmit register +.8byte 0x0, 0xC101, uart_data_wait # FIFO has not reached trigger threshold +.8byte UART_THR, 0x07, write08_test # Write 7 to transmit register +.8byte 0x0, 0xC401, uart_data_wait # Interrupt due to trigger threshold reached +.8byte UART_FCR, 0xC1, write08_test # Set FIFO trigger threshold to 14 +.8byte UART_IIR, 0xC1, read08_test # FIFO has not reached trigger threshold +.8byte UART_THR, 0x08, write08_test # Write 8 to transmit register +.8byte UART_THR, 0x09, write08_test # Write 9 to transmit register +.8byte UART_THR, 0x0A, write08_test # Write 10 to transmit register +.8byte UART_THR, 0x0B, write08_test # Write 11 to transmit register +.8byte UART_THR, 0x0C, write08_test # Write 12 to transmit register +.8byte 0x0, 0xC101, uart_data_wait # FIFO has not reached trigger threshold +.8byte UART_THR, 0x0D, write08_test # Write 13 to transmit register +.8byte 0x0, 0xC401, uart_data_wait # Interrupt due to trigger threshold reached +.8byte UART_THR, 0x0E, write08_test # Write 14 to transmit register +.8byte UART_THR, 0x0F, write08_test # Write 15 to transmit register +.8byte 0x0, 0xC101, uart_data_wait +.8byte UART_LSR, 0x61, read08_test # FIFO contains data, no overrun error +.8byte UART_THR, 0x10, write08_test # Write 16 to transmit register, filling RX shift register +.8byte UART_THR, 0x11, write08_test # Write 17 to transmit register, destroying contents held in shift register +.8byte 0x0, 0x06, uart_lsr_intr_wait # Wait for LSR interrupt ID +.8byte UART_LSR, 0xA3, read08_test # Read overrun error from LSR + +.8byte 0x0, 0x0, terminate_test \ No newline at end of file