diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 9c990750b..1101e6dd4 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -94,6 +94,8 @@ module ifu ( (* mark_debug = "true" *) logic [`XLEN-1:0] PCNextF; // Next PCF, selected from Branch predictor, Privilege, or PC+2/4 logic BranchMisalignedFaultE; // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed) logic [`XLEN-1:0] PCPlus2or4F; // PCF + 2 (CompressedF) or PCF + 4 (Non-compressed) + logic [`XLEN-1:0] PCNextFSpill; // Next PCF after possible + 2 to handle spill + logic [`XLEN-1:0] PCFSpill; // PCF with possible + 2 to handle spill logic [`XLEN-1:0] PCLinkD; // PCF2or4F delayed 1 cycle. This is next PC after a control flow instruction (br or j) logic [`XLEN-1:2] PCPlus4F; // PCPlus4F is always PCF + 4. Fancy way to compute PCPlus2or4F logic [`XLEN-1:0] PCD; // Decode stage instruction address @@ -105,6 +107,7 @@ module ifu ( logic [31:0] ICacheInstrF; // Instruction from the I$ logic [31:0] InstrRawF; // Instruction from the IROM, I$, or bus logic CompressedF; // The fetched instruction is compressed +(* mark_debug = "true" *) logic [31:0] PostSpillInstrRawF; // Fetch instruction after merge two halves of spill logic [31:0] InstrRawD; // Non-decompressed instruction in the Decode stage logic [1:0] IFURWF; // IFU alreays read IFURWF = 10 @@ -112,19 +115,17 @@ module ifu ( logic [31:0] NextInstrD, NextInstrE; // Instruction into the next stage after possible stage flush - logic CacheableF; - logic [`XLEN-1:0] PCNextFSpill; - logic [`XLEN-1:0] PCFSpill; - logic SelNextSpillF; - logic ICacheFetchLine; - logic BusStall; - logic ICacheStallF, IFUCacheBusStallD; - logic GatedStallD; -(* mark_debug = "true" *) logic [31:0] PostSpillInstrRawF; + logic CacheableF; // PMA indicates isntruction address is cacheable + logic SelNextSpillF; // In a spill, stall pipeline and gate local stallF + logic BusStall; // Bus interface busy with multicycle operation + logic ICacheStallF; // I$ busy with multicycle operation + logic IFUCacheBusStallD; // EIther I$ or bus busy with multicycle operation + logic GatedStallD; // StallD gated by selected next spill // branch predictor signal - logic [`XLEN-1:0] PCNext1F, PCNext0F; - logic BusCommittedF, CacheCommittedF; - logic SelIROM; + logic [`XLEN-1:0] PCNext1F; // Branch predictor next PCF + logic BusCommittedF; // Bus memory operation in flight, delay interrupts + logic CacheCommittedF; // I$ memory operation started, delay interrupts + logic SelIROM; // PMA indicates instruction address is in the IROM assign PCFExt = {2'b00, PCFSpill}; @@ -213,13 +214,12 @@ module ifu ( localparam integer LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1; if(`ICACHE) begin : icache localparam integer LINELEN = `ICACHE ? `ICACHE_LINELENINBITS : `XLEN; - localparam integer LLENPOVERAHBW = `LLEN / `AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation) + localparam integer LLENPOVERAHBW = `LLEN / `AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation) logic [LINELEN-1:0] FetchBuffer; logic [`PA_BITS-1:0] ICacheBusAdr; logic ICacheBusAck; logic [1:0] CacheBusRW, BusRW, CacheRWF; - //assign BusRW = IFURWF & ~{IgnoreRequest, IgnoreRequest} & ~{CacheableF, CacheableF} & ~{SelIROM, SelIROM}; assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : '0; assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0; cache #(.LINELEN(`ICACHE_LINELENINBITS), @@ -268,8 +268,7 @@ module ifu ( if(`IROM_SUPPORTED) mux2 #(32) UnCachedDataMux2(FetchBuffer, IROMInstrF, SelIROM, InstrRawF); else assign InstrRawF = FetchBuffer; assign IFUHBURST = 3'b0; - assign {ICacheFetchLine, ICacheStallF} = '0; - assign {ICacheMiss, ICacheAccess} = '0; + assign {ICacheMiss, ICacheAccess, ICacheStallF} = '0; end end else begin : nobus // block: bus assign {BusStall, CacheCommittedF} = '0; @@ -335,7 +334,6 @@ module ifu ( mux2 #(`XLEN) pcmux1(.d0(PCPlus2or4F), .d1(IEUAdrE), .s(PCSrcE), .y(PCNext1F)); assign BPPredWrongE = PCSrcE; assign {InstrClassM, DirPredictionWrongM, BTBPredPCWrongM, RASPredPCWrongM, PredictionInstrClassWrongM} = '0; - assign PCNext0F = PCPlus2or4F; assign NextValidPCE = PCE; end diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 0ebd84f8a..d84334a85 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -103,7 +103,7 @@ module lsu ( logic GatedStallW; // Hazard unit StallW gated when SelHPTW = 1 - logic DCacheStallW; // D$ busy with multicycle operation + logic DCacheStallM; // D$ busy with multicycle operation logic BusStall; // Bus interface busy with multicycle operation logic HPTWStall; // HPTW busy with multicycle operation @@ -152,7 +152,7 @@ module lsu ( if(`VIRTMEM_SUPPORTED) begin : VIRTMEM_SUPPORTED hptw hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF, .DTLBMissM, .DTLBWriteM, .InstrDAPageFaultF, .DataDAPageFaultM, - .FlushW, .DCacheStallW, .SATP_REGW, .PCF, + .FlushW, .DCacheStallM, .SATP_REGW, .PCF, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW, .ReadDataM(ReadDataM[`XLEN-1:0]), // ReadDataM is LLEN, but HPTW only needs XLEN .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M, @@ -179,7 +179,7 @@ module lsu ( // the trap module. assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM; assign GatedStallW = StallW & ~SelHPTW; - assign LSUStallM = DCacheStallW | HPTWStall | BusStall; + assign LSUStallM = DCacheStallM | HPTWStall | BusStall; ///////////////////////////////////////////////////////////////////////////////////////////// // MMU and misalignment fault logic required if privileged unit exists @@ -267,7 +267,7 @@ module lsu ( .FlushCache(FlushDCacheM), .NextAdr(IEUAdrE[11:0]), .PAdr(PAdrM), .ByteMask(ByteMaskM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]), .CacheWriteData(LSUWriteDataM), .SelHPTW, - .CacheStall(DCacheStallW), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), + .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), .CacheCommitted(DCacheCommittedM), .CacheBusAdr(DCacheBusAdr), .ReadDataWord(DCacheReadDataWordM), .FetchBuffer, .CacheBusRW, @@ -307,14 +307,14 @@ module lsu ( if(`DTIM_SUPPORTED) mux2 #(`XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM, SelDTIM, ReadDataWordMuxM); else assign ReadDataWordMuxM = FetchBuffer[`XLEN-1:0]; assign LSUHBURST = 3'b0; - assign {DCacheStallW, DCacheCommittedM, DCacheMiss, DCacheAccess} = '0; + assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = '0; end end else begin: nobus // block: bus, only DTIM assign LSUHWDATA = '0; assign ReadDataWordMuxM = DTIMReadDataWordM; assign {BusStall, BusCommittedM} = '0; assign {DCacheMiss, DCacheAccess} = '0; - assign {DCacheStallW, DCacheCommittedM} = '0; + assign {DCacheStallM, DCacheCommittedM} = '0; end ///////////////////////////////////////////////////////////////////////////////////////////// diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv index e7fdc416b..5e798eed4 100644 --- a/pipelined/src/mmu/hptw.sv +++ b/pipelined/src/mmu/hptw.sv @@ -43,7 +43,7 @@ module hptw ( input logic [1:0] PrivilegeModeW, input logic [`XLEN-1:0] ReadDataM, // page table entry from LSU input logic [`XLEN-1:0] WriteDataM, - input logic DCacheStallW, // stall from LSU + input logic DCacheStallM, // stall from LSU input logic [2:0] Funct3M, input logic [6:0] Funct7M, input logic ITLBMissF, @@ -114,7 +114,7 @@ module hptw ( // State flops flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissOrDAFaultM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB) - assign PRegEn = HPTWRW[1] & ~DCacheStallW | UpdatePTE; + assign PRegEn = HPTWRW[1] & ~DCacheStallM | UpdatePTE; flopenr #(`XLEN) PTEReg(clk, reset, PRegEn, NextPTE, PTE); // Capture page table entry from data cache // Assign PTE descriptors common across all XLEN values @@ -248,24 +248,24 @@ module hptw ( IDLE: if (TLBMiss) NextWalkerState = InitialWalkerState; else NextWalkerState = IDLE; L3_ADR: NextWalkerState = L3_RD; // first access in SV48 - L3_RD: if (DCacheStallW) NextWalkerState = L3_RD; + L3_RD: if (DCacheStallM) NextWalkerState = L3_RD; else NextWalkerState = L2_ADR; L2_ADR: if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // first access in SV39 else NextWalkerState = LEAF; - L2_RD: if (DCacheStallW) NextWalkerState = L2_RD; + L2_RD: if (DCacheStallM) NextWalkerState = L2_RD; else NextWalkerState = L1_ADR; L1_ADR: if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // first access in SV32 else if (ValidNonLeafPTE) NextWalkerState = L1_RD; else NextWalkerState = LEAF; - L1_RD: if (DCacheStallW) NextWalkerState = L1_RD; + L1_RD: if (DCacheStallM) NextWalkerState = L1_RD; else NextWalkerState = L0_ADR; L0_ADR: if (ValidNonLeafPTE) NextWalkerState = L0_RD; else NextWalkerState = LEAF; - L0_RD: if (DCacheStallW) NextWalkerState = L0_RD; + L0_RD: if (DCacheStallM) NextWalkerState = L0_RD; else NextWalkerState = LEAF; LEAF: if (`HPTW_WRITES_SUPPORTED & DAPageFault) NextWalkerState = UPDATE_PTE; else NextWalkerState = IDLE; - UPDATE_PTE: if(DCacheStallW) NextWalkerState = UPDATE_PTE; + UPDATE_PTE: if(DCacheStallM) NextWalkerState = UPDATE_PTE; else NextWalkerState = LEAF; default: NextWalkerState = IDLE; // should never be reached endcase // case (WalkerState)