From 758da62a9f0e8141e6545e1a2df9e4d9b6206c2b Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Mar 2023 23:16:57 -0700 Subject: [PATCH] ported fixes to 32 bit tests --- .../privilege/references/WALLY-trap-s-01.reference_output | 4 ---- .../rv32i_m/privilege/src/WALLY-trap-s-01.S | 6 +++--- 2 files changed, 3 insertions(+), 7 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output index 089aeba9d..5ee52bee5 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output @@ -29,10 +29,6 @@ 00000008 # scause from U mode ecall 00000000 # stval of ecall (*** defined to be zero for now) 00000000 # masked out mstatus.mpp = 0 (from U mode), mstatus.MPIE = 0, and mstatus.MIE = 0 -0007ec01 # value to indicate successful vectoring on s soft interrupt -80000001 # scause value from s soft interrupt -00000000 # stval for ssoft interrupt (0x0) -00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 0007ec03 # value to indicate successful vectoring on m soft interrupt 80000003 # scause value from m soft interrupt 00000000 # stval for msoft interrupt (0x0) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S index 4b1e2afa4..85758b101 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S @@ -57,12 +57,12 @@ GOTO_U_MODE // Causes S mode ecall GOTO_S_MODE // Causes U mode ecall -// some interrupts excluded becaus writing MIP is illegal from S mode -jal cause_s_soft_interrupt +// some interrupts excluded because writing MIP is illegal from S mode and writing SIP is only possible when delegated, which is tested below (priv spec 3.1.9) +//jal cause_s_soft_interrupt jal cause_m_soft_interrupt jal cause_m_time_interrupt li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off. -// since interrupts are not always enabled, +// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3 jal cause_s_ext_interrupt_GPIO li a3, 0x40 jal cause_m_ext_interrupt