From 7732d38c36d09f8bdd5f4ffbd53c9017a0b64133 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 23 Oct 2021 08:53:32 -0700 Subject: [PATCH] lint cleaning and moved files into subdirectories --- tests/wally-riscv-arch-test/.gitignore | 11 + tests/wally-riscv-arch-test/CHANGELOG.md | 413 ++ tests/wally-riscv-arch-test/CONTRIBUTION.md | 66 + tests/wally-riscv-arch-test/COPYING.APACHE | 202 + tests/wally-riscv-arch-test/COPYING.BSD | 9 + tests/wally-riscv-arch-test/COPYING.CC | 395 ++ tests/wally-riscv-arch-test/Makefile | 123 + tests/wally-riscv-arch-test/Makefile.include | 28 + tests/wally-riscv-arch-test/README.md | 74 + tests/wally-riscv-arch-test/doc/.gitignore | 6 + tests/wally-riscv-arch-test/doc/ChangeLog | 147 + .../wally-riscv-arch-test/doc/MIGRATION.adoc | 88 + tests/wally-riscv-arch-test/doc/Makefile | 82 + tests/wally-riscv-arch-test/doc/README.adoc | 460 ++ .../wally-riscv-arch-test/doc/custom.wordlist | 73 + .../wally-riscv-arch-test/doc/file-struct.jpg | Bin 0 -> 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+# Ignore transients generated by the tests +/.cproject +/.project +/work/ +/setup.env +#ignore Mac file system artifacts +*.DS_Store + +riscv-target/ diff --git a/tests/wally-riscv-arch-test/CHANGELOG.md b/tests/wally-riscv-arch-test/CHANGELOG.md new file mode 100644 index 000000000..cf6144267 --- /dev/null +++ b/tests/wally-riscv-arch-test/CHANGELOG.md @@ -0,0 +1,413 @@ +# CHANGELOG + +## [2.5.3] - 2021-10-15 + - fix the lower case `i` in the `RVTEST_CASE` macros used in the shift operation tests. + +## [2.5.2] - 2021-10-14 + - update format for aes32 and sm4 instructions + - update reference signature for sha256 and sm3 instructions in rv64i_m/K_unratified + - delete zip and unzip tests in rv64i_m/K_unratified + - update tests for aes64ks1i, sm4ed and sm4ks to use byte_count with overlap = "Y" to improve the coverage of S-boxes + +## [2.5.1] - 2021-10-07 + - added styles files to the F coverage report directories. + +## [2.5.0] - 2021-10-01 + - Added rv32f tests, references, coverage files and data propagation reports + - fixed broken links in READMEs across the repo. + - corrected string "EBREAK" in io string macro to "ECALL" for ecall.S tests. #207 + - fixed typo `.alive` --> `.align` in `riscv-target/example_target/model_test.h`. + +## [2.4.7] - 2021-10-01 + - Fix for the issue #206 + +## [2.4.6] - 2021-08-02 + - Added rv32e tests in riscv-test-suite + +## [2.4.5] - 2021-07-29 + - fix for issue #195 + +## [2.4.4] - 2021-07-19 + - Annotating tags during releases + +## [2.4.3] - 2021-05-20 + - added new 64-bit K crypto tests as per the test-plan presented by the scalar crypto task group + [here](https://github.com/riscv/riscv-crypto/blob/d89dfee25780f79c162da4eb69cd9076dd701c88/tests/compliance/test-plan-scalar.adoc) + - added new 32-bit K crypto tests as per the above mentioned test-plan. + - added coverage and data propagation reports for the above tests. + - updated README in riscv-test-suite + - added missing semi-colon in example target Makefile.include files + +## [2.4.2] - 2021-04-20 + - changed all occurances of SPTBR to the new name SATP + +## [2.4.1] - 2021-04-01 + - updated issue number in TestFormatSpec to be consistent with doc history + - adding a contribution guideline + - updated comment on usage of RISCV_DEVICE in Makefile.include + - updated licenses that are currently used by tests + - renamed K tests to K_unratified + - updated ci to build and upload pdf for testformatspec + +## [2.4.0] - 2021-03-26 +2021-03-26 Duncan Graham + - Added new K Crypto (scalar) (0.8.1) tests from Imperas + +## [2.3.1] - 2021-03-20 +### Changed + - Compliance Task Group changed to Architecture Test SIG in all docs and comments + - replacing old riscv-compliance link with new riscv-arch-test links + - fixed ci for release +### Removed + - spec/TestFormatSpec.pdf is removed since its old. Keeping only adoc file + - removing obsolete and commented out portions from doc/README + +## [2.3] - 2021-03-11 +### Added + - updated maintainers list in root-level readme + - updated the links to riscof, isac and ctg repos and docs in root-level readme + - adding CI to update versions automatically +### Removed + - replaced spike target with a REAMDE pointing to riscv-isa-sim/arch_test_target/README.md + +## [2.2] - 2021-01-28 + 2021-01-22 Tobias Wölfel + * Add missing base ISA check in riscv-test-suite + + 2021-01-20 Xiretza + * Deduplicate makefiles in riscv-test-suite + * Makefile: Fix ordering of simulate and verify targets to allow multi-job runs (make -j) + * Makefile.include: Document RISCV_TEST + * Makefile: use $(TARGETDIR) variable for postverify target instead of hard-coded path + + 2021-01-16 S Pawan Kumar + * Fixed NARGS macro defintion to work correctly. + + 2021-01-15 Xiretza + * style: Add a missing space to the "OK" message in verify.sh + + 2020-12-17 Neel Gala + * remove env folder symlinks from all riscv-test-suite src folders + * fixed assertion macros for ovpsim + * renamed RVTEST_ASSERT to RVMODEL_ASSERT in the Makefile and ovpsim macros + * tests updated with right set of "correctvals" + + 2020-11-24 Neel Gala + * added MIGRATION.adoc in doc directory to indicate how old framework targets can work with + changes made as part of this PR + * updated doc/README.adoc to avoid the word "compliance" and updated the section on porting a new + target to the framework. + * Added an example_target directory to host dummy files which can be used as a starting point for + porting targets. This was provided by MarcKarasek. + * migrated/ported existing targets (except codasip and sifive-formal) to the new framework + changes. + * in riscv-test-env/p/riscv_test.h changed names of RVTEST_[CODE/DATA]_[BEGIN/END] to + RVTEST_[CODE/DATA]_[BEGIN/END]_OLD respectively to avoid conflicts with the new framework macros. + * in riscv-test-env/p/riscv_test.h re-strutucture RVTEST_DATA_BEGIN_OLD/END to ensure that all + target specific data contents are introduced in RVTEST_DATA_END after the signature. + * added new file riscv-test-suite/env/arch_test.h which contains the macros used by the new set of + tests. A symlink to this in the riscv-test-env directory is also created. The arch_test also + includes aliases for the old macros. + * encoding.h moved to riscv-test-suite/env and a symlink to this file exists in riscv-test-env. + This was done to ensure that the arch_test.h and encoding.h are not to be modified by the + targets + * Added riscv-test-stats which includes coverage and data propagation reports for the tests + available in the riscv-test-suite directory. + * upddted the directory structure of the riscv-test-suite as per definition found in the + TestFormatSpec document. + * new set of tests with better coverage for rv[32/64][I,M,C, Zifencei] added. Almost all tests + were generated using the open source riscv_ctg tool. A few tests like fence, fencei, ebreak, + ecall, etc were handwritten/modified to follow the new macro conventions. + * Updated TestFormatSpec to avoid the word compliance and also updated the definitions of macros + and signatures + * created a root-level Makefile.include to decouple the Makefile and target specific settings. + * Added riscv-target and Makefile.include to the .gitignore file to stop tracking target specific + changes. + * Added special targets for compile(build), simulate(run) and verify in the Makefiles of each + test-suite. + * the existing riscv-targets have been either updated for the new framework or migrated to the + framework. + + 2020-10-15 Simon Davidmann + * riscvOVPsim enhanced and moved to its own respository: github.com/riscv-ovpsim + + 2020-04-24 Allen Baum + * fixed the I-SB-01.S and I-SH-01.S tests and associated reference signatures to account + of tests with negative offsets (which causes stores outside the signature area) + + 2020-03-19 Neel Gala + * restructuring the riscv-test-suite to indicate clearly what is deprecated, wip and usable + tests. + * based on the above fixed the directory structure for riscv-targets where-ever applicable. Only + tested riscvOVPsim and spike. + * fixed script bugs for spike as well + * renamed rv32i/I-IO.S to rv32i/I-IO-01.S along with necessary changes to the reference files + and Makefrag + * renamed mbadaddr csr to mtval as raised in issue #31 + * C.SWSP-01.S test updated to fix issue #37 + + 2020-03-18 Neel Gala + * fixed doc/README.adoc with correct version to pass the sanity-check in the doc/Makefile + + 2020-02-07 Prashanth Mundkur + * Support F extension on RV32 sail-riscv-c. + + 2019-12-01 Allen Baum + * modified macro names to conformn to riscof naming convention of model specific vs. pre-defined + * add more complete list of macros, their uses, parameters, and whether they are required or optional + * minor structural changes (moving sentences, renumbering) and typo fixes + * clarified impact of debug macros + * clarified how SIGUPD and BASEUPD must be used + * remove section about test taxonomy, binary tests, emulated ops + * clarify/fix boundary between test target and framework responsibilities + (split test target into test target and test shell) + * remove To Be discussed items that have been discussed + * remove default case condition; if conditions are unchanged, part of same case + * minor grammatical changes related to the above + + 2019-10-16 Allen Baum + * spec/TestFormatSpec.adoc: changed the format of the signature to fixed physical address size, fixed 32b data size extracted from COMPLIANCE_DATA_BEGIN/END range. + + * more gramatical fixes, clarifications added + * added To Be Discussed items regarding emulated instruction and binary tests + + 2019-09-11 Allen Baum + * spec/TestFormatSpec.adoc: more grammar and typo corrections and changes + clarified and added To Be Discussed issues + + 2019-09-11 Allen Baum + * spec/TestFormatSpec.adoc: many grammar and typo corrections and changes + removed many "to Be Discussed items and made them official + Added wording to clarify spec intent (work in progress/goal rather than final) + Added macros to ease test authoring: RVTEST_SIGBASE, RVTEST_SIGUPDATE, RVTEST_CASE + Added detail on proposals for connection to framework (how framework selects tests). + Expanded definition of signature format + Changed the (proposed) directory structure and naming convention to eliminate ambiguities, add consistancy and slightly better match existing structure + Added many "future work" items related to the above + Added examples and comments to code examples to indicate how proposed macros would be used + * .gitignore: added condition to ignore Mac file system artifacts + + + 2019-11-05 Lee Moore + * Restructured RV32I to move Zicsr and Zifencei into their own suites + + 2019-10-14 Lee Moore + * Added Ability to run a single test by using the Make Variable RISCV_TEST + for example, to only run the test I-ADD-01 from the rv32i suite + make RISCV_ISA=rv32i RISCV_TEST=I-ADD-01 + * Added Top Level Variable to Makefile RISCV_TARGET_FLAGS, + in the case of the RISCV_TARGET this can be passed and appended to the invocation + commandline configuration, for example to pass a command line flag to the RISCV_TARGET + to perform tracing. The value of this flag will be target specific + make RISCV_ISA=rv32i RISCV_TEST=I-ADD-01 RISCV_TARGET_FLAGS="--trace" + This is has also been added to all other targets to allow target configuration from + the commandline + + 2019-10-07 Philipp Wagner + * When executing the test suite, Ibex always writes an instruction + log. Update the Makefile to write it to a test-specific location + (next to all other log files). + * On Ibex, provide an additional .objdump-noalias disassembly file + with no aliases and numeric register names (instead of ABI names). + This file matches the Ibex trace and can be used to debug the test + runs. + + 2019-08-29 Robert Balas + * Added support for using RI5CY as a target. + * Added subdirectory riscv-target/ri5cy + + 2019-08-08 Lee Moore + * Added support for lowRISC/ibex RTL as a target using Verilator. + In conjunction with Philipp Wagner of lowRISC phw@lowrisc.org + + 2019-07-18 Paul Donahue + * Fix typos/grammar and use correct architectural terms. + + 2019-06-21 Ben Selfridge + * Added support for using the the GRIFT simulator as a target. + * Added subdirectory riscv-target/grift + * updated README.md and doc/README.adoc + + 2019-05-23 Prashanth Mundkur + * Added support and instructions for using the C and OCaml simulators from the Sail RISC-V formal model as targets. + * added subdirectories riscv-target/sail-riscv-c and riscv-target/sail-riscv-ocaml + * updated README.md and doc/README.adoc + + 2019-04-05 Allen Baum + * spec/TestFormatSpec.adoc: Adding details, minor corrections, ToBeDiscussed + items and clarifications to the specification of the future compliance test + suite. Also removing restrictions on having absolate addresses in signature + + 2019-02-21 Lee Moore + * Fixed bug in RVTEST_IO_ASSERT_GPR_EQ which was not preserving register t0 + * Corrected commit I-LUI-01.S, register target changed but missed assertion + + 2019-02-21 Deborah Soung + * added RiscvFormalSpec as a target with its own unique environment + + 2019-02-15 Radek Hajek + * updated rv32i tests to support all registers (x31) with assertions + * updated spec/TestFormatSpec.adoc example ISA test with new assertions + + 2019-02-05 Deborah Soung + * [Issue #33] fixing rv32si/ma_fetch.S test + * [Issue #32] fixing breakpoint test + + 2019-02-01 Lee Moore + * updated Infrastructure macros to support non-volatile registers + * updated riscvOVPsim + + 2019-01-29 Deborah Soung + * Added Rocket Chip generated cores as a target + * riscv-target/rocket/compliance_io.h created + * riscv-target/rocket/compliance_test.h created + * riscv-target/rocket/*/Makefile.include created for existing test suites + * README.adoc updated with instructions for using Rocket cores as targets + + 2019-01-22 Premysl Vaclavik + * feature: initial version of Compliance Test Format Specification + * This new document outlines how we should like the compliance + system to work going forward. By contrast the doc/README.adoc file + describes the current system as it is. + * Approved at Compliance TG meeting of 9 Jan 2019. + + 2019-01-02 Radek Hajek + * unified macros in all compliance tests + + 2018-12-20 Lee Moore + * fixed riscvOVPsim + + 2018-11-22 Simon Davidmann + * added information on test suite status + + 2018-11-21 Olof Kindgren + * Added support for using external target directories with $TARGETDIR + + 2018-11-21 Neel Gala + * riscv-test-suite/rv_/references/_.reference_output: changed signature + format for all tests to include only 4-bytes per line starting with the + most significant byte on the left. + * riscv-target/spike/device/rv_/Makefile.include: Added a patch for + spike-device Makefiles where the old-signature format is post-processed + to generate a signature in the new format at the end of each test. + * riscv-target/riscvOVPsim/device/rv_/Makefile.include: same patch as above. + * Makefile: default target for Makefile is now to run all tests supported by + the target mentioned defined by RISCV_TARGET variable. + + 2018-10-11 Simon Davidmann + * Ported github riscv/riscv-tests for RV32 processors to this compliance env + * rv32ua rv32uc rv32ud rv32uf rv32ud rv32ui + + 2018-09-10 Lee Moore + * Added tests to RV32I to improve coverage, usage of Imperas Mutating Fault Simulator to + identify untested usage cases + * Macro renames to support GPR, (S)FPR, (D)FPR + * Added test suite RV32IM to test 32 bit Multiply and Divide instructions + * Added test suite RV32IMC to test 32 bit Compressed instructions + * Added test suite RV64I to test 64 bit Integer instructions + * Added test suite RV64IM to test 64 bit Multiply and Divide instructions + + + 2018-06-15 Radek Hajek + + Modifications to support Codasip simulator. + + The simulator is renamed as Codasip-simulator (was + Codasip-IA-simulator), compliance_test.h has been moved to target + directories and a COMPILE_TARGET has been added to Makefile to + allow use of LLVM. + + * Makefile: Include Codasip simulator target. + * riscv-target/codasip-IA-simulator/compliance_io.h: Renamed as + riscv-target/Codasip-simulator/compliance_io.h. + * riscv-target/Codasip-simulator/compliance_io.h: Renamed from + riscv-target/codasip-IA-simulator/compliance_io. + * riscv-target/Codasip-simulator/compliance_test.h: Created. + * riscv-target/codasip-IA-simulator/device/rv32i/Makefile.include: + Renamed as + riscv-target/Codasip-simulator/device/rv32i/Makefile.include + * riscv-target/Codasip-simulator/device/rv32i/Makefile.include: + Renamed from + riscv-target/codasip-IA-simulator/device/rv32i/Makefile.include. + * riscv-test-env/compliance_test.h: Renamed as + riscv-target/riscvOVPsim/compliance_test.h. + * riscv-target/riscvOVPsim/compliance_test.h: Renamed from + riscv-test-env/compliance_test.h. + * riscv-target/riscvOVPsim/device/rv32i/Makefile.include: Updated + for new environment. + * riscv-target/spike/compliance_test.h: Created. + * riscv-target/spike/device/rv32i/Makefile.include: Updated for + new environment. + * riscv-test-suite/rv32i/Makefile: Likewise. + + 2018-06-10 Jeremy Bennett + + Put placeholders in empty directories to make sure they show in + the GitHub hierarchy. + + * riscv-test-suite/rv32i/.gitignore: Created. + * riscv-test-suite/rv32m/.gitignore: Created. + + 2018-06-10 Jeremy Bennett + + * README.md: Make references to files in the repo into links. + + 2018-06-09 Jeremy Bennett + + * .gitignore: Ignore editor backup files. + + 2018-06-09 Jeremy Bennett + + * README.md: Add better link to documentation README.md. + + 2018-06-08 Jeremy Bennett + + * README.md: Move AsciiDoc details into new README.md in the doc + directory. + + 2018-06-08 Jeremy Bennett + + * README.md: Fix typo in link to AsciiDoc cheat sheet + + 2018-06-08 Jeremy Bennett + + * COPYING.BSD: Created. + * COPYING.CC: Created. + * README.md: Add git process, licensing and engineering process. + + 2018-06-08 Jeremy Bennett + + * README.md: Correct details for running the compliance tests and + directory for OVPsim. + + 2018-06-08 Jeremy Bennett + + Clean restructuring to just the work of interest. + + * thought-experiments: Directory removed. + * .gitignore: Merged with TestStructure/.gitignore + * Makefile: Renamed from TestStructure/Makefile. + * TestStructure/Makefile: Renamed as Makefile. + * README.md: Merged with TestStructure/README.md. + * TestStructure/.gitignore: Deleted and contents moved into + .gitignore. + * TestStructure/README.md: Deleted and contents moved into + README.md. + * TestStructure/doc: Directory deleted. + * TestStructure/riscv-target: Directory moved to riscv-target. + * riscv-target: Directory moved from TestStructure/riscv-target + * TestStructure/riscv-test-env: Directory moved to riscv-test-env. + * riscv-test-env: Directory moved from + TestStructure/riscv-test-env. + * TestStructure/riscv-test-suite: Directory moved to + riscv-test-suite. + * riscv-test-suite: Directory moved from + TestStructure/riscv-test-suite. + * thought-experiments: Directory deleted. + + 2018-05-21 Jeremy Bennett + + Initial commit to populate the repository. + + * ChangeLog: Created. + * README.md: Created. diff --git a/tests/wally-riscv-arch-test/CONTRIBUTION.md b/tests/wally-riscv-arch-test/CONTRIBUTION.md new file mode 100644 index 000000000..01f4424c7 --- /dev/null +++ b/tests/wally-riscv-arch-test/CONTRIBUTION.md @@ -0,0 +1,66 @@ +# Contributing to RISC-V Architecture Tests + +Your inputs are welcome and greatly appreciated! We want to make contributing to this project as easy and transparent as possible, whether it's: + +- Reporting a bug +- Discussing the current state of the code +- Submitting a fix +- Proposing new features +- Becoming a maintainer + +## We develop with Github +We use github to host code, to track issues and feature requests, as well as accept pull requests. + +## We use a simple git flow where all code changes happen through Pull Requests + +Pull requests are the best way to propose changes to the codebase. We actively welcome your pull requests: + +1. Fork the repo and create your branch from `master`. +2. If you have added new tests, please ensure they adhere to the latest TestFormatSpec and that you have run them on the RVI approved reference + models (if support in those models is available). +3. If you have updated any test-macros make sure to update the documentation as well. +4. If you have updated the docs, ensure that they render correctly in the respective format. +5. Make sure to create an entry in the CHANGELOG.md. Please refer to the section on versioning below + to choose an appropriate version number. +6. Ensure the existing tests are not broken and still pass on the the RVI approved reference models. +7. Please include a comment with the SPDX license identifier in all source files, for example: + ``` + // SPDX-License-Identifier: BSD-3-Clause + ``` +8. Issue that pull request! + +## Versioning + +When issuing pull requests, an entry in the CHANGELOG.md is mandatory. The arch-test-repo adheres to +the [`Semantic Versioning`](https://semver.org/spec/v2.0.0.html) scheme. Following guidelines must +be followed while assigning a new version number : + +- Patch-updates: all doc updates (like typos, more clarification,etc) and updates to unratified extensions. +- Minor-updates: Updates to ratified extensions OR migration of extensions to ratified OR changes in docs regarding policies or spec. +- Major-updates: Changes to the framework flow (backward compatible or incompatible). + +Note: You can have either a patch or minor or major update. +Note: In case of a conflict, the maintainers will decide the final version to be assigned. + +## Any contributions you make will be under the permissive open-source License +In short, when you submit code changes, your submissions are understood to be under a permissive open source license like BSD-3, Apache-2.0 and CC, etc that covers the project. Feel free to contact the maintainers if that's a concern. + +## Report bugs using Github's [issues](https://github.com/riscv/riscv-arch-test/issues) +We use GitHub issues to track public bugs. Report a bug by [opening a new issue](https://github.com/riscv/riscv-arch-test/issues/new); it's that easy! + +## Write bug reports with detail, background, and sample code + +**Great Bug Reports** tend to have: + +- A quick summary and/or background +- Steps to reproduce + - Be specific! + - Give sample code if you can. +- What you expected would happen +- What actually happens +- Notes (possibly including why you think this might be happening, or stuff you tried that didn't work) + +## License +By contributing, you agree that your contributions will be licensed under its permissive open source +licenses. + diff --git a/tests/wally-riscv-arch-test/COPYING.APACHE b/tests/wally-riscv-arch-test/COPYING.APACHE new file mode 100644 index 000000000..d64569567 --- /dev/null +++ b/tests/wally-riscv-arch-test/COPYING.APACHE @@ -0,0 +1,202 @@ + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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do \ + $(MAKE) $(JOBS) RISCV_TARGET=$(RISCV_TARGET) RISCV_TARGET_FLAGS="$(RISCV_TARGET_FLAGS)" RISCV_DEVICE=$$isa variant; \ + rc=$$?; \ + if [ $$rc -ne 0 ]; then \ + exit $$rc; \ + fi \ + done + +build: compile +run: simulate +clean_all: clean + +compile: + $(MAKE) $(JOBS) \ + RISCV_TARGET=$(RISCV_TARGET) \ + RISCV_DEVICE=$(RISCV_DEVICE) \ + compile -C $(SUITEDIR) + +simulate: + $(MAKE) $(JOBS) \ + RISCV_TARGET=$(RISCV_TARGET) \ + RISCV_DEVICE=$(RISCV_DEVICE) \ + run -C $(SUITEDIR) + +verify: simulate + riscv-test-env/verify.sh + +postverify: +ifeq ($(wildcard $(TARGETDIR)/$(RISCV_TARGET)/postverify.sh),) + $(info No post verify script found $(TARGETDIR)/$(RISCV_TARGET)/postverify.sh) +else + $(TARGETDIR)/$(RISCV_TARGET)/postverify.sh +endif + +clean: + $(MAKE) $(JOBS) \ + RISCV_TARGET=$(RISCV_TARGET) \ + RISCV_DEVICE=$(RISCV_DEVICE) \ + clean -C $(SUITEDIR) + +help: + @echo "RISC-V Architectural Tests" + @echo "" + @echo " Makefile Environment Variables to be set per Target" + @echo " -- TARGETDIR=''" + @echo " -- XLEN=''" + @echo " -- RISCV_TARGET=''" + @echo " -- RISCV_TARGET_FLAGS=''" + @echo " -- RISCV_DEVICE='$(RISCV_ISA_OPT)' [ leave empty to run all devices ]" + @echo " -- RISCV_TEST=' + * README.adoc: Documentation for rocket chip as target. + +2019-02-05 Deborah Soung + * README.adoc: Update documentation for rocket chip as target (fixed rv32si/ma_fetch.S). + * README.adoc: Update documentation for rocket chip as target (fixed breakpoint.S). + +2019-01-29 Deborah Soung + * README.adoc: Documentation for rocket chip as target. + +2018-11-21 Olof Kindgren + + * README.adoc (Repository structure) Added documentation for the $TARGETDIR environmental variable + +2018-11-21 Neel Gala + * README.adoc: Added new signature format spec. + +2018-06-18 Jeremy Bennett + + * README.adoc (Future work): Reflect changes made to support + Codasip simulator. + (Repository structure): Diagrammatic representation of the file + structure deleted. + +2018-06-12 Jeremy Bennett + + * .gitignore: Add custom.dict. + +2018-06-12 Jeremy Bennett + + Document issue 1.8 Draft. + + * README.adoc (Introduction): Add Future work section and bump + version. + * custom.wordlist: Add words needed for Future work section. + +2018-06-12 Jeremy Bennett + + * README.adoc: Remove special apostrophe from "licensor's". + * custom.wordlist: Updated with more words to be ignored. + +2018-06-12 Jeremy Bennett + + * README-old.md: Deleted. + * README.adoc: Include details of how to contribute and installing + the tools from the old README and reference the licence as an + appendix. + +2018-06-11 Jeremy Bennett + + This makes the document appear directly as the README of the doc + directory, so there is now no longer a need to publish to GitHub + pages. + + * .gitignore: Change name of files ignored. + * Makefile: Remove publish target. + * README.adoc: Symbolic link removed and replaced by design.adoc, + to which the CC license text has been added. + * design.adoc: Renamed as README.adoc. + * publish.sh: Deleted. + +2018-06-11 Jeremy Bennett + + * README.md: Previous version moved to README-old.md for the time + being. + * README.adoc: Created as symbolic link to design.adoc. + +2018-06-10 Jeremy Bennett + + * README.md: Note about make publish. + * design.adoc (Overall structure): Make list or instruction sets + and extensions compact representation. + +2018-06-10 Jeremy Bennett + + * publish.sh: Only publish from clean and committed master branch + to avoid difficult use of git stash. + +2018-06-10 Jeremy Bennett + + * publish.sh: Don't rely on doc directory being available on + gh-pages branch. + +2018-06-10 Jeremy Bennett + + * publish.sh: Make executable and correctly set top level + repository directory. + +2018-06-10 Jeremy Bennett + + Add a mechanism to make the latest documentation available via + GitHub pages. This means that design.html is no longer part of + the master branch, but is published by copying to index.html on + the gh-pages branch. + + * .gitignore: Ignore design.html. + * Makefile: Add publish target and delete design.html when cleaning. + * README.md: Link to GitHub pages for latest documentation. + * design.adoc: Deal with AsciiDoc apparent bug with consecutive + comment blogs. + * design.html: Deleted. + * publish.sh: Created. + +2018-06-10 Jeremy Bennett + + * README.md: Fix link to generated documentation. + * design.html: Regenerated. + +2018-06-09 Jeremy Bennett + + * Makefile: Add sanity check for version number and spell target. + * design.adoc: Fix trivial typo. + * design.html: Regenerated. + +2018-06-09 Jeremy Bennett + + * .gitignore: Don't ignore .html or .xml + * README.md: Note location of old documentation, give link to HTML + and explain how to contribute. + * custom.wordlist: Created. + * design.adoc: Cleaned up from top to bottom and spell checked. + * design.html: Generated. + +2018-06-08 Jeremy Bennett + + * Makefile: Clean up and add license header. + * README.md: Created. + * design.adoc: Add licensing and SPDX license identifier. + * legacy.adoc: Deleted. + +2018-06-04 Jeremy Bennett + + This is the first version of the document taken from Simon + Davidmann's MS Word document. The main document is design.adoc, + legacy material, currently just appendices C and D has been moved + to legacy.adoc. + + design.adoc is correct AsciiDoc. legacy.adoc is just a raw dump, + which needs cleaning up. + + The next step will be restructuring design.adoc as agreed. + + * .gitignore: Created. + * ChangeLog: Created. + * Makefile: Created. + * design.adoc: Created. + * legacy.adoc: Created. diff --git a/tests/wally-riscv-arch-test/doc/MIGRATION.adoc b/tests/wally-riscv-arch-test/doc/MIGRATION.adoc new file mode 100644 index 000000000..d9801c661 --- /dev/null +++ b/tests/wally-riscv-arch-test/doc/MIGRATION.adoc @@ -0,0 +1,88 @@ += Migration guide +:toc: +:icons: font +:numbered: +:source-highlighter: rouge + +This document serves as a guide to users of the architectural suite to migrate their targets from an +older version to a newer version with minimal changes. This guide thus provides a patch scheme to get +the previous versions of the targets up and running with the new versions of the framework. + +However, users are strongly encouraged to completely migrate to the newer versions, as and when +available, and avoid using these patches. + +== Migration from v0.1 to v0.2 + +This section will describe the changes required to transition your targets ported on v0.1 to v0.2 +framework. For examples please see: `riscv-target/riscvOVPsim_0p1` and `riscv-target/spike_0p1`. + +=== Change header filename + +In version v0.1 the target specific assembly macros were split across two files: `compliance_test.h` +and `compliance_io.h`. In version v0.2 these macros are to merged into a single file named +`model_test.h`. The following commands can the achieve the above: + +---- +mv compliance_test.h model_test.h +cat compliance_io.h >> model_test.h +rm compliance_io.h +---- + +=== Change device directory structure + +In version v0.1 a target would have one or multiple of the directories defined to indicate supported +extensions: `rv32i`, `rv32im`, `rv32imc`, `rv32Zicsr` and `rv32Zifencei`. In version v0.2 the +directories of the extensions have changed in order to provide more consistency and less ambiguity. + +For version v0.2, the `device` directory first needs to have either a `rv32i_m` directory to indicate +that the target is a 32-bit machine. The extension directories, as supported by the target, are +now to be created in each of these directories using the following mapping scheme: + +. device/rv32i -> device/rv32i_m/I +. device/rv32im -> device/rv32i_m/M +. device/rv32imc -> device/rv32i_m/C +. device/rv32Zicsr -> device/rv32i_m/privilege +. device/rv32Zifencei -> device/rv32i_m/Zifencei + +The contents of the extension directories need not change, unless there are dependencies on the path +of the directory itself. The following commands will achieve the above: + +---- +cd device +mkdir rv32i_m +mv rv32i rv32i_m/I +mv rv32im rv32i_m/M +mv rv32imc rv32i_m/C +mv rv32Zicsr rv32i_m/privilege +mv rv32Zifencei rv32i_m/Zifencei +---- + +=== Changes in target macro names. + +Since some of the macros from the old framework have been re-purposed in the new v0.2 framework, +there will be name conflicts rendering the old ones useless. In order to retain the old macros, they +have been renamed with a post-fix `_OLD`. The macros that have been renamed are given below: + +. `RVTEST_CODE_BEGIN` -> `RVTEST_CODE_BEGIN_OLD` +. `RVTEST_CODE_END` -> `RVTEST_CODE_END_OLD` +. `RVTEST_DATA_BEGIN` -> `RVTEST_DATA_BEGIN_OLD` +. `RVTEST_DATA_END` -> `RVTEST_DATA_END_OLD` + +The user is thus required to make the above changes in the new `model_test.h` that was created +as part of this migration. The following commands will help achieve the above: + +---- +sed -i 's/RVTEST_CODE_BEGIN/RVTEST_CODE_BEGIN_OLD/g' model_test.h +sed -i 's/RVTEST_CODE_END/RVTEST_CODE_END_OLD/g' model_test.h +sed -i 's/RVTEST_DATA_BEGIN/RVTEST_DATA_BEGIN_OLD/g' model_test.h +sed -i 's/RVTEST_DATA_END/RVTEST_DATA_END_OLD/g' model_test.h + +---- + +note:: the RVTEST_DATA_END in v0.1 enforced a 16-byte alignment before the signature end. This +constraint has been removed. + +=== Changes in device Makefile.include files + +No changes required. + diff --git a/tests/wally-riscv-arch-test/doc/Makefile b/tests/wally-riscv-arch-test/doc/Makefile new file mode 100644 index 000000000..697d89cdc --- /dev/null +++ b/tests/wally-riscv-arch-test/doc/Makefile @@ -0,0 +1,82 @@ +# Makefile for RISC-V Architectural Test SIG documentation + +# This file is part of the RISC-V Foundation Architectural Test SIG +# tool set and documentation. + +# Copyright (C) 2017 CodaSip Limited +# Copyright (C) 2018 Embecosm Limited . +# Copyright (C) 2018 Imperas Limited + +# All rights reserved. + +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: + +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# 3. Neither the name of mosquitto nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. + +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. + +# SPDX-License-Identifier: BSD-3-Clause + +ROOT = README +SRC = $(ROOT).adoc +SRC_STRIPPED = $(ROOT)-stripped.adoc + +.PHONY: all +all: pdf html + +.PHONY: pdf +pdf: $(ROOT).pdf + +$(ROOT).pdf: sanity-check $(SRC) + asciidoctor-pdf -d article $(SRC) + +.PHONY: html +html: $(ROOT).html + +$(ROOT).html: sanity-check $(SRC) + asciidoctor -d article -b html $(SRC) + +# It is all too easy for the document history and title page to have diverging +# version numbers. This target checks first. + +.PHONY: sanity-check +sanity-check: + @s=$$(sed -n < $(SRC) -e '3s/Issue //p') ; \ + t=$$(sed -n < $(SRC) -e "/== Document history/,/^$$/p" | \ + grep -c "$${s}") ; \ + if [ $${t} -ne 1 ] ; \ + then \ + echo "Version number of title and document history do not match" ; \ + exit 1 ; \ + fi + +custom.dict: custom.wordlist + aspell --lang=en create master ./$@ < $< + +.PHONY: spell +spell: custom.dict $(SRC) + sed < $(SRC) > $(SRC_STRIPPED) -e 's/`[^`]\+`//gp' -e '/^----$$/,/^----$$/d' + aspell --master=en_US --mode=none --add-extra-dicts=./custom.dict \ + -c $(SRC_STRIPPED) + $(RM) $(SRC_STRIPPED) + +clean: + rm -f $(ROOT)-stripped.adoc $(ROOT).pdf $(ROOT).html custom.dict diff --git a/tests/wally-riscv-arch-test/doc/README.adoc b/tests/wally-riscv-arch-test/doc/README.adoc new file mode 100644 index 000000000..fa7129b39 --- /dev/null +++ b/tests/wally-riscv-arch-test/doc/README.adoc @@ -0,0 +1,460 @@ += RISC-V Architectural Testing Framework = +RISC-V Foundation Architecture Test SIG +Issue 1.16 Draft +:toc: +:icons: font +:numbered: +:source-highlighter: rouge + +//// +SPDX-License-Identifier: CC-BY-4.0 + +Document conventions: +- one line per paragraph (don't fill lines - this makes changes clearer) +- Wikipedia heading conventions (First word only capitalized) +- US spelling throughout. +- Run "make spell" before committing changes. +- Build the HTML and commit it with any changed source. +- Do not commit the PDF! +//// + +== Introduction +=== About + +This document describes the RISC-V Architectural Testing framework which is used to test if a RISC-V device's has understood and implemented the specifications correctly + +* It explains the framework around the tests, the running of individual tests, and the suites of tests. + +* It explains how to set up targets to run the tests. + +This document is made freely available under a <>. + +=== Intent of the architectural test suite + +The RISC-V Architectural Tests are an evolving set of tests that are created to help ensure that software written for a given RISC-V Profile/Specification will run on all implementations that comply with that profile. + +These tests also help ensure that the implementer has both understood and implemented the specification correctly. + +The RISC-V Architectural Test suite is a minimal filter. Passing the tests and having the results approved by RISC-V International is a prerequisite to licensing the RISC-V trademarks in connection with the design. Passing the RISC-V Architectural Tests does not mean that the design complies with the RISC-V Architecture. These are only a basic set of tests checking important aspects of the specification without focusing on details. + +The RISC-V Architectural Tests are not a substitute for rigorous design verification. + +The result that the architecture tests provide to the user is an assurance that the specification has been interpreted correctly and the implementation under test (DUT) can be declared as RISC-V Architecture Test compliant. + +=== Intended audience + +This document is intended for design and verification engineers who wish to check if their RISC-V implementation (simulation models, HDL models, etc.) is compliant to the RISC-V specification. + +For those who wish to develop new architectural tests and/or to write or adapt their own test framework are suggested to read the link:../spec/TestFormatSpec.adoc[`Test Format Spec`]. + + +=== Contribute + +You are encouraged to contribute to this repository (including changes to this document) by submitting pull requests and by commenting on pull requests submitted by other people as described in the link:../README.md[`README.md`] file in the top level directory. + +While submitting a pull request note that some directories use `ChangeLog` files to track changes in the code and documentation. Please honor these, keeping them up to date and including the ChangeLog entry in the _git_ commit message. + +Make sure to also include a comment with the SPDX license identifier in all source files, for example: +``` +// SPDX-License-Identifier: BSD-3-Clause +``` + +NOTE: Don't forget to add your own name to the list of contributors in the document. + +== Licensing + +In general: + +* code is licensed under the BSD 3-clause license (SPDX license identifier `BSD-3-Clause`); +* documentation is licensed under the Creative Commons Attribution 4.0 International license (SPDX license identifier `CC-BY-4.0`). + +The files link:../COPYING.BSD[`COPYING.BSD`] and link:../COPYING.CC[`COPYING.CC`] in the top level directory contain the complete text of these licenses. + +NOTE: The riscv-ovpsim simulator is licensed under an Imperas license. There is no dependency on this and it is included as a convenience to users. + + +==== AsciiDoc + +This is a structured text format used by this document. Simple usage should be fairly self evident. + +* Comprehensive information on the format is on the http://www.methods.co.nz/asciidoc/[AsciiDoc website]. + +* Comprehensive information on the tooling on the https://asciidoctor.org/[AsciiDoctor website]. + +* You may find this https://asciidoctor.org/docs/asciidoc-syntax-quick-reference/[cheat sheet] helpful. + +==== Installing tools + +To generate the documentation as HTML you need _asciidoctor_ and to generate as +PDF you need _asciidoctor-pdf_. + +* These are the https://asciidoctor.org/docs/install-toolchain/[installation instructions for asciidoctor]. + +* These are the https://asciidoctor.org/docs/asciidoctor-pdf/#install-the-published-gem[installation instructions for asciidoctor-pdf]. + +To spell check you need _aspell_ installed. + +==== Building the documentation + +To build HTML: +[source,make] +---- +make html +---- + +To build PDF: +[source,make] +---- +make pdf +---- + +To build both: +[source,make] +---- +make +---- + +To check the spelling (excludes any listing or code phrases): +[source,make] +---- +make spell +---- + +Any custom words for spell checking should be added to link:./custom.wordlist[`custom.wordlist`]. + +=== Contributors + +This document has been created by the following people (in alphabetical order of surname). + +* Jeremy Bennett +* Mary Bennett +* Simon Davidmann +* Neel Gala +* Radek Hajek +* Lee Moore +* Milan Nostersky +* Marcela Zachariasova + +=== Document history +[cols="<1,<2,<3,<4",options="header,pagewidth",] +|================================================================================ +| _Revision_ | _Date_ | _Author_ | _Modification_ +| 1.16 Draft | 23 September 2020 | Neel Gala| Changed Compliance to Architecture/Architectural. Refined the steps to port a new target. Removed simulator and target specific docs. Added vocabulary from the Test Format Specification +| 1.15 Draft | 14 March 2019 | +Prashanth Mundkur | + +Added support and instructions for using the C and OCaml simulators from the Sail RISC-V formal model as targets. +| 1.14 Draft | 21 February 2019 | +Deborah Soung | + +Documented how to use SiFive's RISC-V ISA Formal Specification model as a target. +| 1.13 Draft | 29 January 2019 | +Deborah Soung | + +Added documentation on how to use Rocket Chip generated cores as targets. +| 1.12 Draft | 22 November 2018 | +Simon Davidmann | + +Updated notes on Test Suites. +| 1.11 Draft | 21 November 2018 | +Neel Gala | + +Added new signature format specs . +| 1.10 Draft | 20 June 2018 | + +Simon Davidmann, Lee Moore | + +Cleaned up description of updated framework and inclusion of riscvOVPsim. + +| 1.9 Draft | 12 June 2018 | + +Jeremy Bennett | + +Update Future work section to take account of Codasip changes. Remove diagrammatic directory structure. + +| 1.8 Draft | 12 June 2018 | + +Jeremy Bennett | + +Add Future work section. + +| 1.7 Draft | 12 June 2018 | + +Jeremy Bennett | + +Add CC license as an appendix. + +| 1.6 Draft | 10 June 2018 | + +Jeremy Bennett | + +Tidy up areas that are flawed in HTML version. + +| 1.5 Draft | 8 June 2018 | + +Jeremy Bennett | + +General tidy up. + +| 1.4 Draft | 8 June 2018 | + +Jeremy Bennett | + +Added license preamble. + +| 1.3 Draft | 5 June 2018 | + +Simon Davidmann | + +Updated to reflect directory structure and trace macros. + +| 1.2 Draft | 3 June 2018 | + +Jeremy Bennett | + +Converted to AsciiDoc, cleaned up and restructured. + +| 1.1 Draft | 1 June 2018 | + +Simon Davidmann +Lee Moore | + +Revised format and expand to describe framework, usage of many tests groups, +and different Targets + +|1.0 | 24 December 2017 | + +Radek Hajek +Milan Nostersky +Marcela Zachariasova | + +First version of the document. + +|================================================================================ + +== Repository structure + +The top level directory contains : + + - a `README.md` file providing high-level details about the RISC-V Architecture Testing Framework. + - top level `Makefile` for running the tests on a RISC-V implementation. + - `ChangeLog` for logging changes with respect to code. + - complete license files for the Creative Commons and BSD licenses used by the task group. + +There are then five top level directories. + +`doc`:: All the documentation for the project, written using _AsciiDoc_. + +`coverage`:: This directory contains a sub-directory structure similar to the `riscv-test-suite` directory. The coverage reports of each test-suite are available in the corresponding directories. The reports are available in the html and yaml formats. The directory also contains multiple coverpoint YAMLs which capture all the coverpoints of interest which are covered by all the tests in the `riscv-test-suite` directory. + +`riscv-target`:: Contains a further subdirectory for each target, within which are placed the `model_test.h` header for that target and a `device` directory for all the devices of that target. If the `$TARGETDIR` environment variable is set to another directory, the scripts will search this directory for targets instead. + +`riscv-test-env`:: This contains the `verify.sh` script which checks if the signatures generated the riscv-target device match the statically hosted reference signatures at the end of simulation. The directory also contains symbolic-links to the `arch_test.h` and `encoding.h` files present in the `riscv-test-suite/env` directory. + +`riscv-test-suite`:: This contains a further `env` subdirectory which contains the `arch_test.h` and the `encoding.h` file which includes common assembly macros and routines which is used across the tests in the suite. Further directories are present which contain the actual architectural tests. The names and structure of these directories is based on the link:../test-pool structure guideline highlighted above. + +`riscv-ovpsim`:: This contains a README pointing to the Imperas OVP riscvOVPsim simulator for use in architectural testing. + +== Vocabulary +=== The architectural test + +At the heart of the testing infrastructure is the detailed <> available as `.S` assembly files. The specification and format of the tests is defined in the link:./TestFormatSpec.adoc[`Test Format Specification`]. + +=== The architectural test pool + +The <> are grouped into different functional test suites targeting the different subsets of the RISC-V specification. For more details on the test-pool structure, hierarchy and conventions please refer to the link:./TestFormatSpec.adoc[`Test Format Specification`]. + +For information on the currently supported different test suites, look here: link:../riscv-test-suite/README.md[../riscv-test-suite/README.md] + +=== The test signature + +Each test in the <> generates a <>, which represents the data written into specific memory locations during the execution of the test. The signature typically will record values (or sanitised values) of the operations carried out in the test. More details on the format and nature of the signatures is available in the link:./TestFormatSpec.adoc[`Test Format Specification`] + +=== The reference signature + +In order to claim that a device/implementation has passed the RISC-V Architecture Tests, the <> obtained from the execution of the tests on the implementation need to be compared against a set of _golden_ <>. These reference signatures are currently generated by the link:https://github.com/rems-project/sail-riscv[`RISC-V SAIL`] formal model and statically hosted in the repository for each test. + +=== The test target +The <> can be either a RISC-V Instruction Set Simulator (ISS), a RISC-V emulator, a RISC-V RTL model running on an HDL simulator, a RISC-V FPGA implementation or a physical chip. Each of the target types offers specific features and represents specific interface challenges. It is a role of the <> to handle different targets while using the same <> as a test source. + +=== The target shell +The <> is the software and hardware environment around the <> that enables it to communicate with the framework, including assembling and linking tests, loading tests into memory, executing tests, and extracting the signature. The input to the <> is a .S <> file, and the output is a <>. + + +== Porting a new target + + +In this section, a short tutorial on how to add a user target to the RISC-V Architectural Test Framework is provided. + +The following steps demonstrate an example in which a target was replaced by the RISCV-ISA-SIM +(a.k.a Spike). In a similar way, any RISC-V ISA simulator or any RTL simulation model of the +RISC-V processor can be ported as a potential target for testing. + +=== Setup environment variables + +NOTE: `ROOTDIR` will always point to the riscv-arch-test repo. + +1. Clone the repository: + + --- + git clone https://github.com/riscv/riscv-arch-test.git + cd riscv-arch-test + + --- + +2. Open the `Makefile.include` available in the root folder of the repository and edit the following +variables based on your target: + + a. `TARGETDIR` : set `TARGETDIR` to point to the directory which contains a sub-folder in the same name + as the target. For example, the arch-test repo includes the targets: sail-riscv-c and spike + under the `riscv-target` folder, in which case we set the `TARGETDIR` to riscv-target as shown + below. One can set this completely arbitrary paths as suitable by the user. + + + --- + export TARGETDIR ?= $(ROOTDIR)/riscv-target + + --- + + b. `XLEN`: set XLEN to max supported XLEN. Allowed values are 32 and 64. + + --- + export XLEN ?= 64 + + --- + +c. `RISCV_TARGET`: set this variable to the name of the target. A folder of the same name must exist in +the `TARGETDIR` directory + + --- + export RISCV_TARGET ?= spike + + --- + +d. `RISCV_DEVICE`: set the `RISCV_DEVICE` environment to the extension you want to compile, simulate and verify. Leave +this blank if you want to iterate through all the supported extensions of the target. Allowed values +are the individual names of the extensions supported by your target like: I, M, C or Zifencei, etc. Multiple extensions are not be provided. + + --- + export RISCV_DEVICE ?= + + --- + +e. `RISCV_TARGET_FLAGS`: set this to a string which needs to be passed to your target's Makefile.include files + + --- + export RISCV_TARGET_FLAGS ?= + + --- + +f. `RISCV_ASSERT`: set this if you want to enable assertions on the test-suites. **Currently no tests use assertions.** + + --- + export RISCV_ASSERT ?= 0 + + --- + +g. `JOBS`: set the number of parallel jobs (along with any other arguments) you would like to +execute. Note that the target needs to be coded in such a way to support parallel execution. Some +targets use common intermediate files, rather than unique files, which makes them unsuitable for +parallel execution, these targets will need to be re-coded. + + --- + JOBS= -j1 + + --- + +3. Now inside your `TARGETDIR/RISCV_TARGET` directory you will need to create the following files: + +a. `model_test.h`: A header file containing the definition of the various target specific +assembly macros that are required to compile and simulate the tests. The list and definition of the +required target specific macros is available in the link:../spec/TestFormatSpec.adoc[Test Format +Specification] + +b. `link.ld`: A linker script to compile the tests for your target. + +c. Any other files required by the target (configuration scripts, logs, etc.) can also be placed in +this directory. + +4. Inside the `TARGETDIR/RISCV_TARGET` directory create a new folder named: `device`. If your device +is a 32-bit target then create a directory `device/rv32i_m`. If your device is a 64-bit target then +create a directory `device/rv64i_m`. If your target is configurable on the `XLEN` parameter then +both the folders need to be created. + +5. Within the `rv32i_m`/`rv64i_m` directories sub-folders in the name of the extensions supported +by the target need to be created. For eg. A target supporting the ISA RV32IMC_Zifence will have the +following directory structure: + + --- + - rv32i_m/I + - rv32i_m/M + - rv32i_m/C + - rv32i_m/privilege + - rv32i_m/Zifencei + + --- + +6. Each of the above extension directories will now need to include a file: `Makefile.include` which +defines the following Makefile variables: + +a. `RUN_TARGET`:: This variable needs to include commands and steps to execute an ELF on target device. Note here that this variable should include all the necessary steps and arguments to run that specific test-suite. For example, in case of spike for the `rv32i_m/C` test-suite the corresponding `Makefile.include` has the `--isa=rv32ic` argument as opposed to just `--isa=rv32i` for the base `rv32i_m/I` test-suite. This variable should also include other steps to extract and sanitize the signature file as well for each test. The only argument available to this variable is the compiled `elf` file. + +b. `COMPILE_TARGET`:: This variable should include the commands and steps required to compile an assembly test for the target for each extension mentioned above. Note, currently only the GCC compiler is supported. This compiler takes `march` and `mabi` arguments from the corresponding architectural suite framework. `COMPILE_TARGET` will more or less be the same across test-suites. The only argument available to `COMPILE_TARGET` is the assembly file of one architectural test. + +The following figure depicts the final directory structure of a target device that should get created at the end of the above steps: + +[#img-testStruct] +.File Structure of the Target directory +image::./file-struct.jpg[TargetStruct] + + +=== Generating Signature + +As previously mentioned the execution of each test on the target must generate a signature file. The name of the signature file should be ``. The signature file should follow the guidelines mentioned in the link:../spec/TestFormatSpec.adoc[`Test Format Specification`]. + +In case of spike, we have ensured that the signature region is bounded by the labels: `begin_signature` and `end_signature`. This is enforced in the `RVMODEL_DATA_BEGIN` and `RVMODEL_DATA_END` macros defined in the `riscv-target/spike/model_test.h` file. Additionally, if you look closely at the `RUN_TARGET` variable defined in the `Makefile.include` files of the spike target, it includes a few bash commands to sanitize the signature produced from spike. This is done to conform the final signature file to the specification defined in the link:../spec/TestFormatSpec.adoc[`Test Format Specification`]. + +=== Compile, simulate and verify the tests + +Once you have ported your target to the riscv-arch-test framework by following the above steps, you +are now ready to compile, simulate and verify the tests on your target + +If you would like to compile, simulate and verify all the extension tests applicable to your target +simply run `make` from the `ROOTDIR`. + +NOTE: For the above to work the `RISCV_DEVICE` in `ROOTDIR/Makefile.include` must be left empty. + +If you would like to only compile the tests for a particular extension you can use the following +command. + + make RISCV_DEVICE=M compile + make RISCV_DEVICE=C compile + +The arguments to the `RISCV_DEVICE` variable must be the extensions supported by the target. +NOTE: If `RISCV_DEVICE` is not defined/empty it will default to the `I` extension which is necessary +for all targets. + +To simulate the compiled tests on your target: + + make RISCV_DEVICE=M simulate + make RISCV_DEVICE=Zifencei simulate + +NOTE: If `RISCV_DEVICE` is not defined/empty it will default to the `I` extension which is necessary +for all targets. + +To verify if the generated signatures match the corresponding reference signatures. + + make RISCV_DEVICE=M verify + +NOTE: If `RISCV_DEVICE` is not defined/empty it will default to the `I` extension which is necessary +for all targets. + +All the above steps create and modify files in the `work` directory created in `ROOTDIR` folder. To +clean the `workdir` simple run : + + make clean + +By default the working directory is set to `ROOTDIR/work`. This can be overwritten by assigning a +new working directory path via the command line. Note, the path must be absolute and not relative : + + make WORK=/home/me/my_path/mywork clean compile simulate diff --git a/tests/wally-riscv-arch-test/doc/custom.wordlist b/tests/wally-riscv-arch-test/doc/custom.wordlist new file mode 100644 index 000000000..2efdc5925 --- /dev/null +++ b/tests/wally-riscv-arch-test/doc/custom.wordlist @@ -0,0 +1,73 @@ +AsciiDoc +asciidoc +AsciiDoctor +asciidoctor +aspell +autotools +CGEN +cmake +Codasip +creativecommons +CY +Davidmann +discoverable +DUT +EF +enforceability +FPGA +GDB +Generis +github +Hajek +HDL +http +https +IC +ies +immunities +Imperas +io +IM +ISA +legalcode +licensor +licensors +licensor's +LLVM +makefile +makefiles +Marcela +md +merchantability +Nostersky +nz +pagewidth +parameterization +pdf +publicdomain +Radek +README +riscv +riscvOVPsim +RTL +rv +RVTEST +SiFive +spdx +src +subdirectory +sublicensable +synched +tbd +testbench +toc +toolchain +TVM +URI +Verilator +Verilog +waivable +WIPO +wordlist +www +Zachariasova diff --git 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+1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the Regents nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, +SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING +OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS +BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED +HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE +MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. diff --git a/tests/wally-riscv-arch-test/riscv-test-env/arch_test.h b/tests/wally-riscv-arch-test/riscv-test-env/arch_test.h new file mode 120000 index 000000000..c1b8c50bc --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-env/arch_test.h @@ -0,0 +1 @@ +../riscv-test-suite/env/arch_test.h \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-env/encoding.h b/tests/wally-riscv-arch-test/riscv-test-env/encoding.h new file mode 120000 index 000000000..fd1833f03 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-env/encoding.h @@ -0,0 +1 @@ +../riscv-test-suite/env/encoding.h \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-env/p/link.ld b/tests/wally-riscv-arch-test/riscv-test-env/p/link.ld new file mode 100644 index 000000000..392e74f9e --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-env/p/link.ld @@ -0,0 +1,22 @@ +OUTPUT_ARCH( "riscv" ) +ENTRY(_start) + +SECTIONS +{ + . = 0x00000000; + .text.trap : { *(.text.trap) } + + . = 0x80000000; + .text.init : { *(.text.init) } + + . = ALIGN(0x1000); + .tohost : { *(.tohost) } + . = ALIGN(0x1000); + .text : { *(.text) } + . = ALIGN(0x1000); + .data : { *(.data) } + .data.string : { *(.data.string)} + .bss : { *(.bss) } + _end = .; +} + diff --git a/tests/wally-riscv-arch-test/riscv-test-env/p/riscv_test.h b/tests/wally-riscv-arch-test/riscv-test-env/p/riscv_test.h new file mode 100644 index 000000000..e452261c4 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-env/p/riscv_test.h @@ -0,0 +1,251 @@ +// See LICENSE for license details. + +#ifndef _ENV_PHYSICAL_SINGLE_CORE_H +#define _ENV_PHYSICAL_SINGLE_CORE_H + +#include "../encoding.h" + +//----------------------------------------------------------------------- +// Begin Macro +//----------------------------------------------------------------------- + +#define RVTEST_RV64U \ + .macro init; \ + .endm + +#define RVTEST_RV64UF \ + .macro init; \ + RVTEST_FP_ENABLE; \ + .endm + +#define RVTEST_RV32U \ + .macro init; \ + .endm + +#define RVTEST_RV32UF \ + .macro init; \ + RVTEST_FP_ENABLE; \ + .endm + +#define RVTEST_RV64M \ + .macro init; \ + RVTEST_ENABLE_MACHINE; \ + .endm + +#define RVTEST_RV64S \ + .macro init; \ + RVTEST_ENABLE_SUPERVISOR; \ + .endm + +#define RVTEST_RV32M \ + .macro init; \ + RVTEST_ENABLE_MACHINE; \ + .endm + +#define RVTEST_RV32S \ + .macro init; \ + RVTEST_ENABLE_SUPERVISOR; \ + .endm + +#if __riscv_xlen == 64 +# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bgez a0, 1f; RVTEST_PASS; 1: +#else +# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1: +#endif + +#define INIT_PMP \ + la t0, 1f; \ + csrw mtvec, t0; \ + li t0, -1; /* Set up a PMP to permit all accesses */ \ + csrw pmpaddr0, t0; \ + li t0, PMP_NAPOT | PMP_R | PMP_W | PMP_X; \ + csrw pmpcfg0, t0; \ + .align 2; \ +1: + +#define INIT_SATP \ + la t0, 1f; \ + csrw mtvec, t0; \ + csrwi satp, 0; \ + .align 2; \ +1: + +#define DELEGATE_NO_TRAPS \ + la t0, 1f; \ + csrw mtvec, t0; \ + csrwi medeleg, 0; \ + csrwi mideleg, 0; \ + csrwi mie, 0; \ + .align 2; \ +1: + +#define RVTEST_ENABLE_SUPERVISOR \ + li a0, MSTATUS_MPP & (MSTATUS_MPP >> 1); \ + csrs mstatus, a0; \ + li a0, SIP_SSIP | SIP_STIP; \ + csrs mideleg, a0; \ + +#define RVTEST_ENABLE_MACHINE \ + li a0, MSTATUS_MPP; \ + csrs mstatus, a0; \ + +#define RVTEST_FP_ENABLE \ + li a0, MSTATUS_FS & (MSTATUS_FS >> 1); \ + csrs mstatus, a0; \ + csrwi fcsr, 0 + +#define RISCV_MULTICORE_DISABLE \ + csrr a0, mhartid; \ + 1: bnez a0, 1b + +#define EXTRA_TVEC_USER +#define EXTRA_TVEC_MACHINE +#define EXTRA_INIT +#define EXTRA_INIT_TIMER + +// +// undefine some unusable CSR Accesses if no PRIV Mode present +// +#if defined(PRIV_MISA_S) +# if (PRIV_MISA_S==0) +# undef INIT_SATP +# define INIT_SATP +# undef INIT_PMP +# define INIT_PMP +# undef DELEGATE_NO_TRAPS +# define DELEGATE_NO_TRAPS +# undef RVTEST_ENABLE_SUPERVISOR +# define RVTEST_ENABLE_SUPERVISOR +# endif +#endif +#if defined(PRIV_MISA_U) +# if (PRIV_MISA_U==0) +# endif +#endif +#if defined(TRAPHANDLER) +#include TRAPHANDLER +#endif + +#define INTERRUPT_HANDLER j other_exception /* No interrupts should occur */ + +#define RVTEST_CODE_BEGIN_OLD \ + .section .text.init; \ + .align 6; \ + .weak stvec_handler; \ + .weak mtvec_handler; \ + .globl _start; \ +_start: \ + /* reset vector */ \ + j reset_vector; \ + .align 2; \ +trap_vector: \ + /* test whether the test came from pass/fail */ \ + csrr t5, mcause; \ + li t6, CAUSE_USER_ECALL; \ + beq t5, t6, write_tohost; \ + li t6, CAUSE_SUPERVISOR_ECALL; \ + beq t5, t6, write_tohost; \ + li t6, CAUSE_MACHINE_ECALL; \ + beq t5, t6, write_tohost; \ + /* if an mtvec_handler is defined, jump to it */ \ + la t5, mtvec_handler; \ + beqz t5, 1f; \ + jr t5; \ + /* was it an interrupt or an exception? */ \ + 1: csrr t5, mcause; \ + bgez t5, handle_exception; \ + INTERRUPT_HANDLER; \ +handle_exception: \ + /* we don't know how to handle whatever the exception was */ \ + other_exception: \ + /* some unhandlable exception occurred */ \ + 1: ori TESTNUM, TESTNUM, 1337; \ + write_tohost: \ + sw TESTNUM, tohost, t5; \ + j write_tohost; \ +reset_vector: \ + RISCV_MULTICORE_DISABLE; \ + INIT_SATP; \ + INIT_PMP; \ + DELEGATE_NO_TRAPS; \ + li TESTNUM, 0; \ + la t0, trap_vector; \ + csrw mtvec, t0; \ + CHECK_XLEN; \ + /* if an stvec_handler is defined, delegate exceptions to it */ \ + la t0, stvec_handler; \ + beqz t0, 1f; \ + csrw stvec, t0; \ + li t0, (1 << CAUSE_LOAD_PAGE_FAULT) | \ + (1 << CAUSE_STORE_PAGE_FAULT) | \ + (1 << CAUSE_FETCH_PAGE_FAULT) | \ + (1 << CAUSE_MISALIGNED_FETCH) | \ + (1 << CAUSE_USER_ECALL) | \ + (1 << CAUSE_BREAKPOINT); \ + csrw medeleg, t0; \ + csrr t1, medeleg; \ + bne t0, t1, other_exception; \ +1: csrwi mstatus, 0; \ + init; \ + EXTRA_INIT; \ + EXTRA_INIT_TIMER; \ + la t0, 1f; \ + csrw mepc, t0; \ + csrr a0, mhartid; \ + mret; \ +1: \ +begin_testcode: + + +//----------------------------------------------------------------------- +// End Macro +//----------------------------------------------------------------------- + +#define RVTEST_CODE_END_OLD \ +end_testcode: \ + ecall; + +//----------------------------------------------------------------------- +// Pass/Fail Macro +//----------------------------------------------------------------------- +#define RVTEST_SYNC fence +//#define RVTEST_SYNC nop + +#define RVTEST_PASS \ + RVTEST_SYNC; \ + li TESTNUM, 1; \ + SWSIG (0, TESTNUM); \ + ecall + +#define TESTNUM gp +#define RVTEST_FAIL \ + RVTEST_SYNC; \ +1: beqz TESTNUM, 1b; \ + sll TESTNUM, TESTNUM, 1; \ + or TESTNUM, TESTNUM, 1; \ + SWSIG (0, TESTNUM); \ + la x1, end_testcode; \ + jr x1; + +//----------------------------------------------------------------------- +// Data Section Macro +//----------------------------------------------------------------------- + +#define EXTRA_DATA + +#define RVTEST_DATA_BEGIN_OLD \ + .align 4; .global begin_signature; begin_signature: + +#define RVTEST_DATA_END_OLD \ + .align 4; .global end_signature; end_signature: \ + EXTRA_DATA \ + .pushsection .tohost,"aw",@progbits; \ + .align 8; .global tohost; tohost: .dword 0; \ + .align 8; .global fromhost; fromhost: .dword 0; \ + .popsection; \ + .align 8; .global begin_regstate; begin_regstate: \ + .word 128; \ + .align 8; .global end_regstate; end_regstate: \ + .word 4; + +#endif diff --git a/tests/wally-riscv-arch-test/riscv-test-env/pm/link.ld b/tests/wally-riscv-arch-test/riscv-test-env/pm/link.ld new file mode 100644 index 000000000..b3e315e78 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-env/pm/link.ld @@ -0,0 +1,17 @@ +OUTPUT_ARCH( "riscv" ) +ENTRY(_start) + +SECTIONS +{ + . = 0x80000000; + .text.init : { *(.text.init) } + . = ALIGN(0x1000); + .tohost : { *(.tohost) } + . = ALIGN(0x1000); + .text : { *(.text) } + . = ALIGN(0x1000); + .data : { *(.data) } + .bss : { *(.bss) } + _end = .; +} + diff --git a/tests/wally-riscv-arch-test/riscv-test-env/pm/riscv_test.h b/tests/wally-riscv-arch-test/riscv-test-env/pm/riscv_test.h new file mode 100644 index 000000000..38a0e86b8 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-env/pm/riscv_test.h @@ -0,0 +1,11 @@ +// See LICENSE for license details. + +#ifndef _ENV_PHYSICAL_MULTI_CORE_H +#define _ENV_PHYSICAL_MULTI_CORE_H + +#include "../p/riscv_test.h" + +#undef RISCV_MULTICORE_DISABLE +#define RISCV_MULTICORE_DISABLE + +#endif diff --git a/tests/wally-riscv-arch-test/riscv-test-env/pt/link.ld b/tests/wally-riscv-arch-test/riscv-test-env/pt/link.ld new file mode 100644 index 000000000..b3e315e78 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-env/pt/link.ld @@ -0,0 +1,17 @@ +OUTPUT_ARCH( "riscv" ) +ENTRY(_start) + +SECTIONS +{ + . = 0x80000000; + .text.init : { *(.text.init) } + . = ALIGN(0x1000); + .tohost : { *(.tohost) } + . = ALIGN(0x1000); + .text : { *(.text) } + . = ALIGN(0x1000); + .data : { *(.data) } + .bss : { *(.bss) } + _end = .; +} + diff --git a/tests/wally-riscv-arch-test/riscv-test-env/pt/riscv_test.h b/tests/wally-riscv-arch-test/riscv-test-env/pt/riscv_test.h new file mode 100644 index 000000000..34c2a331a --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-env/pt/riscv_test.h @@ -0,0 +1,69 @@ +// See LICENSE for license details. + +#ifndef _ENV_PHYSICAL_SINGLE_CORE_TIMER_H +#define _ENV_PHYSICAL_SINGLE_CORE_TIMER_H + +#include "../p/riscv_test.h" + +#define TIMER_INTERVAL 2 + +#undef EXTRA_INIT_TIMER +#define EXTRA_INIT_TIMER \ + li a0, MIP_MTIP; \ + csrs mie, a0; \ + csrr a0, mtime; \ + addi a0, a0, TIMER_INTERVAL; \ + csrw mtimecmp, a0; \ + +#if SSTATUS_XS != 0x18000 +# error +#endif +#define XS_SHIFT 15 + +#undef INTERRUPT_HANDLER +#define INTERRUPT_HANDLER \ + slli t5, t5, 1; \ + srli t5, t5, 1; \ + add t5, t5, -IRQ_M_TIMER; \ + bnez t5, other_exception; /* other interrups shouldn't happen */\ + csrr t5, mtime; \ + addi t5, t5, TIMER_INTERVAL; \ + csrw mtimecmp, t5; \ + mret; \ + +//----------------------------------------------------------------------- +// Data Section Macro +//----------------------------------------------------------------------- + +#undef EXTRA_DATA +#define EXTRA_DATA \ + .align 3; \ +regspill: \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ + .dword 0xdeadbeefcafebabe; \ +evac: \ + .skip 32768; \ + +#endif diff --git a/tests/wally-riscv-arch-test/riscv-test-env/v/entry.S b/tests/wally-riscv-arch-test/riscv-test-env/v/entry.S new file mode 100644 index 000000000..97196620f --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-env/v/entry.S @@ -0,0 +1,125 @@ +#include "riscv_test.h" + +#if __riscv_xlen == 64 +# define STORE sd +# define LOAD ld +# define REGBYTES 8 +#else +# define STORE sw +# define LOAD lw +# define REGBYTES 4 +#endif + +#define STACK_TOP (_end + 4096) + + .section ".text.init","ax",@progbits + .globl _start +_start: + j handle_reset + + /* NMI vector */ +nmi_vector: + j wtf + +trap_vector: + j wtf + +handle_reset: + la t0, trap_vector + csrw mtvec, t0 + la sp, STACK_TOP - SIZEOF_TRAPFRAME_T + csrr t0, mhartid + slli t0, t0, 12 + add sp, sp, t0 + csrw mscratch, sp + la a0, userstart + j vm_boot + + .globl pop_tf +pop_tf: + LOAD t0,33*REGBYTES(a0) + csrw sepc,t0 + LOAD x1,1*REGBYTES(a0) + LOAD x2,2*REGBYTES(a0) + LOAD x3,3*REGBYTES(a0) + LOAD x4,4*REGBYTES(a0) + LOAD x5,5*REGBYTES(a0) + LOAD x6,6*REGBYTES(a0) + LOAD x7,7*REGBYTES(a0) + LOAD x8,8*REGBYTES(a0) + LOAD x9,9*REGBYTES(a0) + LOAD x11,11*REGBYTES(a0) + LOAD x12,12*REGBYTES(a0) + LOAD x13,13*REGBYTES(a0) + LOAD x14,14*REGBYTES(a0) + LOAD x15,15*REGBYTES(a0) + LOAD x16,16*REGBYTES(a0) + LOAD x17,17*REGBYTES(a0) + LOAD x18,18*REGBYTES(a0) + LOAD x19,19*REGBYTES(a0) + LOAD x20,20*REGBYTES(a0) + LOAD x21,21*REGBYTES(a0) + LOAD x22,22*REGBYTES(a0) + LOAD x23,23*REGBYTES(a0) + LOAD x24,24*REGBYTES(a0) + LOAD x25,25*REGBYTES(a0) + LOAD x26,26*REGBYTES(a0) + LOAD x27,27*REGBYTES(a0) + LOAD x28,28*REGBYTES(a0) + LOAD x29,29*REGBYTES(a0) + LOAD x30,30*REGBYTES(a0) + LOAD x31,31*REGBYTES(a0) + LOAD a0,10*REGBYTES(a0) + sret + + .global trap_entry +trap_entry: + csrrw sp, sscratch, sp + + # save gprs + STORE x1,1*REGBYTES(sp) + STORE x3,3*REGBYTES(sp) + STORE x4,4*REGBYTES(sp) + STORE x5,5*REGBYTES(sp) + STORE x6,6*REGBYTES(sp) + STORE x7,7*REGBYTES(sp) + STORE x8,8*REGBYTES(sp) + STORE x9,9*REGBYTES(sp) + STORE x10,10*REGBYTES(sp) + STORE x11,11*REGBYTES(sp) + STORE x12,12*REGBYTES(sp) + STORE x13,13*REGBYTES(sp) + STORE x14,14*REGBYTES(sp) + STORE x15,15*REGBYTES(sp) + STORE x16,16*REGBYTES(sp) + STORE x17,17*REGBYTES(sp) + STORE x18,18*REGBYTES(sp) + STORE x19,19*REGBYTES(sp) + STORE x20,20*REGBYTES(sp) + STORE x21,21*REGBYTES(sp) + STORE x22,22*REGBYTES(sp) + STORE x23,23*REGBYTES(sp) + STORE x24,24*REGBYTES(sp) + STORE x25,25*REGBYTES(sp) + STORE x26,26*REGBYTES(sp) + STORE x27,27*REGBYTES(sp) + STORE x28,28*REGBYTES(sp) + STORE x29,29*REGBYTES(sp) + STORE x30,30*REGBYTES(sp) + STORE x31,31*REGBYTES(sp) + + csrrw t0,sscratch,sp + STORE t0,2*REGBYTES(sp) + + # get sr, epc, badvaddr, cause + csrr t0,sstatus + STORE t0,32*REGBYTES(sp) + csrr t0,sepc + STORE t0,33*REGBYTES(sp) + csrr t0,sbadaddr + STORE t0,34*REGBYTES(sp) + csrr t0,scause + STORE t0,35*REGBYTES(sp) + + move a0, sp + j handle_trap diff --git a/tests/wally-riscv-arch-test/riscv-test-env/v/link.ld b/tests/wally-riscv-arch-test/riscv-test-env/v/link.ld new file mode 100644 index 000000000..b3e315e78 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-env/v/link.ld @@ -0,0 +1,17 @@ +OUTPUT_ARCH( "riscv" ) +ENTRY(_start) + +SECTIONS +{ + . = 0x80000000; + .text.init : { *(.text.init) } + . = ALIGN(0x1000); + .tohost : { *(.tohost) } + . = ALIGN(0x1000); + .text : { *(.text) } + . = ALIGN(0x1000); + .data : { *(.data) } + .bss : { *(.bss) } + _end = .; +} + diff --git a/tests/wally-riscv-arch-test/riscv-test-env/v/riscv_test.h b/tests/wally-riscv-arch-test/riscv-test-env/v/riscv_test.h new file mode 100644 index 000000000..8ca9ffd76 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-env/v/riscv_test.h @@ -0,0 +1,71 @@ +// See LICENSE for license details. + +#ifndef _ENV_VIRTUAL_SINGLE_CORE_H +#define _ENV_VIRTUAL_SINGLE_CORE_H + +#include "../p/riscv_test.h" + +//----------------------------------------------------------------------- +// Begin Macro +//----------------------------------------------------------------------- + +#undef RVTEST_FP_ENABLE +#define RVTEST_FP_ENABLE fssr x0 + +#undef RVTEST_CODE_BEGIN +#define RVTEST_CODE_BEGIN \ + .text; \ + .global userstart; \ +userstart: \ + init + +//----------------------------------------------------------------------- +// Pass/Fail Macro +//----------------------------------------------------------------------- + +#undef RVTEST_PASS +#define RVTEST_PASS li a0, 1; scall + +#undef RVTEST_FAIL +#define RVTEST_FAIL sll a0, TESTNUM, 1; 1:beqz a0, 1b; or a0, a0, 1; scall; + +//----------------------------------------------------------------------- +// Data Section Macro +//----------------------------------------------------------------------- + +#undef RVTEST_DATA_END +#define RVTEST_DATA_END + +//----------------------------------------------------------------------- +// Supervisor mode definitions and macros +//----------------------------------------------------------------------- + +#define MAX_TEST_PAGES 63 // this must be the period of the LFSR below +#define LFSR_NEXT(x) (((((x)^((x)>>1)) & 1) << 5) | ((x) >> 1)) + +#define PGSHIFT 12 +#define PGSIZE (1UL << PGSHIFT) + +#define SIZEOF_TRAPFRAME_T ((__riscv_xlen / 8) * 36) + +#ifndef __ASSEMBLER__ + +typedef unsigned long pte_t; +#define LEVELS (sizeof(pte_t) == sizeof(uint64_t) ? 3 : 2) +#define PTIDXBITS (PGSHIFT - (sizeof(pte_t) == 8 ? 3 : 2)) +#define VPN_BITS (PTIDXBITS * LEVELS) +#define VA_BITS (VPN_BITS + PGSHIFT) +#define PTES_PER_PT (1UL << RISCV_PGLEVEL_BITS) +#define MEGAPAGE_SIZE (PTES_PER_PT * PGSIZE) + +typedef struct +{ + long gpr[32]; + long sr; + long epc; + long badvaddr; + long cause; +} trapframe_t; +#endif + +#endif diff --git a/tests/wally-riscv-arch-test/riscv-test-env/v/string.c b/tests/wally-riscv-arch-test/riscv-test-env/v/string.c new file mode 100644 index 000000000..4ffedc0a4 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-env/v/string.c @@ -0,0 +1,114 @@ +#include +#include +#include + +void* memcpy(void* dest, const void* src, size_t len) +{ + if ((((uintptr_t)dest | (uintptr_t)src | len) & (sizeof(uintptr_t)-1)) == 0) { + const uintptr_t* s = src; + uintptr_t *d = dest; + while (d < (uintptr_t*)(dest + len)) + *d++ = *s++; + } else { + const char* s = src; + char *d = dest; + while (d < (char*)(dest + len)) + *d++ = *s++; + } + return dest; +} + +void* memset(void* dest, int byte, size_t len) +{ + if ((((uintptr_t)dest | len) & (sizeof(uintptr_t)-1)) == 0) { + uintptr_t word = byte & 0xFF; + word |= word << 8; + word |= word << 16; + word |= word << 16 << 16; + + uintptr_t *d = dest; + while (d < (uintptr_t*)(dest + len)) + *d++ = word; + } else { + char *d = dest; + while (d < (char*)(dest + len)) + *d++ = byte; + } + return dest; +} + +size_t strlen(const char *s) +{ + const char *p = s; + while (*p) + p++; + return p - s; +} + +int strcmp(const char* s1, const char* s2) +{ + unsigned char c1, c2; + + do { + c1 = *s1++; + c2 = *s2++; + } while (c1 != 0 && c1 == c2); + + return c1 - c2; +} + +int memcmp(const void* s1, const void* s2, size_t n) +{ + if ((((uintptr_t)s1 | (uintptr_t)s2) & (sizeof(uintptr_t)-1)) == 0) { + const uintptr_t* u1 = s1; + const uintptr_t* u2 = s2; + const uintptr_t* end = u1 + (n / sizeof(uintptr_t)); + while (u1 < end) { + if (*u1 != *u2) + break; + u1++; + u2++; + } + n -= (const void*)u1 - s1; + s1 = u1; + s2 = u2; + } + + while (n--) { + unsigned char c1 = *(const unsigned char*)s1++; + unsigned char c2 = *(const unsigned char*)s2++; + if (c1 != c2) + return c1 - c2; + } + + return 0; +} + +char* strcpy(char* dest, const char* src) +{ + char* d = dest; + while ((*d++ = *src++)) + ; + return dest; +} + +long atol(const char* str) +{ + long res = 0; + int sign = 0; + + while (*str == ' ') + str++; + + if (*str == '-' || *str == '+') { + sign = *str == '-'; + str++; + } + + while (*str) { + res *= 10; + res += *str++ - '0'; + } + + return sign ? -res : res; +} diff --git a/tests/wally-riscv-arch-test/riscv-test-env/v/vm.c b/tests/wally-riscv-arch-test/riscv-test-env/v/vm.c new file mode 100644 index 000000000..8064b7baf --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-env/v/vm.c @@ -0,0 +1,273 @@ +// See LICENSE for license details. + +#include +#include +#include + +#include "riscv_test.h" + +void trap_entry(); +void pop_tf(trapframe_t*); + +volatile uint64_t tohost; +volatile uint64_t fromhost; + +static void do_tohost(uint64_t tohost_value) +{ + while (tohost) + fromhost = 0; + tohost = tohost_value; +} + +#define pa2kva(pa) ((void*)(pa) - DRAM_BASE - MEGAPAGE_SIZE) +#define uva2kva(pa) ((void*)(pa) - MEGAPAGE_SIZE) + +#define flush_page(addr) asm volatile ("sfence.vma %0" : : "r" (addr) : "memory") + +static uint64_t lfsr63(uint64_t x) +{ + uint64_t bit = (x ^ (x >> 1)) & 1; + return (x >> 1) | (bit << 62); +} + +static void cputchar(int x) +{ + do_tohost(0x0101000000000000 | (unsigned char)x); +} + +static void cputstring(const char* s) +{ + while (*s) + cputchar(*s++); +} + +static void terminate(int code) +{ + do_tohost(code); + while (1); +} + +void wtf() +{ + terminate(841); +} + +#define stringify1(x) #x +#define stringify(x) stringify1(x) +#define assert(x) do { \ + if (x) break; \ + cputstring("Assertion failed: " stringify(x) "\n"); \ + terminate(3); \ +} while(0) + +#define l1pt pt[0] +#define user_l2pt pt[1] +#if __riscv_xlen == 64 +# define NPT 4 +#define kernel_l2pt pt[2] +# define user_l3pt pt[3] +#else +# define NPT 2 +# define user_l3pt user_l2pt +#endif +pte_t pt[NPT][PTES_PER_PT] __attribute__((aligned(PGSIZE))); + +typedef struct { pte_t addr; void* next; } freelist_t; + +freelist_t user_mapping[MAX_TEST_PAGES]; +freelist_t freelist_nodes[MAX_TEST_PAGES]; +freelist_t *freelist_head, *freelist_tail; + +void printhex(uint64_t x) +{ + char str[17]; + for (int i = 0; i < 16; i++) + { + str[15-i] = (x & 0xF) + ((x & 0xF) < 10 ? '0' : 'a'-10); + x >>= 4; + } + str[16] = 0; + + cputstring(str); +} + +static void evict(unsigned long addr) +{ + assert(addr >= PGSIZE && addr < MAX_TEST_PAGES * PGSIZE); + addr = addr/PGSIZE*PGSIZE; + + freelist_t* node = &user_mapping[addr/PGSIZE]; + if (node->addr) + { + // check accessed and dirty bits + assert(user_l3pt[addr/PGSIZE] & PTE_A); + uintptr_t sstatus = set_csr(sstatus, SSTATUS_SUM); + if (memcmp((void*)addr, uva2kva(addr), PGSIZE)) { + assert(user_l3pt[addr/PGSIZE] & PTE_D); + memcpy((void*)addr, uva2kva(addr), PGSIZE); + } + write_csr(sstatus, sstatus); + + user_mapping[addr/PGSIZE].addr = 0; + + if (freelist_tail == 0) + freelist_head = freelist_tail = node; + else + { + freelist_tail->next = node; + freelist_tail = node; + } + } +} + +void handle_fault(uintptr_t addr, uintptr_t cause) +{ + assert(addr >= PGSIZE && addr < MAX_TEST_PAGES * PGSIZE); + addr = addr/PGSIZE*PGSIZE; + + if (user_l3pt[addr/PGSIZE]) { + if (!(user_l3pt[addr/PGSIZE] & PTE_A)) { + user_l3pt[addr/PGSIZE] |= PTE_A; + } else { + assert(!(user_l3pt[addr/PGSIZE] & PTE_D) && cause == CAUSE_STORE_PAGE_FAULT); + user_l3pt[addr/PGSIZE] |= PTE_D; + } + flush_page(addr); + return; + } + + freelist_t* node = freelist_head; + assert(node); + freelist_head = node->next; + if (freelist_head == freelist_tail) + freelist_tail = 0; + + uintptr_t new_pte = (node->addr >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_W | PTE_X; + user_l3pt[addr/PGSIZE] = new_pte | PTE_A | PTE_D; + flush_page(addr); + + assert(user_mapping[addr/PGSIZE].addr == 0); + user_mapping[addr/PGSIZE] = *node; + + uintptr_t sstatus = set_csr(sstatus, SSTATUS_SUM); + memcpy((void*)addr, uva2kva(addr), PGSIZE); + write_csr(sstatus, sstatus); + + user_l3pt[addr/PGSIZE] = new_pte; + flush_page(addr); + + __builtin___clear_cache(0,0); +} + +void handle_trap(trapframe_t* tf) +{ + if (tf->cause == CAUSE_USER_ECALL) + { + int n = tf->gpr[10]; + + for (long i = 1; i < MAX_TEST_PAGES; i++) + evict(i*PGSIZE); + + terminate(n); + } + else if (tf->cause == CAUSE_ILLEGAL_INSTRUCTION) + { + assert(tf->epc % 4 == 0); + + int* fssr; + asm ("jal %0, 1f; fssr x0; 1:" : "=r"(fssr)); + + if (*(int*)tf->epc == *fssr) + terminate(1); // FP test on non-FP hardware. "succeed." + else + assert(!"illegal instruction"); + tf->epc += 4; + } + else if (tf->cause == CAUSE_FETCH_PAGE_FAULT || tf->cause == CAUSE_LOAD_PAGE_FAULT || tf->cause == CAUSE_STORE_PAGE_FAULT) + handle_fault(tf->badvaddr, tf->cause); + else + assert(!"unexpected exception"); + + pop_tf(tf); +} + +static void coherence_torture() +{ + // cause coherence misses without affecting program semantics + unsigned int random = ENTROPY; + while (1) { + uintptr_t paddr = DRAM_BASE + ((random % (2 * (MAX_TEST_PAGES + 1) * PGSIZE)) & -4); +#ifdef __riscv_atomic + if (random & 1) // perform a no-op write + asm volatile ("amoadd.w zero, zero, (%0)" :: "r"(paddr)); + else // perform a read +#endif + asm volatile ("lw zero, (%0)" :: "r"(paddr)); + random = lfsr63(random); + } +} + +void vm_boot(uintptr_t test_addr) +{ + unsigned int random = ENTROPY; + if (read_csr(mhartid) > 0) + coherence_torture(); + + _Static_assert(SIZEOF_TRAPFRAME_T == sizeof(trapframe_t), "???"); + +#if (MAX_TEST_PAGES > PTES_PER_PT) || (DRAM_BASE % MEGAPAGE_SIZE) != 0 +# error +#endif + // map user to lowermost megapage + l1pt[0] = ((pte_t)user_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V; + // map kernel to uppermost megapage +#if __riscv_xlen == 64 + l1pt[PTES_PER_PT-1] = ((pte_t)kernel_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V; + kernel_l2pt[PTES_PER_PT-1] = (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D; + user_l2pt[0] = ((pte_t)user_l3pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V; + uintptr_t vm_choice = SATP_MODE_SV39; +#else + l1pt[PTES_PER_PT-1] = (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D; + uintptr_t vm_choice = SATP_MODE_SV32; +#endif + write_csr(satp, ((uintptr_t)l1pt >> PGSHIFT) | + (vm_choice * (SATP_MODE & ~(SATP_MODE<<1)))); + + // Set up PMPs if present, ignoring illegal instruction trap if not. + uintptr_t pmpc = PMP_NAPOT | PMP_R | PMP_W | PMP_X; + asm volatile ("la t0, 1f\n\t" + "csrrw t0, mtvec, t0\n\t" + "csrw pmpaddr0, %1\n\t" + "csrw pmpcfg0, %0\n\t" + ".align 2\n\t" + "1:" + : : "r" (pmpc), "r" (-1UL) : "t0"); + + // set up supervisor trap handling + write_csr(stvec, pa2kva(trap_entry)); + write_csr(sscratch, pa2kva(read_csr(mscratch))); + write_csr(medeleg, + (1 << CAUSE_USER_ECALL) | + (1 << CAUSE_FETCH_PAGE_FAULT) | + (1 << CAUSE_LOAD_PAGE_FAULT) | + (1 << CAUSE_STORE_PAGE_FAULT)); + // FPU on; accelerator on; allow supervisor access to user memory access + write_csr(mstatus, MSTATUS_FS | MSTATUS_XS); + write_csr(mie, 0); + + random = 1 + (random % MAX_TEST_PAGES); + freelist_head = pa2kva((void*)&freelist_nodes[0]); + freelist_tail = pa2kva(&freelist_nodes[MAX_TEST_PAGES-1]); + for (long i = 0; i < MAX_TEST_PAGES; i++) + { + freelist_nodes[i].addr = DRAM_BASE + (MAX_TEST_PAGES + random)*PGSIZE; + freelist_nodes[i].next = pa2kva(&freelist_nodes[i+1]); + random = LFSR_NEXT(random); + } + freelist_nodes[MAX_TEST_PAGES-1].next = 0; + + trapframe_t tf; + memset(&tf, 0, sizeof(tf)); + tf.epc = test_addr - DRAM_BASE; + pop_tf(&tf); +} diff --git a/tests/wally-riscv-arch-test/riscv-test-env/verify.sh b/tests/wally-riscv-arch-test/riscv-test-env/verify.sh new file mode 100755 index 000000000..f69a4c633 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-env/verify.sh @@ -0,0 +1,68 @@ +#!/bin/bash + +printf "\n\nCompare to reference files ... \n\n"; +FAIL=0 +RUN=0 + +for ref in ${SUITEDIR}/references/*.reference_output; +do + base=$(basename ${ref}) + stub=${base//".reference_output"/} + + if [ "${stub}" = "*" ]; then + echo "No Reference Files ${SUITEDIR}/references/*.reference_output" + break + fi + + sig=${WORK}/rv${XLEN}i_m/${RISCV_DEVICE}/${stub}.signature.output + dif=${WORK}/rv${XLEN}i_m/${RISCV_DEVICE}/${stub}.diff + + RUN=$((${RUN} + 1)) + + # + # Ensure both files exist + # + if [ -f ${ref} ] && [ -f ${sig} ]; then + echo -n "Check $(printf %-24s ${stub}) " + else + echo -e "Check $(printf %-24s ${stub}) \e[33m ... IGNORE \e[39m" + continue + fi + diff --ignore-case --strip-trailing-cr ${ref} ${sig} &> /dev/null + if [ $? == 0 ] + then + echo -e "\e[32m ... OK \e[39m" + else + echo -e "\e[31m ... FAIL \e[39m" + FAIL=$((${FAIL} + 1)) + sdiff ${ref} ${sig} > ${dif} + fi +done + +# warn on missing reverse reference +for sig in ${WORK}/rv${XLEN}i_m/${RISCV_DEVICE}/*.signature.output; +do + base=$(basename ${sig}) + stub=${base//".signature.output"/} + ref=${SUITEDIR}/references/${stub}.reference_output + + if [ -f $sig ] && [ ! -f ${ref} ]; then + echo -e "\e[31m Error: sig ${sig} no corresponding ${ref} \e[39m" + FAIL=$((${FAIL} + 1)) + fi +done + +declare -i status=0 +if [ ${FAIL} == 0 ] +then + echo "--------------------------------" + echo -n -e "\e[32m OK: ${RUN}/${RUN} " + status=0 +else + echo "--------------------------------" + echo -n -e "\e[31m FAIL: ${FAIL}/${RUN} " + status=1 +fi +echo -e "RISCV_TARGET=${RISCV_TARGET} RISCV_DEVICE=${RISCV_DEVICE} XLEN=${XLEN} \e[39m" +echo +exit ${status} diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/Makefile.include b/tests/wally-riscv-arch-test/riscv-test-suite/Makefile.include new file mode 100644 index 000000000..080aa1ee7 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/Makefile.include @@ -0,0 +1,58 @@ +#======================================================================= +# Makefile for riscv-tests/isa +#----------------------------------------------------------------------- + +act_dir := . +src_dir := $(act_dir)/src +work_dir := $(WORK) +work_dir_isa := $(work_dir)/rv$(XLEN)i_m/$(RISCV_DEVICE) + +include $(act_dir)/Makefrag +ifneq ($(RISCV_TEST),) + target_tests = $(RISCV_TEST).elf +endif + +default: all + +#-------------------------------------------------------------------- +# Build rules +#-------------------------------------------------------------------- + +vpath %.S $(act_dir) + +INCLUDE=$(TARGETDIR)/$(RISCV_TARGET)/device/rv$(XLEN)i_m/$(RISCV_DEVICE)/Makefile.include +ifeq ($(wildcard $(INCLUDE)),) + $(error Cannot find '$(INCLUDE)`. Check that RISCV_TARGET and RISCV_DEVICE are set correctly.) +endif +-include $(INCLUDE) + +#------------------------------------------------------------ +# Build and run assembly tests + +%.log: %.elf + $(V) echo "Execute $(@)" + $(V) $(RUN_TARGET) + + +define compile_template + +$(work_dir_isa)/%.elf: $(src_dir)/%.S + $(V) echo "Compile $$(@)" + @mkdir -p $$(@D) + $(V) $(COMPILE_TARGET) + +.PRECIOUS: $(work_dir_isa)/%.elf + +endef + +target_elf = $(foreach e,$(target_tests),$(work_dir_isa)/$(e)) +target_log = $(patsubst %.elf,%.log,$(target_elf)) + +compile: $(target_elf) +run: $(target_log) + +#------------------------------------------------------------ +# Clean up + +clean: + rm -rf $(work_dir) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/README.md b/tests/wally-riscv-arch-test/riscv-test-suite/README.md new file mode 100644 index 000000000..2e585c2f6 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/README.md @@ -0,0 +1,66 @@ +# RISC-V Test Suites + +The tests are grouped based on the different extension subsets of the RISC-V unprivileged ISA. +The tests strictly follow the [Test format](../spec/TestFormatSpec.adoc) specification. + +Directory names postfixed with "\_unratified" indicate that tests for extensions that have not yet +been ratified by RVI. + +The coverage report (in html format) of the tests available in this suite is generated through +[RISCOF](https://github.com/riscv-software-src/riscof) and is available here: [Coverage Report](../riscv-test-stats/coverage/README.md). + +These tests have been generated using the open source Compatibility Test Generator from InCore Semiconductors available +at: [CTG](https://github.com/riscv/riscv-ctg). + +The reference signatures are generated using [SAIL](https://github.com/riscv/sail-riscv) or +[SPIKE](https://github.com/riscv-software-src/riscv-isa-sim). + +Test directories with the "\_unratified" post-fix indicate test-suites for extensions which have not been +ratified (but are stable and near ratification) + +Directory structure +``` + +├── env # contains the architectural test header files +└── rv32i_m # top level folder indicate rv32 tests for machine mode + ├── C # include tests and references for "C" extension + │   ├── references # static references signatures for "C" extension + │   └── src # assembly tests for "C" extension + ├── F # include tests and references for "rv32F" extension + │   ├── references # static references signatures for "rv32F" extension + │   └── src # assembly tests for "rv32F" extension + ├── I # include tests and references for "I" extension + │   ├── references # static references signatures for "I" extension + │   └── src # assembly tests for "I" extension + ├── M # include tests and references for "M" extension + │ ├── references # static references signatures for "M" extension + │ └── src # assembly tests for "M" extension + ├── K_unratified # include tests and references for "K" extension + │ ├── references # static references signatures for "K" extension + │ └── src # assembly tests for "K" extension + ├── privilege # include tests and references for tests which require Privilege Spec + │ ├── references # static references signatures for tests which require Privilege Spec + │ └── src # assembly tests for tests which require Privilege Spec + └── Zifencei # include tests and references for "Zifencei" extension + ├── references # static references signatures for "Zifencei" extension + └── src # assembly tests for "Zifencei" extension +└── rv64i_m # top level folder indicate rv64 tests for machine mode + ├── C # include tests and references for "C" extension + │   ├── references # static references signatures for "C" extension + │   └── src # assembly tests for "C" extension + ├── I # include tests and references for "I" extension + │   ├── references # static references signatures for "I" extension + │   └── src # assembly tests for "I" extension + ├── M # include tests and references for "M" extension + │ ├── references # static references signatures for "M" extension + │ └── src # assembly tests for "M" extension + ├── K_unratified # include tests and references for "K" extension + │ ├── references # static references signatures for "K" extension + │ └── src # assembly tests for "K" extension + ├── privilege # include tests and references for tests which require Privilege Spec + │ ├── references # static references signatures for tests which require Privilege Spec + │ └── src # assembly tests for tests which require Privilege Spec + └── Zifencei # include tests and references for "Zifencei" extension + ├── references # static references signatures for "Zifencei" extension + └── src # assembly tests for "Zifencei" extension +``` diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/env/arch_test.h b/tests/wally-riscv-arch-test/riscv-test-suite/env/arch_test.h new file mode 100644 index 000000000..286a64744 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/env/arch_test.h @@ -0,0 +1,1184 @@ +#include "encoding.h" +// TODO the following should come from the YAML. +#ifndef NUM_SPECD_INTCAUSES + #define NUM_SPECD_INTCAUSES 16 +#endif +//#define RVTEST_FIXED_LEN +#ifndef UNROLLSZ + #define UNROLLSZ 5 +#endif +// #ifndef rvtest_gpr_save +// #define rvtest_gpr_save +// #endif + +#define TEST_CASE_1 + +//----------------------------------------------------------------------- +// RV Arch Test Macros +//----------------------------------------------------------------------- +#ifndef RVMODEL_SET_MSW_INT + #warning "RVMODEL_SET_MSW_INT is not defined by target. Declaring as empty macro" + #define RVMODEL_SET_MSW_INT +#endif + +#ifndef RVMODEL_CLEAR_MSW_INT + #warning "RVMODEL_CLEAR_MSW_INT is not defined by target. Declaring as empty macro" + #define RVMODEL_CLEAR_MSW_INT +#endif + +#ifndef RVMODEL_CLEAR_MTIMER_INT + #warning "RVMODEL_CLEAR_MTIMER_INT is not defined by target. Declaring as empty macro" + #define RVMODEL_CLEAR_MTIMER_INT +#endif + +#ifndef RVMODEL_CLEAR_MEXT_INT + #warning "RVMODEL_CLEAR_MEXT_INT is not defined by target. Declaring as empty macro" + #define RVMODEL_CLEAR_MEXT_INT +#endif + +#ifdef RVTEST_FIXED_LEN + #define LI(reg, val)\ + .option push;\ + .option norvc;\ + .align UNROLLSZ;\ + li reg,val;\ + .align UNROLLSZ;\ + .option pop; + + #define LA(reg, val)\ + .option push;\ + .option norvc;\ + .align UNROLLSZ;\ + la reg,val;\ + .align UNROLLSZ;\ + .option pop; + +#else + #define LI(reg,val);\ + .option push;\ + .option norvc;\ + li reg,val;\ + .option pop; + + #define LA(reg,val);\ + .option push;\ + .option norvc;\ + la reg,val;\ + .option pop; +#endif +#if XLEN==64 + #define SREG sd + #define LREG ld + #define REGWIDTH 8 + #define MASK 0xFFFFFFFFFFFFFFFF + +#else + #if XLEN==32 + #define SREG sw + #define LREG lw + #define REGWIDTH 4 + #define MASK 0xFFFFFFFF + + #endif +#endif + +#if FLEN==64 + #define FLREG fld + #define FSREG fsd + #define FREGWIDTH 8 + +#else + #if FLEN==32 + #define FLREG flw + #define FSREG fsw + #define FREGWIDTH 4 + #endif +#endif + +#if XLEN==64 + #if FLEN==32 + #define SREG sw + #define LREG lW + #define REGWIDTH 4 + #define MASK 0xFFFFFFFF + #endif +#endif + +#define MMODE_SIG 3 +#define RLENG (REGWIDTH<<3) + +#define RVTEST_ISA(_STR) + +#ifndef DATA_REL_TVAL_MSK + #define DATA_REL_TVAL_MSK 0x0F05 << (REGWIDTH*8-16) +#endif + +#ifndef CODE_REL_TVAL_MSK + #define CODE_REL_TVAL_MSK 0xD008 << (REGWIDTH*8-16) +#endif + + +// ----------------------------------- CODE BEGIN w/ TRAP HANDLER START ------------------------ // + +.macro RVTEST_CODE_BEGIN + .align UNROLLSZ + .section .text.init; + .globl rvtest_init; \ + rvtest_init: +#ifdef rvtest_mtrap_routine + LA(x1, rvtest_trap_prolog ); + jalr ra, x1 + rvtest_prolog_done: +#endif + LI (x1, (0xFEEDBEADFEEDBEAD & MASK)); + LI (x2, (0xFF76DF56FF76DF56 & MASK)); + LI (x3, (0x7FBB6FAB7FBB6FAB & MASK)); + LI (x4, (0xBFDDB7D5BFDDB7D5 & MASK)); + LA (x5, rvtest_code_begin); + LA (x6, rvtest_data_begin); + LI (x7, (0xB7FBB6FAB7FBB6FA & MASK)); + LI (x8, (0x5BFDDB7D5BFDDB7D & MASK)); + LI (x9, (0xADFEEDBEADFEEDBE & MASK)); + LI (x10, (0x56FF76DF56FF76DF & MASK)); + LI (x11, (0xAB7FBB6FAB7FBB6F & MASK)); + LI (x12, (0xD5BFDDB7D5BFDDB7 & MASK)); + LI (x13, (0xEADFEEDBEADFEEDB & MASK)); + LI (x14, (0xF56FF76DF56FF76D & MASK)); + LI (x15, (0xFAB7FBB6FAB7FBB6 & MASK)); + #ifndef RVTEST_E + LI (x16, (0x7D5BFDDB7D5BFDDB & MASK)); + LI (x17, (0xBEADFEEDBEADFEED & MASK)); + LI (x18, (0xDF56FF76DF56FF76 & MASK)); + LI (x19, (0x6FAB7FBB6FAB7FBB & MASK)); + LI (x20, (0xB7D5BFDDB7D5BFDD & MASK)); + LI (x21, (0xDBEADFEEDBEADFEE & MASK)); + LI (x22, (0x6DF56FF76DF56FF7 & MASK)); + LI (x23, (0xB6FAB7FBB6FAB7FB & MASK)); + LI (x24, (0xDB7D5BFDDB7D5BFD & MASK)); + LI (x25, (0xEDBEADFEEDBEADFE & MASK)); + LI (x26, (0x76DF56FF76DF56FF & MASK)); + LI (x27, (0xBB6FAB7FBB6FAB7F & MASK)); + LI (x28, (0xDDB7D5BFDDB7D5BF & MASK)); + LI (x29, (0xEEDBEADFEEDBEADF & MASK)); + LI (x30, (0xF76DF56FF76DF56F & MASK)); + LI (x31, (0xFBB6FAB7FBB6FAB7 & MASK)); + #endif + .globl rvtest_code_begin + rvtest_code_begin: +.endm + +// --------------------------------- CODE BEGIN w/ TRAP HANDLER END -----------------------------// + +.macro RVTEST_CODE_END + .align 4; + .global rvtest_code_end + rvtest_code_end: +#ifdef rvtest_mtrap_routine + .option push + .option norvc + j exit_cleanup + + rvtest_trap_prolog: + /******************************************************************************/ + /**** Prolog, to be run before any tests ****/ + /**** #include 1 copy of this per mode in rvmodel_boot code? ****/ + /**** ------------------------------------------------------------------- ****/ + /**** if xTVEC isn't completely RW, then we need to change the code at its ****/ + /**** target. The entire trap trampoline and mtrap handler replaces the ****/ + /**** area pointed to by mtvec, after saving its original contents first. ****/ + /**** If it isn't possible to fully write that area, restore and fail. ****/ + /******************************************************************************/ + + //trap_handler_prolog; enter with t1..t6 available + + init_mscratch: + la t1, trapreg_sv + csrrw t1, CSR_MSCRATCH, t1 // swap old mscratch. mscratch not points to trapreg_sv + la t2, mscratch_save + SREG t1, 0(t2) // save old mscratch in mscratch_save region + csrr t1, CSR_MSCRATCH // read the trapreg_sv address + LA( t2, mtrap_sigptr ) // locate the start of the trap signature + SREG t2, 0(t1) // save mtrap_sigptr at first location of trapreg_sv + init_mtvec: + la t1, mtrampoline + la t4, mtvec_save + csrrw t2, CSR_MTVEC, t1 // swap mtvec and trap_trampoline + SREG t2, 0(t4) // save orig mtvec + csrr t3, CSR_MTVEC // now read new_mtval back + beq t3, t1, rvtest_prolog_done // if mtvec==trap_trampoline, mtvec is writable, continue + + /****************************************************************/ + /**** fixed mtvec, can't move it so move trampoline instead ****/ + /**** t1=trampoline, t2=oldmtvec, t3=save area, t4=save end ****/ + /****************************************************************/ + + // t2 = dut's original mtvec setting + // t1 = mtrampoline address + init_tramp: /**** copy trampoline at mtvec tgt ****/ + + csrw CSR_MTVEC, t2 // restore orig mtvec, will now attemp to copy trampoline to it + la t3, tramptbl_sv // addr of save area + addi t4, t3, NUM_SPECD_INTCAUSES*4 // end of save area + + overwrite_tt: // now build new trampoline table with offsets base from curr mtvec + lw t6, 0(t2) // get original mtvec target + sw t6, 0(t3) // save it + lw t5, 0(t1) // get trampoline src + sw t5, 0(t2) // overwrite mtvec target + lw t6, 0(t2) // rd it back to make sure it was written + bne t6, t5, resto_tramp // table isn't fully writable, restore and give up + addi t1, t1, 4 // next src index + addi t2, t2, 4 // next tgt index + addi t3, t3, 4 // next save index + bne t3, t4, overwrite_tt // not done, loop + j rvtest_prolog_done + + resto_tramp: // vector table not writeable, restore + LREG t1, 16(t4) // load mscratch_SAVE at fixed offset from table end + csrw CSR_MSCRATCH, t1 // restore mscratch + LREG t4, 8(t4) // load mtvec_SAVE (used as end of loop marker) + + + resto_loop: // goes backwards, t2= dest vec tbl ptr, t3=src save area ptr, t4=vec tbl begin + lw t6, 0(t3) // read saved tgt entry + sw t6, 0(t2) // restore original tgt + addi t2, t2, -4 // prev tgt index + addi t3, t3, -4 // prev save index + bne t2, t4, resto_loop // didn't restore to begining yet, loop + + j rvtest_end // failure to replace trampoline + + + #define mhandler \ + csrrw sp, CSR_MSCRATCH, sp; \ + SREG t6, 6*REGWIDTH(sp); \ + jal t6, common_prolog; + + /**********************************************************************/ + /**** This is the entry point for all m-modetraps, vectored or not.****/ + /**** At entry, mscratch will contain a pointer to a scratch area. ****/ + /**** This is an array of branches at 4B intevals that spreads out ****/ + /**** to an array of 32B mhandler macros for specd int causes, and ****/ + /**** to a return for anything above that (which causes a mismatch)****/ + /**********************************************************************/ + mtrampoline: // 64 or 32 entry table + value = 0 + .rept NUM_SPECD_INTCAUSES // located at each possible int vectors + j mtrap_handler + 12*(value) //offset < +/- 1MB + value = value + 1 + .endr + .rept RLENG-NUM_SPECD_INTCAUSES // fill at each impossible entry + mret + .endr + + mtrap_handler: /* after executing, sp points to temp save area, t4 is PC */ + .rept NUM_SPECD_INTCAUSES + mhandler + .endr + + common_prolog: + la t5, common_mhandler + jr t5 + /*********************************************************************/ + /**** common code for all ints & exceptions, will fork to handle ****/ + /**** each separately. The common handler first stores trap mode+ ****/ + /**** vector, and mcause signatures. All traps have 4wd sigs, but ****/ + /**** sw and timer ints only store 3 of the 4. ****/ + /**** sig offset Exception ExtInt SWInt TimerInt ****/ + /**** 0: tval IntID -1 -1 ****/ + /**** 4: mepc mip mip mip ****/ + /**** 8: <---------------------- mcause -------------> ****/ + /**** 12: <--------------------- Vect+mode ----------> ****/ + /*********************************************************************/ + /* in general, CSRs loaded in t2, addresses into t3 */ + + common_mhandler: /* enter with link in t6 */ + SREG t5, 5*REGWIDTH(sp) + SREG t4, 4*REGWIDTH(sp) + SREG t3, 3*REGWIDTH(sp) + SREG t2, 2*REGWIDTH(sp) + SREG t1, 1*REGWIDTH(sp) /* save other temporaries */ + + LREG t1, 0(sp) /* load trap sig pointer (runs backwards from DATA_END) */ + + LA( t3, mtrampoline) + sub t2, t6, t3 /* reloc “link” to 0..63 to show which int vector was taken */ + addi t2, t2, MMODE_SIG /* insert mode# into 1:0 */ + SREG t2, 0*REGWIDTH(t1) /* save 1st sig value, (vect, trapmode) */ + sv_mcause: + csrr t2, CSR_MCAUSE + SREG t2, 1*REGWIDTH(t1) /* save 2nd sig value, (mcause) */ + + bltz t2, common_mint_handler /* this is a interrupt, not a trap */ + + /********************************************************************/ + /**** This is the exceptions specific code, storing relative mepc****/ + /**** & relative tval signatures. tval is relocated by code or ****/ + /**** data start, or 0 depending on mcause. mepc signature value ****/ + /**** is relocated by code start, and restored adjusted depending****/ + /**** on op alignment so trapped op isn't re-executed. ****/ + /********************************************************************/ + common_mexcpt_handler: + csrr t2, CSR_MEPC + sv_mepc: + LA( t3, rvtest_prolog_done) /* offset to compensate for different loader offsets */ + sub t4, t2, t3 /* convert mepc to rel offset of beginning of test*/ + SREG t4, 2*REGWIDTH(t1) /* save 3rd sig value, (rel mepc) into trap signature area */ + adj_mepc: //adj mepc so there is padding after op, and its 8B aligned + andi t4, t2, 0x2 /* set to 2 if mepc was misaligned */ + sub t2, t2, t4 /* adjust mepc to prev 4B alignment */ + addi t2, t2, 0x8 /* adjust mepc, so it skips past the op, has padding & is 4B aligned */ + csrw CSR_MEPC, t2 /* restore adjusted value, has 1,2, or 3 bytes of padding */ + + + /* calculate relative mtval if it’s an address (by code_begin or data_begin amt) */ + /* note that masks that determine this are implementation specific from YAML */ + + /* masks are bit reversed, so mcause==0 bit is in MSB (so different for RV32 and RV64) */ + + adj_mtval: + csrr t2, CSR_MCAUSE /* code begin adjustment amount already in t3 */ + + LI(t4, CODE_REL_TVAL_MSK) /* trap#s 12, 3,1,0, -- adjust w/ code_begin */ + sll t4, t4, t2 /* put bit# in MSB */ + bltz t4, sv_mtval /* correct adjustment is code_begin in t3 */ + + LA( t3, mtrap_sigptr) /* adjustment assuming access is to signature region */ + LI(t4, DATA_REL_TVAL_MSK) /* trap#s not 14, 11..8, 2 adjust w/ data_begin */ + sll t4, t4, t2 /* put bit# in MSB */ + bgez t4, no_adj /* correct adjustment is data_begin in t3 */ + sigbound_chk: + csrr t4, CSR_MTVAL /* do a bounds check on mtval */ + bge t3, t4, sv_mtval /* if mtval is greater than the rvmodel_data_begin then use that as anchor */ + LA( t3, rvtest_data_begin) /* else change anchor to rvtest_data_begin */ + blt t3, t4, sv_mtval /* before the signature, use data_begin adj */ + mv t4, t3 /* use sig relative adjust */ + no_adj: + LI(t3, 0) /* else zero adjustment amt */ + + // For Illegal op handling + addi t2, t2, -2 /* check if mcause==2 (illegal op) */ + bnez t2, sv_mtval /* not illegal op, no special treatment */ + csrr t2, CSR_MTVAL + bnez t2, sv_mtval /* mtval isn’t zero, no special treatment */ + illop: + LI(t5, 0x20000) /* get mprv mask */ + csrrs t5, CSR_MSTATUS, t5 /* set mprv while saving the old value */ + csrr t3, CSR_MEPC + lhu t2, 0(t3) /* load 1st 16b of opc w/ old priv, endianess*/ + andi t4, t2, 0x3 + addi t4, t4, -0x3 /* does opcode[1:0]==0b11? (Meaning >16b op) */ + bnez t4, sv_mtval /* entire mtval is in tt2, adj amt will be set to zero */ + lhu t4, 2(t3) + sll t4, t4, 16 + or t3, t2, t4 /* get 2nd hwd, align it & insert it into opcode */ + csrw CSR_MSTATUS, t5 /* restore mstatus */ + +/*******FIXME: this will not handle 48 or 64b opcodes in an RV64) ********/ + + sv_mtval: + csrr t2, CSR_MTVAL + sub t2, t2, t3 /* perform mtval adjust by either code or data position or zero*/ + SREG t2, 3*REGWIDTH(t1) /* save 4th sig value, (rel mtval) into trap signature area */ + + resto_rtn: /* restore and return */ + addi t1, t1,4*REGWIDTH /* adjust trap signature ptr (traps always save 4 words) */ + SREG t1, 0*REGWIDTH(sp) /* save updated trap sig pointer (pts to trap_sigptr */ + + LREG t1, 1*REGWIDTH(sp) + LREG t2, 2*REGWIDTH(sp) + LREG t3, 3*REGWIDTH(sp) + LREG t4, 4*REGWIDTH(sp) + LREG t5, 5*REGWIDTH(sp) + LREG t6, 6*REGWIDTH(sp) /* restore temporaries */ + + csrrw sp, CSR_MSCRATCH, sp /* restore sp from scratch */ + mret + + common_mint_handler: /* t1 has sig ptr, t2 has mcause */ + + LI(t3, 1) + sll t3, t3, t2 /* create mask 1<

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+/////////////////////////////////////////// +// flop.sv +// +// Written: David_Harris@hmc.edu 9 January 2021 +// Modified: +// +// Purpose: various flavors of flip-flops +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +`include "wally-config.vh" + +// ordinary flip-flop +module flop #(parameter WIDTH = 8) ( + input logic clk, + input logic [WIDTH-1:0] d, + output logic [WIDTH-1:0] q); + + always_ff @(posedge clk) + q <= #1 d; +endmodule + diff --git a/wally-pipelined/src/generic/flop/flopen.sv b/wally-pipelined/src/generic/flop/flopen.sv new file mode 100644 index 000000000..618b02e7f --- /dev/null +++ b/wally-pipelined/src/generic/flop/flopen.sv @@ -0,0 +1,37 @@ +/////////////////////////////////////////// +// flopen.sv +// +// Written: David_Harris@hmc.edu 9 January 2021 +// Modified: +// +// Purpose: various flavors of flip-flops +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +`include "wally-config.vh" + +// flop with enable +module flopen #(parameter WIDTH = 8) ( + input logic clk, en, + input logic [WIDTH-1:0] d, + output logic [WIDTH-1:0] q); + + always_ff @(posedge clk) + if (en) q <= #1 d; +endmodule + diff --git a/wally-pipelined/src/generic/flop/flopenl.sv b/wally-pipelined/src/generic/flop/flopenl.sv new file mode 100644 index 000000000..acf3f2a0d --- /dev/null +++ b/wally-pipelined/src/generic/flop/flopenl.sv @@ -0,0 +1,39 @@ +/////////////////////////////////////////// +// flopenl.sv +// +// Written: David_Harris@hmc.edu 9 January 2021 +// Modified: +// +// Purpose: various flavors of flip-flops +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +`include "wally-config.vh" + +// flop with enable, asynchronous load +module flopenl #(parameter WIDTH = 8, parameter type TYPE=logic [WIDTH-1:0]) ( + input logic clk, load, en, + input TYPE d, + input TYPE val, + output TYPE q); + + always_ff @(posedge clk, posedge load) + if (load) q <= #1 val; + else if (en) q <= #1 d; +endmodule + diff --git a/wally-pipelined/src/generic/flop/flopenr.sv b/wally-pipelined/src/generic/flop/flopenr.sv new file mode 100644 index 000000000..9db912eae --- /dev/null +++ b/wally-pipelined/src/generic/flop/flopenr.sv @@ -0,0 +1,38 @@ +/////////////////////////////////////////// +// flopenr.sv +// +// Written: David_Harris@hmc.edu 9 January 2021 +// Modified: +// +// Purpose: various flavors of flip-flops +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +`include "wally-config.vh" + +// flop with enable, asynchronous reset +module flopenr #(parameter WIDTH = 8) ( + input logic clk, reset, en, + input logic [WIDTH-1:0] d, + output logic [WIDTH-1:0] q); + + always_ff @(posedge clk, posedge reset) + if (reset) q <= #1 0; + else if (en) q <= #1 d; +endmodule + diff --git a/wally-pipelined/src/generic/flop/flopenrc.sv b/wally-pipelined/src/generic/flop/flopenrc.sv new file mode 100644 index 000000000..d8806196c --- /dev/null +++ b/wally-pipelined/src/generic/flop/flopenrc.sv @@ -0,0 +1,40 @@ +/////////////////////////////////////////// +// flopenrc.sv +// +// Written: David_Harris@hmc.edu 9 January 2021 +// Modified: +// +// Purpose: various flavors of flip-flops +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +`include "wally-config.vh" + +// flop with enable, asynchronous reset, synchronous clear +module flopenrc #(parameter WIDTH = 8) ( + input logic clk, reset, clear, en, + input logic [WIDTH-1:0] d, + output logic [WIDTH-1:0] q); + + always_ff @(posedge clk, posedge reset) + if (reset) q <= #1 0; + else if (en) + if (clear) q <= #1 0; + else q <= #1 d; +endmodule + diff --git a/wally-pipelined/src/muldiv/div/div64_sim/mux.sv b/wally-pipelined/src/generic/flop/flopens.sv similarity index 54% rename from wally-pipelined/src/muldiv/div/div64_sim/mux.sv rename to wally-pipelined/src/generic/flop/flopens.sv index da2682462..d51659b8b 100644 --- a/wally-pipelined/src/muldiv/div/div64_sim/mux.sv +++ b/wally-pipelined/src/generic/flop/flopens.sv @@ -1,10 +1,10 @@ /////////////////////////////////////////// -// mux.sv +// flopens.sv // // Written: David_Harris@hmc.edu 9 January 2021 // Modified: // -// Purpose: Various flavors of multiplexers +// Purpose: various flavors of flip-flops // // A component of the Wally configurable RISC-V project. // @@ -23,44 +23,17 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -module mux2 #(parameter WIDTH = 8) ( - input logic [WIDTH-1:0] d0, d1, - input logic s, - output logic [WIDTH-1:0] y); +`include "wally-config.vh" - assign y = s ? d1 : d0; +// flop with enable, asynchronous set +module flopens #(parameter WIDTH = 8) ( + input logic clk, set, en, + input logic [WIDTH-1:0] d, + output logic [WIDTH-1:0] q); + + always_ff @(posedge clk, posedge set) + if (set) q <= #1 1; + else if (en) q <= #1 d; endmodule -module mux3 #(parameter WIDTH = 8) ( - input logic [WIDTH-1:0] d0, d1, d2, - input logic [1:0] s, - output logic [WIDTH-1:0] y); - assign y = s[1] ? d2 : (s[0] ? d1 : d0); -endmodule - -module mux4 #(parameter WIDTH = 8) ( - input logic [WIDTH-1:0] d0, d1, d2, d3, - input logic [1:0] s, - output logic [WIDTH-1:0] y); - - assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0); -endmodule - -module mux5 #(parameter WIDTH = 8) ( - input logic [WIDTH-1:0] d0, d1, d2, d3, d4, - input logic [2:0] s, - output logic [WIDTH-1:0] y); - - assign y = s[2] ? d4 : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0)); -endmodule - -module mux6 #(parameter WIDTH = 8) ( - input logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5, - input logic [2:0] s, - output logic [WIDTH-1:0] y); - - assign y = s[2] ? (s[0] ? d5 : d4) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0)); -endmodule - -/* verilator lint_on DECLFILENAME */ diff --git a/wally-pipelined/src/generic/flop/flopr.sv b/wally-pipelined/src/generic/flop/flopr.sv new file mode 100644 index 000000000..5ff6a5a91 --- /dev/null +++ b/wally-pipelined/src/generic/flop/flopr.sv @@ -0,0 +1,38 @@ +/////////////////////////////////////////// +// flopr.sv +// +// Written: David_Harris@hmc.edu 9 January 2021 +// Modified: +// +// Purpose: various flavors of flip-flops +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +`include "wally-config.vh" + +// flop with asynchronous reset +module flopr #(parameter WIDTH = 8) ( + input logic clk, reset, + input logic [WIDTH-1:0] d, + output logic [WIDTH-1:0] q); + + always_ff @(posedge clk, posedge reset) + if (reset) q <= #1 0; + else q <= #1 d; +endmodule + diff --git a/wally-pipelined/src/generic/flop/floprc.sv b/wally-pipelined/src/generic/flop/floprc.sv new file mode 100644 index 000000000..9d5f17c7a --- /dev/null +++ b/wally-pipelined/src/generic/flop/floprc.sv @@ -0,0 +1,41 @@ +/////////////////////////////////////////// +// floprc.sv +// +// Written: David_Harris@hmc.edu 9 January 2021 +// Modified: +// +// Purpose: various flavors of flip-flops +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +`include "wally-config.vh" + +// flop with asynchronous reset, synchronous clear +module floprc #(parameter WIDTH = 8) ( + input logic clk, + input logic reset, + input logic clear, + input logic [WIDTH-1:0] d, + output logic [WIDTH-1:0] q); + + always_ff @(posedge clk, posedge reset) + if (reset) q <= #1 0; + else + if (clear) q <= #1 0; + else q <= #1 d; +endmodule diff --git a/wally-pipelined/src/muldiv/div/README b/wally-pipelined/src/muldiv/div/README deleted file mode 100755 index 6898c5cec..000000000 --- a/wally-pipelined/src/muldiv/div/README +++ /dev/null @@ -1 +0,0 @@ -vsim -do iter64.do -c diff --git a/wally-pipelined/src/muldiv/div/README.md b/wally-pipelined/src/muldiv/div/README.md deleted file mode 100644 index ebb006c95..000000000 --- a/wally-pipelined/src/muldiv/div/README.md +++ /dev/null @@ -1,22 +0,0 @@ -This is a novel integer divider using r4 division by recurrence. The -reference is: - -J. E. Stine and K. Hill, "An Efficient Implementation of Radix-4 -Integer Division Using Scaling," 2020 IEEE 63rd International Midwest -Symposium on Circuits and Systems (MWSCAS), Springfield, MA, USA, -2020, pp. 1092-1095, doi: 10.1109/MWSCAS48704.2020.9184631. - -Although this version does not contain scaling, it could do this, if -needed. Moreover, a higher radix or overlapped radix can be done -easily to expand the the size. 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diff --git a/wally-pipelined/src/muldiv/div/div64_sim/div.sv b/wally-pipelined/src/muldiv/div/div64_sim/div.sv deleted file mode 100755 index 568971e2d..000000000 --- a/wally-pipelined/src/muldiv/div/div64_sim/div.sv +++ /dev/null @@ -1,1535 +0,0 @@ -/////////////////////////////////////////// -// mul.sv -// -// Written: James.Stine@okstate.edu 1 February 2021 -// Modified: -// -// Purpose: Integer Divide instructions -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// - -module div (Q, done, divdone, rem0, div0, N, D, clk, reset, start); - - input logic [63:0] N, D; - input logic clk; - input logic reset; - input logic start; - - output logic [63:0] Q; - output logic [63:0] rem0; - output logic div0; - output logic divdone; - - output logic done; - logic enable; - logic state0; - logic V; - logic [7:0] Num; - logic [5:0] P, NumIter, RemShift; - logic [63:0] op1, op2, op1shift, Rem5; - logic [64:0] Qd, Rd, Qd2, Rd2; - logic [3:0] quotient; - logic otfzero; - logic shiftResult; - - // Divider goes the distance to 37 cycles - // (thanks the evil divisor for D = 0x1) - // but could theoretically be stopped when - // divdone is asserted. The enable signal - // turns off register storage thus invalidating - // any future cycles. - - // Shift D, if needed (for integer) - // needed to allow qst to be in range for integer - // division [1,2) and allow integer divide to work. - // - // The V or valid bit can be used to determine if D - // is 0 and thus a divide by 0 exception. This div0 - // exception is given to FSM to tell the operation to - // quit gracefully. - - // div0 produced output errors have untested results - // (it is assumed the OS would handle some output) - - lz64 p1 (P, V, D); - shifter_l64 p2 (op2, D, P); - assign op1 = N; - assign div0 = ~V; - - // #iter: N = m+v+s = m+(s+2) = m+2+s (mod k = 0) - // v = 2 since \rho < 1 (add 4 to make sure its a ceil) - adder #(8) cpa1 ({2'b0, P}, - {5'h0, shiftResult, ~shiftResult, 1'b0}, - Num); - - // Determine whether need to add just Q/Rem - assign shiftResult = P[0]; - // div by 2 (ceil) - assign NumIter = Num[6:1]; - assign RemShift = P; - - // FSM to control integer divider - // assume inputs are postive edge and - // datapath (divider) is negative edge - fsm64 fsm1 (enablev, state0v, donev, divdonev, otfzerov, - start, div0, NumIter, ~clk, reset); - - flopr #(1) rega (~clk, reset, donev, done); - flopr #(1) regb (~clk, reset, divdonev, divdone); - flopr #(1) regc (~clk, reset, otfzerov, otfzero); - flopr #(1) regd (~clk, reset, enablev, enable); - flopr #(1) rege (~clk, reset, state0v, state0); - - // To obtain a correct remainder the last bit of the - // quotient has to be aligned with a radix-r boundary. - // Since the quotient is in the range 1/2 < q < 2 (one - // integer bit and m fractional bits), this is achieved by - // shifting N right by v+s so that (m+v+s) mod k = 0. And, - // the quotient has to be aligned to the integer position. - - // Used a Brent-Kung for no reason (just wanted prefix -- might - // have gotten away with a RCA) - - // Actual divider unit FIXME: r16 (jes) - divide4x64 p3 (Qd, Rd, quotient, op1, op2, clk, reset, state0, - enable, otfzero, shiftResult); - - // Storage registers to hold contents stable - flopenr #(65) reg3 (clk, reset, enable, Rd, Rd2); - flopenr #(65) reg4 (clk, reset, enable, Qd, Qd2); - - // Probably not needed - just assigns results - assign Q = Qd2[63:0]; - assign Rem5 = Rd2[64:1]; - - // Adjust remainder by m (no need to adjust by - // n ln(r) - shifter_r64 p4 (rem0, Rem5, RemShift); - -endmodule // int32div - -module divide4x64 (Q, rem0, quotient, op1, op2, clk, reset, state0, - enable, otfzero, shiftResult); - - input logic [63:0] op1, op2; - input logic clk, state0; - input logic reset; - input logic enable; - input logic otfzero; - input logic shiftResult; - - output logic [64:0] rem0; - output logic [64:0] Q; - output logic [3:0] quotient; - - logic [67:0] Sum, Carry; - logic [64:0] Qstar; - logic [64:0] QMstar; - logic [7:0] qtotal; - logic [67:0] SumN, CarryN, SumN2, CarryN2; - logic [67:0] divi1, divi2, divi1c, divi2c, dive1; - logic [67:0] mdivi_temp, mdivi; - logic zero; - logic [1:0] qsel; - logic [1:0] Qin, QMin; - logic CshiftQ, CshiftQM; - logic [67:0] rem1, rem2, rem3; - logic [67:0] SumR, CarryR; - logic [64:0] Qt; - - // Create one's complement values of Divisor (for q*D) - assign divi1 = {3'h0, op2, 1'b0}; - assign divi2 = {2'h0, op2, 2'b0}; - assign divi1c = ~divi1; - assign divi2c = ~divi2; - // Shift x1 if not mod k - mux2 #(68) mx1 ({3'b000, op1, 1'b0}, {4'h0, op1}, shiftResult, dive1); - - // I I I . F F F F F ... (Robertson Criteria - \rho * qmax * D) - mux2 #(68) mx2 ({CarryN2[65:0], 2'h0}, 68'h0, state0, CarryN); - mux2 #(68) mx3 ({SumN2[65:0], 2'h0}, dive1, state0, SumN); - // Simplify QST - adder #(8) cpa1 (SumN[67:60], CarryN[67:60], qtotal); - // q = {+2, +1, -1, -2} else q = 0 - qst4 pd1 (qtotal[7:1], divi1[63:61], quotient); - assign ulp = quotient[2]|quotient[3]; - assign zero = ~(quotient[3]|quotient[2]|quotient[1]|quotient[0]); - // Map to binary encoding - assign qsel[1] = quotient[3]|quotient[2]; - assign qsel[0] = quotient[3]|quotient[1]; - mux4 #(68) mx4 (divi2, divi1, divi1c, divi2c, qsel, mdivi_temp); - mux2 #(68) mx5 (mdivi_temp, 68'h0, zero, mdivi); - csa #(68) csa1 (mdivi, SumN, {CarryN[67:1], ulp}, Sum, Carry); - // regs : save CSA - flopenr #(68) reg1 (clk, reset, enable, Sum, SumN2); - flopenr #(68) reg2 (clk, reset, enable, Carry, CarryN2); - // OTF - ls_control otf1 (quotient, Qin, QMin, CshiftQ, CshiftQM); - otf #(65) otf2 (Qin, QMin, CshiftQ, CshiftQM, clk, - otfzero, enable, Qstar, QMstar); - - // Correction and generation of Remainder - adder #(68) cpa2 (SumN2[67:0], CarryN2[67:0], rem1); - // Add back +D as correction - csa #(68) csa2 (CarryN2[67:0], SumN2[67:0], divi1, SumR, CarryR); - adder #(68) cpa3 (SumR, CarryR, rem2); - // Choose remainder (Rem or Rem+D) - mux2 #(68) mx6 (rem1, rem2, rem1[67], rem3); - // Choose correct Q or QM - mux2 #(65) mx7 (Qstar, QMstar, rem1[67], Qt); - // Final results - assign rem0 = rem3[64:0]; - assign Q = Qt; - -endmodule // divide4x64 - -module ls_control (quot, Qin, QMin, CshiftQ, CshiftQM); - - input logic [3:0] quot; - - output logic [1:0] Qin; - output logic [1:0] QMin; - output logic CshiftQ; - output logic CshiftQM; - - // Load/Store Control for OTF - assign Qin[1] = (quot[1]) | (quot[3]) | (quot[0]); - assign Qin[0] = (quot[1]) | (quot[2]); - assign QMin[1] = (quot[1]) | (!quot[3]&!quot[2]&!quot[1]&!quot[0]); - assign QMin[0] = (quot[3]) | (quot[0]) | - (!quot[3]&!quot[2]&!quot[1]&!quot[0]); - assign CshiftQ = (quot[1]) | (quot[0]); - assign CshiftQM = (quot[3]) | (quot[2]); - -endmodule - -// On-the-fly Conversion per Ercegovac/Lang - -module otf #(parameter WIDTH=8) - (Qin, QMin, CshiftQ, CshiftQM, clk, reset, enable, R2Q, R1Q); - - input logic [1:0] Qin, QMin; - input logic CshiftQ, CshiftQM; - input logic clk; - input logic reset; - input logic enable; - - output logic [WIDTH-1:0] R2Q; - output logic [WIDTH-1:0] R1Q; - - logic [WIDTH-1:0] Qstar, QMstar; - logic [WIDTH-1:0] M1Q, M2Q; - - // QM - mux2 #(WIDTH) m1 (QMstar, Qstar, CshiftQM, M1Q); - flopenr #(WIDTH) r1 (clk, reset, enable, {M1Q[WIDTH-3:0], QMin}, R1Q); - // Q - mux2 #(WIDTH) m2 (Qstar, QMstar, CshiftQ, M2Q); - flopenr #(WIDTH) r2 (clk, reset, enable, {M2Q[WIDTH-3:0], Qin}, R2Q); - - assign Qstar = R2Q; - assign QMstar = R1Q; - -endmodule // otf8 - -module adder #(parameter WIDTH=8) (input logic [WIDTH-1:0] a, b, - output logic [WIDTH-1:0] y); - - assign y = a + b; - -endmodule // adder - -module fa (input logic a, b, c, output logic sum, carry); - - assign sum = a^b^c; - assign carry = a&b|a&c|b&c; - -endmodule // fa - -module csa #(parameter WIDTH=8) (input logic [WIDTH-1:0] a, b, c, - output logic [WIDTH-1:0] sum, carry); - - logic [WIDTH:0] carry_temp; - genvar i; - generate - for (i=0;i B. LT and GT are both '0' if A = B. - -module magcompare2b (LT, GT, A, B); - - input logic [1:0] A; - input logic [1:0] B; - - output logic LT; - output logic GT; - - // Determine if A < B using a minimized sum-of-products expression - assign LT = ~A[1]&B[1] | ~A[1]&~A[0]&B[0] | ~A[0]&B[1]&B[0]; - // Determine if A > B using a minimized sum-of-products expression - assign GT = A[1]&~B[1] | A[1]&A[0]&~B[0] | A[0]&~B[1]&~B[0]; - -endmodule // magcompare2b - -// J. E. Stine and M. J. Schulte, "A combined two's complement and -// floating-point comparator," 2005 IEEE International Symposium on -// Circuits and Systems, Kobe, 2005, pp. 89-92 Vol. 1. -// doi: 10.1109/ISCAS.2005.1464531 - -module magcompare8 (LT, EQ, A, B); - - input logic [7:0] A; - input logic [7:0] B; - - logic [3:0] s; - logic [3:0] t; - logic [1:0] u; - logic [1:0] v; - logic GT; - //wire LT; - - output logic EQ; - output logic LT; - - magcompare2b mag1 (s[0], t[0], A[1:0], B[1:0]); - magcompare2b mag2 (s[1], t[1], A[3:2], B[3:2]); - magcompare2b mag3 (s[2], t[2], A[5:4], B[5:4]); - magcompare2b mag4 (s[3], t[3], A[7:6], B[7:6]); - - magcompare2b mag5 (u[0], v[0], t[1:0], s[1:0]); - magcompare2b mag6 (u[1], v[1], t[3:2], s[3:2]); - - magcompare2b mag7 (LT, GT, v[1:0], u[1:0]); - - assign EQ = ~(GT | LT); - -endmodule // magcompare8 - -module shifter_l64 (Z, A, Shift); - - input logic [63:0] A; - input logic [5:0] Shift; - - logic [63:0] stage1; - logic [63:0] stage2; - logic [63:0] stage3; - logic [63:0] stage4; - logic [63:0] stage5; - logic [31:0] thirtytwozeros = 32'h0; - logic [15:0] sixteenzeros = 16'h0; - logic [ 7:0] eightzeros = 8'h0; - logic [ 3:0] fourzeros = 4'h0; - logic [ 1:0] twozeros = 2'b00; - logic onezero = 1'b0; - - output logic [63:0] Z; - - mux2 #(64) mx01(A, {A[31:0], thirtytwozeros}, Shift[5], stage1); - mux2 #(64) mx02(stage1, {stage1[47:0], sixteenzeros}, Shift[4], stage2); - mux2 #(64) mx03(stage2, {stage2[55:0], eightzeros}, Shift[3], stage3); - mux2 #(64) mx04(stage3, {stage3[59:0], fourzeros}, Shift[2], stage4); - mux2 #(64) mx05(stage4, {stage4[61:0], twozeros}, Shift[1], stage5); - mux2 #(64) mx06(stage5, {stage5[62:0], onezero}, Shift[0], Z); - -endmodule // shifter_l64 - -module shifter_r64 (Z, A, Shift); - - input logic [63:0] A; - input logic [5:0] Shift; - - logic [63:0] stage1; - logic [63:0] stage2; - logic [63:0] stage3; - logic [63:0] stage4; - logic [63:0] stage5; - logic [31:0] thirtytwozeros = 32'h0; - logic [15:0] sixteenzeros = 16'h0; - logic [ 7:0] eightzeros = 8'h0; - logic [ 3:0] fourzeros = 4'h0; - logic [ 1:0] twozeros = 2'b00; - logic onezero = 1'b0; - - output logic [63:0] Z; - - mux2 #(64) mx01(A, {thirtytwozeros, A[63:32]}, Shift[5], stage1); - mux2 #(64) mx02(stage1, {sixteenzeros, stage1[63:16]}, Shift[4], stage2); - mux2 #(64) mx03(stage2, {eightzeros, stage2[63:8]}, Shift[3], stage3); - mux2 #(64) mx04(stage3, {fourzeros, stage3[63:4]}, Shift[2], stage4); - mux2 #(64) mx05(stage4, {twozeros, stage4[63:2]}, Shift[1], stage5); - mux2 #(64) mx06(stage5, {onezero, stage5[63:1]}, Shift[0], Z); - -endmodule // shifter_r64 - -module shifter_l32 (Z, A, Shift); - - input logic [31:0] A; - input logic [4:0] Shift; - - logic [31:0] stage1; - logic [31:0] stage2; - logic [31:0] stage3; - logic [31:0] stage4; - logic [15:0] sixteenzeros = 16'h0; - logic [ 7:0] eightzeros = 8'h0; - logic [ 3:0] fourzeros = 4'h0; - logic [ 1:0] twozeros = 2'b00; - logic onezero = 1'b0; - - output logic [31:0] Z; - - mux2 #(32) mx01(A, {A[15:0], sixteenzeros}, Shift[4], stage1); - mux2 #(32) mx02(stage1, {stage1[23:0], eightzeros}, Shift[3], stage2); - mux2 #(32) mx03(stage2, {stage2[27:0], fourzeros}, Shift[2], stage3); - mux2 #(32) mx04(stage3, {stage3[29:0], twozeros}, Shift[1], stage4); - mux2 #(32) mx05(stage4, {stage4[30:0], onezero}, Shift[0], Z); - -endmodule // shifter_l32 - -module shifter_r32 (Z, A, Shift); - - input logic [31:0] A; - input logic [4:0] Shift; - - logic [31:0] stage1; - logic [31:0] stage2; - logic [31:0] stage3; - logic [31:0] stage4; - logic [15:0] sixteenzeros = 16'h0; - logic [ 7:0] eightzeros = 8'h0; - logic [ 3:0] fourzeros = 4'h0; - logic [ 1:0] twozeros = 2'b00; - logic onezero = 1'b0; - - output logic [31:0] Z; - - mux2 #(32) mx01(A, {sixteenzeros, A[31:16]}, Shift[4], stage1); - mux2 #(32) mx02(stage1, {eightzeros, stage1[31:8]}, Shift[3], stage2); - mux2 #(32) mx03(stage2, {fourzeros, stage2[31:4]}, Shift[2], stage3); - mux2 #(32) mx04(stage3, {twozeros, stage3[31:2]}, Shift[1], stage4); - mux2 #(32) mx05(stage4, {onezero, stage4[31:1]}, Shift[0], Z); - -endmodule // shifter_r32 - diff --git a/wally-pipelined/src/muldiv/div/div64_sim/flop.sv b/wally-pipelined/src/muldiv/div/div64_sim/flop.sv deleted file mode 100644 index 7f20fb7fb..000000000 --- a/wally-pipelined/src/muldiv/div/div64_sim/flop.sv +++ /dev/null @@ -1,108 +0,0 @@ -/////////////////////////////////////////// -// flop.sv -// -// Written: David_Harris@hmc.edu 9 January 2021 -// Modified: -// -// Purpose: arious flavors of flip-flops -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// - -// ordinary flip-flop -module flop #(parameter WIDTH = 8) ( - input logic clk, - input logic [WIDTH-1:0] d, - output logic [WIDTH-1:0] q); - - always_ff @(posedge clk) - q <= #1 d; -endmodule - -// flop with asynchronous reset -module flopr #(parameter WIDTH = 8) ( - input logic clk, reset, - input logic [WIDTH-1:0] d, - output logic [WIDTH-1:0] q); - - always_ff @(posedge clk, posedge reset) - if (reset) q <= #1 0; - else q <= #1 d; -endmodule - -// flop with enable -module flopen #(parameter WIDTH = 8) ( - input logic clk, en, - input logic [WIDTH-1:0] d, - output logic [WIDTH-1:0] q); - - always_ff @(posedge clk) - if (en) q <= #1 d; -endmodule - -// flop with enable, asynchronous reset, synchronous clear -module flopenrc #(parameter WIDTH = 8) ( - input logic clk, reset, clear, en, - input logic [WIDTH-1:0] d, - output logic [WIDTH-1:0] q); - - always_ff @(posedge clk, posedge reset) - if (reset) q <= #1 0; - else if (en) - if (clear) q <= #1 0; - else q <= #1 d; -endmodule - -// flop with enable, asynchronous reset -module flopenr #(parameter WIDTH = 8) ( - input logic clk, reset, en, - input logic [WIDTH-1:0] d, - output logic [WIDTH-1:0] q); - - always_ff @(posedge clk, posedge reset) - if (reset) q <= #1 0; - else if (en) q <= #1 d; -endmodule -/* -// flop with enable, asynchronous load -module flopenl #(parameter WIDTH = 8, parameter type TYPE=logic [WIDTH-1:0]) ( - input logic clk, load, en, - input TYPE d, - input TYPE val, - output TYPE q); - - always_ff @(posedge clk, posedge load) - if (load) q <= #1 val; - else if (en) q <= #1 d; -endmodule -*/ -// flop with asynchronous reset, synchronous clear -module floprc #(parameter WIDTH = 8) ( - input logic clk, - input logic reset, - input logic clear, - input logic [WIDTH-1:0] d, - output logic [WIDTH-1:0] q); - - always_ff @(posedge clk, posedge reset) - if (reset) q <= #1 0; - else - if (clear) q <= #1 0; - else q <= #1 d; -endmodule - - diff --git a/wally-pipelined/src/muldiv/div/div64_sim/iter32.do b/wally-pipelined/src/muldiv/div/div64_sim/iter32.do deleted file mode 100755 index d6ae858ae..000000000 --- a/wally-pipelined/src/muldiv/div/div64_sim/iter32.do +++ /dev/null @@ -1,50 +0,0 @@ -# Copyright 1991-2007 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog div.sv test_iter32.sv - -# start and run simulation -vsim -voptargs=+acc work.tb - - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation -run 9586700ns -quit diff --git a/wally-pipelined/src/muldiv/div/div64_sim/iter64.do b/wally-pipelined/src/muldiv/div/div64_sim/iter64.do deleted file mode 100755 index 435b80199..000000000 --- a/wally-pipelined/src/muldiv/div/div64_sim/iter64.do +++ /dev/null @@ -1,50 +0,0 @@ -# Copyright 1991-2007 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog mux.sv flop.sv div.sv test_iter64.sv - -# start and run simulation -vsim -voptargs=+acc work.tb - - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation -run 9586700ns -quit diff --git a/wally-pipelined/src/muldiv/div/div64_sim/test_iter32.sv b/wally-pipelined/src/muldiv/div/div64_sim/test_iter32.sv deleted file mode 100755 index 94a42c211..000000000 --- a/wally-pipelined/src/muldiv/div/div64_sim/test_iter32.sv +++ /dev/null @@ -1,74 +0,0 @@ -module tb; - - logic [31:0] N, D; - logic clk; - logic reset; - logic start; - - logic [31:0] Q; - logic [31:0] rem0; - logic div0; - logic done; - logic divdone; - - integer handle3; - integer desc3; - integer i; - - bit [31:0] Ncomp; - bit [31:0] Dcomp; - bit [31:0] Qcomp; - bit [31:0] Rcomp; - - logic [7:0] count [0:15]; - - int32div dut (Q, done, divdone, rem0, div0, N, D, clk, reset, start); - - initial - begin - clk = 1'b0; - forever #5 clk = ~clk; - end - - initial - begin - handle3 = $fopen("iter32.out"); - #8000000 $finish; - end - - always @(posedge clk, posedge reset) - begin - desc3 = handle3; - #0 start = 1'b0; - #0 reset = 1'b1; - #30 reset = 1'b0; - for (i=0; i<2; i=i+1) - begin - N = $random; - D = $random; - start <= 1'b1; - // Wait 2 cycles (to be sure) - repeat (2) - @(posedge clk); - start <= 1'b0; - repeat (25) - @(posedge clk); - Ncomp = N; - Dcomp = D; - Qcomp = Ncomp/Dcomp; - Rcomp = Ncomp%Dcomp; - $fdisplay(desc3, "%h %h %h %h || %h %h || %b %b", - N, D, Q, rem0, Qcomp, Rcomp, - (Q==Qcomp), (rem0==Rcomp)); - end // for (i=0; i<2, i=i+1) - - - end - -endmodule // tb - - - - - - diff --git a/wally-pipelined/src/muldiv/div/div64_sim/test_iter64.sv b/wally-pipelined/src/muldiv/div/div64_sim/test_iter64.sv deleted file mode 100755 index a194c1311..000000000 --- a/wally-pipelined/src/muldiv/div/div64_sim/test_iter64.sv +++ /dev/null @@ -1,72 +0,0 @@ -module tb; - - logic [63:0] N, D; - logic clk; - logic reset; - logic start; - - logic [63:0] Q; - logic [63:0] rem0; - logic div0; - logic done; - logic divdone; - - integer handle3; - integer desc3; - integer i; - - bit [63:0] Ncomp; - bit [63:0] Dcomp; - bit [63:0] Qcomp; - bit [63:0] Rcomp; - - logic [7:0] count [0:15]; - - div dut (Q, done, divdone, rem0, div0, N, D, clk, reset, start); - - initial - begin - clk = 1'b0; - forever #5 clk = ~clk; - end - - initial - begin - handle3 = $fopen("iter64.out"); - #8000000 $finish; - end - - always @(posedge clk, posedge reset) - begin - desc3 = handle3; - #0 start = 1'b0; - #0 reset = 1'b1; - #30 reset = 1'b0; - for (i=0; i<2; i=i+1) - begin - N = $random; - D = $random; - start <= 1'b1; - // Wait 2 cycles (to be sure) - repeat (2) - @(posedge clk); - start <= 1'b0; - repeat (41) - @(posedge clk); - Ncomp = N; - Dcomp = D; - Qcomp = Ncomp/Dcomp; - Rcomp = Ncomp%Dcomp; - $fdisplay(desc3, "%h %h %h %h || %h %h || %b %b", - N, D, Q, rem0, Qcomp, Rcomp, - (Q==Qcomp), (rem0==Rcomp)); - end // for (i=0; i<2, i=i+1) - end - -endmodule // tb - - - - - - diff --git a/wally-pipelined/src/muldiv/div/divide4x32.sv b/wally-pipelined/src/muldiv/div/divide4x32.sv deleted file mode 100755 index c5c311701..000000000 --- a/wally-pipelined/src/muldiv/div/divide4x32.sv +++ /dev/null @@ -1,1006 +0,0 @@ -module int32div (Q, done, divdone, rem0, div0, N, D, clk, reset, start); - - input logic [31:0] N, D; - input logic clk; - input logic reset; - input logic start; - - output logic [31:0] Q; - output logic [31:0] rem0; - output logic div0; - output logic done; - output logic divdone; - - logic enable; - logic state0; - logic V; - logic [5:0] Num; - logic [4:0] P, NumIter, RemShift; - logic [31:0] op1, op2, op1shift, Rem5; - logic [32:0] Qd, Rd, Qd2, Rd2; - logic [3:0] quotient; - logic otfzero; - - // Divider goes the distance to 19 cycles - // (thanks the evil divisor for D = 0x1) - // but could theoretically be stopped when - // divdone is asserted. The enable signal - // turns off register storage thus invalidating - // any future cycles. - - // Shift D, if needed (for integer) - // needed to allow qst to be in range for integer - // division [1,2) and allow integer divide to work. - // - // The V or valid bit can be used to determine if D - // is 0 and thus a divide by 0 exception. This div0 - // exception is given to FSM to tell the operation to - // quit gracefully. - - // div0 produced output errors have untested results - // (it is assumed the OS would handle some output) - - lz32 p1 (P, V, D); - shifter_l32 p2 (op2, D, P); - assign op1 = N; - assign div0 = ~V; - - // Brent-Kung adder chosen for the heck of it and - // since so small (maybe could have used a RCA) - - // #iter: N = m+v+s = m+(s+2) = m+2+s (mod k = 0) - // v = 2 since \rho < 1 (add 4 to make sure its a ceil) - adder #(6) cpa1 ({1'b0, P}, - {3'h0, shiftResult, ~shiftResult,1'b0}, - Num); - - // Determine whether need to add just Q/Rem - assign shiftResult = P[0]; - // div by 2 (ceil) - assign NumIter = Num[5:1]; - assign RemShift = P; - - // FSM to control integer divider - // assume inputs are postive edge and - // datapath (divider) is negative edge - fsm32 fsm1 (enablev, state0v, donev, divdonev, otfzerov, - start, div0, NumIter, ~clk, reset); - - flopr #(1) rega (~clk, reset, donev, done); - flopr #(1) regb (~clk, reset, divdonev, divdone); - flopr #(1) regc (~clk, reset, otfzerov, otfzero); - flopr #(1) regd (~clk, reset, enablev, enable); - flopr #(1) rege (~clk, reset, state0v, state0); - - // To obtain a correct remainder the last bit of the - // quotient has to be aligned with a radix-r boundary. - // Since the quotient is in the range 1/2 < q < 2 (one - // integer bit and m fractional bits), this is achieved by - // shifting N right by v+s so that (m+v+s) mod k = 0. And, - // the quotient has to be aligned to the integer position. - - // Used a Brent-Kung for no reason (just wanted prefix -- might - // have gotten away with a RCA) - - // Actual divider unit FIXME: r16 (jes) - divide4x32 p3 (Qd, Rd, quotient, op1, op2, clk, reset, state0, - enable, otfzero, shiftResult); - - // Storage registers to hold contents stable - flopenr #(33) reg3 (clk, reset, enable, Rd, Rd2); - flopenr #(33) reg4 (clk, reset, enable, Qd, Qd2); - - // Probably not needed - just assigns results - assign Q = Qd2[31:0]; - assign Rem5 = Rd2[32:1]; - - // Adjust remainder by m (no need to adjust by - // n ln(r) - shifter_r32 p4 (rem0, Rem5, RemShift); - -endmodule // int32div - -module divide4x32 (Q, rem0, quotient, op1, op2, clk, reset, state0, - enable, otfzero, shiftResult); - - input logic [31:0] op1, op2; - input logic clk, state0; - input logic reset; - input logic enable; - input logic otfzero; - input logic shiftResult; - - output logic [32:0] rem0; - output logic [32:0] Q; - output logic [3:0] quotient; - - logic [35:0] Sum, Carry; - logic [32:0] Qstar; - logic [32:0] QMstar; - logic [7:0] qtotal; - logic [35:0] SumN, CarryN, SumN2, CarryN2; - logic [35:0] divi1, divi2, divi1c, divi2c, dive1; - logic [35:0] mdivi_temp, mdivi; - logic zero; - logic [1:0] qsel; - logic [1:0] Qin, QMin; - logic CshiftQ, CshiftQM; - logic [35:0] rem1, rem2, rem3; - logic [35:0] SumR, CarryR; - logic [32:0] Qt; - - // Create one's complement values of Divisor (for q*D) - assign divi1 = {3'h0, op2, 1'b0}; - assign divi2 = {2'h0, op2, 2'b0}; - assign divi1c = ~divi1; - assign divi2c = ~divi2; - // Shift x1 if not mod k - mux2 #(36) mx1 ({3'b000, op1, 1'b0}, {4'h0, op1}, shiftResult, dive1); - - // I I I . F F F F F ... (Robertson Criteria - \rho * qmax * D) - mux2 #(36) mx2 ({CarryN2[33:0], 2'h0}, 36'h0, state0, CarryN); - mux2 #(36) mx3 ({SumN2[33:0], 2'h0}, dive1, state0, SumN); - // Simplify QST - adder #(8) cpa1 (SumN[35:28], CarryN[35:28], qtotal); - // q = {+2, +1, -1, -2} else q = 0 - qst4 pd1 (qtotal[7:1], divi1[31:29], quotient); - assign ulp = quotient[2]|quotient[3]; - assign zero = ~(quotient[3]|quotient[2]|quotient[1]|quotient[0]); - // Map to binary encoding - assign qsel[1] = quotient[3]|quotient[2]; - assign qsel[0] = quotient[3]|quotient[1]; - mux4 #(36) mx4 (divi2, divi1, divi1c, divi2c, qsel, mdivi_temp); - mux2 #(36) mx5 (mdivi_temp, 36'h0, zero, mdivi); - csa #(36) csa1 (mdivi, SumN, {CarryN[35:1], ulp}, Sum, Carry); - // regs : save CSA - flopenr #(36) reg1 (clk, reset, enable, Sum, SumN2); - flopenr #(36) reg2 (clk, reset, enable, Carry, CarryN2); - // OTF - ls_control otf1 (quotient, Qin, QMin, CshiftQ, CshiftQM); - otf #(33) otf2 (Qin, QMin, CshiftQ, CshiftQM, clk, - otfzero, enable, Qstar, QMstar); - - // Correction and generation of Remainder - adder #(36) cpa2 (SumN2[35:0], CarryN2[35:0], rem1); - // Add back +D as correction - csa #(36) csa2 (CarryN2[35:0], SumN2[35:0], divi1, SumR, CarryR); - adder #(36) cpa3 (SumR, CarryR, rem2); - // Choose remainder (Rem or Rem+D) - mux2 #(36) mx6 (rem1, rem2, rem1[35], rem3); - // Choose correct Q or QM - mux2 #(33) mx7 (Qstar, QMstar, rem1[35], Qt); - // Final results - assign rem0 = rem3[32:0]; - assign Q = Qt; - -endmodule // divide4x32 - -module ls_control (quot, Qin, QMin, CshiftQ, CshiftQM); - - input logic [3:0] quot; - - output logic [1:0] Qin; - output logic [1:0] QMin; - output logic CshiftQ; - output logic CshiftQM; - - assign Qin[1] = (quot[1]) | (quot[3]) | (quot[0]); - assign Qin[0] = (quot[1]) | (quot[2]); - assign QMin[1] = (quot[1]) | (!quot[3]&!quot[2]&!quot[1]&!quot[0]); - assign QMin[0] = (quot[3]) | (quot[0]) | - (!quot[3]&!quot[2]&!quot[1]&!quot[0]); - assign CshiftQ = (quot[1]) | (quot[0]); - assign CshiftQM = (quot[3]) | (quot[2]); - - endmodule - -module otf #(parameter WIDTH=8) - (Qin, QMin, CshiftQ, CshiftQM, clk, reset, enable, R2Q, R1Q); - - input logic [1:0] Qin, QMin; - input logic CshiftQ, CshiftQM; - input logic clk; - input logic reset; - input logic enable; - - output logic [WIDTH-1:0] R2Q; - output logic [WIDTH-1:0] R1Q; - - logic [WIDTH-1:0] Qstar, QMstar; - logic [WIDTH-1:0] M1Q, M2Q; - - // QM - mux2 #(WIDTH) m1 (QMstar, Qstar, CshiftQM, M1Q); - flopenr #(WIDTH) r1 (clk, reset, enable, {M1Q[WIDTH-3:0], QMin}, R1Q); - // Q - mux2 #(WIDTH) m2 (Qstar, QMstar, CshiftQ, M2Q); - flopenr #(WIDTH) r2 (clk, reset, enable, {M2Q[WIDTH-3:0], Qin}, R2Q); - - assign Qstar = R2Q; - assign QMstar = R1Q; - - endmodule // otf8 - - module adder #(parameter WIDTH=8) (input logic [WIDTH-1:0] a, b, - output logic [WIDTH-1:0] y); - assign y = a + b; - - endmodule // adder - - module fa (input logic a, b, c, output logic sum, carry); - - assign sum = a^b^c; - assign carry = a&b|a&c|b&c; - - endmodule // fa - -// Modular Carry-Save Adder - module csa #(parameter WIDTH=8) (input logic [WIDTH-1:0] a, b, c, - output logic [WIDTH-1:0] sum, carry); - - logic [WIDTH:0] carry_temp; - genvar i; - generate - for (i=0;i B. LT and GT are both '0' if A = B. - -module magcompare2b (LT, GT, A, B); - - input logic [1:0] A; - input logic [1:0] B; - - output logic LT; - output logic GT; - - // Determine if A < B using a minimized sum-of-products expression - assign LT = ~A[1]&B[1] | ~A[1]&~A[0]&B[0] | ~A[0]&B[1]&B[0]; - // Determine if A > B using a minimized sum-of-products expression - assign GT = A[1]&~B[1] | A[1]&A[0]&~B[0] | A[0]&~B[1]&~B[0]; - -endmodule // magcompare2b - -// J. E. Stine and M. J. Schulte, "A combined two's complement and -// floating-point comparator," 2005 IEEE International Symposium on -// Circuits and Systems, Kobe, 2005, pp. 89-92 Vol. 1. -// doi: 10.1109/ISCAS.2005.1464531 - -module magcompare8 (LT, EQ, A, B); - - input logic [7:0] A; - input logic [7:0] B; - - logic [3:0] s; - logic [3:0] t; - logic [1:0] u; - logic [1:0] v; - logic GT; - //wire LT; - - output logic EQ; - output logic LT; - - magcompare2b mag1 (s[0], t[0], A[1:0], B[1:0]); - magcompare2b mag2 (s[1], t[1], A[3:2], B[3:2]); - magcompare2b mag3 (s[2], t[2], A[5:4], B[5:4]); - magcompare2b mag4 (s[3], t[3], A[7:6], B[7:6]); - - magcompare2b mag5 (u[0], v[0], t[1:0], s[1:0]); - magcompare2b mag6 (u[1], v[1], t[3:2], s[3:2]); - - magcompare2b mag7 (LT, GT, v[1:0], u[1:0]); - - assign EQ = ~(GT | LT); - -endmodule // magcompare8 diff --git a/wally-pipelined/src/muldiv/div/divide4x64.sv b/wally-pipelined/src/muldiv/div/divide4x64.sv deleted file mode 100755 index 4b474c654..000000000 --- a/wally-pipelined/src/muldiv/div/divide4x64.sv +++ /dev/null @@ -1,1453 +0,0 @@ -module int64div (Qf, done, divdone, remf, div0, N, D, clk, reset, start); - - input logic [63:0] N, D; - input logic clk; - input logic reset; - input logic start; - - output logic [63:0] Qf; - output logic [63:0] remf; - output logic div0; - output logic done; - output logic divdone; - - logic enable; - logic state0; - logic V; - logic [7:0] Num; - logic [5:0] P, NumIter, RemShift; - logic [63:0] op1, op2, op1shift, Rem5; - logic [64:0] Qd, Rd, Qd2, Rd2; - logic [63:0] Q, rem0; - logic [3:0] quotient; - logic otfzero; - logic shiftResult; - - // Divider goes the distance to 37 cycles - // (thanks the evil divisor for D = 0x1) - // but could theoretically be stopped when - // divdone is asserted. The enable signal - // turns off register storage thus invalidating - // any future cycles. - - // Shift D, if needed (for integer) - // needed to allow qst to be in range for integer - // division [1,2) and allow integer divide to work. - // - // The V or valid bit can be used to determine if D - // is 0 and thus a divide by 0 exception. This div0 - // exception is given to FSM to tell the operation to - // quit gracefully. - - // div0 produced output errors have untested results - // (it is assumed the OS would handle some output) - - lz64 p1 (P, V, D); - shifter_l64 p2 (op2, D, P); - assign op1 = N; - assign div0 = ~V; - - // Brent-Kung adder chosen for the heck of it and - // since so small (maybe could have used a RCA) - - // #iter: N = m+v+s = m+(s+2) = m+2+s (mod k = 0) - // v = 2 since \rho < 1 (add 4 to make sure its a ceil) - adder #(8) cpa1 ({2'b0, P}, - {5'h0, shiftResult, ~shiftResult, 1'b0}, - Num); - - // Determine whether need to add just Q/Rem - assign shiftResult = P[0]; - // div by 2 (ceil) - assign NumIter = Num[6:1]; - assign RemShift = P; - - // FSM to control integer divider - // assume inputs are postive edge and - // datapath (divider) is negative edge - fsm64 fsm1 (enablev, state0v, donev, divdonev, otfzerov, - start, div0, NumIter, ~clk, reset); - - flopr #(1) rega (~clk, reset, donev, done); - flopr #(1) regb (~clk, reset, divdonev, divdone); - flopr #(1) regc (~clk, reset, otfzerov, otfzero); - flopr #(1) regd (~clk, reset, enablev, enable); - flopr #(1) rege (~clk, reset, state0v, state0); - - // To obtain a correct remainder the last bit of the - // quotient has to be aligned with a radix-r boundary. - // Since the quotient is in the range 1/2 < q < 2 (one - // integer bit and m fractional bits), this is achieved by - // shifting N right by v+s so that (m+v+s) mod k = 0. And, - // the quotient has to be aligned to the integer position. - - // Actual divider unit FIXME: r16 (jes) - divide4x64 p3 (Qd, Rd, quotient, op1, op2, clk, reset, state0, - enable, otfzero, shiftResult); - - // Storage registers to hold contents stable - flopenr #(65) reg3 (clk, reset, enable, Rd, Rd2); - flopenr #(65) reg4 (clk, reset, enable, Qd, Qd2); - - // Probably not needed - just assigns results - assign Q = Qd2[63:0]; - assign Rem5 = Rd2[64:1]; - - // Adjust remainder by m (no need to adjust by - // n lg(r) - shifter_r64 p4 (rem0, Rem5, RemShift); - - // RISC-V has exceptions for divide by 0 (see Table 6.1 of spec) - mux2 #(64) exc1 (Q, {64{1'b1}}, div0, Qf); - mux2 #(64) exc2 (rem0, op1, div0, remf); - -endmodule // int32div - -module divide4x64 (Q, rem0, quotient, op1, op2, clk, reset, state0, - enable, otfzero, shiftResult); - - input logic [63:0] op1, op2; - input logic clk, state0; - input logic reset; - input logic enable; - input logic otfzero; - input logic shiftResult; - - output logic [64:0] rem0; - output logic [64:0] Q; - output logic [3:0] quotient; - - logic [67:0] Sum, Carry; - logic [64:0] Qstar; - logic [64:0] QMstar; - logic [7:0] qtotal; - logic [67:0] SumN, CarryN, SumN2, CarryN2; - logic [67:0] divi1, divi2, divi1c, divi2c, dive1; - logic [67:0] mdivi_temp, mdivi; - logic zero; - logic [1:0] qsel; - logic [1:0] Qin, QMin; - logic CshiftQ, CshiftQM; - logic [67:0] rem1, rem2, rem3; - logic [67:0] SumR, CarryR; - logic [64:0] Qt; - - // Create one's complement values of Divisor (for q*D) - assign divi1 = {3'h0, op2, 1'b0}; - assign divi2 = {2'h0, op2, 2'b0}; - assign divi1c = ~divi1; - assign divi2c = ~divi2; - // Shift x1 if not mod k - mux2 #(68) mx1 ({3'b000, op1, 1'b0}, {4'h0, op1}, shiftResult, dive1); - - // I I I . F F F F F ... (Robertson Criteria - \rho * qmax * D) - mux2 #(68) mx2 ({CarryN2[65:0], 2'h0}, 68'h0, state0, CarryN); - mux2 #(68) mx3 ({SumN2[65:0], 2'h0}, dive1, state0, SumN); - // Simplify QST - adder #(8) cpa1 (SumN[67:60], CarryN[67:60], qtotal); - // q = {+2, +1, -1, -2} else q = 0 - qst4 pd1 (qtotal[7:1], divi1[63:61], quotient); - assign ulp = quotient[2]|quotient[3]; - assign zero = ~(quotient[3]|quotient[2]|quotient[1]|quotient[0]); - // Map to binary encoding - assign qsel[1] = quotient[3]|quotient[2]; - assign qsel[0] = quotient[3]|quotient[1]; - mux4 #(68) mx4 (divi2, divi1, divi1c, divi2c, qsel, mdivi_temp); - mux2 #(68) mx5 (mdivi_temp, 68'h0, zero, mdivi); - csa #(68) csa1 (mdivi, SumN, {CarryN[67:1], ulp}, Sum, Carry); - // regs : save CSA - flopenr #(68) reg1 (clk, reset, enable, Sum, SumN2); - flopenr #(68) reg2 (clk, reset, enable, Carry, CarryN2); - // OTF - ls_control otf1 (quotient, Qin, QMin, CshiftQ, CshiftQM); - otf #(65) otf2 (Qin, QMin, CshiftQ, CshiftQM, clk, - otfzero, enable, Qstar, QMstar); - - // Correction and generation of Remainder - adder #(68) cpa2 (SumN2[67:0], CarryN2[67:0], rem1); - // Add back +D as correction - csa #(68) csa2 (CarryN2[67:0], SumN2[67:0], divi1, SumR, CarryR); - adder #(68) cpa3 (SumR, CarryR, rem2); - // Choose remainder (Rem or Rem+D) - mux2 #(68) mx6 (rem1, rem2, rem1[67], rem3); - // Choose correct Q or QM - mux2 #(65) mx7 (Qstar, QMstar, rem1[67], Qt); - // Final results - assign rem0 = rem3[64:0]; - assign Q = Qt; - -endmodule // divide4x64 - -module ls_control (quot, Qin, QMin, CshiftQ, CshiftQM); - - input logic [3:0] quot; - - output logic [1:0] Qin; - output logic [1:0] QMin; - output logic CshiftQ; - output logic CshiftQM; - - // Load/Store Control for OTF - assign Qin[1] = (quot[1]) | (quot[3]) | (quot[0]); - assign Qin[0] = (quot[1]) | (quot[2]); - assign QMin[1] = (quot[1]) | (!quot[3]&!quot[2]&!quot[1]&!quot[0]); - assign QMin[0] = (quot[3]) | (quot[0]) | - (!quot[3]&!quot[2]&!quot[1]&!quot[0]); - assign CshiftQ = (quot[1]) | (quot[0]); - assign CshiftQM = (quot[3]) | (quot[2]); - -endmodule - -// On-the-fly Conversion per Ercegovac/Lang - -module otf #(parameter WIDTH=8) - (Qin, QMin, CshiftQ, CshiftQM, clk, reset, enable, R2Q, R1Q); - - input logic [1:0] Qin, QMin; - input logic CshiftQ, CshiftQM; - input logic clk; - input logic reset; - input logic enable; - - output logic [WIDTH-1:0] R2Q; - output logic [WIDTH-1:0] R1Q; - - logic [WIDTH-1:0] Qstar, QMstar; - logic [WIDTH-1:0] M1Q, M2Q; - - // QM - mux2 #(WIDTH) m1 (QMstar, Qstar, CshiftQM, M1Q); - flopenr #(WIDTH) r1 (clk, reset, enable, {M1Q[WIDTH-3:0], QMin}, R1Q); - // Q - mux2 #(WIDTH) m2 (Qstar, QMstar, CshiftQ, M2Q); - flopenr #(WIDTH) r2 (clk, reset, enable, {M2Q[WIDTH-3:0], Qin}, R2Q); - - assign Qstar = R2Q; - assign QMstar = R1Q; - -endmodule // otf8 - -module adder #(parameter WIDTH=8) (input logic [WIDTH-1:0] a, b, - output logic [WIDTH-1:0] y); - - assign y = a + b; - -endmodule // adder - -module fa (input logic a, b, c, output logic sum, carry); - - assign sum = a^b^c; - assign carry = a&b|a&c|b&c; - -endmodule // fa - -module csa #(parameter WIDTH=8) (input logic [WIDTH-1:0] a, b, c, - output logic [WIDTH-1:0] sum, carry); - - logic [WIDTH:0] carry_temp; - genvar i; - generate - for (i=0;i B. LT and GT are both '0' if A = B. - -module magcompare2b (LT, GT, A, B); - - input logic [1:0] A; - input logic [1:0] B; - - output logic LT; - output logic GT; - - // Determine if A < B using a minimized sum-of-products expression - assign LT = ~A[1]&B[1] | ~A[1]&~A[0]&B[0] | ~A[0]&B[1]&B[0]; - // Determine if A > B using a minimized sum-of-products expression - assign GT = A[1]&~B[1] | A[1]&A[0]&~B[0] | A[0]&~B[1]&~B[0]; - -endmodule // magcompare2b - -// J. E. Stine and M. J. Schulte, "A combined two's complement and -// floating-point comparator," 2005 IEEE International Symposium on -// Circuits and Systems, Kobe, 2005, pp. 89-92 Vol. 1. -// doi: 10.1109/ISCAS.2005.1464531 - -module magcompare8 (LT, EQ, A, B); - - input logic [7:0] A; - input logic [7:0] B; - - logic [3:0] s; - logic [3:0] t; - logic [1:0] u; - logic [1:0] v; - logic GT; - //wire LT; - - output logic EQ; - output logic LT; - - magcompare2b mag1 (s[0], t[0], A[1:0], B[1:0]); - magcompare2b mag2 (s[1], t[1], A[3:2], B[3:2]); - magcompare2b mag3 (s[2], t[2], A[5:4], B[5:4]); - magcompare2b mag4 (s[3], t[3], A[7:6], B[7:6]); - - magcompare2b mag5 (u[0], v[0], t[1:0], s[1:0]); - magcompare2b mag6 (u[1], v[1], t[3:2], s[3:2]); - - magcompare2b mag7 (LT, GT, v[1:0], u[1:0]); - - assign EQ = ~(GT | LT); - -endmodule // magcompare8 diff --git a/wally-pipelined/src/muldiv/div/imperas-riscv-tests b/wally-pipelined/src/muldiv/div/imperas-riscv-tests deleted file mode 160000 index c171bf199..000000000 --- a/wally-pipelined/src/muldiv/div/imperas-riscv-tests +++ /dev/null @@ -1 +0,0 @@ -Subproject commit c171bf1999a3cf7e8cd26511dfcf794d1498e5a1 diff --git a/wally-pipelined/src/muldiv/div/int32div.do b/wally-pipelined/src/muldiv/div/int32div.do deleted file mode 100755 index e83f307ad..000000000 --- a/wally-pipelined/src/muldiv/div/int32div.do +++ /dev/null @@ -1,114 +0,0 @@ -# Copyright 1991-2007 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog mux_div.sv shifters_div.sv divide4x32.sv test_int32div.sv - -# start and run simulation -vsim -voptargs=+acc work.tb - -view list -view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively -add wave -noupdate -divider -height 32 "Control Signals" -add wave -hex -color gold /tb/clk -add wave -hex -color #0080ff /tb/reset -add wave -hex -color #0080ff /tb/start -add wave -hex -color #0080ff /tb/done -add wave -hex -color #0080ff /tb/divdone -add wave -noupdate -divider -height 32 "Key Parts" -add wave -unsigned /tb/dut/NumIter -add wave -unsigned /tb/dut/RemShift -add wave -unsigned /tb/dut/Qd2 -add wave -unsigned /tb/dut/Rd2 -add wave -unsigned /tb/dut/rem0 -add wave -unsigned /tb/dut/Q -add wave -unsigned /tb/dut/P -add wave -unsigned /tb/dut/shiftResult -add wave -noupdate -divider -height 32 "FSM" -add wave -hex /tb/dut/fsm1/CURRENT_STATE -add wave -hex /tb/dut/fsm1/NEXT_STATE -add wave -hex -color #0080ff /tb/dut/fsm1/start -add wave -hex -color #0080ff /tb/dut/fsm1/state0 -add wave -hex -color #0080ff /tb/dut/fsm1/done -add wave -hex -color #0080ff /tb/dut/fsm1/en -add wave -hex -color #0080ff /tb/dut/fsm1/divdone -add wave -hex -color #0080ff /tb/dut/fsm1/reset -add wave -hex -color #0080ff /tb/dut/fsm1/otfzero -add wave -hex -color #0080ff /tb/dut/fsm1/LT -add wave -hex -color #0080ff /tb/dut/fsm1/EQ -add wave -hex -color gold /tb/dut/fsm1/clk -add wave -noupdate -divider -height 32 "Datapath" -add wave -hex /tb/dut/N -add wave -hex /tb/dut/D -add wave -hex /tb/dut/reset -add wave -hex /tb/dut/start -add wave -hex /tb/dut/Q -add wave -hex /tb/dut/rem0 -add wave -hex /tb/dut/div0 -add wave -hex /tb/dut/done -add wave -hex /tb/dut/divdone -add wave -hex /tb/dut/enable -add wave -hex /tb/dut/state0 -add wave -hex /tb/dut/V -add wave -hex /tb/dut/Num -add wave -hex /tb/dut/P -add wave -hex /tb/dut/NumIter -add wave -hex /tb/dut/RemShift -add wave -hex /tb/dut/op1 -add wave -hex /tb/dut/op2 -add wave -hex /tb/dut/op1shift -add wave -hex /tb/dut/Rem5 -add wave -hex /tb/dut/Qd -add wave -hex /tb/dut/Rd -add wave -hex /tb/dut/Qd2 -add wave -hex /tb/dut/Rd2 -add wave -hex /tb/dut/quotient -add wave -hex /tb/dut/otfzero -add wave -noupdate -divider -height 32 "Divider" -add wave -hex -r /tb/dut/p3/* - - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation -run 338ns - - diff --git a/wally-pipelined/src/muldiv/div/int64div.do b/wally-pipelined/src/muldiv/div/int64div.do deleted file mode 100755 index dc83d046f..000000000 --- a/wally-pipelined/src/muldiv/div/int64div.do +++ /dev/null @@ -1,116 +0,0 @@ -# Copyright 1991-2007 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog mux_div.sv shifters_div.sv divide4x64.sv test_int64div.sv - -# start and run simulation -vsim -voptargs=+acc work.tb - -view list -view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively -add wave -noupdate -divider -height 32 "Control Signals" -add wave -hex -color gold /tb/clk -add wave -hex -color #0080ff /tb/reset -add wave -hex -color #0080ff /tb/start -add wave -hex -color #0080ff /tb/done -add wave -hex -color #0080ff /tb/divdone -add wave -noupdate -divider -height 32 "Key Parts" -add wave -unsigned /tb/dut/NumIter -add wave -unsigned /tb/dut/RemShift -add wave -unsigned /tb/dut/Qd2 -add wave -unsigned /tb/dut/Rd2 -add wave -unsigned /tb/dut/rem0 -add wave -unsigned /tb/dut/Q -add wave -unsigned /tb/dut/P -add wave -unsigned /tb/dut/shiftResult -add wave -noupdate -divider -height 32 "FSM" -add wave -hex /tb/dut/fsm1/CURRENT_STATE -add wave -hex /tb/dut/fsm1/NEXT_STATE -add wave -hex -color #0080ff /tb/dut/fsm1/start -add wave -hex -color #0080ff /tb/dut/fsm1/state0 -add wave -hex -color #0080ff /tb/dut/fsm1/done -add wave -hex -color #0080ff /tb/dut/fsm1/en -add wave -hex -color #0080ff /tb/dut/fsm1/divdone -add wave -hex -color #0080ff /tb/dut/fsm1/reset -add wave -hex -color #0080ff /tb/dut/fsm1/otfzero -add wave -hex -color #0080ff /tb/dut/fsm1/LT -add wave -hex -color #0080ff /tb/dut/fsm1/EQ -add wave -hex -color gold /tb/dut/fsm1/clk -add wave -noupdate -divider -height 32 "Datapath" -add wave -hex /tb/dut/N -add wave -hex /tb/dut/D -add wave -hex /tb/dut/reset -add wave -hex /tb/dut/start -add wave -hex /tb/dut/Qf -add wave -hex /tb/dut/remf -add wave -hex /tb/dut/Q -add wave -hex /tb/dut/rem0 -add wave -hex /tb/dut/div0 -add wave -hex /tb/dut/done -add wave -hex /tb/dut/divdone -add wave -hex /tb/dut/enable -add wave -hex /tb/dut/state0 -add wave -hex /tb/dut/V -add wave -hex /tb/dut/Num -add wave -hex /tb/dut/P -add wave -hex /tb/dut/NumIter -add wave -hex /tb/dut/RemShift -add wave -hex /tb/dut/op1 -add wave -hex /tb/dut/op2 -add wave -hex /tb/dut/op1shift -add wave -hex /tb/dut/Rem5 -add wave -hex /tb/dut/Qd -add wave -hex /tb/dut/Rd -add wave -hex /tb/dut/Qd2 -add wave -hex /tb/dut/Rd2 -add wave -hex /tb/dut/quotient -add wave -hex /tb/dut/otfzero -add wave -noupdate -divider -height 32 "Divider" -add wave -hex -r /tb/dut/p3/* - - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 350 -configure wave -valuecolwidth 200 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation -run 538ns - - diff --git a/wally-pipelined/src/muldiv/div/iter32.do b/wally-pipelined/src/muldiv/div/iter32.do deleted file mode 100755 index 7f0f964da..000000000 --- a/wally-pipelined/src/muldiv/div/iter32.do +++ /dev/null @@ -1,50 +0,0 @@ -# Copyright 1991-2007 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog mux_div.sv shifters_div.sv divide4x32.sv test_iter32.sv - -# start and run simulation -vsim -voptargs=+acc work.tb - - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation -run 9586700ns -quit diff --git a/wally-pipelined/src/muldiv/div/iter64.do b/wally-pipelined/src/muldiv/div/iter64.do deleted file mode 100755 index c538291ea..000000000 --- a/wally-pipelined/src/muldiv/div/iter64.do +++ /dev/null @@ -1,50 +0,0 @@ -# Copyright 1991-2007 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog mux_div.sv shifters_div.sv divide4x64.sv test_iter64.sv - -# start and run simulation -vsim -voptargs=+acc work.tb - - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation -run 9586700ns -quit diff --git a/wally-pipelined/src/muldiv/div/mux_div.sv b/wally-pipelined/src/muldiv/div/mux_div.sv deleted file mode 100644 index d13045e6d..000000000 --- a/wally-pipelined/src/muldiv/div/mux_div.sv +++ /dev/null @@ -1,51 +0,0 @@ -module mux2 #(parameter WIDTH = 8) - (input logic [WIDTH-1:0] d0, d1, - input logic s, - output logic [WIDTH-1:0] y); - - assign y = s ? d1 : d0; - -endmodule // mux2 - -module mux3 #(parameter WIDTH = 8) - (input logic [WIDTH-1:0] d0, d1, d2, - input logic [1:0] s, - output logic [WIDTH-1:0] y); - - assign y = s[1] ? d2 : (s[0] ? d1 : d0); - -endmodule // mux3 - -module mux4 #(parameter WIDTH = 8) - (input logic [WIDTH-1:0] d0, d1, d2, d3, - input logic [1:0] s, - output logic [WIDTH-1:0] y); - - assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0); - -endmodule // mux4 - -module mux21x32 (Z, A, B, Sel); - - input logic [31:0] A; - input logic [31:0] B; - input logic Sel; - - output logic [31:0] Z; - - assign Z = Sel ? B : A; - -endmodule // mux21x32 - -module mux21x64 (Z, A, B, Sel); - - input logic [63:0] A; - input logic [63:0] B; - input logic Sel; - - output logic [63:0] Z; - - assign Z = Sel ? B : A; - -endmodule // mux21x64 - diff --git a/wally-pipelined/src/muldiv/div/shift.sv b/wally-pipelined/src/muldiv/div/shift.sv deleted file mode 100644 index 412cee32f..000000000 --- a/wally-pipelined/src/muldiv/div/shift.sv +++ /dev/null @@ -1,151 +0,0 @@ -module shifter_l64 (Z, A, Shift); - - input logic [63:0] A; - input logic [5:0] Shift; - - logic [63:0] stage1; - logic [63:0] stage2; - logic [63:0] stage3; - logic [63:0] stage4; - logic [63:0] stage5; - logic [31:0] thirtytwozeros = 32'h0; - logic [15:0] sixteenzeros = 16'h0; - logic [ 7:0] eightzeros = 8'h0; - logic [ 3:0] fourzeros = 4'h0; - logic [ 1:0] twozeros = 2'b00; - logic onezero = 1'b0; - - output logic [63:0] Z; - - mux2 #(64) mx01(A, {A[31:0], thirtytwozeros}, Shift[5], stage1); - mux2 #(64) mx02(stage1, {stage1[47:0], sixteenzeros}, Shift[4], stage2); - mux2 #(64) mx03(stage2, {stage2[55:0], eightzeros}, Shift[3], stage3); - mux2 #(64) mx04(stage3, {stage3[59:0], fourzeros}, Shift[2], stage4); - mux2 #(64) mx05(stage4, {stage4[61:0], twozeros}, Shift[1], stage5); - mux2 #(64) mx06(stage5, {stage5[62:0], onezero}, Shift[0], Z); - -endmodule // shifter_l64 - -module shifter_r64 (Z, A, Shift); - - input logic [63:0] A; - input logic [5:0] Shift; - - logic [63:0] stage1; - logic [63:0] stage2; - logic [63:0] stage3; - logic [63:0] stage4; - logic [63:0] stage5; - logic [31:0] thirtytwozeros = 32'h0; - logic [15:0] sixteenzeros = 16'h0; - logic [ 7:0] eightzeros = 8'h0; - logic [ 3:0] fourzeros = 4'h0; - logic [ 1:0] twozeros = 2'b00; - logic onezero = 1'b0; - - output logic [63:0] Z; - - mux2 #(64) mx01(A, {thirtytwozeros, A[63:32]}, Shift[5], stage1); - mux2 #(64) mx02(stage1, {sixteenzeros, stage1[63:16]}, Shift[4], stage2); - mux2 #(64) mx03(stage2, {eightzeros, stage2[63:8]}, Shift[3], stage3); - mux2 #(64) mx04(stage3, {fourzeros, stage3[63:4]}, Shift[2], stage4); - mux2 #(64) mx05(stage4, {twozeros, stage4[63:2]}, Shift[1], stage5); - mux2 #(64) mx06(stage5, {onezero, stage5[63:1]}, Shift[0], Z); - -endmodule // shifter_r64 - -module shifter_l32 (Z, A, Shift); - - input logic [31:0] A; - input logic [4:0] Shift; - - logic [31:0] stage1; - logic [31:0] stage2; - logic [31:0] stage3; - logic [31:0] stage4; - logic [15:0] sixteenzeros = 16'h0; - logic [ 7:0] eightzeros = 8'h0; - logic [ 3:0] fourzeros = 4'h0; - logic [ 1:0] twozeros = 2'b00; - logic onezero = 1'b0; - - output logic [31:0] Z; - - mux2 #(32) mx01(A, {A[15:0], sixteenzeros}, Shift[4], stage1); - mux2 #(32) mx02(stage1, {stage1[23:0], eightzeros}, Shift[3], stage2); - mux2 #(32) mx03(stage2, {stage2[27:0], fourzeros}, Shift[2], stage3); - mux2 #(32) mx04(stage3, {stage3[29:0], twozeros}, Shift[1], stage4); - mux2 #(32) mx05(stage4, {stage4[30:0], onezero}, Shift[0], Z); - -endmodule // shifter_l32 - -module shifter_r32 (Z, A, Shift); - - input logic [31:0] A; - input logic [4:0] Shift; - - logic [31:0] stage1; - logic [31:0] stage2; - logic [31:0] stage3; - logic [31:0] stage4; - logic [15:0] sixteenzeros = 16'h0; - logic [ 7:0] eightzeros = 8'h0; - logic [ 3:0] fourzeros = 4'h0; - logic [ 1:0] twozeros = 2'b00; - logic onezero = 1'b0; - - output logic [31:0] Z; - - mux2 #(32) mx01(A, {sixteenzeros, A[31:16]}, Shift[4], stage1); - mux2 #(32) mx02(stage1, {eightzeros, stage1[31:8]}, Shift[3], stage2); - mux2 #(32) mx03(stage2, {fourzeros, stage2[31:4]}, Shift[2], stage3); - mux2 #(32) mx04(stage3, {twozeros, stage3[31:2]}, Shift[1], stage4); - mux2 #(32) mx05(stage4, {onezero, stage4[31:1]}, Shift[0], Z); - -endmodule // shifter_r32 - -`define XLEN 32 -module shift_right #(parameter WIDTH=8) (input logic [`XLEN-1:0] A, - input logic [$clog2(`XLEN)-1:0] Shift, - output logic [`XLEN-1:0] Z); - - logic [`XLEN-1:0] stage [$clog2(`XLEN):0]; - genvar i; - - assign stage[0] = A; - generate - for (i=0;i<$clog2(`XLEN);i=i+1) - begin : genbit - mux2 #(`XLEN) mux_inst (stage[i], - {{(`XLEN/(2**(i+1))){1'b0}}, stage[i][`XLEN-1:`XLEN/(2**(i+1))]}, - Shift[$clog2(`XLEN)-i-1], - stage[i+1]); - end - endgenerate - assign Z = stage[$clog2(`XLEN)]; - -endmodule // shift_right - -module shift_left #(parameter WIDTH=8) (input logic [`XLEN-1:0] A, - input logic [$clog2(`XLEN)-1:0] Shift, - output logic [`XLEN-1:0] Z); - - logic [`XLEN-1:0] stage [$clog2(`XLEN):0]; - genvar i; - - assign stage[0] = A; - generate - for (i=0;i<$clog2(`XLEN);i=i+1) - begin : genbit - mux2 #(`XLEN) mux_inst (stage[i], - {stage[i][`XLEN-1-`XLEN/(2**(i+1)):0], {(`XLEN/(2**(i+1))){1'b0}}}, - Shift[$clog2(`XLEN)-i-1], - stage[i+1]); - end - endgenerate - assign Z = stage[$clog2(`XLEN)]; - -endmodule // shift_right - - - diff --git a/wally-pipelined/src/muldiv/div/shift_left.do b/wally-pipelined/src/muldiv/div/shift_left.do deleted file mode 100755 index 0b0ce9850..000000000 --- a/wally-pipelined/src/muldiv/div/shift_left.do +++ /dev/null @@ -1,55 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog mux_div.sv shift.sv shift_left_tb.sv - -# start and run simulation -vsim -voptargs=+acc work.stimulus - -view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively -add wave -hex -r /stimulus/* - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation -run 800ns -quit diff --git a/wally-pipelined/src/muldiv/div/shift_left.out b/wally-pipelined/src/muldiv/div/shift_left.out deleted file mode 100644 index 67fedc18f..000000000 --- a/wally-pipelined/src/muldiv/div/shift_left.out +++ /dev/null @@ -1,79 +0,0 @@ -12153524 01 || 242a6a48 242a6a48 | 1 -8484d609 03 || 2426b048 2426b048 | 1 -06b97b0d 0d || 2f61a000 2f61a000 | 1 -b2c28465 12 || 11940000 11940000 | 1 -00f3e301 0d || 7c602000 7c602000 | 1 -3b23f176 1d || c0000000 c0000000 | 1 -76d457ed 0c || 457ed000 457ed000 | 1 -7cfde9f9 06 || 3f7a7e40 3f7a7e40 | 1 -e2f784c5 0a || de131400 de131400 | 1 -72aff7e5 17 || f2800000 f2800000 | 1 -8932d612 0f || 6b090000 6b090000 | 1 -793069f2 0e || 1a7c8000 1a7c8000 | 1 -f4007ae8 05 || 800f5d00 800f5d00 | 1 -2e58495c 1d || 80000000 80000000 | 1 -96ab582d 05 || d56b05a0 d56b05a0 | 1 -b1ef6263 0a || bd898c00 bd898c00 | 1 -c03b2280 00 || c03b2280 c03b2280 | 1 -557845aa 1d || 40000000 40000000 | 1 -cb203e96 13 || f4b00000 f4b00000 | 1 -86bc380d 13 || c0680000 c0680000 | 1 -359fdd6b 15 || ad600000 ad600000 | 1 -81174a02 0e || d2808000 d2808000 | 1 -0effe91d 0f || f48e8000 f48e8000 | 1 -11844923 0a || 11248c00 11248c00 | 1 -e5730aca 1c || a0000000 a0000000 | 1 -7968bdf2 0a || a2f7c800 a2f7c800 | 1 -20c4b341 18 || 41000000 41000000 | 1 -3c20f378 09 || 41e6f000 41e6f000 | 1 -75c50deb 16 || 7ac00000 7ac00000 | 1 -634bf9c6 0e || fe718000 fe718000 | 1 -de7502bc 0a || d40af000 d40af000 | 1 -85d79a0b 11 || 34160000 34160000 | 1 -42f24185 0f || 20c28000 20c28000 | 1 -9dcc603b 1a || ec000000 ec000000 | 1 -bf23327e 15 || 4fc00000 4fc00000 | 1 -78d99bf1 19 || e2000000 e2000000 | 1 -31230762 0c || 30762000 30762000 | 1 -4fa1559f 0f || aacf8000 aacf8000 | 1 -7c6da9f8 17 || fc000000 fc000000 | 1 -cfc4569f 1c || f0000000 f0000000 | 1 -adcbc05b 09 || 9780b600 9780b600 | 1 -a4ae3249 10 || 32490000 32490000 | 1 -ebfec0d7 11 || 81ae0000 81ae0000 | 1 -4b212f96 0c || 12f96000 12f96000 | 1 -e12ccec2 08 || 2ccec200 2ccec200 | 1 -bb825a77 1d || e0000000 e0000000 | 1 -090cdb12 1e || 80000000 80000000 | 1 -36e5816d 19 || da000000 da000000 | 1 -0fd28f1f 13 || 78f80000 78f80000 | 1 -42d92f85 18 || 85000000 85000000 | 1 -2dda595b 09 || b4b2b600 b4b2b600 | 1 -9ff2ae3f 0a || cab8fc00 cab8fc00 | 1 -2c156358 06 || 0558d600 0558d600 | 1 -c71a0c8e 1c || e0000000 e0000000 | 1 -7d3599fa 06 || 4d667e80 4d667e80 | 1 -39961773 03 || ccb0bb98 ccb0bb98 | 1 -9799a82f 13 || 41780000 41780000 | 1 -afd8565f 04 || fd8565f0 fd8565f0 | 1 -7bf8fdf7 0b || c7efb800 c7efb800 | 1 -f3091ae6 1a || 98000000 98000000 | 1 -14cfc129 0d || f8252000 f8252000 | 1 -ed536cda 05 || aa6d9b40 aa6d9b40 | 1 -da8ae2b5 1f || 80000000 80000000 | 1 -3cf11979 04 || cf119790 cf119790 | 1 -e8740cd0 0a || d0334000 d0334000 | 1 -55f6adab 0e || ab6ac000 ab6ac000 | 1 -6e5daddc 1a || 70000000 70000000 | 1 -fedf72fd 03 || f6fb97e8 f6fb97e8 | 1 -2b0eed56 0e || bb558000 bb558000 | 1 -b3d97667 0a || 65d99c00 65d99c00 | 1 -5b6fb9b6 18 || b6000000 b6000000 | 1 -3cd18779 18 || 79000000 79000000 | 1 -4a74bf94 13 || fca00000 fca00000 | 1 -823f2c04 19 || 08000000 08000000 | 1 -6dcb69db 0d || 6d3b6000 6d3b6000 | 1 -6cb0b7d9 0d || 16fb2000 16fb2000 | 1 -bb45e276 0a || 1789d800 1789d800 | 1 -5b172db6 15 || b6c00000 b6c00000 | 1 -a3071a46 04 || 3071a460 3071a460 | 1 diff --git a/wally-pipelined/src/muldiv/div/shift_left_tb.sv b/wally-pipelined/src/muldiv/div/shift_left_tb.sv deleted file mode 100644 index 2d5d3dad8..000000000 --- a/wally-pipelined/src/muldiv/div/shift_left_tb.sv +++ /dev/null @@ -1,71 +0,0 @@ -// -// File name : tb -// Title : test -// project : HW3 -// Library : test -// Purpose : definition of modules for testbench -// notes : -// -// Copyright Oklahoma State University -// - -// Top level stimulus module - -`timescale 1ns/1ps - -`define XLEN 32 -module stimulus; - - logic [`XLEN-1:0] A; - logic [$clog2(`XLEN)-1:0] Shift; - logic [`XLEN-1:0] Z; - logic [`XLEN-1:0] Z_corr; - - //logic [63:0] A; - //logic [5:0] Shift; - //logic [63:0] Z; - //logic [63:0] Z_corr; - //logic [63:0] Z_orig; - - - logic clk; - - integer handle3; - integer desc3; - integer i; - - // instatiate part to test - shift_left dut1 (A, Shift, Z); - assign Z_corr = (A << Shift); - - initial - begin - clk = 1'b1; - forever #5 clk = ~clk; - end - - initial - begin - handle3 = $fopen("shift_left.out"); - desc3 = handle3; - end - - initial - begin - for (i=0; i < 256; i=i+1) - begin - // Put vectors before beginning of clk - @(posedge clk) - begin - A = $random; - Shift = $random; - end - @(negedge clk) - begin - $fdisplay(desc3, "%h %h || %h %h | %b", A, Shift, Z, Z_corr, (Z == Z_corr)); - end - end // for (i=0; i < 256; i=i+1) - $finish;// - end // initial begin - -endmodule // stimulus diff --git a/wally-pipelined/src/muldiv/div/shift_right.do b/wally-pipelined/src/muldiv/div/shift_right.do deleted file mode 100755 index a41b7bfa7..000000000 --- a/wally-pipelined/src/muldiv/div/shift_right.do +++ /dev/null @@ -1,55 +0,0 @@ -# Copyright 1991-2016 Mentor Graphics Corporation -# -# Modification by Oklahoma State University -# Use with Testbench -# James Stine, 2008 -# Go Cowboys!!!!!! -# -# All Rights Reserved. -# -# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION -# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION -# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. - -# Use this run.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do run.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do run.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -vlog mux_div.sv shift.sv shift_right_tb.sv - -# start and run simulation -vsim -voptargs=+acc work.stimulus - -view wave - --- display input and output signals as hexidecimal values -# Diplays All Signals recursively -add wave -hex -r /stimulus/* - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {75 ns} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 - --- Run the Simulation -run 800ns -quit diff --git a/wally-pipelined/src/muldiv/div/shift_right.out b/wally-pipelined/src/muldiv/div/shift_right.out deleted file mode 100644 index 42202ab57..000000000 --- a/wally-pipelined/src/muldiv/div/shift_right.out +++ /dev/null @@ -1,24 +0,0 @@ -12153524 01 || 090a9a92 090a9a92 | 1 -8484d609 03 || 10909ac1 10909ac1 | 1 -06b97b0d 0d || 000035cb 000035cb | 1 -b2c28465 12 || 00002cb0 00002cb0 | 1 -00f3e301 0d || 0000079f 0000079f | 1 -3b23f176 1d || 00000001 00000001 | 1 -76d457ed 0c || 00076d45 00076d45 | 1 -7cfde9f9 06 || 01f3f7a7 01f3f7a7 | 1 -e2f784c5 0a || 0038bde1 0038bde1 | 1 -72aff7e5 17 || 000000e5 000000e5 | 1 -8932d612 0f || 00011265 00011265 | 1 -793069f2 0e || 0001e4c1 0001e4c1 | 1 -f4007ae8 05 || 07a003d7 07a003d7 | 1 -2e58495c 1d || 00000001 00000001 | 1 -96ab582d 05 || 04b55ac1 04b55ac1 | 1 -b1ef6263 0a || 002c7bd8 002c7bd8 | 1 -c03b2280 00 || c03b2280 c03b2280 | 1 -557845aa 1d || 00000002 00000002 | 1 -cb203e96 13 || 00001964 00001964 | 1 -86bc380d 13 || 000010d7 000010d7 | 1 -359fdd6b 15 || 000001ac 000001ac | 1 -81174a02 0e || 0002045d 0002045d | 1 -0effe91d 0f || 00001dff 00001dff | 1 -11844923 0a || 00046112 00046112 | 1 diff --git a/wally-pipelined/src/muldiv/div/shift_right_tb.sv b/wally-pipelined/src/muldiv/div/shift_right_tb.sv deleted file mode 100755 index b35277484..000000000 --- a/wally-pipelined/src/muldiv/div/shift_right_tb.sv +++ /dev/null @@ -1,64 +0,0 @@ -// -// File name : tb -// Title : test -// project : HW3 -// Library : test -// Purpose : definition of modules for testbench -// notes : -// -// Copyright Oklahoma State University -// - -// Top level stimulus module - -`timescale 1ns/1ps - -`define XLEN 32 -module stimulus; - - logic [`XLEN-1:0] A; - logic [$clog2(`XLEN)-1:0] Shift; - logic [`XLEN-1:0] Z; - logic [`XLEN-1:0] Z_corr; - - logic clk; - - integer handle3; - integer desc3; - integer i; - - // instatiate part to test - shift_right dut1 (A, Shift, Z); - assign Z_corr = (A >> Shift); - - initial - begin - clk = 1'b1; - forever #5 clk = ~clk; - end - - initial - begin - handle3 = $fopen("shift_right.out"); - desc3 = handle3; - #250 $finish; - end - - initial - begin - for (i=0; i < 128; i=i+1) - begin - // Put vectors before beginning of clk - @(posedge clk) - begin - A = $random; - Shift = $random; - end - @(negedge clk) - begin - $fdisplay(desc3, "%h %h || %h %h | %b", A, Shift, Z, Z_corr, (Z == Z_corr)); - end - end // @(negedge clk) - end // for (j=0; j < 32; j=j+1) - -endmodule // stimulus diff --git a/wally-pipelined/src/muldiv/div/shifter.sv b/wally-pipelined/src/muldiv/div/shifter.sv deleted file mode 100644 index acf0b49e9..000000000 --- a/wally-pipelined/src/muldiv/div/shifter.sv +++ /dev/null @@ -1,18 +0,0 @@ -module shifter_right(input logic signed [63:0] a, - input logic [ 5:0] shamt, - output logic signed [63:0] y); - - - assign y = a >> shamt; - -endmodule // shifter_right - -module shifter_left(input logic signed [63:0] a, - input logic [ 5:0] shamt, - output logic signed [63:0] y); - - - assign y = a << shamt; - -endmodule // shifter_right - diff --git a/wally-pipelined/src/muldiv/div/shifters_div.sv b/wally-pipelined/src/muldiv/div/shifters_div.sv deleted file mode 100644 index b69100dc4..000000000 --- a/wally-pipelined/src/muldiv/div/shifters_div.sv +++ /dev/null @@ -1,106 +0,0 @@ -module shifter_l64 (Z, A, Shift); - - input logic [63:0] A; - input logic [5:0] Shift; - - logic [63:0] stage1; - logic [63:0] stage2; - logic [63:0] stage3; - logic [63:0] stage4; - logic [63:0] stage5; - logic [31:0] thirtytwozeros = 32'h0; - logic [15:0] sixteenzeros = 16'h0; - logic [ 7:0] eightzeros = 8'h0; - logic [ 3:0] fourzeros = 4'h0; - logic [ 1:0] twozeros = 2'b00; - logic onezero = 1'b0; - - output logic [63:0] Z; - - mux2 #(64) mx01(A, {A[31:0], thirtytwozeros}, Shift[5], stage1); - mux2 #(64) mx02(stage1, {stage1[47:0], sixteenzeros}, Shift[4], stage2); - mux2 #(64) mx03(stage2, {stage2[55:0], eightzeros}, Shift[3], stage3); - mux2 #(64) mx04(stage3, {stage3[59:0], fourzeros}, Shift[2], stage4); - mux2 #(64) mx05(stage4, {stage4[61:0], twozeros}, Shift[1], stage5); - mux2 #(64) mx06(stage5, {stage5[62:0], onezero}, Shift[0], Z); - -endmodule // shifter_l64 - -module shifter_r64 (Z, A, Shift); - - input logic [63:0] A; - input logic [5:0] Shift; - - logic [63:0] stage1; - logic [63:0] stage2; - logic [63:0] stage3; - logic [63:0] stage4; - logic [63:0] stage5; - logic [31:0] thirtytwozeros = 32'h0; - logic [15:0] sixteenzeros = 16'h0; - logic [ 7:0] eightzeros = 8'h0; - logic [ 3:0] fourzeros = 4'h0; - logic [ 1:0] twozeros = 2'b00; - logic onezero = 1'b0; - - output logic [63:0] Z; - - mux2 #(64) mx01(A, {thirtytwozeros, A[63:32]}, Shift[5], stage1); - mux2 #(64) mx02(stage1, {sixteenzeros, stage1[63:16]}, Shift[4], stage2); - mux2 #(64) mx03(stage2, {eightzeros, stage2[63:8]}, Shift[3], stage3); - mux2 #(64) mx04(stage3, {fourzeros, stage3[63:4]}, Shift[2], stage4); - mux2 #(64) mx05(stage4, {twozeros, stage4[63:2]}, Shift[1], stage5); - mux2 #(64) mx06(stage5, {onezero, stage5[63:1]}, Shift[0], Z); - -endmodule // shifter_r64 - -module shifter_l32 (Z, A, Shift); - - input logic [31:0] A; - input logic [4:0] Shift; - - logic [31:0] stage1; - logic [31:0] stage2; - logic [31:0] stage3; - logic [31:0] stage4; - logic [15:0] sixteenzeros = 16'h0; - logic [ 7:0] eightzeros = 8'h0; - logic [ 3:0] fourzeros = 4'h0; - logic [ 1:0] twozeros = 2'b00; - logic onezero = 1'b0; - - output logic [31:0] Z; - - mux2 #(32) mx01(A, {A[15:0], sixteenzeros}, Shift[4], stage1); - mux2 #(32) mx02(stage1, {stage1[23:0], eightzeros}, Shift[3], stage2); - mux2 #(32) mx03(stage2, {stage2[27:0], fourzeros}, Shift[2], stage3); - mux2 #(32) mx04(stage3, {stage3[29:0], twozeros}, Shift[1], stage4); - mux2 #(32) mx05(stage4, {stage4[30:0], onezero}, Shift[0], Z); - -endmodule // shifter_l32 - -module shifter_r32 (Z, A, Shift); - - input logic [31:0] A; - input logic [4:0] Shift; - - logic [31:0] stage1; - logic [31:0] stage2; - logic [31:0] stage3; - logic [31:0] stage4; - logic [15:0] sixteenzeros = 16'h0; - logic [ 7:0] eightzeros = 8'h0; - logic [ 3:0] fourzeros = 4'h0; - logic [ 1:0] twozeros = 2'b00; - logic onezero = 1'b0; - - output logic [31:0] Z; - - mux2 #(32) mx01(A, {sixteenzeros, A[31:16]}, Shift[4], stage1); - mux2 #(32) mx02(stage1, {eightzeros, stage1[31:8]}, Shift[3], stage2); - mux2 #(32) mx03(stage2, {fourzeros, stage2[31:4]}, Shift[2], stage3); - mux2 #(32) mx04(stage3, {twozeros, stage3[31:2]}, Shift[1], stage4); - mux2 #(32) mx05(stage4, {onezero, stage4[31:1]}, Shift[0], Z); - -endmodule // shifter_r32 - diff --git a/wally-pipelined/src/muldiv/div/test_int32div.sv b/wally-pipelined/src/muldiv/div/test_int32div.sv deleted file mode 100755 index 79940b7fe..000000000 --- a/wally-pipelined/src/muldiv/div/test_int32div.sv +++ /dev/null @@ -1,50 +0,0 @@ -module tb; - - logic [31:0] N, D; - logic clk; - logic reset; - logic start; - - logic [31:0] Q; - logic [31:0] rem; - logic div0; - logic done; - logic divdone; - - integer handle3; - integer desc3; - integer i; - - logic [7:0] count [0:15]; - - int32div dut (Q, done, divdone, rem, div0, N, D, clk, reset, start); - - initial - begin - clk = 1'b0; - forever #5 clk = ~clk; - end - - initial - begin - #800 $finish; - end - - - initial - begin - #0 N = 32'h0; - #0 D = 32'h0; - #0 start = 1'b0; - #0 reset = 1'b1; - #22 reset = 1'b0; - #25 N = 32'h9830_07C0; - #0 D = 32'h0000_000C; - //#25 N = 32'h06b9_7b0d; - //#0 D = 32'h46df_998d; - #0 start = 1'b1; - #50 start = 1'b0; - - end - -endmodule // tb diff --git a/wally-pipelined/src/muldiv/div/test_int64div.sv b/wally-pipelined/src/muldiv/div/test_int64div.sv deleted file mode 100644 index 8e7f4cc2b..000000000 --- a/wally-pipelined/src/muldiv/div/test_int64div.sv +++ /dev/null @@ -1,71 +0,0 @@ -module tb; - - logic [63:0] N, D; - logic clk; - logic reset; - logic start; - - logic [63:0] Q; - logic [63:0] rem; - logic div0; - logic done; - logic divdone; - - integer handle3; - integer desc3; - integer i; - - logic [7:0] count [0:15]; - - bit [63:0] Ncomp; - bit [63:0] Dcomp; - bit [63:0] Qcomp; - bit [63:0] Rcomp; - - int64div dut (Q, done, divdone, rem, div0, N, D, clk, reset, start); - assign Ncomp = N; - assign Dcomp = D; - assign Qcomp = Ncomp/Dcomp; - assign Rcomp = Ncomp%Dcomp; - - initial - begin - clk = 1'b0; - forever #5 clk = ~clk; - end - - initial - begin - #800 $finish; - end - - initial - begin - handle3 = $fopen("div64.out"); - desc3 = handle3; - end - - always - begin - desc3 = handle3; - #5 $fdisplay(desc3, "%h %h | %h %h | %h %h %b %b", - N, D, Q, rem, Qcomp, Rcomp, - (Q==Qcomp), (rem==Rcomp)); - end - - initial - begin - #0 N = 64'h0; - #0 D = 64'h0; - #0 start = 1'b0; - #0 reset = 1'b1; - #22 reset = 1'b0; - #25 N = 64'hffff_ffff_ffff_ffff; - #0 D = 64'h0000_0000_0000_0000; - #0 start = 1'b1; - #50 start = 1'b0; - - - end - -endmodule // tb diff --git a/wally-pipelined/src/muldiv/div/test_iter32.sv b/wally-pipelined/src/muldiv/div/test_iter32.sv deleted file mode 100755 index 94a42c211..000000000 --- a/wally-pipelined/src/muldiv/div/test_iter32.sv +++ /dev/null @@ -1,74 +0,0 @@ -module tb; - - logic [31:0] N, D; - logic clk; - logic reset; - logic start; - - logic [31:0] Q; - logic [31:0] rem0; - logic div0; - logic done; - logic divdone; - - integer handle3; - integer desc3; - integer i; - - bit [31:0] Ncomp; - bit [31:0] Dcomp; - bit [31:0] Qcomp; - bit [31:0] Rcomp; - - logic [7:0] count [0:15]; - - int32div dut (Q, done, divdone, rem0, div0, N, D, clk, reset, start); - - initial - begin - clk = 1'b0; - forever #5 clk = ~clk; - end - - initial - begin - handle3 = $fopen("iter32.out"); - #8000000 $finish; - end - - always @(posedge clk, posedge reset) - begin - desc3 = handle3; - #0 start = 1'b0; - #0 reset = 1'b1; - #30 reset = 1'b0; - for (i=0; i<2; i=i+1) - begin - N = $random; - D = $random; - start <= 1'b1; - // Wait 2 cycles (to be sure) - repeat (2) - @(posedge clk); - start <= 1'b0; - repeat (25) - @(posedge clk); - Ncomp = N; - Dcomp = D; - Qcomp = Ncomp/Dcomp; - Rcomp = Ncomp%Dcomp; - $fdisplay(desc3, "%h %h %h %h || %h %h || %b %b", - N, D, Q, rem0, Qcomp, Rcomp, - (Q==Qcomp), (rem0==Rcomp)); - end // for (i=0; i<2, i=i+1) - - - end - -endmodule // tb - - - - - - diff --git a/wally-pipelined/src/muldiv/div/test_iter64.sv b/wally-pipelined/src/muldiv/div/test_iter64.sv deleted file mode 100755 index 0674d8665..000000000 --- a/wally-pipelined/src/muldiv/div/test_iter64.sv +++ /dev/null @@ -1,72 +0,0 @@ -module tb; - - logic [63:0] N, D; - logic clk; - logic reset; - logic start; - - logic [63:0] Q; - logic [63:0] rem0; - logic div0; - logic done; - logic divdone; - - integer handle3; - integer desc3; - integer i; - - bit [63:0] Ncomp; - bit [63:0] Dcomp; - bit [63:0] Qcomp; - bit [63:0] Rcomp; - - logic [7:0] count [0:15]; - - int64div dut (Q, done, divdone, rem0, div0, N, D, clk, reset, start); - - initial - begin - clk = 1'b0; - forever #5 clk = ~clk; - end - - initial - begin - handle3 = $fopen("iter64.out"); - #8000000 $finish; - end - - always @(posedge clk, posedge reset) - begin - desc3 = handle3; - #0 start = 1'b0; - #0 reset = 1'b1; - #30 reset = 1'b0; - for (i=0; i<2; i=i+1) - begin - N = $random; - D = $random; - start <= 1'b1; - // Wait 2 cycles (to be sure) - repeat (2) - @(posedge clk); - start <= 1'b0; - repeat (41) - @(posedge clk); - Ncomp = N; - Dcomp = D; - Qcomp = Ncomp/Dcomp; - Rcomp = Ncomp%Dcomp; - $fdisplay(desc3, "%h %h %h %h || %h %h || %b %b", - N, D, Q, rem0, Qcomp, Rcomp, - (Q==Qcomp), (rem0==Rcomp)); - end // for (i=0; i<2, i=i+1) - end - -endmodule // tb - - - - - - diff --git a/wally-pipelined/src/muldiv/div/udiv b/wally-pipelined/src/muldiv/div/udiv deleted file mode 100755 index 8b1ac689b125bcbebc7b536ebf471dadd896c360..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 16696 zcmeHOeQaA-6~DHVH2sLr7L+&zp`{F)K22`c}l<1gcYsbs}nnk!Lft= z+&LB6iqcJ3ZMF(&0x={u2?0{61md57fTa|=BEi)Dg9g*IGEwj*TGG-%_-M^J_nqUs z_u>>Z?LXd)?B6}V^KtJx@4n}I^WJ?X+|%v#cmx-p_>@5DSioe0q{#203P4b_i8}ah z6zfC{$W@Xv^+6LrYnC^>cC01d2Z(+RSgC*?HEF@fJw!ym1q*fv3nLu|`c)%OvJ+pV zeloJY+@6BYP!#!H#ylE8VYK>T7p9t}T1>Uu@i4V_jFA0MM8C`AcbWVcXQ(|!&L`#s zKW&sxCn})BqR4L{oPLMN&xu`R&xmbcIdt8KeUSDJkYAG`!w4sGJB-}kLGa^KYI@%P zn@@8uwYSiD&?x_mlwPqVnHXr@u_YO6P9{>hd~?37wYhbNnoXCxBNf*nf5b9%FyJg1vye4q_Tx#aJehGKPe% z59Xu#P$CsgCQigbL<>D@L^Fmy8cn3co}NfYr@l?yrtTDaq;Ibti)Z4)iL4RN^zH3T zrc?30=s*%Zhey*X^3+Y!iiX%NFJ+l??GgAlcYDaKNi0UI?Q{%${ql7aTy83+>H1_| z5MLWK^~|&U2A&WocrLL$F4rtPk0I0*Ej(Wf$j?}Kd0#^k%B+RAUN2XOUj#OM%+kUA zax>s&z|DZ00XG9~2HXs|8Th}-z+dav{ZpIxbFFr|`nOwz(4L((yrnDJ#LsIl$~=^I zehui`rHwBE)He#WA3@FScYj|hmCm9J+VfJ|C8QqYoK@a>BT~5fq*i!GoA|@bfxe!} z>Kd4WYLj&@zzkTMY`*~EN~?Oo<<40U$DyK4R%Z})%^ItqYbw^EYl}KjjD^A`!h zJ|gXRb|7rJrxj+j3paOb7iN8$=aP2yp0N@FR8xT3(zT)bM(8K|WB*UKqgv!P_iGdF z@2F7K3fGNg+UfQ`f>2xy$61WQ*QM&WK=vF3Uz`8CPk|Bx^@ATIQ_-d#`qkPMU2V_2 ztrfyWZR*8?@14KVem4NpjP_c12Fy!`Rvhw#_5e#OL&QP-DUo`$y)N-NZF<2*M*ro-A+^5o6gDK}`3ybYGui&q zW+6hKjud_q>W>uO5A}r#|L)f&o6i7!sAtn%95cmN??SgO-1QlaTi>Mf(NnnHQ@Ghx z_*1B~@@;M6qDR~HR_;9x&48N$Hv?`4+zhxGa5L~BWxxYZgZ3%y%En}ViRj|WL9X<2#k1D;Nmw=ue10_h zmr^MY*Z>RJmjRmqaV6OXcnom;ty1XV?Yu12cGkG*421_06l`{f%-0dWqut1f0fMR zgS<)#9+t}Et)+PI1Xs$OcUUG$`3@cbKS<`|pzt3W@cZD-fGyU=uTyy+ncq*{)7kl` z($qhYOBp$3m%3eTY2NxsPKsNf-qxbF?AT<|_ld%HSFy!7ks_jdAJEER>rLR!~^B`@vT}P{1;`cqW!A!z6QJf zM+DzD?EHhG(zx}(U4XB1yFJ{cf>y??`@|X%sL1nOY|aO-&nj`NG{=}Vygz#3q?~o+ z6JC#y{Ir8#Pdwjm%_u@V0u_&?KYTyvmi+uY;LG~hZu$OAfySl%{Cs{D_)7g>=(xTi z9DrBMzb<^h zuYmlVq~9t2U3ma_g&VWr=OjOWoNNI;AXd*CCw0KD@Xo(3T9LQJHt&jP>PyISylmQ`Oy9$O|S`uPyA0FQYHP^aSL@I$}=jJJj$5d>+nKStwr3-R9v z9_<4T`=5|~g!U`Q|AB(f&w$5%I_+NvUZI#)C;~740c$0(KA17GMh@Qe85DE-HFRTC zAH*FSS=g-+OY6hQ^guMJ$Bc9)t4DKrF_<15OU8|OOl@mvZK-U8dqom@G?R&r>+zJ4 z85cvD=xAJzDk{A>e2UicOMG(>3yM&o-jt0J6Q&^Ioad;?_G(Fi9W}WU~}T zZoAQS*j>X3!fiJd_tMyR@7TL0)a>}E5ghpyVL>y;eotCFYjgQdC8i_$PmdqID5Hmfv4oyWz6A;XF zhwKU!hW988S?9I#0c8B8gG&$Yp=RNE79-EsNiA);j`$FKaE{FWJRf6JKxZvHFJ`V4 zDpvo)G(Th9z=ni;Ut>Dr@aOp*qr!%SPXEV&{~OG)x&OQlVdVCC50tb2QSiq#2>bJV zk?}j!E*>N1nf-aakN^%3nf-ZQ$#@EM)`Bstg~*5G>q(wqtx6bhsvA zndhmD3OYk^_TOZMn1l-El>K==%Q#Jj+`jYpze4^UWLKmgYDUfz`eWVc{|a!J6OIo* zQf47^&g7iu|LYEah5X7$;TRm@#kU>)K{8-u`-S|!=kVuwIpcrx$KP@5@gE}x#*KVp zr~}S;uR8pBp3hiEehkk1{et|<%_w9^*hC_O)Bo3?!2Yv;lVVyjc9~-N+v)!%XsrIc zzF@3HrKRxrVd^?m@EYM|AX z=lNcM{GImLmbEOW_Q|}gV*iKBj9FoSEArT}ng%Ig1Kk)t21*q^+#kNLEC!DIZuLKm cKTJ@n9KpF=Q;T!%%Kk^%Op7%R2Zt#B12|}cO8@`> diff --git a/wally-pipelined/src/muldiv/div/udiv.c b/wally-pipelined/src/muldiv/div/udiv.c deleted file mode 100644 index c27565698..000000000 --- a/wally-pipelined/src/muldiv/div/udiv.c +++ /dev/null @@ -1,24 +0,0 @@ -#include -#include -#include - -int main() { - - uint64_t N; - uint64_t D; - uint64_t Q; - - D = 0xdf7f3844121bcc23; - N = 0x10fd3dedadea5195; - N = 0xffffffffffffffff; - D = 0x0000000000000000; - Q = N/D; - - printf("N = %" PRIx64 "\n", N); - printf("D = %" PRIx64 "\n", D); - printf("Q = %" PRIx64 "\n", Q); - printf("R = %" PRIx64 "\n", N%D); - - - -}

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