From 4d18836bfc7841e8e277322fa347562675f78a0f Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 23 Apr 2025 19:13:06 -0700 Subject: [PATCH 1/2] Use Verilator for benchmarks by default --- benchmarks/coremark/Makefile | 3 +-- benchmarks/embench/Makefile | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/benchmarks/coremark/Makefile b/benchmarks/coremark/Makefile index a999e70f3..7073cf730 100644 --- a/benchmarks/coremark/Makefile +++ b/benchmarks/coremark/Makefile @@ -28,8 +28,7 @@ PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \ all: $(work_dir)/coremark.bare.riscv.elf.memfile run: $(work_dir)/coremark.bare.riscv.elf.memfile -# time wsim rv$(XLEN)gc coremark --sim verilator 2>&1 | tee $(work_dir)/coremark.sim.log - time wsim ${CONFIG} coremark 2>&1 | tee $(work_dir)/coremark.sim.log + time wsim --sim verilator ${CONFIG} coremark 2>&1 | tee $(work_dir)/coremark.sim.log $(work_dir)/coremark.bare.riscv.elf.memfile: $(work_dir)/coremark.bare.riscv riscv64-unknown-elf-objdump -D $< > $<.elf.objdump diff --git a/benchmarks/embench/Makefile b/benchmarks/embench/Makefile index 09d2939b0..0a52f79ae 100644 --- a/benchmarks/embench/Makefile +++ b/benchmarks/embench/Makefile @@ -43,7 +43,7 @@ sim: sim_build_memfile sim_run speed # launches sim to simulate tests on wally sim_run: - wsim rv32gc embench --params "BPRED_LOGGER=1\'b1" + wsim --sim verilator rv32gc embench --params "BPRED_LOGGER=1\'b1" # builds the objdump based on the compiled c elf files objdump: From eeb470cd945f521f8b2bcc64ab7868879a6b4fb7 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Wed, 23 Apr 2025 19:23:23 -0700 Subject: [PATCH 2/2] Remove outdated Verilator README --- sim/verilator/README.md | 32 -------------------------------- 1 file changed, 32 deletions(-) delete mode 100644 sim/verilator/README.md diff --git a/sim/verilator/README.md b/sim/verilator/README.md deleted file mode 100644 index 5fd1b57b3..000000000 --- a/sim/verilator/README.md +++ /dev/null @@ -1,32 +0,0 @@ -# Simulation with Verilator - -Different executables will be built for different architecture configurations, e.g., rv64gc, rv32i. A executable can run all the test suites that it can run with `+TEST=`. - -Demand: - -- Avoid unnecessary compilation by sharing the same executable for a specific configuration - - executables are stored in `obj_dir_non_profiling` and `obj_dir_profiling` correspondingly -- Wsim should support `-s verilator` option and run simulation with Verilator. - -## Folder Structure - -This folder contains the following files that help the simulation of Wally with Verilator: - -- Makefile: simplify the usage with Verialtor -- executables - - `obj_dir_non_profiling`: non-profiling executables for different configurations - - `obj_dir_profiling`: profiling executables for different configurations -- logs in `logs` and `logs_profiling` correspondingly -- [NOT WORKING] `logs`: contains all the logs - -## Examples - -```shell -# non-profiling mode -make WALLYCONF=rv64gc TEST=arch64i run -# profiling mode -make WALLYCONF=rv64gc TEST=arch64i profile - -# remove all the temporary files, including executables and logs -make clean -``` \ No newline at end of file