From 79ec595d9748e5f0ff812aff865116e5093d2fb6 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Thu, 13 Feb 2025 02:06:09 -0800 Subject: [PATCH] Fix lockstep and fcov running at the same time --- sim/questa/wally.do | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/sim/questa/wally.do b/sim/questa/wally.do index 70c258c04..8d5174d55 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -119,11 +119,13 @@ if {[lcheck lst "--fcov"]} { if {[lcheck lst "--lockstep"]} { set IMPERAS_HOME $::env(IMPERAS_HOME) set lockstep 1 + set SVLib " -sv_lib ${IMPERAS_HOME}/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model " set lockstepvlog "+incdir+${IMPERAS_HOME}/ImpPublic/include/host \ +incdir+${IMPERAS_HOME}/ImpProprietary/include/host \ - ${IMPERAS_HOME}/ImpPublic/source/host/rvvi/*.sv \ + ${IMPERAS_HOME}/ImpPublic/source/host/rvvi/rvviApiPkg.sv \ ${IMPERAS_HOME}/ImpProprietary/source/host/idv/*.sv" - set SVLib " -sv_lib ${IMPERAS_HOME}/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model " + # only add standard rvviTrace interface if not using the custom one from cvw-arch-verif + if {!$FunctCoverage} {append lockstepvlog " ${IMPERAS_HOME}/ImpPublic/source/host/rvvi/rvviTrace.sv"} } # if --breker found set flag and remove from list @@ -181,7 +183,7 @@ if {$DEBUG > 0} { # because vsim will run vopt set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared" set SOURCES "${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv" -vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${DefineArgs} {*}${lockstepvlog} {*}${brekervlog} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286,2605,2250 +vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${DefineArgs} {*}${lockstepvlog} {*}${FCvlog} {*}${brekervlog} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286,2605,2250 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals