From 7c1606264a365e94a6de0911bb9ac5d747d4aaf1 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 19 Oct 2023 06:16:52 -0700 Subject: [PATCH] Adjusted synthesis scripts to report on DESIGN even when a wrapper is used --- .gitignore | 1 + synthDC/scripts/synth.tcl | 15 +++++++++++---- synthDC/wallySynth.py | 2 +- 3 files changed, 13 insertions(+), 5 deletions(-) diff --git a/.gitignore b/.gitignore index 41ccba5f9..04ae44109 100644 --- a/.gitignore +++ b/.gitignore @@ -82,6 +82,7 @@ synthDC/ppa/plots synthDC/wallyplots/ synthDC/runArchive synthDC/hdl +synthDC/wrappers sim/power.saif tests/fp/vectors/*.tv synthDC/Summary.csv diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 075bb5db9..00800a7ef 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -53,6 +53,7 @@ if { $wrapper == 1 } { } else { set my_toplevel $::env(DESIGN) } +set my_design $::env(DESIGN) # Set number of significant digits set report_default_significant_digits 6 @@ -238,6 +239,12 @@ set write_rep 1 ;# generates estimated area and timing report set write_cst 1 ;# generate report of constraints set write_hier 1 ;# generate hierarchy report +# Report on DESIGN, not wrapper. However, design has a suffix for the parameters. +if { $wrapper == 1 } { + set designname [format "%s%s" $my_design "__*"] + current_design $designname +} + # Report Constraint Violators set filename [format "%s%s" $outputDir "/reports/constraint_all_violators.rpt"] redirect $filename {report_constraint -all_violators} @@ -246,16 +253,16 @@ redirect $filename {report_constraint -all_violators} redirect $outputDir/reports/check_design.rpt { check_design } # Report Final Netlist (Hierarchical) -set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sv"] +set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_design ".sv"] write_file -f verilog -hierarchy -output $filename -set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sdc"] +set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_design ".sdc"] write_sdc $filename -set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".ddc"] +set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_design ".ddc"] write_file -format ddc -hierarchy -o $filename -set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sdf"] +set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_design ".sdf"] write_sdf $filename # QoR diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py index 139bcdd60..141b6e8c5 100755 --- a/synthDC/wallySynth.py +++ b/synthDC/wallySynth.py @@ -7,7 +7,7 @@ import argparse def runSynth(config, mod, tech, freq, maxopt, usesram): global pool - command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} USESRAM={} MAXCORES=1".format(config, mod, tech, freq, maxopt, usesram) + command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} USESRAM={} MAXCORES=1 WRAPPER=1".format(config, mod, tech, freq, maxopt, usesram) pool.map(mask, [command]) def mask(command):