From 7c50b2c571ba5cc2b9c8ac7a5ec3255d115d5ba7 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 12 Nov 2023 06:36:57 -0800 Subject: [PATCH] Renamed qsel to uslc and simplified radix2 uslc --- src/fpu/fdivsqrt/fdivsqrtstage2.sv | 4 +-- src/fpu/fdivsqrt/fdivsqrtstage4.sv | 23 +++++-------- .../{fdivsqrtqsel2.sv => fdivsqrtuslc2.sv} | 24 +++++++------ .../{fdivsqrtqsel4.sv => fdivsqrtuslc4.sv} | 34 +++++++++---------- ...divsqrtqsel4cmp.sv => fdivsqrtuslc4cmp.sv} | 10 +++--- 5 files changed, 46 insertions(+), 49 deletions(-) rename src/fpu/fdivsqrt/{fdivsqrtqsel2.sv => fdivsqrtuslc2.sv} (69%) rename src/fpu/fdivsqrt/{fdivsqrtqsel4.sv => fdivsqrtuslc4.sv} (72%) rename src/fpu/fdivsqrt/{fdivsqrtqsel4cmp.sv => fdivsqrtuslc4cmp.sv} (90%) diff --git a/src/fpu/fdivsqrt/fdivsqrtstage2.sv b/src/fpu/fdivsqrt/fdivsqrtstage2.sv index ad0c828e9..40a2a5a01 100644 --- a/src/fpu/fdivsqrt/fdivsqrtstage2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtstage2.sv @@ -49,7 +49,7 @@ module fdivsqrtstage2 import cvw::*; #(parameter cvw_t P) ( // Quotient Selection logic // Given partial remainder, select digit of +1, 0, or -1 (up, uz, un) - fdivsqrtqsel2 qsel2(WS[P.DIVb+3:P.DIVb], WC[P.DIVb+3:P.DIVb], up, uz, un); + fdivsqrtuslc2 uslc2(.WS(WS[P.DIVb+3:P.DIVb]), .WC(WC[P.DIVb+3:P.DIVb]), .up, .uz, .un); // Sqrt F generation. Extend C, U, UM to Q4.k fdivsqrtfgen2 #(P) fgen2(.up, .uz, .C({2'b11, CNext}), .U({3'b000, U}), .UM({3'b000, UM}), .F); @@ -60,7 +60,7 @@ module fdivsqrtstage2 import cvw::*; #(parameter cvw_t P) ( else if (uz) Dsel = '0; else Dsel = D; // un - // Residual Generation + // Residual Update // WSA, WCA = WS + WC - qD mux2 #(P.DIVb+4) addinmux(Dsel, F, SqrtE, AddIn); csa #(P.DIVb+4) csa(WS, WC, AddIn, up&~SqrtE, WSA, WCA); diff --git a/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/src/fpu/fdivsqrt/fdivsqrtstage4.sv index fea2851b6..a24c1155f 100644 --- a/src/fpu/fdivsqrt/fdivsqrtstage4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtstage4.sv @@ -31,36 +31,29 @@ module fdivsqrtstage4 import cvw::*; #(parameter cvw_t P) ( input logic [P.DIVb:0] U,UM, // U1.DIVb input logic [P.DIVb+3:0] WS, WC, // Q4.DIVb input logic [P.DIVb+1:0] C, // Q2.DIVb - input logic SqrtE, j1, + input logic SqrtE, j1, output logic [P.DIVb+1:0] CNext, // Q2.DIVb - output logic un, + output logic un, output logic [P.DIVb:0] UNext, UMNext, // U1.DIVb output logic [P.DIVb+3:0] WSNext, WCNext // Q4.DIVb ); logic [P.DIVb+3:0] Dsel; // Q4.DIVb - logic [3:0] udigit; + logic [3:0] udigit; // {+2, +1, -1, -2} or 0000 for 0 logic [P.DIVb+3:0] F; // Q4.DIVb logic [P.DIVb+3:0] AddIn; // Q4.DIVb - logic [4:0] Smsbs; - logic [2:0] Dmsbs; - logic [7:0] WCmsbs, WSmsbs; - logic CarryIn; + logic [4:0] Smsbs; // U1.4 + logic [2:0] Dmsbs; // U0.3 drop leading 1 from D + logic [7:0] WCmsbs, WSmsbs; // U4.4 + logic CarryIn; logic [P.DIVb+3:0] WSA, WCA; // Q4.DIVb // Digit Selection logic - // u encoding: - // 1000 = +2 - // 0100 = +1 - // 0000 = 0 - // 0010 = -1 - // 0001 = -2 assign Smsbs = U[P.DIVb:P.DIVb-4]; // U1.4 most significant bits of square root assign Dmsbs = D[P.DIVb-1:P.DIVb-3]; // U0.3 most significant fractional bits of divisor after leading 1 assign WCmsbs = WC[P.DIVb+3:P.DIVb-4]; // Q4.4 most significant bits of residual assign WSmsbs = WS[P.DIVb+3:P.DIVb-4]; // Q4.4 most significant bits of residual - - fdivsqrtqsel4cmp qsel4(.Dmsbs, .Smsbs, .WSmsbs, .WCmsbs, .SqrtE, .j1, .udigit); + fdivsqrtuslc4cmp uslc4(.Dmsbs, .Smsbs, .WSmsbs, .WCmsbs, .SqrtE, .j1, .udigit); assign un = 1'b0; // unused for radix 4 // F generation logic diff --git a/src/fpu/fdivsqrt/fdivsqrtqsel2.sv b/src/fpu/fdivsqrt/fdivsqrtuslc2.sv similarity index 69% rename from src/fpu/fdivsqrt/fdivsqrtqsel2.sv rename to src/fpu/fdivsqrt/fdivsqrtuslc2.sv index de64bafc9..e4fcfeadf 100644 --- a/src/fpu/fdivsqrt/fdivsqrtqsel2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuslc2.sv @@ -1,10 +1,10 @@ /////////////////////////////////////////// -// fdivsqrtqsel2.sv +// fdivsqrtuslc2.sv // // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu // Modified:13 January 2022 // -// Purpose: Radix 2 Quotient Digit Selection +// Purpose: Radix 2 Unified Quotient/Square Root Digit Selection // // Documentation: RISC-V System on Chip Design Chapter 13 // @@ -26,22 +26,26 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module fdivsqrtqsel2 ( - input logic [3:0] WS, WC, - output logic up, uz, un +module fdivsqrtuslc2 ( + input logic [3:0] WS, WC, // Q4.0 most significant bits of redundant residual + output logic up, uz, un // {+1, 0, -1} ); - logic magnitude, sign; + logic sign; + + // Carry chain logic determines if W = WS + WC = -1, < -1, > -1 to choose 0, -1, 1 respectively - assign magnitude = ~((WS[2]^WC[2]) & (WS[1]^WC[1]) & + //if p2 * p1 * p0, W = -1 and choose digit of 0 + assign uz = ((WS[2]^WC[2]) & (WS[1]^WC[1]) & (WS[0]^WC[0])); + + // Otherwise determine sign using carry chain: sign = p3 ^ g_2:0 assign sign = (WS[3]^WC[3])^ (WS[2] & WC[2] | ((WS[2]^WC[2]) & (WS[1]&WC[1] | ((WS[1]^WC[1]) & (WS[0]&WC[0]))))); // Produce digit = +1, 0, or -1 - assign up = magnitude & ~sign; - assign uz = ~magnitude; - assign un = magnitude & sign; + assign up = ~uz & ~sign; + assign un = ~uz & sign; endmodule diff --git a/src/fpu/fdivsqrt/fdivsqrtqsel4.sv b/src/fpu/fdivsqrt/fdivsqrtuslc4.sv similarity index 72% rename from src/fpu/fdivsqrt/fdivsqrtqsel4.sv rename to src/fpu/fdivsqrt/fdivsqrtuslc4.sv index de520bef2..268ca9ea2 100644 --- a/src/fpu/fdivsqrt/fdivsqrtqsel4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuslc4.sv @@ -1,10 +1,10 @@ /////////////////////////////////////////// -// fdivsqrtqsel4.sv +// fdivsqrtuslc4.sv // // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu // Modified:13 January 2022 // -// Purpose: Radix 4 Quotient Digit Selection +// Purpose: Table-based Radix 4 Unified Quotient/Square Root Digit Selection // // Documentation: RISC-V System on Chip Design Chapter 13 // @@ -26,25 +26,25 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module fdivsqrtqsel4 ( - input logic [2:0] Dmsbs, - input logic [4:0] Smsbs, - input logic [7:0] WSmsbs, WCmsbs, +module fdivsqrtuslc4 ( + input logic [2:0] Dmsbs, // U0.3 fractional bits after implicit leading 1 + input logic [4:0] Smsbs, // U1.4 leading bits of square root approximation + input logic [7:0] WSmsbs, WCmsbs, // Q4.4 redundant residual most significant bits input logic Sqrt, j1, - output logic [3:0] udigit + output logic [3:0] udigit // {2, 1, -1, -2} digit is 0 if none are hot ); - logic [6:0] Wmsbs; - logic [7:0] PreWmsbs; - logic [2:0] A; + logic [7:0] PreWmsbs; // Q4.4 nonredundant residual msbs + logic [6:0] Wmsbs; // Q4.3 truncated nonredundant residual + logic [2:0] A; // U0.3 upper bits of D or Smsbs, discarding integer bit - assign PreWmsbs = WCmsbs + WSmsbs; - assign Wmsbs = PreWmsbs[7:1]; + assign PreWmsbs = WCmsbs + WSmsbs; // add redundant residual to find msbs + assign Wmsbs = PreWmsbs[7:1]; // truncate least significant bit to Q4.3 to index table // D = 0001.xxx... // Dmsbs = | | // W = xxxx.xxx... // Wmsbs = | | - logic [3:0] USel4[1023:0]; + logic [3:0] USel4[1023:0]; // 1024-bit table indexed with 3 bits of A and 7 bits of Wmsbs // Prepopulate selection table; this is constant at compile time always_comb begin @@ -101,10 +101,10 @@ module fdivsqrtqsel4 ( // Select A always_comb if (Sqrt) begin - if (j1) A = 3'b101; - else if (Smsbs == 5'b10000) A = 3'b111; - else A = Smsbs[2:0]; - end else A = Dmsbs; + if (j1) A = 3'b101; // on first sqrt iteration A = .101 + else if (Smsbs == 5'b10000) A = 3'b111; // if S = 1.0, use A = .111 + else A = Smsbs[2:0]; // otherwise use A = S (in U0.3 format) + end else A = Dmsbs; // division Unless A = D (IN U0.3 format, dropping leading 1) // Select quotient digit from lookup table based on A and W assign udigit = USel4[{A,Wmsbs}]; diff --git a/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv b/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv similarity index 90% rename from src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv rename to src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv index fe436413e..ccb5e618a 100644 --- a/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv @@ -1,10 +1,10 @@ /////////////////////////////////////////// -// fdivsqrtqsel4cmp.sv +// fdivsqrtuslc4cmp.sv // // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu // Modified:13 January 2022 // -// Purpose: Comparator-based Radix 4 Quotient Digit Selection +// Purpose: Comparator-based Radix 4 Unified Quotient/Square Root Digit Selection // // Documentation: RISC-V System on Chip Design Chapter 13 // @@ -26,12 +26,12 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module fdivsqrtqsel4cmp ( +module fdivsqrtuslc4cmp ( input logic [2:0] Dmsbs, // U0.3 fractional bits after implicit leading 1 input logic [4:0] Smsbs, // U1.4 leading bits of square root approximation - input logic [7:0] WSmsbs, WCmsbs, // Q4.4 + input logic [7:0] WSmsbs, WCmsbs, // Q4.4 residual most significant bits input logic SqrtE, j1, - output logic [3:0] udigit + output logic [3:0] udigit // {2, 1, -1, -2} digit is 0 if none are hot ); logic [6:0] Wmsbs; logic [7:0] PreWmsbs;