From 135f3b6f8f820d37552f28bd7ec3a736457a2aa3 Mon Sep 17 00:00:00 2001
From: Divya2030 <imlucky.divya@gmail.com>
Date: Wed, 3 Apr 2024 10:39:02 -0700
Subject: [PATCH] vcs testbench

---
 sim/run_vcs.sh         | 24 ++++++++++++++++++++++++
 testbench/testbench.sv | 12 ++++++++----
 2 files changed, 32 insertions(+), 4 deletions(-)
 create mode 100755 sim/run_vcs.sh

diff --git a/sim/run_vcs.sh b/sim/run_vcs.sh
new file mode 100755
index 000000000..8acbd1b99
--- /dev/null
+++ b/sim/run_vcs.sh
@@ -0,0 +1,24 @@
+#!/bin/bash
+
+
+# Set CONFIG_VARIANT from the first script argument
+#CONFIG_VARIANT=${1:-rv64i}
+CONFIG_VARIANT=${1}
+# Set TESTSUITE from the second script argument
+TESTSUITE=$2
+INCLUDE_DIRS=$(find ../src -type d | xargs -I {} echo -n "{} ")
+SOURCE_PATH="+incdir+../config/${CONFIG_VARIANT} +incdir+../config/deriv/${CONFIG_VARIANT} +incdir+../config/shared +define+ +define+P.XLEN=64  +define+FPGA=0 +incdir+../testbench ../src/cvw.sv +incdir+../src" 
+
+SIMFILES="$INCLUDE_DIRS $(find ../src -name "*.sv" ! -path "../src/generic/clockgater.sv" ! -path "../src/generic/mem/rom1p1r_128x64.sv" ! -path "../src/generic/mem/ram2p1r1wbe_128x64.sv" ! -path "../src/generic/mem/rom1p1r_128x32.sv" ! -path "../src/generic/mem/ram2p1r1wbe_512x64.sv")  ../testbench/testbench.sv $(find ../testbench/common -name "*.sv" ! -path "../testbench/common/wallyTracer.sv")" 
+OUTPUT="sim_out"
+
+clean() {
+    rm -rf obj_dir work transcript vsim.wlf $OUTPUT *.vcd csrc ucli.key vc_hdrs.h program.out
+    rm -rf simv* *.daidir dve *.vpd *.dump DVEfiles/ verdi* novas* *fsdb* *.vg *.rep *.db *.chk *.log *.out profileReport* simprofile_dir*
+}
+
+# Clean and run simulation with VCS
+clean
+vcs +lint=all,noGCWM -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -v2k_generate  ${SOURCE_PATH} +define+TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV
+./$OUTPUT | tee program.out
+
diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index ee725c245..3ae597642 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -299,9 +299,11 @@ module testbench;
   // Find the test vector files and populate the PC to function label converter
   ////////////////////////////////////////////////////////////////////////////////
   logic [P.XLEN-1:0] testadr;
-  assign begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
-  assign end_signature_addr = ProgramAddrLabelArray["sig_end_canary"];
-  assign signature_size = end_signature_addr - begin_signature_addr;
+  always_comb begin
+  	begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
+ 	end_signature_addr = ProgramAddrLabelArray["sig_end_canary"];
+  	signature_size = end_signature_addr - begin_signature_addr;
+  end
   always @(posedge clk) begin
     if(SelectTest) begin
       if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
@@ -556,7 +558,8 @@ module testbench;
   logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls
   if (P.ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM;
   else                  assign ecf = 0;
-  assign TestComplete = ecf & 
+  always_comb begin
+  	TestComplete = ecf & 
 			    (dut.core.ieu.dp.regf.rf[3] == 1 | 
 			     (dut.core.ieu.dp.regf.we3 & 
 			      dut.core.ieu.dp.regf.a3 == 3 & 
@@ -564,6 +567,7 @@ module testbench;
            ((InstrM == 32'h6f | InstrM == 32'hfc32a423 | InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) |
            ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" );
   //assign DCacheFlushStart =  TestComplete;
+  end
   
   DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), .reset(reset), .start(DCacheFlushStart), .done(DCacheFlushDone));