From a3aeff2703e33e1328fb87b666d1f182b2475fd3 Mon Sep 17 00:00:00 2001
From: James Stine <james.stine@okstate.edu>
Date: Wed, 15 Feb 2023 18:12:12 -0600
Subject: [PATCH] Update if-then-else for ram items

---
 src/generic/mem/ram1p1rwbe.sv  | 14 +++++++-------
 src/generic/mem/ram2p1r1wbe.sv |  2 +-
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv
index e33e708a3..f1e784c13 100644
--- a/src/generic/mem/ram1p1rwbe.sv
+++ b/src/generic/mem/ram1p1rwbe.sv
@@ -55,10 +55,10 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) (
      logic [WIDTH-1:0] BitWriteMask;
      for (index=0; index < WIDTH; index++) 
        assign BitWriteMask[index] = bwe[index/8];
-    TS1N28HPCPSVTB64X128M4SW sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
+    ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
 			      .A(addr), .D(din), 
 			      .BWEB(~BitWriteMask), .Q(dout));
-     
+    
   end else if (`USE_SRAM == 1 && WIDTH == 44  && DEPTH == 64) begin
      genvar index;
      // 64 x 44-bit SRAM
@@ -69,15 +69,15 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) (
 			      .A(addr), .D(din), 
 			      .BWEB(~BitWriteMask), .Q(dout));
 
-  end if (`USE_SRAM == 1 && WIDTH == 128 && DEPTH == 32) begin
+  end else if (`USE_SRAM == 1 && WIDTH == 128 && DEPTH == 32) begin
      genvar index;
      // 64 x 128-bit SRAM
      logic [WIDTH-1:0] BitWriteMask;
      for (index=0; index < WIDTH; index++) 
        assign BitWriteMask[index] = bwe[index/8];
-    TS1N28HPCPSVTB64X128M4SW sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
-			      .A(addr), .D(din), 
-			      .BWEB(~BitWriteMask), .Q(dout));
+     ram1p1rwbe_128x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
+				.A(addr), .D(din), 
+				.BWEB(~BitWriteMask), .Q(dout));
      
   end else if (`USE_SRAM == 1 && WIDTH == 22  && DEPTH == 32) begin
      genvar index;
@@ -85,7 +85,7 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) (
      logic [WIDTH-1:0] BitWriteMask;
      for (index=0; index < WIDTH; index++) 
        assign BitWriteMask[index] = bwe[index/8];
-     ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we),
+     ram1p1rwbe_64x22 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we),
 			      .A(addr), .D(din), 
 			      .BWEB(~BitWriteMask), .Q(dout));     
     
diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv
index 08c232bba..da099cdc7 100644
--- a/src/generic/mem/ram2p1r1wbe.sv
+++ b/src/generic/mem/ram2p1r1wbe.sv
@@ -64,7 +64,7 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) (
 				  .QA(rd1),
 				  .QB());
 
-   end if (`USE_SRAM == 1 && WIDTH == 36 && DEPTH == 1024) begin
+   end else if (`USE_SRAM == 1 && WIDTH == 36 && DEPTH == 1024) begin
    
       ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk), 
 				  .CEBA(~ce1), .CEBB(~ce2),