From 9260d3c424092d3cd660fb5f3055f600b6ee0f6e Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 18 Jan 2024 22:46:07 -0800 Subject: [PATCH] Add Zfh support to imperas.ic, use Zicond in riscof now that it is fixed in riscv-arch-test --- config/rv32gc/config.vh | 4 ++-- sim/imperas.ic | 1 + tests/riscof/spike/spike_rv32gc_isa.yaml | 3 +-- tests/riscof/spike/spike_rv64gc_isa.yaml | 3 +-- 4 files changed, 5 insertions(+), 6 deletions(-) diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index a59bb1ab3..4baef0075 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -41,8 +41,8 @@ localparam ZIFENCEI_SUPPORTED = 1; localparam COUNTERS = 12'd32; localparam ZICNTR_SUPPORTED = 1; localparam ZIHPM_SUPPORTED = 1; -localparam ZFH_SUPPORTED = 0; -localparam ZFA_SUPPORTED = 0; +localparam ZFH_SUPPORTED = 1; +localparam ZFA_SUPPORTED = 1; localparam SSTC_SUPPORTED = 1; localparam ZICBOM_SUPPORTED = 1; localparam ZICBOZ_SUPPORTED = 1; diff --git a/sim/imperas.ic b/sim/imperas.ic index f3c620b96..5de5935c6 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -20,6 +20,7 @@ # More extensions --override cpu/Zcb=T --override cpu/Zicond=T +--override cpu/Zfh=T # Cache block operations --override cpu/Zicbom=T diff --git a/tests/riscof/spike/spike_rv32gc_isa.yaml b/tests/riscof/spike/spike_rv32gc_isa.yaml index 7d97edb6a..c2c95fbf4 100644 --- a/tests/riscof/spike/spike_rv32gc_isa.yaml +++ b/tests/riscof/spike/spike_rv32gc_isa.yaml @@ -1,7 +1,6 @@ hart_ids: [0] hart0: - ISA: RV32IMAFDCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs -# ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbs + ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbs # ISA: RV32IMAFDCZicsr_Zicboz_Zifencei_Zca_Zba_Zbb_Zbc_Zbs # _Zbkb_Zcb physical_addr_sz: 32 User_Spec_Version: '2.3' diff --git a/tests/riscof/spike/spike_rv64gc_isa.yaml b/tests/riscof/spike/spike_rv64gc_isa.yaml index 471fbbb13..4374ad07c 100644 --- a/tests/riscof/spike/spike_rv64gc_isa.yaml +++ b/tests/riscof/spike/spike_rv64gc_isa.yaml @@ -2,8 +2,7 @@ hart_ids: [0] hart0: # ISA: RV64IMAFDCSUZicsr_Zicboz_Zifencei_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb # ISA: RV64IMAFDCSUZicsr_Zifencei_Zca_Zcb_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb -# ISA: RV64IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb - ISA: RV64IMAFDCSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb + ISA: RV64IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb physical_addr_sz: 56 User_Spec_Version: '2.3' supported_xlen: [64]