diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index cbdcf91c1..5bb7d2c9a 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -633,7 +633,7 @@ connect_debug_port u_ila_0/probe125 [get_nets [list {wallypipelinedsoc/core/lsu/ create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe126] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe126] -connect_debug_port u_ila_0/probe126 [get_nets [list {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/interlockfsm/InterlockCurrState} ]] +connect_debug_port u_ila_0/probe126 [get_nets [list {m_axi_rready} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe127] @@ -924,8 +924,4 @@ set_property port_width 1 [get_debug_ports u_ila_0/probe183] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe183] connect_debug_port u_ila_0/probe183 [get_nets [list {m_axi_rlast} ]] -create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe184] -set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe184] -connect_debug_port u_ila_0/probe184 [get_nets [list {m_axi_rready} ]] diff --git a/fpga/generator/wave_config.wcfg b/fpga/generator/wave_config.wcfg index 1d64470ac..144f881e5 100644 --- a/fpga/generator/wave_config.wcfg +++ b/fpga/generator/wave_config.wcfg @@ -3,29 +3,29 @@ - + - - - + + + - - + + - + - - - - - - - + + + + + + + FullPathName @@ -82,17 +82,10 @@ true STYLE_DIGITAL - - FullPathName - wallypipelinedsoc/core/lsu/ReadDataM[63:0] - ReadDataM[63:0] - HEXRADIX - true - STYLE_DIGITAL - CPU to LSU label + FullPathName wallypipelinedsoc/core/IEUAdrM[63:0] @@ -109,6 +102,14 @@ true STYLE_DIGITAL + + FullPathName + wallypipelinedsoc/core/lsu/ReadDataM[63:0] + ReadDataM[63:0] + HEXRADIX + true + STYLE_DIGITAL + FullPathName wallypipelinedsoc/core/lsu/WriteDataM[63:0] @@ -118,50 +119,6 @@ STYLE_DIGITAL - - FullPathName - wallypipelinedsoc/core/IEUAdrM[63:0] - IEUAdrM[63:0] - HEXRADIX - true - STYLE_DIGITAL - - - FullPathName - wallypipelinedsoc/core/MemRWM[1:0] - MemRWM[1:0] - HEXRADIX - true - STYLE_DIGITAL - - - FullPathName - wallypipelinedsoc/core/lsu/WriteDataM[63:0] - WriteDataM[63:0] - HEXRADIX - true - STYLE_DIGITAL - - - xIP - label - - FullPathName - wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW_5[9:9] - MIP_REGW_5[9:9] - HEXRADIX - true - STYLE_DIGITAL - - - - FullPathName - wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW_5[9:9] - MIP_REGW_5[9:9] - HEXRADIX - true - STYLE_DIGITAL - PLIC label @@ -169,6 +126,7 @@ interrupts label + FullPathName wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0] @@ -251,71 +209,14 @@ STYLE_DIGITAL - - xIE - label - - FullPathName - wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW_1[1:1] - MIE_REGW_1[1:1] - HEXRADIX - true - STYLE_DIGITAL - - - FullPathName - wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW_2[3:3] - MIE_REGW_2[3:3] - HEXRADIX - true - STYLE_DIGITAL - - - FullPathName - wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW_3[5:5] - MIE_REGW_3[5:5] - HEXRADIX - true - STYLE_DIGITAL - - - FullPathName - wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW_4[7:7] - MIE_REGW_4[7:7] - HEXRADIX - true - STYLE_DIGITAL - - - FullPathName - wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW_5[9:9] - MIE_REGW_5[9:9] - HEXRADIX - true - STYLE_DIGITAL - - - FullPathName - wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[11:11] - MIE_REGW[11:11] - HEXRADIX - true - STYLE_DIGITAL - - - - sdc - label - dcache label - - label + FullPathName wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[3:0] CurrState[3:0] - BINARYRADIX + HEXRADIX true STYLE_DIGITAL dcache fsm @@ -324,7 +225,6 @@ EBU label - FullPathName wallypipelinedsoc/core/ebu.ebu/HTRANS[1:0] @@ -365,9 +265,12 @@ STYLE_DIGITAL + FullPathName wallypipelinedsoc/core/HRDATA[63:0] HRDATA[63:0] HEXRADIX + true + STYLE_DIGITAL FullPathName @@ -620,27 +523,6 @@ STYLE_DIGITAL - - FullPathName - wallypipelinedsoc/core/hzu/StallM - StallM - true - STYLE_DIGITAL - - - FullPathName - wallypipelinedsoc/core/priv.priv/trap/mretM - mretM - true - STYLE_DIGITAL - - - FullPathName - wallypipelinedsoc/core/priv.priv/trap/sretM - sretM - true - STYLE_DIGITAL - faults label @@ -722,6 +604,95 @@ STYLE_DIGITAL + + hazards + label + + wallypipelinedsoc/core/hzu/BPPredWrongE + BPPredWrongE + + + wallypipelinedsoc/core/hzu/BreakpointFaultM + BreakpointFaultM + + + wallypipelinedsoc/core/hzu/CSRRdStallD + CSRRdStallD + + + wallypipelinedsoc/core/hzu/CSRWriteFencePendingDEM + CSRWriteFencePendingDEM + + + wallypipelinedsoc/core/hzu/DivBusyE + DivBusyE + + + wallypipelinedsoc/core/hzu/EcallFaultM + EcallFaultM + + + wallypipelinedsoc/core/hzu/FDivBusyE + FDivBusyE + + + wallypipelinedsoc/core/hzu/IFUStallF + IFUStallF + + + wallypipelinedsoc/core/hzu/LoadStallD + LoadStallD + + + wallypipelinedsoc/core/hzu/LSUStallM + LSUStallM + + + wallypipelinedsoc/core/hzu/MDUStallD + MDUStallD + + + wallypipelinedsoc/core/hzu/StoreStallD + StoreStallD + + + + flush/stall + label + + + wallypipelinedsoc/core/hzu/FlushD + FlushD + + + wallypipelinedsoc/core/hzu/FlushE + FlushE + + + wallypipelinedsoc/core/hzu/FlushM + FlushM + + + wallypipelinedsoc/core/hzu/FlushW + FlushW + + + wallypipelinedsoc/core/hzu/StallD + StallD + + + wallypipelinedsoc/core/hzu/StallE + StallE + + + wallypipelinedsoc/core/hzu/StallF + StallF + + + wallypipelinedsoc/core/hzu/StallM + StallM + + FullPathName wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[63:0] @@ -739,58 +710,120 @@ STYLE_DIGITAL - label + FullPathName wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[3:0] CurrState[3:0] HEXRADIX icache fsm + true + STYLE_DIGITAL - label + FullPathName wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[2:0] CurrState[2:0] HEXRADIX ifu bus fsm + true + STYLE_DIGITAL + FullPathName wallypipelinedsoc/core/ifu/PCNextF[63:0] PCNextF[63:0] HEXRADIX + true + STYLE_DIGITAL + FullPathName wallypipelinedsoc/core/ifu/PCPF[55:0] PCPF[55:0] HEXRADIX + true + STYLE_DIGITAL + FullPathName wallypipelinedsoc/core/lsu/DTLBMissM DTLBMissM + true + STYLE_DIGITAL + FullPathName wallypipelinedsoc/core/lsu/DTLBWriteM DTLBWriteM + true + STYLE_DIGITAL + FullPathName wallypipelinedsoc/core/lsu/ITLBMissF ITLBMissF + true + STYLE_DIGITAL + FullPathName wallypipelinedsoc/core/lsu/ITLBWriteF ITLBWriteF + true + STYLE_DIGITAL + FullPathName wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[63:0] MEPC_REGW[63:0] HEXRADIX + true + STYLE_DIGITAL + FullPathName wallypipelinedsoc/core/priv.priv/csr/csrs/SEPC_REGW[63:0] SEPC_REGW[63:0] HEXRADIX + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/interlockfsm/InterlockCurrState + InterlockCurrState + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/hptw/WalkerState[3:0] + WalkerState[3:0] + HEXRADIX + true + STYLE_DIGITAL + FullPathName wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[63:0] rf[2]__0[63:0] HEXRADIX + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[63:0] + rf[4]__0[63:0] + HEXRADIX + true + STYLE_DIGITAL + + + FullPathName + wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63:0] + rf[10]__0[63:0] + HEXRADIX + true + STYLE_DIGITAL