From 9514abf0e062dd636be89c00da91504bea753e3c Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 17 Jul 2022 01:39:57 +0000 Subject: [PATCH] Don't delete hdl directory at end of run --- synthDC/Makefile | 2 +- synthDC/extractSummary.py | 7 +++++++ synthDC/scripts/synth.tcl | 2 +- 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index 369529e39..98b719428 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -107,7 +107,7 @@ ifeq ($(SAIFPOWER), 1) cp -f ../pipelined/regression/power.saif . endif dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out - rm -rf $(OUTPUTDIR)/hdl +# rm -rf $(OUTPUTDIR)/hdl rm -rf $(OUTPUTDIR)/WORK rm -rf $(OUTPUTDIR)/alib-52 diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py index 93363a069..29e1c8024 100755 --- a/synthDC/extractSummary.py +++ b/synthDC/extractSummary.py @@ -78,6 +78,13 @@ def freqPlot(tech, width, config): ''' plots delay, area for syntheses with specified tech, module, width ''' + current_directory = os.getcwd() + final_directory = os.path.join(current_directory, 'plots/wally') +# if not os.path.exists(final_directory): +# os.makedirs(final_directory) +# os.chdir(final_directory) + + freqsL, delaysL, areasL = ([[], []] for i in range(3)) for oneSynth in allSynths: if (width == oneSynth.width) & (config == oneSynth.config) & (tech == oneSynth.tech) & ('' == oneSynth.special): diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 251522dc8..9b72849f8 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -56,7 +56,7 @@ set vhdlout_show_unconnected_pins "true" # Due to parameterized Verilog must use analyze/elaborate and not # read_verilog/vhdl (change to pull in Verilog and/or VHDL) # -set alib_library_analysis_path ./$outputDir +#set alib_library_analysis_path ./$outputDir define_design_lib WORK -path ./$outputDir/WORK analyze -f sverilog -lib WORK $my_verilog_files elaborate $my_toplevel -lib WORK