diff --git a/addins/ahbsdc b/addins/ahbsdc deleted file mode 160000 index 33418c8dc..000000000 --- a/addins/ahbsdc +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 33418c8dc11baf63e843b0d35f57d22c1e3182e3 diff --git a/addins/cvw-arch-verif b/addins/cvw-arch-verif index 189974e49..6d658b7b4 160000 --- a/addins/cvw-arch-verif +++ b/addins/cvw-arch-verif @@ -1 +1 @@ -Subproject commit 189974e497d7b8d2c08bb1d151b1ccdeaf3a64c9 +Subproject commit 6d658b7b42c83fd584008d72964cc75d0876b769 diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index 7152865ac..3843c736e 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit 7152865aca51062c87ff2cbb014e199a24bdc874 +Subproject commit 3843c736e427a2b52a0d06e6220b073afa4be401 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-spi-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-spi-01.reference_output index e19f75391..027e02f54 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-spi-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-spi-01.reference_output @@ -146,30 +146,6 @@ 00000015 -00000010 - -00000010 - -00000010 - -00000010 - -00000010 - -00000010 - -00000011 - -00000011 - -00000011 - -00000011 - -00000011 - -00000011 - 00000011 #delay1 00000022 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-spi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-spi-01.S index 19b70829c..94defaf87 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-spi-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-spi-01.S @@ -316,87 +316,11 @@ test_cases: .4byte 0x0, 0x00000000, spi_data_wait # wait for transmission to end .4byte rx_data, 0x00000015, read32_test # read rx_data -# SCKCS Delay of 0, SCKMODE 10 -.4byte sck_mode, 0x00000002, write32_test #set sckmode to 10 -.4byte delay0, 0x00000001, write32_test # set sckcs delay to 0 -.4byte tx_data, 0x00000010, write32_test # place 10 into tx_data -.4byte 0x0, 0x00000000, spi_data_wait #wait for transmission -.4byte rx_data, 0x00000010, read32_test # reade rx_data - -# Arbitrary SCKCS delay, SCKMODE 10 -.4byte delay0, 0x00050001, write32_test # set sckcs delay to 5 -.4byte tx_data, 0x00000010, write32_test # place 10 into tx_data -.4byte 0x0, 0x00000000, spi_data_wait #wait for transmission -.4byte rx_data, 0x00000010, read32_test # reade rx_data - -# Long SCKCS delay, SCKMODE 10 -.4byte delay0, 0x00A50001, write32_test # set sckcs delay to 0 -.4byte tx_data, 0x00000010, write32_test # place 10 into tx_data -.4byte 0x0, 0x00000000, spi_data_wait #wait for transmission -.4byte rx_data, 0x00000010, read32_test # reade rx_data - -# CSSCK Delay 0, SCKMODE 10 -.4byte delay0, 0x00010000, write32_test # set sckcs delay to 0 -.4byte tx_data, 0x00000010, write32_test # place 10 into tx_data -.4byte 0x0, 0x00000000, spi_data_wait #wait for transmission -.4byte rx_data, 0x00000010, read32_test # reade rx_data - -# Arbitrary CSSCK delay, SCKMODE 10 -.4byte delay0, 0x00010005, write32_test # set sckcs delay to 0 -.4byte tx_data, 0x00000010, write32_test # place 10 into tx_data -.4byte 0x0, 0x00000000, spi_data_wait #wait for transmission -.4byte rx_data, 0x00000010, read32_test # reade rx_data - -# Long CSSCK delay, SCKMODE 10 -.4byte delay0, 0x000100A5, write32_test # set sckcs delay to 0 -.4byte tx_data, 0x00000010, write32_test # place 10 into tx_data -.4byte 0x0, 0x00000000, spi_data_wait #wait for transmission -.4byte rx_data, 0x00000010, read32_test # reade rx_data - - - -# SCKCS Delay of 0, SCKMODE 11 -.4byte sck_mode, 0x00000003, write32_test -.4byte delay0, 0x00000001, write32_test # set sckcs delay to 0 -.4byte tx_data, 0x00000011, write32_test # place 10 into tx_data -.4byte 0x0, 0x00000000, spi_data_wait #wait for transmission -.4byte rx_data, 0x00000011, read32_test # reade rx_data - -# Arbitrary SCKCS delay, SCKMODE 11 -.4byte delay0, 0x00050001, write32_test # set sckcs delay to 0 -.4byte tx_data, 0x00000011, write32_test # place 10 into tx_data -.4byte 0x0, 0x00000000, spi_data_wait #wait for transmission -.4byte rx_data, 0x00000011, read32_test # reade rx_data - -# Long SCKCS delay, SCKMODE 11 -.4byte delay0, 0x00A50001, write32_test # set sckcs delay to 0 -.4byte tx_data, 0x00000011, write32_test # place 10 into tx_data -.4byte 0x0, 0x00000000, spi_data_wait #wait for transmission -.4byte rx_data, 0x00000011, read32_test # reade rx_data - -# CSSCK Delay 0, SCKMODE 11 -.4byte delay0, 0x00010000, write32_test # set sckcs delay to 0 -.4byte tx_data, 0x00000011, write32_test # place 10 into tx_data -.4byte 0x0, 0x00000000, spi_data_wait #wait for transmission -.4byte rx_data, 0x00000011, read32_test # reade rx_data - -# Arbitrary CSSCK delay, SCKMODE 11 -.4byte delay0, 0x00010005, write32_test # set sckcs delay to 0 -.4byte tx_data, 0x00000011, write32_test # place 10 into tx_data -.4byte 0x0, 0x00000000, spi_data_wait #wait for transmission -.4byte rx_data, 0x00000011, read32_test # reade rx_data - -# Long CSSCK delay, SCKMODE 11 -.4byte delay0, 0x000100A5, write32_test # set sckcs delay to 0 -.4byte tx_data, 0x00000011, write32_test # place 10 into tx_data -.4byte 0x0, 0x00000000, spi_data_wait #wait for transmission -.4byte rx_data, 0x00000011, read32_test # reade rx_data - # =========== Test delay1 register =========== # Test inter cs delay -.4byte sck_mode, 0x00000000, write32_test #reset sck_mode + .4byte delay0, 0x00010001, write32_test # reset delay0 register .4byte delay1, 0x00000005, write32_test # set inter_cs delay to 5 .4byte rx_mark, 0x0000003, write32_test # preset rx watermark b/c of hardware interlock diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-spi-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-spi-01.reference_output index bc17f4beb..8d9ae8bbc 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-spi-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-spi-01.reference_output @@ -146,30 +146,6 @@ 00000000 00000015 00000000 -00000010 -00000000 -00000010 -00000000 -00000010 -00000000 -00000010 -00000000 -00000010 -00000000 -00000010 -00000000 -00000011 -00000000 -00000011 -00000000 -00000011 -00000000 -00000011 -00000000 -00000011 -00000000 -00000011 -00000000 00000011 #delay1 00000000 00000022 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-spi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-spi-01.S index a31069470..23cfd169a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-spi-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-spi-01.S @@ -258,7 +258,7 @@ test_cases: .8byte 0x0, 0x00000000, spi_data_wait # wait for transmission to end .8byte rx_data, 0x00000011, read32_test # read rx_data -# =========== Test delay0 register (mode auto)=========== +# =========== Test delay0 register =========== # Test cs-sck delay of 0 with sck phase = 0 (implicit half cycle delay) @@ -320,87 +320,11 @@ test_cases: .8byte 0x0, 0x00000000, spi_data_wait # wait for transmission to end .8byte rx_data, 0x00000015, read32_test # read rx_data -# SCKCS Delay of 0, SCKMODE 10 -.8byte sck_mode, 0x00000002, write32_test #set sckmode to 10 -.8byte delay0, 0x00000001, write32_test # set sckcs delay to 0 -.8byte tx_data, 0x00000010, write32_test # place 10 into tx_data -.8byte 0x0, 0x00000000, spi_data_wait #wait for transmission -.8byte rx_data, 0x00000010, read32_test # reade rx_data - -# Arbitrary SCKCS delay, SCKMODE 10 -.8byte delay0, 0x00050001, write32_test # set sckcs delay to 5 -.8byte tx_data, 0x00000010, write32_test # place 10 into tx_data -.8byte 0x0, 0x00000000, spi_data_wait #wait for transmission -.8byte rx_data, 0x00000010, read32_test # reade rx_data - -# Long SCKCS delay, SCKMODE 10 -.8byte delay0, 0x00A50001, write32_test # set sckcs delay to 0 -.8byte tx_data, 0x00000010, write32_test # place 10 into tx_data -.8byte 0x0, 0x00000000, spi_data_wait #wait for transmission -.8byte rx_data, 0x00000010, read32_test # reade rx_data - -# CSSCK Delay 0, SCKMODE 10 -.8byte delay0, 0x00010000, write32_test # set sckcs delay to 0 -.8byte tx_data, 0x00000010, write32_test # place 10 into tx_data -.8byte 0x0, 0x00000000, spi_data_wait #wait for transmission -.8byte rx_data, 0x00000010, read32_test # reade rx_data - -# Arbitrary CSSCK delay, SCKMODE 10 -.8byte delay0, 0x00010005, write32_test # set sckcs delay to 0 -.8byte tx_data, 0x00000010, write32_test # place 10 into tx_data -.8byte 0x0, 0x00000000, spi_data_wait #wait for transmission -.8byte rx_data, 0x00000010, read32_test # reade rx_data - -# Long CSSCK delay, SCKMODE 10 -.8byte delay0, 0x000100A5, write32_test # set sckcs delay to 0 -.8byte tx_data, 0x00000010, write32_test # place 10 into tx_data -.8byte 0x0, 0x00000000, spi_data_wait #wait for transmission -.8byte rx_data, 0x00000010, read32_test # reade rx_data - - - -# SCKCS Delay of 0, SCKMODE 11 -.8byte sck_mode, 0x00000003, write32_test -.8byte delay0, 0x00000001, write32_test # set sckcs delay to 0 -.8byte tx_data, 0x00000011, write32_test # place 10 into tx_data -.8byte 0x0, 0x00000000, spi_data_wait #wait for transmission -.8byte rx_data, 0x00000011, read32_test # reade rx_data - -# Arbitrary SCKCS delay, SCKMODE 11 -.8byte delay0, 0x00050001, write32_test # set sckcs delay to 0 -.8byte tx_data, 0x00000011, write32_test # place 10 into tx_data -.8byte 0x0, 0x00000000, spi_data_wait #wait for transmission -.8byte rx_data, 0x00000011, read32_test # reade rx_data - -# Long SCKCS delay, SCKMODE 11 -.8byte delay0, 0x00A50001, write32_test # set sckcs delay to 0 -.8byte tx_data, 0x00000011, write32_test # place 10 into tx_data -.8byte 0x0, 0x00000000, spi_data_wait #wait for transmission -.8byte rx_data, 0x00000011, read32_test # reade rx_data - -# CSSCK Delay 0, SCKMODE 11 -.8byte delay0, 0x00010000, write32_test # set sckcs delay to 0 -.8byte tx_data, 0x00000011, write32_test # place 10 into tx_data -.8byte 0x0, 0x00000000, spi_data_wait #wait for transmission -.8byte rx_data, 0x00000011, read32_test # reade rx_data - -# Arbitrary CSSCK delay, SCKMODE 11 -.8byte delay0, 0x00010005, write32_test # set sckcs delay to 0 -.8byte tx_data, 0x00000011, write32_test # place 10 into tx_data -.8byte 0x0, 0x00000000, spi_data_wait #wait for transmission -.8byte rx_data, 0x00000011, read32_test # reade rx_data - -# Long CSSCK delay, SCKMODE 11 -.8byte delay0, 0x000100A5, write32_test # set sckcs delay to 0 -.8byte tx_data, 0x00000011, write32_test # place 10 into tx_data -.8byte 0x0, 0x00000000, spi_data_wait #wait for transmission -.8byte rx_data, 0x00000011, read32_test # reade rx_data - # =========== Test delay1 register =========== # Test inter cs delay -.8byte sck_mode, 0x00000000, write32_test #reset sck_mode + .8byte delay0, 0x00010001, write32_test # reset delay0 register .8byte delay1, 0x00000005, write32_test # set inter_cs delay to 5 .8byte rx_mark, 0x0000003, write32_test # preset rx watermark b/c of hardware interlock