diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index b4d2d1b60..de6eb166c 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -27,7 +27,6 @@ add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/PendingInterruptM add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/hzu/FlushF add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE @@ -92,7 +91,7 @@ add wave -noupdate -group Bpred -group {branch update selection inputs} /testben add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong -add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 16 -radix binary}} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel +add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 17 -radix binary}} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNext add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRUpdateEN add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr @@ -214,7 +213,6 @@ add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/ add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/SelReplayCPURequest add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/RAdr @@ -383,7 +381,6 @@ add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/GPIOIntr add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADPLIC add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HRESPPLIC add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADYPLIC -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/ExtIntM add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intClaim add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intEn add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intInProgress @@ -391,11 +388,11 @@ add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/pl add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intPriority add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intThreshold add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/nextIntPending -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/pendingArray -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/pendingMaxP -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/pendingPGrouped -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/pendingRequestsAtMaxP add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/requests +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/irqMatrix +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/priorities_with_irqs +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/max_priority_with_irqs +add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/irqs_at_max_priority add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/threshMask add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HCLK add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HSELGPIO @@ -425,21 +422,21 @@ add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIME add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIMECMP add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/TimerIntM add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/SwIntM -add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HCLK -add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HRESETn -add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HSELUART -add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HADDR -add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HWRITE -add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HWDATA -add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HREADUART -add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HRESPUART -add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HREADYUART -add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/LSR -add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/MCR -add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/MSR -add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/RBR -add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/TXHR -add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/LCR +add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HCLK +add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HRESETn +add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HSELUART +add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HADDR +add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HWRITE +add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HWDATA +add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HREADUART +add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HRESPUART +add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HREADYUART +add wave -noupdate -group uart -expand -group Registers -expand /testbench/dut/uncore/uart/uart/u/LSR +add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uart/uart/u/MCR +add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uart/uart/u/MSR +add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uart/uart/u/RBR +add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uart/uart/u/TXHR +add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uart/uart/u/LCR add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/INTR add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxstate add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txstate @@ -448,6 +445,11 @@ add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txbitsexpected add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxbitsreceived add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxbitsexpected add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxdata +add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxoverrunerr +add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxdataready +add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxdataavailintr +add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/RXBR +add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/squashRXerrIP add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxshiftreg add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/SOUTbit add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/SINsync @@ -526,4 +528,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {0 ns} {496 ns} +WaveRestoreZoom {0 ns} {208 ns} diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PERIPH.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PERIPH.reference_output index a67889e2a..7b23883c6 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PERIPH.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PERIPH.reference_output @@ -430,3 +430,67 @@ FFFFFF33 00000000 00000000 00000000 +04BEEF1B +00000009 +80000000 +0000000A +00000004 +00000061 +00000061 +00000065 +00000060 +00000001 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +04BEEF1C +00000009 +80000000 +00000003 +00080000 +00080000 +00080000 +00000000 +00000000 +00000000 +00080000 +00080000 +FFFFFFFF +FFF7FFFF +00000000 +00000000 +04BEEF1D +00000009 +80000000 +00000003 +00000001 +00000001 +00000001 +00000000 +00080000 +00000000 +00080001 +00000001 +FFFFFFFF +FFFFFFFE +00000000 +00000000 +04BEEF1E +00000009 +80000000 +0000000A +00000004 +00000061 +00000061 +0000006e +00000060 +00000001 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PERIPH.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PERIPH.S index 9a42f2193..c44d7a681 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PERIPH.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PERIPH.S @@ -41,11 +41,12 @@ trap_handler: ##### ################### ################### # save registers - addi sp, sp, 0x20 + addi sp, sp, 0x28 sw t0, 0x00(sp) sw t1, 0x08(sp) sw t2, 0x10(sp) sw t3, 0x18(sp) + sw t4, 0x20(sp) # =================================== # ===== Signature Output Format ===== @@ -56,7 +57,7 @@ trap_handler: ##### # # : # 0x00: test ID = 0xBEEF - # 0x04: mcause (low) = 0x0000000B + # 0x04: mcause (low) = 0x0000000B (MEIP) or 0x00000009 (SEIP) # 0x08: mcause (high) = 0x80000000 # ----- If GPIO ----- # 0x0C: claim ID = 3 @@ -87,18 +88,26 @@ trap_handler: ##### add t0, t0, a1 sw t0, 0x00(s0) - # 0x04: mcause (low) = 0x0000000B + # 0x04: mcause (low) = 0x0000000B (MEIP) or 0x00000009 (SEIP) # 0x08: mcause (high) = 0x80000000 - # Expect interrupt from src 11 (machine external interrupt) - csrrc t1, mcause, x0 - sw t1, 0x04(s0) - srli t1,t1,32 - sw t1, 0x08(s0) + csrrc t0, mcause, x0 + andi t1, t0, 0x7FF + sw t0, 0x04(s0) + srli t0,t0,32 + sw t0, 0x08(s0) + # MEIP or SEIP? + # MEIP is on context 0 + li t4, 0x0C200004 + li t0, 0xB + beq t1, t0, meip + # SEIP is on context 1 + li t4, 0x0C201004 + meip: - # 0x: claim ID + # 0x0C: claim ID # 3: GPIO # A: UART - li t0, 0x0C200004 + mv t0, t4 lw t1, 0(t0) sw t1, 0x0C(s0) li t2, 0xA @@ -150,7 +159,7 @@ trap_handler: ##### # signal to main code that gpio was serviced ori a0, a0, 0b00001000 # signal to plic that gpio was serviced - li t0, 0x0C200004 + mv t0, t4 li t1, 3 sw t1, 0(t0) j trap_handler_end @@ -181,7 +190,7 @@ trap_handler: ##### # signal to main code that uart was serviced ori a0, a0, 0b00010000 # signal to plic that uart was serviced - li t0, 0x0C200004 + mv t0, t4 li t1, 0xA sw t1, 0(t0) @@ -193,7 +202,8 @@ trap_handler: ##### ld t1, 0x08(sp) ld t2, 0x10(sp) ld t3, 0x18(sp) - addi sp, sp, SEXT_IMM(-0x20) + ld t4, 0x20(sp) + addi sp, sp, SEXT_IMM(-0x28) mret ################ @@ -267,7 +277,7 @@ main_code: ##### # set MEIE li t0, 0x800 csrrs x0, mie, t0 -Intr01BEEF01: +Intr01BEEF00: # UART TX 'h' li t0, 0x10000000 li t1, 'h' @@ -276,7 +286,7 @@ Intr01BEEF01: li t1, 0b00010000 1: bne t1,a0,1b li a0, 0 -Intr01BEEF02: +Intr01BEEF01: # GPIO raise pin 19 li t0, 0x10060000 li t1, 0x00080000 @@ -286,12 +296,12 @@ Intr01BEEF02: 1: bne t1,a0,1b li a0, 0 # Now let's go bonkers and trigger both! -Intr01BEEF03: +Intr01BEEF02: # TX 'e' li t0, 0x10000000 li t1, 'e' sb t1, 0(t0) -Intr01BEEF04: +Intr01BEEF03: # GPIO lower pin 19 raise pin 0 li t0, 0x10060000 li t1, 0x00000001 @@ -787,6 +797,91 @@ Intr03BEEF1A: li t1, 0b00010000 1: bne t1,a0,1b li a0, 0 + + #################################################### + ##### Test 4 - Signs of Life on PLIC Context 1 ##### + #################################################### + li a1, 0x04beef00 # group ID + # clear MEIE (good to turn off while configuring peripherals) + li t0, 0x800 + csrrc x0, mie, t0 + # ========== Configure PLIC ========== + # priority threshold = 0 + li t0, 0xC200000 + li t1, 0 + sw t1, 0(t0) + # source 3 (GPIO) priority = 6 + li t0, 0xC000000 + li t1, 6 + sw t1, 0x0C(t0) + # source 0xA (UART) priority = 7 + li t1, 7 + sw t1, 0x28(t0) + # disable sources 3,0xA on context 0 + li t0, 0x0C002000 + li t1, 0 + sw t1, 0(t0) + # enable sources 3,0xA on context 1 + li t0, 0x0C002080 + li t1, 0b10000001000 + sw t1, 0(t0) + # ========== Configure UART ========== + # MCR: Loop = 1 + li t0, 0x10000000 + li t1, 0b10000 + sb t1, 4(t0) + # LCR: Use 8 data bits plus odd parity bit + li t1, 0b00001011 + sb t1, 3(t0) + # IER: Enable Received Data Available Interrupt + li t1, 0x01 + sb t1, 1(t0) + # ========== Configure GPIO ========== + # raise all input_en + li t0, 0x10060000 + li t1, 0xFFFFFFFF + sw t1, 0x04(t0) + # raise all output_en + sw t1, 0x08(t0) + # raise all input_en + sw t1, 0x18(t0) + # ========== Execute Test ========== + # set MEIE and SEIE + li t0, 0xA00 + csrrs x0, mie, t0 +Intr04BEEF1B: + # UART TX 'e' + li t0, 0x10000000 + li t1, 'e' + sb t1, 0(t0) + # wait to finish + li t1, 0b00010000 + 1: bne t1,a0,1b + li a0, 0 +Intr04BEEF1C: + # GPIO raise pin 19 + li t0, 0x10060000 + li t1, 0x00080000 + sw t1, 0x0C(t0) + # wait to finish + li t1, 0b00001000 + 1: bne t1,a0,1b + li a0, 0 + # Now let's go bonkers and trigger both! +Intr04BEEF1D: + # TX 'n' + li t0, 0x10000000 + li t1, 'n' + sb t1, 0(t0) +Intr04BEEF1E: + # GPIO lower pin 19 raise pin 0 + li t0, 0x10060000 + li t1, 0x00000001 + sw t1, 0x0C(t0) + # wait to finish + li t1, 0b00011000 + 1: bne t1,a0,1b + li a0, 0 # --------------------------------------------------------------------------------------------- //terminate_test: