From 9e83b0bfafd4a02eccc46e7fdf98e41ced59962f Mon Sep 17 00:00:00 2001
From: James Stine <james.stine@okstate.edu>
Date: Thu, 16 Feb 2023 08:07:17 -0600
Subject: [PATCH] Update topo psyn stuff

---
 synthDC/.synopsys_dc.setup | 20 ++++++++++++++++++++
 synthDC/Makefile           |  4 +++-
 synthDC/scripts/synth.tcl  | 30 ++++++++++++++++++++++++++++++
 synthDC/wallySynth.py      |  4 ++--
 4 files changed, 55 insertions(+), 3 deletions(-)

diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup
index 2fdc11c27..1310c4dd7 100755
--- a/synthDC/.synopsys_dc.setup
+++ b/synthDC/.synopsys_dc.setup
@@ -21,6 +21,21 @@ if {$tech == "sky130"} {
     set s10lib /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a
     lappend search_path $s10lib
 }
+elseif {$tech == "tsmc28psyn"} {
+    set TLU /home/jstine/TLU+
+    set s10lib /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a
+    lappend search_path $s10lib
+    set TLUPLUS true
+    set mw_logic1_net VDD
+    set mw_logic0_net VSS
+    set TLU_PDK /import/yukari1/jstine/TLU+/
+    set CAPTABLE $TLU/1p8m/
+    set MW_REFERENCE_LIBRARY /home/jstine/MW
+    set MW_TECH_FILE tcbn28hpcplusbwp7t30p140
+    set MAX_TLU_FILE $CAPTABLE/crn28hpc+_1p08m+ut-alrdl_5x1z1u_typical.tluplus
+    set MIN_TLU_FILE $CAPTABLE/crn28hpc+_1p08m+ut-alrdl_5x1z1u_rcworst.tluplus
+    set PRS_MAP_FILE $MW_REFERENCE_LIBRARY/astro_layername.map
+}
 
 # Synthetic libraries
 set synthetic_library   [list dw_foundation.sldb]
@@ -36,6 +51,11 @@ if {$tech == "sky130"} {
 } elseif {$tech == "tsmc28"} {
     lappend target_library $s10lib/tcbn28hpcplusbwp30p140tt0p9v25c.db
 }
+} elseif {$tech == "tsmc28psyn"} {
+    set mw_reference_library [list ]    
+    lappend target_library $s10lib/tcbn28hpcplusbwp30p140tt0p9v25c.db
+    lappend mw_reference_library $MW_REFERENCE_LIBRARY/tcbn28hpcplusbwp7t30p140    
+}
 
 # Set Link Library
 set link_library "$target_library $synthetic_library"
diff --git a/synthDC/Makefile b/synthDC/Makefile
index 76531d950..d7fb2b914 100755
--- a/synthDC/Makefile
+++ b/synthDC/Makefile
@@ -122,6 +122,8 @@ synth: mkdirecs configs rundc clean
 rundc:
 	dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out
 	
+rundctopo:
+	dc_shell-xg-t -64bit -topographical_mode -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out
 	
 clean:
 	rm -rf $(OUTPUTDIR)/hdl
@@ -132,4 +134,4 @@ clean:
 	rm -f filenames*.log
 	rm -f power.saif
 	rm -f Synopsys_stack_trace_*.txt
-	rm -f crte_*.txt
\ No newline at end of file
+	rm -f crte_*.txt
diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl
index 1040f35ce..830203520 100755
--- a/synthDC/scripts/synth.tcl
+++ b/synthDC/scripts/synth.tcl
@@ -49,6 +49,36 @@ set report_default_significant_digits 6
 set verilogout_show_unconnected_pins "true"
 set vhdlout_show_unconnected_pins "true"
 
+#  Set up MW List
+set MY_LIB_NAME $my_toplevel
+# Create MW
+if { [shell_is_in_topographical_mode] } {
+    echo "In Topographical Mode...processing\n"
+    if {[file isdirectory $MY_LIB_NAME]} {
+	echo "MW directory already here, deleting/readdding."
+	[exec rm -rf $my_toplevel]
+	create_mw_lib  -technology $MW_REFERENCE_LIBRARY/$MW_TECH_FILE.tf \
+	    -mw_reference_library $mw_reference_library $MY_LIB_NAME
+    } else {
+	create_mw_lib  -technology $MW_REFERENCE_LIBRARY/$MW_TECH_FILE.tf \
+	    -mw_reference_library $mw_reference_library $MY_LIB_NAME
+    }
+
+    # Open MW
+    open_mw_lib $MY_LIB_NAME
+    
+    # TLU+
+    set_tlu_plus_files -max_tluplus $MAX_TLU_FILE -min_tluplus $MIN_TLU_FILE \
+	-tech2itf_map $PRS_MAP_FILE
+
+} else {
+    if {[file isdirectory $MY_LIB_NAME]} {
+	[exec rm -rf $my_toplevel]
+	echo "MW directory already here, deleting."
+    }
+    echo "In normal DC mode...processing\n"
+}
+
 # Due to parameterized Verilog must use analyze/elaborate and not 
 # read_verilog/vhdl (change to pull in Verilog and/or VHDL)
 #
diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py
index 3253607d5..cfcfde788 100755
--- a/synthDC/wallySynth.py
+++ b/synthDC/wallySynth.py
@@ -16,7 +16,7 @@ def mask(command):
 
 if __name__ == '__main__':
     
-    techs = ['sky90', 'tsmc28']
+    techs = ['sky90', 'tsmc28', 'tsmc28psyn']
     allConfigs = ['rv32gc', 'rv32imc', 'rv64gc', 'rv64imc', 'rv32e', 'rv32i', 'rv64i']
     freqVaryPct = [-20, -12, -8, -6, -4, -2, 0, 2, 4, 6, 8, 12, 20]
 
@@ -61,4 +61,4 @@ if __name__ == '__main__':
         defaultfreq = 500 if tech == 'sky90' else 1500
         freq = args.targetfreq if args.targetfreq else defaultfreq
         config = args.version if args.version else 'rv64gc'
-        runSynth(config, mod, tech, freq, maxopt, usesram)
\ No newline at end of file
+        runSynth(config, mod, tech, freq, maxopt, usesram)