From 9f9c3bcece1408dd9b132053dcd58823bd70c95e Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 2 Feb 2021 14:22:12 -0500
Subject: [PATCH] Changed DTIM latency to 2 cycles

---
 wally-pipelined/src/uncore/dtim.sv | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/wally-pipelined/src/uncore/dtim.sv b/wally-pipelined/src/uncore/dtim.sv
index 486f902fd..6a49fcf59 100644
--- a/wally-pipelined/src/uncore/dtim.sv
+++ b/wally-pipelined/src/uncore/dtim.sv
@@ -39,27 +39,21 @@ module dtim (
 //  logic [`XLEN-1:0] write;
   logic [15:0] entry;
   logic            memread, memwrite;
-//  logic busy;
   logic [3:0] busycount;
 
   // busy FSM to extend READY signal
   always_ff @(posedge HCLK, negedge HRESETn) 
     if (~HRESETn) begin
-//      busy <= 0;
       HREADYTim <= 1;
     end else begin
-//      if (~busy & HSELTim) begin
       if (HREADYTim & HSELTim) begin
-//        busy <= 1;
         busycount <= 0;
         HREADYTim <= 0;
-//      end else if (busy) begin
       end else if (~HREADYTim) begin
-        busycount <= busycount + 1;
-        if (busycount == 4) begin // TIM latency, for testing purposes
-//          busy <= 0;
+        if (busycount == 0) begin // TIM latency, for testing purposes
           HREADYTim <= 1;
-        end
+        end else
+          busycount <= busycount + 1;
       end
     end