From a166b522e50fe39808a4b196afd4de6dbcb55450 Mon Sep 17 00:00:00 2001
From: David Harris <David_Harris@hmc.edu>
Date: Wed, 5 Mar 2025 08:39:25 -0800
Subject: [PATCH] Fixed clock edge for Design Compiler compatibility

---
 src/uncore/spi_controller.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/uncore/spi_controller.sv b/src/uncore/spi_controller.sv
index 0ed8e57be..6438d39c5 100644
--- a/src/uncore/spi_controller.sv
+++ b/src/uncore/spi_controller.sv
@@ -207,7 +207,7 @@ module spi_controller (
   // Aligned EXACTLY ON THE MIDDLE of the leading and trailing edges.
   // Sweeeeeeeeeet...
   assign InvertClock = ^SckMode;
-  always_ff @(posedge ~PCLK) begin
+  always_ff @(negedge PCLK) begin
     if (~PRESETn | TransmitStart) begin
       ShiftEdge <= 0;
       SampleEdge <= 0;