diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 852d08b19..480575aa6 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -306,12 +306,12 @@ connect_debug_port u_ila_0/probe58 [get_nets [list wallypipelinedsoc/core/hzu/CS create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe59] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59] -connect_debug_port u_ila_0/probe59 [get_nets [list wallypipelinedsoc/core/hzu/LSUStallW ]] +connect_debug_port u_ila_0/probe59 [get_nets [list wallypipelinedsoc/core/hzu/LSUStallM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe60] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60] -connect_debug_port u_ila_0/probe60 [get_nets [list wallypipelinedsoc/core/hzu/IFUStallD ]] +connect_debug_port u_ila_0/probe60 [get_nets [list wallypipelinedsoc/core/hzu/IFUStallF ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe61] diff --git a/pipelined/regression/fpga-wave.do b/pipelined/regression/fpga-wave.do index 29a606fca..e95443fbe 100644 --- a/pipelined/regression/fpga-wave.do +++ b/pipelined/regression/fpga-wave.do @@ -10,7 +10,7 @@ add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/Ret add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/StoreStallD -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallW +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/MDUStallD add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM @@ -191,7 +191,7 @@ add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HWRITED add wave -noupdate -expand -group lsu -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/InterlockCurrState add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/InterlockStall -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallW +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/WriteDataM diff --git a/pipelined/regression/linux-wave.do b/pipelined/regression/linux-wave.do index bcd34467f..d8bb0f3db 100644 --- a/pipelined/regression/linux-wave.do +++ b/pipelined/regression/linux-wave.do @@ -15,7 +15,7 @@ add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallW +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/ExceptionM add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM @@ -185,7 +185,7 @@ add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/i add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IEUAdrM add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/PAdrM add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallW +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/WriteDataM diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index 22ed684d5..b008df118 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -9,8 +9,8 @@ add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPP add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallD -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallW +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/MDUStallD add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE @@ -218,7 +218,7 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW -add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallW +add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM add wave -noupdate -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM @@ -593,18 +593,18 @@ add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/VPN add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/TLBWrite add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/PTE add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/VAdr -add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/FRD1E -add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/FRD2E -add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/FRD3E -add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcAE -add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcBE -add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/Funct3E -add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/MDUE -add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/W64E -add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/X -add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/Y -add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/Z -add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/fregfile/rf +add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/FRD1E +add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/FRD2E +add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/FRD3E +add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcAE +add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcBE +add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/Funct3E +add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/MDUE +add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/W64E +add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/unpack/X +add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/unpack/Y +add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/unpack/Z +add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/fregfile/rf add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayCntEn @@ -619,8 +619,17 @@ add wave -noupdate /testbench/ResetCount add wave -noupdate /testbench/InReset add wave -noupdate /testbench/DCacheFlushDone add wave -noupdate /testbench/DCacheFlushStart +add wave -noupdate /testbench/dut/core/fpu/fpu/XE +add wave -noupdate /testbench/dut/core/fpu/fpu/YE +add wave -noupdate /testbench/dut/core/fpu/fpu/ZE +add wave -noupdate /testbench/dut/core/fpu/fpu/PostProcResM +add wave -noupdate /testbench/dut/core/fpu/fpu/fregfile/rf +add wave -noupdate /testbench/dut/core/fpu/fpu/fhazard/ForwardXE +add wave -noupdate /testbench/dut/core/fpu/fpu/fhazard/ForwardYE +add wave -noupdate /testbench/dut/core/fpu/fpu/fhazard/ForwardZE +add wave -noupdate /testbench/dut/core/fpu/fpu/fhazard/YEnE TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {128608 ns} 0} +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {4266 ns} 0} quietly wave cursor active 5 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -636,4 +645,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {128173 ns} {130237 ns} +WaveRestoreZoom {4234 ns} {4338 ns} diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv index a96c9dda8..d1694b8b4 100644 --- a/pipelined/src/hazard/hazard.sv +++ b/pipelined/src/hazard/hazard.sv @@ -34,11 +34,11 @@ module hazard( // Detect hazards (* mark_debug = "true" *) input logic BPPredWrongE, CSRWriteFenceM, RetM, TrapM, (* mark_debug = "true" *) input logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD, -(* mark_debug = "true" *) input logic LSUStallW, IFUStallD, +(* mark_debug = "true" *) input logic LSUStallM, IFUStallF, (* mark_debug = "true" *) input logic FCvtIntStallD, FPUStallD, (* mark_debug = "true" *) input logic DivBusyE,FDivBusyE, (* mark_debug = "true" *) input logic EcallFaultM, BreakpointFaultM, -(* mark_debug = "true" *) input logic wfiM, IntPendingM, +(* mark_debug = "true" *) input logic WFIStallM, // Stall & flush outputs (* mark_debug = "true" *) output logic StallF, StallD, StallE, StallM, StallW, (* mark_debug = "true" *) output logic FlushD, FlushE, FlushM, FlushW @@ -75,19 +75,19 @@ module hazard( // Stall causes // Most data depenency stalls are identified in the decode stage // Division stalls in the execute stage - // Flushing the decode or execute stage has priority over stalls. + // Flushing any stage has priority over the corresponding stage stall. // Even if the register gave clear priority over enable, various FSMs still need to disable the stall, so it's best to gate the stall here with flush - // WFI is an odd case. It stalls in the Memory stage until a pending interrupt or timeout trap // The IFU and LSU stall the entire pipeline on a cache miss, bus access, or other long operation. // The IFU stalls the entire pipeline rather than just Fetch to avoid complications with instructions later in the pipeline causing Exceptions // A trap could be asserted at the start of a IFU/LSU stall, and should flush the memory operation assign StallFCause = '0; assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FCvtIntStallD | FPUStallD) & ~FlushDCause; assign StallECause = (DivBusyE | FDivBusyE) & ~FlushECause; - // WFI terminates if any enabled interrupt is pending, even if global interrupts are disabled. It could also terminate with TW trap - assign StallMCause = ((wfiM) & (~TrapM & ~IntPendingM)); - //assign StallWCause = (IFUStallD | LSUStallW) & ~TrapM; - assign StallWCause = (IFUStallD & ~FlushDCause) | (LSUStallW & ~FlushWCause); + assign StallMCause = WFIStallM & ~FlushMCause; + // Need to gate IFUStallF when the equivalent FlushFCause = FlushDCause = 1. + //assign StallWCause = ((IFUStallF & ~FlushDCause) | LSUStallM) & ~FlushWCause; + // Because FlushWCause is a strict subset of FlushDCause, FlushWCause is factored out. + assign StallWCause = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause); // Stall each stage for cause or if the next stage is stalled assign #1 StallF = StallFCause | StallD; diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 2591e60f8..a0eaa20c7 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -38,7 +38,7 @@ module ifu ( // Bus interface (* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA, (* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUHADDR, -(* mark_debug = "true" *) output logic IFUStallD, +(* mark_debug = "true" *) output logic IFUStallF, (* mark_debug = "true" *) output logic [2:0] IFUHBURST, (* mark_debug = "true" *) output logic [1:0] IFUHTRANS, (* mark_debug = "true" *) output logic [2:0] IFUHSIZE, @@ -274,7 +274,7 @@ module ifu ( end assign IFUCacheBusStallD = ICacheStallF | BusStall; - assign IFUStallD = IFUCacheBusStallD | SelNextSpillF; + assign IFUStallF = IFUCacheBusStallD | SelNextSpillF; assign GatedStallD = StallD & ~SelNextSpillF; flopenl #(32) AlignedInstrRawDFlop(clk, reset | FlushD, ~StallD, PostSpillInstrRawF, nop, InstrRawD); diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 807f1ce2b..f0b2d61b4 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -40,7 +40,7 @@ module lsu ( input logic clk, reset, input logic StallM, FlushM, StallW, FlushW, - output logic LSUStallW, + output logic LSUStallM, // connected to cpu (controls) input logic [1:0] MemRWM, input logic [2:0] Funct3M, @@ -120,7 +120,7 @@ module lsu ( flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM); assign IEUAdrExtM = {2'b00, IEUAdrM}; assign IEUAdrExtE = {2'b00, IEUAdrE}; - assign LSUStallW = DCacheStallW | HPTWStall | BusStall; + assign LSUStallM = DCacheStallW | HPTWStall | BusStall; ///////////////////////////////////////////////////////////////////////////////////////////// // HPTW(only needed if VM supported) diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv index d195e95c1..8146ccaf2 100644 --- a/pipelined/src/mmu/hptw.sv +++ b/pipelined/src/mmu/hptw.sv @@ -306,5 +306,5 @@ module hptw ( endmodule // another idea. We keep gating the control by ~FlushW, but this adds considerable length to the critical path. -// should we do this differently? For example TLBMiss is gated by ~FlushW and then drives HPTWStall, which drives LSUStallW, which drives +// should we do this differently? For example TLBMiss is gated by ~FlushW and then drives HPTWStall, which drives LSUStallM, which drives // the hazard unit to issue stall and flush controlls. ~FlushW already suppresses these in the hazard unit. diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index 35e17495d..e54bd04aa 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -41,7 +41,7 @@ module csr #(parameter input logic StallE, StallM, StallW, input logic [31:0] InstrM, input logic [`XLEN-1:0] PCM, SrcAM, IEUAdrM, PCNext2F, - input logic CSRReadM, CSRWriteM, TrapM, mretM, sretM, wfiM, InterruptM, + input logic CSRReadM, CSRWriteM, TrapM, mretM, sretM, wfiM, IntPendingM, InterruptM, input logic MTimerInt, MExtInt, SExtInt, MSwInt, input logic [63:0] MTIME_CLINT, input logic InstrValidM, FRegWriteM, LoadStallD, @@ -185,7 +185,7 @@ module csr #(parameter // CSR Write values /////////////////////////////////////////// assign CSRAdrM = InstrM[31:20]; - assign UnalignedNextEPCM = TrapM ? ((wfiM & InterruptM) ? PCM+4 : PCM) : CSRWriteValM; + assign UnalignedNextEPCM = TrapM ? ((wfiM & IntPendingM) ? PCM+4 : PCM) : CSRWriteValM; assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[`XLEN-1:1], 1'b0} : {UnalignedNextEPCM[`XLEN-1:2], 2'b00}; // 3.1.15 alignment assign NextCauseM = TrapM ? {InterruptM, {(`XLEN-`LOG_XLEN-1){1'b0}}, CauseM}: CSRWriteValM; assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM; diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index ef805a8a9..b8985abb0 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -77,7 +77,7 @@ module privileged ( output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], output logic [2:0] FRM_REGW, - output logic BreakpointFaultM, EcallFaultM, wfiM, IntPendingM, BigEndianM + output logic BreakpointFaultM, EcallFaultM, WFIStallM, BigEndianM ); logic [`LOG_XLEN-1:0] CauseM; @@ -98,6 +98,7 @@ module privileged ( logic [11:0] MIP_REGW, MIE_REGW; logic [1:0] NextPrivilegeModeM; logic DelegateM; + logic wfiM, IntPendingM; /////////////////////////////////////////// // track the current privilege level @@ -123,7 +124,7 @@ module privileged ( .FlushE, .FlushM, .FlushW, .StallE, .StallM, .StallW, .InstrM, .PCM, .SrcAM, .IEUAdrM, .PCNext2F, - .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .InterruptM, + .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .IntPendingM, .InterruptM, .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, @@ -159,8 +160,8 @@ module privileged ( .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MEDELEG_REGW, .STATUS_MIE, .STATUS_SIE, .InstrValidM, .CommittedM, .CommittedF, - .TrapM, .RetM, - .InterruptM, .IntPendingM, .DelegateM, + .TrapM, .RetM, .wfiM, + .InterruptM, .IntPendingM, .DelegateM, .WFIStallM, .CauseM); endmodule diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index ec3cc8634..0a44af2aa 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -42,9 +42,9 @@ module trap ( (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, input logic [`XLEN-1:0] MEDELEG_REGW, input logic STATUS_MIE, STATUS_SIE, - input logic InstrValidM, CommittedM, CommittedF, + input logic InstrValidM, wfiM, CommittedM, CommittedF, output logic TrapM, RetM, - output logic InterruptM, IntPendingM, DelegateM, + output logic InterruptM, IntPendingM, DelegateM, WFIStallM, output logic [`LOG_XLEN-1:0] CauseM ); @@ -71,6 +71,7 @@ module trap ( assign InterruptM = (|ValidIntsM) & InstrValidM; // suppress interrupt if the memory system has partially processed a request. assign DelegateM = `S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM]) & (PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE); + assign WFIStallM = wfiM & ~IntPendingM; /////////////////////////////////////////// // Trigger Traps and RET diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index 22a0321d0..6519f8239 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -110,7 +110,7 @@ module wallypipelinedcore ( logic [1:0] PrivilegeModeW; logic [`XLEN-1:0] PTE; logic [1:0] PageType; - logic sfencevmaM, wfiM, IntPendingM; + logic sfencevmaM, WFIStallM; logic SelHPTW; @@ -119,8 +119,8 @@ module wallypipelinedcore ( var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0]; // IMem stalls - logic IFUStallD; - logic LSUStallW; + logic IFUStallF; + logic LSUStallM; @@ -174,7 +174,7 @@ module wallypipelinedcore ( .FlushD, .FlushE, .FlushM, .FlushW, // Fetch .HRDATA, .PCF, .IFUHADDR, .PCNext2F, - .IFUStallD, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, + .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE, .ICacheAccess, .ICacheMiss, @@ -285,7 +285,7 @@ module wallypipelinedcore ( .InstrDAPageFaultF, .PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW, - .LSUStallW); // change to LSUStallW + .LSUStallM); // change to LSUStallM // *** Ross: please make EBU conditional when only supporting internal memories @@ -319,11 +319,11 @@ module wallypipelinedcore ( hazard hzu( .BPPredWrongE, .CSRWriteFenceM, .RetM, .TrapM, .LoadStallD, .StoreStallD, .MDUStallD, .CSRRdStallD, - .LSUStallW, .IFUStallD, + .LSUStallM, .IFUStallF, .FCvtIntStallD, .FPUStallD, .DivBusyE, .FDivBusyE, .EcallFaultM, .BreakpointFaultM, - .wfiM, .IntPendingM, + .WFIStallM, // Stall & flush outputs .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW @@ -358,14 +358,14 @@ module wallypipelinedcore ( .PrivilegeModeW, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, - .FRM_REGW,.BreakpointFaultM, .EcallFaultM, .wfiM, .IntPendingM, .BigEndianM + .FRM_REGW,.BreakpointFaultM, .EcallFaultM, .WFIStallM, .BigEndianM ); end else begin assign CSRReadValW = 0; assign UnalignedPCNextF = PCNext2F; assign RetM = 0; assign TrapM = 0; - assign wfiM = 0; + assign WFIStallM = 0; assign sfencevmaM = 0; assign BigEndianM = 0; end